From 6981cfa58bf972d209c8515675c51b30cdf37ac8 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 1 Feb 2023 23:08:47 -0800 Subject: [PATCH] add example of writing out simulation netlist --- compiler/tests/05_rom_base_bank_small_test.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/tests/05_rom_base_bank_small_test.py b/compiler/tests/05_rom_base_bank_small_test.py index 85b1ce76..69128d83 100644 --- a/compiler/tests/05_rom_base_bank_small_test.py +++ b/compiler/tests/05_rom_base_bank_small_test.py @@ -26,6 +26,8 @@ class rom_bank_test(openram_test): a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_64B", word_size=1) self.local_check(a) + print('wriitng file') + a.sp_write(OPTS.openram_temp + 'simulation_file.sp') openram.end_openram() # run the test from the command line @@ -33,4 +35,4 @@ if __name__ == "__main__": (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner())