diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index aea4e909..e2f0186a 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -8,7 +8,7 @@
 import debug
 import design
 from sram_factory import factory
-from math import log
+from math import log, ceil
 from tech import drc
 from vector import vector
 from globals import OPTS
diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py
index 328dc630..66827ef5 100755
--- a/compiler/tests/21_ngspice_delay_extra_rows_test.py
+++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py
@@ -33,7 +33,7 @@ class timing_sram_test(openram_test):
         c = sram_config(word_size=1,
                         num_words=16,
                         num_banks=1,
-                        num_spare_rows=5)
+                        num_spare_rows=3)
         c.words_per_row=1
         c.recompute_sizes()
         debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")