diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py
index 91ad0500..e0545af4 100755
--- a/compiler/tests/16_control_logic_test.py
+++ b/compiler/tests/16_control_logic_test.py
@@ -36,17 +36,21 @@ class control_logic_test(openram_test):
         
         # Check port specific control logic
         OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 1
-        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
 
         debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
         a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="rw")
         self.local_check(a)
         
+        OPTS.num_rw_ports = 0
+        OPTS.num_w_ports = 1
         debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
         a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="w")
         self.local_check(a)
         
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 1
         debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
         a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="r")
         self.local_check(a)