diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 4f7e7fd1..c85528a5 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -67,27 +67,24 @@ class bank(design.design): self.DRC_LVS() def add_pins(self): - self.din_list = [] - self.dout_list = [] + self.read_index = [] port_number = 0 for port in range(OPTS.num_rw_ports): - self.din_list.append("din{}".format(port_number)) - self.dout_list.append("dout{}".format(port_number)) + self.read_index.append("{}".format(port_number)) port_number += 1 for port in range(OPTS.num_w_ports): - self.din_list.append("din{}".format(port_number)) port_number += 1 for port in range(OPTS.num_r_ports): - self.dout_list.append("dout{}".format(port_number)) + self.read_index.append("{}".format(port_number)) port_number += 1 """ Adding pins for Bank module""" for port in range(self.total_read): for bit in range(self.word_size): - self.add_pin(self.dout_list[port]+"[{0}]".format(bit),"OUT") + self.add_pin("dout{0}[{1}]".format(self.read_index[port],bit),"OUT") for port in range(self.total_write): for bit in range(self.word_size): - self.add_pin(self.din_list[port]+"[{0}]".format(bit),"IN") + self.add_pin("din{0}[{1}]".format(port,bit),"IN") for port in range(self.total_ports): for bit in range(self.addr_size): self.add_pin("addr{0}[{1}]".format(port,bit),"INPUT") @@ -98,7 +95,7 @@ class bank(design.design): for port in range(self.total_ports): self.add_pin("bank_sel{}".format(port),"INPUT") for port in range(self.total_read): - self.add_pin("s_en{0}".format(port), "INPUT") + self.add_pin("s_en{0}".format(self.read_index[port]), "INPUT") for port in range(self.total_write): self.add_pin("w_en{0}".format(port), "INPUT") for pin in ["clk_buf_bar","clk_buf"]: @@ -364,7 +361,7 @@ class bank(design.design): temp = [] for bit in range(self.word_size): - temp.append(self.dout_list[port]+"[{0}]".format(bit)) + temp.append("dout{0}[{1}]".format(self.read_index[port],bit)) if self.words_per_row == 1: temp.append(self.read_bl_list[port]+"[{0}]".format(bit)) temp.append(self.read_br_list[port]+"[{0}]".format(bit)) @@ -393,7 +390,7 @@ class bank(design.design): temp = [] for bit in range(self.word_size): - temp.append(self.din_list[port]+"[{0}]".format(bit)) + temp.append("din{0}[{1}]".format(port,bit)) for bit in range(self.word_size): if (self.words_per_row == 1): temp.append(self.write_bl_list[port]+"[{0}]".format(bit)) diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 302c34ed..67789b78 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -19,7 +19,6 @@ class sram_base(design): self.sram_config = sram_config sram_config.set_local_config(self) - print("PORTS: {} - {} - {}".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)) self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports @@ -29,29 +28,20 @@ class sram_base(design): def add_pins(self): """ Add pins for entire SRAM. """ - self.din_list = [] - self.DIN_list = [] - self.dout_list = [] - self.DOUT_list = [] + self.read_index = [] port_number = 0 for port in range(OPTS.num_rw_ports): - self.din_list.append("din{}".format(port_number)) - self.dout_list.append("dout{}".format(port_number)) - self.DIN_list.append("DIN{}".format(port_number)) - self.DOUT_list.append("DOUT{}".format(port_number)) + self.read_index.append("{}".format(port_number)) port_number += 1 for port in range(OPTS.num_w_ports): - self.din_list.append("din{}".format(port_number)) - self.DIN_list.append("DIN{}".format(port_number)) port_number += 1 for port in range(OPTS.num_r_ports): - self.dout_list.append("dout{}".format(port_number)) - self.DOUT_list.append("DOUT{}".format(port_number)) + self.read_index.append("{}".format(port_number)) port_number += 1 for port in range(self.total_write): for bit in range(self.word_size): - self.add_pin(self.DIN_list[port]+"[{0}]".format(bit),"INPUT") + self.add_pin("DIN{0}[{1}]".format(port,bit),"INPUT") for port in range(self.total_ports): for bit in range(self.addr_size): @@ -69,7 +59,7 @@ class sram_base(design): for port in range(self.total_read): for bit in range(self.word_size): - self.add_pin(self.DOUT_list[port]+"[{0}]".format(bit),"OUTPUT") + self.add_pin("DOUT{0}[{1}]".format(self.read_index[port],bit),"OUTPUT") self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") @@ -261,8 +251,6 @@ class sram_base(design): self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size*self.total_write) self.add_mod(self.data_dff) - print("PORTS: {} - {} - {}".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)) - # Create the bank module (up to four are instantiated) from bank import bank self.bank = bank(self.sram_config, @@ -288,7 +276,7 @@ class sram_base(design): temp = [] for port in range(self.total_read): for bit in range(self.word_size): - temp.append(self.DOUT_list[port]+"[{0}]".format(bit)) + temp.append("DOUT{0}[{1}]".format(self.read_index[port],bit)) for port in range(self.total_write): for bit in range(self.word_size): temp.append("BANK_DIN{0}[{1}]".format(port,bit)) @@ -299,7 +287,7 @@ class sram_base(design): for port in range(self.total_ports): temp.append("bank_sel{0}[{1}]".format(port,bank_num)) for port in range(self.total_read): - temp.append("s_en{0}".format(port)) + temp.append("s_en{0}".format(self.read_index[port])) for port in range(self.total_write): temp.append("w_en{0}".format(port)) temp.extend(["clk_buf_bar","clk_buf" , "vdd", "gnd"])