diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index 00ca1610..a1eab007 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -62,6 +62,7 @@ class verilog:
         self.vf.write("  // FIXME: This delay is arbitrary.\n")
         self.vf.write("  parameter DELAY = 3 ;\n")
         self.vf.write("  parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n")
+        self.vf.write("  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n")
         self.vf.write("\n")
 
         for port in self.all_ports:
@@ -129,7 +130,7 @@ class verilog:
         if port in self.write_ports:
             self.vf.write("    din{0}_reg = din{0};\n".format(port))
         if port in self.read_ports:
-            self.vf.write("    dout{0} = {1}'bx;\n".format(port, self.word_size))
+            self.vf.write("    #(T_HOLD) dout{0} = {1}'bx;\n".format(port, self.word_size))
         if port in self.readwrite_ports:
             self.vf.write("    if ( !csb{0}_reg && web{0}_reg && VERBOSE ) \n".format(port))
             self.vf.write("      $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))