diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index 75f50f9f..1dc052e3 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -95,7 +95,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
 
         if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
             global total_drc_errors
-            tempgds = OPTS.openram_temp + "/temp.gds"
+            tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
             self.gds_write(tempgds)
             num_errors = verify.run_drc(self.name, tempgds, final_verification)  
             total_drc_errors += num_errors
@@ -110,8 +110,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
 
         if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
             global total_lvs_errors
-            tempspice = OPTS.openram_temp + "/temp.sp"
-            tempgds = OPTS.openram_temp + "/temp.gds"
+            tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name)
+            tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
             self.sp_write(tempspice)
             self.gds_write(tempgds)
             num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification)
diff --git a/compiler/bitcells/bitcell_1w_1r.py b/compiler/bitcells/bitcell_1w_1r.py
new file mode 100644
index 00000000..4df9e813
--- /dev/null
+++ b/compiler/bitcells/bitcell_1w_1r.py
@@ -0,0 +1,106 @@
+import design
+import debug
+import utils
+from tech import GDS,layer,parameter,drc
+
+class bitcell_1w_1r(design.design):
+    """
+    A single bit cell (6T, 8T, etc.)  This module implements the
+    single memory cell used in the design. It is a hand-made cell, so
+    the layout and netlist should be available in the technology
+    library.
+    """
+
+    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    (width,height) = utils.get_libcell_size("cell_1w_1r", GDS["unit"], layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names, "cell_1w_1r", GDS["unit"])
+
+    def __init__(self, name=""):
+        # Ignore the name argument
+        design.design.__init__(self, "cell_1w_1r")
+        debug.info(2, "Create bitcell with 1W and 1R Port")
+
+        self.width = bitcell_1w_1r.width
+        self.height = bitcell_1w_1r.height
+        self.pin_map = bitcell_1w_1r.pin_map
+
+    def analytical_delay(self, slew, load=0, swing = 0.5):
+        # delay of bit cell is not like a driver(from WL)
+        # so the slew used should be 0
+        # it should not be slew dependent?
+        # because the value is there
+        # the delay is only over half transsmission gate
+        from tech import spice
+        r = spice["min_tx_r"]*3
+        c_para = spice["min_tx_drain_c"]
+        result = self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew, swing = swing)
+        return result
+   
+ 
+    def list_bitcell_pins(self, col, row):
+        """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
+        bitcell_pins = ["bl0_{0}".format(col),
+                        "br0_{0}".format(col),
+                        "bl1_{0}".format(col),
+                        "br1_{0}".format(col),
+                        "wl0_{0}".format(row),
+                        "wl1_{0}".format(row),
+                        "vdd",
+                        "gnd"]
+        return bitcell_pins
+    
+    def list_all_wl_names(self):
+        """ Creates a list of all wordline pin names """
+        row_pins = ["wl0", "wl1"]    
+        return row_pins
+    
+    def list_all_bitline_names(self):
+        """ Creates a list of all bitline pin names (both bl and br) """
+        column_pins = ["bl0", "br0", "bl1", "br1"]
+        return column_pins
+    
+    def list_all_bl_names(self):
+        """ Creates a list of all bl pins names """
+        column_pins = ["bl0", "bl1"]
+        return column_pins
+        
+    def list_all_br_names(self):
+        """ Creates a list of all br pins names """
+        column_pins = ["br0", "br1"]
+        return column_pins
+        
+    def list_read_bl_names(self):
+        """ Creates a list of bl pin names associated with read ports """
+        column_pins = ["bl0", "bl1"]
+        return column_pins
+    
+    def list_read_br_names(self):
+        """ Creates a list of br pin names associated with read ports """
+        column_pins = ["br0", "br1"]
+        return column_pins
+        
+    def list_write_bl_names(self):
+        """ Creates a list of bl pin names associated with write ports """
+        column_pins = ["bl0"]
+        return column_pins
+    
+    def list_write_br_names(self):
+        """ Creates a list of br pin names asscociated with write ports"""
+        column_pins = ["br0"]
+        return column_pins
+    
+    def analytical_power(self, proc, vdd, temp, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 #temporary
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+
+    def get_wl_cin(self):
+        """Return the relative capacitance of the access transistor gates"""
+        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
+        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
+        #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
+        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
+        return 2*access_tx_cin
diff --git a/compiler/bitcells/replica_bitcell_1w_1r.py b/compiler/bitcells/replica_bitcell_1w_1r.py
new file mode 100644
index 00000000..6f59adec
--- /dev/null
+++ b/compiler/bitcells/replica_bitcell_1w_1r.py
@@ -0,0 +1,32 @@
+import design
+import debug
+import utils
+from tech import GDS,layer,drc,parameter
+
+class replica_bitcell_1w_1r(design.design):
+    """
+    A single bit cell which is forced to store a 0.
+    This module implements the single memory cell used in the design. It
+    is a hand-made cell, so the layout and netlist should be available in
+    the technology library. """
+
+    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    (width,height) = utils.get_libcell_size("replica_cell_1w_1r", GDS["unit"], layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1w_1r", GDS["unit"])
+
+    def __init__(self, name=""):
+        # Ignore the name argument        
+        design.design.__init__(self, "replica_cell_1w_1r")
+        debug.info(2, "Create replica bitcell 1w+1r object")
+
+        self.width = replica_bitcell_1w_1r.width
+        self.height = replica_bitcell_1w_1r.height
+        self.pin_map = replica_bitcell_1w_1r.pin_map
+
+    def get_wl_cin(self):
+        """Return the relative capacitance of the access transistor gates"""
+        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
+        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
+        #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
+        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
+        return 2*access_tx_cin
diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py
new file mode 100644
index 00000000..c01b67b7
--- /dev/null
+++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py
@@ -0,0 +1,20 @@
+word_size = 2
+num_words = 16
+
+bitcell = "bitcell_1w_1r"
+replica_bitcell = "replica_bitcell_1w_1r"
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+output_path = "temp"
+output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
new file mode 100755
index 00000000..2954ffbc
--- /dev/null
+++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
@@ -0,0 +1,51 @@
+#!/usr/bin/env python3
+"""
+Run a regression test on a 1 bank SRAM
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
+class psram_1bank_2mux_1w_1r_test(openram_test):
+
+    def runTest(self):        
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        from sram import sram
+        from sram_config import sram_config
+        OPTS.bitcell = "bitcell_1w_1r"
+        OPTS.replica_bitcell="replica_bitcell_1w_1r"
+        
+        OPTS.num_rw_ports = 0
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+        
+        c = sram_config(word_size=4,
+                        num_words=32,
+                        num_banks=1)
+        c.num_words=32
+        c.words_per_row=2
+        c.recompute_sizes()
+        debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
+                                                                                                                          OPTS.num_r_ports,
+                                                                                                                          OPTS.num_w_ports,
+                                                                                                                          c.word_size,
+                                                                                                                          c.num_words,
+                                                                                                                          c.words_per_row,
+                                                                                                                          c.num_banks))
+        a = sram(c, "sram")
+        self.local_check(a, final_verification=True)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()
diff --git a/compiler/verify/assura.py b/compiler/verify/assura.py
index d3c605f3..af034730 100644
--- a/compiler/verify/assura.py
+++ b/compiler/verify/assura.py
@@ -30,7 +30,7 @@ num_drc_runs = 0
 num_lvs_runs = 0
 num_pex_runs = 0
 
-def run_drc(name, gds_name):
+def run_drc(name, gds_name, final_verification=False):
     """Run DRC check on a given top-level name which is
        implemented in gds_name."""
 
@@ -93,7 +93,7 @@ def run_drc(name, gds_name):
     return errors
 
 
-def run_lvs(name, gds_name, sp_name):
+def run_lvs(name, gds_name, sp_name, final_verification=False):
     """Run LVS check on a given top-level name which is
        implemented in gds_name and sp_name. """
 
@@ -178,7 +178,7 @@ def run_lvs(name, gds_name, sp_name):
     return errors
 
 
-def run_pex(name, gds_name, sp_name, output=None):
+def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
     """Run pex on a given top-level name which is
        implemented in gds_name and sp_name. """
     debug.error("PEX extraction not implemented with Assura.",-1)
diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py
index 2de76386..5f8d2c73 100644
--- a/compiler/verify/calibre.py
+++ b/compiler/verify/calibre.py
@@ -282,7 +282,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
     return total_errors
 
 
-def run_pex(cell_name, gds_name, sp_name, output=None):
+def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False):
     """Run pex on a given top-level name which is
        implemented in gds_name and sp_name. """
 
diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py
index 5b4e8e3f..7db9a5c2 100644
--- a/compiler/verify/magic.py
+++ b/compiler/verify/magic.py
@@ -45,7 +45,7 @@ def write_magic_script(cell_name, gds_name, extract=False, final_verification=Fa
     #f.write("load {}_new\n".format(cell_name))
     #f.write("cellname rename {0}_new {0}\n".format(cell_name))
     #f.write("load {}\n".format(cell_name))
-    f.write("cellname delete \(UNNAMED\)\n")
+    f.write("cellname delete \\(UNNAMED\\)\n")
     f.write("writeall force\n")
     f.write("select top cell\n")
     f.write("expand\n")
@@ -58,9 +58,8 @@ def write_magic_script(cell_name, gds_name, extract=False, final_verification=Fa
     else:
         pre = ""
     if final_verification:
-        f.write(pre+"extract unique\n".format(cell_name))
-    else:
-        f.write(pre+"extract\n".format(cell_name))
+        f.write(pre+"extract unique all\n".format(cell_name))
+    f.write(pre+"extract\n".format(cell_name))
     #f.write(pre+"ext2spice hierarchy on\n")        
     #f.write(pre+"ext2spice scale off\n")
     # lvs exists in 8.2.79, but be backword compatible for now
@@ -260,7 +259,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
     return total_errors
 
 
-def run_pex(name, gds_name, sp_name, output=None):
+def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
     """Run pex on a given top-level name which is
        implemented in gds_name and sp_name. """
 
diff --git a/compiler/verify/none.py b/compiler/verify/none.py
index 531a394d..c69ed93b 100644
--- a/compiler/verify/none.py
+++ b/compiler/verify/none.py
@@ -9,7 +9,7 @@ drc_warned = False
 lvs_warned = False
 pex_warned = False
 
-def run_drc(cell_name, gds_name, extract=False):
+def run_drc(cell_name, gds_name, extract=False, final_verification=False):
     global drc_warned
     if not drc_warned:
         debug.warning("DRC unable to run.")
@@ -25,7 +25,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
     # Since we warned, return a failing test.
     return 1
 
-def run_pex(name, gds_name, sp_name, output=None):
+def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
     global pex_warned    
     if not pex_warned:
         debug.warning("PEX unable to run.")
diff --git a/technology/freepdk45/gds_lib/cell_1w_1r.gds b/technology/freepdk45/gds_lib/cell_1w_1r.gds
new file mode 100644
index 00000000..67498962
Binary files /dev/null and b/technology/freepdk45/gds_lib/cell_1w_1r.gds differ
diff --git a/technology/freepdk45/gds_lib/replica_cell_1w_1r.gds b/technology/freepdk45/gds_lib/replica_cell_1w_1r.gds
new file mode 100644
index 00000000..31deb82b
Binary files /dev/null and b/technology/freepdk45/gds_lib/replica_cell_1w_1r.gds differ
diff --git a/technology/freepdk45/sp_lib/cell_1w_1r.sp b/technology/freepdk45/sp_lib/cell_1w_1r.sp
new file mode 100644
index 00000000..eb3803b4
--- /dev/null
+++ b/technology/freepdk45/sp_lib/cell_1w_1r.sp
@@ -0,0 +1,14 @@
+
+.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
+MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
+MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
+MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
+MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
+MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
+MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
+MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
+MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
+MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
+.ENDS
+
diff --git a/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp b/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp
new file mode 100644
index 00000000..fd06db8c
--- /dev/null
+++ b/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp
@@ -0,0 +1,14 @@
+
+.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
+MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
+MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
+MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
+MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
+MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
+MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1
+MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
+MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
+MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
+.ENDS
+
diff --git a/technology/scn4m_subm/gds_lib/cell_1w_1r.gds b/technology/scn4m_subm/gds_lib/cell_1w_1r.gds
new file mode 100644
index 00000000..782c43dc
Binary files /dev/null and b/technology/scn4m_subm/gds_lib/cell_1w_1r.gds differ
diff --git a/technology/scn4m_subm/gds_lib/replica_cell_1w_1r.gds b/technology/scn4m_subm/gds_lib/replica_cell_1w_1r.gds
new file mode 100644
index 00000000..ce6e413b
Binary files /dev/null and b/technology/scn4m_subm/gds_lib/replica_cell_1w_1r.gds differ
diff --git a/technology/scn4m_subm/mag_lib/cell_6t.ext b/technology/scn4m_subm/mag_lib/cell_6t.ext
new file mode 100644
index 00000000..79f3c8b4
--- /dev/null
+++ b/technology/scn4m_subm/mag_lib/cell_6t.ext
@@ -0,0 +1,41 @@
+timestamp 1536091415
+version 8.2
+tech scmos
+style TSMC0.35um(tsmc35)from:t11c
+scale 1000 1 5
+resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
+node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "br" 6 -1.43219e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
+node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
+node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
+node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
+node "a_28_32#" 160 -8.06466e-13 28 32 p 960 144 304 72 0 0 0 0 0 0 2000 456 0 0 1920 272 0 0 0 0 0 0
+node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
+equiv "gnd" "gnd"
+node "vdd" 2340 2596 -32 116 nw 256 64 800 176 17600 576 0 0 0 0 0 0 0 0 3456 464 256 64 0 0 0 0
+cap "wl" "bl" 189.768
+cap "a_36_40#" "br" 17.59
+cap "wl" "br" 189.768
+cap "vdd" "bl" 135.015
+cap "bl" "br" 27.492
+cap "vdd" "br" 117.084
+cap "gnd" "a_28_32#" 880.405
+cap "gnd" "a_36_40#" 401.284
+cap "a_28_32#" "a_36_40#" 272.793
+cap "gnd" "wl" 1198.41
+cap "gnd" "bl" 712.11
+cap "a_28_32#" "wl" 108.364
+cap "vdd" "gnd" 510.12
+cap "gnd" "br" 698.471
+cap "a_36_40#" "wl" 108.364
+cap "a_28_32#" "bl" 104.205
+cap "vdd" "a_28_32#" 430.812
+cap "a_36_40#" "bl" 29.396
+cap "a_28_32#" "br" 308.488
+cap "vdd" "a_36_40#" 709.108
+fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "a_28_32#" 16 0
+fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
+fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "a_28_32#" 32 0 "gnd" 32 0
+fet nfet 28 40 29 41 256 80 "gnd" "a_28_32#" 16 0 "gnd" 32 0 "a_36_40#" 32 0
+fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "a_28_32#" 12 0 "vdd" 12 0
+fet pfet 28 148 29 149 192 56 "vdd" "a_28_32#" 32 0 "vdd" 12 0 "a_36_40#" 12 0
diff --git a/technology/scn4m_subm/mag_lib/cell_6t.spice b/technology/scn4m_subm/mag_lib/cell_6t.spice
new file mode 100644
index 00000000..31eec08a
--- /dev/null
+++ b/technology/scn4m_subm/mag_lib/cell_6t.spice
@@ -0,0 +1,15 @@
+* SPICE3 file created from cell_6t.ext - technology: scmos
+
+M1000 a_36_40# a_28_32# vdd vdd pfet w=0.6u l=0.8u
++  ad=0.76p pd=3.6u as=2p ps=8.8u
+M1001 vdd a_36_40# a_28_32# vdd pfet w=0.6u l=0.8u
++  ad=0p pd=0u as=0.76p ps=3.6u
+M1002 a_36_40# a_28_32# gnd gnd nfet w=1.6u l=0.4u
++  ad=2.4p pd=7.2u as=4.48p ps=12u
+M1003 gnd a_36_40# a_28_32# gnd nfet w=1.6u l=0.4u
++  ad=0p pd=0u as=2.4p ps=7.2u
+M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
++  ad=0p pd=0u as=0.8p ps=3.6u
+M1005 a_28_32# wl br gnd nfet w=0.8u l=0.4u
++  ad=0p pd=0u as=0.8p ps=3.6u
+C0 vdd 0 2.60fF
diff --git a/technology/scn4m_subm/mag_lib/replica_cell_6t.ext b/technology/scn4m_subm/mag_lib/replica_cell_6t.ext
new file mode 100644
index 00000000..726cd738
--- /dev/null
+++ b/technology/scn4m_subm/mag_lib/replica_cell_6t.ext
@@ -0,0 +1,35 @@
+timestamp 1541443051
+version 8.2
+tech scmos
+style TSMC0.35um(tsmc35)from:t11c
+scale 1000 1 5
+resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
+node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "br" 6 1.40998e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
+node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
+node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
+node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
+node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
+equiv "gnd" "gnd"
+node "vdd" 2517 2596 -32 116 nw 1216 208 1104 248 17600 576 0 0 0 0 2000 456 0 0 5632 736 256 64 0 0 0 0
+cap "vdd" "br" 442.06
+cap "bl" "wl" 189.768
+cap "gnd" "br" 698.471
+cap "bl" "a_36_40#" 29.396
+cap "wl" "a_36_40#" 108.364
+cap "bl" "vdd" 239.22
+cap "bl" "gnd" 712.11
+cap "wl" "vdd" 108.364
+cap "wl" "gnd" 1198.41
+cap "bl" "br" 27.492
+cap "a_36_40#" "vdd" 981.901
+cap "wl" "br" 189.768
+cap "a_36_40#" "gnd" 401.284
+cap "vdd" "gnd" 1390.52
+cap "a_36_40#" "br" 17.59
+fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "vdd" 16 0
+fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
+fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "vdd" 32 0 "gnd" 32 0
+fet nfet 28 40 29 41 256 80 "gnd" "vdd" 16 0 "gnd" 32 0 "a_36_40#" 32 0
+fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "vdd" 24 0
+fet pfet 28 148 29 149 192 56 "vdd" "vdd" 32 0 "vdd" 12 0 "a_36_40#" 12 0
diff --git a/technology/scn4m_subm/mag_lib/replica_cell_6t.spice b/technology/scn4m_subm/mag_lib/replica_cell_6t.spice
new file mode 100644
index 00000000..bb64476f
--- /dev/null
+++ b/technology/scn4m_subm/mag_lib/replica_cell_6t.spice
@@ -0,0 +1,16 @@
+* SPICE3 file created from replica_cell_6t.ext - technology: scmos
+
+M1000 a_36_40# vdd vdd vdd pfet w=0.6u l=0.8u
++  ad=0.76p pd=3.6u as=2.76p ps=12.4u
+** SOURCE/DRAIN TIED
+M1001 vdd a_36_40# vdd vdd pfet w=0.8u l=0.6u
++  ad=0p pd=0u as=0p ps=0u
+M1002 a_36_40# vdd gnd gnd nfet w=1.6u l=0.4u
++  ad=2.4p pd=7.2u as=4.48p ps=12u
+M1003 gnd a_36_40# vdd gnd nfet w=1.6u l=0.4u
++  ad=0p pd=0u as=3.04p ps=10.4u
+M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
++  ad=0p pd=0u as=0.8p ps=3.6u
+M1005 vdd wl br gnd nfet w=0.8u l=0.4u
++  ad=0p pd=0u as=0.8p ps=3.6u
+C0 vdd 0 2.60fF
diff --git a/technology/scn4m_subm/sp_lib/cell_1w_1r.sp b/technology/scn4m_subm/sp_lib/cell_1w_1r.sp
new file mode 100644
index 00000000..b40f589a
--- /dev/null
+++ b/technology/scn4m_subm/sp_lib/cell_1w_1r.sp
@@ -0,0 +1,14 @@
+
+.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
+MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
+MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u
+MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
+MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
+MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u
+MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u
+MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u
+MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u
+MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u
+.ENDS
+
diff --git a/technology/scn4m_subm/sp_lib/cell_6t.st0 b/technology/scn4m_subm/sp_lib/cell_6t.st0
new file mode 100644
index 00000000..52729df3
--- /dev/null
+++ b/technology/scn4m_subm/sp_lib/cell_6t.st0
@@ -0,0 +1,38 @@
+****** HSPICE -- M-2017.03 linux64 (Feb 20 2017) ******
+ Input File: cell_6t.sp
+ lic:
+ lic: FLEXlm: SDK_11.6.4
+ lic: USER:   mrg                  HOSTNAME: 72fb17cef281
+ lic: HOSTID: 0242ac110002         PID:      69
+ lic: Using FLEXlm license file:
+ lic: 27000@license.soe.ucsc.edu
+ lic: Checkout 1 hspice
+ lic: License/Maintenance for hspice will expire on 18-dec-2020/2018.09
+ lic: 1(in_use)/50(total) FLOATING license(s) on SERVER 27000@license.soe.ucsc.edu
+ lic:
+ init: begin read circuit files,  cpu clock=  9.60E-01
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/a
+                         d
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/b
+                         ehave
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/c
+                         omlinear
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/d
+                         io
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/f
+                         et
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/l
+                         in_tech
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/p
+                         ci
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/s
+                         ignet
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/t
+                         i
+       option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/x
+                         ilinx
+       option runlvl
+ init: end read circuit files,  cpu clock=  9.60E-01 peak memory=       290 mb
+ init: begin check errors,  cpu clock=  9.60E-01
+>error          ***** hspice job aborted
+ lic: Release hspice token(s)
diff --git a/technology/scn4m_subm/sp_lib/replica_cell_1w_1r.sp b/technology/scn4m_subm/sp_lib/replica_cell_1w_1r.sp
new file mode 100644
index 00000000..6c2d3c1b
--- /dev/null
+++ b/technology/scn4m_subm/sp_lib/replica_cell_1w_1r.sp
@@ -0,0 +1,14 @@
+
+.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
+MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
+MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u
+MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
+MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
+MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u
+MM1 Q vdd gnd gnd n w=1.6u l=0.4u
+MM0 vdd Q gnd gnd n w=1.6u l=0.4u
+MM3 Q vdd vdd vdd p w=0.6u l=0.4u
+MM2 vdd Q vdd vdd p w=0.6u l=0.4u
+.ENDS
+