From add0e3ad68d7d64c9e9135d800278dca60cf8b08 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Tue, 11 Sep 2018 10:17:24 -0700
Subject: [PATCH 1/4] Add none option for verify wrapper with warning messages.

---
 compiler/verify/__init__.py |  6 +++---
 compiler/verify/none.py     | 41 +++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+), 3 deletions(-)
 create mode 100644 compiler/verify/none.py

diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py
index 91c52a90..1f0ffaab 100644
--- a/compiler/verify/__init__.py
+++ b/compiler/verify/__init__.py
@@ -30,7 +30,7 @@ if OPTS.check_lvsdrc and OPTS.tech_name == "freepdk45":
     debug.check(OPTS.drc_exe[0]!="magic","Magic does not support FreePDK45 for DRC.")
     
 if OPTS.drc_exe == None:
-    pass
+    from .none import run_drc,print_drc_stats
 elif "calibre"==OPTS.drc_exe[0]:
     from .calibre import run_drc,print_drc_stats
 elif "assura"==OPTS.drc_exe[0]:
@@ -41,7 +41,7 @@ else:
     debug.warning("Did not find a supported DRC tool.")
 
 if OPTS.lvs_exe == None:
-    pass
+    from .none import run_lvs,print_lvs_stats
 elif "calibre"==OPTS.lvs_exe[0]:
     from .calibre import run_lvs,print_lvs_stats
 elif "assura"==OPTS.lvs_exe[0]:
@@ -53,7 +53,7 @@ else:
 
 
 if OPTS.pex_exe == None:
-    pass
+    from .none import run_pex,print_pex_stats
 elif "calibre"==OPTS.pex_exe[0]:
     from .calibre import run_pex,print_pex_stats
 elif "magic"==OPTS.pex_exe[0]:
diff --git a/compiler/verify/none.py b/compiler/verify/none.py
new file mode 100644
index 00000000..531a394d
--- /dev/null
+++ b/compiler/verify/none.py
@@ -0,0 +1,41 @@
+"""
+This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools.
+
+"""
+import debug
+
+# Only print the warning once.
+drc_warned = False
+lvs_warned = False
+pex_warned = False
+
+def run_drc(cell_name, gds_name, extract=False):
+    global drc_warned
+    if not drc_warned:
+        debug.warning("DRC unable to run.")
+        drc_warned=True
+    # Since we warned, return a failing test.        
+    return 1
+    
+def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
+    global lvs_warned
+    if not lvs_warned:
+        debug.warning("LVS unable to run.")
+        lvs_warned=True
+    # Since we warned, return a failing test.
+    return 1
+
+def run_pex(name, gds_name, sp_name, output=None):
+    global pex_warned    
+    if not pex_warned:
+        debug.warning("PEX unable to run.")
+        pex_warned=True
+    # Since we warned, return a failing test.        
+    return 1
+
+def print_drc_stats():
+    pass
+def print_lvs_stats():
+    pass
+def print_pex_stats():
+    pass

From fcc4a75295f77ceb5468cb2a6f5574e479e48a55 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Tue, 11 Sep 2018 13:28:28 -0700
Subject: [PATCH 2/4] Create VCG using nets as nodes rather than pins.

---
 compiler/base/hierarchy_layout.py    | 98 ++++++++++++++++++++--------
 compiler/tests/20_sram_1bank_test.py |  4 +-
 2 files changed, 72 insertions(+), 30 deletions(-)

diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 3ac5ea63..331e1195 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -602,6 +602,7 @@ class layout(lef.lef):
         """ 
         Connect a mapping of pin -> name for a bus. This could be
         replaced with a channel router in the future. 
+        NOTE: This has only really been tested with point-to-point connections (not multiple pins on a net).
         """
         (horizontal_layer, via_layer, vertical_layer)=layer_stack
         if horizontal:
@@ -720,6 +721,7 @@ class layout(lef.lef):
         try to minimize the number of tracks -- instead, it picks an order to avoid the vertical
         conflicts between pins.
         """
+        local_debug = True
 
         def remove_net_from_graph(pin, g):
             # Remove the pin from the keys
@@ -732,6 +734,29 @@ class layout(lef.lef):
                     g[other_pin]=conflicts
             return g
 
+        def vcg_pins_overlap(pins1, pins2, vertical):
+            # Check all the pin pairs on two nets and return a pin
+            # overlap if any pin overlaps vertically
+            for pin1 in pins1:
+                for pin2 in pins2:
+                    if vcg_pin_overlap(pin1, pin2, vertical):
+                        return True
+
+            return False
+                            
+        def vcg_pin_overlap(pin1, pin2, vertical):
+            # Check for vertical overlap of the two pins
+
+            # Pin 1 must be in the "LEFT" set and overlap the right
+            x_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().x-pin2.center().x)<pitch
+
+            # Pin 1 must be in the "TOP" set and overlap the bottom
+            y_overlap = pin1.by() > pin2.by() and abs(pin1.center().y-pin2.center().y)<pitch
+            
+            return (not vertical and x_overlap) or (vertical and y_overlap)
+
+
+
         if not pitch:
             pitch = self.m2_pitch
 
@@ -744,22 +769,38 @@ class layout(lef.lef):
         
         # Initialize the vertical conflict graph (vcg) and make a list of all pins
         vcg = {}
-        
+
+        # Create names for the nets for the graphs
+        nets = {}
+        index = 0
+        print(route_map)
+        for pin_connections in route_map:
+                net_name = "n{}".format(index)
+                print("N",net_name)
+                index += 1
+                nets[net_name] = []
+                for pin_name in pin_connections:
+                    pin = all_pins[pin_name]
+                    nets[net_name].append(pin)
+        if local_debug:
+            import pprint
+            pprint.pprint(nets)
+
         # Find the vertical pin conflicts
         # FIXME: O(n^2) but who cares for now
-        for top_name,top_pin in top_pins.items():
-            vcg[top_name]=[]    
-            for bot_name,bot_pin in bottom_pins.items():
-                # Remember, vertical is the boolean of the routes in the channel
-                # so check the intervals of the pins in the other dimension
-                x_overlap = abs(top_pin.center().x-bot_pin.center().x)<pitch
-                y_overlap = abs(top_pin.center().y-bot_pin.center().y)<pitch
-                             
-                if (vertical and y_overlap) or (not vertical and x_overlap):
+        for net_name1 in nets:
+            print("NET1:",net_name1)
+            vcg[net_name1]=[]
+            for net_name2 in nets:
+                print("NET2:",net_name2)
+                # Skip yourself
+                if net_name1 == net_name2:
+                    continue
+                if vcg_pins_overlap(nets[net_name1], nets[net_name2], vertical):
                     try:
-                        vcg[bot_name].append(top_name)
+                        vcg[net_name1].append(net_name2)
                     except:
-                        vcg[bot_name] = [top_name]
+                        vcg[net_name1] = [net_name2]
                     
         #FIXME: What if we have a cycle? 
 
@@ -773,27 +814,28 @@ class layout(lef.lef):
 
         # list of routes to do
         while vcg:
-            #print(vcg)
+            if local_debug:
+                from pprint import pformat
+                print("VCG:\n",pformat(vcg))
             # get a route from conflict graph with empty fanout set
-            route_pin=None
-            for route_pin,conflicts in vcg.items():
+            net_name=None
+            for net_name,conflicts in vcg.items():
                 if len(conflicts)==0:
-                    vcg=remove_net_from_graph(route_pin,vcg)
+                    vcg=remove_net_from_graph(net_name,vcg)
                     break
+            else:
+                # FIXME: We don't support cyclic VCGs right now.
+                debug.error("Cyclic VCG in channel router.",-1)
+                    
+            if local_debug:
+                print("Routing:",net_name,pin_connections)
 
-            # Get the connected pins from the routing map
-            for pin_connections in route_map:
-                if route_pin in pin_connections:
-                    break
-            #print("Routing:",route_pin,pin_connections)
+            # These are the pins we'll have to connect
+            pin_list = nets[net_name]
+
+            # Remove the net from other constriants in the VCG
+            vcg=remove_net_from_graph(net_name, vcg)
             
-            # Remove the other pins from the conflict graph too
-            for other_pin in pin_connections:
-                vcg=remove_net_from_graph(other_pin, vcg)
-                
-            # Create a list of the pins rather than a list of the names
-            pin_list = [all_pins[pin_name] for pin_name in pin_connections]
-
             # Add the trunk route and move up to next track
             if vertical:
                 self.add_vertical_trunk_route(pin_list, offset, layer_stack, pitch)
diff --git a/compiler/tests/20_sram_1bank_test.py b/compiler/tests/20_sram_1bank_test.py
index ce482b6d..01a1fe4b 100755
--- a/compiler/tests/20_sram_1bank_test.py
+++ b/compiler/tests/20_sram_1bank_test.py
@@ -23,8 +23,8 @@ class sram_1bank_test(openram_test):
         
         c.words_per_row=1
         debug.info(1, "Single bank, no column mux with control logic")
-        a = sram(c, "sram1")
-        self.local_check(a, final_verification=True)
+        #a = sram(c, "sram1")
+        #self.local_check(a, final_verification=True)
 
         c.num_words=32
         c.words_per_row=2

From 5e34233479ef7facbd83d18933353421ce7e60a8 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Tue, 11 Sep 2018 13:43:47 -0700
Subject: [PATCH 3/4] Finish new VCG testing.

Reversed VCG graph edge directions.
Channel tracks get added left to right or top down like
normal left edge algorithm examples.
---
 compiler/base/hierarchy_layout.py    | 52 +++++++++++-----------------
 compiler/tests/20_sram_1bank_test.py |  4 +--
 2 files changed, 23 insertions(+), 33 deletions(-)

diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 331e1195..191fa492 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -721,8 +721,6 @@ class layout(lef.lef):
         try to minimize the number of tracks -- instead, it picks an order to avoid the vertical
         conflicts between pins.
         """
-        local_debug = True
-
         def remove_net_from_graph(pin, g):
             # Remove the pin from the keys
             g.pop(pin,None)
@@ -747,11 +745,11 @@ class layout(lef.lef):
         def vcg_pin_overlap(pin1, pin2, vertical):
             # Check for vertical overlap of the two pins
 
-            # Pin 1 must be in the "LEFT" set and overlap the right
-            x_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().x-pin2.center().x)<pitch
+            # Pin 1 must be in the "TOP" set
+            x_overlap = pin1.by() > pin2.by() and abs(pin1.center().x-pin2.center().x)<pitch
 
-            # Pin 1 must be in the "TOP" set and overlap the bottom
-            y_overlap = pin1.by() > pin2.by() and abs(pin1.center().y-pin2.center().y)<pitch
+            # Pin 1 must be in the "LET" set
+            y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y-pin2.center().y)<pitch
             
             return (not vertical and x_overlap) or (vertical and y_overlap)
 
@@ -773,50 +771,42 @@ class layout(lef.lef):
         # Create names for the nets for the graphs
         nets = {}
         index = 0
-        print(route_map)
+        #print(route_map)
         for pin_connections in route_map:
                 net_name = "n{}".format(index)
-                print("N",net_name)
                 index += 1
                 nets[net_name] = []
                 for pin_name in pin_connections:
                     pin = all_pins[pin_name]
                     nets[net_name].append(pin)
-        if local_debug:
-            import pprint
-            pprint.pprint(nets)
 
         # Find the vertical pin conflicts
         # FIXME: O(n^2) but who cares for now
         for net_name1 in nets:
-            print("NET1:",net_name1)
             vcg[net_name1]=[]
             for net_name2 in nets:
-                print("NET2:",net_name2)
                 # Skip yourself
                 if net_name1 == net_name2:
                     continue
                 if vcg_pins_overlap(nets[net_name1], nets[net_name2], vertical):
                     try:
-                        vcg[net_name1].append(net_name2)
+                        vcg[net_name2].append(net_name1)
                     except:
-                        vcg[net_name1] = [net_name2]
+                        vcg[net_name2] = [net_name1]
                     
         #FIXME: What if we have a cycle? 
 
-        # This is the starting offset of the first trunk
-        if vertical:
-            half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[2])]        
-            offset = offset + vector(half_minwidth,0)
-        else:
-            half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[0])]        
-            offset = offset + vector(0,half_minwidth)
+        # The starting offset is the first trunk at the top or left
+        # so we must offset from the lower left of the channel placement
+        # in the case of vertical tracks
+        if not vertical:
+            # This will start from top down
+            offset = offset + vector(0,len(nets)*pitch)
 
         # list of routes to do
         while vcg:
-            if local_debug:
-                from pprint import pformat
-                print("VCG:\n",pformat(vcg))
+            #from pprint import pformat
+            #print("VCG:\n",pformat(vcg))
             # get a route from conflict graph with empty fanout set
             net_name=None
             for net_name,conflicts in vcg.items():
@@ -826,23 +816,23 @@ class layout(lef.lef):
             else:
                 # FIXME: We don't support cyclic VCGs right now.
                 debug.error("Cyclic VCG in channel router.",-1)
-                    
-            if local_debug:
-                print("Routing:",net_name,pin_connections)
+
+                
 
             # These are the pins we'll have to connect
             pin_list = nets[net_name]
+            #print("Routing:",net_name,[x.name for x in pin_list])
 
             # Remove the net from other constriants in the VCG
             vcg=remove_net_from_graph(net_name, vcg)
             
-            # Add the trunk route and move up to next track
+            # Add the trunk routes from the bottom up or right to left
             if vertical:
                 self.add_vertical_trunk_route(pin_list, offset, layer_stack, pitch)
-                offset += vector(pitch,0)
+                offset -= vector(pitch,0)
             else:
                 self.add_horizontal_trunk_route(pin_list, offset, layer_stack, pitch)
-                offset += vector(0,pitch)
+                offset -= vector(0,pitch)
 
 
     def create_vertical_channel_route(self, route_map, left_inst, right_inst, offset, 
diff --git a/compiler/tests/20_sram_1bank_test.py b/compiler/tests/20_sram_1bank_test.py
index 01a1fe4b..ce482b6d 100755
--- a/compiler/tests/20_sram_1bank_test.py
+++ b/compiler/tests/20_sram_1bank_test.py
@@ -23,8 +23,8 @@ class sram_1bank_test(openram_test):
         
         c.words_per_row=1
         debug.info(1, "Single bank, no column mux with control logic")
-        #a = sram(c, "sram1")
-        #self.local_check(a, final_verification=True)
+        a = sram(c, "sram1")
+        self.local_check(a, final_verification=True)
 
         c.num_words=32
         c.words_per_row=2

From 3587f90e945c5e966ae25d863fd6c78c6162d224 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Tue, 11 Sep 2018 14:47:55 -0700
Subject: [PATCH 4/4] Fix copy pasta error in create vertical channel route

---
 compiler/base/hierarchy_layout.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 191fa492..5cd67eea 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -835,13 +835,13 @@ class layout(lef.lef):
                 offset -= vector(0,pitch)
 
 
-    def create_vertical_channel_route(self, route_map, left_inst, right_inst, offset, 
+    def create_vertical_channel_route(self, route_map, left_pins, right_pins, offset, 
                                       layer_stack=("metal1", "via1", "metal2"),
                                       pitch=None):
         """
         Wrapper to create a vertical channel route
         """
-        self.create_channel_route(route_map, left_inst, right_inst, offset,
+        self.create_channel_route(route_map, left_pins, right_pins, offset,
                                   layer_stack, pitch, vertical=True)
 
     def create_horizontal_channel_route(self, route_map, top_pins, bottom_pins, offset,