From 642dc8517c5809ad2b46ec371f7e63899d50e22b Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Thu, 1 Nov 2018 14:05:55 -0700
Subject: [PATCH] Added no mux functional test for 1rw+1r. Delay
 characterization also works for the custom cell as well.

---
 compiler/example_config_freepdk45.py          | 14 +++--
 compiler/example_config_scn4m_subm.py         | 18 ++++--
 .../22_sram_1rw_1r_1bank_nomux_func_test.py   | 60 +++++++++++++++++++
 3 files changed, 82 insertions(+), 10 deletions(-)
 create mode 100755 compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py

diff --git a/compiler/example_config_freepdk45.py b/compiler/example_config_freepdk45.py
index 5e7a689f..c6f36c29 100644
--- a/compiler/example_config_freepdk45.py
+++ b/compiler/example_config_freepdk45.py
@@ -11,8 +11,14 @@ output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
 
 #Setting for multiport
 # netlist_only = True
-# bitcell = "pbitcell"
-# replica_bitcell="replica_pbitcell"
 # num_rw_ports = 1
-# num_r_ports = 0
-# num_w_ports = 1
+# num_r_ports = 1
+# num_w_ports = 0
+
+#Pbitcell modules for multiport
+#bitcell = "pbitcell"
+#replica_bitcell="replica_pbitcell"
+
+#Custom 1rw+1r multiport cell. Set the above port numbers to rw = 1, r = 1, w = 0
+# bitcell = "bitcell_1rw_1r"
+# replica_bitcell = "replica_bitcell_1rw_1r"
diff --git a/compiler/example_config_scn4m_subm.py b/compiler/example_config_scn4m_subm.py
index 436d0ffd..e53d64a8 100644
--- a/compiler/example_config_scn4m_subm.py
+++ b/compiler/example_config_scn4m_subm.py
@@ -10,9 +10,15 @@ output_path = "temp"
 output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
 
 #Setting for multiport
-netlist_only = True
-bitcell = "pbitcell"
-replica_bitcell="replica_pbitcell"
-num_rw_ports = 1
-num_r_ports = 1
-num_w_ports = 1
\ No newline at end of file
+# netlist_only = True
+# num_rw_ports = 1
+# num_r_ports = 1
+# num_w_ports = 0
+
+#Pbitcell modules for multiport
+#bitcell = "pbitcell"
+#replica_bitcell="replica_pbitcell"
+
+#Custom 1rw+1r multiport cell. Set the above port numbers to rw = 1, r = 1, w = 0
+# bitcell = "bitcell_1rw_1r"
+# replica_bitcell = "replica_bitcell_1rw_1r"
\ No newline at end of file
diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
new file mode 100755
index 00000000..aa80656d
--- /dev/null
+++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
@@ -0,0 +1,60 @@
+#!/usr/bin/env python3
+"""
+Run a functioal test on 1 bank SRAM
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test")
+class psram_1bank_nomux_func_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 1
+        
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram import sram
+        from sram_config import sram_config
+        c = sram_config(word_size=4,
+                        num_words=32,
+                        num_banks=1)
+        c.words_per_row=1
+        debug.info(1, "Functional test for sram 1rw,1r with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                                                                c.num_words,
+                                                                                                                c.words_per_row,
+                                                                                                                c.num_banks))
+        s = sram(c, name="sram")
+        tempspice = OPTS.openram_temp + "temp.sp"
+        s.sp_write(tempspice)
+        
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        
+        f = functional(s.s, tempspice, corner)
+        f.num_cycles = 10
+        (fail, error) = f.run()
+        self.assertTrue(fail,error)
+        
+        globals.end_openram()
+        
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()