diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index ebdc9093..aa9212b3 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -48,26 +48,27 @@ class timing_sram_test(openram_test): loads = [tech.spice["FF_in_cap"]*4] slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data,slews,loads) + #print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.0339194, - 'read0_power': 0.0340617, - 'write0_power': 0.0287779, - 'delay1': [0.0575725], - 'delay0': [0.16744839999999997], - 'min_period': 0.391, - 'write1_power': 0.0299736, - 'slew0': [0.026416], - 'slew1': [0.020441199999999996]} + golden_data = {'read1_power': 0.0345742, + 'read0_power': 0.03526189999999999, + 'write0_power': 0.0270014, + 'delay1': [0.0573107], + 'delay0': [0.07055809999999998], + 'min_period': 0.234, + 'write1_power': 0.0376625, + 'slew0': [0.0284344], + 'slew1': [0.0189185]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 5.557800000000001, - 'read0_power': 5.5712, - 'write0_power': 3.8325, - 'delay1': [1.0323], - 'delay0': [2.2134], - 'min_period': 6.25, - 'write1_power': 3.6903, - 'slew0': [1.3009000000000002], - 'slew1': [0.983561]} + golden_data = {'read1_power': 11.2474, + 'read0_power': 11.3148, + 'write0_power': 6.9064, + 'delay1': [1.0298], + 'delay0': [1.4102], + 'min_period': 4.063, + 'write1_power': 11.6964, + 'slew0': [1.3118], + 'slew1': [0.9816656]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index ccf40f31..be2c04d6 100644 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -46,26 +46,27 @@ class timing_sram_test(openram_test): loads = [tech.spice["FF_in_cap"]*4] slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data,slews,loads) + #print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.03228762, - 'read0_power': 0.03281849, - 'write0_power': 0.02902607, - 'delay1': [0.059081419999999996], - 'delay0': [0.1716648], - 'min_period': 0.391, - 'write1_power': 0.02879424, - 'slew0': [0.02851539], - 'slew1': [0.02319674]} + golden_data = {'read1_power': 0.03308298, + 'read0_power': 0.03866541, + 'write0_power': 0.02695139, + 'delay1': [0.05840294000000001], + 'delay0': [0.40787249999999997], + 'min_period': 0.781, + 'write1_power': 0.037257830000000006, + 'slew0': [0.035826199999999996], + 'slew1': [0.02059459]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 5.063901, - 'read0_power': 4.926464999999999, - 'write0_power': 3.480712, - 'delay1': [1.044746], - 'delay0': [2.23024], - 'min_period': 6.563, - 'write1_power': 3.1949449999999997, - 'slew0': [1.3469], - 'slew1': [1.035352]} + golden_data = {'read1_power': 10.31395, + 'read0_power': 10.0321, + 'write0_power': 6.072756, + 'delay1': [1.042564], + 'delay0': [1.412224], + 'min_period': 4.688, + 'write1_power': 10.53758, + 'slew0': [1.355812], + 'slew1': [1.03401]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib index 990f264e..e0360805 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib @@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("0.043273977"); + values("0.0370166"); } fall_power(scalar){ - values("0.042322667"); + values("0.026622831"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("0.088241812"); + values("0.034203045"); } fall_power(scalar){ - values("0.088188668"); + values("0.039377859"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.055, 0.055, 0.063",\ - "0.055, 0.056, 0.063",\ - "0.061, 0.062, 0.069"); + values("0.054, 0.055, 0.061",\ + "0.055, 0.055, 0.062",\ + "0.06, 0.061, 0.067"); } cell_fall(CELL_TABLE) { - values("0.162, 0.163, 0.171",\ - "0.163, 0.164, 0.172",\ - "0.168, 0.169, 0.178"); + values("0.438, 0.439, 0.449",\ + "0.439, 0.44, 0.449",\ + "0.445, 0.446, 0.455"); } rise_transition(CELL_TABLE) { - values("0.015, 0.016, 0.028",\ - "0.015, 0.016, 0.028",\ - "0.015, 0.016, 0.028"); + values("0.013, 0.014, 0.026",\ + "0.013, 0.014, 0.026",\ + "0.013, 0.015, 0.026"); } fall_transition(CELL_TABLE) { - values("0.018, 0.02, 0.035",\ - "0.018, 0.02, 0.035",\ - "0.018, 0.02, 0.035"); + values("0.027, 0.029, 0.043",\ + "0.027, 0.029, 0.043",\ + "0.027, 0.029, 0.043"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("0.2245"); + values("0.449"); } fall_constraint(scalar) { - values("0.2245"); + values("0.449"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("0.449"); + values("0.898"); } fall_constraint(scalar) { - values("0.449"); + values("0.898"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib index 088b7826..201f0467 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib @@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("3.9245536"); + values("5.5339993"); } fall_power(scalar){ - values("4.1029534"); + values("3.2697936"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("6.3714394"); + values("5.5897458"); } fall_power(scalar){ - values("6.2007335"); + values("5.460329"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.668, 0.753, 1.433",\ - "0.671, 0.756, 1.437",\ - "0.723, 0.805, 1.485"); + values("0.664, 0.748, 1.425",\ + "0.667, 0.75, 1.429",\ + "0.718, 0.8, 1.477"); } cell_fall(CELL_TABLE) { - values("1.697, 1.807, 2.782",\ - "1.702, 1.811, 2.787",\ - "1.756, 1.865, 2.839"); + values("0.857, 0.981, 1.971",\ + "0.859, 0.984, 1.976",\ + "0.911, 1.033, 2.025"); } rise_transition(CELL_TABLE) { - values("0.185, 0.334, 1.877",\ - "0.186, 0.336, 1.877",\ - "0.188, 0.339, 1.878"); + values("0.182, 0.331, 1.876",\ + "0.183, 0.333, 1.876",\ + "0.186, 0.336, 1.876"); } fall_transition(CELL_TABLE) { - values("0.235, 0.444, 2.457",\ - "0.234, 0.444, 2.457",\ - "0.234, 0.444, 2.456"); + values("0.361, 0.487, 2.459",\ + "0.365, 0.488, 2.459",\ + "0.369, 0.496, 2.459"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_scn3me_subm){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("4.6875"); + values("3.125"); } fall_constraint(scalar) { - values("4.6875"); + values("3.125"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("9.375"); + values("6.25"); } fall_constraint(scalar) { - values("9.375"); + values("6.25"); } } }