From 63392c8d714b479854ccac4202c0ed47c8819cd1 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 2 Feb 2018 13:04:38 -0800
Subject: [PATCH] Fix gnd connection in control logic.

---
 compiler/control_logic.py   |  1 +
 compiler/replica_bitline.py | 12 +++++++-----
 compiler/route.py           |  2 +-
 compiler/wire.py            |  2 --
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/compiler/control_logic.py b/compiler/control_logic.py
index eceeb29a..325d92e9 100644
--- a/compiler/control_logic.py
+++ b/compiler/control_logic.py
@@ -326,6 +326,7 @@ class control_logic(design.design):
         x_off += self.inv1.width
         
         # BUFFER INVERTERS FOR W_EN
+        # FIXME: Can we remove these two invs and size the previous one?
         self.pre_w_en_bar_offset = vector(x_off, y_off)
         self.pre_w_en_bar=self.add_inst(name="inv_pre_w_en_bar",
                                         mod=self.inv1,
diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py
index 9345cb48..7fa9544a 100644
--- a/compiler/replica_bitline.py
+++ b/compiler/replica_bitline.py
@@ -242,11 +242,15 @@ class replica_bitline(design.design):
         # Add a rail in M1 from bottom to two along delay chain
         gnd_start = self.rbl_inv_inst.get_pin("gnd").ll() - self.offset_fix
         
+        self.add_rect(layer="metal2",
+                      offset=gnd_start,
+                      width=self.m2_width,
+                      height=self.rbl_inst.uy()+2*self.m2_pitch - gnd_start.y)
         self.add_layout_pin(text="gnd",
-                            layer="metal2",
+                            layer="metal1",
                             offset=gnd_start.scale(1,0),
-                            width=self.m2_width,
-                            height=self.rbl_inst.uy()+2*self.m2_pitch)
+                            width=self.m1_width,
+                            height=gnd_start.y)
                       
         # Connect the WL pins directly to gnd
         for row in range(self.rows):
@@ -273,8 +277,6 @@ class replica_bitline(design.design):
         # Connect the bitcell gnd pins to the rail
         gnd_pins = self.get_pins("gnd")
         gnd_start = gnd_pins[0].ul()
-        self.add_via_center(layers=("metal1", "via1", "metal2"),
-                            offset=gnd_pins[0].uc())
         rbl_gnd_pins = self.rbl_inst.get_pins("gnd")
         # Add L shapes to each vertical gnd rail
         for pin in rbl_gnd_pins:
diff --git a/compiler/route.py b/compiler/route.py
index 9e643bc7..03b62cff 100644
--- a/compiler/route.py
+++ b/compiler/route.py
@@ -7,7 +7,7 @@ from vector3d import vector3d
 
 class route():
     """ 
-    Object route
+    Object route (used by the router module)
     Add a route of minimium metal width between a set of points.
     The wire must be completely rectilinear and the 
     z-dimension of the points refers to the layers (plus via)
diff --git a/compiler/wire.py b/compiler/wire.py
index 879baf9b..08670bb5 100644
--- a/compiler/wire.py
+++ b/compiler/wire.py
@@ -12,8 +12,6 @@ class wire(path):
     The points are the center of the wire.
     The layer stack is the vertical, contact/via, and horizontal layers, respectively. 
     """
-    unique_id = 1
-
     def __init__(self, obj, layer_stack, position_list):
         self.obj = obj
         self.layer_stack = layer_stack