From a51aacfa90ad8a5fc1302d2e26c61817e2a5afdd Mon Sep 17 00:00:00 2001
From: Jennifer Eve Sowash <jsowash@mada0.SOE.UCSC.EDU>
Date: Fri, 7 Dec 2018 19:42:11 -0800
Subject: [PATCH 01/28] Added corner case for 1 inv pos polarity and renamed
 variables.

---
 compiler/pgates/pdriver.py        | 63 +++++++++++++++++--------------
 compiler/tests/04_pdriver_test.py | 12 +++---
 2 files changed, 41 insertions(+), 34 deletions(-)
 mode change 100644 => 100755 compiler/tests/04_pdriver_test.py

diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py
index 34fcc94a..ef311586 100644
--- a/compiler/pgates/pdriver.py
+++ b/compiler/pgates/pdriver.py
@@ -13,25 +13,25 @@ class pdriver(pgate.pgate):
     """
     unique_id = 1
 
-    def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []):
+    def __init__(self, neg_polarity=False, fanout_size=8, size_list = [], height=None, name=""):
 
         self.stage_effort = 4
-        self.row_height = height 
+        self.height = height 
         self.neg_polarity = neg_polarity
         self.size_list = size_list
-        self.c_load = c_load
-
-        if len(self.size_list) > 0 and (self.c_load != 8 or self.neg_polarity):
-            raise Exception("Cannot specify both size_list and neg_polarity or c_load.")
-        
-        self.compute_sizes()
+        self.fanout_size = fanout_size
 
+        if len(self.size_list) > 0 and (self.fanout_size != 8 or self.neg_polarity):
+            debug.error("Cannot specify both size_list and neg_polarity or fanout_size.", -1)
+ 
         if name=="":
-            name = "pdriver_{0}_{1}_".format(self.num_inv, pdriver.unique_id)
-            pdriver.unique_id += 1
-
+            name = "pdriver_{}".format(pdriver.unique_id)
+            pdriver.unique_id += 1               
+        
         pgate.pgate.__init__(self, name) 
         debug.info(1, "Creating {}".format(self.name))
+        
+        self.compute_sizes()
 
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -45,8 +45,8 @@ class pdriver(pgate.pgate):
             self.num_inv = len(self.size_list)
         else:
             # find the number of stages
-            #c_load is a unit inverter fanout, not a capacitance so c_in=1
-            num_stages = int(round(log(self.c_load)/log(4)))
+            #fanout_size is a unit inverter fanout, not a capacitance so c_in=1
+            num_stages = max(1,int(round(log(self.fanout_size)/log(4))))
 
             # find inv_num and compute sizes
             if self.neg_polarity:
@@ -65,30 +65,35 @@ class pdriver(pgate.pgate):
         self.calc_size_list = []
         self.num_inv = num_stages
         # compute sizes
-        c_prev = self.c_load
+        fanout_size_prev = self.fanout_size
         for x in range(self.num_inv-1,-1,-1):
-            c_prev = int(round(c_prev/self.stage_effort))
-            self.calc_size_list.append(c_prev)
+            fanout_size_prev = int(round(fanout_size_prev/self.stage_effort))
+            self.calc_size_list.append(fanout_size_prev)
 
 
     def diff_polarity(self, num_stages):
         self.calc_size_list = []
         # find which delay is smaller
-        delay_below = ((num_stages-1)*(self.c_load**(1/num_stages-1))) + num_stages-1
-        delay_above = ((num_stages+1)*(self.c_load**(1/num_stages+1))) + num_stages+1
-        if (delay_above < delay_below):
-            # recompute stage_effort for this delay
+        if (num_stages > 1):
+            delay_below = ((num_stages-1)*(self.fanout_size**(1/num_stages-1))) + num_stages-1
+            delay_above = ((num_stages+1)*(self.fanout_size**(1/num_stages+1))) + num_stages+1
+            if (delay_above < delay_below):
+                # recompute stage_effort for this delay
+                self.num_inv = num_stages+1
+                polarity_stage_effort = self.fanout_size**(1/self.num_inv)
+            else:
+                self.num_inv = num_stages-1
+                polarity_stage_effort = self.fanout_size**(1/self.num_inv)
+        else: # num_stages is 1, can't go to 0
             self.num_inv = num_stages+1
-            polarity_stage_effort = self.c_load**(1/self.num_inv)
-        else:
-            self.num_inv = num_stages-1
-            polarity_stage_effort = self.c_load**(1/self.num_inv)
+            polarity_stage_effort = self.fanout_size**(1/self.num_inv)
+
         
         # compute sizes
-        c_prev = self.c_load
+        fanout_size_prev = self.fanout_size
         for x in range(self.num_inv-1,-1,-1):
-            c_prev = int(round(c_prev/polarity_stage_effort))
-            self.calc_size_list.append(c_prev)
+            fanout_size_prev = int(round(fanout_size_prev/polarity_stage_effort))
+            self.calc_size_list.append(fanout_size_prev)
 
 
     def create_netlist(self):
@@ -118,11 +123,11 @@ class pdriver(pgate.pgate):
         self.inv_list = []
         if len(self.size_list) > 0: # size list specified
             for x in range(len(self.size_list)):
-                self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height))
+                self.inv_list.append(pinv(size=self.size_list[x], height=self.height))
                 self.add_mod(self.inv_list[x])
         else: # find inv sizes
             for x in range(len(self.calc_size_list)):
-                self.inv_list.append(pinv(size=self.calc_size_list[x], height=self.row_height))
+                self.inv_list.append(pinv(size=self.calc_size_list[x], height=self.height))
                 self.add_mod(self.inv_list[x])
     
     
diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py
old mode 100644
new mode 100755
index 1cd450c5..b14fb115
--- a/compiler/tests/04_pdriver_test.py
+++ b/compiler/tests/04_pdriver_test.py
@@ -11,6 +11,8 @@ import globals
 from globals import OPTS
 import debug
 
+#os.system("chmod u+x 04_pdriver_test.py")
+
 class pdriver_test(openram_test):
 
     def runTest(self):
@@ -22,12 +24,12 @@ class pdriver_test(openram_test):
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         # a tests the error message for specifying conflicting conditions
-        #a = pdriver.pdriver(c_load = 4,size_list = [1,2,4,8])
+        #a = pdriver.pdriver(fanout_size = 4,size_list = [1,2,4,8])
         b = pdriver.pdriver(size_list = [1,2,4,8])
-        c = pdriver.pdriver(c_load = 50)
-        d = pdriver.pdriver(c_load = 50, neg_polarity = True)
-        e = pdriver.pdriver(c_load = 64)
-        f = pdriver.pdriver(c_load = 64, neg_polarity = True)
+        c = pdriver.pdriver(fanout_size = 50)
+        d = pdriver.pdriver(fanout_size = 50, neg_polarity = True)
+        e = pdriver.pdriver(fanout_size = 64)
+        f = pdriver.pdriver(fanout_size = 64, neg_polarity = True)
         #self.local_check(a)
         self.local_check(b)
         self.local_check(c)

From bc44c80d40bdc6c8450a975cd75e909d62455d25 Mon Sep 17 00:00:00 2001
From: Jennifer Eve Sowash <jsowash@mada0.SOE.UCSC.EDU>
Date: Thu, 13 Dec 2018 19:03:31 -0800
Subject: [PATCH 02/28] Added height to init in pdriver.py

---
 compiler/pgates/pdriver.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py
index ef311586..5da68032 100644
--- a/compiler/pgates/pdriver.py
+++ b/compiler/pgates/pdriver.py
@@ -28,7 +28,7 @@ class pdriver(pgate.pgate):
             name = "pdriver_{}".format(pdriver.unique_id)
             pdriver.unique_id += 1               
         
-        pgate.pgate.__init__(self, name) 
+        pgate.pgate.__init__(self, name, height) 
         debug.info(1, "Creating {}".format(self.name))
         
         self.compute_sizes()

From cc27736a45cfd1e82f9c6dd37b0a70fd20df6f90 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Wed, 2 Jan 2019 10:14:45 -0800
Subject: [PATCH 03/28] moved DRC and LVS error reports to datasheet.info from
 datasheet.py

---
 compiler/characterizer/lib.py                 | 18 ++++++++++++--
 compiler/datasheet/datasheet.py               | 15 ++----------
 compiler/datasheet/datasheet_gen.py           | 14 ++++++++++-
 .../datasheet/server_scripts/deliverable.py   | 24 ++++++++++++++-----
 compiler/datasheet/server_scripts/filelist.py |  3 ---
 5 files changed, 49 insertions(+), 25 deletions(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index fbe84811..f8d8116d 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -533,6 +533,17 @@ class lib:
                         git_id
                         ))
 
+        # information of checks
+        from hierarchy_design import total_drc_errors
+        from hierarchy_design import total_lvs_errors
+        DRC = 'skipped'
+        LVS = 'skipped'
+        if OPTS.check_lvsdrc:
+            DRC = str(total_drc_errors)
+            LVS = str(total_lvs_errors)
+
+        datasheet.write("{0},{1},".format(DRC, LVS))
+
         for port in self.all_ports:
             #DIN timings
             if port in self.write_ports:
@@ -627,8 +638,11 @@ class lib:
                         min(list(map(round_time,self.times["hold_times_HL"]))),
                         max(list(map(round_time,self.times["hold_times_HL"])))
 
-                        )) 
-                                                                                            
+                        ))
+
+
+
+
         datasheet.write("END\n")
         datasheet.close()
                 
diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 0ccca339..7536a343 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -4,8 +4,6 @@ from characterization_corners import *
 from deliverables import *
 from timing_and_current_data import *
 from in_out import *
-from hierarchy_design import total_drc_errors
-from hierarchy_design import total_lvs_errors
 import os
 import csv
 import base64
@@ -33,15 +31,6 @@ class datasheet():
             #css styling is kept in a seperate file
             self.html += datasheet_css.read()
 
-        if OPTS.check_lvsdrc:
-            
-            DRC = str(total_drc_errors) + ' errors'
-            LVS = str(total_lvs_errors) + ' errors'
-            PEX = 'n/a'
-        else:
-            DRC = 'skipped'
-            LVS = 'skipped'
-            PEX = 'skipped'
         
         with open(OPTS.openram_temp + "/datasheet.info") as info:           
             self.html += '<!--'
@@ -65,8 +54,8 @@ class datasheet():
 
 
         self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ self.name + '.html' + '</p>'
-        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'DRC: ' + str(DRC) + '</p>'
-        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS: ' + str(LVS) + '</p>'
+        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'DRC: ' + str(self.DRC) + '</p>'
+        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS: ' + str(self.LVS) + '</p>'
         self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'Git commit id: ' + str(self.git_id) + '</p>'
 
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p>'
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index af5fbee0..4b266dbc 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -102,6 +102,11 @@ def parse_characterizer_csv(sram,f,pages):
             ORIGIN_ID = row[col]
             col += 1
 
+            DRC = row[col]
+            col += 1
+
+            LVS = row[col]
+            col += 1
     
             for sheet in pages:
 
@@ -336,6 +341,9 @@ def parse_characterizer_csv(sram,f,pages):
                                         col += 2
 
                             col += 1
+
+
+
                         else:
                             break
 
@@ -351,6 +359,9 @@ def parse_characterizer_csv(sram,f,pages):
                 pages.append(new_sheet)
 
                 new_sheet.git_id = ORIGIN_ID 
+                new_sheet.DRC = DRC
+                new_sheet.LVS = LVS
+
 
                 new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
 
@@ -470,7 +481,8 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet.io.append(in_out_item('NUM_R_PORTS',NUM_R_PORTS))
                 new_sheet.io.append(in_out_item('NUM_W_PORTS',NUM_W_PORTS))
                 new_sheet.io.append(in_out_item('Area',sram.width * sram.height))
-                
+
+
 
 
 
diff --git a/compiler/datasheet/server_scripts/deliverable.py b/compiler/datasheet/server_scripts/deliverable.py
index 801415c9..9ba3c0e6 100644
--- a/compiler/datasheet/server_scripts/deliverable.py
+++ b/compiler/datasheet/server_scripts/deliverable.py
@@ -1,7 +1,19 @@
-class deliverable:
-    def __init__(self, name, file_type, path, size):
-        self.name = name
-        self.file_type = file_type
-        self.path = path
-        self.size = size
+from flask_table import *
 
+class deliverables(Table):
+    """
+    Set up delivarables table columns and title information
+    """
+    typ = Col('Type')
+    description = Col('Description')
+    link = Col('Link')
+
+
+class deliverables_item(object):
+    """
+    Define deliverables table row elemenent information
+    """
+    def __init__(self, typ, description,link):
+        self.typ = typ
+        self.description = description
+        self.link = link
diff --git a/compiler/datasheet/server_scripts/filelist.py b/compiler/datasheet/server_scripts/filelist.py
index ec2eee88..154d586a 100644
--- a/compiler/datasheet/server_scripts/filelist.py
+++ b/compiler/datasheet/server_scripts/filelist.py
@@ -14,6 +14,3 @@ class filelist:
                 out_file.write('{}/{}\n'.format(root,file))
                 #print('{}/{}'.format(root,file))
 
-
-
-

From c69e5fdb18111f1031eb182e595e6b9d471337ce Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Wed, 2 Jan 2019 10:30:03 -0800
Subject: [PATCH 04/28] added compile time to datasheet

---
 compiler/characterizer/lib.py       | 7 +++++--
 compiler/datasheet/datasheet.py     | 1 +
 compiler/datasheet/datasheet_gen.py | 6 +++++-
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index f8d8116d..3e97aba1 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -1,6 +1,7 @@
 import os,sys,re
 import debug
 import math
+import datetime
 from .setup_hold import *
 from .delay import *
 from .charutils import *
@@ -515,7 +516,8 @@ class lib:
 
         datasheet = open(OPTS.openram_temp +'/datasheet.info', 'a+')
 
-        datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13},{14},".format(
+        current_time = datetime.datetime.now()
+        datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13},{14},{15},".format(
                         "sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name),
                         OPTS.num_words,
                         OPTS.num_banks,
@@ -530,7 +532,8 @@ class lib:
                         self.out_dir,
                         lib_name,
                         OPTS.word_size,
-                        git_id
+                        git_id,
+                        current_time
                         ))
 
         # information of checks
diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 7536a343..9b46e190 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -54,6 +54,7 @@ class datasheet():
 
 
         self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ self.name + '.html' + '</p>'
+        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Compiled at: '+ self.time + '</p>'
         self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'DRC: ' + str(self.DRC) + '</p>'
         self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS: ' + str(self.LVS) + '</p>'
         self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'Git commit id: ' + str(self.git_id) + '</p>'
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index 4b266dbc..f6c574a7 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -102,6 +102,9 @@ def parse_characterizer_csv(sram,f,pages):
             ORIGIN_ID = row[col]
             col += 1
 
+            DATETIME = row[col]
+            col+= 1
+
             DRC = row[col]
             col += 1
 
@@ -358,7 +361,8 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet = datasheet(NAME)
                 pages.append(new_sheet)
 
-                new_sheet.git_id = ORIGIN_ID 
+                new_sheet.git_id = ORIGIN_ID
+                new_sheet.time = DATETIME
                 new_sheet.DRC = DRC
                 new_sheet.LVS = LVS
 

From 53b7e46db4ec63e10792a87888172de860673e17 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Thu, 3 Jan 2019 12:28:29 -0800
Subject: [PATCH 05/28] fixed bug where retrieving git id would fail depending
 on cwd

---
 compiler/characterizer/lib.py                 | 14 ++++++++++++--
 .../datasheet/server_scripts/deliverable.py   | 19 -------------------
 2 files changed, 12 insertions(+), 21 deletions(-)
 delete mode 100644 compiler/datasheet/server_scripts/deliverable.py

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 3e97aba1..0ed7b3e6 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -510,9 +510,19 @@ class lib:
             git_id = 'AAAAAAAAAAAAAAAAAAAA'
         else:
             with open(os.devnull, 'wb') as devnull:
-                proc = subprocess.Popen(['git','rev-parse','HEAD'], stdout=subprocess.PIPE)
+                print(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/')
+                proc = subprocess.Popen(['git','rev-parse','HEAD'], cwd=os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/', stdout=subprocess.PIPE)
+
                 git_id = str(proc.stdout.read())
-                git_id = git_id[2:-3] 
+                
+                try:
+                    git_id = git_id[2:-3] 
+                except:
+                    pass
+
+                if len(git_id) != 40:
+                    debug.warning("Failed to retrieve git id")
+                    git_id = 'Failed to retruieve'
 
         datasheet = open(OPTS.openram_temp +'/datasheet.info', 'a+')
 
diff --git a/compiler/datasheet/server_scripts/deliverable.py b/compiler/datasheet/server_scripts/deliverable.py
deleted file mode 100644
index 9ba3c0e6..00000000
--- a/compiler/datasheet/server_scripts/deliverable.py
+++ /dev/null
@@ -1,19 +0,0 @@
-from flask_table import *
-
-class deliverables(Table):
-    """
-    Set up delivarables table columns and title information
-    """
-    typ = Col('Type')
-    description = Col('Description')
-    link = Col('Link')
-
-
-class deliverables_item(object):
-    """
-    Define deliverables table row elemenent information
-    """
-    def __init__(self, typ, description,link):
-        self.typ = typ
-        self.description = description
-        self.link = link

From 6acc8c89028fd8f8d8aa65488b5fcfd4284ef59c Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Thu, 3 Jan 2019 13:41:25 -0800
Subject: [PATCH 06/28] removed print debug statement

---
 compiler/characterizer/lib.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 0ed7b3e6..ae1d3c82 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -510,7 +510,6 @@ class lib:
             git_id = 'AAAAAAAAAAAAAAAAAAAA'
         else:
             with open(os.devnull, 'wb') as devnull:
-                print(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/')
                 proc = subprocess.Popen(['git','rev-parse','HEAD'], cwd=os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/', stdout=subprocess.PIPE)
 
                 git_id = str(proc.stdout.read())

From 30c74accafc62a3ddb3c509dddfd4a869441d07b Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Thu, 3 Jan 2019 15:37:53 -0800
Subject: [PATCH 07/28] Update README to include DRC/LVS tool in example

---
 README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/README.md b/README.md
index 693d32ef..dbc18f64 100644
--- a/README.md
+++ b/README.md
@@ -98,6 +98,12 @@ output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
 
 # Disable analytical models for full characterization (WARNING: slow!)
 # analytical_delay = False
+
+# To force this to use magic and netgen for DRC/LVS/PEX
+# Could be calibre for FreePDK45
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
 ```
 
 You can then run OpenRAM by executing:

From 2236ca40df830eb6fb7d0427ceb78ea8d63f64ec Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Thu, 3 Jan 2019 19:20:31 -0800
Subject: [PATCH 08/28] Make xa least priority since it fails functional tests.

---
 compiler/characterizer/__init__.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py
index 4a2f161e..19da7d59 100644
--- a/compiler/characterizer/__init__.py
+++ b/compiler/characterizer/__init__.py
@@ -21,7 +21,7 @@ if not OPTS.analytical_delay:
         if OPTS.spice_exe=="" or OPTS.spice_exe==None:
             debug.error("{0} not found. Unable to perform characterization.".format(OPTS.spice_name),1)
     else:
-        (OPTS.spice_name,OPTS.spice_exe) = get_tool("spice",["xa", "hspice", "ngspice", "ngspice.exe"])
+        (OPTS.spice_name,OPTS.spice_exe) = get_tool("spice",["hspice", "ngspice", "ngspice.exe", "xa"])
 
     # set the input dir for spice files if using ngspice 
     if OPTS.spice_name == "ngspice":

From 5508ae945d268ff376e17ca5e369f24418641351 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Mon, 7 Jan 2019 17:08:47 -0800
Subject: [PATCH 09/28] updated file html description to simplify parsing

---
 compiler/datasheet/datasheet.py               |     9 +-
 compiler/datasheet/datasheet_gen.py           |     1 +
 .../datasheet/server_scripts/file_data.py     |     4 +
 .../datasheet/server_scripts/filelist.info    |    13 +
 .../contents2/sram_2_16_scn4m_subm.gds        |   Bin 0 -> 602124 bytes
 .../contents2/sram_2_16_scn4m_subm.html       |    86 +
 .../contents2/sram_2_16_scn4m_subm.lef        | 12857 ++++++++++++++++
 .../{ => contents2}/sram_2_16_scn4m_subm.py   |     4 +-
 .../contents2/sram_2_16_scn4m_subm.sp         |   559 +
 .../{ => contents2}/sram_2_16_scn4m_subm.v    |     0
 .../sram_2_16_scn4m_subm_TT_3p3V_25C.lib      |     0
 .../sram_2_16_scn4m_subm_TT_5V_25C.lib        |     0
 .../sram_2_16_scn4m_subm_TT_5p0V_25C.lib      |   321 +
 .../files/test_files/sram_2_16_scn4m_subm.gds |   Bin 419780 -> 0 bytes
 .../test_files/sram_2_16_scn4m_subm.html      |   116 -
 .../files/test_files/sram_2_16_scn4m_subm.lef |  9314 -----------
 .../files/test_files/sram_2_16_scn4m_subm.sp  |   767 -
 .../sram_2_16_scn4m_subm_TT_5p0V_25C.lib      |   625 -
 .../files/test_files/testfolder/file1         |     0
 .../files/test_files/testfolder/file2         |     0
 .../files/test_files/testfolder2/file3        |     0
 .../files/test_files/testfolder2/file4        |     0
 compiler/datasheet/server_scripts/index.html  |   124 +
 23 files changed, 13973 insertions(+), 10827 deletions(-)
 create mode 100644 compiler/datasheet/server_scripts/file_data.py
 create mode 100644 compiler/datasheet/server_scripts/filelist.info
 create mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.gds
 create mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.html
 create mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef
 rename compiler/datasheet/server_scripts/files/test_files/{ => contents2}/sram_2_16_scn4m_subm.py (91%)
 create mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp
 rename compiler/datasheet/server_scripts/files/test_files/{ => contents2}/sram_2_16_scn4m_subm.v (100%)
 rename compiler/datasheet/server_scripts/files/test_files/{ => contents2}/sram_2_16_scn4m_subm_TT_3p3V_25C.lib (100%)
 rename compiler/datasheet/server_scripts/files/test_files/{ => contents2}/sram_2_16_scn4m_subm_TT_5V_25C.lib (100%)
 create mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.gds
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.html
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.lef
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.sp
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/testfolder/file1
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/testfolder/file2
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/testfolder2/file3
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/testfolder2/file4
 create mode 100644 compiler/datasheet/server_scripts/index.html

diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 9b46e190..8eb18a0d 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -32,10 +32,13 @@ class datasheet():
             self.html += datasheet_css.read()
 
         
-        with open(OPTS.openram_temp + "/datasheet.info") as info:           
+#        with open(OPTS.openram_temp + "/datasheet.info") as info:           
             self.html += '<!--'
-            for row in info:
-                self.html += row
+#            for row in info:
+#                self.html += row
+            for item in self.description:
+               self.html += item + ','
+               self.teml += 'EOL'
             self.html +='-->'
     
         vlsi_logo = 0
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index f6c574a7..3fc38510 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -365,6 +365,7 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet.time = DATETIME
                 new_sheet.DRC = DRC
                 new_sheet.LVS = LVS
+                new_sheet.description = [NAME, NUM_WORDS, NUM_BANKS, NUM_RW_PORTS, NUM_W_PORTS, NUM_R_PORTS, TECH_NAME, WORD_SIZE, ORIGIN_ID, DATETIME]
 
 
                 new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
diff --git a/compiler/datasheet/server_scripts/file_data.py b/compiler/datasheet/server_scripts/file_data.py
new file mode 100644
index 00000000..f5ed4c23
--- /dev/null
+++ b/compiler/datasheet/server_scripts/file_data.py
@@ -0,0 +1,4 @@
+import csv
+
+class version_data:
+    
diff --git a/compiler/datasheet/server_scripts/filelist.info b/compiler/datasheet/server_scripts/filelist.info
new file mode 100644
index 00000000..77d515cc
--- /dev/null
+++ b/compiler/datasheet/server_scripts/filelist.info
@@ -0,0 +1,13 @@
+./files/test_files/sram_2_16_scn4m_subm.py
+./files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib
+./files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
+./files/test_files/sram_2_16_scn4m_subm.sp
+./files/test_files/sram_2_16_scn4m_subm.v
+./files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
+./files/test_files/sram_2_16_scn4m_subm.gds
+./files/test_files/sram_2_16_scn4m_subm.html
+./files/test_files/sram_2_16_scn4m_subm.lef
+./files/test_files/testfolder/file2
+./files/test_files/testfolder/file1
+./files/test_files/testfolder2/file4
+./files/test_files/testfolder2/file3
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.gds b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.gds
new file mode 100644
index 0000000000000000000000000000000000000000..4c5bacd19fc27e9ad82b0d0e32784ca5de725cd9
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new file mode 100644
index 00000000..613c384d
--- /dev/null
+++ b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.html
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oCmr19/6lSPHpF9orVrurY2CEhJSsqECdu3J0bNOc5ut1iuuuqdd5Kv5npM6h4vydF0SBBKRPvN057UHK4ZeLoS/57rq+avvbZ//8CBUBw2/n1D2h9QNnHIkDffnD0bZB3ivqHJDBcrqISv5aJN5IAWQjOkYYm2/WjTPyBKCsoI4hsa6000yTnS1gMU2Wyp1BEY9hpakaY13DYgepFUQQfuvHP9+kmTtmwpKenaNbJPtD1NT4SaB7PAs7LGju1oaq4l0Zqe6PZDaX9qrtc1o5eaQ+HX55/fvXvoUFTztgIMbtMuufnmvn31iLZGQnBQ4I4dI0ZAFu/48e++O3NmaBpMaLoFEDpcEtRZG5fVvmpjz7ENowQtA/2FqCrUHkl0XyX/SJNzbUDVlPz8l1++885f/GL9+okTtWsh/Qli2InuYS1wTqGCTWifQBg0mfuDJI4WEHTgtts+/PCGG9pfNF07aFJfNQdplqS6up079VVzSs3mbt2So+Ycl5MzbZrR2K/fH/8Ir7D1aNtpKU2P/3rTgmoeDrg29FJzmJ9BWwQWSQTagnpA81WiQ6VKK15FRT9UYciubqlBkKDskNcbyfvjjw3HFkfXZkUnJx89+UeazGsDYuQQ+w9Nf4InFeG2q+83IlydFrglgwo2+h470rLoLOizZl133YABmze/8MLtt8MrLAn3foimtydNh8f6iVBzECCvd+/eu+7SS81Bs2DKnkSrOfQkTOJjNPbqde+98Apbbyuartf1hmre/J7DtYFq3rYIzTkGfQmN44KmhOqjVrwgHqxVHIi2QrWKUNHRzgAKk9dEu/9FRT//+ccfQ+WW0PZBjyDDW7s8tMJ06HBJANJmIC4b+gprte+PbRhlaBxdvzP8Q1rqSJN/bQDwREW73eYH5ur9jbj++p07QweDgppjnZb2h24TFYGIr179l7/ceqt2+U9+Mnx4QcHs2U888dFHa9Zs315cHPpZ0PR3373ppi+/vOmmvn1LS39saz+c3kg7CZE21QTUJHIpSfREOZGRjFSTRGtWKDzfpctNN4Uuh63DGYwtaznRZw3ad7m2bbvuungmvQrX84lTcxBcn+/o0UWL9Lip4zi73WweNOippxKn5vGP30A1bylAmwoLc3Lq6qBGNcjE4cN33716dfOfhdQRECBYAsIBiSWgJpBMAm1+/PHs2Z99pu/+Q8vwGsksoSDBy5bt3XtpVDV0uCTEQZuvpwFr4Z2wD9phlJFP6wP9BnH0aOc6jZaWOtLkXxtaFi/+6qsRI2AmUVgC/Qx7rj12fb8R4ZKpYMhyJHse7YRTSMuiWwS9+Uh582sB0PR9+y5c6Nw5sm3+MJrO81273nYbRGRBgGDIZrQT0CQ/CzlIy6g5pOUkPtdcVSUpca0n/qzF+/Qm+WqeuFSr1qnmAEyRhmqefECboBbK73+/adPYseGGV8ISWAvvDDd9DLQJWeAzZ65ePXUqfCo0eQDaBK0JV4mlebT7HJprDsB2YSgeCOKhQ9XVmZna91yuFviRI5FVMAt9Z2wJJKGx3kTQskeazGtDC6S7hF4hy5Zdf/2l5YYT8Y1AOg5Uktav53ntohtu+PDDu+768suysmiqii5f/uCDU6fec8/06cOGha5dseKLLw4f/uUvn3tuw4ZIWvvyy9tv/+STESO6dKmpieT9HJeXd9ttFsuQIS+8ELo2+IgfSgRGR6KlCqA0JWXAAKt1+PDlyxnGYunaNTlqnohjCUcw77xXr3vvDV0rihcurF/v9x86tHBhWzjScBXiL59G0laqg0dypK1ZzUGbcJgUgiAI0laYNKl795KSL7647bZ33tEu1y2C/sYbGzYcPOhwuN1+f+hau91iiWa2rUmTVq6cMSPyaDrL2mzh6xmDWMR2XCAKICWwBGYhBXGJv9+CWeBXX71qFaVGY2amKJaXf/BBe1JzANJXYIInGOoaCFRVbdoky2736dMGQ5cuN92k1xDM5EfT4RrT1sJPTs+jmgOo5giCIEh7gn388blzWVa76L33iouHDCkpaWpKT4+8ocrK+nq3e82aoqLiYr9fFCVp376TJy9csFrNZoNh/PghQ/Lzu3TJzLTZNmzYvfv06UjafOedo0f79Zs8uUePioouXVJSPJ7m328wdO16aQY8EAhUVm7cGNtE9CBAIOVajVBVn+/8+Xi6PlTdAgFQ86NH//SneFrWYjINHvz88ybTgAGPPUYpx9lsyVdzLbLc2Lh/fyBQUbF2rSRVVm7YEAhUVHz8McdlZY0Zw/PZ2ZMmUWo0du4sSTU1l5aRihZVFYSaGkmqq9u1i+dzc6dN4/nc3BtvVBS/v7paD4VVFEGAqwvOIOw/HIssezwlJVbryJFvv61NJYIpruLvSVRzANUcQRAEabv07Jma6nDceecVV1w6YkQ3QQcaG91uv3/LlgMHSku/+OLbb8+eff/9rVu/+w6Gis6YMXp0375+vyBI0q5dx46Vl0fSJmj6jTf27l1Wlp1ttfp8oe8J6jLDGI0cl5ERHFQB0c3YBsklToDCZYELQnHxk0/G07IWqItiNg8a9MwzlLKs0SiKFRVr14riqVNLl+q1Fe0RMYzN1qcP9BXIa2Sfvqi5bVfTYT9hn2H/eT4v75ZbKGVZszk4cY8+57d9qDl8N73eAwfuuw/VHEEQBOmYhBN03XLQm2f48L59c3Kg8GJ6ekqK2bxgwdKlGzdCYkwkLUABpk2bbr/9k0/69cvMdDgS11nJVPNEx7MZJiNj1CirdcSIt96ilOMslsQNTIQl8fVYYgUx/K2RPnNeAjbb+PFFRQxjsXTvrih+f1WV27116zXXxN9ye1LzeMo+opojSFuEUkJkuaX3oq2gKGYzy1LqdBIiyxkZqmowVFTIMqUcR4iimEyEqKrZTIjBUF1NqSimpcWzPVUl5NJwLZIcEp6D3jz79586VVU1efIf/rByZWOjy+XzLV/+4IPTpv3kJ8OGRVYBHUZDX399dLnp0dKe1BxQlIaGPXt8viNH/vhHWKJXNjZMOaRVcwCODorxRd9qourcB3vjh7npMGhV3+mH3O6dO2+6SZLq67/5xu3+6is9RuKjmgMwAzGqOYIg7R1KZVmSTKaGBkniOEplORDo04cQSera1Wp1u3v04Di43VHV8EUtkbZLUmcSBU1fsGDp0mCNUqibDvH1SFoATYdZSOPRdJbNzBwzxmweOvSVVyyWq6565x2TaciQF19sT2quBfLvYbuwBI4U+iHWPkxNDV+8Mp6BucnXdH3bh/33evfsuf32+KuPo5oDoObw3Y9/3xAEQVozqsowokiIqtrthPh8bnd6uiQdOkTIjh33379v32uvffllWlpV1aOP5ufL8siRLb2/iP4kVdABmK4IUlwg3QVSX5Kj6dpp7SEjmeOyssaONRjy8m65RVVl2e/XS4BArYIzZeqj5rD/INbR1neH7Wo1Heb1jLadYGuVleEH3UJqRzy91/Y1PV5QzQFUcwRBOh4sK8uEiGL37qmpqipJ/ftbrV98UV+/YkWPHv37f/vtF198/fXzz//kJ5J06tRLL7X03iL6o/Mg0ciBaDoMGJ0x45pr+vYdPrxv39xcbR2Y5lvw+2WZZbdvP3cuLw/mH7XbjcZAoPlPQUqDdiCpFlmGooqnT7/8cjxHB/F4k6l37/vugyXxqznomtU6atR770G9mmB6CcMYjbJcX3/pFAnhAL2DIZIwXBJuVGAYJQypjKQdeCfc0sBNTnC5LPt8DGMwpKfrMdAz2UNI4drQq/3YQDUH1q8/dapHjzlz1q2bPLn5d95zz/TpQ4c+++zdd0+cOGPG6NF9+pw9W1nZ2AjVpeI/LgRB4odSyHRGfhyOk2VZVhRCTCaTyWxuaDh9+rvv9u//xz/eeae8/NChpiavd//+oqL6+h07cnJmzFBVVU1NJYRlBYEQSg0GQhjm+HFCOM7ttlgyMw0GlmUYl4vSmppu3WQ5L8/p5HmPh1JZpvTSsYhIMgk3SLQFIuhannvu/fd3737jjQ0bDhwAQd+8ecmS229PT7fZTKZIWjh3zum02aZOXbVq+vSKCpfLao1vjyQpvp9ziG0H4/Gqqig+33ffPflk/AktwfrrPwRuOSCyHnlr2mg6RPdB2qKNpkPRQKdz48aePeEVsq71jkl3lGh6W1FzuN6gfyBJzGodO3bDBn3VHGYXbv6djzwyZ87o0cExLcOHFxTMmjV+/IABW7YsWXLHHT175ubGN3AKQRCkJZCkTp0I4fna2qYmVTUaKe3T57HHZHn8+H/968UXH3988OBPPz1woKlJUUymPn0IYVm3mxBFYVmWlSSGIYTnCwosltraffteeumKKz755MCBe+/dufPaazt3XryYkJoaWVYUScrNpZTSHytjjSSfFhZ0ALLStZoOP7eRtxC5pgcCNTVFReHWimJZWXwaDZFsmGyIUkoZxmDIy7v55vgmNuI4ux00Otw7oGZItO3qpelaoORlqOzqMUlQe9b0tqLm2tagf+D5Ccva7VdcoSii2NCQHDUHQMpDl6el2WwmE0TW4+s9BEGQZCPLBkN1NSGKAnkBsqyqLFtfbzKdO7dyZV4ey3KcKErSFVcQ4nYbDISoKs+zrKJwnMGgKI2NV19dXFxc/M03f/7z9dePH9+3b3Fxjx6qeuHCe+/NnZuWZrPV1Jw9K8tGY2WlqhISb3AT0R+upXfgIo8++sYb27aBoEMMbPlyt3vqVO2g0ubRavpnn82du2FDXt4PpzdSlMbGvXt9vmPH/vIXlk1LGzRIVQWhrk6Wm5qOHYttMqNQ/H6omqIogQBIDAhNrOIiSU4nSFuopquqqsqyLHs8paWx7a02ug+CqN3b2ARRK7vQGrQcusXouajpWk0M9ny8qRqhe65v+6EkUs0JIUSr5pAsFM9RQDvhbggZxmDIyIhNzXfsKCvr0iVyNQc4jmWZGAMNTU0PP/zWW7F9NjZSU5csmT8/mVtsKZLft0BsPYxXAtLaUFVVTUnheZ8vO5tlCfH7VdVguHDB5Sov37q1qspqzcgQxQED5s4lpGfP118npKzsttsoVVVJEgRBqKrauvVf/zpz5osv9uw5f37BgkWLCDEYCKmqghCm2z1s2EMPEWI2nz5ttzudiuJ0clxmZuR7iN+aRNMqIugATHI0efLDD69cuX//qVOVlffcM336sGHPPnv33RMmRN6OVtOrq91uiyX0PYFAWdm774JGQw1svdRcC2gQRCvDTQUfOUFp83rLymCJqiqKKFJKKctarcOHv/pqPHH6RETTQ2PSehV5TE40HQomJqL9ZAJXIPwNefzxnNNEAEO9p09fvXrq1Mg/BYlwBQWXT2JxONxuvz/ymRaSQ0tpa0ego/14I8mE4/z+vDyWFcWsLJaVJKuVZWXZaCSEUpiST5ZVlVJFUVWjsbZWVQ2G+npV5fmGBlXlOKdTVQ0GQVBVg8HnU1We93pVlePcblVlWbNZVVk2JUVVOS4tTVU5LiuLEEJMpkDAYnE4BMFiSUmRZZOJEL9/06aFCz/99N//zspyu7t2HT3abj958pZbCDEaS0okyWYzmdau/dWvqqquuOL3vz96dOHCL7+cObOmZsKEJUvKyydNWriwqWnkyMWLKeW4mhpKvV673eXiOEwFbH20IkEHQNNnz37iiY8+gorpjzwyd+4110T7qDorKyend2+rdfz4oiKn02KZODH+fYP8cqOxX78//jFyxdRL04PKWFQ0fjxke7tcW7ZcdRXoI7SsjVLHBmq6Fm26TuI0PRF9nrj2IYkLeiN0LUz8FHlroOaTJq1cOWNG5J8CNYfxKvn52dmpqVu27N9fUvLcc6tWff01JMv95CcPP/zf/549W1mZyEnNEATpCAQCdvvx45Jks50+LUlWa0WFJFks1dWqqqq5uapKiN1OiKqaTIR4PNdcQ4jHM3y40eh29+uXmup05uVZLC5XVlZqalNTampOTlMTy+bnOxyS1KWLIOzZk5srCLt3d+okCHv2ZGaK4u7dGRmiWFpKCKUeT1oaw5w9y7IHDvztb0aj3b569Z///NFHp04RQkh5ucfDcWfOECKKubkpKV98sXDhypXvvrtpU2lp795/+9u5c4qSmWmxGI2CQAjLpqSwLMuyrKoqiqK0dL8izdGKUly0wM8qTGwERRi1WenNR8VCZy3973/37v3Zz6680unct6+gIC0t+ofv2iSES5fn5k6b5vXu3XvXXc23AJrOMBZLt26QswslDiP5bHh+mOwB+6OqgcBTT8WTxoBJL8lt/2IPQOoIDPyNv89D24e/4z+n8KngAGWeT02FZzswaDiSFuJXc0iHAx2PPBGuNQBx9PYa8cWnBEh7xO8fMMBkgtm5GYbjRLGpyem0Wk2mr76qqjp37uBBQWhsPHfOZrNYAoFp0264IS/vT396+OH77jObDQZZ5nmf7/Rpk4nnKeU4VQ0EzGaeZ9mUFEUZOpQQluU4QljWaBQEQRBFo7Fr12uucbsVRVXnzfvpT+fN27evro6Q7dsPHbruOrfb7//2W0IuXLDZZNlk6tz57rsLCtasefHF1asJycx8+OGVKwkxGKqqeJ6QigqO83h8Pp5nWatVkihVFEoZJtbkQCQ5UElav/7S8jo33PDhh3fd9eWXZWWXG3qVfEC49+17/fX58yGmDuIOhRq174R5SWHyI1DzRx99442tW6FWzLhxXbtWVb388pQpO3ZEq+kpKZMnHzwYbphmMMIaSaHDxBW5S1TLBkPPngsWQA0ZvTKkEzl5U2LLCCa+fUIuLVaYiKz0RGe9N09sag6sXv3447feGqzTsn9/SQn8axDP/rStbOnWT1vMTG2L+9wWoZQQmPsyWUDqCCGq6nBQqihQCLhTp86dfb7s7Jqa1NSdOwnJzLRaCamsTE8nhON4nhC/v7KyXz+f7+zZysqDBz/77OTJTz4ZPNhsNpvNZkYDKDUhqmowMAylLCvLLCvLDEMpxzEMpTzPMAxjMIgipUYjwzAMx1FKCMfB8kCAYQhhGIbheYaB94DCMwyUpYR3wlqDAWYVhSMTBL9flm+88cYb77133brPP//b37Kyrr566VJCCgt/+1tKGSaa4omqSsilRbebB781ejFpUvfuJSVffHHbbe+8o13eBu6fLs4/Gn5iI0iA2bx5yZI77oD3wPtBzeE9O3aUl+fk3H//55+PG1dS4nBEk17SfAWVaEhcSkaiWoaYKGgoJr0kvn1CLk2Lgj43mwcNeuqp+GoBXaT5pBftq15HBMSj5suXP/jg1Kmg5jBGBRLh9N1DBEHaEyaT18vzRqMoguCKIqUcV1FRU9O58+efE+L3DxtmtZ4+nZ7OsmfPvv/+o4/26vXMMz7fW285nUVFf/vb3r1VVV98EQhYLFaryWQ2WyyQd64owddgZXdY0lyV9+D7tZ/94d9wA3O5tapKCKUwP0xwW7KsKIHA9u3bt7/3XmZmdvawYYQ4nR4PIaqam9vSfY/ESxsQdADSWrSaDrE0bRVkiK/De8KlwYCmP/30rl3DhrndohjZ/aUk1dXt3Bm6HCqoQGm5aI6m7Wl6IpQRNT3yPo9/kHEooZpusYwc+fbbMPctvFqtY8Z8/HH8W3Q6u3X7y19++tP162fNivazoOYwZBzUHIaSw3gVvXo7+bS/VBCMqCGtDb/fZCopEQSjkWVlWRSzslRVljt37tvX5erbNzPz2LF587777plnVq1yuf71r8OHH398ypTCQlk+fbq42GxmmM6dBYFl+/VTFEUJBPx+v9/jUVVVlSR4VRRVFUVVJUQUVVVVL50qUdFACCGSBJINrakqIYGAoiiKKCqKqgYC0BqsBbOANoNbCW4RtiJJVqvNZjLBWklyOs+cKS8/dmztWkIIqatr6b5H4qXNCDoA2g1Zpz17dumSnv7ss/fcM3GiNvUlkroNq1cXF/fq9cADmzePGROJpnu9Bw7cd592cnuQcqigYrEMHvzss9FLTNvWdL2UETTd5zt6NJgigpqe6D7XApouihUV69YxjNEI1QOCwBbDTZIVCQ0NGRm/+lXXroMG/eIX0U5Dlhw1R8lDkPaLokBKiMdjs7lcGzcOHlxe/uCDRUWPP75iRV3d+vWpqV26+P3l5YS43dde63Ll5Gza5PPZ7fv2iSLHBQKyLEl5ecHodegraHcwqt1cAg+sDb7Cpy4uCbZzMVIefL24Nhi5D10uyxxns1mtXbsOHTptGiEGQ2T/xiKtmTYm6IB2YqPms9KbJxpNlySn0+c7ePC++4LzZW7ZMmKEHtp0UfJgmB1IHtSKia+f2pKmQ5lLiObCEtB0PRItUNN/HFX1+8N/d2Bwc7RtnjxZX5+WNnToE08EAqGzBTc/xyckrYGaB7/j7SFqjiBIIkhJkeX6erPZ4+nZk+PMZodDVTnOYklNdTjMZoNhx46nnjp+fNmy48c3bXrttfx8s1kUBcHhcLszMtxujrPZBMFiKS01GJqa8vM5zu3OyTEYAgG/32gkpLycZWXZ52NZWQ4EWFaSFIVlg4otyxCyI0SWIcItCIqiqn6/ohAS/JvnBcFoZBhRZNlgegohPh/HqaogcBwhPh/DqGpTE8sS0tTk9SpKRoYoKorZHAj4fD4fwwQCLhelhAQCRqMoulwGQyDgdHKcqrrdlOblLVpESGHh//0fROlb+pwg8dImBR0ATR8x4t573347WjXXEm00XQtoE0TWQZugNkv0eyFJTifE6SHZA+pj6BVFhvi0dnZMGPoZT7uJUEZt0gUs0a/gIGp6c8C1EW6toni9589H3hrkml9//cqVM2Y4HIJgMITOFrxv3+uv/+pX2pEkAKi5NmkNbr8TreYtFUdvH4kumNyCtCwuFyE9eni9mZk7dxoMqjpkSFZWaekHH7zxxl13rVzZ0LBx47BheXlOJyFpaV5vS82aeTEKrqoMExzoSUinTqKoqp07y7Isd+qkKJLUqVNWlqLs35+SQkhpqdlst1ssHg/L2u2yrKq9e//610uXHjxI6dVXv/56ly4LFnz3nck0cuSNNxKSktK5MyHBjHakLdOGBR3Qq87xmTOyPGaMyzVw4AcfeL2ERDOfFgglaBmUUIxNyxKXkx3aMiQtxN9yojVd77rgqOmXB4YCh461gKPw+0+ceO65SNoBNb/ttg8/vOEGUHPtWq2mhw74Dqfm8dx+IwjSEVBVt/v7702m2tqrrvJ4tmyZN6+4+IUXiotnzuzTx+Wi1O12u51OjktPr6212+vro23/h9nkF7erqlBRPIiqQVEu/ZzPBxnkHo/H4/MZjQaD3Z6ebjZfuGC3E1JZGQjIsiC43arK8xkZU6d++inDXHfdF1/k5v7yl5WVnTv/6lcul822YEFp6Vtvff/9qFGEDBnym99UVopinz5+v9HYuzfUk4E9bulzgsRLmxf0+NHWTe/Xr0+fQYO2b3e5fvYzjycQiDSarqeWJVPT9WoZNT257Seqz6EqP8yfCq8ez65dM2fCETX/2ebVXEs4TUc1b4tg7BxpDXTqBBnYNTXz51dVvfNOaqrNZjKlpooiIXa7IBgMXi8hDON22+1eb3p6S+wjpTC4U1FSUlJSUlOdzqYmr/f8eVGcPp3SoUPffDM3d/780tIePR55hGEaGzt1mjfPZBo5csGChgaez8vz+1mW5wlRFI+HEEqdTkoZJvjKcZIUCHCcLPt8qkop1jhv+3ToUxg6pRFUgJkzZ/lyQXj++d27hw51OptTjUtBTUdNT2b7iepzuEIir4l+7FhtbUZGJGquJVTTtctbSs0x0QVBWj92u9/PMKrK8zyfmpqS4nb/7neELFmyb98rr4wZYzTa7VlZfr+icJwss2wgQIiq8jylqsrzisIwgtBc6wwDiShQm0WSFMXjoVRV/X5KVdXnI0RRgq+yTIgoMoyiGI1ms6K4XIJgNp8/z7KE+Hx+f02Nx9PU5HJVVjY1OZ01NS6XxdK7d0rKlClvvJGf//DDTU35+f/3f8ePU3rddU88IQgZGQMGeDyi6PdTmp6eni4Ifr/XC1nslHJcIEApIVBkkWXhuOBVlhlGUWQZ9j445BRpy3RQQQ+n5toKMMuW7d07aNCLL+7ZU1gYv6bHNugTNR1ATU9+n0dCfT3HjRx5++1r106eHLmaawEdf+65Vau+/hq+g2vWbN9eXJy4fUYQpK3T1GS3V1ZCZRZF2br1hRceeODRR6+8kuNMpvr6YKwa8rwTi9GoKD6fKLKsLFdVmUzZ2Z07nzs3bJjF4vPJssGQl6coL764Zo0gdOnyhz/k5vboce+9DofVevXVL7/scrHsmDEt3ZdI66XDCXokaq5Fq+nRbOeHQzPjGfQJMq3NA4YM8vj1FDU9SPvU9JSUCRO2b7fbp007exZe9agORAgholhQsGhRQcH11//vfzfccO2148bF09qjj7755rZtkRRIRVoPmNyCtBwNDYWFhOzd+3//d+rUf/+bk6MoDAM53JCMR+nFUoZ6AFnkkiRJUMU8SH29z0dIRoYolpdnZFRVff/911/bbJWVPD9lytat+fm/+lWvXq+8Ulo6Z46qZmWNGOH3GwyZmR6Py1VebjKx7NmzLd2TSOulAwl6tGquBTT93/8+fLh//8i3qK/+Jk5PE63pMPQQNT2Zmi7LbveZM6Ez4MKNYjw1fCoqXC6r9cUXt23LyIAlkDs+a9Z11w0YoNdRtCyY6IIgrZmUFJZdu7aq6n//Gz48I0NVBYEQRbFaCVEUmw2yvH+sKrk+WCyEeDzHjwtCv34Wyy9+cezYmDG///2gQZI0ePCiRU5nTk737oEApbW1HKcoDgfLwqRClBqNfj/DBP8VRZBQOpCgw8yjoOaQ+RptxG7hws2bx4xp35qujdPrVYkcykeCkl6q6bED/SAIZ868/jpqeiiqKgi1teHWclxWVvSPVkHNp05dtWr69Gef/eCD776DW1xYC5MKhZZNRBAEiQ1VJYTjGIZSrxeSSVTVYCgo2L798cc7dbLZDIbaWreb57OzCSGEZYPJLQwD091HUzQZMBhkmRCWlaSUFEIUxWxWFJb1+aA1VWUYv19VWbampq6ustLtHj/+t789fXrUqGefLSwkZPTo55+nNCcnJYXS1FSDgVJFkSRKZdlkkmVKeV5RKGUYSglRFEoJEcWW7mOk9dKBBH327L/+9aOPoEYETIACZd2ibad9a3piKpH/UEmD81PGq6SCcPLk889DUkdwsnqoQx9/7nXb1nRZdjgOHQq/tqkpsgGggFbNz51zOm02WA63uKDpoWUTYcbQyOcNbW1gHL317CEmt3RMIN4sywxjt/v9JlNGBiH19d9807u30Xj8OMNQ2tSkqjBsUq8tKgohLMvzpaUsy7LV1QwTCGRlpaTIssPBcYKQnX3iRCAwd+411zz5JM8XF3fr9vzzHo/dbjIRAlXNEUQfOpCgQ10IGJQGS+DRfPI1HSLKsCSeKHVyNF2/lpMxsynDWCzdu+s3RLKtajo8W4A2tcthCayNpJ3qarfbYglVcy2hmr59+7Jld91VUrJy5e9+19Cwfv1DDzU0fPzxgw9ifB1BkMjhOFWF4Z5GIyGS5HKlph479uqrKSmi2NQUCDAMDEzXL5XFYMjMTE8nhOfz8wVBUfLyJInnLZZrrvntb6uqcnN///va2uuue/llg+HChV69Hn9cUUwmEHen02JxuYzGlu4zpP3QgQQdgBoRP3w0H5+mb9lSUtK1a+SfkuX6+l279IpShyZ76BVFbruarnclk7ao6dDmrl0zZ0LLwddI65qDms+fv2HDhAnh1FwLaPqiRW+9tW2b1Woy8TxUIoa1IO6QZqZHjyEdBYydd2QgFYQQRZEkk0mWq6qqqz/4YP78+vrGRpPJ62WY9HRKKdUvUWTfvjNnTp584olnnjl69J131qw5c8Zuz8/v1OnYsYoKQlR15MjnnvP7ZblTJ7vd7//uO1WV5exsSVKU3Fyv12rVY9pEBAE6nKAD2pgfLIlnoBtUgI5W0/XVX22yh75RZNT0RO9zotuHG0J4jeT9WjXfsaO8PJqY9969xcUXLoRb27Nnly4tM0VI7GCiS+vfK6S9IsuS1K0bIRzndhNSWnrunNFosXz+Oc+nprpcFoskBQIsqygMw/McV1oafGXZsjKeZ9nycp5XlOpqi8Vg8HgURVUFISUlIyMzk5CUlOrqpqZAwGB45pklS0pKnn76+edra/Pz8/MnTXrood//vqDgwQfvvbd37xkzZs369FOjcdy4++7z+x2OigpCZJlSp5PnKaWUYRwOShmmoYHSQAAj6Ih+dFBBBy6v6bEOdANNX7/+1KkePSL/lL76mzg9RU1P9D43377FctVV77wD+8+ymZljxsCrHlu8SEmJw2G3x6bmQGOj2+33h1/rcvl8+u4zgiDtFYZhGKeTEJ73+fz+1NT8/FOnfL78fJaVZas1mC9OiM8ny7LcubMsS1JenixLUo8esiyK/fo1NWVleb2ynJWVm1tb29Q0adLEiWPG7Nt3/Pi3344da7EwTJ8+zzzz17+OHv3YY3/4g9EoijU1u3alpppMPXu63YR4PKdPGwy/+EVjI6VpaSxLKaWUqqrHw/OK4vW2dA8h7ZkOLehA8wPdom3tzjvXr580KTZNhwoqWv2NTShR0xPdD8nXdI7Lyho71mYbP37rVjgKeNWKezzba2rKyvrlL02m0aPXrz92zOGI5urVAiM9YOIh7XKHw+32+7UjQNoWmGiBA0OR5ENpIJCdTUggYLMRwjBXXHHqVE1NYeGOHWVlubmDB8+YUVIyePCNN1ZVjRo1dWp19ciR06aVl2/Y8PXXNlt9PcOMHm00Umq1ut1NTWVlGRmZmV99tXbt+vVXXjloUP/+J06YTCy7b5/H43KdOMHzDBMIpKZaLBkZPp+iHDr0n/+sX2+1nj2bnl5YSAjHWa2KIoper6oSwjCBAMv+WOIfgsQDCvr/JxGavnnz2bPdukX+KVE8e3b5cm1Nktas6XrXTkFNb759t/v0aYYxGC6tmwviDtuNbRsQNT940OOZOLFfv4KC7t03b16y5Pbb46m+AhMP9ep1xx3//OfkyQ8//N//9ux5++3//CfOEhotmFKCdGRUleerqwnhuJKSzMycHL9/5Mhhw3Jzx44dOtTvP3p09+7x4w8d2rFjwoSjRzdsmDOnuPjzz2+7berUwkKjsVs3g+HQIYOhoaFHj/R0Uezb12bzeLKz7XaPJyPDanU4Ro40GPz+bt2gDowoGo1OpyQpSqdOimI219f/9a9PP334MCGpqWfOEEKIKDKMqioKIZQajYSwbCLnaUYQFPRL0FfTf/rTjz66/vp9+y5c6Nw58k/pK5ShUwUFZTpeElM7BTX98u2rqt9fVRXuHaETEkUCqPn993/++bhxM2c++WRREcwPMHx43765ufFr+tmzlZUOx5YtBw6Uljaf+oIgWjB2jgCCYDLxfEaG05meXl8vihzXqZPTeeYMpbKclaWqkmSzgcb7fCkp1dVut8FQW8tx6ekM4/criqJAOx5PIOBwCILRWF/vdtts5865XGlpBw74fCZTXZ2iKEpaGqV+f0GBwUBIXZ3J5HLl5NTUmM3duhHidvM8papKiCSxrKJQqqo+H6Wi+GND7REkHlDQL4O+mj5p0sqVM2a0rKZrpwqCmKte+pgY8U2spus7s2mi9xlQFK/3/Plwa6GyfuStud2iyPNPP71r17Bh2lxzSEHRV9PbEx1THDGKj3QcoKa6IDCM1UppWlpODmS5I0jyQUEPS/vS9HBDD6+++v334++rxGm6z3f06KJFIKB6KW/ozKZ6PVVI5K3FiRPPPQe3Ftrl0OeQHBVJO6DmDzywefOYMatXFxf36hX6HtD0LVv27y8pAU0vLV216r77VHXr1kWLzpx5773f/hYrmicTVGQEIYRSSmVZlmWZYRiGCWsvsBaGczIaIt+S38+yZrPJZLdnZREiyzjfJ9ISoKD/CK1H0y+dg7N//0ceif5oLuqjoghCbS3HZWRcdZXJNHjw88/H31eJ0PTQGVhBeQ2Gnj0XLIh1Ty8/BLN1F0yUJKfT69279667nM6NG3v2hFfo80g+H4maa5k9+4knPvrI4/H7AwG73WoNlg+DUonwLeiYkfWOGUdPDti3SHhYlmVB0BO7HVUNBCjleVmmlOMIgbxzBEk2KOgRkQhNP3myvj4tLfJP6Sd8kuR0ut27dt16qyw7nd99ZzB07frTn7bmpJdQTYdbFJ7v1m3OnFj3tK3WNY+WaNUcgKxxmHIodC18CzCOnkySH0fHyD3SsnBcIOB0NjQYjXl5RmMgUFJSWLhw4e7dikKIy8UwlPI8IZSazTyvKDzPcaoKSs1xskwppYEAw3CcJFHKcZQyDM9Tqijhk1ZUlVJJ6tRJFMvLRbG8/NQpQng+ml9qBNELFPQo0FfTr78+Wk3XV/j8/ooKr3f//t/8Rt8EkmDrydB0s3nQoKefToSmWyzXXPPRR9AbRmO/fn/8Y6x73pKaHpuaRw4O/UT0AmPnyOVRFEJUlRBBUBSb7eTJEyeamoxGu71LF4ZR1R/7tDbFRZv0Ev4Tqmo0KgrLiqLF4nafPEmIyZSS0tK9gHREUNCjRi9NdzgEwWAATY8m6UVP4VNVn+/8+dAEEv00/cSJ557TJueAUsfTZqI1PZj8k5ZWWAi9YTT26nXvvcEbjHjbT46mC4LFUljIsmPH7thx5owsxzqlkXYaLy0wkBSqnidi/1s/KJQIkmigAGIwyURVbTZCunQZOrSx0eVSVZ6/WKdFz20aDIpCqSz/9rfTp+flEeJyBQIt3RNIRwQFPUb01XSYhTQ2TY8/Mztcnrce+vhDMeX53Nxp0+JvOXGazjBGY6dOoevgBiO++Tt/fJbQ+HqbECgoxvO7dzudkydnZ2dlde4cz3MeuM5HjLj33rfegqsd6pq33SmH2jrJSTvB5BakNaAohPA8pZQKAqUMEwhQ2rPntdd26mS3d+4MsXBZ5jiDQVVZVvvKsvA3IVCFBVJfCGEYQlQ1fIqLIBiNDQ02m8+XmfnHPz7wQK9emZkm0+TJqkqp2ayqlDLMxVdoH0ESAwp6XCRC048dq629dDKa8PxQ0yEz22b7yU/27bPbp007e9ZmGz++qIjjcnKmTWu+rXCaHkzwiIdExY8To+mJRhut9/kqKmCIavyVZEDNX3tt//6BA2fOXLasoQFm9Iw/HQsi5XC1Q13zlu5DpP2AzyKQaDlypLxcEGSZ49xujlMUiLPrhaLA8FCHo66urEyWa2r27IGho4QEFR9ecfAokkhQ0HVAX02//fa1aydPrqhwuazWSD51qaSqqqpq55uEKYTM5kGDnnoqkhhtqPJCgoceyts2NB3y5i+3Fa+3rAz2PL5+IIQQeJLAMGZzXh7ss99/4kSstXScTkEwGEDNn3xy587hw2E5zOgJ6SihVybUYOmYlVj0AuUSQZLPkCE33/zKK6pqNNpsJpMshxf0aEsuMgyUVaTUbE5PNxhcri5dXK516zhOUdzuoJpTyjAsq6pYfhFJJCjougGa/uijb7yxdWs8mn7unNNps02dumrV9OnRaLrXW1YG/wyFroWZJiFJI7LWEheZbu2aDsNbBeHMmddfh7rjoOzQMux/PPsJ+wP7BvsZjKY7nceORdsaqPmLL+7ZU1ioVXMt2umH4Mrcs+fVV3/5y4aG9esfeghen3327rsnTIjnuJBkkrgUFExuQVo/KSnjxv3ud36/1ztmDMeZTD8+WDRSWFZVJUkUCbFYTCZZrq9PSSkv377dYlFVr5cQKLwI/w3G1BEkMaCg68xzz73//u7d4WKWkbcTm6Y3D0h8NO/vuJouCCdPPv881B0HZYcBtfHsW+LUfNmyvXt/7NYLNL28vLbW6WTZH8aQHnlk7txrrsGyibGBcfTYwH5DYsPlMhrz8zMzx459+GFCeN5uVxSWZVlCWJbjKCWE53meEJ6XZUKCJRchcQVeGYZSg0FVoeSitjijqtrthPB8ba0kWSwFBZ9/vmpVQYGqulyKQojVWlGRmup2m82CYLcnuiI70rFBQU8IoTHLxGt6cN7Nxx4LXQfx4NgUs61rOixp2dz0llVzLV27duoUPs1p1qzrrhswIPn9g7QGMHaOtB0UhWV5fty4hQsPHz5/PvF1ylX1xImXXyakvt5qFQSOg+zzpqaW7gekPYOCnkBCNX316scfv/XWaLN+QdPnzPnoo+uvr652uy2WcO8MBM6ff/99l2vbtuuuAwV0u3fuvOkmiAfHcyygklA2EZaAblJqNnfrFl8/BW8tFi26XA2ZeOuma29akq/p+qo58M47R4/27RutmgP79586VVnZ3NqOWjaxLdJ2lRpj50h8SJLX6/HwfP/+Y8f+5jerV0fymehrol9kw4Z//KOwMCuLUqvV7zeZ3G5C/H6sj44kEhT0hKPV9OA06UuWRD9N+pEjtbUZGfPnb9gwYULzmg6Rclmur9+1Kx4R1MIwdvuVV0KVGFgC4ht/4gegjXnLstt9+jRoenzVxwkJ3rRoNd1k6t//0UdNpsGD47tpiQRt3XeXa/PmoUPjOSOgNYsWFRWNGhVbCzCUubHR5fL5tMvh+lyzZvv24uJE90l7BaUTQZIDpYEAxxGiKFVVfv8VV/zyl126jB//8cdWq8nEcVA9HeYQpRQSWhjGYAgWWAwmtFwstkipJBFCafhBnwMGZGaePl1fv2sX/I40NhLS2BhpvTUEiQUU9CSh1fThw/v2zc2NTdN37Cgvz8kBTS8pcTj0qJzdPBADBlGGwaYguyC++m6LZVNTr7ySZW223r1hSbiaKtES1PTvvnvySUp53m43GLp2/elPExdNhzKX8LfTuXFjz57xtHb+fP/+O3YYDBwXvoJvJECMvFevO+549VWoaH6xxjnWNW+bxB9Hb7uReKTjIkkQBZckUVQUo3HChCee2Lq1rGzAAIuFkIoKRVFVntdra1lZFsvw4VVVX3559dXduilKWhoh6emYg44kEhT0pKKvpt9//+efjxunn6ZznN0OUx0FX3v1+u1vg6ksiVXz0FQQSM7Rb1twdHl5N98M/w/qn4hj0VfNx49/992bburaNTs7K6umZu3aBx6IX9MbG91uvx8qmmNai75gHL15sH8QPYCYN/xFqclUW+t0ZmTcccfrr1dXOxwWy/XXM4wsC4Je23M6Jam+PiVFFA8edDiKih5/nBBRrK9v6X5A2jMo6C1AIjS9psbjCZ/00jyQR56SMmHC9u2QxAKvRmPv3vfdp6qS5HZ7vQcO3HdfctQ8/iztS+E4ux2eAEChSVBzqM2i77Hoq+a33PLBB1OmHDxYXd2pU1rajBlLlsBy0HSjkefj03QEQZC2CaWyfHHCIJZNTTWbDx+uqvL7+/TJzBw16qWXAgGPp7par+0FAhbL99/7fLJ85ZWHD3/22ZVX8nxp6blzLd0PSHsGBb3F0FfTFy0qKrrqKrdbFKN/qAfZ3hAj1y6nlGVNJklqaPj2W0mqqtq4Ud8eQDUPxz33fPrpdddt3VpampenXa7V9Orqjz5CTUeCxJamkszkFoydI/oB6SuUKgohDCMIfr/ff/XVhFitdXVW68SJzzzz9tvbtwtCIODxKIogiKLDQSkh6ek8T6nXSwjLGgxQz5zjVJXnOU6Swv9barF4PF26EMJxlZVpaSZTevoNN8jyRx+pqt9/4QLLKgrDWCySpF/MHkFQ0FsYvTR99eri4l69Hnhg8+YxY2LT9HBQyjD6tQYkX82hjGPrV3OQmP/9r7g4mIUfSqimf/DB4sW33abvcSHxgDKKIMmF4yorCZFls5njMjN79Xrmma+/HjWqutpoHDzY5RIESTIaVbWpSRAojW1eEaj4Istud0PDkSMrVrz1Vs+eVuvu3cuXS5LRaDR6PEYjZqUj+oGC3ipoWU2X5aam8Frc/NpoSbyaExKsnaJVc21NdL1IhJpH/n6tpv/kJ8OHFxSgpiMI0jERRZ73eAiRZaOxqam29uRJh8NiGTRo1KgHHigtTUsbOHDePEWBSYt+WFhRW34xXPuKQqmisKwsm0xpaSZTaqrBIEmSVFa2adMtt2RmUlpRQQghlz6FRpB4QEFvRbSUpkP6CtQ4h9lGQZ1heqP4a6gDyVFzqJ7O87m506ZdquaS5HTqtRV91XzlyuPHw8fLmydU0/U6RqQtEnnKCia3IO0JKJpIqaIwDMtSWlNDCMsGAm43w9x668CB48f/6U+SRKnZTAghwQGm0QBty7LZzLKSZLNxnCRZLAYDy+7cWV+/ZcvKlYQIArSPIHqAgt7q0FfTX3jhm2+GDvV4AoEf03RRPHt2+XK3u6ho/Hio2N0W1Rzy6duKmn/++Zkz3bv/5jeffXbddbG14HB88snDD8PfWllHWgMopgiSHCiVJLMZ/qsoipKRAX8R0qlTba3X26/fiy/abFOnbt5stXJc586EsKyiqCohGRmSRCnLyjIhRmO49mWZUoYJBDhOEESR530+QeB5QVAUv99iqa/ftGniRELKylatUlVKDQZVZdlAQFUJgbrskU2HhCBa8KJppeil6TDf5Guv7d8/cKC+uemRgGoejt27y8tzcn72s7VrJ0+OrQVUc6T1g7coSMtiNvt8RqPLxXFlZYQMGrRsWZ8+M2du2gQDQg0GQpxOjgsE0tIkyWCIpWyiKObnp6Tw/MaNmzY9/XTXroQoCssSIsuZmYQYDA4HIZReOjEcgkQCCnqrRi9Nf/LJnTuHD4doutMpCAZDovcc1TwcBw9WV2dlTZny/vs33hhbC1o1T0+/6SZU89ZN8iW1+fQVnJYI6TgEAhwHuelZWYRkZKiqqo4b9/jjv/jFo4+eOmWx9O6tqoQwjNtNCKV+f7TtU8qyDgfLKgrLXnGFxXL4MCH79//xj+npkuTzERIIZGQEq80gSHSgoLcB9I2mv/jinj2FhXppOtRQZ9nMzDFjGMZuv/LK9qHmcBT6qnmvXq++escd48e/++7MmbG1EBo1V1VV1atPEQRB2heyzDCSRKksKwqlsux0lpe73Sz71Vc8/8QTDz74zjs9elgslJaXp6dbraNHG42iaDYbDIGA2cyyisJxDENIIBC+fY5zuZxOrzc93Wo1GhVFVd97j5DGxiNHFi+2WFjWZjOb/f7wLSBIOLiW3gEkUrSTsd9zz/Tpw4aBpj/88Ouvb9nCcQzDMGfPVlY6HPAarh3QdPj7iSeuvXbv3tj2h+NycqZNuzjP6KWzmbZ1NYfjgiXxq/kVV7zxxpw5dXVebzQ3VFowoQWJHxwYiiCAwWC1yvJ//rNjR0rK7Nm9ehUWXn11WlplpSTxvNt98X2UUqooPE9IpFnkHg/HZWQcO7Z69Zw5Y8c+/3xJicNBaXY2pYREH6FHOjIYQW9jgKbv33/qVGUlRNO3bVu69M47N29esuSOO/bvX758/vxZs667bsCA5tsBTf/3vw8f7t8/tj0xmwcNeuqpUDUHfL7jxxcvRjUvL3e5rNaKCqcztsq7qObthdaW6IIgHZnGRkFoampooHTq1JtvfvNNk4mQ3NzRoz0eVZWkujqXC2YhlWWGUZRoarPU1vJ8bu7AgT7fqlUOx86dS5cSEgjgBEZI9KCgt0kgah66PC3NZjOZli9/8MGpUyNpZ+HCzZvHjIlN00NnHtWiqoJQV6fX8WrVHApBJlrNfb6jRx97LJ42L1xwu63WgQOXL58zJ7YWtGretevs2f/4h179iSAI0pGRJEpTU1lWUSoqqqsF4eqrKR069MMPKTUY+vdnWaMxPV1VobRidPnj3btLUiDg8/G8yVRfv3HjhAldusjy1q0tfcRI2wMFvU0CCS3h1qanp6REc8cfm6aDKMe2NnKMxn79/vhHUHNIm/F6Dxy4775Eq3kgcP78++/H1mZ1tcdjsQwY8Prreqh5jx5z577yitvt84li/MeLtCwtFUfH5BYE0UKpqoqiojCMIFCakqIolA4d+rvf3XDDE0+cO9e9u83m9bpclPbo4fPZ7d99F3nLPh/LnjsnSZKUk5OerqpnzzY2HjlSVKSqspyerqpms9drsfj9KSmEyHJKSkv3BNJ6QUFvkzSfZX727IULjY3RthmtpoMoa0UcBBoEV1V9vvPn4zlGUGejsVeve+9NREa7NocelsSv5pBl3rfva6/NnRtbC1o179375z9/9VWHw+3GzEUEQZDE09hI6dChFRWimJlpNKpqQ4PR6PPl5ETegqIoisUiy1AH3edzuQ4dWr/+1782mVQV6rpYrbLMsoKgqizrcrX0ESOtFxT0NgkI+oIFS5du3NjY6HIFa6yCms+e/de/fvRRbC2Dpm/ZUlLStWvz7wRRhomNIFcbpjeKR3CBRNeBgWozkEMPS+JXcyhkCXVaYmshNNe8rq6pyeuN/3gRJDlg7Bxp65w/z3GjR48aNX9+SUlmJsc1NTEMIX36RN4CywYCGRmCwPM+nyzLstGYm+vx7NqlKJWVn31GiM+XmRkI8LzPRwjLYn10JDwo6G2YN97YsOHgwYyMmTOXLqV04sSnnurV6+c/f/XV/ftPnaqqiqfl22778MMbbohE0/UlOWputY4a9e67kEMfv5rDJFBLlnzzTWFhbC3gMNCOBoosgrROVNVi8fkqKhobCwpEURAUpaaG5xsaIm/BYJBlnpcklhUEl4tlMzKMRpOJUlEsLy8q4nmTyW6HoaeEqGqsxQOQjgAKOhKWX//6iy9mzjx/vlOnYKQ5cbRFNfd4AgGOe/TRbduuvjq2FlDNEQRBWhOqWl/PMEOH/uxntbUcx7Lp6QwTTbqm2200CoLVKoo8zzAs6/V6vYT4fH37UgoV1aurbTavNy2NEIMhGvVHOhpYBx25DDAFEtRZHziwb9/c3G++2bKlsvKKK0TxlVfia5vj7HYY9BmsA8MwBoPRWFDwq1+1FTUXBFlm2S5dXnrpF7+IrQWtmo8f/8AD774b/5EibQuIo7ePYoj4TABpL0iS2Ww2qyrHGQyKYjSKoiAEAhxHaXzt9ujRqxchp05ZrSxLCNRax0GiSHOgoCOXoFVzqLMOM5guWLB0qc+3YcPs2V26jBvXvfuFC7G1D6LMsqmpwcmSAFWVZUFo/WoeCCgKpZ07//3v8+bF1oJWzadMeeSRVasOHTp9GmruIgiCIC2J3y+KdjvHUWqz8byqer2EWCyESFJ87QoC1EIPVmCD4o3xaj/SnkFB79AMH963b04OSDlkrl9ezYMzmE6fvnr11Klffnn77Z98MmJEly41NZFvi2UzM8eMCVXzIIoiiq1ZzVWVEEqzspYu/dWvYmtBq+a33PLnP69Z8803331XURH/8SJIS4Gx89hoH09OgPZ0DXBcVpbZXFn56aeff26xmEx+v88nyyxLiCQZDPG0LIowINTvVxRCKJVlQhgGIumXm+wPQVDQOygwmdE990yfPmwYLJFlRVEUlmUYhglVcy2TJq1cOWNGtJre/MRGlPK8Hg/7EqHmp041NKSmjhz59ts//WlsLWCuORKO9pTogiBtBVUlxGgkRFUh9CKKhDBMIKAo9fWKMmZM797ffuv3u929e5vNomi1iqLBENnMGzab3282V1enptbXWyyCYLHYbJQajbt3V1babCw7cKAguN0mkywTIkk2W0v3BNJ6wUGiHY577pk+fehQrZoDoOZQqDGcmmsBTd+378KFzp0j2a4sNzUdPQpZ5qFrRbGsbNWqeI4rEWpeWtrUlJKCao4gCNKegDlCCTEaGxpg6j9CRLFPH4Ohvv7gwf/856mnunc3mTyebt1qajIyzpyJvGVRZFlF4ThZNpkIcTjOnw8ERJHjCMnJGThQlkWRUpZVVaji0tL9gLRmUNA7HD175uampenVWuSaDlMXQZZ5IFBZuXGjJNXV7dwpCGfOvP6633/ixHPPxbYPBkPfvg89ZLVeffXKlXqpeUWFy2W1Dhny5puzZ8fWAqo50r5pT4kNSEeDYSj1eAhRFLudYQIBvz893e8/cOD++6+5prSUZSWprEySeN7vNxoDgWhm5pZljvN6jUZRTEmhVJYlqbqaYQYOTEnp23fsWEIotdk4TlEUhRC4SUCQy4MXR4djy5b9+0tKwq2NrYY61E0/ebK+/sfUH7LMfb6DB++7z+vdu/euuwTh5MnnnydEkiJ7gKgF1Nxk6t37d7+jlONsNr//5MkXXohfzadOXbVq+vTYWtCq+aJFb71VVBRbO0jHAWUXQZKJLHOc202I39+9e06Ooshy374GwyefPPfcHXdwXE5Or1433eRw2O3nzuXm1tVFM1ERqD/LyrLRaDDY7Wlpo0ffeef//udySZLFQoggKAoIOg4QRZoHBb3DsWXLgQOlpc89t2rV119rl+/ff+pUZeWjj7755tat0bbpcAiCwXD99StXzpjx3XcOR48eiT4KqJsOag5LJKmhYe9eUTxz5rXXYmtTq+bnzjmd0WcHatX82WdXrvz663/+c926ffsS3RsIgiAdGVXluEBAVRlGllWVUkgf4TiWFcXs7IvvcTrhnYQYDPn5Fosg7Nw5ciTP//e/mzY99lh2ttsty3a7JNXVVVaazYFAdrbbnZLicFBKCM+rqqKwLLQUfL3cnuTkyDIhZ84Q0r37NddUV3s8ViulHMdxlBoMDQ1eL89j7Bz5MXCQaAfl0UfffHPbtueeW7Vq925Y0tjodvv98bRJKc/b7SbTyJHvvedyyfLevSkpZ88++GD8ews6zjAWS/fulJpM2dkGQ17eLbfAWlBzr/ebb+bMia19fdUcpPzZZ394C4QgzdNWBoxivB9pbVgsgqAoUBlFlillGEmilOdV1Wr99luW9ft79yZEEAYMoJRhnM709BMntm8/fvyDD7p2zcoymbp1q6mprpYks5mQ+NTZYPB6RVGSLJa0tJ49r7pq48aUlNGjX3jB7SbE623pfkLaEijoHZr4pRzQVk8vLOzTJzeXEEJuvvnbb0+cWLeuXz+D4auvYmvZZLryyqeegomNQtfC0FK//9ixRYtia19fNU9Pv+mmJUugLgCCIAiSHLxeiyU/nxC/3+PhOKNRlgmpqzt3TpZTUgYOzMpimOLi+vp9+/70J6/3u+8eeKChoapq3z6j0eVSVb/f5era1WLh+XPnYPBmKFRDuH0QRVEURZ8vN5fjhg279trS0upqjsvMJMRsPn2aUlHs0qWl+wlpS6CgI3EROrFRY6PL5fPNnv3EEx99tG/f8eP5+Vu3/vznqam9eqWnX65+SzgoNZu7dQun5gAMMI1tz6ur3W6LZcGCTz8dPz5+Nc/MnDnzxRdRzZH2DcbOkdYJyzY1nT4tyx5PTY0knTixY8fdd9933+zZy5bNnVtcbDAYDBcuEOL3T5woy99/X1WVmUnpzJkXLuTk7N9vMEhSINC5c01NXp7fbzRGM78HoCiKoig2m81ms+XmjhpVWztw4NSpgwcHAl7vrbcGAn5/164uF8PgrBdINKCgI1EAFWCgUOOJE2Vl9fX33XfLLSNGaNV88uQ//GHlyouDTQ2GW25Zs2bKlM8+mzt3w4a8vJQUjyeSbUFCS/PvgZotUB8m8qMANZ8/f8OGCRN27Cgvz8mJth+0at658y23/P3vsqwoKOeIHrSVRBcE0QujUZZl2e/nOLOZEEpZlhBKVbVTJ5ZtbJSk2tqTJxsbjx3bupUQSXK5XnnlX/9asGDBgrvuuuGGqqozZ/buzcoyGvv0qa2tqjIYMjIsltmzCRGEmhqY28PvF4TMTEoJCQQISU2VZVmm9Ny5zEyXy25nGEUJBHw+k6mhgRCGuZhZLsuEqCrDqCrLShIUZxRFhqFUEAihVJJYVpKcTlHMzc3M7N//xhtPnhw7dtasG27YuHHv3qYmQnr2hGOpraUUfyGQ6EBBRyICpHz58gcfnDYtdO3l1TwIxKchjSRyTZfl+vpduxTF6y0rC5V1WB7tzKMlJQ6H3X7//Z9/Pm5c/Gq+bdvBg6WloihJspys84AgCNLe8PuNRqOR4/x+nrdYHI6tW53O06c3bjxy5OTJTZsMBperoCAjw2QaM4YQj6emhhCG6daNkO+/Lynp2pXjOnf2ep3OY8e6drXbDQZFEcVAgGU5zm53u1UVZuuMD1lmWb+f4whxOmWZYRRFkijlOErT0oYOvfHGhQsbGoYPnzJl+vR169avP3/eaBw5cvp0QVAUKNEIs4giSDTgOGIkIh55ZM6c0aPDrYXBps2XaNRqOmR+R7Ld0Lrp8Dcsj3z/9VXzb7757ruKiltuefzxDz5IXJ8jHZnWlkzS2vYHaeuoqqqqKsMwDMOkpvJ8Y2NurtO5alVx8Rtv3HCDqhYXv/RSTk4gcPy41Wo2BwL19QyTmlpZabP16+dymUzl5S4Xx1244HTK8rlzJhMhBoMsi6KiyLKiEOL3K0ogEG7rkE0OW9f+He79RqPVKkmCQKnBcOxYbW1W1sCBt91WXj5//iuvmEwFBaNGEbJu3WefHTpE6fDhU6eKoiSZTJD80tI9jbRVMIKORETPnl26pKeHW3v2bGWlwxFJO9FG0yF9Beqmx7bn8au5y/Xpp3/4AySxHDp0+nR19ZQpjzwS37ynCIIgHRtZlmVZdjgcDodjw4Y5cwhhmPx8QszmtLRTp86f5/muXVNSFMVkCgQcjsxMSaquJkRRPB6Ph5AePXheUUSR5wMBQZAklhVFSSIkEJBlhvF4ZDk4q6ce+xoIeL1du7700t//XlR06pSi9Ow5fPiNN951V3a23b59+xdffPjhNdcQ0qfPmDEGg6KcP0+pogQC8Gw1EMCSikgsoKAjEQHTG/3kJ8OHFxSEroUa6pG3BpoOAzTfemv69G3bsrNtNr1LUMWj5jD4taFh/fqHHoIlvXv//OevvnrmzIULjY369y+CtFYwdo7ohapSyjCEUGo02u1ms8fjdO7Z8/nnhKSl3X67qopit26y7HZXV/fsmZqqKJKkKBaLILAsz3McpVlZhChKWhrDEOL1Koosi6IoUhoISBLDCAJIP8vKsqJwnCxzHNRcURRKVVVVKaVUUQiRJJstEHA4FEVV/X4YP6QoisKyHk96enl5XV1tbU7Oa6+9/HJp6dmzp0516mQw9O0bCMhyfn52dnl5WVl5+bff7tmzbVtWVpcuP/tZXV3Pnvn5hKhqICCKlFoshLAsHDNsu6V7HmmLUElav57ntYtuuOHDD++668svy8oup2JIxwSEFXLQZ80aP37AgLNnL1xobIR66mvWbN9eXBxby/Pnjx3L808+OWOGz2e11tb+5z/x763bLYo8/8ADmzePGbN6dXFxr17RHqm2Ls2IEffe+/bb0d6EIAiCIFpgMKggMAxkZhPC84oiCIHA8eOrVn366YoVf/7z2LG9e6uq3Z6WxvN+v9/v9aqqoogix0Gdc0WRJEkiRBAolWVRpFSWAwFFgemHZFmWGebicvisoqiqKKoqIZKkKCD+kmQ0Ohwcx7KyLElpaVOmjB37wgs9ew4fPmCA1ZqT4/MZjZmZsuzzybIofvrp119XV4siy86cmZ6ekTF6dGMjz/fsSQjPl5YSwrIQLW9qolSWg0fXtlDVi7cVSDKZNKl795KSL7647bZ33tEuR0FHWozhw/v2zcnZvPmFF26/PT09JcVsLi5ev/7GG/PyOC5W3ddXzd94Y8OGAwcWLFi69LPPWrq3EARB2jaUQmWUUGRZUbKyCJHl2to9e156acyYiRNzc9eu/ec/n36aEJ/P6bTZOE5VzeaMjNRUVfV46uoURRT9fkJkWRAEgWHKysxms9lsbmhoaGhogKrkZrMkjRixe/e+fUeO/OEPixe//bbXK8uEXHnlwIFpaTk5PXv26tXQ4POJoiCoKqVud1WV11tUtGfP2bOEZGcPGZKR0b//6NFuN8d17SqKXq/XSynPX2pN7QMU9JYinKBjigvSAoSq+YIFS5du3FhcfOhQz54vvzxlSkVFQUFamtMZeZuo5giCIG0RVbXb/f7a2kAgJyctbcaMN97YvdvprKkpLLzvvtOnL1w4cmTjRkJqa/fvp9RqleXu3VNTrdbMzLQ0m81mM5kMBp5PSXE6s7KysrKyJEmSJMnv9/v9/u+/Lytbv/7UqeJipxNuEAgxmQgpKfn++6ysnByL5YorKOX5jAyPx+9XVadTUYxGk2natLw8v9/vV5SGBllmGIaRJKeTEJZFhUWSBQo6klTCqfkbb2zYcPAgIYTk5EDW+Pvv33rrpk02m8EQfiQ+gGqOIAjSdjEaHY7MTEVhGLfb5ZKkvXtVlWF8vgsXZLlzZ0L69p02jWV79Jg1i+NkmefPnbNaa2ouXGBZSllWVSUJSh8S0tBACAg6x3EcxwUCqakFBYSMGkVpUNABjisrq6pSVY4jRBB4nhBKOY4Qk0mSAgGn0+fjOEr9foj6SxKlPA+1Xlq6t5COAgo6kkCeffbuuydMgKGlFovRyPPdu2dnp6ZarSYTz/9QzYPAgE4Q7r//ffLkXbvCaXq0ag63B7NmXXfdgAF+vyBI0syZY8f261dY2Lt3dvaaNUVFxcWo5giCIMlEEIxGqBTOMITIcl4eIZJkNLIsIW63LLOszyfLZrPDARnmhMhyRkYgIAiCAHnpiiLLnToF25NlWQ4EKKWUEIPh/HlKCVEUhoFhqqqqKJIky2lphFAqCCxLCMTXAwFFUdX09KDuB4e0qioMLkWQZIKCjiQEUPNHHpk795prQtf+/e8ffLBnT6iaa9EKd6imR6vmIOWrV//lL7feql0uSbKsKFA8EW4YWrrnEARBOhYX9Re02OOBV1hKqaoyDCGSpB18KYpQzVxVCeE4SjnuYn0t7jJmA8oN7bEspYQEy/sqCiE8T4iq8jwhDCMIwUg7VF9RVUxrQVoCFHQkIUC6SLi1ohisEPtjhGo6REVeeOGbb4YOjTyhBWZCDV3OcSzLMB9/vHPnyZONjW6339/SPYcgCNI+wWGICBI5KOhIQmhsdLn0k12tiHfpkpLi9S5btnfvoEF6tW8yGY0cfhcQBEEQBGkV4HAHJCHAUMvQ5Y2NLpfP99xzq1bt3h1tm6Dpsal581XMYRqmlu4zBEEQBEEQQjCCjiSILVsOHCgt7dXrjjv++U9IL4GYOuSdJz+ZBCZUgr+16TewP7C3Ld1nCIIgCIIghKCgIwnl7NnKSodDK8ctS+vZEwRBEARBkHBgiguCIAiCIAiCtCJQ0BEEQRAEQRCkFYGCjiAIgiAIgiCtCBR0BEEQBEEQBGlFoKAjCIIgCIIgSCsCq7ggCNLGaGp6+OG33mr+Pdu2nTuXl1da6nCkpCxbtnfv4MGlpU1NKSnxtBlKauqSJfPna5f06JGa6nLNmzd48MmTN9/cr19JSUFBWprTCWtLShwOu72o6Ny5Ll0cDr/faFy8eMeOESMi36vQLWoZP7579wsXYLvjx+fnX7ig3Tpw8GBVVVZWUdG5c3l5hw5VV2dmrlt36lRBQSRbh/0vLPzXv2bN0mufI0HbnxMm5OdXVGj3Z926kycLCuAo4Iji2VYoaWlGoygeOnT33atXp6ebTIIAyxsb/X6jsbDwzTdnz3Y4BMFg0LdPwn0qtms1kq3Dkc6bN2TIiRNw/Wh7G4BvFvT5ihVHjvTrF+1RwBU4fvx7782cGcneFhX9/Ocffzx0aE5OXV3kRxH5+UpEf0Z7xpPT88n8/ur770AivoOhQGvw77P2X5XY9jl+UNARBGmHBH/e8vMJ+eUvhww5ceLf/z58uH//xYu/+mrkyOb/KY+NwsLs7Pr6detmzfrsM+1PiBbQZa00Ny/okQA/XStW3HTT1q2hP+qhgOhodSfyH07Y84ULr7rqyBG47dG3D0NZvHjcuH37Hnhg1KjDh8PtD6yF1/hvBkKBG4PQcwpLYG0kwtSagat3xYoZM7ZuDb2p0wLXGLzOmzd48IkTCxdu3jx2bOS3RnDtwc1kUVFZWZcu4d4J7wlV8+ZpW+crmT2f/O+vXiTnnEJrt9zSr19JCbz+4hfr10+c2FKajoKOIEibR6tl2hg2RKTgn13Q9LQ0k0kQ5s375JOJEyNvMxIWLrzqqsOHtT8hf/nLV1+NHKn9IQTh6NEjLc3lgh+V+I89VM0hQgnb1f60gAqkpRmNglBYmJNTV3fzzX37Rr8P8AO/YsXhw/37J+JWR0uoms+cuXr11KkgdnBEhYXZ2XV1evVnKCBD8DfEIOFv0B1Ym0zhC3dlxhOzXLZs8uSdO7WCCDe02qdP0NuLF1977bffwvUG6gyfjTwiDixcOGrUkSPNCzq8J9r+ifZ8JaI/I6clej5531+9SMR3UHs2IcwBPaP9N2fx4muv3bevpQQdc9ARBGlXwE8aRKbh0af2H3SIi4C+67tdaFm7JDRGBToCPyQ337xmzZQp8WwRjiI05ePmm9esmTo19EcFIm2wD7Bv0f60w0N2uAmBHzN9+zAUeOgcbi0ckV79GQqIkTaCC9vSqgCshXcmujcSAVxF2mNcu/bkyYKChQs3bx4zRpsYBr0N/QxXgrYHIv9OwVUK1y3csoa+B5bDe7Tf3+ZpW+cr+T2f/O9v/CTnnMKNSujzzOafaSQaFHQEQdot8M9uqCiPH//jqSDxA+kZiVOB0KOAI01cVGzZsj17gj0JTycg8pSIbQGQD6pdAk8MkiNY2rhdcOuHD/fvD6/Nv7OtEPrkYdmyvXuHDGn+UytWHD58abQy8icYkN0Lf4eLkWuXa9/fPG3rfCW/55P//Y2fZJ5T+BdbuyTym8NEgIKOIEg7J/QHPhK9gwfc4V5D36+NbAHwqHT79jvvXLfu0KFf/3rNGoha6SWXoTH7yFUmNiD6DnG+RMfhoOXQY4TtQq5/aE9GcqYiAcRFqz5w1HDzA6+wBNbCO1u/7oQSOm4hkpxmGGTcfDvh0N4ww6e05xH+huXw/CSSbOm2eL6S3/PJ/P7GT6LPaei/FdrkFrj2IkmGTBwo6AiCtHNCI8qJeHAJD6D//vc9ey4XA4MtPvHEtdd++61W2fWNBEdSxyDyW45wwEBb+DsRcTjIjIe+giWQVa9Nd9Fqerg0idBbpmj24YeD0kJvfrRLtIPV9OqH1kw8T2ngs5BpDUu0sU/t39DDkWyr45yv+J+PJfr7qxcte04v3sAcPtxS/YOCjiBIOweGjUb7KRhCFO413Kcgi3HIkDffnD0bZB1iPKG51BcrKlyuPklsJOeHBLJjQbDgZwyGr+nVfmhUD6pVQG59qKZ//PHs2Z99FpqJG5oeEzlaTYQthub0wxLt/rSGxIm2wooVR44EBR0GcMONFvwNyyOvNILnK3IS/f3Vi0Sf09B/1a+77t13b75ZG5WHJ3gt9ZwBBR1BkHZOaEwlnthqJGgHqsJD0vHj33135szQ7YamcEQOxJWbP1ItkdxgRA7IE/w0glTFdiMUSmhZPXj0f3Go3KWaDrz00vXX79wJf8Pa0CzVSAgdlAYSE+7JgzbC13oGIEZO6FUU7omEltD6P9F+p+Bsaj8FN1rwN+hj83MXAG33fLVUzwOJ+/7GT0udU7gmFy7ctGnsWO1yeM6Q/H5AQUcQpN2iLZ6lXZ7oXO1QQDXmzVu/Xr+MxtBsVDjSZMbRtRKcuDiTVlzgRxTq84QqDhBPtfv4o6qhLYQONWtexUIlLNyRxs+hQ9XVl7YciY7MmzdkiB7PK8J9E+MZGBotLRVHb9meT+b3N1pa2zkNN69FokFBRxCkXRGck2/w4JMni4ruvPPjj7X/vEK0KRFVq2G+Q6gDEKpf2pkCtcu1j1OjBWJgWnWDtBk4auiB0KiYvvHC0Dhc/G1qs5MBeAQfeiyhtyiwJzCDbLTbDR2UBkDCUrhkJ1irfX/oYLVQ3Qx3RHDlhKpS6JHqhfYMwhJ4qgNXsnYP4W+YUie0uGdszyvgm6i9gYFvaPP10RN9vpJDy/Z86D7o9f2Nh5Y9p9DPy5ZdfBYHJO72uHlwoiIEQdo8kQxzhH9kI49hR9KmNl1EO0NnuJkvtVysUPFjhdXCARFiSPkA4YOfWNB0bcpH4oB9AEWI5KgjAeLfMP2QtlcPH7777tWrod/CxbS0Wem///2mTWPHRn4zFjooDa6Z5hMtYC28E/YzdHZD0CCYHEo70QwcUfN7BcIa/4yzze8/XEXa+Sy187OG+6y20kU8gxebn3w++ecrEf3cOns+Ed/fcETyLyp8Z5NzTiMfHN9Ss65iBB1BkHYI/GMNsViYrhkm5UlcjXD4aYGIeLisUIh4wV5BVnrk03SHA44IJjeBWTah/XAVfGE57CfMdRoaf4oW0Ee9agbDEcH5gl7V9qf2xxuOAs5vuKz0yKdxuVzF5YsDGZsn9J3a1i7eSk2Zor1OQvcZlsBaeGciJmAKBa5DuCbhqgh3DcM3CwZAQ6JR/NdwbCTufCWT1tDz+n5/46H1nFP4DsKw0ZaaSZRK0vr1PK9ddMMNH354111ffllW1hI7hCAIgiAIgiAdgUmTuncvKfnii9tue+cd7XKMoCMIgiAIgiBIKwIFHUEQBEEQBEFaESjoCIIgCIIgCNKKQEFHEARBEARBkFYECjqCIAiCIAiCtCJQ0BEEQRAEQRCkFYGCjiAIgiAIgiCtCBR0BEEQBEEQBGlFoKAjCIIgCIIgSCsCBR1BEARBEARBWhEo6AiCIAiCIAjSiuBCF/30p336HD8+aVL37mfPtvTuIQiCIAiCIEj7JD3daPT5QpdTSVq/nudbevcQBEEQBEEQBCEEU1wQBEEQBEEQpFWBgo4gCIIgCIIgrYj/B6WcjiTomrJxAAAAJXRFWHRkYXRlOmNyZWF0ZQAyMDEyLTA3LTExVDE1OjA0OjE2LTA3OjAwWuZbyQAAACV0RVh0ZGF0ZTptb2RpZnkAMjAxMi0wNy0xMVQxNTowNDoxNi0wNzowMCu743UAAAAgdEVYdHBkZjpIaVJlc0JvdW5kaW5nQm94ADQ5NngxNTUrMCswL/j8PwAAABR0RVh0cGRmOlZlcnNpb24AUERGLTEuNCAcRzp4AAAAAElFTkSuQmCC" alt="VLSIDA"></a><a href="https://vlsida.github.io/OpenRAM"><img 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Am9buaRvKQTKBcsdGxwFPe+gbZ0Cmdi7yP44ZtCwFTyHK3LEFfjvJI++83IPb8YlgLlqh4aQQsCgz+sHuliDh4as/OOfodR0XkhLK03KRec8SPkQhiYE2Whnx5IhIGBf6dPnHguOvR85HoG/j5103f7pwfo5icO6lXHol/d3ffOfuk4SEFS1tq39/WEZHDYCZj72ISt85KPEX9kUS6Z8isC7vlq0prjbulQfzQ49cExuzsGmrdlCOE/S0vEBQq2QtYH+cqoAIDSc364MZ9YPxReyOFInB28sXfG4xO2xoQKLPB1kk23xTsKKD+3eeDfNw/kMdXliDUx5+PDy8XXW6+VV/t9k9EV0SR00+iYk/+buzo6tFwtXfSzJjP6zi8nl1S12nevTQFdoWTudkm0AkfBlENG4w/EnrVvtVVCiYCSwCgamID2Av3OdCPG5fAzEDVw2WA0ZEjcOOnfpsGx5O8XpCawiCHB6SsPKqCM+5Rb0Ak2u7DhXvJ3/mO0yuQXA09fb/kIoSFEP3/hID2IRN3yEVFF2O+sQ0hoqsslxAnlJasRYUecD7OPchEJvApBat9D6z5L9geepmkoFB8as+vOAfi7lC/UlFoQ8duVo9dnRbmentGxJ0dE5bPDpQdMRWLBwQuIXSshhAkFO4GLCCoISkI6/Ula0hUVJu56At3/lCl9bMK2Hw85oHySfP0PFLWHIMY0vjo5E9ObBXjzic7FzmGrY2DlPYMP3Dtsn0Fr4DZE20fgvjvDuKXP4eemblQidO4OyD6/dQB0+fcGpN/ZPz3c3yyEB4uXH4v94+oReF/c6Vadw3cGk+KHg1P5C0foHDjGSaM+5Z+PrR327x39jA5nJ2U+OXlrt/AyHp/ff1FFwHNbBqGp5YRg32oAfUZiFvsSdf6O3E7f+XJaTpnzBFPuD1Q/s+0AHeocHQgUB9JsbFKsWsAUjjv5qvNci9bPA+CWZGon94nlK4AYI/m8wErXjZNhM5AkAp0d+0i4EKQ2akJuLcBdL9nBsP0xtBU6CxCrudE3cMquMw7Kpt38Mlzf1vZT7k5X9CN3McmaRNSSIusl0N9LhJXqnzwR1BMLiTN5pW3Xl/O/cYc+OGbXhLhcfgPMHLvXN/b2xA2FFeb+Y8eGlvftdLpLSAWmXJ+Op9FNW1OzvA+cZoShgzsf7k8uqXIUzev+za68M0P9zgFhd/Q7aOAUxvh9y8YQMdQtovxcrSm7LKTRPA1RIRVf3LS4ZwfC6+T3RXQSOtTfrbRwmC5ndVZS1suzV7ezRDBxr4dXj3hnX8/7R+3+2dD9hjNTqJj8DmArbJvL/s77EBIPQL+p9xFF3fDFwwLoFGTeL8LUP7NpEJBtXINH4dHx2xLRt+jUSl550D+3DHzFsjLd1Pvw01O2GNvN3PLgO76YCqy7Px7XZ7YRoGNuow3HNlehNACc4J2mtUsSdkI5RSX34VlzPI7xEJASmNuQHpAbAB96FRJpAdA0Ak1plafEGGeFwL9KAwPgSfa8IZANmHr5Cd0Bt1NdqTEGMbT1JiB74Zv12nD+OgHJwyOwPwiJFtwnAWSHZHkusei9zY924cfbFnecnZT1r5nrlJMT2MXCwnBTYommDifMv/rq5GMPjNzdNbzcx1RnzcDQFUQBsR4ErCOGaWrPnvOBvN+M3KvbsLLulp7zfWVnv79uGAJfDDuB1sidX9hrc1bf0PuoYjOgqVHL3DJ/RuHZxlNe4ztZctvC9gFV6p0C6D/7ZgKKppmJWY9O2A4iKyzmNSFbxN367ObBRBq7+dbY2/1yeAqWvrLKAXTYORBZUeF8bd7Y04sACMPX+qzOPin3LJ9uzOrChtLYE+AK+vC6Zf07FamhQv58fTj+J4snsCNxczyuT2sjQMdqPrJCZII21i6wDjcdFi3IC6BDbkBkt+8uByFGyHmChY5xLUIXk5AS+BvRjAN5ADL0NN0CeSA4xwk6BRZBeY4DhQ0mNhPijpXt6Bx5Cbptp2x56Yl1yEtflowlwbjQUQ+u34bNp6pzdRcWIZP+yv1DZZ/RbVKTerpET0b5+/LsNYMjC5X2/FRlwP929fr7loHwJM17IgIXZyaeIIpveFQ+6TWM37l6eVklIY+sGz4/LbF5nV/JV42MPomwb3zXXPOGtl47dDriT2tGQB+7Py0Pjt6FswR7X3VSWBH42LqhkO+N9kAKl3fmrYDbUWcWnfV/aOVoQn7g9J+YuAXBiWJL+BTYXXM86pE1w/fkuwrct7njH8dtv3dYivIQ8BFrDJkA/PR4CBae/YXtiRI6qisXofXeunoFUUUWvMY/3P3HixqEHiS0+ef0jTf3OWzsZlD+4BD6YH9yo4/pzgltB+hkZSEDIhCsPJC2g7WgIROjDHAzIuNnUL8+jisUxbWg46wBsrZduflvXX2o7sIdIcTFganCgnSHLUJJ9gSyivjoTHq1/AW+CJoINXpFvr4D8JWDEkxEsQ5fGTnUPM/IGsPw6F8OmmRz4I7F4njgrGTtxEiPSNSih5oXGMdnXvJHIVUfGrsLnbJ6EpIi/XrpWCyaFj4Yu/uJ8TmzErOGReV3Ca4wIpWIQX9xe78nNzCrF1FD3x0VWkGiKwzPk2eCEGmUtyAnybf0YJDg3x1w8HejdgdZXhbk8l/WD4U2cdP29Peu+/7AtEfGbyPaSA0SAclLO/rSSaNjvqVPxpOTNnfUYxRAh4xT4T9aPFHxGFO65dDnoEhC9swmV05Z8He/nILItdFujRMQ4fx+zE7EVOpI0dkA0JyFR/0Tl+bfNgx6aafQ6ERCvDBjQ2yY2e3J+rEgPeH7X022vtd3+h18Zupm+HR1EJP/td19/rDKlZPf/aG2EaAjJoFvwdNokB5A53lGtPuP0NQz9ZUAwMUBCygDvvKi6wWvIeUZEsMAo0l5iC1Mwl7O9AsT9gMoR5kONHP9eZWVdFZHqmHwCQheIVGv/EVpWsg+hgSeflgDSDwQHiv7jIL98qeGB1VfG+pr9JEwDsPMd/lQsoB5Sf8EsiJwvHzLMD05acuPhxgJOggHjbhr4dRDp5osO3M4m/w+x8flYsGRDE/NfFWNF2To01YSNIcXXsiDINH3BqRN7ZbNaAlOyTsThM3LkpZaaOszx/07IuokGcnLzvmCVo1y1q3+FCNjTr4xd1V0yBllnEIuI9B+fXcvdOju3Aun91NTICsOguz6D1LLPxP09KZBLAmuL2eb9YOBaY9P3GJRs5gOnw675fMZGTp1Bs/26+F7fjo0RX3KEVJ0vZPSEzqI5G6uezY+vbP/wccmbkO2yBFiWeGCsNYHdD5lFkTWeaUUtsfXSkaah0bvuqF3BnCvnrmqVhEy53kCgv1qlt/+Ze+OxUpkea7W+72U5F8vG+vmYFyf1haADisCgX5ylw5hur1J4hSAD3kJChAOCsjqH0lziHF85Og44Gu2fNXlxjk6iAs/oxPo4DIWLoGgcPQsLZJuJVBDWwIyCplTL3Y3HL3Y2ozCra+j61m2/RTEF6lMjRDlLGmsIowB0Ccvo8hj9NP5FHGkA0Pe8uwMj2IgyNtZeC7TRsqnW/oeVvoWCPT39ve4d8m41n3Wr2/52mqD7IU0wnqD3Lr3alJvCRFlcAXX9TjCXwxNBbs8yF/y/BHIvjozxrrD347aTYxV5+BKomd/v2rEohbvY5o0Wk6Gqn7v2hUkF9QvNCFYfGjVqA/2u+t+5C2v/97nOEUVzPG6vzocj8Tw4KnGVA+a9sSkreSEMEx7ghIeWD7m68PmwDGG9Pa8lX06nlI/ZRSrTOCDq0Zvy3HLSAed6R8OHbaEB2OhYslnVXh43E6IF9WnDty9vzzU7dHx24mDU+jEbze3PAg2f9X5b6pnh+K/Td48OT5HrQfi/t3TmxQCTZ1wh+e3BaAjLyG5CvhFQ+yB4JoMiPDgHAdhOU46LQQt4JoYwkgAIcEtKkAQGcuaqzCEsWr5FFwD+8BH/oIRDecuHLqPoLMqKYfFzVXyUbD8iWSQZCnW2hgWGOaePum5DRuPQFobKBpGwt8RMrKJEbrGEi4sjA0Pi05GPwIphAOZeiAcvEzbf69ac0OvDENd8L/dfR5qpZ2pmjDsLPKNzEw8ruTPfAt2new4+d1r2nw6EVHcPTD1R0MO4HyzNyjwpAF29y0bawRejok9+Z9ZayFn+I7wu0GCef/yMfvyba34b/W5wKl/Tt8wJsZMHwPoT24c+spOt3SHDGxG4olXZ6+iPoYaJHzL0xsHvbBtgDtjhnl/dPxWEjyok4+Xhvzim/GGhp3vD65RBE4KkTmHjc5f1g11M+y+f+dTuOUHdS5U2A1D8q/tpIVJ/u9VqwZH4tuUmyJCxwf7+LqheETZTqlvLB+kFHT48dcTINmtnwIRLUJ1BJ1KQcsijR/+10vHrM1yS3TvekLaAtBxbALoQDYN2CVfCio9F434SRXUg16b3xwoLzRFvfg/4UmI6AEEMfCZb6R+Ug7UWAng1HSB4KXYcDCQWAZ2XlnsbD6EsYmTlYyp45+wQPAt7DYu0wbIvj1vxZzumcp9RMKWpzcNeWGr83RpzZoHGM87+h0ykjoRXjjzg6thLZrUGZXPIEYRR1bXeYMmpIKih9XHY46XOMmn77J30PmnQ/aPic3tEOQAzdWlsAq/WzGGQjzqnza0LOKKP64e+fa+Hm7y1y6H4+6HOB55X+O75ujAajpb44WeBL+om9e/cfWqa5KPGrkJcYDPeH+um/TaW1evRCxowUftUFH4tZ/Oto4ypS4dyVX66YllGA+5yBcdiv/+V5PciTBC5A4Lr6KKuJa6HP+3rR/JgZ+btokIUnVTzHZSCf1w0SRSIOAJMPtLNW1bTqffrhiz+6StA5bKSvwXgSxHnx0WCUSWRJwSwOzmdDk7rS0AHfzd9h9z4lmsS4J9Ejxh7nYviCAjUj8WpTWwLjD7va6VHQY+VRVVC6xfvg2PJaHSPdqXKHsnrzzwewunET/duk9MAMiXNy9Gmqa6LagIgKZfn9XFzbswtrsGpP10KHn1ypBCchVgIcZGrffBovCXd/Xld+4w5N1Z/yhw/jYZWr/YUEGAQPC2RDmCmEZ6EPyif1g96q29ZgUI6QDn37CEbCqqW4TSiDs/O5BImCIMw4VplCVCEnp7v0Nq5CwquDTdBHRcjvBFhrgbXyJh+rctmHbKDc1iuH/V89M3XNvzmPqe8LBkR2H7Yp2vkeADtOHTE08Y5yBKuX3BVHtXhM1c8cUAtX81fG8IRSr0z2De0d78d3efX43Y9+Bos6dUiSwfXDn6l8P3kqpMoTwzT/93fTkZwY9Nt0O6kB5g29iueZZcBdrGE1HsPpHJt/BltQWg4yTc+47ZQseCJkSo/x1icnqazQyQLpgwV6H19QZXnjRbKntcGY2QELI7qdBBQAntOZ6u5tm8LiaMTF4oI6/qnql+6njwlh/tevN8u3BiR110b1/6hzHbJ8Xn6gpoW+AElQDWtcej8GEidUD14agP22Nf3bxoTNc8azRHvYdAfuGh+N+P2TU0Kl+xQ8AlhW+ALXV9306n8DcMilS0AIE8QXctnIJh6CL8inCbxHZlnYNYA7xOngnc6bL+ju0oHf0b7dB9I/bcNTBNeTUxWvF5uJMh9q6B6chj9Nxeag5Npyv9WAk+Tk1yZ9L8ferwbLOsWuxi04asLggBif41hokTAly21pawdyENAFUvWCkdPY35GCslF7JhChAC3VRbr2WVhv5u5ailR7pe2/MoSbiMMFQ6ZPGGnyF9jXoQ1vUtOZH3Lh1HhSObW+DqQJZDkiKDdTlQGHH7gmlK++hiPI1+1BaATtbv/e9rVIaTRmmIflJKwlOgx/5dwbpQQYlQKb4aEEoBuoWOt/bKaERnkABdacWYgPRTET/4ajJ5V1r96V+es/bGnhkW8aLEs0x5t/FUl1TboITN4C4NuZbUwIRusBoisA5j+9KOPi82RgeT4uqpyZunJ2YpQFR9QN28m9Lz75sGFJ4NhO4ngbBaeOgWtydBhuo08rXeP2ovxIL6FICmqueL26Cn7Bl4uYJ9wMS4bDKYk+KVRFNwFMuPxlDxsiU1feiWBAAkAVd6bUa4OjPqxs9muVa5kIDlw+uXD+1SYLH+KO2NAAAgAElEQVSdTTgGyIVJ1ir3S0jzPbmzf5rSseCf/EhPNc6aZ/NVWXnHl0OiCo1lo7zaZ0Fawh/XjHCRxge8hnJBPhsbpq83Jo1NA8lbiPUfHp3/5tyVMXJcmlK4s6E09kn4dRceSnhiw1BSB9uMhH++MGM9VbMNySzn/ODryfbkjP2Fro+0BaDDGGChUxNZEeJEe1JFyNPsZ4CwWABdlf7gUzj0gd9zms7X/vJL/Mg9g1LxZRkhIRiqd7udrcn9R48LK3984lbiUXUTTNJ54926+3zhsH1vECw/GZJyt4Ut5QS+yyAIzK+fVy1SOevSOUA8KLDhBKZ6HI5KKiPbd8iRnw5JIcOUddJtMOKrQ3F/WjPqWEkIBP3H1y+zlmqsOR5z3SczBWM0jRx+AERfi5ADigZ5ycNrRjpU5k1LyL6t76FZiccDfcnSLR1QOofkrp8cSHpjb68m5TmxeZDHJ27DmDU0OSdKQ6BN9jqnEVhUHp2wo3/nIiPJLZ4S2GQCLx1OkbODb81bSVUTFbrJpmR+eiL1iexPxncKJUJuH0O5plQoJIO0P9k48pMhqb8dtVMXuUtjwXgTUcrKUQSm/d/Mdfg21VIE65J+Kpw/CVslGRzzSpoKNgEOdfSinJm4hfQ1xlYMRvGOL6Y1SR3vcMxtAehQLgc+1Su96Q1HH5SLO9VBHT6Bi4MiDVQxnCyutaIhOVso7DPx9MgW7cUhSjAuKppAyfvILwWlo03DASCKGm8Rpztr1EelQCinkd0XhoT6SnyDmrEFIeU6pTnQ6qjGgAkQjZ/k7LaX2XHqFVC1wMIam/LPBDy4alSrh3GSv+nB0bujQ8pFH1KvSZDIxsEv73RQAiXMv6p9wDnsL37APxx0YFzXXBXJoqa9rMqXTFILDiYgnvvTuO2jY/ONhHz6CSZSmrAmPb15MPwJOdntX9ZLs9fe2EskzOoj7LtN2V1QiSCG4wiLB/YvIKI+ZeEhtvAXFhFnj/bFf520dVoCNdLkc1YC0g2irrN3KtLDjwenEimjJHfGfoK/IMX76nA3nt11+WP7kRtHUJE/PXlzsCVvOIwToj1nxTMpuUmecRYqg9eGdN59shNrAPlPXNzF5iOk99RL0ncn8okub03+1dLx9s4Dvkt/m7Lljr4HjZhPeKGXd/bjjfMXh3dEM875j0zYbkS38VBM7L+3SxgRYpWfD0sxHBuwLizqYTy+zr9RnPrpjQP1/GIO9kl/Jvp0RArLv7pv/pnA6z+dSdZfh8Nw/2ArAbo5qWy1QCEAbY+V1iPC3UfFCbQuqiE0hHLp5K68SQ/g1KN7oN35Dw0M8f0gLIIZkFRE5SFauwQ5jeyM0DsqjyOArrICIHoB0PHEkjfGaFjBJOYFQMmfLnGe+rYMcTrhRe26azUVWnm+OY5U2ctoS6iBZ12Ig8WATAYlJyTLGEIUJkR+K2hsAkQiKf0kSrItHtZ9bwFqlt1viHJRNXpDeM5c2S8z7r/wS+dMojkenbBNpTECajH0SHnRqBerSc9HtN7Ph+0nD4khaMNC/POa4e+l9LSpVUbOAMQwpIKJDD5Lmg7ZKVslxYbqxa7/5ZLxXEVXUxOyb+qVQbpH3RiU37ZqYM3KzJi/bRhChQ2bcUJ/I/NI0HWHNMxAvGT/2dFnqV6Fg0IN/565fnpCliECQcLxiyXjDdMSTIR2QF+Bqctc8cVj5aNAD2IY40b492A2ru91lKWIPFaEe9jBjKnsnM/7+5MXpCduPBFpM0J3/klU0Ve3LKbgn6I14IsQ27xp8dxa94DGEQapdwcSpTUcZh9DJJHD1dTF3e8dnvKzISlRenkNGu+CHniJDi/p1+kU90WZru7LO1yVGQ3r4mzbRCfMGJrIuHChXNjOsEb+/Jvx+Gz5CDaGjZFRhwhyiVfMd0ONBMf44+uHvr23p8P6qHyXWMKtNqABuIhI9O9w2O4fbBagAzRgH7CFWa0mhkSJpCkXHWGgCAeDOmohUZI0EfiT/xCV1wtXgNkbEilwvOdtyXGofCBgcdKshtIQLsbOGgBonikUjAaXuRADHAimQ/5J1CWoSjAOWM+9+FOqFFlSJ1p3C8hSYNq6XmjOVqlWoZSU1mfydHQrum/9Zyl/6H8BlHlAeqD6Mw9LZl2yqBeiSLFoxm2egn7IToPWniKoHXprMY6/bTYXyT8PfS1lj1Q8Lc8bPUJK6Fn/CBxcc5kcGhpVQDwIFhzPg84XQ+/OL6e0+rOR/e6pKVs7BMg2nFdL2bPH1w1jp2xzIwx5DGT7ImQMLON06CcHun99KM5absyZuLxQboAdhj1I/1Q6/c3yMTYFbrjXc9M2fKffIXUmp4Ev9y4ZrxyV1OvA8kUsz49fvXnM89d29SZsx3qQkAk/H5oSGYLSsR5Qg4b++TcNKUQ4E/7992N3do8oMXhbNbGkIjofVf0/TE1+bXfvZiQpI4faJ9cvtfhmMVH9/7J++Bt7bJOxUDXw2SmbWPYMtSjWNCYqVMkja0e4cOTav30iae8bsRvew1jqyI6AwsdZQBPWNO+Rlc881eRarfJ/d18PMN2+c3UEmuuj65bh4VCzdLQ49BdLJigdFGIVcshAr6szYbrQOFkZB75PbRysezIcNIQ3ZJc08s8Q2YsrHl7OwalNOdQsQAfND34l2W4BTfK+gqoS8EK6EtCTxcmStIRxyBFMAWGUBHMhOsh1zvkI8gz05DiyRaPWj7PRw5akfyl2vQq0kd+fmCL66RaQbYBv3X53Bq/CXUyWaCajUaqU3DJGHgJnY7A+zgDgUigkTaJzpkLIbhUj5/JirmIB6DHPSZk9u2vZNzBXsiPRVxFsfCpol2VJQClJdxEIXb4NXvvFGevUN54fPDYRCvFWf1y0NGjmVEIovlAozAz7y/peD4zaA/9j/FaNj4h/eWTtsI9Tu9tbYRS8H9i5iHI8JBgIoHie2fT2fnNPT5ussJ2DK96/ZjkLmJk0qPdad7wLBfaYgdndj7MksDzoBLH+PafqZnnQn9aMBLKNYbCPub3voT+N36G2/0wXhTvuWDDdGBVMDiMh+xW8ucUmNlXVSjpZxhkfVmYAImYm2Pq3jUM+S0tqatIYNCHsM3p3MMu9YfDZVNnk3uF2eAt+Nmy/QWJAU0DyoNhphsd7TGweWxNYeDMQ1Ju25HRmLTzoPD8EpvEfx+3s2b5YbZ5AK0pXw7k7q2REopjnp683wlCPlYTd8OkMdTIY9O9Z67EJ9B2blnsmCL7FSOmOrxWtDmIkh19aVpTNd32GM0Z9ihtj4aG4O780e7kdXuLOwWYBOsGcoAywbgZQK1Rt5J5QyQFCy6jgT/mC6nVEB32/8ShNSlsQaGMuPdHIbSwfOxkYyAjDQ71Qo1EDj8pzEnqqN2WtWX4/DafZ/I3TYG8w9snNe/gbeSijye5BX8zsG2leWAZgThptLEh739ZOZTScSBRVh56SOZ19D4QPZA5joNYHHTaDo290AG16AsqNf89aqwI6dKgNH/76DZYlvHVGhsjspVlrKWKn0BbqmfS8eEQhxG1uQEL2d+Yth661Pg5uQnrO+mCui/gdYo5gS2E5DFHdidIgaigvOxqruiJDCL7Q2/sexJWqjvCwFMBEIQeI69WuG5qSQuIpxfJFymJ8wILEbuAPY3YZJSt1nfW0VL0oM41c8C9MX4871PDWshQtOxpDZnk0l38YuxO3qnILczJ3YfmEWbbJLmA1EMd/Rcf53jXLdKyUE9goUMrHujwbByE9KCg4MT5X0TIcwR/4o0XuFieyuTFaI0RKkuNe/63pFErMdZ/OdDw+/Wh78oj1P/SbEXuI61GnYdT/ZNEE2DCHV5FFEh264ds4dCps/NvXGbEFBDTdP3I3wZ+wXrV1XuEB5ww/56FTEezG0K067JaXu+z2L4d00QPm9ZZxOnz0m9e5o9R02KE62CxA51L00cCr2aS1NpP15IhikttxHYKSFlMa8oHQdhoI1WWQ0AiuaXduxO2EfNBtVaOJGe7oRuoEuGaSpRhJE63PbJ8sNZ1htFXLXC2US4PiO0zYIbh+qHBFwfNQEDX0IFnUjTHoKXypLkQRpcw1cjnPyJkQPh16CZlO3VHYGNm7NJhXcsOooVI4iUlw3XCH7nhV3wlZNZX+hZFwIxqgD/GVMFnYGPfZedf3vTg+hYD+6PplgyMLFDrgKMOwhapuxdGhc//1iH2GKgNc/peTbIto1AhHNOqaqjHAEVPc4D87+rkOOIR8/8WwfViv6ncCzbrsaFcIEzbv9DMzKeuh0TvBfWvgtn9GQBZXKpkJqBrx8YHkwgrb+GcM/JdnrUFioaYLzd/N86eBKaorZC3kjSL2R/2TMbB03fr5dLqVMSRm4YIeaikKyhF4D4iXpmbOoe7aW/NWQIMoeIWP+jg18VdLx1mDFOoaqmHgk1Aj4YexJTvyN8vHEqNr/9SNHiH6jIxgcDjm56r3YuPiUOJi3RURTNAdhmAcxwnVZf+xZaDD213T4+izUzdHBkv9OX7H+D+o7Gx4m8kYzPpEoi7sfTO86S9SJwnjONPFYv/3qRuh8oylgmpZ130628XewuHwbA42F9CxEEFY0mmRjhwLEShBLk0KwNAoLbybECMkZgGyOe7tI39iS/LqgEj+DxjF0JZsLToWt0+SDFOui8nh28zdpmVttIJvkwTa0C0fAdl8iyX3FsS6j7DVGMgwEnxK7eZz1IUokT9Rnhh5UfCI9rutIU/hsdXasVUNFA0xmcA0PZAUF5+kSp0Y3EW8r3m7tLydFg4Esr6LlEDK36vl7ZbLecbACK3ndeICBY45n3mgMBM2tcH/SHDseKGYGrWpWSF2vCyrhesm09tOQwAjjmW0t3p+m0sf3LEl371m5YzE48rkIYfRkiNxdy2cjK/J9Xy4+Skxop/dsARkUQjI1hsV9rT3rnaYpxDP28NjtxvuL27Bq4ZwBwjYU9vzLTZjeHUOSWmOGNYxvi824xtPSDyqKsIAUeti2OpesLHEXrqIOyWNAcAN6wKyINd5YVt/BVLg3X9mraP2kyWC0UR8FqyxQeVznPIUZDvB+2q2znTS5obPZjmTfzgcLRw6wTvzkomXEdONZSOzNAwjncwnxvnw19RQNpyB4N3/dvf664ZhNl5oh/3bH8Qt+fiEbew/1EesQxSf+2tjCZARIH1ywzLE+Ga7XjMRhXTjZzOJE7a/BUKXxbcs7N9ZCl2x/uGIJpHWET37OY06TU9M3AqPZHMhr+n3K0ciA7Xv0DjCVevu/BwrQc05oQa/XT4KR4KLSxr9qLmAjt0K0IDIoJ7DbH8qMRYAig0OIIIvOEsxV8F3xCdw1gagwyknz5UqFi4avYGYJzZqVSzFupkPdpMBJn6ywLQqxck6AYIzGPTaolRBA6P/8nHVcknRIS3jG3PudX7B5Fbsd2uDXISYTFYLM1VtkiUncZrjMs1pn0vyW8X8MIbIwZIq8uhy8QmrgSm8BrJVqi8e88gy8eWq1YtbB3UWvsWd+CAuSVugnWSp0Fc+rkUriS+acfIVkGnQp0I2N/Va54GaP07XTjKT6HwUSsnHl2pDlfHHsTtutJT+4jFw0/1syYRNzRJg2M/CtIQT/72KumXmnyLrBOE/f17rwDnWq0MxOj9IakNgR2+kbUkpaPfEuqGYuvadWx8BPlZ958uBkbo1oxMahH0S+cIPmH/iUnt33vKBkYWKQNdPkNfLC+RsToa6o+IPsaZwF8dKXOX6+OGg1IfH7bBUYiPlUyioDYX9qxF7kWaqBNx0nlMeQmgMhSNYI41x4p98ZuoWmB8jLIhVZ/r7bhCDVo+Kxua3o3cThoOzQX0Bsc3JoPv8tgFKicjarKed2WQ4igG+h1aOcqiEcT2r6lM8xq/PXUVZCfVPeiOA68kNg11fy1RQ1ZpklsYLJTYVEv9zOzBldSTA7bej9kSGVDBZeiBx7O0LphtTx/cTBy80js0dSfny/Jb+uCJcjIS8jE9P2TS4i3lDgy8BZ8zPvhnv4pJGP2ouoNMxKIMloCxB9+EDMAIQoeAFZ/UG89DzWpGLuG4Yy1QTlUzip3Q3LJXYugrsull4E8WL2lKIpax7JuG+1bVAZPoXsswYTlGGBAtECKuNncuClPqRVnzUzB1BrSTPEV0jop3TeBQUvHpLzqzEGeangTCBXi9MNX/KrdmRJM6UrYw7jYSLGcv0dYjOdX9D575mCb84olH76Cl/eRcsQlD57Bi6jhaD/dJvCATvG7nnnkFI8czaIVjjP68Z+WGqld60BY95fc8jhG7jwlJfXjyNty2YsSvPgRB4aFThY+O3woNbf82J/3xm4yBMMMVauBgIRQ9wFRox4liRZF1H/6AuQRMChT0j4YRF4EhkaSAmc6B3zdlaX7hsCjWwA0BW0WjhvQGRp56bugFtovJwskTBP6AERyw0N/mYZaPj9SmkxOKJ9gNGFvnijA2WQEcTDADgYuQstD/f4ZE/jduBpW/o5QEpdJDkCjdCnMiyANUQHYrDSX4vWPH4QslfOD89gb877NPFQUr/PDFha2SIuK/ojt0VBeHYyQG45N0Fr1ljWFCJ77eOsYJkIwDqoTEN5ThYCf66fghFZVk7rYeRGFFGLnX8E2r2+GjFsdib5lt+3Zo2IvokGyMjubkx1Koa7xe39yf9r4vBQ9c8NWWzEQ4GfqByYQ9KRVYXV7n+qAWAbnQssN6UN4G87xAiGUg0HQGxZJNmaDHuxYaxEiD8MJvS3qLLxhZGC9hoA4vT5jc4clkPYkYKatOIWUUdCDeiGuNhqQCU7TUkp49KSJRSs/DIAPqQH8n4saNzd5ofhzUA63vQ3Q0jQnR/cq+ZcuEqKg2RYBJlujuNUR1cKIyNatBKsSOFoWLfY1b4YMVVywoH74RTFxoH5aisQ015I+6MpC3OITfIb0fvMWq7IL5+YPnoRRnxrTKWP4/fjvBDsSh8g7dmd5rhREVDVSOMSiMmUN09rajduLeutY8vtx8bakKkcoZYEOYdktfQfuCNRD+jM0tyKXQ8m3rSKLIAFJyVLC7Ux3Ef6W7re5h6abF6li4eandeh/tXjP3J4BQIH1CeXyruVqLqEfbZjxPa5/W5q8EmM9TWe32e3o10C/ZnujhCoM0fxuw0lB6sXkTWPLy6oRwPYPrC9A039ckwokOhm1ML2pHhnWAoFz07/IhkCdYaRFblFce6jo/L4Umpv4wpEBNW4e9dU1HtC6bnlgGUJswCDG1vL41Mv13Dygx2iEyHMFSfpSeerfY2Fmle/XPTNpLy07J/MiFAumfRxLzyYDUe9iKwTDf1zrBRQLG0vLm3F7WqHQ5bHSRKmUgLOHo1Bsa8Lbcz5r9D5sdFP9YftQagu3kr4zTQTSx0s39GsKnbVIn0UY3HEo8fhIkjSLLmRjgffyCAjh6czLoumhSy2Cc8D05O1egfL2KPufIv4DL9c0tuGcicQC1+vHyK8WvTsnEFLxO/qGoY8r1v0PCvQqpkoXq0iNAhl9hzGOsBEnXcuYo2AWcj4rX+33U3qS9XUeH69DHzasF9WQkG39O4KMh26JfkvwkmfGjMLgXoLP4FZ4JIW/p+SrLrhEruPCqZpFB9TBEptNBZYMrSI+IkdHgtosD7RuwFqowdOoPBXp74zjUuCH38k2gu+3c6hayNbbUKHIXxwCC96qOrDIMRzufJyVtABKOOxzdH4lDaQF7LEZOkWnQ4KmcHX7tqNZJzpV9EygKnjJb/O/1JgihPyoJB9Omj64bZjxy/32c3Lu3X0az54YfISDDwjazrzu5ofRxGhWSznYLNiX+hXIiseeD86g3wS2S6T25nFsNwOQAKi33z/BlUGXTnLuoceBucE1dZgv4ZMJ6DimrvKN38Bz70Xa25qb8LuuivG4tbd9XWN4QF1Zk2Z0f+ftVIXhAnGLegpjMpChSgc/nmnC4/Wzze4NA5bVq3E/+YvjEurMwasZhnnAeuKReuZS3X5bACHSwzcD4PLB9FzgD3J8HmzAsO6DAe2du1I0saJCUYlfgVsbVVw/qGpkDLASzat4IUMYcbxIsmrWNPLW6iJAd30Ygmzd2hZW2yeCZxqIK580QCSCMHVvoCsdB5XTSwHpcmSG1oYIyeWYdO0IlFVwPpkTBVOHSCpDDDhRjRG3Y0PtWoYcIL0dgZ5O6y2O8mLTRGOnc/jzl7AjHwLTdFVzP4B+InuAIaGgAAPYqqZvrD8iPhx0bdgxYa6VhGSLZhGAh/x1LDcEUyTCX4/+xwEPHPfTEqYX6emLTFUKRxEEC/4bMZ2WUh6PDIYI7dzY98i57dF0EL9WhgA9B3k83Rx6vW4MdBHMoJvZdynjb5WV3tYMnJhTa8HQ46KJ3mvWGSMrKzUfpFMGLF0Rhsc6M+jnAgesEze6YINp8cs9jyat3iBPYH9yyaBHvg/khmJx0nZ5m8Mv2d6RY6cZvDDIhUXf15/A4Y/1D/c+rNCsjWeSEhZ+9CxSU3b0f90v/MWo+Fayy0rFKsgvaZL607ZE3liyRJ2+vrYbpZ+YzLKcoBG2YdCsTUfXDt8ukJ5hIoOE7e3NODDYe1bgcr/v1rl8HLWd+FW3yWloAc0/WzWKcUhfZ5YesAdipNckTb9H/BAZ37i5W9qUHyCJsMBYHsBNbilB6sz3cBnQmaDRXMCc7Ka9dfPT7Gg19op45YGAz4jQRhTghAddHQ2xSla4jNIV5ARhyzYXHiFKX2G7U9odeLM4WAVhQQ/YgYcbbW0a6Y4b53pR+F+5yGhQ77AaCzwGz/j6xD6iNWI9yeUPBKiynRnlsb7PeQLhIZ69oJbP0suA1YLRokleFaz6tFFnkFNHbur8xZC/KS8oIvBT/7qhqfT9MSIaDd/9nbzxOSD1DAnJi3XuOH9M2Rrmy3XWSjnp2U+cbVq6231elF7X6zfPTwqPx7JJH3WWxpLFnoEfn6+NTCRJP8z5BaqzFU15HZNRrr2DpZCsISfL939Dus1JM8I8PABmx2Wg89BmpXAAJ2/RdDCAxV6wabM+uSMYp03iPsozfVCB+fsPVHQ6jsIwYjv7qNWV3mfjwHBHS/keMb3T0qT7X4gU0Q09aUi+qKgJrvD0i7c0C6UeSB4zBLlAeZn55E6R937khUEVNHLVODslCVSUItucv1Tsi9IP9T3x+E6jxNTlkQlgELFWFWQ7sUGoVEWMMw0skBB11jDADK5a4B6Xg1uLCgIui+pWMoF2U9PMgxdkUzErOM3YB6FhikZzY7SKdjfS2OHKg/BFfAW2W1JByGVFR4584M2J/TGoAuFITJXRIAnheTs/CA2eQE8si2iD1bWarzHnmWIeq1RgFr7GUF6Ji9/B37HXUNskjDYsXgRYBoXVLO/ik5gpGO51Mu1L+eYC6XAMSY1SI3VN9ZyzcXWgNAt07Vovqk0BLGsoH7mPDsDOgKPy0jV1SMrEa6x1XpWOgfCx2PqxqwYtgRoZM5gD0BYI0vQSXAiWKPYv2VsDwGp7EzYMlR94Wh6tRPYmtds0wOJ+ESPMhO9vkZG3AfmQNz6vlRBb60s68z1XCjj4hymQoSALGxQQZ0noM8TUtSZYUd9oCMYfvdn6nEMuoEEAG93bwemZPiUb+Zm7HWW+++LR+aTpQFP7Z26McHzhN0IXXAoAYOFCqBKdjUj68f5iJJocMRGgfJ3/2P6RsMXSBBUiw2RioulOlzP5pjHZRk3RtWM4mo1LX8GFA3Tn1vXpN8dNAg5BFEeq9CK7G756d3u+fryQ7HjH7xB4PSDB+JOgfjl4yPiHAWH+56osyVtc6qTJkIviH8bngFOEI3ZUduz+lMCuJoXchYeDaAd9ohsIoXRwpyFozUwgiyVKJ5ZzdAEWoGic7k1j6spuYdMEsykGqtHYSmJ8k7z8Ut8E4jT6LwrM3jUKiIRGPWIije45IjXVG1uk7PwsDI6DKtG1l6hHf67+5eaJmaNOE2I2kZoFP8M3ubVAEFVeMnCOIAuw6pEuO2SLMPf91AQUBKxE8SHhwiO+X9BtaC89WSKn8q0Z4F2QV1LcjLX9GrkFS2cV1Hvbb9JTHJG2l6MgN2BgnTHSAm0arQ5Qa1Ir9a/tNpOesh4Sztd7sMjAZ3zyUiwNcbzwt8wzIxD1IP2pIvAfTHLWym3XUhuQHubC+w8YsONNj4PGziVC1ykLnPy/r/YH6JvSZ2A65ZoSTfe7QfGOk2tXfdmQZoDZQz+EINzQnWEGpIrEgKtjlUoKtu+3Y6vfDmRVaAbtp4ovO6rGh031HBFWzMrX/M1iPhq4FVCPOARxe9B1n6bITkBAQRCg/rrXMFgkrrs6LvWzbGmqV159GMcwhqZbqMaHhFrajhsd5QuPL7CyernYR9t8Q9UheUkC71ERMCC0xqdfszXRwBZH802JwVnceHmxr95vUOz2feiNRFP8rLtZ5AZoxgH3T6wDqVH5wF5c/pfhxHCNsj9cVglaIs34KD3XhNBGpBv3CEtYG7YBCA+7xr4jw3Z59XjgrvBaobIwYYqoRCptZbBAo6o3JRhBjvjlCAx9YNs3kciEGKdBtxBjw1mTWf2jgIvY3rrSRSLvIKUIbUz6eORAuS+nHDYNcZ5B3OpHGwBYAOriFWEYtVV6pIvlld4IGujoB4Fy1rg8RV4qgEBJFykwuFoBgohdRPz4v9cdGD9UeYusN+5tiDan0a6JnynoZMxXXjq8GzsMZAmNgvEjzyvvdEFWMN3/YdiibSUomC+YEjAr5dNwpYI62hXjZsD3OC7a/oGq4iz3DWOl3JblnG3Mx+4/qOl86no2NO/m70rglxOcqGZeAADXx3o/EjNo8ICXD/KHSQqUCAQWrzA8ZkJr8KJpuLKaEWxKJbvzbSj3AmggoG0L9TEYXqYW/6dy60LkyhQDynPAhMyTsTDMeC0w/b0J6+wEgkqOeHg/ezxmAdcAKZuSi4Q/xks6PASQGI3EX5RWV/a9lBYKJCF1Bjz34Y6tmpYfTqnL849gUAACAASURBVNWEjKr50c3M2F8vG9ekfLZQLr8Ybk4qy92zykIIUKIgn7PpZW7JQzsuNofaQ9bnoCDMKQ0iIp9E7SoIy6YHsrJQp4loe3U8syT0hs9m2mcMdnZfdZzkAcg6id1X/+SRuRfCRCPC84lJW9E4KrAGahcejP/ewqk2ff54SCpxZ+GW5A18P6kO+NruPioY2MUAOgdV3DNYShiG+p4jmf7Pl4xffDjOxfmNftQCQIfOBt2EetabMqixQMFB/guP1doli9oaoxgwJd4HkCojYNIkScmJsycnrXzXvCRjeI9rROvCmRizJcfEFDUYFb1rKwBV300LtHG7qOFmsUqjz4rKhbXEIKOtz5fB630im0GcTmoUe82iOh/eBq7fCPt0cFN0LN2EQ5eMj/zu8QAvbxDdOzhfP6QUNdwaz0ForAa+858y0pnnjKVagRWgy8KJ52CW8DZXRkPdDBAbZhS/K9KMUGUNdtj9CcBofWbKZrLaGtQ2v17Mc2rKLM6Ic+2JQq+y4+5PjHQr3BT4oMTMseIQegv2qyXjB6GYsAegMLKz4yVhbP+RuO062XhCVFgg9IKGTAJzHj6HdOcbs7uk5DuuhuH6qUkIzCJBgheb0zDMkYSzUXB2ObYtflHqgppZaT2Yi2IOlOVzdon9cVQf/5q53vCLYqsiHfn4gC1NYX0hbmR0RKNj86BKDDuXE/hNojhcdDjOYW53PXx3h8WxYTp8KnT4GzeqHYn9qJwdIeXvzX0yyHwQ5CMRCdwxszgUCfn/dptdaA+P3UlBZ0t+CAknvnvhJOvMmvRMSpY7+6fjEGZpx8H+YWp3NIsI+Z3d1Po4AXQUchkVc3LZkVjS7TJd7lzl7JwWADpMC1QAKbpokr/FItpTtwJqCYnE2iV0HnKZv4CYktWkTjgHFb2pzoSw7nOzTlCQyzJTXJTw0awTWLUgFwf5i5RFhswJkWtpQL9orgPFqk2+qnECXd0IpfbhJeJ3ZYFRwauwK7xA7gIHwi1AVXQv6G0wk501lgRiSkWKDm+nLwNquZGh6kklAWLIENBWNYbKGmCI3K27FcNJv1hmT4/SYtlDBAnhE9zpPB1L6sda/v7zZpj1DzRXgnR1IW7ky7dR3pdUJMTgqF+7/OpKQqnJ+02Gu0CDuUoKESLFFczRA/ntQKs39vbkp+sazZlXUh5+c9tXRhVjjuBYG//OdUapCkJplOF/pDgU4rhJrwI1NAlaJcOUbq4wNnqAcnl2szD77ovQjZvC54LLhhhcHccqJ8qRSXNB5rBuoSJHemio5tlh4NLERnb/ifhVLLx58ZiuJ5VQUk8L050MiI32APHyypw1k+Jz1N7COB/xyT+3DiTFgg1TBDv0XctQebqtOZEzP9CFyE1svFxWIEKE1DKG8BExO3JPRX8TCcWOh2BUZUvCy//w60n2RY4IJ05sV0KmMzgWHNruaz1Ri7IHDfE7l1bUnoTJTV2QbJ61BYBOT6ScBR/FoK4VCDaE2HITM845YiesLW5NQ/XR+6bzZCoY0arQBACHyxE0hJ9REAby4hQF9DkH6AT+VHy/m68Q7Cs9Lr2RNt07QHBZ1gmKTpCcQB8zakLXKVZgXVAuMgaWB1gRWQn0cE0WMFmxarXQLqLYgYAyGmsAGWBY/1Q8FMd5FlY74qHkQj9JnYg3Ao28X7hsDjDtyWxjpO7iKpYE0sWcN71qHQqWmQcGiFZFbMNqx8n8iT/58mpQjSSx+vnQfVLfS8+CROLptMJ2KF7gEA47z5WqpoGr8H2NjM43MI5VFGYDqhTPlTtThQGFfM06wpsUfXcsmEokiDuXuz6HXNuPjt9+HbE/lmoYYDp07drMKJQS67OicqxEF2RnRHKH+hBWp/Scb12dXXVqTSNtLxhk5CVXd2frQBSl6+puuEORRVN0zZ+CfLo2hKyN5A/ARnb9CDafvjF35TU9My3Se3EPOtP421wYE1qOp3Rc1zw9Y3CdhfnRSqv8H1ol6woUmbqkS8jZZ6dsuCrZnOqHoRJJQIJJ44QmDRipEmoTXMf0w3+55YE4J9F3Ms+4Q3mcGYknlDFBbshfLJ2ANd2k/p2djB3Qr9NpTAHeMunjnZ3m/vGWATr3QQiIbYuYDzEiaAIygjtievKX8zMjqkFhqqv8heqfGLaIvpGpANyXUBPDXC3YVoMGl4FXHsR+SSCKCjIdBp+/wIBDrcDRG6BPbyd3yUxCVRF2ZKN/Zz7FjbzDFtDNS6Y+AGabC1lgWOcIiYLFUpshjsjW4TJpPxh44OFxOw3PJNN2rs5nS3Yn8h1iqut7JQeN5H/Pz1gP2W1Q8JyErYd3i1K/LpLhWfeF2+rl2WuMcgR8BOD+YdWI1/fYaVsdDKHxQ4Q7EkVl5CUH0GkYa4wTMTh3oRgpaEuhHxSBHQIqyZzFrv/0WX/YJ4c2HXq4v0/biMDDuDduxsfWDSeqyPVoZpF5ccwuwosQfjCl1EH9y/phTS00+u9Z69gMWYK2hB+78bMZDsdpP5jEiJKRMQWDIgsYCfFfuDQx+StqfL88GE8xCqQvPDu7Kz6ipCfvxUhrTh5KwqDYOdn32egR1lQigQkg4i+sl6Q8/HB/d6J51ZgfHLOLdLsq/wwLBvw4eXEb7dOdE/CgQLUhnmHpItYM8l29eneudXhOiwFd9Yqf8NRhsTSxPZVCA7NaFaMQ+5eci34COvAq2KScbM4giJzDW8JEUezZR/E4HO+VeZBc7fxnqGvMk2C10TGTP7oQCGSndgdkFBsRZl7N/2Uxb3z1ycREBIe1IoIfWFZpMKE6H6QmR/hXMQHAEFWVYWMJ6rmu5xHEbUQSqfQmTAMngAskGiTzrWsFgvWcseNecfuXRvpZ6UejzFsCSRORr7R8diGC7xqYDqbjJbNeeOgZygI8pb4oxUWTIkq7ty9hb4HrD4hHEsObh5+xRwEy+c2/YQliD2OLDHkClw2H42K0VDfu2b6E2KI7+6exGAA0sMn/dJJX1lk/DOnGXof/MW2TyugCZQQ+Prlx6JdNSX3MXgruBXUKwhv9ecOYlnFdcxYdjn9td18KzJJC8v1rlpEEUT0gM4DbmXS1jWa8cTZsjhMihKCFaKPcsqDP0xMMPdJ3+6U/MWmbyp/OjT49kPTAijEQQS66cvMj5oofLd9nX8mRabJRQLnZifVprQTodCl2t04mqIYMEXKDTHGAOFE/YrTqpDNW6tFlepy9/iUE/aGtiZyE+vA0ZzOAo4LsvhS5VpOm5g0dOuXxMMlVbhnDjQxXQ25eUq4zt+o/Z91easdhG4G8Hw85YKTrUk8AtmLJUuO4utYEFYNbCfgG/XGiksfDGh9lL3Qm6NnNg744mNCkjBmkZX9z3sp4Sx0ydV8QhLpCW3JcBrW5PcnsJIhiR7nRo0OpIiuMS/mpsG6xmQDHQWRsdtYkxftjQlonTTQuAUwp5YMmXScKOEeDNrl/+Zj8ClcGLOQ1Oc1v63uQ+nAdA6uQuFABtUnh+GoAADHUzfi4PC8930B5le+/doib0WF1bBczFB1agfiHJ80sCaHeW1K7UkbIMrwtN3JAZ/IHrMalaXY81GvrsqJ+uniCa+m6i3upj5g3vk42FU7wW94/cg9LC05vROLU/0Pa2GhXbXJC6wG6m8OHLCb5OM5Pw4lKQee+tzmgKdzs8Eo4Df4dFh6PhTFpmN4shISMUmGVmClyC+N9ZRuErAjbnFgt5RiAT7enhi7ZGcOQmZt8nOKZiRGl/LTgBNhuW/MsAJ9sW3Qj3V4YTtw2GWWJSMJH19Q5uFvP4m3tZuQu5Mb71bJxh085ylHR1Bvo5yOluKHXUcxbZO84YAXW9ZAZo7Fi7S3ogIVIFVMWJLUxc3YrKUY64CB8OtlgduZ1enVXb3eClXCHElaKNBvoJ6P6OicFd5zdVB3HmL17YPp3+qXzmgiZwaBmwIj9VSSn62tdfIrKCMcAvAThQgQT/HRoqh5PIKYhqx0eAuSeLi5vyUdw+r06FkcFn2FD1lpLeEvG4+zaCw7oKEzIS05uE4VNfCUlNfnt5rQnzoZ5hR/H+s5PEfE+OYQBEtXY+lBFD5cyrTRL2Hl2OUR4mRl8BW6X28RhQKEGgU2mMAVJVEbG5EOnGLXTnD+tqaLGBwUxCkWiH52f5vQTcnyjbDOywnIeKIlLFh8j6VmcXtbcDwZ2LpxFQdGk4xAspBBQixPcBXJG3KQIIsn1aF8nz/5uTBS7GZ69soZQNXcbKAludg07Q508ZzGljfaF8zYqtEJJd44Vh8KEtBDNjTvyROhEicjHT2AOmNJMQDwc2kdNX6obfZBL64QLDuhMD3UqkGYrPTiGJKnDjcxcl9bkXeDRUvYPz7Oho8f7SgoBim5fwQ3xCXHzeMasK9kzH2rVEwMWLrDOpOehjXt6Y3PYAzW7BOijqCP8xLCXuUVGcfjvV41CXPEtvQEyjUyJz4YHB1urarwIZVpwMKElHLH744SngtzA49qooNP9PlvxTFyIFBAneApCCdct7sRFGXHvp/SAdWnFu1yKXV1wQMfYJCNKUZpekZkiy5FinrvQfV+Kk/otjRkpEVkhVS1WbgHBQlIzsrpf2Y3Q7Tv7HyQjK35Fft4KcMmvSx5EdGA4DIkd53dOXYKWYBPCsuenb7wqOdMISmLW4XCoIAFve2W/gbZ5ejJz/XRIKtJvPOGrj8fgLCWJfEtecds8Rmvf9YIDOoQvgE44u/LvoZgmV6J9XsOWP6cK1UG9R2Aq+hBUNBJ+qVfwQo1D+CVidiXpk/wqQZK5xVo83vIBtHoPAPqB+Q0p3fE/IxAy8si3+u0unQ7HxuaxtU9sV4oFTYAiIM5vG21ZC/1j1hOASA4vHwkCDbUMn2Kkrz0eTbxok/yrl868XtQjxYMC90JWS7JuZZcGZ5cHNzVx/EX9eM0d3AUHdPTUx9dqFaq+IoE87bXEWVqn1hHzmieBQFN2AOQoR9ktlZqJC/WSOB2Vm4V9OP9UYT4inEf2xV5Bj2/qSMLevg5SuDR3clv5Oohyci0YpfsYOUl0EyY3kjmnlQdxUXcH7GJKi2yxOKTsXCuoyqyfFqk4KUeMGqTqox15pPAeTwrDi3peLtPB4aNGmF9wJgDlScsFf5fHJDUX0HFpEvACnws42sfROJsb4LUgVWp7gqFKRe0XJAU2gdHWCiwiygmPK1WbwXGHTVQf+r3FuchvXw/fV40xsLRA6ONatC9X5LC31j2IcpzxMySH9StYqMgBcKagQbzIEkXSGGdpZ1p3bFd8b4QRfn3rogGdzbWe9W+Php7910vHOkteeMXP2bc+AYG+tXDoTSrB8a2PqU1v0CxAh80g7pFc3oAmfAVFMil8DAYZ0erOHonzVSk4w8yECKboD8GNhoDd2bXuHEeRTcHS7K1igBsKP6cX6oowA83VadAypLEF0xtNsO602+Z+cPqIVKqDCPINkClFSG4zBmaP5GXmanb6IoRLuet4rWvrBK01d9xXynX4CUl7/f2BpL02HplUTeG3fT7dRXaUK2V2PM95ccxAswAduFTFIsTOrRfvHDnQyRUFBjVaiIeUL1zbUPXYRyN3LulqW6UVH5XOSQemrG9liQvHoucOU9itAlklETlhTWSVJ/DBYqEzBvIQkM43LFYC9C9krBOG+d53zFUsGDD68S6DtPBuIioHtY0G60K5DDHS9SY0+hTJJu9pF2QGvtc/7dlpm61TR6EdfHDVKDxy5Ni7IEPw3MQzA65moFmAfjpDOI0SStFbQSHcCzldgUJ05YS3gPL2TUEqRDD+PXUtUItbD/ldy5vUJFogozIU7mwayN6Ft5O/QKlj4UKkkEeFDL1sFCDQfUPEU2pOm6XXSCJ3I5fI2HSq/YI1SjixFBkbF+5O6i5o/a5jBdNVA/R5Cox0rHizLs9b65Cs9f/OBRvmFX4jlBXkzoamN+YBYd8rO/sSs0MSqyt8cjyPfzHMQLMAHZUIgE4QPxADSjbkLtdBECSKGiIGO9w6uhEUJpic5BkXzr1SuHLE1NlbzKmmAPSEKZJ7pOVNcsymNAyGu7Nj6DbZwdKCnVtwQOQixOYwKpy0Iu42CcVBzkKymTN4MeQvYGNvkfLB+QWb9LRl7F1YgYT3JxNVueSRty5PygBJD9mf6khOkm6D+3Ktp7XODBBxs/57C6TmmaVB4BIDef/y0a3ug22dEXt6ucJmoFmAzhzh1UQOCGGNagV8pxmwDqaTmxusBy7Ba3ATQobkgp36S74X8IXU3hmL9YpFupiaxCMtt9CBcgJQESOqxn2hLEhKrvKnO3ypGPKcxm6Dip1GLVPWGzYZlNMjBe4Fa1QcJXYfI535MY8fWU6oPALlQ8nHK9wR0c2FGjU62FtYN3wYpF9n3TIId5ZY8W34yOZDDHk9hY6ntdIMLLntq1Ex+cbelAXz49Skny4eb1PVvpXu5unGMwNNm4HmArq6iwpJh7Mm1SJmL/8ER8xpuxWU6F5HAIXEI5JgJEwLaK+dyZPKGAp8QX9yvfa+sWmjtjkb8Qwdop9Riwq3w8TuMU+g2Z12cKGenFYl+9VL0PWYe+GCV0FzYBrXgvWKSNEPHMXsb8JiGp6AxySdC9nYG7ZE+ofMIfnTUbxA0Si+iMdBggmDhL6+VbzN7kzjlXHOr0fs+/2YHSqTKk9MKsT3UpIp0nZlPL3nKS/2GWgZoBtPh7Aka72ePtfv/CyvOleAgxHfI1V4KN0QFqdBLwj46hWOACPs0J7XiLHc7IY+5MAnlhBKk9ylx1UiFHGzQb7ve19SXKnGaJNmadHD3by6RaexfUn/UmxzYymi3gUeCOI/qVtk3+DQQX/+tPZeGKexvYAviuyv+YXJ9OI5ANMvpGvXfsCX3REClx4as3tu92N6qvF6UjWRGBZMv+we1PNAl+QMtBKgoxck2x+17eGmlamOmaxsc6l7WS/2OAjVsZdWeVo7uqqhBB3oSS4XrNGW0AIHPjM7OXkFbBFQfUDKN4kEJwEk+WnVGsOFMBitQus3+pXAPD+0UDtLTme9cWtmidBZqus5bOx+ClO1w99o5yimYeWRtj6ZPArMObsTdkXwMAB6S+bW4TCu7IM4RWcnZV2dfJQCDkSKLj8W604Wwyt7zjxPf4FmoJUA3RgtMf0wKirdOSy5qs7Dn7hGARoEG9DuUBwqhTdAA1FAQhLYmGY3BDMHv5J1goaZTzLehGnuki3GTZFRprxvdgawacCbmjznW7dtmSV8CexXjNpy8OY95zWSCIFtEAQXWhcYGKOZmS4LYw61lTzXHHB0IbU6zX6Jl9qFZGYnha+XV33+mUBPmOil9vYu5/G2NqBbzxWaFhDGJuSSUpx73tHKEBdK5ntRwvS6rhEIM/rEJpWIoTqpFk3RUSKboJ75C2yJmbLwEl02wvamNtwALDMApTRk4AFCBCG/ceZT5XZSw1o/s9ktZ5sEzRoRrUwFAU1QPVIv22UD0/e+q5XnNJwE2RIYIesZonWYdyx0xKOso57mmQHPDFxJM/BtArrDeQQK974t2hLFGGCTUq7IJhwJYKV8HasBkTV8BBOCsQ/wwZUXpIgdTUgqRwwcN24EwgqgT3Z4Z1cHEe3s/0CDADEa8Ar7wQYCGQmUCJLBGj3DFyQGxDT0NBgKmsONSBGJpivWWUKgngqQw+u+BFYRIvhxDjsjW84bfb2WtkBKXhjeUSYESQ/KHE8lP1ev2fOZZwYu8xm44ICOmITAotOHzYAOMiKjJneKaoLaGVrWRilfR8PFB1ZWFIlOHPDi7xj45pgaqxwsxjsCZLvP1qKHNfmlsWbs/0hctec16v2pEFOO6oQ1C4ZgN7J6XWKPTpy/cFNGxXGlVOEvnFtdJvXh4H/wzQKyXGjN6cOWsHgcW6lVovjUe6Yf8SW4PfKT+6RytDkQidwvOldDri5P88yAZwau4Bm44IDOXO97VyJFFS4DZFjouO9UK0zXstZJFWmz7amLZBy38z8S9iNIjNxe1zZTMEPADiWBIHDcbOJp9BKkNoYqf5HaZ/qj6XQ2II62B7ckpDba/Oih8hE7DKD/1EGtCIbH8nRsBRKniqLczcYSsvstrTzbPI3ciIwuLAme5pkBzwxcwTPQMkBHuwKpTSM6VCWnbXQquQQLHcepoJ4ebd/rerHEVUMkkz5fq9HrBJpVHNaAroM4iIk4UlnK/AnbgIsVj2vkQIlRakmDzzm6UjYEIndRxRwNvG5Jv/q1jJmNCHkIqKcKHKs9h9Er42dv0aS88NaRsawr7BiQx7Bp8DTPDHhm4EqdgRYAOrwzhvbRZaIxx5VH0Lw7HkI8mfC/IJo0k0TEDL67waZG+AF7jvwR4D6Tr1FRGooZKATcYT8wcoFvkIu4G0gGPsLvJzyMnvE8JLqlQTTcBV4e2xk7nc4BWSJIWXvg6xkDVjADkyQBao2x2z2Ite7kI/X14hFohqbF+M6poFDCU535YB1+Owlwxa1qrkjHBsVfAlw7D7DN0ejwWs9Bzwx4ZuBynIEWADpgRxYUbGpocaLMgwgaQvvcQ3KPSFJvb8fwiq6DmqIK1DgH1piM3g4btj8LBoAF3kFc0MA7YAtsbRLwOezc/YPE/kjadx9JREMKGkkaXCVjkNUlWDYHkqzGW0hwjleXyyqFTIUZYHEynJbm29mtARyHkEHcAgPe1MZgKM1qXhotAnxIG3ZLnuaZAc8MXJEz0AJAp2Yx6VPMEfP65GEmYzuD7JLIMECkIASjE7WIqSsQT67aWi3tMxGrqEZUes9rhSq5VBqbBgTv5yq04I7yUGQcU00BN+Q4+A64s4cg0Q0uVv7jCE8txjv5e+ssJrw+V0A/xj55tdBHNkOJby3AZxhsINgnIZ+Xbj3NMwOeGWj9Gejb8dQd/Q5rpvqMU2GLM+JzyoNa/x4t67EFgG5jIapxiKtQ8c4kRfEVCCM6FCMUm5r8XPAkEOhGJiz4E9EsXr5h0yxsxA1huYP1kDmkvaUqHiCuDHxSFIgXob24EJpRTwMiaPfr4l81N5OUGRl4V8u+D56rPTPgmQHHMzC4S+HfJm0eGlVIXdmSSt8FBxOe2zywFevWOr5rE4+2ANABqawN2sk9et5EbE/ubO3A1AeCHQrEK0aCiNDgLpJ0hSQB8hFY1kHrf4fT1K9NfJKL/XSse6gb1jalNEf3IrVM6wTcm21T73mrQQDK87M9GnS3W56Mi32yPOPzzMDFNQM+XnW/HL7v4bE7KFylj8yUVRr8pzUjPk9PuKgG2gJA5zmwQPETYiQC7girpQ4RanFvHar0xwa/KAONbgR2Imm6dvqYpCKBdNZnRDIBEA6DX9TTmjcDhxZpOZbM8vTAAgl7w4YA7zQBWcqR27yePVd5ZsAzA+fPwK+G7/vNyN0RAcgipBVX+r2+p/dj69yOHbkg89kyQLceIqhdAcVcIkwLyK5iQYmsIQZd4l/qxT6FpQH6VcNCp8IReQ2xKz2teTOQ+okUdzU2RqIyMom7QuKeOkk9JkgYPK5ob9Q+qXl38VzlmQHPDGjakC4FPxqcenVyZrBvNb+n6jqv5Udjf7l0HPl8Lp7paT1At34mbHCpZFQrhjngoppw7sssqUtMIkAkFga4abS0tHXP7AlYEtD/4XH1tAOfCuVl1krqLBZNcV/4SPkniSejR2o+umyfnZOneWagZTPg6yWZKqrrrtDv0vSEE09M2tKjfYmXiZ+ZCafoi9sGvLSjT8smtTWv/nYA3eEITx2SBFioRBQAQQigbwHTnZVPc9BJvSRrxCbFnUgpn4AwwamLPN+3qh+EuL40W7LBQJ1Lgpqk1oFXfBjU8zOE7SC4QnMWUbzQ5FVH8Uk5QCkdhahG92d4mmcGmjsDY7vmjYjO9/eq3ZPfYenRrrV1F/vXqVtE2Y8Hp8aGlp+qDPhgf9LmbIp/tagNjCx6adbavp0IlJFWU2eCdfntipbFM7ZoRLYXX0BAxxd66CsJ61cNcHE/uJH4UqpAoLmm4D0LA4DVdZwWEilorhgbPlJR+4hGxM1o1SB8pHiFXna5SbmrwGLoC4bNtgBMlMTu5zc0PDiEeRBjF8LnMEucj4HMMMqypQqo1KfGb6zHvnIyGVeoFGpdisi2X7f/TQ53MN3I18h16gEpAkWcl1KUkhEBvTx391jobs+r50T7GRgUWXhb30N3DTjoZapLL2qXVRby8o4+a49H8cWyP/liODI2Nu+xiduGRBaQ5Zhf3rGSsD+uHrHkSBwo3OzhsaT9deIWpkKZRlSU3XAiau5HaIUvlnYBAZ2Qd0ToEgWqN2gTBIsJUx0Apc3kQOBgh1JLU1QiBPjoteIkvMhPloQuQwSwcrZLYQ1IZLCSdAIsANik0DJU6eQ4n5IPC3qHOxL61OhXEKRm/Ti+QaskNJTCNJpcCKAr7bkUddO/E2qZ4Z84A+gcLoh7IQ8nOyMjYRgS7GqV7lw9FzkSYkfJ+dbLgM0ju/lPks+A6Q2hAHrKRkpzcOsmLV1u3s5z2pU6A1TH/tHg/b8asS/IV3599fWm0iq/zw8mvLi1H0B5Ec5Kl5CKG3oeeWLSVp0bkcZ+YlFG3AtbB2zLRS7czNan4+kXZqwfHp2v1gS6PlDY7ieLJ+45ebFE811AQIdDJ1MKgZeqgTigeaP5BTFycbEeX9dQAPq8d0HIuy77M6xUMJfIJoQ3QD9ArxKzAHkS14MA3F/r1Ecq3vGpi4ZRDztEUKjRhNjh9WGO+DQUz6NDVdYZVwFRsgA08A2sqzgjYTmMjDRGRyYR5lMUG+G5zU7CxXicfQSBTgIAc85FpsFLXNB9b3Eco+usE89xzww0NgNjY3MfHrdrTGwuQFZbr5VV+R0vCX0npcdXhwiusYTXNdbJhfw82Lfm5j6Hnpq8NcBH1QqWn+7uvI6PrRu6KtOqTm8Tx9QhsPLB0bu/NyBddQsAlFf7sUj83/a+Z2tcQkoTb9Ts0y8goOMRJaOhiNb1sEbSYsiGTwAAIABJREFUSCFxkeAa5w1cpiwyxrIgsl4QQ2hi85J73t+t+1BIyp/WkZnGCagkB9zpVKxN0BOUDhGeJB6QAh3i+tDvK2aJ84HqZ3gRCqsnXHTReHCCQmOGi2SzFTiQek3K7+3XjXQ9bRkEFLNqJDtzMRLPR54ZcG8G2gVUzel+/C8Tt0YEVClnYMGZgI9Sk17Z1Rc0v2iZ9Hk9Mh8dvzWpnZLVsaXwfW7LwMUZcelFEe49t+OzRkbnPzJh+8jokyjTOQNUOFIc/uNFE1pi+Du+U7OONhfQsUOxtaVQTnu37gsTfXyNVpBmNm+BP8pHoMHAceewgcX5KWIjY/OadeuchzYmuGFJIK8ABI6qxCaclnVmRAHgho4blgG9B/jluAkOjHRw/OhyjdITys2IBc3JmOTcBQNfOpE36HC8loN298W0B8Th0BvWIS8xz6nCAevS8sbk7HnDnDeGEcLnQDrhCPU0zwy00gxgls5JyvzzhB0dA88q7hjK5YuD8T//ZsKZanauF2mbFJ/z1OTNvTtKcUp+tOXn/N7Zl/z7VaNaONz2gZV39k9/eOxOP2/dxNS0snN+z2wa9OI2R1XdW3izpl/eLEDHEQf2AXxEsqgiDxiGwCv47qxRXgfCl0vMuEacenepJspVDhs4ThovlCHWACqV4YZI1QhIBhgbnJzUNiKlDGhLRjDkj1yF/1PMed0HKEa97ocEVQ0bn9uhAAHyuo4VzYnRIHYoFQ0DbtwRIoV8vICv0OJFelrzULHc+TudQ6nDsbCqkYRLES+KQuGmwu/DobeXQaoyzYX7tbI8rY4yHWo9wCHcSYgXNigB7VskPkH2g6tZHMJ6zwB6r2u0dt0dTuoVdTDEr8bPu7ai2rvy4tgLX9KTPyEu95fD9k5JyPbWKWm+xRAXd381+XSl8598Wz9wTOiZV+esHh17Uo0ZX+iijPhH1w7LON0ixTOAfnPvjMcnbvW3APrZGm/Q/MP9yUeK296d0ERAx0OYvVUqCpntYkvpNSAMixv4k7SIxLZUC8YppYd6r9AmUhuausY67gCIUMl9bnJgJqvzJcvuF6LzUw0yISxO69xHJCLmPQH0NHGp1XqkUr0cpE/xUqZJYizJh6VTLgrNgV3EjgKmFvuaAUN6RFJkrr2YzzwUewg4FprCXHpjrUq+SnoW6SEZdPWCc/g5eXYB9EhR2eOnpS623JGUkyHyOOrWiFis3ZKMBP9B9uYGrp+BAfrgL8VLY0bpssJmtaMrtKz1emiu3hjDyF87JZSadYdL4iLMJQo3YzmeKAvml5wQUZYUUTKoSyHWE3EfmSWhpyv9auu9Qv3O+XvXentp+wvaZZwOq6tXzq1L4hHbcpCERxL1fs+gA8rHyLx9fTj+O19MbcsxNXbv3h1PPTp+x7SEE4obYcxLjnR9csOQvfktdWDOTsp6asqm+PAy9e2BdMooDp+fnrDiaMzWnMjGxvXtft5EQMf+RVYBGSJYaZTm0Yco8O0v2nAgEsuXAHQsaEo6YDsjaAExT2wS0YiCS7LgxozWuk1yAOisGaB57k6tJKvBxG6XLCc3O0kAKF+UJlgP/hppCRgz8MeDyPKjc9A0cJZtB+IZ4J6tgFEbr+VvgRulfyE1UVX5DqNDBJFwL/JoJmHAm+opZR/Dhkn2InpjkSDhIosrvSmeR1ijyzkMJDq0YmDnQkzIEdEnT50NKKnyHdSlqENAFea5v09tda0XWF9W5VtV6x3gA5TXc7yqxju7LHj5sdgF6d0OFLbHnYX+zGHr0/FUYkRZfkVAm/9QHQ7vQh782dCU+0fu7RgkPjC2vSuOxv7g60mEv1/IMTTpXnwlnp6yCV2Kukq30Ls9u2lgywGddC6vXbXqmuRMb51GlwmpN+0vbPfC1v4fH2jjzXETAZ1kgRSdQAXIOwVEiJcxqOGGyVb1M2EeAqS2HDoWiAVkKgA6eKoaZAWWKRV27BuWMrY8+j/VACOsXShvLPqWNMk5kyfkiYRWkkrMgoA2fbLSJDWrKqmbY6MQaM6OhnngKtZFKTNNckp/2THETWyCRoW9wp63rRIu6guSLKihUpDPm2BRbxEy8haauk64+TgXwWkzErNemb1G99dpWGFl53zR2DEuBdH80kywBDrxZt342tZpXoUV/idKQ3ad7LjwULfVmbYpKG7tc+je4SlY+ifPBP19y8B39lkKJV4ET90mQ5h/45LJ8dnKSIdeuPXzaQjS22Qk7twUtfjz0zewS1Nvnje+r6Djz78Z13JA5+439Mp4dupmvAtqJHzxjpWEPrp2+BcHu7kztm/vnCYCOgMBlKEgMLohnUnIhdlbXyNWp8r3LSPVi7cpnMLwRKNNnAsWOnoVpenmFBGh99BF6Odz6GKep4rknJzpSl7NCfgPm5Eu3H7OGOGpI1rZCZHNSEHn860yBszGAm692xT7S1vtCOsKDAlVQWCTzovw1AeDtc76R9Uha3Lfxb0JWTowX/Y95zXdMSsApn+TYX6Yf7oVTNfXWoTzwvBcJmzDU1M2QwX4KsmBpmF9Y4kb82HZdp33rnnz1vheU+91qCj871sGzU9LMEgYggz/NWPd+K65nMnBf24diOOrsuZy3uu4+KKpj969ZsXspEyVbrDwbMBPF00gXrTRq9rwhFfnrAF5LfkRNRbm2xdM3d4CHbr1s3x9y6IxsXlqeVOayPuXj96Rp5fiabvWdEC3HqvSusCuwGUDxEA8bDXCRLBYAQqeQ/IpRsTLpyimqfYgvyz99wSngVMUQsZokNEUM2KRULivxN0Y5q2iBjHugkOV7ULudiGFjMZ4OmEdj21NjsXZS0WXQrgse4X8vbZjYHLgrJLnultclOUh7XOJRDXbow5vic0epnsg+guUw9rzJ1VHbExWh5de9AdD/Kq/uGnxsCgigaWBvIdOhWGTdwo6iyYpzP8cT1lb56UHB8o6d67Wu6TKDxq9Q2CVsV/mQiYeumbjiS5pRe3gYQorAugB/ALW+fRcrddb+3o9sPwiivBukzfz/rXLZycdVxBWUBF475LxizMuakAfFZP34XXLkV2q6aqo9vnbxiGtJUf566StPxy8X7lG+f4cOhVx/aczs0pD2uTVGDdtGaDbjp2UitWi44ZqP1ssLko4BCxxCBYolPTPtQpsSd1WgtiFRSHGx7q0NNQ8LLNEyetNyl/cKGKY1m0QLxmLxVS3BkG0KH1vleCgC9aIeCrYJxJyqZdN4Cs6HL2kERY060r8ZDGizTa0S1M6d5fUjTLCtWT8+g5J9h+WC0kdw86DZ2S2iWLlTziZy6LdNSD9r5O2AOs8DagNc/LB/mQoFHjz0TF5Q6MK4sLKCiqCjpcEV9T4FpwJLK/2OXwqvHNw5ZzuxxAUU4AmyLdWOBlLA6dOlAb/b0+vbTmd3563smeHYvUJTlQoYwj3y2LamvMQMFr/mL7hzn7p+CG4Hu3Qa7t7/3nNCGfuh+bco7WviQ45s+Cmb4yXyHL+7x19IUZa5T7sC9G6EMGkeiuu9L/n60nLjl5ADHH0GK0L6OffQZVe4xjYhL4QsCYzl2pwCwO+K+5H60aq9IylEttpNuHjpJ6Rmzp3R8/m4BjmOXwOAkojulKdBNjFjBTUM6rKObj4WzjEtEAusYYxAFIj4J+gRQ0VkoQjajDw4C6saYx0AF2IL+UVQBDZWXIeUB0Jikk5e9FHRo+QfQ8uEI4wpZcLpX7fiD1/Hr9D2YyHT4ffvmAaeI2/XtFpwDqh6lU1XvZRfMDT1cnH/jZ5S5eQM96y8AlIqTWQ/eOBwojfrRj92MTtQyLz1dyXn/N5ePXIN/e2zJHzLXyDLmSXvxqx94GRe9j3qJviWCY7yvz0xAs5hqbe67lpG1EZhvlX40g5W+2z9EjXF7f335HbCsTIiOiCV+asTogoVXYT7vdVmdE/WTyp6GxbSjm/TUC3nnuY9+0v6Umy9IaR2O+28zKhgz7ksUJCw8+KHxZGPbUaANlWbEAe5PWxFRIoJPy1YcPqBhqSxKhhsmlA2SIU84VqomHXqW0gGFwGc9maQDQxHsFok25NuzTSIeWZOqlVrReHQoQePURPUVAnTD2uafwQdMKGif0TUC7S+IsiTLnlU/z7MbuoOaBCPPIrAm/4dKb7Lq8BnYsoKkb6wN4di3t1OA30q8gxRpVbHvz4umGk7LhrQJpaLWrrTe+lJD+4clTFRRxK0/L5dN0DWQZfm7MG5Y9a5BAOvZfS475lY1xf1eaffn7jN6NjTvrrOQBKq/xf2dX7rb29WI1aPrCXZ8PRH0U3pbrKKw/6v+393tnXo7iqzTD9QgE6aJL6sSgRFdGB0y9h2nkBjdhUZODCcapOwIrsMVfomlZsGMIHvxIL3ZC4iOc2oCESldAhwBRNCMWVXARJteKQrLsCyhnbiQ2ycYFo8tKzj0lGsI7iQ3bRKHOB0FP5kB06JxquNdYwF91dSh8Rs4eVrSgXLPE/rhn56q4mJKcm5AS+pVt4Ob6+eT2O9e9UFOhbR2q+vDNBr+/p5e9Td++wfRDuakZ25nUiznBztstkFZfS5JnHGuJb3afT6W7hpb7edYUVgZuzI3EzOHwOCjv896rVM5OyVKgOi9zru3v9ffMgpsvh+RfDwcjgs/+bu2pc1zy1WkMQff7/7Z0JfFTV2cYnBAghEEggIUBCQhJIwr5vYQfZVcSlarV+frZaa1v31qq4tFq11qXWXVtbP1dUBGTfCfsSCEtYsidAEvYEEsKe7//eM3NzM3NnkgwhDDDnx0/hzr3nnnvuzHve87zP+7x7okHS049eVHqRerTBEQVodcUEQUgXQcdzF+ptPdjy4y0Js9OjSs9eHp/JLYMORUQJ0kqiY5D4s1V6fHYVpcHQ426yZyKS+5MxVzOv7HrrW0I7SxY74ExttYJkS85Sq8ouPi+wNZ3zICLfqDnpquHDAnqwP4BNWDcNW0y6KZAI9BvSUNnNkPnJSgMLSCy7y28Gfj0GXa+7jUFvGi5rYS0y6OtmEty6ywM9U58dvJl0Ia4+UtboyaUDp+92BwHAyYpqdoJ6NBNi9xIO9fW5sPdEwJc74rDyXUKOaPsjIUQSL2XBqP4mwK1nqruLoAY92DsVWZLwwNLWTU6evYB8VQjIuCODU40Jyv9LwzbcFJcJYEUjoWZWetQflw484Ekle+ymLzaoeOZt89s2KVG7CsLm6/eH/nLuCCIlFz/RTRqeefu6NTd2xEm30qCB6T/c3Om/2+IAAC++fzd6qLlBx/qQ9UNckdY8xhLQUswiJArXMluQ0BHn0nnoUMvjp0j+jrGBhKR+LYmXqoEexIyRBH23G2iGANAkQEFYzJDMfql6qtlurCTlNaBUQnsniosZpQnyqn2K/Gyn24SHUweNOSEziMWGlYxRSUVQPwFGqPsBQchuihzHg0D8zm8sJQdtaxKF/SKlVHRdokaOo6qTIx2Cix/pu+3OLumgIvxQdxwKfnpZ/5V7nagDVTUkVgXUVn/eOb2Br3wNgN1BzMlIurvrHmgSeOt8PbKLA19b0/ObnbUdqK9qbLX+OXuaEZH5j/ZPSWhR5C9Yk4TRWbTAf/+xsRsJMqZ3JOXylREbftF1t40Y6nPopB+oy4ebOxeUeKiTTtrw9zcvSGhxzBaH8skpCnhmxQB0Ik2fsaYHWRH/OHALaRBWJP1CvR92x1BoNP/E5ZmQmht0nhgCIgZaIbz8E7w7drwkCrloUOsQQwd4UeEqrFXP+xyKz5Vb9sywFKZYCdpYt+jRUsiimg12PIk2sDjgZbM2YB/PYCIpVgd8XGylVOpdAa10vUtoLcDKonmrFdA4kmEz6MFWEo4uWU63rArg2tWMmmKm4WjSpLzGYfkvKBNCNPLPgzJ1jBCrzUJCLBSJ4Ir8VU21sXm0JWKgoOFV2mXW14z5wsI0Qi4o6F4DJfpig45DM0AIUO2m8443IW45y93MDpD0l4evGxm5X3fl5mS0Kz7th1wfuUUtG5NCUr4+PwyQtLZsQTW/17V+Ghk3QFXjYvZCArGZOetNWBdTDrS4YdoEtiOm9+Xat8jWaXXExr+25J9oMnVF3x/c2hiZ3qLWD34ycQVOtA6doeQONPfD7vYlTp6xRgMYF5P31ujV7F3UVexyvt3Z4aH5Q2rUSS2e7JZBx6OEjoKBUw3LC8c5cqj8S2CKchHVEhPWVPBo1TBhG98VIRTVQKjjJ2sZ6pUbljdtpuVophzFTSbLEUgniH2ABlwC9WBYadhZ7Bd2EKgBk8cWgcGwZrBgKBa8FSVXQAr+h+akG1uTNpaud0p4UG/A0LnLRUKLxmrLJaRctuktd1c1ryHd83dSnOySoRjDWapgawWY+C9pVqDhMM3J8ucvzAbcHmR1ydsEo2dgjFwyW2BNc7BBJSkCbo17jjUH80ECF9SlOo3hUVyUZUM1CT9cLxU5rvYW0PDc/T1SH+u/Dd4FbzrrWLPHFg1cnuem2jX5pUjo/QKpa99z9IYIzPzMdiOj9uGe14PZ7lN+7rwPpdd+MWtUrcTTLtfLAVxixqhWEYxTaRZrR2/r1TU9cbqdjRA18KmJm0ICrEmSkLtfXt2bdc7Z+Zf9ONHvjyYkJbSQWC6/vENl/ggAfLzF6QPWaMDkFr07dqVNpFcqRxNX+MPSy5ay4JZBx1rhpJdQmw3kSDOa2HHMOt8PcWAxYcWSagS/gu0/LjZRPjxlDDoGVzWcUyiJjvmfWEA4Gyo0itHHz+Ul4E1jK7kEH1yBxSKYVSbGXcw09lr7YuqASZUvBGPNUoGHbtfyN4p2o3jQaiWgb1+xsJhgPGhuQqCyWYQU0GAAsgMokT0BYwAm4r8qFRMoXDHKlQSjdTNrfyvzfzMwrDlyiUZ6vvmphqOMdtN7FTA6WwEMesuEKq+7Ck6YEJv73thVQWRgS6mBBq+v7QFi4MZzQXEBwPl9320TYvJUUR5S2+EUD4koJFqojtAtpvzJJQPmZERV8xaYki4hR3FmgTJW72uDJHc1L7x0p2HQ/zFm9S3xWTo3g3tp/oVVqIzI3pc7Yn+/0KmPCd7y3+uXUC5ZEdLZxPwrJe7FlbVD7r4UDx7c6NTfR68lHKLSiQHTPtsad/E6umqosKTYspDQoIwQkfkPt3R5bsVlmw23DDqPAmKAIi5/dBtt+iqwUFjAwEgBHEBpFFTNmZh4IBfHBHcQZPokkxNbaedTq+XVehc9d8b0rg4HxUMXYFQ+oB/MJSlLjlJfrBDZizQajM2gO/SkOftapqvy+jlRBuZEGcbxchdHZK5Y/xLtY8UuLlEfCcd/RsWLYGVlt3RJBQyqHFJdnXBXlzQKLwT7Syogr4VM9CcWDwJ7qdH9IwJP3ByfA0OxTdPShvXIM5Krtx0M/iBZvM7H+2+NCYZrLF+JsrO+Ty0b+J9tVYi6YPLYid/fcxdsSBjQ1D0h6TzveNNpO6PB5SGH1Gh4pif3bXOod9hB//rnAK+3Hmi5q9qaKl1CjiEs1TG4iIR4HgkxA5j7B082xjA1aaAl1pb7QNL4zfyhUO9Nb9204dlXRqybEp8V0AB3qvz0+XqfbY1/d1PXy54kaTpadfDvo9ay91KoC0+9/WALSlLsrI00sbgWx54ckDI5LrdBPcEAyG5Dx23yd+PgdLoYz6X7yF2Dzohwnws3i/IiAIvVG608TrF0Gr87tIuQLohJWhOLfMTKOysbhCkHRs/TiNUuWiX7bjsPm8heAZ9a4ftwaUT2tqGlAT5+qAA+uM/ANS07mZeAYHECJxE0ycFA6963+ZDEwXH4hL1FYznMTelQqIfaL1kgl8r9Y4IBf9iFEKcFKpGapTVpaKWxYdJ1cpgZ+mHFugbaxNjcd8euQqJae1afLYUtnhJmYeVgu8t5wLe6rVPWLQmZOhGC04EdvtjR4c8r+5L0/+2URWPak+8uvYCQzk5v//TyfvnOWcyoBZBO+bNOGW0DT6plQBZ9bQzJBS2pP5l29KIq5kCVe7x/StfQY838pH4QFnlZbviflvWvpj0lYZ0UR2sFNYsPGbC4k8T03hi9VqXI461sLmj52wWDndk7Skbc2Tn9oT6pcIG0x/LJLmr63Io+s9Lba//0uAbb8t7ue14YulF56IyPWPfUpP746bUy1v/tvvvJgSkEJFRvvBFYLpcLdbkIg66Gj6sOTEFEETyEQByS4lJUU/Nh8TdR0AWtJgRKoA8NRUlf1AwfqDep9s6qW2DKUQ8/kGJTD1fm0vZf8Y41bUIVBhS0p4GlgZ/8lygiJZAA7sWGoqeHaliZ5pKjll69XCFw+QPbhdYtIU2tIqi6nKJxaqVhbLo5Vn2qf4rDbv1+C/rUqJmsYVhn8CKZEA2QYaikDrEKqpGrCeRC4HIcavYNXOVGQ/0m/SdrdEEup3hItKX7vW70dMVdMiUu668j1kO5Y+S8q00FIbiW1bSYcDZUicib4rKC/M8o40s/yHt9uyv2qaUDoBLjxk6/Zf7QiHy+Baqt3d+K9EgXAk9/HLj5oT47AxtWINS6QSfxBE4bOl9dQ492CCrGF2btqT7nD/P92z7b7+uxOzLwhD4eRoVi8HMryGKt2jxhx2ffJtI3Su0AwBexBCJ4d3TOeHHoBlxvNY2Hy/wx0F+lmmeBgEHdmpD1WP+tOhKFN4oGwKcp8cA1zr5CSBk3rn8OB5bghLNzLt3xn3XKRErXKOryr5SEZ1f0c+OOrArdWx1hkeDrAYEVnmJ405LPb1zaqxWzKv3xPVyXH3YjTvrlkHK7aIPOEwB8i6W+YFUIwWcHWcZkQwo0sqE3f1yRWIQTTf25iCFOU2ZwlkHSAbWlkctdX5x6haRjsFgeEBHEgmMNiZ0qbp840bXUkEYhxMof1gNwIXBt+OCEW4tzhONIzBYDrZB9rDzyjQyJxYnBKF87tLusK6ZLSOq3AulI85G9CyOnUAaxBObK7QZ/n5wsET6z7RKEdvmzOpWmcXvwF3EhBu7m+CwkUnUtl7kZkffOHqlJcVXR+E2Oito3rF0+4um4uoIiaxfB7qB0w5NLBsKF4J+tm5TCZZwSl20jdbChDrl/7vCcInMxHOgfH05YEd+iSFsefBgJiG3pGd8g/9NKxUnbPZRzAgWVzp73mZ/VjuVh34mqMSLc4RFR+cQzB7YtUNsF/QmxLKSwVkfdF4nwf01cFhpQpq5Fg+yBecMWZ4fT7eMDUsgwUsfJuYUA+t2uGGeTODJqP4R0PWUUVfSpK/p97kRemGIjSNWjS+5f//zeE02SC1qs2ecmtdTZeKo83rv1wTdHryWkwXvkV0KpEwIkyGeSLFbltZzAk/JmYUACpnUOOdIt9Kh/g/NHT/ptPtDyP1vjdx9pzmoxOc6K0cMUWpgVftes0YgBVKdzu3OYJQZZzbwkwEacktIz9U+eq9/S/xQB6os26HisUpwIWMNlGg6OPJXSjqTboAnUDTuJW4o5M23M+rFMjcdSoJEdz1uiRtUYXDbt+SIPsm7xLPxcESxkWQJ2JziMdWYBc83EV/clPAD0xAaCcGvEINGbvPi242vZUhgb2xc47G0uW2Tm4p+pmj1Q6/KtMatboa0o4G+9aTtjyER3VG6hN2KekJHDmpwEKA9vWopBBzpvRBaoFo6hYYCLTzVE24vax2AIagCcjzc6NXGj8NC1c9bta0XAMM1JniFKYRqgIXAqa8TKvNZQksMDS1DiDfQ7hy05e8GXn6uqocM5gPIvCUXEge6lbm/7LxIF8AV5WKBz3c2UW2i2iX3J44sHQcOvfJHJv94btxKRd11ONutY4LhvJrIc/nnoRmTlyRRlKliEVu9rDRMRaN6kC+0Qkmf/mrS8Z6vDKFZiv1IPBd/z0yh90tRV0UHHY5sXt2tWEhNUzELCJWTf8GrgDn2Z2oGZcda56+NBjU4FNTp75oIPQvauzzR+yopCAtqQiHy1Fqp3/db67m9XI4SOxfxtnx0QPSFTUeuK16dv5thjYUNX5rUhDQ2dOOLMTCA+O0vF6+tc0ridDL1/2wO9Wh1m+W/ud5oqSGR4OZa0JnDCBovVlzAvb61Nk5PkXvAK2HjNzWx3EQZd5FA060ZQDmxBFZ9zMlAL+S9pMyxFeRUGHbkSVVTT2SUc5xaokZBFicsMdCO3uMIbppwCfixRUuKjV+080a4fJOog1sbW2BywAWJ69aawoyt88hyHD10MPY2+rZWElk9hif9jixPhj9udScDq93238wfjxe9NS6Wp1Eh6RI4R9/mN9d3W7quk0f+rnjvJHIGHziVMMfG0e2ePIJDoOBh+UW9ftwpai3L2wVL/vq47rJvQxmX39dg1qUNe+2bHMeVGtASjv3pvq1/NGZ5f4jRxkYwnEIOnE5Ob+53RNwoMGFZPyoGW7PoXZ7dFG9J0GTMOEoIdu5m4Ftbys3wjuPy2H8dMis3506DNKFCqk+Fp/Hd73LPL+7sI6/28SxprQAvDnPxhyYC1+yvmDR15cPYB4QdCGp9i8sFb6FwmsNxy5oLv1gMtnkvqazfPjvNpd4TL2TANiyzAilE+cG5Gu2r61/RDuThAf0LojeufVfNPLPfzbXFPLHElREPhPaLHpArf0y2NqljGF2ccG3x2AhjxLdW2DA3neryRW6ePqfKJ7E4gFDQpNpd3gRvBF4NXjO//yMLBusY6K8q46LyOLYrbBZbwNjkN/IdF5ftdMXnHA9ANZWIvwqATFAVaISIKLoHkiCNpxDhe4AuUu3WWCwxrCpBSucIUl9AvxB3GAgohUkv49DbTGQCj3/GVfUFt4hakZZHBSzYAkD1LI1FZqyaMnTUz7fTKOAhvYdqURcPaVWQDTdsV89sFQ0Ez1AMgnUryN/8lLBbRtBL0rJ0gp504AxjacllOm1X7WmMjsGjGhyfu+s6YVVpikdgjBNPHfzPh2Cn7FAHcJdJWO4ccU/FGNEPwcO+eNXqvlmKOrBVsZXKX+NRu9lEsIDPTBdsSgvzro9bckpBtC0IL3n88AAAgAElEQVSiMAVHPoLf+eyMqIITjatJm3lq0JZH+m1lR6+ejvUGyg3Iw7OJyWD6tk2Dz+Eyv1dW9/o0xRXt9d7uu18culFVhqI3usIhRdRF9YyvisXv3uqon69VWtY4n/wdqB1hQnCt7KIqqirj4LOeIXSMMSUYC7EHW0YIt+RMww+SO83JjCJ8XZ0kfr4nhB8e7b8Nx1bZZazw2xu6ufCj2ZONj869o0s6K3SLRqcaNWD7YvWZ5H82jI6/svKhgcPOzxYD90nKa33b9DEuyqHwdYoLPtYl9BjfKHZ7FH6CrQT0x6r/1+Hrm9nyTun5o82dgLO4CwxdkDG+zDgl3AjOqPoi4aDMTm/HcNCl2HHoYgw6mSyII7LZZ1BCZekq2iPmuTDlgjNAW9SJK5A64ErraUd2L9z4z6vUtXTxxO58lL9BdMeM5BnWP/ZAQDpAQ8DrBAAQaagzdRp3nsGda9BdmTp4M9n5uuuaUtiCfFF8bfwXUHJA9kHhBzB5wCDW35vtpwiDhQLwmwtbYlYWZUeQIWk6Algl74xZDW7Ap/yS2QI/OG8YVxlPBsT406DkR/ptV2aR00AzXlvb81ubSADwK34lDEsVeDReC2SxNKft/XOHYdlNBwDeQo29jsHFKpLJUoFn/XwSgVnWHt9qWnN6pl4HoI0ij3NTXPsPkjtf137vTfEsFVZThZtPCOH5FX1cw/rYONaY/m0PqguZ0RW5re/5aSS5u//bfdfwyHzC1OqNmD4RB3nYxxYPmrGnvbMTOM4yc0OH7J93SQcpVoxDZkBZMbxXPH0Aq0MnG81Iiwa+d23WGQ86a/f32qlXttp/PACcihiGswHwyn7dK/XB3jsaaPrvNNYh/HpWU4S9MPfdQg+r1RGTerTMjxrlaqlgboGV7pgx2tgzm8JOLYsCGpxhG8e63ifsIEOq73uBbLVjpxsB9CXlhpETNyU+G0qodKVdzJJAxtZfVvXh78vumgXGpb4DakDqnLzipq+s6YmfUVDij0roRXjoEDZ2fVdRcwcLAq0FwVuiiJh19V/sCLAM7iGBu+zFFewO0GcMOrXWPNDvht3IwsPAgMX11H/jy/HAv7NJSv6oIlmUETJ+0k2pOk1TCuk8C3sd9ZEHPoK7QxobnYfgYmSzEhxYflH8tGAurt/f6t7uu6bE57TwL+NXxw9A2Rd+k/wFQ0CK0IKsyK9TY3cerqIqZkDDs99OXsQO15ZH0xBlXTsHFmT268mLMI7qHGBoOHyPLEw0yhZ2CC76eEJSj1aHbCFNfo/K1bPkFjfl5GW55jmuzw5OBsMFOWWGMJ0HSvz/sbHr+xpHvkYNg85uQ80DBjH9WHPsBXsXMmNtlsiysSD08UWDth8yX9uMt8MNJ1ysZNF4DOr13DNrBFg52bYcNKITGDhux1LRuMFZHb4vO+f7yZbOIPUuHgFxgjdGr8aw2u1p7C5hYcYzxfC5kB9gOWcFur1Tpp5OxYry6ppeKCM6GwDcla8mL+mGDbWdgRON5UVbYsehIKCkl4ZvnNQhh5WGB+Rbp/ZwnMvbx6DDtjK+ffzrnyVkdmt1JLTxSVVTRe9WBULA4tm1EKBmVqXSlnZTos3wXPmKPtpvG5seXQKMOzKfnHPsVMNvUmP/rFl81S7CoMP32DOromYF/QGMwKFmgNhrTAm6rxcQDiwSFVwS4mGtqFR4zsSyUOWSWmuXooHXk+2JRRPE7oT8IX8VgEjtDxgYrBJl2tTdEVykIJyMTWPN8xeOcAI4En9we8kLhdIOr8aTm6jJL61YMiHhoK5DgqtSeGeJtdIr+Rq4/oF48kOajI2f/TODNsW1LCYnCDoUntpfV/cimXNA2wMk7mPoCSceLPXvFHL0aJk/ReZW7Q3DqMG/3ljQqjp8GG755ujVd3e1/py4JCmvzXNJ/bYfrAhCshXA7BJoVR4r58A5eWZ5v1KDeDrUwOcGbwIFVsZO2ydYXT8oDS8m9SEYa/J4Fsv/3bAEc6BMIQvS97uioaaYnuniIFuHf09aBkSrlhzuDjWCtarCrEiEliJEnaqZ5YgsLQNDMp7J5HcGoA/5unfYIdx2m2/uU3rWt/iUH+aPLQU7mxvjclhR1BSxz9h7vCmoy4KsCGfD/sPALQDxUc1L9IniTMw3PnKLxohhWWePg/TGluhfWxMYvzNuCXRP4Gm2dOp22MTvd8c8unAQIzcdAELnr45cS/xDfcqatCQ3/MF5Q6EGqSPXd8h9fdTasIBSbCtMWdB2xeNkzwTbCpqQSnBr6nf2kb5bqaZCvEee3RaEd7wp8BHl8W7vlEFX6stReqYBSnC7Dzf/46AUfeRcyLv7bFsCgo5Fpxqs3NtGHxIfXYRBZ0Kx0VR/PnNcNAD4avBiK5qWS4l7ToNfCMkaNBxJAP01QASkaBFrQE0b/r4qi4xbaqkn9HCWDbYCQp3U+oIYo1jkcG/Al2UM2vdWLFq58MEhQeKuojaOvVOUcOHqaHgfSxEHrYn+1FPWhA9BKmAlwgVkicKyo8IoJ6uueEbPsI8kbW3/ysofZUg8YPsRsgdiiWX+r9LG9/6zScvYmGOn+PZRBuy73TGfbOmkWCi8mOigYlAOrA+bZX7qWw6E4ArVdDKwLMCXykfmWrb5/96agH+nqq/RPz/XPw/bCB1CfoflcM4aPp/UB9dJGXSGERpw8rd9Un/da4dyshgqPxgd6MBYwHwnrmjK0aaSJ3mn6mR8apYrF4C7s0fDmkCtG91+n+HLKr9Y7XwfbBAMnyU5bV5a1Yfq9c46sTuOL/lgr1QrylRuQRUdVF0np/Msc9LbEV8F11JcexAMkipVKJWusG15xU0wYY54PV45qwWguRaQEPYn2xrWCXF+syJnpUUSEaG+oF89696C3jDQ8HzYuLDrMh0/HjRLGtFatd7w5JsLQm6dPta0wBCvkkwrXqv+dJjs38wfYsw/ILz8yYTl7P6I7jKBpBdBTueXx9uE3Q+ewyaABY8aLAPaFKI7ZBsVRt0KHGn2UmSC1Ed8Mx9ZlAi/86E+4DzWpBbcc56aGIz+beFJEeXHc2dj5/ikF2PQtd4w0xBdgF9QWUG2kPQiI5Kr3xCHF8uIm6zn1EBY7HynZB7VqGHNj+6RwkPI3kKXhM7IWiJpRBTkVPOiZQNZm/6VNbuH9uMz+8DsmCxO2hKFfZQILT1riuo474odj9HnoKwW9QTiwLWv4wZSlD5HithZHwpiaGdLp5uvYmvOBEPw+vfEpSjBKreXLeqD84fiH9Xu3IPRs78mZiXfJ5SKzvvOSmuPfJWOpAP7gIr0CjsMPRkrLz/+eUNwS9UwMEY45i8M2Tg5LhttXs3mWyDV6IwL/gneggQg+wbHkf/n+qWTO+aonz02gnSYr3bUWHktNvg4E0WgssKj0u5UXi6SubMzIudltgOnwkl0HICzIw/0SqX+n85eh0CJyIF6Efyudh0Owks14kj4mJ9dvywxvNDmwsvdCV08uiiRMrDGu/xl2Mbf9CYgYf15sh4gM0D+FIjH59s7Ysjgn0APvTUhI7r5Ccm519xeQoiIEHBTZ3EFSKXoMSjUheWE13fdlzcIHufQ7uic/uqI9URf1ScHSxs/umggIWjjiRGBJWOi950574Mb8dSgFGyu2jRgfwnJ3DVzFFvDPwxMGRW1X2epcjmfAt2cPl+f+AdfFVYFHQVCPmjCNxNv75zxm947QvzJiJSHwsozsQra4nKsOQvkC0l9eGUOo5YDF23Q9V4RqCo7LEoAwhwnycUaTNfsIFUXWouTTv1MPS4KJgBXupUDW5NvN643VEigEowjWZQYTRTYi3PFcUbXEFFcPY3T9Jnq8qCy7OqOYuh5XMD3EEvksEryWCxyTMgl5eqggYNoAZOmN0IaCKO7rnZUl3N1ae71ycTlNwBlauQNqAtwLWAv1O6tbk3InDo4Geqb1WWQqFcEzqCuvU6lYGAZArBQubk1v/CXVvVi+2/9Xlgs7YNOPNF/C7tphXiAG/CTxqGzItrl5CuF3v7jGBYku5GTgvTZJKlVrS7kx/zEkoEEUd14wJW/mEFJJmVw1eX81Ah+/nNTV6qmubFxYWxU7ATaMhosesZWHi0TRv/f1va0K37E0ktKKlwgPXoMPwQnnT/6ExE9/tvItaQjWQdp8YGN9+3OGHYASbmtyWLVz1RkxFvjM5SYD/Zx/4km5FgR1zWdHwqYgIwpcg5ryep9YbA2gS/sToYX+MKQDeNj9lp9+XILMN0N301UGzLjyawlMNOx/pA49VKrmGw04gmicFzTerOma/HlwYiDk7C3Y+X+da+dd3ZOI79MLdV89PbGrn9d3Rs5aNilQO3K4WSV4kulu+fMJ9VuXSjy155B1x8U9AOH/Vi6wCBs/DHuTUKF0IKTju6unluEoUERECYGgABoyWnMN9bQV/4ChA1UIlKLGluRJ+Pvpo6/6XurOKitcUaHXSbJupepcFU4yI3U1kE8cT5xOKeKG1X+mA5ZrogcgGJDMmEqSg8LlV7ySIMsFPcgL7QW81rVzZlbws6iq641HgQJHcp0XNUNWhueGht/DcooB1SZlxnxXFJ/uySXi5yD8bF5Lw9bH938uPZ1Erz4+12x72zqAm6r90zmJGRzBThAmvx+d+yv5w3VP8WIQGaH7adlhcjrATzBNdPzXED5/7mx6z8ri9CSM/Ls4E2AuVbpFfba+aFwbNx4OkwPdR6GtSswGnTY0+8nd562K9YIwtZorsAZnhm8mRxFo+MP6wMU5eXVvUwFx2/rlPmXoRtaNSlT/iwL24sre0MHUmMAbKHwN4iKTqPcdyJg/DcTAWdMBzawbSGLSucQZFxltcXmgor8bsFgWB+O5wPxfzxheUywVIzjFeD4k/ZFqVi7M8dG70WQkk2VOg5EznoD0uXYobxIHwvfwOeHbNLjw6zKTyxODAkoU/FhdRVGqLDU/6PNneltaLv8hJbFUFkEorE2n/SjgbBZZqZFEa1BPSIiUO7O42DQ/SWpTZ6OTmCmAxO50O25BAbd+NwYYkAYzCXQMyAJGlJkz+sWFsiifmPxxxUkLZOsXVxhgo19mf1dDLTtOH9n/eBeKI+LXdMgEUBwnHrOkThtuJCy4cJDuMSechf573mByAHiwaC5CmsLWoLCuFKDoU9AHtxenkL9mq131O9qNip1jDMZDEac5UE9oGxW0ONtJPdlqIDyfApVnAETtoUX5NdcxulekxzUpRUGHWJop1uFd3RVN/IPnxggBAAd6yw52/Dt9V3f3NCdzWltPTo8PHIsoT2oDtnRz0mPfHhR4lED0RBzP23KQqBq3DpuTfT1L6t6K5kwrPaAtoWkNQ1vtx9Mhk44gRwobBl9KqeeIyAAsD6MafEoE/x99BoIi+q+eL5Lsl0RHF0/LxE87K/uGucWNUVVZmZae5gSri908SnGFOOrE+TVmWA4GEoKMTteyBrG6vtIv23Kp+Y3BT/k3eQuLGbsWjgfMwfewpZIxVqPnPKfurzfV05gcc4n6P1o/63ETvX6FaBSD8wdBr/e8e5hASdJcE2sqC/qsyKvNZk7dmGDm+MzXxi6CcI7PQCIA80/tGAICWWOHXKEndP741aiKaSQE74baFUuzA5/on8KY9PBJSIK7yd3Ivjx6YQVhLgrd0X0uD7Q//NJfVkC2cS8Pz5Jl/oyBM/JSvX9cEtn4uemI1EHL7FBN94Zi5m9RDAZHUaXTzWfp5pNmUh8T5WkylXYaw6yFVDINYWnRam8VMwiyIyoLWpKh/j7mHL4LaZEbDYE5D1hEDGvCDG2G2xl04PRS88+FtSvoF1KfBUCj1bBQ5YcJf51yrYgaTsJGVi1H0eeXruKIC1WnrvDsUFYmHHiXHM7Bi9km1bmw7abNOTMKDDNJdKtj+iUdb+nmvN6RZ9GvoyUa/C31gDjFwXEjEE5dNKlFkVNnhntbzzlHjYAGr8J7vMzy/rnG+quEW98YcimhJZk6MgXAI/yj8sGks3I38HWkbICZ2/oy/eGyF49XPvvd0fzawfS1UYul+B2UbzY6DACN380YYXmrKkvFeuEpJXitNZk+NZzIXeSv45XyLcDP/EfG7rBX3ajH+MlUCEndcg1eFWyVgGL3zd7eFaRSTItG6mHeu94rH8KqsL0w3TkHm+Kmg1RRNUtwgb0CUlUmUJg5f+ZNYLKyy7GifDvt1MWUq9DOhT9Bj+il6aoC6/mvXFJaMHrqxrEbTD3HyvT4e/usudPiVtUOSeWmbSjQRpvSl6lY8M6vzZiHTtF9RGxd3Zv7DNww3VrzndyVV7YbxYMO1bm9+nEZWz4dF8DwCf1cDCjhe1D1IFOeN2cQ6FXXpOx8bXZfij4l3OGm2Yp62fWoUHnnsACQl7k4a1fUDE9Ct+Q4fN3zVAam7J3+NqwBkn9B6zAZOPsi6CKZrkwtQLOaCz4+JvkU7smBJhCOQcwB0MP+GOEO4Dj9623FGzUTD8KLY0FpqAykV3LXSEjx8Rjbdv0k8Idqv4GR4D7uRaMhYWqOFvWBlFkrPwU9t25+LeqXt1CyoMotWFMfKtugtXgwkONd2ySslti2TNTgtL6ZCLGgEDxNdCwpO+PS4LHoj2rUOU+Ten0YlJvQkm19fRQFP4wYAvMa5ATvnGApPwIb58+Ws/Xb9m4DEbgayPX2YptWgpLAlCVQVuDMQCk4nPpGiynztVHv+W9TZ1Jmfld3+1RgccxczhiUOMJDxpdy/bNj39+w9KuoapKtdjKn9IjyVYHn6npo3ELZLkwvsrKMIZX1/TAQ69pP3bnE1og+1SPXvIpEAFKJnrWqGP/v+q566mBm1s2xv5aK8Ei1avrxuCbA16FNeFtyk8ICd/fza/IfXfsjSOk6nxx42KluMk/ITX+buEQ0iZNTybk+PKwDbwv9Snz8O6mzipzRz8f0veTA7cQF+EIYyAiQqoaHRpJqOpk3HNUegCRdGFe8JY31vdAqgENL2WQebWZx5rDelJrDLTOV4avJ4LK0k5+MqlVsKGOVo5FGyWO9VGhKLAgKxxlC9fVSuvWoBMvRUAREyyOJHOl6SbinyqOChAEyAP+NeZJIA6tYcTDqfmQIO62Y8PfR/NLVgiLiPdiizG1jg2MPnOBqH1hheMmCzVbbyAwfARtRi0kICEdbxAH2dhwlrf9nwR7aawcsRMs4QMcb2I9QuAXLBv9Gaj3yqzzX1mWlP/u9LrKH2jni3XWwgCwM7kv/juIUECYRhY6K1wa9hP8/eA2rdKIJtKrGsAOz4gk+tUeEeVxCSJhScFe+DszjVwi5vK7XbHs5as519U5DRPwyYQVCIkoeAGrAd5N0E9dix1nGK+OWKdiWRzEs/toC9Xf48kqhNzyOoxmm8YhIyTPc15GxI0dc55K3KLIM1zCdhv33KijTZyN+NhNNq1HbOX03dEw21zklDt7Fhzz+XfMQW5QnYC7R5iR5Bdn51fzOFEByIs60YWrCK6S40OgVclVOvYDBfNDw/KGD46HrowdYiYAUw/22umnCSSwJJPFw4QcLDXPoVWdo2j//viVqCGqnzB1Of6+vudb680D4yyroGc6DRTf+cc90cRRjVEERAKeTsSga3sIi8+eI81Ivl9oxpeHx0L8tl/bQ2qPohB89D7fGr0KcostAO77SUoC+wA1WkKghEYI+davd54Qtykazuq77n9+AMQTL9fWWM5Z7O+eOcqFxg7n1q1Bx/qgnI4jeXyvxAnBeREMaNDISmdEaxdOC0D2zmlSk1M1EO2Ok5xiwVmLxHFWhiwoWkyYYxUkPk2faylIFjwEs8hplDM11lA+liGdYNmxiSwqcTdWFrMtF44NN1LLBnsFdK8iR4jBNW1qk8ElkOUllmtz1QHiybFS/B9GIsYa6gtdmPrydO7kuPW+fNO0tZDT2BlYo7i2AbEFAX1CzfEaaKj6fTpRlP+U74kSy+vrepI0iKWoxafHZM+6bV6/1taNMIZg2s5KYU88REoo3BxnJbrw2olfTd8TjakKbHj21ZHruuNoa4xj/HokyJMLQiZ2ECUmpB9te3OpFPGnZf3mZVY4JfT5yx67VcBN4exYHxdq7C4eeeGds/Xxw/FYsx/0Zhi0EBeXVPkRy9gH45J0eh/nE5eGWIkhdiY3lhheAHnRtqOyHCptdP+8YUtzBPJmVb6ne9rDfbeRbX+hvPzEGb/5meG4z6ZWzzi2ebfPgWyjppG16t9b40lZcjZ4HPAn0ApW4u9aiY+fTR9jRLGQY0PfRu3GeJxpu2MfXpCIdrxjh7A2H+y1Q2m98WoPlfo/vVxkh0HSHumX0loL/BaWBrywUpISHC93doRspjevWzMxNseWVCwn8vZZzu+bM9zZVep43Rp0GZcW2IXrgtesNNMVWIFJUkgIxxENV+WkMV5gwdSwN5WIwVxu/a/QGWmcGdJFznRsQOQEY8lrVbYVpzV+itT00RuuNwxuYBzuwqKCIo2x8gZ7BRTMOUFB/1yOrURZDHTbtHEay5WECs5KXaRmUdpC4iP4yckjcpBwKxsFlIEZeclBOYJpVrFT68ZFexyavhiY3sjpQcTZW1k6TLwojXWnnXvcB9CBkToZKKirNdgo/m9mhGmSjtujx+zCBydPRPVArOzTrQkQyIwdQlNDrYWkcHUQo0mwC0cV64+vzRYegw47Df0Q4A70mFD0Rf+PAAC54OoSfrTszdleQFVWR5ATQBpMLypPiQxMhoscdxcPSGkn6ijprGfyQhdkRyAh60zExkVX+kdsO76bsoAUWd27AXNAXhhoiGcx7QFpGqKIqmQzJxDDRMeGlHf+DrSNJuK93XZT9Ung13KfItkJCanRWf4nV8Fdoapnt1ZWGjh+/RfbXdVEJSj6+fVL9PwmfHO0InTxdxxzNHl+12ebllLgQxIZCBIgnuOzgN1/dv1SvhjqIyw+Xjz7JyZ26pBkgHilOQGSBo/WMXnKsUP9CIT9pxM3U4xbZytqH/nwrb79R4OEqlkXdW7QzQZR6RgK4zu+tJY8xtJFDXdaHhNwJuW/mhy51sDQ426wFrsw9shpICrEYxVHm6pAYCbG+tQku2Lx1UqDTe9yRyUMnZXm8B5L2kyNQV8ulhe9GsTZcdUdG8j+ga3C2oRIw43YCkBicWwsV9TCxuizJtFYyaRKX7jsXVjPAP3hveB9M3LxvrXkKXOHvXLXsjD4Sr09fHNWrCtFiMZxfmpyBLDys0krKO2oLuL3M+br611LNdWke+u5iKd/f/PCeJv2LLLmyIDo+2h1kgp+QqO2FSa1brPw3XTbxn6ZokUkJakidqxGZLtMjM1TYTrgWjz0xTkROkpOrjyYBkWClLMGDfnl1b1R4HPjEdAneHfcKp0+QQ/QUd7e0N3IAXejW7zdJwYg4qghzuVSBfDxJYl24mXGblnw3rpuFXEFSe4ViKYBIUdQGnUOcWA+jWuhERC0DmemR0FDNAVwcPMRfpgSl4lt1TNUqcRNbODN9U7DA3xVvrpxSayNO6TKOr+2pqdeUwJz/ECPVFL2GQD+PlK9QGGO2blfTl48PlqeQo2cN0vkAOvPFuS1Ueuh/KvjLDBfp8Y8VEN0i5wG2D5tmiJ7UNFW5LW5Ydp442Q6/t3zDDpRypT/CBWdhvUE38BlNm2Y4G1fVORG4ukn3CzK7I4NH5yYIUq/2DvCqnb0j0M7ZU+gcBtQIGrjBVbmPKE2DiyuymFjNEkaIi4KbcaxsQ/Y+Z2Yfmw0dp/BO1pVzPTBVEvmfKs1pxP6xATTLRQabD2QPQ/OzoBORN4A7b5FBuEtAg++mvOOlbd58fRANJjKSkHtJfDbuJWb1ewcn8jjj+D8LrzjJ4i9ygRgIGBA6waitoY/OKIQgkRUM2u2C79z3C5IKQRIjbcgdZCw3o0ds3UWnf4pb+zU+fpA6h9vTiDRH7K2+gg5ctyxTiFF+IPInqze23pJTluqeh491QgH7ab4LHLQKXegTsZqIJmCSox+efUfEEoltEWyXpuJqRIzBNeFwaBL46ITMl84mXigs+1i26YlsLCHRxbgrQPuo7uAgrFR6MaxcwQA4BqqqCM9v7a2B5QbdRocTej8jFNnAaYdafbwoiHr94fq/bC2sf4hVwuycXNcRkjAKWSb1J6W90K6EKiUYow43poj6Jv/bdTagQLRyOcYdIIuX+yI04Mu4EjPJCaT/WRj7wiMzgpB9eesoqZIDqC/Pz4mj/CmrgbBbxju410zR8JuJEqPPCfTou7ORKMddssPY9hdmY7H2cHnhmxkr6A76cz/l6kdAeucna+Oe55BRycL4yscQaSyGouAFxwP04b3ip8LXU8hyOAYEYmW9iNNzsUcU/hUBVrRbY8ZV0m9vXivlHBTBHk8dAKe2GKjFBdDInAqKBBoRqgleqylRUeTuzAMkHpEsliTsMX4yKTCOuqosFEgMpy9rMLp5jGjRgiM46xtes9yolDO50xuTcoSdT/YBLDGICXGmMFYCJC6lqR31vmVf3zBHbMpSaN+n4AhiDTBATf16dx+VoACckE1/VLp4+x5xMTjiIs66mngY6LFwa9at+mEO4iRHitrODczElmC9fmhxrGB1aLT/asekhuFkC8rBMJegCrUgeNGwDiwIZECViMHeWDzDsveBdFFzYNjWiM9oPqEKA3grMYaFI2U5MKW7OKNhHp9ivA9EScIDywFC0aqF8/X2eyBR4+PySXiyjKDSjvp/sAOzk6GX4hbDcRM1n69euVHTjbiZRnL18FDfaDnTlvhb4my/m1dT3JZMbiseQAsaBYSMITcQkzSWKsEaGtLYQgS5+TxOrs7x/HQYS6SNYpTz4DhRL62pgfOr34JWDxhdiieOmeJ+7K+JuWFzcuIhHRIwBMhXJ3bg8lmv0WSJ4XF6QS55j8P29C3NS6p1XlnX8Xaz9pZI+YV6sGL75xlGIMFpZ03nO881Pg9z6BD2EDaG6CZnw7FnXv9ShiBzhoh1oz51roZnA8lMSbh+q8AAA6QSURBVHqMfSk47Dj2GlxFNWxilzsl+qo3PH2S5pEUFxa5VuoT+iO8Gr1BWdkzXQw6jjCYPoiNaTVnUHJl0NUCA90wZkwlbEfvEM577nIbZ5w+YywJU5yqORZskuEpyQTccOIEqlIrw2bVNlIwK0Z8Df0NHaWPJiSNjtqrTC2///c2dfmrKGeZY7huT40iqKkfGL/MT7ckoDxlqr4CKQ0Gy+DwAixd0Wk/vHIqhOHB4beasuNBDAjEBTY8gwPOyYtzwnEGWZkYas9Wh6idRmYTPik2+kBpYzS8EBUxfTrNlJcrn44RAkKzltg9L+vNO2NXIVyuzA02Pbc48M313b7YUclHQUqhdcBJJH8PlAbsP9GYdC27uh+O06hCo6BGjh8Zj0Q3L36433bEWCKaljBRqPg+tbQ/bjXoCqdhTIkrQJm3Bi0h91l84P9gzUnsJDrKLodtEFsWJkQnenMh05VZFPhBchcioq4HwKfUREX5i1UBF5v47cLsdnbrH0vFO2NXdxOlBKtRVrdAxgeGoi5jq92IjNNGhCJQelDbteBGp0i2erB3qoi1aVsHHmHbweBfzx0KC7PKseknkC2FD6Ey0TjIG0fH5uGFiQYAz6QzzzPoVMxAlRdcggYAIni3c8SQKOLW/0iZZtkQ+girD1aiMaRJJ9Bm8NDh9imBXHg1OPJKKFyfEIK0u3/Q+OMXBLJQYU/rp5qopJ6EibnnU1x4xwY8Qnk5RVfnU3YMQECmgydTCballUoPhjNU4gSsFqYtP1lOVhC/BBVGyB9vs80AXicsF9xD7ZdjQRvkzhmjkUap9Rkiv5H8IKUEQugP2wExsUZqVs6GhPEi0Tyk8Wn8PvJKqCSJ8irogTr/zdFrYE8DUED8YHl4Z0O3txzEajBt2HHNfMtfMENcjo1zNOh43P+4btWwyHydOs1dANORtfoqtSN4MSvWiMj9BGxZe3hMZG9rly/EBJIOijmGF8TfgX1QMcNY60vU6PZUAtnYIahY5dAaJg1VSJFDYYRGU84JwN8U4fthd8y0XdFQy53Ns/E4kA5cmno+F5goxmB3CbsT1hVWZRbUYH8CXRVmXZ3JXMsMl7PYNITLRCjbKIZDYhGwG8gS4nFqReUWJLtRUaQ6Y1PnoCgAOUp/TYwg7UhzQuIqgOysH88z6Ji51G+E9C3fz3qCt1AKA+No2opyLHtmWPFlftDUHQXlACU3NvL4Aaz5L+4tJEiQkBbsjCp7LsDo8FhE8wsZFo2KrkdNYSviI+vAjsLQAccdXWMWAys/UmPykArU+wHz7QUbi13Trfg4/bTDoA83fT4BVcjGKtxsOad9q8Sgj3R6snkXV/lRagmRWKSqlPGlJ/WO+JXOEK/Fhwf9gM0m9RZ8BAd4ZNFgqNy12L+zroiaIjyrNvj8JvaeaHr3zJFKyhGFFlULFIgDC0WaIsq9HOSLgkN9waKFHR0a6UUoZMXAJLG5n5yFedqwP3RGWnso0uAnGE3sO5zC5XltXODRDn3XwgGI+cjX3BKfOSD8oC7fqPerOW4VjWWAPQEv4tU1PVntauH2hi4Q/yJFiFJHuvCW/iFsd8ijaNOzd9lU0BJtd7tbs0LPum1+hyBRNqfxImAuUfjip4xIdPmrwywaG7MXXTYVaVCds34QuUEmwYUb4XkGnbFTfAfmn2qYYDRJSKIxbeQK4c6Lq6t9c0GTVd6Q0dsFbMlZYi1CRNgQGMRR25ZaevxRUAlkSoTaAUxU4yChTkASoHYCp2DrwPRtzCqtYHyptFeYrG0XLLJRYDB28VXVp8BKP1mDouRSUSgOgqNjI0jAxkJR4FWfbFm4O9Wlvc02A3h55McjqKS8Nn7hoNt4Q1Xu/Ws6hUGNzoCNciOyh/KONyXZBCmlmnbixvlsCx7vD2/aKqjNA+K/Q5VZnB0BFk/wACwYpQEIM8AsFN+A6gd8YRettbsvJAoimSSs2+J+8jmwQ9m5BqwHuJPk4iPzwqcomcAoN10Y3HiWal5Cau6Y9nkAF11Djjb1E7TaOE6tEx9Gy1RkIKKwKwZ5elNZ82rezsVpLG8Qje7rvou58mWJLJd0J6w5cQLSel0YVkLEb4xaQxEMA2jjc/YCw0aHqxmbCfSKoUgCIimxeMcxsJf6dMIy+PVqSVAnrN4bNvn78Ur3xvESmRfLiJdMP7hsB7HOEEV0gw5eDGrsmNCvxodPDXyBfcTa8tyc1mGCxAyNLX+TBllovwc8fYKKYT3to5okr6bNskZN5Y63VRh0uYwExAKBU5AQoB/MNOc40hbBf0BmCHgqyUP/5pLoZCqPtX+9RFkVZ5EIAURJ09PoUERxF1jxFgZC2hR3Nw3JVnrma+gf5P5h0JFbwaCrjTBwMHTgSzEFuGxI9VLbd/3+ECKcNeUtuDcksuS/nrywV9ghY4Y9wALlpxH/wlXHxMQGFcHUXJobAd4N1YQ0cdOgqHEAsDU+nrACRFsFUfWPVIo5ZfYorSAolpmP796D1Ogq1mmKkyAPCfQBaxM7yB6CpYsh8XdNq/ICObdfbO/wcUpnZ1qMNbqji5PRUCOISu0kyl4j7YKizpKccBdWVXX1yx47qWoC4VUDwSq6Z/z0sCCrXXhgCfllC7PaOdNHmxyX88G4FTojky648I4ZJjLLeu+eZ9Axc6AfMAVxjQlgIpUFvuGiYWHhrYsqr0Xc5y632xtHUngIKkJXx85yMlOLCLtUTzbEWrkXBh3ghQgqXjAW1tGLh+sC8MLlQPB2gjBqeOD+OSssGGsceZLvOQf8x3Qp2rfGkrnIusagVQDUDj5j2nDP6VDxc+iTnUr06GoV1zbt7Wo8iCr322NWDbCJGVEv9KllA3HSa/1ZSfon4QXyH1AmTmuVv+daHACwEmlBCDbprGetc/FS2StgxGGXI4T7454Y8nRMY6Gmg7k5LnN09D6YgtAx6ZkFo+SM7+bCkH+nJBCYNb2kjg/C9ADQZ+05cbrhuQtSNhpDj19MdJH1u/SML54ylrGOR1X9241uv5/YJvlo5AqxGCizzr4KsXiCE9TVAoehegYrk2mf0IHeG5tkqFaKYEMs0mOmJ6uDnmfQSavJWiDJmRhf6N6Ay4ASLhpmGswda0vDeiLn4ohyYNAhOIqzoUFwyJTDhjQK1WKCERvI0vTEg6MF03AEebDXLBtIyoDRm6aJArkApKiRcBeohNHXmRtfa5QVTTEfodMwZtMOJf9oteXwTkk1kuYjyjYwcKiB5222GYCogG4tPHEFufDb+Gxrguvqw25PnuYjS7zR7R7cvpCtN0WRCGZKWQz5Hss3GWwkt7gJZn367hiId1sK8dYrB4eqcT8mELiGzEmejggEgEDtJtlWYwiuTgHraAbFprweZPDYoBPIvFBpE1gJogtbE0faqKu+LtNnYU1Kb43PIpkZchHfT+AsEeQq80PIisknoussqwD609TBm1gP/Hwv4ECAvCPOBWPKxXN4nkGH+QcTEcYINg5fGAaIs4ioeiw8eow1bix2X8Rvh5hIioOPQxPEDYcVTsU4urWT36IrUjRBe0A5MJrA37jDjo01hj8MzNT+QpLZ/qVVioBrAfQJ5xo1BvQOde1yDLozxQJOBncCbyGcSyYRUQHSjuiNP6aai46jvWaOEDb8Rdc0VWwe5t/s9EjyxbFuV9kEwAzp0/ogGTFUh2jke+5ImT/+HRYN+BjBENcifFfZVFyJj0MUhNKyUI+qvwhBcUGogBRfNJZB2L7Y3pEKU66f3cMMOtYZJ5fseWV82/azxFaR6ipkxKNpgnGLKAp4yGATlAPVFJB0RLjwbcN6W4JjzCwymXzFougCOE6GjutVxHRSkeeFcqN76GwUkCJwhG7YDZDlBNSOtAvCZOh8OVPRIrsKMQCAIMg8oC6AM7jzbQdYlV5Mx3DtHcRjfXHoxnu6pancQtxViva+sqb3yr1h195keJ/4Wp8BDzPoBDnT51mgosvGsZ4lvL/kTzrDl9W7I53nWLYYcQwxbjUZ+XYQDbxDYp7kZ+LYElQkngmX3I62qLrC++ZkeISO+frV+Z5wOfzC3JWCoaPaiOWF8+7YMNMASuwqUGjhTOG8OxfjxaALjeeIPB2QEfsP4CDTtCbHG10bRwhUvnXdmpFR1nr2ZB6SKfpVagc36rRdGxPmfcqreQY8zKAr/IRUGuwvCrdk0FB01LV55RKAb9SsnPnU+LZKSAA76Oyc2nrF3AuOI6gRIr0EAExFIrHLoChH90hhDQw6qa2te5twZtSQQPaprQEchKdPtJZu+XOpn6K2ZqNO+iFkNDVx0x1dREdQ4w+Eoa+taNp1cn/vTbwz4EEz4EkGHWtIdQiS/rG/eMokxAfHmmEjHjR99kNhaWHHgE1vHCq4jWmBUNAk0UYvlqQhMCIwfccArN4vcwKPHopOaDcJ9sLMMVLs7W9/jf6b4gaTO2ZRwvHMhXoU6EIKNUdqCtc4PHiNTp/3sa+iGfAkgw5kAbZA4QvKOuONEngE8nZMyPTk2cegsxrhmIPqOLO8xF2LsiS4ynJlWuO00gPizudbTh8T3MlZqNaTJ6RuxwY5jMy6snO+aJ7U7Z29d/POgEfMgEcZ9POW00XCM8EgSoQTQDzwCjPovFMccKGbunQPlShu1dZc+4pAnmGRYCpcQ08e8XXyDsI7A94ZuJwz4EkGnXkAYeAPWAQ2HQwdyMKZn3s5J63u722nYFH3A/De0TsD3hm4AmbAwww6EU6ILrDF8UaBXLzW/Ar4CnmH6J0B7wx4ygx4mEFnWiSfEz4fSUBoWroELjxlDr3j8M6Adwa8M+ARM+B5Bl1NCwYda660DzxioryD8M6Adwa8M+DpM+CpBt3T5807Pu8MeGfAOwMeNwNeg+5xr8Q7IO8MeGfAOwPuzYDXoLs3b96rvDPgnQHvDHjcDHgNuse9Eu+AvDPgnQHvDLg3A16D7t68ea/yzoB3Brwz4HEz4DXoHvdKvAPyzoB3Brwz4N4M/D/7dRlr8OerHwAAAABJRU5ErkJggg=="="OpenRAM"></a><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">sram_2_16_scn4m_subm.html</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Compiled at: 2019-01-03 13:39:31.087652</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">DRC: skipped</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">LVS: skipped</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Git commit id: 55b01255ef603a3e2b5c8630974818d79a2e8d96</p><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p><table id="data">
+<thead><tr><th>Type</th><th>Description</th></tr></thead>
+<tbody>
+<tr><td>WORD_SIZE</td><td>2</td></tr>
+<tr><td>NUM_WORDS</td><td>16</td></tr>
+<tr><td>NUM_BANKS</td><td>1</td></tr>
+<tr><td>NUM_RW_PORTS</td><td>1</td></tr>
+<tr><td>NUM_R_PORTS</td><td>0</td></tr>
+<tr><td>NUM_W_PORTS</td><td>0</td></tr>
+<tr><td>Area</td><td>0</td></tr>
+</tbody>
+</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p><table id="data">
+<thead><tr><th>Parameter</th><th>Min</th><th>Typ</th><th>Max</th><th>Units</th></tr></thead>
+<tbody>
+<tr><td>Power supply (VDD) range</td><td>5.0</td><td>5.0</td><td>5.0</td><td>Volts</td></tr>
+<tr><td>Operating Temperature</td><td>25</td><td>25</td><td>25</td><td>Celsius</td></tr>
+<tr><td>Operating Frequency (F)</td><td></td><td></td><td>not available in netlist only</td><td>MHz</td></tr>
+</tbody>
+</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing and Current Data</p><table id="data">
+<thead><tr><th>Parameter</th><th>Min</th><th>Max</th><th>Units</th></tr></thead>
+<tbody>
+<tr><td>DIN0[1:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>DIN0[1:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>DIN0[1:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>DIN0[1:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>DOUT0[1:0] cell rise</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
+<tr><td>DOUT0[1:0] cell fall</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
+<tr><td>DOUT0[1:0] rise transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>DOUT0[1:0] fall transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>CSb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>CSb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>CSb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>CSb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>ADDR0[3:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>ADDR0[3:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>ADDR0[3:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>ADDR0[3:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>WEb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>WEb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
+<tr><td>WEb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+<tr><td>WEb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
+</tbody>
+</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p><table id="data">
+<thead><tr><th>Corner Name</th><th>Process</th><th>Power Supply</th><th>Temperature</th><th>Library Name Suffix</th></tr></thead>
+<tbody>
+<tr><td>TT</td><td>Typical - Typical</td><td>5.0</td><td>25</td><td>_TT_5p0V_25C.lib</td></tr>
+</tbody>
+</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p><table id="data">
+<thead><tr><th>Type</th><th>Description</th><th>Link</th></tr></thead>
+<tbody>
+<tr><td>.sp</td><td>SPICE netlists</td><td><a href="sram_2_16_scn4m_subm.sp">sram_2_16_scn4m_subm.sp</a></td></tr>
+<tr><td>.v</td><td>Verilog simulation models</td><td><a href="sram_2_16_scn4m_subm.v">sram_2_16_scn4m_subm.v</a></td></tr>
+<tr><td>.html</td><td>This datasheet</td><td><a href="sram_2_16_scn4m_subm.html">sram_2_16_scn4m_subm.html</a></td></tr>
+<tr><td>.lib</td><td>Synthesis models</td><td><a href="sram_2_16_scn4m_subm_TT_5p0V_25C.lib">sram_2_16_scn4m_subm_TT_5p0V_25C.lib</a></td></tr>
+<tr><td>.py</td><td>OpenRAM configuration file</td><td><a href="sram_2_16_scn4m_subm.py">sram_2_16_scn4m_subm.py</a></td></tr>
+</tbody>
+</table>
\ No newline at end of file
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef
new file mode 100644
index 00000000..c9c2b943
--- /dev/null
+++ b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef
@@ -0,0 +1,12857 @@
+VERSION 5.4 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+  DATABASE MICRONS 1000 ;
+END UNITS
+SITE  MacroSite
+   CLASS Core ;
+   SIZE 215000.0 by 336100.0 ;
+END  MacroSite
+MACRO sram_2_16_scn4m_subm
+   CLASS BLOCK ;
+   SIZE 215000.0 BY 336100.0 ;
+   SYMMETRY X Y R90 ;
+   SITE MacroSite ;
+   PIN DIN0[0]
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  179000.0 51800.0 179800.0 52600.0 ;
+      END
+   END DIN0[0]
+   PIN DIN0[1]
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  200800.0 51800.0 201600.00000000003 52600.0 ;
+      END
+   END DIN0[1]
+   PIN ADDR0[0]
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  58000.0 264700.0 58800.0 265500.0 ;
+      END
+   END ADDR0[0]
+   PIN ADDR0[1]
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  58000.0 286700.0 58800.0 287500.0 ;
+      END
+   END ADDR0[1]
+   PIN ADDR0[2]
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  58000.0 304700.0 58800.0 305500.0 ;
+      END
+   END ADDR0[2]
+   PIN ADDR0[3]
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  58000.0 326700.0 58800.0 327500.0 ;
+      END
+   END ADDR0[3]
+   PIN csb0
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  10000.0 10000.0 10799.999999999996 10799.999999999996 ;
+      END
+   END csb0
+   PIN web0
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  10000.0 32000.0 10799.999999999996 32800.00000000001 ;
+      END
+   END web0
+   PIN clk0
+      DIRECTION INPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  48500.0 1400.0000000000057 49099.99999999999 11200.000000000004 ;
+      END
+   END clk0
+   PIN DOUT0[0]
+      DIRECTION OUTPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  172000.0 114800.00000000001 172800.0 117800.00000000001 ;
+      END
+   END DOUT0[0]
+   PIN DOUT0[1]
+      DIRECTION OUTPUT ;
+      PORT
+         LAYER metal2 ;
+         RECT  178800.0 114800.00000000001 179600.00000000003 117800.00000000001 ;
+      END
+   END DOUT0[1]
+   PIN vdd
+      DIRECTION INOUT ;
+      USE POWER ; 
+      SHAPE ABUTMENT ; 
+      PORT
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+   END
+   END    sram_2_16_scn4m_subm
+END    LIBRARY
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.py b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.py
similarity index 91%
rename from compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.py
rename to compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.py
index 1b26c11d..bd4df95d 100644
--- a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.py
+++ b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.py
@@ -14,5 +14,5 @@ netlist_only = True
 bitcell = "pbitcell"
 replica_bitcell="replica_pbitcell"
 num_rw_ports = 1
-num_r_ports = 1
-num_w_ports = 1
+num_r_ports = 0
+num_w_ports = 0
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp
new file mode 100644
index 00000000..f5eb553a
--- /dev/null
+++ b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp
@@ -0,0 +1,559 @@
+**************************************************
+* OpenRAM generated memory.
+* Words: 16
+* Data bits: 2
+* Banks: 1
+* Column mux: 1:1
+**************************************************
+*********************** "dff" ******************************
+* Positive edge-triggered FF
+.SUBCKT dff D Q clk vdd gnd
+
+* SPICE3 file created from dff.ext - technology: scmos
+
+M1000 vdd clk a_24_24# vdd p w=8u l=0.4u
+M1001 a_84_296# D vdd vdd p w=4u l=0.4u
+M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u
+M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u
+M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u
+M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u
+M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u
+M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u
+M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u
+M1009 vdd Q a_320_336# vdd p w=2u l=0.4u
+M1010 gnd clk a_24_24# gnd n w=4u l=0.4u
+M1011 Q a_280_24# vdd vdd p w=8u l=0.4u
+M1012 a_84_24# D gnd gnd n w=2u l=0.4u
+M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u
+M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u
+M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u
+M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u
+M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u
+M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u
+M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u
+M1020 gnd Q a_320_24# gnd n w=2u l=0.4u
+M1021 Q a_280_24# gnd gnd n w=4u l=0.4u
+
+.ENDS
+
+.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd
+Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff
+Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff
+Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff
+Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff
+.ENDS row_addr_dff
+
+.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd
+Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff
+Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff
+.ENDS data_dff
+
+* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+
+* ptx M{0} {1} p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
+
+* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+
+* ptx M{0} {1} n m=1 w=1.2000000000000002u l=0.4u pd=3.20u ps=3.20u as=1.20p ad=1.20p
+
+.SUBCKT pbitcell_1RW_0W_0R bl0 br0 wl0 vdd gnd
+Minverter_nmos_left Q Q_bar gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Minverter_nmos_right gnd Q Q_bar gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Minverter_pmos_left Q Q_bar vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
+Minverter_pmos_right vdd Q Q_bar vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
+Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+Mreadwrite_nmos_right0 Q_bar wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pbitcell_1RW_0W_0R
+
+.SUBCKT bitcell_array_16x2_1 bl0_0 br0_0 bl0_1 br0_1 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 vdd gnd
+Xbit_r0_c0 bl0_0 br0_0 wl0_0 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r1_c0 bl0_0 br0_0 wl0_1 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r2_c0 bl0_0 br0_0 wl0_2 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r3_c0 bl0_0 br0_0 wl0_3 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r4_c0 bl0_0 br0_0 wl0_4 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r5_c0 bl0_0 br0_0 wl0_5 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r6_c0 bl0_0 br0_0 wl0_6 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r7_c0 bl0_0 br0_0 wl0_7 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r8_c0 bl0_0 br0_0 wl0_8 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r9_c0 bl0_0 br0_0 wl0_9 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r10_c0 bl0_0 br0_0 wl0_10 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r11_c0 bl0_0 br0_0 wl0_11 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r12_c0 bl0_0 br0_0 wl0_12 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r13_c0 bl0_0 br0_0 wl0_13 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r14_c0 bl0_0 br0_0 wl0_14 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r15_c0 bl0_0 br0_0 wl0_15 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r0_c1 bl0_1 br0_1 wl0_0 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r1_c1 bl0_1 br0_1 wl0_1 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r2_c1 bl0_1 br0_1 wl0_2 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r3_c1 bl0_1 br0_1 wl0_3 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r4_c1 bl0_1 br0_1 wl0_4 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r5_c1 bl0_1 br0_1 wl0_5 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r6_c1 bl0_1 br0_1 wl0_6 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r7_c1 bl0_1 br0_1 wl0_7 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r8_c1 bl0_1 br0_1 wl0_8 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r9_c1 bl0_1 br0_1 wl0_9 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r10_c1 bl0_1 br0_1 wl0_10 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r11_c1 bl0_1 br0_1 wl0_11 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r12_c1 bl0_1 br0_1 wl0_12 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r13_c1 bl0_1 br0_1 wl0_13 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r14_c1 bl0_1 br0_1 wl0_14 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r15_c1 bl0_1 br0_1 wl0_15 vdd gnd pbitcell_1RW_0W_0R
+.ENDS bitcell_array_16x2_1
+
+* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+
+.SUBCKT precharge_1 bl br en_bar vdd
+Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS precharge_1
+
+.SUBCKT precharge_array_1 bl_0 br_0 bl_1 br_1 en_bar vdd
+Xpre_column_0 bl_0 br_0 en_bar vdd precharge_1
+Xpre_column_1 bl_1 br_1 en_bar vdd precharge_1
+.ENDS precharge_array_1
+*********************** "sense_amp" ******************************
+
+.SUBCKT sense_amp bl br dout en vdd gnd
+
+* SPICE3 file created from sense_amp.ext - technology: scmos
+
+M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u
+M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u
+M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u
+M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u
+M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u
+M1005 bl en dout vdd p w=4.8u l=0.4u
+M1006 a_48_304# en br vdd p w=4.8u l=0.4u
+
+.ENDS
+
+.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd
+Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp
+Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp
+.ENDS sense_amp_array
+*********************** Write_Driver ******************************
+.SUBCKT write_driver din bl br en vdd gnd
+
+**** Inverter to conver Data_in to data_in_bar ******
+* din_bar = inv(din)
+M_1 din_bar din gnd gnd n W=0.8u L=0.4u
+M_2 din_bar din vdd vdd p W=1.4u L=0.4u
+
+**** 2input nand gate follwed by inverter to drive BL ******
+* din_bar_gated = nand(en, din)
+M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u
+M_4 net_7 din gnd gnd n W=1.4u L=0.4u
+M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u
+M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u
+* din_bar_gated_bar = inv(din_bar_gated)
+M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u
+M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u
+
+**** 2input nand gate follwed by inverter to drive BR******
+* din_gated = nand(en, din_bar)
+M_9 din_gated en vdd vdd p W=1.4u L=0.4u
+M_10 din_gated en net_8 gnd n W=1.4u L=0.4u
+M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u
+M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u
+* din_gated_bar = inv(din_gated)
+M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u
+M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u
+
+************************************************
+* pull down with en enable
+M_15 bl din_gated_bar net_5 gnd n W=2.4u L=0.4u
+M_16 br din_bar_gated_bar net_5 gnd n W=2.4u L=0.4u
+M_17 net_5 en gnd gnd n W=2.4u L=0.4u
+
+
+
+.ENDS   $ write_driver
+
+.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd
+Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver
+Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver
+.ENDS write_driver_array
+
+* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+
+* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+
+.SUBCKT pinv_1 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_1
+
+* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+
+.SUBCKT pnand2_1 A B Z vdd gnd
+Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pnand2_1
+
+.SUBCKT pnand3_1 A B C Z vdd gnd
+Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pnand3_1
+
+.SUBCKT pinv_2 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_2
+
+.SUBCKT pnand2_2 A B Z vdd gnd
+Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pnand2_2
+
+.SUBCKT pre2x4_1 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd
+Xpre_inv_0 in_0 inbar_0 vdd gnd pinv_2
+Xpre_inv_1 in_1 inbar_1 vdd gnd pinv_2
+Xpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_2
+Xpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_2
+Xpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_2
+Xpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_2
+XXpre2x4_nand_0 inbar_0 inbar_1 Z_0 vdd gnd pnand2_2
+XXpre2x4_nand_1 in_0 inbar_1 Z_1 vdd gnd pnand2_2
+XXpre2x4_nand_2 inbar_0 in_1 Z_2 vdd gnd pnand2_2
+XXpre2x4_nand_3 in_0 in_1 Z_3 vdd gnd pnand2_2
+.ENDS pre2x4_1
+
+.SUBCKT pinv_3 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_3
+
+.SUBCKT pnand3_2 A B C Z vdd gnd
+Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pnand3_2
+
+.SUBCKT pre3x8_2 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd
+Xpre_inv_0 in_0 inbar_0 vdd gnd pinv_3
+Xpre_inv_1 in_1 inbar_1 vdd gnd pinv_3
+Xpre_inv_2 in_2 inbar_2 vdd gnd pinv_3
+Xpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_3
+Xpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_3
+Xpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_3
+Xpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_3
+Xpre_nand_inv_4 Z_4 out_4 vdd gnd pinv_3
+Xpre_nand_inv_5 Z_5 out_5 vdd gnd pinv_3
+Xpre_nand_inv_6 Z_6 out_6 vdd gnd pinv_3
+Xpre_nand_inv_7 Z_7 out_7 vdd gnd pinv_3
+XXpre3x8_nand_0 inbar_0 inbar_1 inbar_2 Z_0 vdd gnd pnand3_2
+XXpre3x8_nand_1 in_0 inbar_1 inbar_2 Z_1 vdd gnd pnand3_2
+XXpre3x8_nand_2 inbar_0 in_1 inbar_2 Z_2 vdd gnd pnand3_2
+XXpre3x8_nand_3 in_0 in_1 inbar_2 Z_3 vdd gnd pnand3_2
+XXpre3x8_nand_4 inbar_0 inbar_1 in_2 Z_4 vdd gnd pnand3_2
+XXpre3x8_nand_5 in_0 inbar_1 in_2 Z_5 vdd gnd pnand3_2
+XXpre3x8_nand_6 inbar_0 in_1 in_2 Z_6 vdd gnd pnand3_2
+XXpre3x8_nand_7 in_0 in_1 in_2 Z_7 vdd gnd pnand3_2
+.ENDS pre3x8_2
+
+.SUBCKT hierarchical_decoder_16rows_1 addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd
+Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd pre2x4_1
+Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd pre2x4_1
+XDEC_NAND_0 out_0 out_4 Z_0 vdd gnd pnand2_1
+XDEC_NAND_4 out_0 out_5 Z_4 vdd gnd pnand2_1
+XDEC_NAND_8 out_0 out_6 Z_8 vdd gnd pnand2_1
+XDEC_NAND_12 out_0 out_7 Z_12 vdd gnd pnand2_1
+XDEC_NAND_1 out_1 out_4 Z_1 vdd gnd pnand2_1
+XDEC_NAND_5 out_1 out_5 Z_5 vdd gnd pnand2_1
+XDEC_NAND_9 out_1 out_6 Z_9 vdd gnd pnand2_1
+XDEC_NAND_13 out_1 out_7 Z_13 vdd gnd pnand2_1
+XDEC_NAND_2 out_2 out_4 Z_2 vdd gnd pnand2_1
+XDEC_NAND_6 out_2 out_5 Z_6 vdd gnd pnand2_1
+XDEC_NAND_10 out_2 out_6 Z_10 vdd gnd pnand2_1
+XDEC_NAND_14 out_2 out_7 Z_14 vdd gnd pnand2_1
+XDEC_NAND_3 out_3 out_4 Z_3 vdd gnd pnand2_1
+XDEC_NAND_7 out_3 out_5 Z_7 vdd gnd pnand2_1
+XDEC_NAND_11 out_3 out_6 Z_11 vdd gnd pnand2_1
+XDEC_NAND_15 out_3 out_7 Z_15 vdd gnd pnand2_1
+XDEC_INV_0 Z_0 decode_0 vdd gnd pinv_1
+XDEC_INV_1 Z_1 decode_1 vdd gnd pinv_1
+XDEC_INV_2 Z_2 decode_2 vdd gnd pinv_1
+XDEC_INV_3 Z_3 decode_3 vdd gnd pinv_1
+XDEC_INV_4 Z_4 decode_4 vdd gnd pinv_1
+XDEC_INV_5 Z_5 decode_5 vdd gnd pinv_1
+XDEC_INV_6 Z_6 decode_6 vdd gnd pinv_1
+XDEC_INV_7 Z_7 decode_7 vdd gnd pinv_1
+XDEC_INV_8 Z_8 decode_8 vdd gnd pinv_1
+XDEC_INV_9 Z_9 decode_9 vdd gnd pinv_1
+XDEC_INV_10 Z_10 decode_10 vdd gnd pinv_1
+XDEC_INV_11 Z_11 decode_11 vdd gnd pinv_1
+XDEC_INV_12 Z_12 decode_12 vdd gnd pinv_1
+XDEC_INV_13 Z_13 decode_13 vdd gnd pinv_1
+XDEC_INV_14 Z_14 decode_14 vdd gnd pinv_1
+XDEC_INV_15 Z_15 decode_15 vdd gnd pinv_1
+.ENDS hierarchical_decoder_16rows_1
+
+.SUBCKT pinv_4 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_4
+
+.SUBCKT pinv_5 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_5
+
+.SUBCKT pnand2_3 A B Z vdd gnd
+Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pnand2_3
+
+.SUBCKT wordline_driver in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en_bar vdd gnd
+Xwl_driver_nand0 en_bar in_0 wl_bar_0 vdd gnd pnand2_3
+Xwl_driver_inv0 wl_bar_0 wl_0 vdd gnd pinv_4
+Xwl_driver_nand1 en_bar in_1 wl_bar_1 vdd gnd pnand2_3
+Xwl_driver_inv1 wl_bar_1 wl_1 vdd gnd pinv_4
+Xwl_driver_nand2 en_bar in_2 wl_bar_2 vdd gnd pnand2_3
+Xwl_driver_inv2 wl_bar_2 wl_2 vdd gnd pinv_4
+Xwl_driver_nand3 en_bar in_3 wl_bar_3 vdd gnd pnand2_3
+Xwl_driver_inv3 wl_bar_3 wl_3 vdd gnd pinv_4
+Xwl_driver_nand4 en_bar in_4 wl_bar_4 vdd gnd pnand2_3
+Xwl_driver_inv4 wl_bar_4 wl_4 vdd gnd pinv_4
+Xwl_driver_nand5 en_bar in_5 wl_bar_5 vdd gnd pnand2_3
+Xwl_driver_inv5 wl_bar_5 wl_5 vdd gnd pinv_4
+Xwl_driver_nand6 en_bar in_6 wl_bar_6 vdd gnd pnand2_3
+Xwl_driver_inv6 wl_bar_6 wl_6 vdd gnd pinv_4
+Xwl_driver_nand7 en_bar in_7 wl_bar_7 vdd gnd pnand2_3
+Xwl_driver_inv7 wl_bar_7 wl_7 vdd gnd pinv_4
+Xwl_driver_nand8 en_bar in_8 wl_bar_8 vdd gnd pnand2_3
+Xwl_driver_inv8 wl_bar_8 wl_8 vdd gnd pinv_4
+Xwl_driver_nand9 en_bar in_9 wl_bar_9 vdd gnd pnand2_3
+Xwl_driver_inv9 wl_bar_9 wl_9 vdd gnd pinv_4
+Xwl_driver_nand10 en_bar in_10 wl_bar_10 vdd gnd pnand2_3
+Xwl_driver_inv10 wl_bar_10 wl_10 vdd gnd pinv_4
+Xwl_driver_nand11 en_bar in_11 wl_bar_11 vdd gnd pnand2_3
+Xwl_driver_inv11 wl_bar_11 wl_11 vdd gnd pinv_4
+Xwl_driver_nand12 en_bar in_12 wl_bar_12 vdd gnd pnand2_3
+Xwl_driver_inv12 wl_bar_12 wl_12 vdd gnd pinv_4
+Xwl_driver_nand13 en_bar in_13 wl_bar_13 vdd gnd pnand2_3
+Xwl_driver_inv13 wl_bar_13 wl_13 vdd gnd pinv_4
+Xwl_driver_nand14 en_bar in_14 wl_bar_14 vdd gnd pnand2_3
+Xwl_driver_inv14 wl_bar_14 wl_14 vdd gnd pinv_4
+Xwl_driver_nand15 en_bar in_15 wl_bar_15 vdd gnd pnand2_3
+Xwl_driver_inv15 wl_bar_15 wl_15 vdd gnd pinv_4
+.ENDS wordline_driver
+
+.SUBCKT pinv_6 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_6
+
+.SUBCKT bank dout0_0 dout0_1 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd
+Xbitcell_array bl0_0 br0_0 bl0_1 br0_1 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 vdd gnd bitcell_array_16x2_1
+Xprecharge_array0 bl0_0 br0_0 bl0_1 br0_1 p_en_bar0 vdd precharge_array_1
+Xsense_amp_array0 dout0_0 bl0_0 br0_0 dout0_1 bl0_1 br0_1 s_en0 vdd gnd sense_amp_array
+Xwrite_driver_array0 din0_0 din0_1 bl0_0 br0_0 bl0_1 br0_1 w_en0 vdd gnd write_driver_array
+Xrow_decoder0 addr0_0 addr0_1 addr0_2 addr0_3 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 vdd gnd hierarchical_decoder_16rows_1
+Xwordline_driver0 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 wl_en0 vdd gnd wordline_driver
+.ENDS bank
+
+* ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+
+.SUBCKT pinv_9 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pinv_9
+
+* ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+
+* ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+
+.SUBCKT pinv_10 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+.ENDS pinv_10
+
+.SUBCKT dff_buf_2 D Q Qb clk vdd gnd
+Xdff_buf_dff D qint clk vdd gnd dff
+Xdff_buf_inv1 qint Qb vdd gnd pinv_9
+Xdff_buf_inv2 Qb Q vdd gnd pinv_10
+.ENDS dff_buf_2
+
+.SUBCKT dff_buf_array_2x1_1 din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd
+Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_2
+Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_2
+.ENDS dff_buf_array_2x1_1
+
+.SUBCKT pnand2_4 A B Z vdd gnd
+Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pnand2_4
+
+.SUBCKT pinv_11 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+.ENDS pinv_11
+
+.SUBCKT pand2_4_1 A B Z vdd gnd
+Xpand2_nand A B zb_int vdd gnd pnand2_4
+Xpand2_inv zb_int Z vdd gnd pinv_11
+.ENDS pand2_4_1
+
+.SUBCKT pinv_12 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_12
+
+.SUBCKT pinv_13 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+.ENDS pinv_13
+
+.SUBCKT pbuf_4_1 A Z vdd gnd
+Xbuf_inv1 A zb_int vdd gnd pinv_12
+Xbuf_inv2 zb_int Z vdd gnd pinv_13
+.ENDS pbuf_4_1
+
+.SUBCKT pinv_14 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+.ENDS pinv_14
+
+* ptx M{0} {1} n m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
+
+* ptx M{0} {1} p m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p
+
+.SUBCKT pinv_15 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
+.ENDS pinv_15
+
+.SUBCKT pbuf_16_2 A Z vdd gnd
+Xbuf_inv1 A zb_int vdd gnd pinv_14
+Xbuf_inv2 zb_int Z vdd gnd pinv_15
+.ENDS pbuf_16_2
+
+.SUBCKT pinv_16 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
+Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+.ENDS pinv_16
+
+* ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+
+* ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
+
+.SUBCKT pinv_17 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
+Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+.ENDS pinv_17
+
+.SUBCKT pbuf_8_3 A Z vdd gnd
+Xbuf_inv1 A zb_int vdd gnd pinv_16
+Xbuf_inv2 zb_int Z vdd gnd pinv_17
+.ENDS pbuf_8_3
+
+.SUBCKT pinv_18 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_18
+
+.SUBCKT pinv_19 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
+Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
+.ENDS pinv_19
+
+.SUBCKT replica_pbitcell_1RW_0W_0R bl0 br0 wl0 vdd gnd
+Minverter_nmos_left Q vdd gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Minverter_nmos_right gnd Q vdd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Minverter_pmos_left Q vdd vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
+Minverter_pmos_right vdd Q vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
+Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+Mreadwrite_nmos_right0 vdd wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS replica_pbitcell_1RW_0W_0R
+
+.SUBCKT replica_pbitcell bl0 br0 wl0 vdd gnd
+Xpbitcell bl0 br0 wl0 vdd gnd replica_pbitcell_1RW_0W_0R
+.ENDS replica_pbitcell
+
+.SUBCKT bitcell_array_8x1_2 bl0_0 br0_0 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 vdd gnd
+Xbit_r0_c0 bl0_0 br0_0 wl0_0 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r1_c0 bl0_0 br0_0 wl0_1 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r2_c0 bl0_0 br0_0 wl0_2 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r3_c0 bl0_0 br0_0 wl0_3 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r4_c0 bl0_0 br0_0 wl0_4 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r5_c0 bl0_0 br0_0 wl0_5 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r6_c0 bl0_0 br0_0 wl0_6 vdd gnd pbitcell_1RW_0W_0R
+Xbit_r7_c0 bl0_0 br0_0 wl0_7 vdd gnd pbitcell_1RW_0W_0R
+.ENDS bitcell_array_8x1_2
+
+.SUBCKT pinv_20 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_20
+
+.SUBCKT delay_chain_1 in out vdd gnd
+Xdinv0 in dout_1 vdd gnd pinv_20
+Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_20
+Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_20
+Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_20
+Xdinv1 dout_1 dout_2 vdd gnd pinv_20
+Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_20
+Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_20
+Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_20
+Xdinv2 dout_2 dout_3 vdd gnd pinv_20
+Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_20
+Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_20
+Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_20
+Xdinv3 dout_3 out vdd gnd pinv_20
+Xdload_3_0 out n_3_0 vdd gnd pinv_20
+Xdload_3_1 out n_3_1 vdd gnd pinv_20
+Xdload_3_2 out n_3_2 vdd gnd pinv_20
+.ENDS delay_chain_1
+
+.SUBCKT pinv_21 A Z vdd gnd
+Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
+Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+.ENDS pinv_21
+
+* ptx M{0} {1} p m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+
+.SUBCKT replica_bitline_rw en out vdd gnd
+Xrbl_inv bl0_0 out vdd gnd pinv_21
+Mrbl_access_tx vdd delayed_en bl0_0 vdd p m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
+Xdelay_chain en delayed_en vdd gnd delay_chain_1
+Xbitcell bl0_0 br0_0 delayed_en vdd gnd replica_pbitcell
+Xload bl0_0 br0_0 gnd gnd gnd gnd gnd gnd gnd gnd vdd gnd bitcell_array_8x1_2
+.ENDS replica_bitline_rw
+
+.SUBCKT control_logic_rw csb web clk s_en w_en p_en_bar wl_en clk_buf vdd gnd
+Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array_2x1_1
+Xclkbuf clk clk_buf vdd gnd pbuf_4_1
+Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_18
+Xand2_gated_clk_bar cs clk_bar gated_clk_bar vdd gnd pand2_4_1
+Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2_4_1
+Xbuf_wl_en gated_clk_bar wl_en vdd gnd pbuf_16_2
+Xbuf_w_en_buf we w_en vdd gnd pbuf_8_3
+Xand2_rbl_in gated_clk_bar we_bar rbl_in vdd gnd pand2_4_1
+Xand2_pre_p_en gated_clk_buf we_bar pre_p_en vdd gnd pand2_4_1
+Xinv_p_en_bar pre_p_en p_en_bar vdd gnd pinv_19
+Xbuf_s_en pre_s_en s_en vdd gnd pbuf_8_3
+Xreplica_bitline rbl_in pre_s_en vdd gnd replica_bitline_rw
+.ENDS control_logic_rw
+
+.SUBCKT sram_2_16_scn4m_subm DIN0[0] DIN0[1] ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] csb0 web0 clk0 DOUT0[0] DOUT0[1] vdd gnd
+Xbank0 DOUT0[0] DOUT0[1] BANK_DIN0[0] BANK_DIN0[1] A0[0] A0[1] A0[2] A0[3] s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank
+Xcontrol0 csb0 web0 clk0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw
+Xrow_address0 ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] A0[0] A0[1] A0[2] A0[3] clk_buf0 vdd gnd row_addr_dff
+Xdata_dff0 DIN0[0] DIN0[1] BANK_DIN0[0] BANK_DIN0[1] clk_buf0 vdd gnd data_dff
+.ENDS sram_2_16_scn4m_subm
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.v b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.v
similarity index 100%
rename from compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.v
rename to compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.v
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
similarity index 100%
rename from compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
rename to compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5V_25C.lib
similarity index 100%
rename from compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib
rename to compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5V_25C.lib
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
new file mode 100644
index 00000000..e75a83e4
--- /dev/null
+++ b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
@@ -0,0 +1,321 @@
+library (sram_2_16_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1v" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1 ,fF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("2.45605, 9.8242, 78.5936");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (DATA){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (ADDR){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    leakage_power () {
+      when : "CSb0";
+      value : 0.000172;
+    }
+    cell_leakage_power : 0;
+    bus(DIN0){
+        bus_type  : DATA; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        memory_write(){ 
+            address : ADDR0; 
+            clocked_on  : clk0; 
+        }
+        pin(DIN0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(DOUT0){
+        bus_type  : DATA; 
+        direction  : output; 
+        max_capacitance : 78.5936;  
+        min_capacitance : 2.45605;  
+        memory_read(){ 
+            address : ADDR0; 
+        }
+        pin(DOUT0[1:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : rising_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.079, 0.079, 0.079",\
+                   "0.079, 0.079, 0.079",\
+                   "0.079, 0.079, 0.079");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.079, 0.079, 0.079",\
+                   "0.079, 0.079, 0.079",\
+                   "0.079, 0.079, 0.079");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    bus(ADDR0){
+        bus_type  : ADDR; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        max_transition       : 0.4;
+        pin(ADDR0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(CSb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(WEb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 9.8242;  
+        internal_power(){
+            when : "!CSb0 & clk0 & !WEb0"; 
+            rise_power(scalar){
+                values("5.193773500000001");
+            }
+            fall_power(scalar){
+                values("5.193773500000001");
+            }
+        }
+        internal_power(){
+            when : "!CSb0 & !clk0 & WEb0"; 
+            rise_power(scalar){
+                values("5.193773500000001");
+            }
+            fall_power(scalar){
+                values("5.193773500000001");
+            }
+        }
+        internal_power(){
+            when : "CSb0"; 
+            rise_power(scalar){
+                values("0");
+            }
+            fall_power(scalar){
+                values("0");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.0"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0"); 
+            }
+            fall_constraint(scalar) {
+                values("0"); 
+            }
+         }
+    }
+
+    }
+}
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.gds b/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.gds
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diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.html b/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.html
deleted file mode 100644
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--- a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.html
+++ /dev/null
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---><a href="https://vlsida.soe.ucsc.edu/"><img src=/home/jesse/clones/PrivateRAM/compiler/datasheet/assets/vlsi_logo.png alt="VLSIDA"></a><a href="https://vlsida.github.io/OpenRAM"><img src=/home/jesse/clones/PrivateRAM/compiler/datasheet/assets/openram_logo_placeholder.png alt="OpenRAM"></a><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">sram_2_16_scn4m_subm.html</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">DRC: skipped</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">LVS: skipped</p><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p><table id="data">
-<thead><tr><th>Type</th><th>Description</th></tr></thead>
-<tbody>
-<tr><td>WORD_SIZE</td><td>2</td></tr>
-<tr><td>NUM_WORDS</td><td>16</td></tr>
-<tr><td>NUM_BANKS</td><td>1</td></tr>
-<tr><td>NUM_RW_PORTS</td><td>1</td></tr>
-<tr><td>NUM_R_PORTS</td><td>1</td></tr>
-<tr><td>NUM_W_PORTS</td><td>1</td></tr>
-<tr><td>Area</td><td>0</td></tr>
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-</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p><table id="data">
-<thead><tr><th>Parameter</th><th>Min</th><th>Typ</th><th>Max</th><th>Units</th></tr></thead>
-<tbody>
-<tr><td>Power supply (VDD) range</td><td>5.0</td><td>5.0</td><td>5.0</td><td>Volts</td></tr>
-<tr><td>Operating Temperature</td><td>25</td><td>25</td><td>25</td><td>Celsius</td></tr>
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-<thead><tr><th>Parameter</th><th>Min</th><th>Max</th><th>Units</th></tr></thead>
-<tbody>
-<tr><td>Cycle time</td><td>2</td><td>3</td><td>4</td></tr>
-<tr><td>Access time</td><td>2</td><td>3</td><td>4</td></tr>
-<tr><td>Positive clk setup</td><td>2</td><td>3</td><td>4</td></tr>
-<tr><td>Positive clk hold</td><td>2</td><td>3</td><td>4</td></tr>
-<tr><td>DIN0[1:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>DIN0[1:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>DIN0[1:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DIN0[1:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DIN1[1:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>DIN1[1:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>DIN1[1:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DIN1[1:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] cell rise</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] cell fall</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] rise transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] fall transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DOUT2[1:0] cell rise</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
-<tr><td>DOUT2[1:0] cell fall</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
-<tr><td>DOUT2[1:0] rise transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DOUT2[1:0] fall transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb1 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb1 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb1 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb1 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb2 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb2 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb2 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb2 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR1[3:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR1[3:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR1[3:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR1[3:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR2[3:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR2[3:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR2[3:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR2[3:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>WEb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>WEb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>WEb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>WEb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>AC current</td><td>2</td><td>3</td><td>4</td></tr>
-<tr><td>Standby current</td><td>2</td><td>3</td><td>4</td></tr>
-</tbody>
-</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p><table id="data">
-<thead><tr><th>Corner Name</th><th>Process</th><th>Power Supply</th><th>Temperature</th><th>Library Name Suffix</th></tr></thead>
-<tbody>
-<tr><td>TT</td><td>Typical - Typical</td><td>5.0</td><td>25</td><td>_TT_5p0V_25C.lib</td></tr>
-</tbody>
-</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p><table id="data">
-<thead><tr><th>Type</th><th>Description</th><th>Link</th></tr></thead>
-<tbody>
-<tr><td>.sp</td><td>SPICE netlists</td><td><a href="sram_2_16_scn4m_subm.sp">sram_2_16_scn4m_subm.sp</a></td></tr>
-<tr><td>.v</td><td>Verilog simulation models</td><td><a href="sram_2_16_scn4m_subm.v">sram_2_16_scn4m_subm.v</a></td></tr>
-<tr><td>.html</td><td>This datasheet</td><td><a href="sram_2_16_scn4m_subm.html">sram_2_16_scn4m_subm.html</a></td></tr>
-<tr><td>.lib</td><td>Synthesis models</td><td><a href="sram_2_16_scn4m_subm_TT_5p0V_25C.lib">sram_2_16_scn4m_subm_TT_5p0V_25C.lib</a></td></tr>
-<tr><td>.py</td><td>OpenRAM configuration file</td><td><a href="sram_2_16_scn4m_subm.py">sram_2_16_scn4m_subm.py</a></td></tr>
-</tbody>
-</table><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">*Feature only supported with characterizer</p>
\ No newline at end of file
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.lef b/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.lef
deleted file mode 100644
index 562ace7d..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.lef
+++ /dev/null
@@ -1,9314 +0,0 @@
-VERSION 5.4 ;
-NAMESCASESENSITIVE ON ;
-BUSBITCHARS "[]" ;
-DIVIDERCHAR "/" ;
-UNITS
-  DATABASE MICRONS 1000 ;
-END UNITS
-SITE  MacroSite
-   CLASS Core ;
-   SIZE 231500.0 by 299900.00000000006 ;
-END  MacroSite
-MACRO sram_2_16_scn4m_subm
-   CLASS BLOCK ;
-   SIZE 231500.0 BY 299900.00000000006 ;
-   SYMMETRY X Y R90 ;
-   SITE MacroSite ;
-   PIN DIN0[0]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  186200.0 8600.000000000002 187000.0 9400.000000000002 ;
-      END
-   END DIN0[0]
-   PIN DIN0[1]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  208000.0 8600.000000000002 208800.0 9400.000000000002 ;
-      END
-   END DIN0[1]
-   PIN ADDR0[0]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  56800.0 220500.0 57599.99999999999 221300.0 ;
-      END
-   END ADDR0[0]
-   PIN ADDR0[1]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  56800.0 242500.0 57599.99999999999 243300.0 ;
-      END
-   END ADDR0[1]
-   PIN ADDR0[2]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  56800.0 260500.0 57599.99999999999 261300.0 ;
-      END
-   END ADDR0[2]
-   PIN ADDR0[3]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  56800.0 282500.0 57599.99999999999 283300.0 ;
-      END
-   END ADDR0[3]
-   PIN csb0
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  7599.9999999999945 28200.000000000004 8399.99999999999 29000.000000000004 ;
-      END
-   END csb0
-   PIN web0
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  7599.9999999999945 50200.0 8399.99999999999 51000.0 ;
-      END
-   END web0
-   PIN clk0
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  36900.0 19600.0 37499.99999999999 29100.0 ;
-      END
-   END clk0
-   PIN DOUT0[0]
-      DIRECTION OUTPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  179200.0 68800.00000000001 180000.0 71800.00000000001 ;
-      END
-   END DOUT0[0]
-   PIN DOUT0[1]
-      DIRECTION OUTPUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  186000.0 68800.00000000001 186800.0 71800.00000000001 ;
-      END
-   END DOUT0[1]
-   PIN vdd
-      DIRECTION INOUT ;
-      USE POWER ; 
-      SHAPE ABUTMENT ; 
-      PORT
-         LAYER metal3 ;
-         RECT  181700.00000000003 131300.0 182300.0 131900.0 ;
-         LAYER metal3 ;
-         RECT  188500.0 131300.0 189100.00000000003 131900.0 ;
-         LAYER metal3 ;
-         RECT  181700.00000000003 149700.00000000003 182300.0 150300.0 ;
-         LAYER metal3 ;
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-         LAYER metal3 ;
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-         LAYER metal3 ;
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-         LAYER metal3 ;
-         RECT  181700.00000000003 186500.0 182300.0 187100.00000000003 ;
-         LAYER metal3 ;
-         RECT  188500.0 186500.0 189100.00000000003 187100.00000000003 ;
-         LAYER metal3 ;
-         RECT  181700.00000000003 204900.0 182300.0 205500.0 ;
-         LAYER metal3 ;
-         RECT  188500.0 204900.0 189100.00000000003 205500.0 ;
-         LAYER metal3 ;
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-         LAYER metal3 ;
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-         LAYER metal3 ;
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-         LAYER metal3 ;
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-         LAYER metal3 ;
-         RECT  181700.00000000003 260100.00000000003 182300.0 260700.0 ;
-         LAYER metal3 ;
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-         LAYER metal3 ;
-         RECT  181400.0 112000.0 182200.00000000003 112800.00000000001 ;
-         LAYER metal3 ;
-         RECT  188200.00000000003 112000.0 189000.0 112800.00000000001 ;
-         LAYER metal3 ;
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-         LAYER metal3 ;
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-         LAYER metal3 ;
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-      RECT  29200.000000000004 148400.0 28400.000000000004 149200.00000000003 ;
-      RECT  185200.00000000003 256399.99999999997 184400.0 257200.0 ;
-      RECT  29200.000000000004 165200.0 28400.000000000004 166000.0 ;
-      RECT  182800.0 198800.0 182000.0 199600.00000000003 ;
-      RECT  192400.00000000003 218000.0 191600.00000000003 218800.0 ;
-   END
-   END    sram_2_16_scn4m_subm
-END    LIBRARY
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.sp b/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.sp
deleted file mode 100644
index 3b8783d8..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm.sp
+++ /dev/null
@@ -1,767 +0,0 @@
-**************************************************
-* OpenRAM generated memory.
-* Words: 16
-* Data bits: 2
-* Banks: 1
-* Column mux: 1:1
-**************************************************
-*********************** "dff" ******************************
-* Positive edge-triggered FF
-.SUBCKT dff D Q clk vdd gnd
-
-* SPICE3 file created from dff.ext - technology: scmos
-
-M1000 vdd clk a_24_24# vdd p w=8u l=0.4u
-M1001 a_84_296# D vdd vdd p w=4u l=0.4u
-M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u
-M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u
-M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u
-M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u
-M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u
-M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u
-M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u
-M1009 vdd Q a_320_336# vdd p w=2u l=0.4u
-M1010 gnd clk a_24_24# gnd n w=4u l=0.4u
-M1011 Q a_280_24# vdd vdd p w=8u l=0.4u
-M1012 a_84_24# D gnd gnd n w=2u l=0.4u
-M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u
-M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u
-M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u
-M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u
-M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u
-M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u
-M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u
-M1020 gnd Q a_320_24# gnd n w=2u l=0.4u
-M1021 Q a_280_24# gnd gnd n w=4u l=0.4u
-
-.ENDS
-
-* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-
-* ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-
-.SUBCKT pinv_2 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pinv_2
-
-.SUBCKT dff_inv_2 D Q Qb clk vdd gnd
-Xdff_inv_dff D Q clk vdd gnd dff
-Xdff_inv_inv1 Q Qb vdd gnd pinv_2
-.ENDS dff_inv_2
-
-.SUBCKT dff_inv_array_2x1_1 din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd
-XXdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_inv_2
-XXdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_inv_2
-.ENDS dff_inv_array_2x1_1
-
-* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-
-.SUBCKT pnand2_1 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand2_1
-
-.SUBCKT pnand3_1 A B C Z vdd gnd
-Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand3_1
-
-* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-
-.SUBCKT pinv_3 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_3
-
-.SUBCKT pinv_4 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pinv_4
-
-* ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-
-* ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p
-
-.SUBCKT pinv_5 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-.ENDS pinv_5
-
-.SUBCKT pinvbuf_2_4_1 A Zb Z vdd gnd
-Xbuf_inv1 A zb_int vdd gnd pinv_3
-Xbuf_inv2 zb_int z_int vdd gnd pinv_4
-Xbuf_inv3 z_int Zb vdd gnd pinv_5
-Xbuf_inv4 zb_int Z vdd gnd pinv_5
-.ENDS pinvbuf_2_4_1
-
-.SUBCKT pinv_6 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_6
-
-.SUBCKT pinv_7 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-.ENDS pinv_7
-
-* ptx M{0} {1} n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p
-
-* ptx M{0} {1} p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p
-
-.SUBCKT pinv_8 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p
-.ENDS pinv_8
-
-* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-
-* ptx M{0} {1} p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p
-
-* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-
-* ptx M{0} {1} n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-
-.SUBCKT replica_pbitcell_1RW_1W_1R bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd
-Minverter_nmos_left Q vdd gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Minverter_nmos_right gnd Q vdd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Minverter_pmos_left Q vdd vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p
-Minverter_pmos_right vdd Q vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p
-Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mreadwrite_nmos_right0 vdd wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mwrite_nmos_left0 bl1 wl1 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mwrite_nmos_right0 vdd wl1 br1 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mread_access_nmos_left0 RA_to_R_left0 vdd gnd gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-Mread_access_nmos_right0 gnd Q RA_to_R_right0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-Mread_nmos_left0 bl2 wl2 RA_to_R_left0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-Mread_nmos_right0 RA_to_R_right0 wl2 br2 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-.ENDS replica_pbitcell_1RW_1W_1R
-
-.SUBCKT replica_pbitcell bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd
-Xpbitcell bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd replica_pbitcell_1RW_1W_1R
-.ENDS replica_pbitcell
-
-.SUBCKT pbitcell_1RW_1W_1R bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd
-Minverter_nmos_left Q Q_bar gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Minverter_nmos_right gnd Q Q_bar gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Minverter_pmos_left Q Q_bar vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p
-Minverter_pmos_right vdd Q Q_bar vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p
-Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mreadwrite_nmos_right0 Q_bar wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mwrite_nmos_left0 bl1 wl1 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mwrite_nmos_right0 Q_bar wl1 br1 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Mread_access_nmos_left0 RA_to_R_left0 Q_bar gnd gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-Mread_access_nmos_right0 gnd Q RA_to_R_right0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-Mread_nmos_left0 bl2 wl2 RA_to_R_left0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-Mread_nmos_right0 RA_to_R_right0 wl2 br2 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p
-.ENDS pbitcell_1RW_1W_1R
-
-.SUBCKT bitcell_array_8x1_1 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 vdd gnd
-Xbit_r0_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r1_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r2_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r3_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r4_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r5_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r6_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r7_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R
-.ENDS bitcell_array_8x1_1
-
-.SUBCKT pinv_9 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_9
-
-.SUBCKT delay_chain_1 in out vdd gnd
-Xdinv0 in dout_1 vdd gnd pinv_9
-Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_9
-Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_9
-Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_9
-Xdinv1 dout_1 dout_2 vdd gnd pinv_9
-Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_9
-Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_9
-Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_9
-Xdinv2 dout_2 dout_3 vdd gnd pinv_9
-Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_9
-Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_9
-Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_9
-Xdinv3 dout_3 out vdd gnd pinv_9
-Xdload_3_0 out n_3_0 vdd gnd pinv_9
-Xdload_3_1 out n_3_1 vdd gnd pinv_9
-Xdload_3_2 out n_3_2 vdd gnd pinv_9
-.ENDS delay_chain_1
-
-.SUBCKT pinv_10 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_10
-
-* ptx M{0} {1} p m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-
-.SUBCKT replica_bitline_rw en out vdd gnd
-Xrbl_inv bl0_0 out vdd gnd pinv_10
-Mrbl_access_tx vdd delayed_en bl0_0 vdd p m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Xdelay_chain en delayed_en vdd gnd delay_chain_1
-Xbitcell bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 delayed_en delayed_en delayed_en vdd gnd replica_pbitcell
-Xload bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vdd gnd bitcell_array_8x1_1
-.ENDS replica_bitline_rw
-
-.SUBCKT control_logic_rw csb web clk s_en w_en clk_buf_bar clk_buf vdd gnd
-Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_inv_array_2x1_1
-Xclkbuf clk clk_buf_bar clk_buf vdd gnd pinvbuf_2_4_1
-Xnand3_w_en_bar clk_buf_bar cs we w_en_bar vdd gnd pnand3_1
-Xinv_pre_w_en w_en_bar pre_w_en vdd gnd pinv_6
-Xinv_pre_w_en_bar pre_w_en pre_w_en_bar vdd gnd pinv_7
-Xinv_w_en2 pre_w_en_bar w_en vdd gnd pinv_8
-Xnand2_rbl_in_bar clk_buf_bar cs rbl_in_bar vdd gnd pnand2_1
-Xinv_rbl_in rbl_in_bar rbl_in vdd gnd pinv_6
-Xinv_pre_s_en_bar pre_s_en pre_s_en_bar vdd gnd pinv_7
-Xinv_s_en pre_s_en_bar s_en vdd gnd pinv_8
-Xreplica_bitline rbl_in pre_s_en vdd gnd replica_bitline_rw
-.ENDS control_logic_rw
-
-.SUBCKT pinv_12 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pinv_12
-
-.SUBCKT dff_inv_4 D Q Qb clk vdd gnd
-Xdff_inv_dff D Q clk vdd gnd dff
-Xdff_inv_inv1 Q Qb vdd gnd pinv_12
-.ENDS dff_inv_4
-
-.SUBCKT dff_inv_array_1x1_2 din_0 dout_0 dout_bar_0 clk vdd gnd
-XXdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_inv_4
-.ENDS dff_inv_array_1x1_2
-
-.SUBCKT pnand2_2 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand2_2
-
-.SUBCKT pnand3_2 A B C Z vdd gnd
-Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand3_2
-
-.SUBCKT pinv_13 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_13
-
-.SUBCKT pinv_14 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pinv_14
-
-.SUBCKT pinv_15 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-.ENDS pinv_15
-
-.SUBCKT pinvbuf_2_4_2 A Zb Z vdd gnd
-Xbuf_inv1 A zb_int vdd gnd pinv_13
-Xbuf_inv2 zb_int z_int vdd gnd pinv_14
-Xbuf_inv3 z_int Zb vdd gnd pinv_15
-Xbuf_inv4 zb_int Z vdd gnd pinv_15
-.ENDS pinvbuf_2_4_2
-
-.SUBCKT pinv_16 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_16
-
-.SUBCKT pinv_17 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-.ENDS pinv_17
-
-.SUBCKT pinv_18 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p
-.ENDS pinv_18
-
-.SUBCKT control_logic_w csb clk w_en clk_buf_bar clk_buf vdd gnd
-Xctrl_dffs csb cs_bar cs clk_buf vdd gnd dff_inv_array_1x1_2
-Xclkbuf clk clk_buf_bar clk_buf vdd gnd pinvbuf_2_4_2
-Xnand3_w_en_bar clk_buf_bar cs w_en_bar vdd gnd pnand2_2
-Xinv_pre_w_en w_en_bar pre_w_en vdd gnd pinv_16
-Xinv_pre_w_en_bar pre_w_en pre_w_en_bar vdd gnd pinv_17
-Xinv_w_en2 pre_w_en_bar w_en vdd gnd pinv_18
-.ENDS control_logic_w
-
-.SUBCKT pinv_20 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pinv_20
-
-.SUBCKT dff_inv_6 D Q Qb clk vdd gnd
-Xdff_inv_dff D Q clk vdd gnd dff
-Xdff_inv_inv1 Q Qb vdd gnd pinv_20
-.ENDS dff_inv_6
-
-.SUBCKT dff_inv_array_1x1_3 din_0 dout_0 dout_bar_0 clk vdd gnd
-XXdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_inv_6
-.ENDS dff_inv_array_1x1_3
-
-.SUBCKT pnand2_3 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand2_3
-
-.SUBCKT pnand3_3 A B C Z vdd gnd
-Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand3_3
-
-.SUBCKT pinv_21 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_21
-
-.SUBCKT pinv_22 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pinv_22
-
-.SUBCKT pinv_23 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-.ENDS pinv_23
-
-.SUBCKT pinvbuf_2_4_3 A Zb Z vdd gnd
-Xbuf_inv1 A zb_int vdd gnd pinv_21
-Xbuf_inv2 zb_int z_int vdd gnd pinv_22
-Xbuf_inv3 z_int Zb vdd gnd pinv_23
-Xbuf_inv4 zb_int Z vdd gnd pinv_23
-.ENDS pinvbuf_2_4_3
-
-.SUBCKT pinv_24 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_24
-
-.SUBCKT pinv_25 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p
-.ENDS pinv_25
-
-.SUBCKT pinv_26 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p
-.ENDS pinv_26
-
-.SUBCKT bitcell_array_8x1_2 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 vdd gnd
-Xbit_r0_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r1_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r2_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r3_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r4_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r5_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r6_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r7_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R
-.ENDS bitcell_array_8x1_2
-
-.SUBCKT pinv_27 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_27
-
-.SUBCKT delay_chain_2 in out vdd gnd
-Xdinv0 in dout_1 vdd gnd pinv_27
-Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_27
-Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_27
-Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_27
-Xdinv1 dout_1 dout_2 vdd gnd pinv_27
-Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_27
-Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_27
-Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_27
-Xdinv2 dout_2 dout_3 vdd gnd pinv_27
-Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_27
-Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_27
-Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_27
-Xdinv3 dout_3 out vdd gnd pinv_27
-Xdload_3_0 out n_3_0 vdd gnd pinv_27
-Xdload_3_1 out n_3_1 vdd gnd pinv_27
-Xdload_3_2 out n_3_2 vdd gnd pinv_27
-.ENDS delay_chain_2
-
-.SUBCKT pinv_28 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_28
-
-.SUBCKT replica_bitline_r en out vdd gnd
-Xrbl_inv bl0_0 out vdd gnd pinv_28
-Mrbl_access_tx vdd delayed_en bl0_0 vdd p m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-Xdelay_chain en delayed_en vdd gnd delay_chain_2
-Xbitcell bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 delayed_en delayed_en delayed_en vdd gnd replica_pbitcell
-Xload bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vdd gnd bitcell_array_8x1_2
-.ENDS replica_bitline_r
-
-.SUBCKT control_logic_r csb clk s_en clk_buf_bar clk_buf vdd gnd
-Xctrl_dffs csb cs_bar cs clk_buf vdd gnd dff_inv_array_1x1_3
-Xclkbuf clk clk_buf_bar clk_buf vdd gnd pinvbuf_2_4_3
-Xnand2_rbl_in_bar clk_buf_bar cs rbl_in_bar vdd gnd pnand2_3
-Xinv_rbl_in rbl_in_bar rbl_in vdd gnd pinv_24
-Xinv_pre_s_en_bar pre_s_en pre_s_en_bar vdd gnd pinv_25
-Xinv_s_en pre_s_en_bar s_en vdd gnd pinv_26
-Xreplica_bitline rbl_in pre_s_en vdd gnd replica_bitline_r
-.ENDS control_logic_r
-
-.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd
-XXdff_r0_c0 din_0 dout_0 clk vdd gnd dff
-XXdff_r1_c0 din_1 dout_1 clk vdd gnd dff
-XXdff_r2_c0 din_2 dout_2 clk vdd gnd dff
-XXdff_r3_c0 din_3 dout_3 clk vdd gnd dff
-.ENDS row_addr_dff
-
-.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd
-XXdff_r0_c0 din_0 dout_0 clk vdd gnd dff
-XXdff_r0_c1 din_1 dout_1 clk vdd gnd dff
-.ENDS data_dff
-
-.SUBCKT bitcell_array_16x2_1 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 wl0_8 wl1_8 wl2_8 wl0_9 wl1_9 wl2_9 wl0_10 wl1_10 wl2_10 wl0_11 wl1_11 wl2_11 wl0_12 wl1_12 wl2_12 wl0_13 wl1_13 wl2_13 wl0_14 wl1_14 wl2_14 wl0_15 wl1_15 wl2_15 vdd gnd
-Xbit_r0_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r1_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r2_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r3_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r4_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r5_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r6_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r7_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r8_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_8 wl1_8 wl2_8 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r9_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_9 wl1_9 wl2_9 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r10_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_10 wl1_10 wl2_10 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r11_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_11 wl1_11 wl2_11 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r12_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_12 wl1_12 wl2_12 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r13_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_13 wl1_13 wl2_13 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r14_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_14 wl1_14 wl2_14 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r15_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_15 wl1_15 wl2_15 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r0_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r1_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r2_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r3_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r4_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r5_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r6_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r7_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r8_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_8 wl1_8 wl2_8 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r9_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_9 wl1_9 wl2_9 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r10_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_10 wl1_10 wl2_10 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r11_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_11 wl1_11 wl2_11 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r12_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_12 wl1_12 wl2_12 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r13_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_13 wl1_13 wl2_13 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r14_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_14 wl1_14 wl2_14 vdd gnd pbitcell_1RW_1W_1R
-Xbit_r15_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_15 wl1_15 wl2_15 vdd gnd pbitcell_1RW_1W_1R
-.ENDS bitcell_array_16x2_1
-
-* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-
-.SUBCKT precharge_1 bl br en vdd
-Mlower_pmos bl en br vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mupper_pmos1 bl en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mupper_pmos2 br en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS precharge_1
-
-.SUBCKT precharge_array_1 bl_0 br_0 bl_1 br_1 en vdd
-Xpre_column_0 bl_0 br_0 en vdd precharge_1
-Xpre_column_1 bl_1 br_1 en vdd precharge_1
-.ENDS precharge_array_1
-
-.SUBCKT precharge_2 bl br en vdd
-Mlower_pmos bl en br vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mupper_pmos1 bl en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mupper_pmos2 br en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS precharge_2
-
-.SUBCKT precharge_array_2 bl_0 br_0 bl_1 br_1 en vdd
-Xpre_column_0 bl_0 br_0 en vdd precharge_2
-Xpre_column_1 bl_1 br_1 en vdd precharge_2
-.ENDS precharge_array_2
-*********************** "sense_amp" ******************************
-
-.SUBCKT sense_amp bl br dout en vdd gnd
-
-* SPICE3 file created from sense_amp.ext - technology: scmos
-
-M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u
-M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u
-M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u
-M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u
-M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u
-M1005 bl en dout vdd p w=4.8u l=0.4u
-M1006 a_48_304# en br vdd p w=4.8u l=0.4u
-
-.ENDS
-
-.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd
-Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp
-Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp
-.ENDS sense_amp_array
-*********************** Write_Driver ******************************
-.SUBCKT write_driver din bl br en vdd gnd
-* SPICE3 file created from write_driver.ext - technology: scmos
-
-M1000 a_44_708# a_36_700# bl gnd n w=2.4u l=0.4u
-M1001 br a_16_500# a_44_708# gnd n w=2.4u l=0.4u
-M1002 a_44_708# en gnd gnd n w=2.4u l=0.4u
-M1003 gnd a_8_284# a_16_500# gnd n w=0.8u l=0.4u
-M1004 a_36_700# a_20_328# gnd gnd n w=0.8u l=0.4u
-M1005 vdd a_8_284# a_16_500# vdd p w=1.4u l=0.4u
-M1006 a_36_700# a_20_328# vdd vdd p w=1.4u l=0.4u
-M1007 vdd en a_20_328# vdd p w=1.4u l=0.4u
-M1008 a_20_328# a_64_360# vdd vdd p w=1.4u l=0.4u
-M1009 a_48_328# en a_20_328# gnd n w=1.4u l=0.4u
-M1010 gnd a_64_360# a_48_328# gnd n w=1.4u l=0.4u
-M1011 a_40_228# en a_8_284# gnd n w=1.4u l=0.4u
-M1012 gnd din a_40_228# gnd n w=1.4u l=0.4u
-M1013 a_64_360# din gnd gnd n w=0.8u l=0.4u
-M1014 a_8_284# en vdd vdd p w=1.4u l=0.4u
-M1015 vdd din a_8_284# vdd p w=1.4u l=0.4u
-M1016 a_64_360# din vdd vdd p w=1.4u l=0.4u
-
-.ENDS
-
-.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd
-XXwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver
-XXwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver
-.ENDS write_driver_array
-
-.SUBCKT pinv_29 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_29
-
-.SUBCKT pnand2_4 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand2_4
-
-.SUBCKT pnand3_4 A B C Z vdd gnd
-Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand3_4
-
-.SUBCKT pinv_30 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_30
-
-.SUBCKT pnand2_5 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand2_5
-
-.SUBCKT pre2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd
-XXpre_inv_0 in_0 inbar_0 vdd gnd pinv_30
-XXpre_inv_1 in_1 inbar_1 vdd gnd pinv_30
-XXpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_30
-XXpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_30
-XXpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_30
-XXpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_30
-XXpre2x4_nand_0 inbar_0 inbar_1 Z_0 vdd gnd pnand2_5
-XXpre2x4_nand_1 in_0 inbar_1 Z_1 vdd gnd pnand2_5
-XXpre2x4_nand_2 inbar_0 in_1 Z_2 vdd gnd pnand2_5
-XXpre2x4_nand_3 in_0 in_1 Z_3 vdd gnd pnand2_5
-.ENDS pre2x4
-
-.SUBCKT pinv_31 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_31
-
-.SUBCKT pnand3_5 A B C Z vdd gnd
-Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand3_5
-
-.SUBCKT pre3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd
-XXpre_inv_0 in_0 inbar_0 vdd gnd pinv_31
-XXpre_inv_1 in_1 inbar_1 vdd gnd pinv_31
-XXpre_inv_2 in_2 inbar_2 vdd gnd pinv_31
-XXpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_31
-XXpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_31
-XXpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_31
-XXpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_31
-XXpre_nand_inv_4 Z_4 out_4 vdd gnd pinv_31
-XXpre_nand_inv_5 Z_5 out_5 vdd gnd pinv_31
-XXpre_nand_inv_6 Z_6 out_6 vdd gnd pinv_31
-XXpre_nand_inv_7 Z_7 out_7 vdd gnd pinv_31
-XXpre3x8_nand_0 inbar_0 inbar_1 inbar_2 Z_0 vdd gnd pnand3_5
-XXpre3x8_nand_1 in_0 inbar_1 inbar_2 Z_1 vdd gnd pnand3_5
-XXpre3x8_nand_2 inbar_0 in_1 inbar_2 Z_2 vdd gnd pnand3_5
-XXpre3x8_nand_3 in_0 in_1 inbar_2 Z_3 vdd gnd pnand3_5
-XXpre3x8_nand_4 inbar_0 inbar_1 in_2 Z_4 vdd gnd pnand3_5
-XXpre3x8_nand_5 in_0 inbar_1 in_2 Z_5 vdd gnd pnand3_5
-XXpre3x8_nand_6 inbar_0 in_1 in_2 Z_6 vdd gnd pnand3_5
-XXpre3x8_nand_7 in_0 in_1 in_2 Z_7 vdd gnd pnand3_5
-.ENDS pre3x8
-
-.SUBCKT hierarchical_decoder_16rows addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd
-Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd pre2x4
-Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd pre2x4
-XDEC_NAND_0 out_0 out_4 Z_0 vdd gnd pnand2_4
-XDEC_NAND_1 out_0 out_5 Z_1 vdd gnd pnand2_4
-XDEC_NAND_2 out_0 out_6 Z_2 vdd gnd pnand2_4
-XDEC_NAND_3 out_0 out_7 Z_3 vdd gnd pnand2_4
-XDEC_NAND_4 out_1 out_4 Z_4 vdd gnd pnand2_4
-XDEC_NAND_5 out_1 out_5 Z_5 vdd gnd pnand2_4
-XDEC_NAND_6 out_1 out_6 Z_6 vdd gnd pnand2_4
-XDEC_NAND_7 out_1 out_7 Z_7 vdd gnd pnand2_4
-XDEC_NAND_8 out_2 out_4 Z_8 vdd gnd pnand2_4
-XDEC_NAND_9 out_2 out_5 Z_9 vdd gnd pnand2_4
-XDEC_NAND_10 out_2 out_6 Z_10 vdd gnd pnand2_4
-XDEC_NAND_11 out_2 out_7 Z_11 vdd gnd pnand2_4
-XDEC_NAND_12 out_3 out_4 Z_12 vdd gnd pnand2_4
-XDEC_NAND_13 out_3 out_5 Z_13 vdd gnd pnand2_4
-XDEC_NAND_14 out_3 out_6 Z_14 vdd gnd pnand2_4
-XDEC_NAND_15 out_3 out_7 Z_15 vdd gnd pnand2_4
-XDEC_INV_0 Z_0 decode_0 vdd gnd pinv_29
-XDEC_INV_1 Z_1 decode_1 vdd gnd pinv_29
-XDEC_INV_2 Z_2 decode_2 vdd gnd pinv_29
-XDEC_INV_3 Z_3 decode_3 vdd gnd pinv_29
-XDEC_INV_4 Z_4 decode_4 vdd gnd pinv_29
-XDEC_INV_5 Z_5 decode_5 vdd gnd pinv_29
-XDEC_INV_6 Z_6 decode_6 vdd gnd pinv_29
-XDEC_INV_7 Z_7 decode_7 vdd gnd pinv_29
-XDEC_INV_8 Z_8 decode_8 vdd gnd pinv_29
-XDEC_INV_9 Z_9 decode_9 vdd gnd pinv_29
-XDEC_INV_10 Z_10 decode_10 vdd gnd pinv_29
-XDEC_INV_11 Z_11 decode_11 vdd gnd pinv_29
-XDEC_INV_12 Z_12 decode_12 vdd gnd pinv_29
-XDEC_INV_13 Z_13 decode_13 vdd gnd pinv_29
-XDEC_INV_14 Z_14 decode_14 vdd gnd pinv_29
-XDEC_INV_15 Z_15 decode_15 vdd gnd pinv_29
-.ENDS hierarchical_decoder_16rows
-
-.SUBCKT pinv_32 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_32
-
-.SUBCKT pinv_33 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_33
-
-.SUBCKT pnand2_6 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-.ENDS pnand2_6
-
-.SUBCKT wordline_driver in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd
-Xwl_driver_inv_en0 en en_bar_0 vdd gnd pinv_33
-Xwl_driver_nand0 en_bar_0 in_0 wl_bar_0 vdd gnd pnand2_6
-Xwl_driver_inv0 wl_bar_0 wl_0 vdd gnd pinv_32
-Xwl_driver_inv_en1 en en_bar_1 vdd gnd pinv_33
-Xwl_driver_nand1 en_bar_1 in_1 wl_bar_1 vdd gnd pnand2_6
-Xwl_driver_inv1 wl_bar_1 wl_1 vdd gnd pinv_32
-Xwl_driver_inv_en2 en en_bar_2 vdd gnd pinv_33
-Xwl_driver_nand2 en_bar_2 in_2 wl_bar_2 vdd gnd pnand2_6
-Xwl_driver_inv2 wl_bar_2 wl_2 vdd gnd pinv_32
-Xwl_driver_inv_en3 en en_bar_3 vdd gnd pinv_33
-Xwl_driver_nand3 en_bar_3 in_3 wl_bar_3 vdd gnd pnand2_6
-Xwl_driver_inv3 wl_bar_3 wl_3 vdd gnd pinv_32
-Xwl_driver_inv_en4 en en_bar_4 vdd gnd pinv_33
-Xwl_driver_nand4 en_bar_4 in_4 wl_bar_4 vdd gnd pnand2_6
-Xwl_driver_inv4 wl_bar_4 wl_4 vdd gnd pinv_32
-Xwl_driver_inv_en5 en en_bar_5 vdd gnd pinv_33
-Xwl_driver_nand5 en_bar_5 in_5 wl_bar_5 vdd gnd pnand2_6
-Xwl_driver_inv5 wl_bar_5 wl_5 vdd gnd pinv_32
-Xwl_driver_inv_en6 en en_bar_6 vdd gnd pinv_33
-Xwl_driver_nand6 en_bar_6 in_6 wl_bar_6 vdd gnd pnand2_6
-Xwl_driver_inv6 wl_bar_6 wl_6 vdd gnd pinv_32
-Xwl_driver_inv_en7 en en_bar_7 vdd gnd pinv_33
-Xwl_driver_nand7 en_bar_7 in_7 wl_bar_7 vdd gnd pnand2_6
-Xwl_driver_inv7 wl_bar_7 wl_7 vdd gnd pinv_32
-Xwl_driver_inv_en8 en en_bar_8 vdd gnd pinv_33
-Xwl_driver_nand8 en_bar_8 in_8 wl_bar_8 vdd gnd pnand2_6
-Xwl_driver_inv8 wl_bar_8 wl_8 vdd gnd pinv_32
-Xwl_driver_inv_en9 en en_bar_9 vdd gnd pinv_33
-Xwl_driver_nand9 en_bar_9 in_9 wl_bar_9 vdd gnd pnand2_6
-Xwl_driver_inv9 wl_bar_9 wl_9 vdd gnd pinv_32
-Xwl_driver_inv_en10 en en_bar_10 vdd gnd pinv_33
-Xwl_driver_nand10 en_bar_10 in_10 wl_bar_10 vdd gnd pnand2_6
-Xwl_driver_inv10 wl_bar_10 wl_10 vdd gnd pinv_32
-Xwl_driver_inv_en11 en en_bar_11 vdd gnd pinv_33
-Xwl_driver_nand11 en_bar_11 in_11 wl_bar_11 vdd gnd pnand2_6
-Xwl_driver_inv11 wl_bar_11 wl_11 vdd gnd pinv_32
-Xwl_driver_inv_en12 en en_bar_12 vdd gnd pinv_33
-Xwl_driver_nand12 en_bar_12 in_12 wl_bar_12 vdd gnd pnand2_6
-Xwl_driver_inv12 wl_bar_12 wl_12 vdd gnd pinv_32
-Xwl_driver_inv_en13 en en_bar_13 vdd gnd pinv_33
-Xwl_driver_nand13 en_bar_13 in_13 wl_bar_13 vdd gnd pnand2_6
-Xwl_driver_inv13 wl_bar_13 wl_13 vdd gnd pinv_32
-Xwl_driver_inv_en14 en en_bar_14 vdd gnd pinv_33
-Xwl_driver_nand14 en_bar_14 in_14 wl_bar_14 vdd gnd pnand2_6
-Xwl_driver_inv14 wl_bar_14 wl_14 vdd gnd pinv_32
-Xwl_driver_inv_en15 en en_bar_15 vdd gnd pinv_33
-Xwl_driver_nand15 en_bar_15 in_15 wl_bar_15 vdd gnd pnand2_6
-Xwl_driver_inv15 wl_bar_15 wl_15 vdd gnd pinv_32
-.ENDS wordline_driver
-
-.SUBCKT pinv_34 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p
-.ENDS pinv_34
-
-.SUBCKT bank dout0_0 dout0_1 dout2_0 dout2_1 din0_0 din0_1 din1_0 din1_1 addr0_0 addr0_1 addr0_2 addr0_3 addr1_0 addr1_1 addr1_2 addr1_3 addr2_0 addr2_1 addr2_2 addr2_3 s_en0 s_en2 w_en0 w_en1 clk_buf_bar0 clk_buf0 clk_buf_bar1 clk_buf1 clk_buf_bar2 clk_buf2 vdd gnd
-Xbitcell_array bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 wl0_8 wl1_8 wl2_8 wl0_9 wl1_9 wl2_9 wl0_10 wl1_10 wl2_10 wl0_11 wl1_11 wl2_11 wl0_12 wl1_12 wl2_12 wl0_13 wl1_13 wl2_13 wl0_14 wl1_14 wl2_14 wl0_15 wl1_15 wl2_15 vdd gnd bitcell_array_16x2_1
-Xprecharge_array0 bl0_0 br0_0 bl0_1 br0_1 clk_buf_bar0 vdd precharge_array_1
-Xprecharge_array2 bl2_0 br2_0 bl2_1 br2_1 clk_buf_bar2 vdd precharge_array_2
-Xsense_amp_array0 dout0_0 bl0_0 br0_0 dout0_1 bl0_1 br0_1 s_en0 vdd gnd sense_amp_array
-Xsense_amp_array2 dout2_0 bl2_0 br2_0 dout2_1 bl2_1 br2_1 s_en2 vdd gnd sense_amp_array
-Xwrite_driver_array0 din0_0 din0_1 bl0_0 br0_0 bl0_1 br0_1 w_en0 vdd gnd write_driver_array
-Xwrite_driver_array1 din1_0 din1_1 bl1_0 br1_0 bl1_1 br1_1 w_en1 vdd gnd write_driver_array
-Xrow_decoder0 addr0_0 addr0_1 addr0_2 addr0_3 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 vdd gnd hierarchical_decoder_16rows
-Xrow_decoder1 addr1_0 addr1_1 addr1_2 addr1_3 dec_out1_0 dec_out1_1 dec_out1_2 dec_out1_3 dec_out1_4 dec_out1_5 dec_out1_6 dec_out1_7 dec_out1_8 dec_out1_9 dec_out1_10 dec_out1_11 dec_out1_12 dec_out1_13 dec_out1_14 dec_out1_15 vdd gnd hierarchical_decoder_16rows
-Xrow_decoder2 addr2_0 addr2_1 addr2_2 addr2_3 dec_out2_0 dec_out2_1 dec_out2_2 dec_out2_3 dec_out2_4 dec_out2_5 dec_out2_6 dec_out2_7 dec_out2_8 dec_out2_9 dec_out2_10 dec_out2_11 dec_out2_12 dec_out2_13 dec_out2_14 dec_out2_15 vdd gnd hierarchical_decoder_16rows
-Xwordline_driver0 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 clk_buf0 vdd gnd wordline_driver
-Xwordline_driver1 dec_out1_0 dec_out1_1 dec_out1_2 dec_out1_3 dec_out1_4 dec_out1_5 dec_out1_6 dec_out1_7 dec_out1_8 dec_out1_9 dec_out1_10 dec_out1_11 dec_out1_12 dec_out1_13 dec_out1_14 dec_out1_15 wl1_0 wl1_1 wl1_2 wl1_3 wl1_4 wl1_5 wl1_6 wl1_7 wl1_8 wl1_9 wl1_10 wl1_11 wl1_12 wl1_13 wl1_14 wl1_15 clk_buf1 vdd gnd wordline_driver
-Xwordline_driver2 dec_out2_0 dec_out2_1 dec_out2_2 dec_out2_3 dec_out2_4 dec_out2_5 dec_out2_6 dec_out2_7 dec_out2_8 dec_out2_9 dec_out2_10 dec_out2_11 dec_out2_12 dec_out2_13 dec_out2_14 dec_out2_15 wl2_0 wl2_1 wl2_2 wl2_3 wl2_4 wl2_5 wl2_6 wl2_7 wl2_8 wl2_9 wl2_10 wl2_11 wl2_12 wl2_13 wl2_14 wl2_15 clk_buf2 vdd gnd wordline_driver
-.ENDS bank
-
-.SUBCKT sram_2_16_scn4m_subm DIN0[0] DIN0[1] DIN1[0] DIN1[1] ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] ADDR1[0] ADDR1[1] ADDR1[2] ADDR1[3] ADDR2[0] ADDR2[1] ADDR2[2] ADDR2[3] csb0 csb1 csb2 web0 clk0 clk1 clk2 DOUT0[0] DOUT0[1] DOUT2[0] DOUT2[1] vdd gnd
-Xbank0 DOUT0[0] DOUT0[1] DOUT2[0] DOUT2[1] BANK_DIN0[0] BANK_DIN0[1] BANK_DIN1[0] BANK_DIN1[1] A0[0] A0[1] A0[2] A0[3] A1[0] A1[1] A1[2] A1[3] A2[0] A2[1] A2[2] A2[3] s_en0 s_en2 w_en0 w_en1 clk_buf_bar0 clk_buf0 clk_buf_bar1 clk_buf1 clk_buf_bar2 clk_buf2 vdd gnd bank
-Xcontrol0 csb0 web0 clk0 s_en0 w_en0 clk_buf_bar0 clk_buf0 vdd gnd control_logic_rw
-Xcontrol1 csb1 clk1 w_en1 clk_buf_bar1 clk_buf1 vdd gnd control_logic_w
-Xcontrol2 csb2 clk2 s_en2 clk_buf_bar2 clk_buf2 vdd gnd control_logic_r
-Xrow_address0 ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] A0[0] A0[1] A0[2] A0[3] clk_buf0 vdd gnd row_addr_dff
-Xrow_address1 ADDR1[0] ADDR1[1] ADDR1[2] ADDR1[3] A1[0] A1[1] A1[2] A1[3] clk_buf1 vdd gnd row_addr_dff
-Xrow_address2 ADDR2[0] ADDR2[1] ADDR2[2] ADDR2[3] A2[0] A2[1] A2[2] A2[3] clk_buf2 vdd gnd row_addr_dff
-Xdata_dff0 DIN0[0] DIN0[1] BANK_DIN0[0] BANK_DIN0[1] clk_buf0 vdd gnd data_dff
-Xdata_dff1 DIN1[0] DIN1[1] BANK_DIN1[0] BANK_DIN1[1] clk_buf1 vdd gnd data_dff
-.ENDS sram_2_16_scn4m_subm
diff --git a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib b/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
deleted file mode 100644
index 4ce58d08..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
+++ /dev/null
@@ -1,625 +0,0 @@
-library (sram_2_16_scn4m_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 2;
-    bit_from : 0;
-    bit_to : 1;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 4;
-    bit_from : 0;
-    bit_to : 3;
-    }
-
-cell (sram_2_16_scn4m_subm){
-    memory(){ 
-    type : ram;
-    address_width : 4;
-    word_width : 2;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 0;
-
-    leakage_power () {
-      when : "CSb0 & CSb1 & CSb2";
-      value : 0.000436;
-    }
-    cell_leakage_power : 0;
-    bus(DIN0){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR0; 
-            clocked_on  : clk0; 
-        }
-        pin(DIN0[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-    bus(DOUT0){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR0; 
-        }
-        pin(DOUT0[1:0]){
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk0"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    bus(ADDR0){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR0[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    pin(CSb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(WEb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(clk0){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb0 & clk0 & !WEb0"; 
-            rise_power(scalar){
-                values("15.41143495605");
-            }
-            fall_power(scalar){
-                values("15.41143495605");
-            }
-        }
-        internal_power(){
-            when : "!CSb0 & !clk0 & WEb0"; 
-            rise_power(scalar){
-                values("15.41143495605");
-            }
-            fall_power(scalar){
-                values("15.41143495605");
-            }
-        }
-        internal_power(){
-            when : "CSb0"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0.0"); 
-            }
-            fall_constraint(scalar) {
-                values("0.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0"); 
-            }
-            fall_constraint(scalar) {
-                values("0"); 
-            }
-         }
-    }
-
-    bus(DIN1){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR1; 
-            clocked_on  : clk1; 
-        }
-        pin(DIN1[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk1"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk1"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-    bus(ADDR1){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR1[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk1"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk1"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    pin(CSb1){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk1"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk1"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(clk1){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb1 & clk1"; 
-            rise_power(scalar){
-                values("15.41143495605");
-            }
-            fall_power(scalar){
-                values("15.41143495605");
-            }
-        }
-        internal_power(){
-            when : "CSb1"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk1; 
-            rise_constraint(scalar) {
-                values("0.0"); 
-            }
-            fall_constraint(scalar) {
-                values("0.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk1; 
-            rise_constraint(scalar) {
-                values("0"); 
-            }
-            fall_constraint(scalar) {
-                values("0"); 
-            }
-         }
-    }
-
-    bus(DOUT2){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR2; 
-        }
-        pin(DOUT2[1:0]){
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk2"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    bus(ADDR2){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR2[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk2"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk2"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    pin(CSb2){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk2"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk2"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(clk2){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb2 & !clk2"; 
-            rise_power(scalar){
-                values("15.41143495605");
-            }
-            fall_power(scalar){
-                values("15.41143495605");
-            }
-        }
-        internal_power(){
-            when : "CSb2"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk2; 
-            rise_constraint(scalar) {
-                values("0.0"); 
-            }
-            fall_constraint(scalar) {
-                values("0.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk2; 
-            rise_constraint(scalar) {
-                values("0"); 
-            }
-            fall_constraint(scalar) {
-                values("0"); 
-            }
-         }
-    }
-
-    }
-}
diff --git a/compiler/datasheet/server_scripts/files/test_files/testfolder/file1 b/compiler/datasheet/server_scripts/files/test_files/testfolder/file1
deleted file mode 100644
index e69de29b..00000000
diff --git a/compiler/datasheet/server_scripts/files/test_files/testfolder/file2 b/compiler/datasheet/server_scripts/files/test_files/testfolder/file2
deleted file mode 100644
index e69de29b..00000000
diff --git a/compiler/datasheet/server_scripts/files/test_files/testfolder2/file3 b/compiler/datasheet/server_scripts/files/test_files/testfolder2/file3
deleted file mode 100644
index e69de29b..00000000
diff --git a/compiler/datasheet/server_scripts/files/test_files/testfolder2/file4 b/compiler/datasheet/server_scripts/files/test_files/testfolder2/file4
deleted file mode 100644
index e69de29b..00000000
diff --git a/compiler/datasheet/server_scripts/index.html b/compiler/datasheet/server_scripts/index.html
new file mode 100644
index 00000000..6b1596ba
--- /dev/null
+++ b/compiler/datasheet/server_scripts/index.html
@@ -0,0 +1,124 @@
+
+</ul>
+    <link rel="stylesheet" href="static/index.css">
+
+    <button class="collapsible">files</button>
+    <div class="content">
+        
+        
+        
+        
+            
+
+        <button class="collapsible">./files/test_files</button>
+        <div class="content">
+            
+            <button class="collapsible">sram_2_16_scn4m_subm.py</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm.py">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm_TT_5V_25C.lib</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm_TT_3p3V_25C.lib</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm.sp</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm.sp">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm.v</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm.v">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm_TT_5p0V_25C.lib</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm.gds</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm.gds">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm.html</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm.html">link</a> 
+             </div>
+            
+            <button class="collapsible">sram_2_16_scn4m_subm.lef</button>
+            <div class="content">
+                <a href="./files/test_files/sram_2_16_scn4m_subm.lef">link</a> 
+             </div>
+            
+        </div>
+
+        
+        
+        
+            
+
+        <button class="collapsible">./files/test_files/testfolder</button>
+        <div class="content">
+            
+            <button class="collapsible">file2</button>
+            <div class="content">
+                <a href="./files/test_files/testfolder/file2">link</a> 
+             </div>
+            
+            <button class="collapsible">file1</button>
+            <div class="content">
+                <a href="./files/test_files/testfolder/file1">link</a> 
+             </div>
+            
+        </div>
+
+        
+        
+        
+            
+
+        <button class="collapsible">./files/test_files/testfolder2</button>
+        <div class="content">
+            
+            <button class="collapsible">file4</button>
+            <div class="content">
+                <a href="./files/test_files/testfolder2/file4">link</a> 
+             </div>
+            
+            <button class="collapsible">file3</button>
+            <div class="content">
+                <a href="./files/test_files/testfolder2/file3">link</a> 
+             </div>
+            
+        </div>
+
+        
+        
+    </div>
+
+
+    <script type="text/javascript">
+        var coll = document.getElementsByClassName("collapsible");
+        var i;
+
+        for (i = 0; i < coll.length; i++) {
+            coll[i].addEventListener("click", function() {
+        this.classList.toggle("active");
+        var content = this.nextElementSibling;
+        if (content.style.display === "block") {
+            content.style.display = "none";
+        } else {
+          content.style.display = "block";
+        }
+          });
+        }
+        </script>
+</ul>
\ No newline at end of file

From 1283cbc3be5419ed11ee45a9c6af92932213d2a9 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Mon, 7 Jan 2019 18:17:38 -0800
Subject: [PATCH 10/28] fixed EOL error in descriptor

---
 compiler/datasheet/datasheet.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 8eb18a0d..cb8ed55c 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -38,7 +38,7 @@ class datasheet():
 #                self.html += row
             for item in self.description:
                self.html += item + ','
-               self.teml += 'EOL'
+            self.html += 'EOL'
             self.html +='-->'
     
         vlsi_logo = 0

From 19a986c35c29a3fe1c19a611bc02cbeb36d6f80a Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Mon, 7 Jan 2019 19:43:57 -0800
Subject: [PATCH 11/28] no-flask rewrite for initial datasheet case complete

---
 compiler/datasheet/datasheet.py     |   3 +
 compiler/datasheet/datasheet_gen.py | 173 ++++++++++++++++++++++++++--
 2 files changed, 169 insertions(+), 7 deletions(-)

diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index cb8ed55c..726e9920 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -65,6 +65,9 @@ class datasheet():
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p>'
         self.html += in_out(self.io,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
 
+#        for row in self.io_table.rows:
+#            print(row)
+        
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p>'
         self.html += operating_conditions(self.operating,table_id='data').__html__()
 
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index 3fc38510..b97981fa 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -19,6 +19,7 @@ if OPTS.datasheet_gen:
     import os, math
     import optparse
     import csv
+    from table_gen import *
     from deliverables import *
     from operating_conditions import *
     from timing_and_current_data import *
@@ -355,6 +356,11 @@ def parse_characterizer_csv(sram,f,pages):
                     new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
                     new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
 
+                    #
+                    new_sheet.corners.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
+                    new_sheet.dlv.add_row(['.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))])
+                    #
+
             if found == 0:
                 
                 #if this is the first corner for this sram, run first time configuration and set up tables
@@ -367,18 +373,62 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet.LVS = LVS
                 new_sheet.description = [NAME, NUM_WORDS, NUM_BANKS, NUM_RW_PORTS, NUM_W_PORTS, NUM_R_PORTS, TECH_NAME, WORD_SIZE, ORIGIN_ID, DATETIME]
 
+            
 
                 new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
 
+                #
+                new_sheet.corners_table = table_gen("corners")               
+                new_sheet.corners_table.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
+                #
+
                 new_sheet.operating.append(operating_conditions_item('Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'))
                 new_sheet.operating.append(operating_conditions_item('Operating Temperature',TEMP,TEMP,TEMP,'Celsius'))
+
+                #
+                new_sheet.operating_table = table_gen("operating_table")
+                new_sheet.operating_table.add_row(['Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'])
+                new_sheet.operating_table.add_row(['Operating Temperature',TEMP,TEMP,TEMP,'Celsius'])
+                #
+
                 try:
                     new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'))
+                    #
+                    new_sheet.operating_table.add_row(['Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'])
+                    #
                 except Exception:
                     new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',"not available in netlist only",'MHz')) #failed to provide non-zero MIN_PERIOD
-                
-                
+                    #
+                    new_sheet.operating_table.add_row(['Operating Frequency (F)','','',"not available in netlist only",'MHz']) #failed to provide non-zero MIN_PERIOD
+                    #
+
+                #
+                new_sheet.timing_table = table_gen("timing")
+                #
                 while(True):
+                    #
+                    if(row[col].startswith('DIN')):
+                        start = col
+                        
+                        new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+                        col += 2
+
+                        
+                        new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+                    
+                        new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        col +=1
+
+                    #
                     if(row[col].startswith('DIN')):
                         start = col
                         new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
@@ -394,6 +444,8 @@ def parse_characterizer_csv(sram,f,pages):
                         col += 2
 
                         col +=1
+
+                    #
                         
                     elif(row[col].startswith('DOUT')):
                         start = col
@@ -410,7 +462,29 @@ def parse_characterizer_csv(sram,f,pages):
                         col += 2
 
                         col +=1
+                    #
+                    elif(row[col].startswith('DOUT')):
+                        start = col
+                        
+                        new_sheet.timing_table.add_row(['{0} cell rise'.format(row[start]),row[col+1],row[col+2],'ns'])
+                        col += 2
 
+                        
+                        new_sheet.timing_table.add_row(['{0} cell fall'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+                    
+                        new_sheet.timing_table.add_row(['{0} rise transition'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        new_sheet.timing_table.add_row(['{0} fall transition'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        col +=1
+
+                    #
                     elif(row[col].startswith('CSb')):
                         start = col
                         new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
@@ -426,7 +500,29 @@ def parse_characterizer_csv(sram,f,pages):
                         col += 2
 
                         col +=1
+                    #
+                    elif(row[col].startswith('CSb')):
+                        start = col
+                        
+                        new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+                        col += 2
 
+                        
+                        new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+                    
+                        new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        col +=1
+
+                    #
                     elif(row[col].startswith('WEb')):
                         start = col
                         new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
@@ -442,7 +538,29 @@ def parse_characterizer_csv(sram,f,pages):
                         col += 2
 
                         col +=1
+                    #
+                    elif(row[col].startswith('WEb')):
+                        start = col
+                        
+                        new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+                        col += 2
 
+                        
+                        new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+                    
+                        new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        col +=1
+
+                    #
                     elif(row[col].startswith('ADDR')):
                         start = col
                         new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
@@ -458,25 +576,58 @@ def parse_characterizer_csv(sram,f,pages):
                         col += 2
 
                         col +=1
+                    #
+                    elif(row[col].startswith('ADDR')):
+                        start = col
+                        
+                        new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+                        col += 2
+
+                        
+                        new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+                    
+                        new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
+
+                        col += 2
+
+                        col +=1
+
+                    #
                     else:
                         break
 
 
                     
-               
+                #
+                new_sheet.dlv_table = table_gen("dlv")
+                new_sheet.io_table = table_gen("io")
+                #
+
                 if not OPTS.netlist_only:
                     #physical layout files should not be generated in netlist only mode
                     new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'gds')))
                     new_sheet.dlv.append(deliverables_item('.lef','LEF files','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'lef')))
-   
-
+  
+               
                 new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'sp')))
                 new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'v')))
                 new_sheet.dlv.append(deliverables_item('.html','This datasheet','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'html')))
                 new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="{1}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
                 new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'py')))
 
-
+                #
+                new_sheet.dlv_table.add_row(['.sp','SPICE netlists','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'sp')])
+                new_sheet.dlv_table.add_row(['.v','Verilog simulation models','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'v')])
+                new_sheet.dlv_table.add_row(['.html','This datasheet','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'html')])
+                new_sheet.dlv_table.add_row(['.lib','Synthesis models','<a href="{1}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))])
+                new_sheet.dlv_table.add_row(['.py','OpenRAM configuration file','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'py')])
+                #
 
                 #debug table for multiport information
                 new_sheet.io.append(in_out_item('WORD_SIZE',WORD_SIZE))
@@ -487,7 +638,15 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet.io.append(in_out_item('NUM_W_PORTS',NUM_W_PORTS))
                 new_sheet.io.append(in_out_item('Area',sram.width * sram.height))
 
-
+                #
+                new_sheet.io_table.add_row(['WORD_SIZE',WORD_SIZE])
+                new_sheet.io_table.add_row(['NUM_WORDS',NUM_WORDS])
+                new_sheet.io_table.add_row(['NUM_BANKS',NUM_BANKS])
+                new_sheet.io_table.add_row(['NUM_RW_PORTS',NUM_RW_PORTS])
+                new_sheet.io_table.add_row(['NUM_R_PORTS',NUM_R_PORTS])
+                new_sheet.io_table.add_row(['NUM_W_PORTS',NUM_W_PORTS])
+                new_sheet.io_table.add_row(['Area',sram.width * sram.height])
+                #
 
 
 

From 6033cc604d21cf047d22173d51cb9855efc83b89 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Tue, 8 Jan 2019 18:54:20 -0800
Subject: [PATCH 12/28] stable, but incomplete flaskless table gen rewrite

---
 compiler/datasheet/datasheet.py     |  5 +++--
 compiler/datasheet/datasheet_gen.py | 25 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 726e9920..5e724512 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -1,3 +1,4 @@
+from table_gen import *
 from flask_table import *
 from operating_conditions import *
 from characterization_corners import *
@@ -63,8 +64,8 @@ class datasheet():
         self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'Git commit id: ' + str(self.git_id) + '</p>'
 
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p>'
-        self.html += in_out(self.io,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
-
+        #self.html += in_out(self.io,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
+        self.html += self.io_table.to_html()
 #        for row in self.io_table.rows:
 #            print(row)
         
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index b97981fa..59d58551 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -145,8 +145,33 @@ def parse_characterizer_csv(sram,f,pages):
                                     item.max = str(math.floor(1000/float(MIN_PERIOD)))
                             except Exception:
                                 pass
+                    #
+                    for item in sheet.operating_table.rows:
+                        #check if the new corner data is worse than the previous worse corner data
 
+                        if item[0] == 'Operating Temperature':
+                            if float(TEMP) > float(ite[3]):
+                                item[2] = item[3]
+                                item[3] = TEMP
+                            if float(TEMP) < float(item[1]):
+                                item[2] = item[1]
+                                item[1] = TEMP
 
+                        if item[0] == 'Power supply (VDD) range':
+                            if float(VOLT) > float(item[3]):
+                                item[2] = item[3]
+                                item[3] = VOLT
+                            if float(VOLT) < float(item[1]):
+                                item[2] = item[1]
+                                item[1] = VOLT
+
+                        if item.parameter == 'Operating Frequncy (F)':
+                            try:
+                                if float(math.floor(1000/float(MIN_PERIOD)) < float(item[3])):
+                                    item[3] = str(math.floor(1000/float(MIN_PERIOD)))
+                            except Exception:
+                                pass
+                    #
 
                     while(True):
                         if(row[col].startswith('DIN')):

From e58515b89b695f3cbdaf708891318d422ced15e9 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Tue, 8 Jan 2019 19:50:47 -0800
Subject: [PATCH 13/28] tables stable and flask removed, headers are bugged

---
 .../datasheet/characterization_corners.py     |  23 -
 compiler/datasheet/datasheet.py               |  27 +-
 compiler/datasheet/datasheet_gen.py           | 451 ++++++------------
 compiler/datasheet/deliverables.py            |  19 -
 compiler/datasheet/in_out.py                  |  17 -
 compiler/datasheet/operating_conditions.py    |  23 -
 compiler/datasheet/timing_and_current_data.py |  22 -
 compiler/globals.py                           |   8 +-
 compiler/openram.py                           |   4 +-
 9 files changed, 150 insertions(+), 444 deletions(-)
 delete mode 100644 compiler/datasheet/characterization_corners.py
 delete mode 100644 compiler/datasheet/deliverables.py
 delete mode 100644 compiler/datasheet/in_out.py
 delete mode 100644 compiler/datasheet/operating_conditions.py
 delete mode 100644 compiler/datasheet/timing_and_current_data.py

diff --git a/compiler/datasheet/characterization_corners.py b/compiler/datasheet/characterization_corners.py
deleted file mode 100644
index 494b491f..00000000
--- a/compiler/datasheet/characterization_corners.py
+++ /dev/null
@@ -1,23 +0,0 @@
-from flask_table import *
-
-class characterization_corners(Table):
-    """
-    Set up characterization corners table columns and title information
-    """
-    corner_name = Col('Corner Name')
-    process = Col('Process')
-    power_supply = Col('Power Supply')
-    temperature = Col('Temperature')
-    library_name_suffix = Col('Library Name Suffix')
-
-class characterization_corners_item(object):
-    """
-    Defines the contents of a charcaterization corner table row
-    """
-    def __init__(self, corner_name, process, power_supply, temperature, library_name_suffix):
-        self.corner_name = corner_name
-        self.process = process
-        self.power_supply = power_supply
-        self.temperature = temperature
-        self.library_name_suffix = library_name_suffix
-
diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 5e724512..56214d64 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -1,10 +1,4 @@
 from table_gen import *
-from flask_table import *
-from operating_conditions import *
-from characterization_corners import *
-from deliverables import *
-from timing_and_current_data import *
-from in_out import *
 import os
 import csv
 import base64
@@ -15,11 +9,6 @@ class datasheet():
     Defines the layout,but not the data,  of the html datasheet
     """
     def __init__(self,identifier):
-        self.io = []
-        self.corners = []
-        self.timing = []
-        self.operating = []
-        self.dlv = []
         self.name = identifier
         self.html = ""
         
@@ -64,22 +53,24 @@ class datasheet():
         self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'Git commit id: ' + str(self.git_id) + '</p>'
 
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p>'
-        #self.html += in_out(self.io,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
+#        self.html += in_out(self.io,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
         self.html += self.io_table.to_html()
-#        for row in self.io_table.rows:
-#            print(row)
         
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p>'
-        self.html += operating_conditions(self.operating,table_id='data').__html__()
+#        self.html += operating_conditions(self.operating,table_id='data').__html__()
+        self.html += self.operating_table.to_html()
 
         self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing and Current Data</p>'
-        self.html += timing_and_current_data(self.timing,table_id='data').__html__()
+#        self.html += timing_and_current_data(self.timing,table_id='data').__html__()
+        self.html += self.timing_table.to_html()
 
         self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p>'
-        self.html += characterization_corners(self.corners,table_id='data').__html__()
+#        self.html += characterization_corners(self.corners,table_id='data').__html__()
+        self.html += self.corners_table.to_html()
 
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p>'
-        self.html += deliverables(self.dlv,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
+#        self.html += deliverables(self.dlv,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
+        self.html += self.dlv_table.to_html()
 
         
        
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index 59d58551..4a307db9 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -1,35 +1,21 @@
 #!/usr/bin/env python3
 """
 This is a script to load data from the characterization and layout processes into 
-a web friendly html datasheet. This script requres the python-flask and flask-table
-packages to be installed.
+a web friendly html datasheet.
 """
 #TODO:
-#locate all port elements in .lib
-#Locate all timing elements in .lib
+#include log file
 #Diagram generation
 #Improve css
 
 
 import debug
 from globals import OPTS
-
-if OPTS.datasheet_gen:
-    import flask_table
-    import os, math
-    import optparse
-    import csv
-    from table_gen import *
-    from deliverables import *
-    from operating_conditions import *
-    from timing_and_current_data import *
-    from characterization_corners import *
-    from datasheet import *
-    from in_out import *
-else:
-    debug.warning("Python library flask_table not found. Skipping html datasheet generation. This can be installed with pip install flask-table.")
-    #make sure appropriate python libraries are installed
-
+import os, math
+import optparse
+import csv
+from datasheet import *
+from table_gen import *
 
 def process_name(corner):
     """
@@ -120,37 +106,11 @@ def parse_characterizer_csv(sram,f,pages):
                     found = 1
                     #if the .lib information is for an existing datasheet compare timing data
 
-                    for item in sheet.operating:
-                        #check if the new corner data is worse than the previous worse corner data
-
-                        if item.parameter == 'Operating Temperature':
-                            if float(TEMP) > float(item.max):
-                                item.typ = item.max
-                                item.max = TEMP
-                            if float(TEMP) < float(item.min):
-                                item.typ = item.min
-                                item.min = TEMP
-
-                        if item.parameter == 'Power supply (VDD) range':
-                            if float(VOLT) > float(item.max):
-                                item.typ = item.max
-                                item.max = VOLT
-                            if float(VOLT) < float(item.min):
-                                item.typ = item.min
-                                item.min = VOLT
-
-                        if item.parameter == 'Operating Frequncy (F)':
-                            try:
-                                if float(math.floor(1000/float(MIN_PERIOD)) < float(item.max)):
-                                    item.max = str(math.floor(1000/float(MIN_PERIOD)))
-                            except Exception:
-                                pass
-                    #
                     for item in sheet.operating_table.rows:
                         #check if the new corner data is worse than the previous worse corner data
 
                         if item[0] == 'Operating Temperature':
-                            if float(TEMP) > float(ite[3]):
+                            if float(TEMP) > float(item[3]):
                                 item[2] = item[3]
                                 item[3] = TEMP
                             if float(TEMP) < float(item[1]):
@@ -165,49 +125,51 @@ def parse_characterizer_csv(sram,f,pages):
                                 item[2] = item[1]
                                 item[1] = VOLT
 
-                        if item.parameter == 'Operating Frequncy (F)':
+                        if item[0] == 'Operating Frequncy (F)':
                             try:
                                 if float(math.floor(1000/float(MIN_PERIOD)) < float(item[3])):
                                     item[3] = str(math.floor(1000/float(MIN_PERIOD)))
                             except Exception:
                                 pass
-                    #
+
 
                     while(True):
+
+                       
                         if(row[col].startswith('DIN')):
                             start = col
-                            for item in sheet.timing:
-                                if item.parameter.startswith(row[col]):
+                            for item in sheet.timing_table.rows:
+                                if item[0].startswith(row[col]):
 
-                                    if item.parameter.endswith('setup rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    if item[0].endswith('setup rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('setup falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('setup falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
@@ -215,38 +177,38 @@ def parse_characterizer_csv(sram,f,pages):
 
                         elif(row[col].startswith('DOUT')):
                             start = col
-                            for item in sheet.timing:
-                                if item.parameter.startswith(row[col]):
+                            for item in sheet.timing_table.rows:
+                                if item[0].startswith(row[col]):
 
-                                    if item.parameter.endswith('cell rise'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    if item[0].endswith('cell rise'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('cell fall'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('cell fall'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('rise transition'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('rise transition'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('fall transition'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('fall transition'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
@@ -254,38 +216,38 @@ def parse_characterizer_csv(sram,f,pages):
 
                         elif(row[col].startswith('CSb')):
                             start = col
-                            for item in sheet.timing:
-                                if item.parameter.startswith(row[col]):
+                            for item in sheet.timing_table.rows:
+                                if item[0].startswith(row[col]):
 
-                                    if item.parameter.endswith('setup rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    if item[0].endswith('setup rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('setup falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('setup falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
@@ -294,38 +256,38 @@ def parse_characterizer_csv(sram,f,pages):
 
                         elif(row[col].startswith('WEb')):
                             start = col
-                            for item in sheet.timing:
-                                if item.parameter.startswith(row[col]):
+                            for item in sheet.timing_table.rows:
+                                if item[0].startswith(row[col]):
 
-                                    if item.parameter.endswith('setup rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    if item[0].endswith('setup rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('setup falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('setup falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
@@ -334,38 +296,38 @@ def parse_characterizer_csv(sram,f,pages):
 
                         elif(row[col].startswith('ADDR')):
                             start = col
-                            for item in sheet.timing:
-                                if item.parameter.startswith(row[col]):
+                            for item in sheet.timing_table.rows:
+                                if item[0].startswith(row[col]):
 
-                                    if item.parameter.endswith('setup rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    if item[0].endswith('setup rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('setup falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('setup falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold rising'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold rising'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
-                                    elif item.parameter.endswith('hold falling'):
-                                        if float(row[col+1]) < float(item.min):
-                                            item.min = row[col+1]
-                                        if float(row[col+2]) > float(item.max):
-                                            item.max = row[col+2]
+                                    elif item[0].endswith('hold falling'):
+                                        if float(row[col+1]) < float(item[1]):
+                                            item[1] = row[col+1]
+                                        if float(row[col+2]) > float(item[2]):
+                                            item[2] = row[col+2]
 
                                         col += 2
 
@@ -377,14 +339,8 @@ def parse_characterizer_csv(sram,f,pages):
                             break
 
 
-                    #regardless of if there is already a corner for the current sram, append the new corner to the datasheet
-                    new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
-                    new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
-
-                    #
-                    new_sheet.corners.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
-                    new_sheet.dlv.add_row(['.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))])
-                    #
+                    new_sheet.corners_table.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
+                    new_sheet.dlv_table.add_row(['.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))])
 
             if found == 0:
                 
@@ -398,40 +354,18 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet.LVS = LVS
                 new_sheet.description = [NAME, NUM_WORDS, NUM_BANKS, NUM_RW_PORTS, NUM_W_PORTS, NUM_R_PORTS, TECH_NAME, WORD_SIZE, ORIGIN_ID, DATETIME]
 
-            
-
-                new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
-
-                #
                 new_sheet.corners_table = table_gen("corners")               
                 new_sheet.corners_table.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
-                #
-
-                new_sheet.operating.append(operating_conditions_item('Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'))
-                new_sheet.operating.append(operating_conditions_item('Operating Temperature',TEMP,TEMP,TEMP,'Celsius'))
-
-                #
                 new_sheet.operating_table = table_gen("operating_table")
                 new_sheet.operating_table.add_row(['Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'])
                 new_sheet.operating_table.add_row(['Operating Temperature',TEMP,TEMP,TEMP,'Celsius'])
-                #
 
                 try:
-                    new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'))
-                    #
                     new_sheet.operating_table.add_row(['Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'])
-                    #
                 except Exception:
-                    new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',"not available in netlist only",'MHz')) #failed to provide non-zero MIN_PERIOD
-                    #
                     new_sheet.operating_table.add_row(['Operating Frequency (F)','','',"not available in netlist only",'MHz']) #failed to provide non-zero MIN_PERIOD
-                    #
-
-                #
                 new_sheet.timing_table = table_gen("timing")
-                #
                 while(True):
-                    #
                     if(row[col].startswith('DIN')):
                         start = col
                         
@@ -453,41 +387,6 @@ def parse_characterizer_csv(sram,f,pages):
 
                         col +=1
 
-                    #
-                    if(row[col].startswith('DIN')):
-                        start = col
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-                    
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        col +=1
-
-                    #
-                        
-                    elif(row[col].startswith('DOUT')):
-                        start = col
-                        new_sheet.timing.append(timing_and_current_data_item('{0} cell rise'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} cell fall'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-                    
-                        new_sheet.timing.append(timing_and_current_data_item('{0} rise transition'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} fall transition'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        col +=1
-                    #
                     elif(row[col].startswith('DOUT')):
                         start = col
                         
@@ -509,23 +408,6 @@ def parse_characterizer_csv(sram,f,pages):
 
                         col +=1
 
-                    #
-                    elif(row[col].startswith('CSb')):
-                        start = col
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-                    
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        col +=1
-                    #
                     elif(row[col].startswith('CSb')):
                         start = col
                         
@@ -547,23 +429,6 @@ def parse_characterizer_csv(sram,f,pages):
 
                         col +=1
 
-                    #
-                    elif(row[col].startswith('WEb')):
-                        start = col
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-                    
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        col +=1
-                    #
                     elif(row[col].startswith('WEb')):
                         start = col
                         
@@ -585,23 +450,6 @@ def parse_characterizer_csv(sram,f,pages):
 
                         col +=1
 
-                    #
-                    elif(row[col].startswith('ADDR')):
-                        start = col
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-                    
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
-                        col += 2
-
-                        col +=1
-                    #
                     elif(row[col].startswith('ADDR')):
                         start = col
                         
@@ -623,47 +471,26 @@ def parse_characterizer_csv(sram,f,pages):
 
                         col +=1
 
-                    #
                     else:
                         break
 
 
                     
-                #
                 new_sheet.dlv_table = table_gen("dlv")
                 new_sheet.io_table = table_gen("io")
-                #
 
                 if not OPTS.netlist_only:
                     #physical layout files should not be generated in netlist only mode
-                    new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'gds')))
-                    new_sheet.dlv.append(deliverables_item('.lef','LEF files','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'lef')))
-  
+                    new_sheet.dlv_table.add_row(['.gds','GDSII layout views','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'gds')])
+                    new_sheet.dlv_table.add_row(['.lef','LEF files','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'lef')])
+ 
                
-                new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'sp')))
-                new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'v')))
-                new_sheet.dlv.append(deliverables_item('.html','This datasheet','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'html')))
-                new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="{1}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
-                new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'py')))
-
-                #
                 new_sheet.dlv_table.add_row(['.sp','SPICE netlists','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'sp')])
                 new_sheet.dlv_table.add_row(['.v','Verilog simulation models','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'v')])
                 new_sheet.dlv_table.add_row(['.html','This datasheet','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'html')])
                 new_sheet.dlv_table.add_row(['.lib','Synthesis models','<a href="{1}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))])
                 new_sheet.dlv_table.add_row(['.py','OpenRAM configuration file','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'py')])
-                #
 
-                #debug table for multiport information
-                new_sheet.io.append(in_out_item('WORD_SIZE',WORD_SIZE))
-                new_sheet.io.append(in_out_item('NUM_WORDS',NUM_WORDS))
-                new_sheet.io.append(in_out_item('NUM_BANKS',NUM_BANKS))
-                new_sheet.io.append(in_out_item('NUM_RW_PORTS',NUM_RW_PORTS))
-                new_sheet.io.append(in_out_item('NUM_R_PORTS',NUM_R_PORTS))
-                new_sheet.io.append(in_out_item('NUM_W_PORTS',NUM_W_PORTS))
-                new_sheet.io.append(in_out_item('Area',sram.width * sram.height))
-
-                #
                 new_sheet.io_table.add_row(['WORD_SIZE',WORD_SIZE])
                 new_sheet.io_table.add_row(['NUM_WORDS',NUM_WORDS])
                 new_sheet.io_table.add_row(['NUM_BANKS',NUM_BANKS])
@@ -671,7 +498,7 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet.io_table.add_row(['NUM_R_PORTS',NUM_R_PORTS])
                 new_sheet.io_table.add_row(['NUM_W_PORTS',NUM_W_PORTS])
                 new_sheet.io_table.add_row(['Area',sram.width * sram.height])
-                #
+                
 
 
 
@@ -680,18 +507,18 @@ def parse_characterizer_csv(sram,f,pages):
 class datasheet_gen():
      def datasheet_write(sram,name):
         
-        if OPTS.datasheet_gen:
-            in_dir = OPTS.openram_temp
-        
-            if not (os.path.isdir(in_dir)):
-                os.mkdir(in_dir)
+
+        in_dir = OPTS.openram_temp
+
+        if not (os.path.isdir(in_dir)):
+            os.mkdir(in_dir)
 
 
-            datasheets = []
-            parse_characterizer_csv(sram, in_dir + "/datasheet.info", datasheets)
+        datasheets = []
+        parse_characterizer_csv(sram, in_dir + "/datasheet.info", datasheets)
 
 
-            for sheets in datasheets:
-                with open(name, 'w+') as f:
-                    sheets.generate_html()
-                    f.write(sheets.html)
+        for sheets in datasheets:
+            with open(name, 'w+') as f:
+                sheets.generate_html()
+                f.write(sheets.html)
diff --git a/compiler/datasheet/deliverables.py b/compiler/datasheet/deliverables.py
deleted file mode 100644
index 9ba3c0e6..00000000
--- a/compiler/datasheet/deliverables.py
+++ /dev/null
@@ -1,19 +0,0 @@
-from flask_table import *
-
-class deliverables(Table):
-    """
-    Set up delivarables table columns and title information
-    """
-    typ = Col('Type')
-    description = Col('Description')
-    link = Col('Link')
-
-
-class deliverables_item(object):
-    """
-    Define deliverables table row elemenent information
-    """
-    def __init__(self, typ, description,link):
-        self.typ = typ
-        self.description = description
-        self.link = link
diff --git a/compiler/datasheet/in_out.py b/compiler/datasheet/in_out.py
deleted file mode 100644
index 98ba9fe5..00000000
--- a/compiler/datasheet/in_out.py
+++ /dev/null
@@ -1,17 +0,0 @@
-from flask_table import *
-
-class in_out(Table):
-    """
-    Set up I/O table columns and title information for multiport debugging
-    """
-    typ = Col('Type')
-    description = Col('Description')
-
-
-class in_out_item(object):
-    """
-    Define table row element for I/O table
-    """
-    def __init__(self, typ, description):
-        self.typ = typ
-        self.description = description
diff --git a/compiler/datasheet/operating_conditions.py b/compiler/datasheet/operating_conditions.py
deleted file mode 100644
index 69648174..00000000
--- a/compiler/datasheet/operating_conditions.py
+++ /dev/null
@@ -1,23 +0,0 @@
-from flask_table import *
-
-class operating_conditions(Table):
-    """
-    Set up operating conditions columns and title information
-    """
-    parameter = Col('Parameter')
-    min = Col('Min')
-    typ = Col('Typ')
-    max = Col('Max')
-    units = Col('Units')
-
-class operating_conditions_item(object):
-    """
-    Define operating conditions table row element
-    """
-    def __init__(self, parameter, min, typ, max, units):
-        self.parameter = parameter
-        self.min = min
-        self.typ = typ
-        self.max = max
-        self.units = units
-
diff --git a/compiler/datasheet/timing_and_current_data.py b/compiler/datasheet/timing_and_current_data.py
deleted file mode 100644
index ff95df49..00000000
--- a/compiler/datasheet/timing_and_current_data.py
+++ /dev/null
@@ -1,22 +0,0 @@
-from flask_table import *
-
-class timing_and_current_data(Table):
-    """
-    Set up timing and current table columns and title information
-    """
-    parameter = Col('Parameter')
-    min = Col('Min')
-    max = Col('Max')
-    units = Col('Units')
-
-class timing_and_current_data_item(object):
-    """
-    Define timing and current data row element
-    """
-    def __init__(self, parameter, min, max, units):
-        self.parameter = parameter
-        self.min = min
-        self.max = max
-        self.units = units
-
-
diff --git a/compiler/globals.py b/compiler/globals.py
index 90a209f5..5843e41c 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -107,13 +107,7 @@ def check_versions():
     # FIXME: Check versions of other tools here??
     # or, this could be done in each module (e.g. verify, characterizer, etc.)
     global OPTS
-
-    try:
-        import flask_table
-        OPTS.datasheet_gen = 1
-    except:
-        OPTS.datasheet_gen = 0
-
+ 
     try:
         import coverage
         OPTS.coverage = 1
diff --git a/compiler/openram.py b/compiler/openram.py
index fa52f3a2..9c98037c 100755
--- a/compiler/openram.py
+++ b/compiler/openram.py
@@ -47,9 +47,7 @@ c = sram_config(word_size=OPTS.word_size,
 print("Words per row: {}".format(c.words_per_row))
 
 #from parser import *
-output_extensions = ["sp","v","lib","py"]
-if OPTS.datasheet_gen:
-    output_extensions.append("html")
+output_extensions = ["sp","v","lib","py","html"]
 if not OPTS.netlist_only:
     output_extensions.extend(["gds","lef"])
 output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in output_extensions]

From 3f8628fa948087084274a980bf2ea1a33e8ab981 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Tue, 8 Jan 2019 20:04:30 -0800
Subject: [PATCH 14/28] flask totally purged, fixed table headers

---
 compiler/datasheet/datasheet.py     | 4 ++--
 compiler/datasheet/datasheet_gen.py | 8 +++++++-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 56214d64..3d871054 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -48,8 +48,8 @@ class datasheet():
 
         self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ self.name + '.html' + '</p>'
         self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Compiled at: '+ self.time + '</p>'
-        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'DRC: ' + str(self.DRC) + '</p>'
-        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS: ' + str(self.LVS) + '</p>'
+        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'DRC errors: ' + str(self.DRC) + '</p>'
+        self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS errors: ' + str(self.LVS) + '</p>'
         self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'Git commit id: ' + str(self.git_id) + '</p>'
 
         self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p>'
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index 4a307db9..db03216b 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -354,9 +354,11 @@ def parse_characterizer_csv(sram,f,pages):
                 new_sheet.LVS = LVS
                 new_sheet.description = [NAME, NUM_WORDS, NUM_BANKS, NUM_RW_PORTS, NUM_W_PORTS, NUM_R_PORTS, TECH_NAME, WORD_SIZE, ORIGIN_ID, DATETIME]
 
-                new_sheet.corners_table = table_gen("corners")               
+                new_sheet.corners_table = table_gen("corners")
+                new_sheet.corners_table.add_row(['Corner Name','Process','Power Supply','Temperature','Library Name Suffix'])
                 new_sheet.corners_table.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
                 new_sheet.operating_table = table_gen("operating_table")
+                new_sheet.operating_table.add_row(['Parameter','Min','Typ','Max','Units'])
                 new_sheet.operating_table.add_row(['Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'])
                 new_sheet.operating_table.add_row(['Operating Temperature',TEMP,TEMP,TEMP,'Celsius'])
 
@@ -365,6 +367,7 @@ def parse_characterizer_csv(sram,f,pages):
                 except Exception:
                     new_sheet.operating_table.add_row(['Operating Frequency (F)','','',"not available in netlist only",'MHz']) #failed to provide non-zero MIN_PERIOD
                 new_sheet.timing_table = table_gen("timing")
+                new_sheet.timing_table.add_row(['Parameter','Min','Max','Units'])
                 while(True):
                     if(row[col].startswith('DIN')):
                         start = col
@@ -477,7 +480,10 @@ def parse_characterizer_csv(sram,f,pages):
 
                     
                 new_sheet.dlv_table = table_gen("dlv")
+                new_sheet.dlv_table.add_row(['Type','Description','Link'])
+
                 new_sheet.io_table = table_gen("io")
+                new_sheet.io_table.add_row(['Type', 'Value'])
 
                 if not OPTS.netlist_only:
                     #physical layout files should not be generated in netlist only mode

From 1c9b59e71c17395996fbd343b21d9c3a12806e07 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Tue, 8 Jan 2019 20:05:29 -0800
Subject: [PATCH 15/28] removed flask requirement from README.md

---
 README.md | 1 -
 1 file changed, 1 deletion(-)

diff --git a/README.md b/README.md
index dbc18f64..5c4ae3c5 100644
--- a/README.md
+++ b/README.md
@@ -31,7 +31,6 @@ The OpenRAM compiler has very few dependencies:
 + [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
 + Python 3.5 or higher
 + Python numpy (pip3 install numpy to install)
-+ flask_table (pip3 install flask to install)
 
 If you want to perform DRC and LVS, you will need either:
 + Calibre (for [FreePDK45])

From 8b8985dbd1251e5b4a8125d83b40b7fa1514d767 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Wed, 9 Jan 2019 06:15:22 -0800
Subject: [PATCH 16/28] track table_gen

---
 compiler/datasheet/datasheet.py               |     2 +-
 compiler/datasheet/server_scripts/__init__.py |    24 -
 .../datasheet/server_scripts/file_data.py     |     4 -
 .../datasheet/server_scripts/filelist.info    |    13 -
 compiler/datasheet/server_scripts/filelist.py |    16 -
 .../contents2/sram_2_16_scn4m_subm.gds        |   Bin 602124 -> 0 bytes
 .../contents2/sram_2_16_scn4m_subm.html       |    86 -
 .../contents2/sram_2_16_scn4m_subm.lef        | 12857 ----------------
 .../contents2/sram_2_16_scn4m_subm.py         |    18 -
 .../contents2/sram_2_16_scn4m_subm.sp         |   559 -
 .../contents2/sram_2_16_scn4m_subm.v          |    47 -
 .../sram_2_16_scn4m_subm_TT_3p3V_25C.lib      |   321 -
 .../sram_2_16_scn4m_subm_TT_5V_25C.lib        |   321 -
 .../sram_2_16_scn4m_subm_TT_5p0V_25C.lib      |   321 -
 compiler/datasheet/server_scripts/index.html  |   124 -
 .../datasheet/server_scripts/static/index.css |    25 -
 .../server_scripts/templates/index.html       |    42 -
 compiler/datasheet/table_gen.py               |    43 +
 18 files changed, 44 insertions(+), 14779 deletions(-)
 delete mode 100644 compiler/datasheet/server_scripts/__init__.py
 delete mode 100644 compiler/datasheet/server_scripts/file_data.py
 delete mode 100644 compiler/datasheet/server_scripts/filelist.info
 delete mode 100644 compiler/datasheet/server_scripts/filelist.py
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.gds
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.html
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.py
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.v
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5V_25C.lib
 delete mode 100644 compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
 delete mode 100644 compiler/datasheet/server_scripts/index.html
 delete mode 100644 compiler/datasheet/server_scripts/static/index.css
 delete mode 100644 compiler/datasheet/server_scripts/templates/index.html
 create mode 100644 compiler/datasheet/table_gen.py

diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index 3d871054..b459d46c 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -52,7 +52,7 @@ class datasheet():
         self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS errors: ' + str(self.LVS) + '</p>'
         self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'Git commit id: ' + str(self.git_id) + '</p>'
 
-        self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p>'
+        self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration</p>'
 #        self.html += in_out(self.io,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
         self.html += self.io_table.to_html()
         
diff --git a/compiler/datasheet/server_scripts/__init__.py b/compiler/datasheet/server_scripts/__init__.py
deleted file mode 100644
index f670aeaf..00000000
--- a/compiler/datasheet/server_scripts/__init__.py
+++ /dev/null
@@ -1,24 +0,0 @@
-import os
-import jinja2
-from flask import Flask, render_template
-from filelist import *
-
-
-filedir = './files'
-file_data = './filelist.info'
-
-
-app = Flask('server_scripts')
-
-
-if __name__ == '__main__':
-    
-    files = filelist()
-
-    files.update_filelist(filedir,file_data)
-    
-    f = open('./index.html','w')
-    with app.app_context():
-        f.write(render_template('index.html', filedir = filedir , os = os))
-
-       
diff --git a/compiler/datasheet/server_scripts/file_data.py b/compiler/datasheet/server_scripts/file_data.py
deleted file mode 100644
index f5ed4c23..00000000
--- a/compiler/datasheet/server_scripts/file_data.py
+++ /dev/null
@@ -1,4 +0,0 @@
-import csv
-
-class version_data:
-    
diff --git a/compiler/datasheet/server_scripts/filelist.info b/compiler/datasheet/server_scripts/filelist.info
deleted file mode 100644
index 77d515cc..00000000
--- a/compiler/datasheet/server_scripts/filelist.info
+++ /dev/null
@@ -1,13 +0,0 @@
-./files/test_files/sram_2_16_scn4m_subm.py
-./files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib
-./files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
-./files/test_files/sram_2_16_scn4m_subm.sp
-./files/test_files/sram_2_16_scn4m_subm.v
-./files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
-./files/test_files/sram_2_16_scn4m_subm.gds
-./files/test_files/sram_2_16_scn4m_subm.html
-./files/test_files/sram_2_16_scn4m_subm.lef
-./files/test_files/testfolder/file2
-./files/test_files/testfolder/file1
-./files/test_files/testfolder2/file4
-./files/test_files/testfolder2/file3
diff --git a/compiler/datasheet/server_scripts/filelist.py b/compiler/datasheet/server_scripts/filelist.py
deleted file mode 100644
index 154d586a..00000000
--- a/compiler/datasheet/server_scripts/filelist.py
+++ /dev/null
@@ -1,16 +0,0 @@
-import os
-from deliverable import *
-class filelist:
-    
-    
-    def __init__(self):
-        self.list = []
-    
-    def update_filelist(self,path,outdir):
-        out_file = open(outdir,'w')
-        for root, dirs, files in os.walk(path):
-            for file in files:
-                self.list.append(root + '/' + file)
-                out_file.write('{}/{}\n'.format(root,file))
-                #print('{}/{}'.format(root,file))
-
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.gds b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.gds
deleted file mode 100644
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oCmr19/6lSPHpF9orVrurY2CEhJSsqECdu3J0bNOc5ut1iuuuqdd5Kv5npM6h4vydF0SBBKRPvN057UHK4ZeLoS/57rq+avvbZ//8CBUBw2/n1D2h9QNnHIkDffnD0bZB3ivqHJDBcrqISv5aJN5IAWQjOkYYm2/WjTPyBKCsoI4hsa6000yTnS1gMU2Wyp1BEY9hpakaY13DYgepFUQQfuvHP9+kmTtmwpKenaNbJPtD1NT4SaB7PAs7LGju1oaq4l0Zqe6PZDaX9qrtc1o5eaQ+HX55/fvXvoUFTztgIMbtMuufnmvn31iLZGQnBQ4I4dI0ZAFu/48e++O3NmaBpMaLoFEDpcEtRZG5fVvmpjz7ENowQtA/2FqCrUHkl0XyX/SJNzbUDVlPz8l1++885f/GL9+okTtWsh/Qli2InuYS1wTqGCTWifQBg0mfuDJI4WEHTgtts+/PCGG9pfNF07aFJfNQdplqS6up079VVzSs3mbt2So+Ycl5MzbZrR2K/fH/8Ir7D1aNtpKU2P/3rTgmoeDrg29FJzmJ9BWwQWSQTagnpA81WiQ6VKK15FRT9UYciubqlBkKDskNcbyfvjjw3HFkfXZkUnJx89+UeazGsDYuQQ+w9Nf4InFeG2q+83IlydFrglgwo2+h470rLoLOizZl133YABmze/8MLtt8MrLAn3foimtydNh8f6iVBzECCvd+/eu+7SS81Bs2DKnkSrOfQkTOJjNPbqde+98Apbbyuartf1hmre/J7DtYFq3rYIzTkGfQmN44KmhOqjVrwgHqxVHIi2QrWKUNHRzgAKk9dEu/9FRT//+ccfQ+WW0PZBjyDDW7s8tMJ06HBJANJmIC4b+gprte+PbRhlaBxdvzP8Q1rqSJN/bQDwREW73eYH5ur9jbj++p07QweDgppjnZb2h24TFYGIr179l7/ceqt2+U9+Mnx4QcHs2U888dFHa9Zs315cHPpZ0PR3373ppi+/vOmmvn1LS39saz+c3kg7CZE21QTUJHIpSfREOZGRjFSTRGtWKDzfpctNN4Uuh63DGYwtaznRZw3ad7m2bbvuungmvQrX84lTcxBcn+/o0UWL9Lip4zi73WweNOippxKn5vGP30A1bylAmwoLc3Lq6qBGNcjE4cN33716dfOfhdQRECBYAsIBiSWgJpBMAm1+/PHs2Z99pu/+Q8vwGsksoSDBy5bt3XtpVDV0uCTEQZuvpwFr4Z2wD9phlJFP6wP9BnH0aOc6jZaWOtLkXxtaFi/+6qsRI2AmUVgC/Qx7rj12fb8R4ZKpYMhyJHse7YRTSMuiWwS9+Uh582sB0PR9+y5c6Nw5sm3+MJrO81273nYbRGRBgGDIZrQT0CQ/CzlIy6g5pOUkPtdcVSUpca0n/qzF+/Qm+WqeuFSr1qnmAEyRhmqefECboBbK73+/adPYseGGV8ISWAvvDDd9DLQJWeAzZ65ePXUqfCo0eQDaBK0JV4mlebT7HJprDsB2YSgeCOKhQ9XVmZna91yuFviRI5FVMAt9Z2wJJKGx3kTQskeazGtDC6S7hF4hy5Zdf/2l5YYT8Y1AOg5Uktav53ntohtu+PDDu+768suysmiqii5f/uCDU6fec8/06cOGha5dseKLLw4f/uUvn3tuw4ZIWvvyy9tv/+STESO6dKmpieT9HJeXd9ttFsuQIS+8ELo2+IgfSgRGR6KlCqA0JWXAAKt1+PDlyxnGYunaNTlqnohjCUcw77xXr3vvDV0rihcurF/v9x86tHBhWzjScBXiL59G0laqg0dypK1ZzUGbcJgUgiAI0laYNKl795KSL7647bZ33tEu1y2C/sYbGzYcPOhwuN1+f+hau91iiWa2rUmTVq6cMSPyaDrL2mzh6xmDWMR2XCAKICWwBGYhBXGJv9+CWeBXX71qFaVGY2amKJaXf/BBe1JzANJXYIInGOoaCFRVbdoky2736dMGQ5cuN92k1xDM5EfT4RrT1sJPTs+jmgOo5giCIEh7gn388blzWVa76L33iouHDCkpaWpKT4+8ocrK+nq3e82aoqLiYr9fFCVp376TJy9csFrNZoNh/PghQ/Lzu3TJzLTZNmzYvfv06UjafOedo0f79Zs8uUePioouXVJSPJ7m328wdO16aQY8EAhUVm7cGNtE9CBAIOVajVBVn+/8+Xi6PlTdAgFQ86NH//SneFrWYjINHvz88ybTgAGPPUYpx9lsyVdzLbLc2Lh/fyBQUbF2rSRVVm7YEAhUVHz8McdlZY0Zw/PZ2ZMmUWo0du4sSTU1l5aRihZVFYSaGkmqq9u1i+dzc6dN4/nc3BtvVBS/v7paD4VVFEGAqwvOIOw/HIssezwlJVbryJFvv61NJYIpruLvSVRzANUcQRAEabv07Jma6nDceecVV1w6YkQ3QQcaG91uv3/LlgMHSku/+OLbb8+eff/9rVu/+w6Gis6YMXp0375+vyBI0q5dx46Vl0fSJmj6jTf27l1Wlp1ttfp8oe8J6jLDGI0cl5ERHFQB0c3YBsklToDCZYELQnHxk0/G07IWqItiNg8a9MwzlLKs0SiKFRVr14riqVNLl+q1Fe0RMYzN1qcP9BXIa2Sfvqi5bVfTYT9hn2H/eT4v75ZbKGVZszk4cY8+57d9qDl8N73eAwfuuw/VHEEQBOmYhBN03XLQm2f48L59c3Kg8GJ6ekqK2bxgwdKlGzdCYkwkLUABpk2bbr/9k0/69cvMdDgS11nJVPNEx7MZJiNj1CirdcSIt96ilOMslsQNTIQl8fVYYgUx/K2RPnNeAjbb+PFFRQxjsXTvrih+f1WV27116zXXxN9ye1LzeMo+opojSFuEUkJkuaX3oq2gKGYzy1LqdBIiyxkZqmowVFTIMqUcR4iimEyEqKrZTIjBUF1NqSimpcWzPVUl5NJwLZIcEp6D3jz79586VVU1efIf/rByZWOjy+XzLV/+4IPTpv3kJ8OGRVYBHUZDX399dLnp0dKe1BxQlIaGPXt8viNH/vhHWKJXNjZMOaRVcwCODorxRd9qourcB3vjh7npMGhV3+mH3O6dO2+6SZLq67/5xu3+6is9RuKjmgMwAzGqOYIg7R1KZVmSTKaGBkniOEplORDo04cQSera1Wp1u3v04Di43VHV8EUtkbZLUmcSBU1fsGDp0mCNUqibDvH1SFoATYdZSOPRdJbNzBwzxmweOvSVVyyWq6565x2TaciQF19sT2quBfLvYbuwBI4U+iHWPkxNDV+8Mp6BucnXdH3bh/33evfsuf32+KuPo5oDoObw3Y9/3xAEQVozqsowokiIqtrthPh8bnd6uiQdOkTIjh33379v32uvffllWlpV1aOP5ufL8siRLb2/iP4kVdABmK4IUlwg3QVSX5Kj6dpp7SEjmeOyssaONRjy8m65RVVl2e/XS4BArYIzZeqj5rD/INbR1neH7Wo1Heb1jLadYGuVleEH3UJqRzy91/Y1PV5QzQFUcwRBOh4sK8uEiGL37qmpqipJ/ftbrV98UV+/YkWPHv37f/vtF198/fXzz//kJ5J06tRLL7X03iL6o/Mg0ciBaDoMGJ0x45pr+vYdPrxv39xcbR2Y5lvw+2WZZbdvP3cuLw/mH7XbjcZAoPlPQUqDdiCpFlmGooqnT7/8cjxHB/F4k6l37/vugyXxqznomtU6atR770G9mmB6CcMYjbJcX3/pFAnhAL2DIZIwXBJuVGAYJQypjKQdeCfc0sBNTnC5LPt8DGMwpKfrMdAz2UNI4drQq/3YQDUH1q8/dapHjzlz1q2bPLn5d95zz/TpQ4c+++zdd0+cOGPG6NF9+pw9W1nZ2AjVpeI/LgRB4odSyHRGfhyOk2VZVhRCTCaTyWxuaDh9+rvv9u//xz/eeae8/NChpiavd//+oqL6+h07cnJmzFBVVU1NJYRlBYEQSg0GQhjm+HFCOM7ttlgyMw0GlmUYl4vSmppu3WQ5L8/p5HmPh1JZpvTSsYhIMgk3SLQFIuhannvu/fd3737jjQ0bDhwAQd+8ecmS229PT7fZTKZIWjh3zum02aZOXbVq+vSKCpfLao1vjyQpvp9ziG0H4/Gqqig+33ffPflk/AktwfrrPwRuOSCyHnlr2mg6RPdB2qKNpkPRQKdz48aePeEVsq71jkl3lGh6W1FzuN6gfyBJzGodO3bDBn3VHGYXbv6djzwyZ87o0cExLcOHFxTMmjV+/IABW7YsWXLHHT175ubGN3AKQRCkJZCkTp0I4fna2qYmVTUaKe3T57HHZHn8+H/968UXH3988OBPPz1woKlJUUymPn0IYVm3mxBFYVmWlSSGIYTnCwosltraffteeumKKz755MCBe+/dufPaazt3XryYkJoaWVYUScrNpZTSHytjjSSfFhZ0ALLStZoOP7eRtxC5pgcCNTVFReHWimJZWXwaDZFsmGyIUkoZxmDIy7v55vgmNuI4ux00Otw7oGZItO3qpelaoORlqOzqMUlQe9b0tqLm2tagf+D5Ccva7VdcoSii2NCQHDUHQMpDl6el2WwmE0TW4+s9BEGQZCPLBkN1NSGKAnkBsqyqLFtfbzKdO7dyZV4ey3KcKErSFVcQ4nYbDISoKs+zrKJwnMGgKI2NV19dXFxc/M03f/7z9dePH9+3b3Fxjx6qeuHCe+/NnZuWZrPV1Jw9K8tGY2WlqhISb3AT0R+upXfgIo8++sYb27aBoEMMbPlyt3vqVO2g0ubRavpnn82du2FDXt4PpzdSlMbGvXt9vmPH/vIXlk1LGzRIVQWhrk6Wm5qOHYttMqNQ/H6omqIogQBIDAhNrOIiSU4nSFuopquqqsqyLHs8paWx7a02ug+CqN3b2ARRK7vQGrQcusXouajpWk0M9ny8qRqhe65v+6EkUs0JIUSr5pAsFM9RQDvhbggZxmDIyIhNzXfsKCvr0iVyNQc4jmWZGAMNTU0PP/zWW7F9NjZSU5csmT8/mVtsKZLft0BsPYxXAtLaUFVVTUnheZ8vO5tlCfH7VdVguHDB5Sov37q1qspqzcgQxQED5s4lpGfP118npKzsttsoVVVJEgRBqKrauvVf/zpz5osv9uw5f37BgkWLCDEYCKmqghCm2z1s2EMPEWI2nz5ttzudiuJ0clxmZuR7iN+aRNMqIugATHI0efLDD69cuX//qVOVlffcM336sGHPPnv33RMmRN6OVtOrq91uiyX0PYFAWdm774JGQw1svdRcC2gQRCvDTQUfOUFp83rLymCJqiqKKFJKKctarcOHv/pqPHH6RETTQ2PSehV5TE40HQomJqL9ZAJXIPwNefzxnNNEAEO9p09fvXrq1Mg/BYlwBQWXT2JxONxuvz/ymRaSQ0tpa0ego/14I8mE4/z+vDyWFcWsLJaVJKuVZWXZaCSEUpiST5ZVlVJFUVWjsbZWVQ2G+npV5fmGBlXlOKdTVQ0GQVBVg8HnU1We93pVlePcblVlWbNZVVk2JUVVOS4tTVU5LiuLEEJMpkDAYnE4BMFiSUmRZZOJEL9/06aFCz/99N//zspyu7t2HT3abj958pZbCDEaS0okyWYzmdau/dWvqqquuOL3vz96dOHCL7+cObOmZsKEJUvKyydNWriwqWnkyMWLKeW4mhpKvV673eXiOEwFbH20IkEHQNNnz37iiY8+gorpjzwyd+4110T7qDorKyend2+rdfz4oiKn02KZODH+fYP8cqOxX78//jFyxdRL04PKWFQ0fjxke7tcW7ZcdRXoI7SsjVLHBmq6Fm26TuI0PRF9nrj2IYkLeiN0LUz8FHlroOaTJq1cOWNG5J8CNYfxKvn52dmpqVu27N9fUvLcc6tWff01JMv95CcPP/zf/549W1mZyEnNEATpCAQCdvvx45Jks50+LUlWa0WFJFks1dWqqqq5uapKiN1OiKqaTIR4PNdcQ4jHM3y40eh29+uXmup05uVZLC5XVlZqalNTampOTlMTy+bnOxyS1KWLIOzZk5srCLt3d+okCHv2ZGaK4u7dGRmiWFpKCKUeT1oaw5w9y7IHDvztb0aj3b569Z///NFHp04RQkh5ucfDcWfOECKKubkpKV98sXDhypXvvrtpU2lp795/+9u5c4qSmWmxGI2CQAjLpqSwLMuyrKoqiqK0dL8izdGKUly0wM8qTGwERRi1WenNR8VCZy3973/37v3Zz6680unct6+gIC0t+ofv2iSES5fn5k6b5vXu3XvXXc23AJrOMBZLt26QswslDiP5bHh+mOwB+6OqgcBTT8WTxoBJL8lt/2IPQOoIDPyNv89D24e/4z+n8KngAGWeT02FZzswaDiSFuJXc0iHAx2PPBGuNQBx9PYa8cWnBEh7xO8fMMBkgtm5GYbjRLGpyem0Wk2mr76qqjp37uBBQWhsPHfOZrNYAoFp0264IS/vT396+OH77jObDQZZ5nmf7/Rpk4nnKeU4VQ0EzGaeZ9mUFEUZOpQQluU4QljWaBQEQRBFo7Fr12uucbsVRVXnzfvpT+fN27evro6Q7dsPHbruOrfb7//2W0IuXLDZZNlk6tz57rsLCtasefHF1asJycx8+OGVKwkxGKqqeJ6QigqO83h8Pp5nWatVkihVFEoZJtbkQCQ5UElav/7S8jo33PDhh3fd9eWXZWWXG3qVfEC49+17/fX58yGmDuIOhRq174R5SWHyI1DzRx99442tW6FWzLhxXbtWVb388pQpO3ZEq+kpKZMnHzwYbphmMMIaSaHDxBW5S1TLBkPPngsWQA0ZvTKkEzl5U2LLCCa+fUIuLVaYiKz0RGe9N09sag6sXv3447feGqzTsn9/SQn8axDP/rStbOnWT1vMTG2L+9wWoZQQmPsyWUDqCCGq6nBQqihQCLhTp86dfb7s7Jqa1NSdOwnJzLRaCamsTE8nhON4nhC/v7KyXz+f7+zZysqDBz/77OTJTz4ZPNhsNpvNZkYDKDUhqmowMAylLCvLLCvLDEMpxzEMpTzPMAxjMIgipUYjwzAMx1FKCMfB8kCAYQhhGIbheYaB94DCMwyUpYR3wlqDAWYVhSMTBL9flm+88cYb77133brPP//b37Kyrr566VJCCgt/+1tKGSaa4omqSsilRbebB781ejFpUvfuJSVffHHbbe+8o13eBu6fLs4/Gn5iI0iA2bx5yZI77oD3wPtBzeE9O3aUl+fk3H//55+PG1dS4nBEk17SfAWVaEhcSkaiWoaYKGgoJr0kvn1CLk2Lgj43mwcNeuqp+GoBXaT5pBftq15HBMSj5suXP/jg1Kmg5jBGBRLh9N1DBEHaEyaT18vzRqMoguCKIqUcV1FRU9O58+efE+L3DxtmtZ4+nZ7OsmfPvv/+o4/26vXMMz7fW285nUVFf/vb3r1VVV98EQhYLFaryWQ2WyyQd64owddgZXdY0lyV9+D7tZ/94d9wA3O5tapKCKUwP0xwW7KsKIHA9u3bt7/3XmZmdvawYYQ4nR4PIaqam9vSfY/ESxsQdADSWrSaDrE0bRVkiK/De8KlwYCmP/30rl3DhrndohjZ/aUk1dXt3Bm6HCqoQGm5aI6m7Wl6IpQRNT3yPo9/kHEooZpusYwc+fbbMPctvFqtY8Z8/HH8W3Q6u3X7y19++tP162fNivazoOYwZBzUHIaSw3gVvXo7+bS/VBCMqCGtDb/fZCopEQSjkWVlWRSzslRVljt37tvX5erbNzPz2LF587777plnVq1yuf71r8OHH398ypTCQlk+fbq42GxmmM6dBYFl+/VTFEUJBPx+v9/jUVVVlSR4VRRVFUVVJUQUVVVVL50qUdFACCGSBJINrakqIYGAoiiKKCqKqgYC0BqsBbOANoNbCW4RtiJJVqvNZjLBWklyOs+cKS8/dmztWkIIqatr6b5H4qXNCDoA2g1Zpz17dumSnv7ss/fcM3GiNvUlkroNq1cXF/fq9cADmzePGROJpnu9Bw7cd592cnuQcqigYrEMHvzss9FLTNvWdL2UETTd5zt6NJgigpqe6D7XApouihUV69YxjNEI1QOCwBbDTZIVCQ0NGRm/+lXXroMG/eIX0U5Dlhw1R8lDkPaLokBKiMdjs7lcGzcOHlxe/uCDRUWPP75iRV3d+vWpqV26+P3l5YS43dde63Ll5Gza5PPZ7fv2iSLHBQKyLEl5ecHodegraHcwqt1cAg+sDb7Cpy4uCbZzMVIefL24Nhi5D10uyxxns1mtXbsOHTptGiEGQ2T/xiKtmTYm6IB2YqPms9KbJxpNlySn0+c7ePC++4LzZW7ZMmKEHtp0UfJgmB1IHtSKia+f2pKmQ5lLiObCEtB0PRItUNN/HFX1+8N/d2Bwc7RtnjxZX5+WNnToE08EAqGzBTc/xyckrYGaB7/j7SFqjiBIIkhJkeX6erPZ4+nZk+PMZodDVTnOYklNdTjMZoNhx46nnjp+fNmy48c3bXrttfx8s1kUBcHhcLszMtxujrPZBMFiKS01GJqa8vM5zu3OyTEYAgG/32gkpLycZWXZ52NZWQ4EWFaSFIVlg4otyxCyI0SWIcItCIqiqn6/ohAS/JvnBcFoZBhRZNlgegohPh/HqaogcBwhPh/DqGpTE8sS0tTk9SpKRoYoKorZHAj4fD4fwwQCLhelhAQCRqMoulwGQyDgdHKcqrrdlOblLVpESGHh//0fROlb+pwg8dImBR0ATR8x4t573347WjXXEm00XQtoE0TWQZugNkv0eyFJTifE6SHZA+pj6BVFhvi0dnZMGPoZT7uJUEZt0gUs0a/gIGp6c8C1EW6toni9589H3hrkml9//cqVM2Y4HIJgMITOFrxv3+uv/+pX2pEkAKi5NmkNbr8TreYtFUdvH4kumNyCtCwuFyE9eni9mZk7dxoMqjpkSFZWaekHH7zxxl13rVzZ0LBx47BheXlOJyFpaV5vS82aeTEKrqoMExzoSUinTqKoqp07y7Isd+qkKJLUqVNWlqLs35+SQkhpqdlst1ssHg/L2u2yrKq9e//610uXHjxI6dVXv/56ly4LFnz3nck0cuSNNxKSktK5MyHBjHakLdOGBR3Qq87xmTOyPGaMyzVw4AcfeL2ERDOfFgglaBmUUIxNyxKXkx3aMiQtxN9yojVd77rgqOmXB4YCh461gKPw+0+ceO65SNoBNb/ttg8/vOEGUHPtWq2mhw74Dqfm8dx+IwjSEVBVt/v7702m2tqrrvJ4tmyZN6+4+IUXiotnzuzTx+Wi1O12u51OjktPr6212+vro23/h9nkF7erqlBRPIiqQVEu/ZzPBxnkHo/H4/MZjQaD3Z6ebjZfuGC3E1JZGQjIsiC43arK8xkZU6d++inDXHfdF1/k5v7yl5WVnTv/6lcul822YEFp6Vtvff/9qFGEDBnym99UVopinz5+v9HYuzfUk4E9bulzgsRLmxf0+NHWTe/Xr0+fQYO2b3e5fvYzjycQiDSarqeWJVPT9WoZNT257Seqz6EqP8yfCq8ez65dM2fCETX/2ebVXEs4TUc1b4tg7BxpDXTqBBnYNTXz51dVvfNOaqrNZjKlpooiIXa7IBgMXi8hDON22+1eb3p6S+wjpTC4U1FSUlJSUlOdzqYmr/f8eVGcPp3SoUPffDM3d/780tIePR55hGEaGzt1mjfPZBo5csGChgaez8vz+1mW5wlRFI+HEEqdTkoZJvjKcZIUCHCcLPt8qkop1jhv+3ToUxg6pRFUgJkzZ/lyQXj++d27hw51OptTjUtBTUdNT2b7iepzuEIir4l+7FhtbUZGJGquJVTTtctbSs0x0QVBWj92u9/PMKrK8zyfmpqS4nb/7neELFmyb98rr4wZYzTa7VlZfr+icJwss2wgQIiq8jylqsrzisIwgtBc6wwDiShQm0WSFMXjoVRV/X5KVdXnI0RRgq+yTIgoMoyiGI1ms6K4XIJgNp8/z7KE+Hx+f02Nx9PU5HJVVjY1OZ01NS6XxdK7d0rKlClvvJGf//DDTU35+f/3f8ePU3rddU88IQgZGQMGeDyi6PdTmp6eni4Ifr/XC1nslHJcIEApIVBkkWXhuOBVlhlGUWQZ9j445BRpy3RQQQ+n5toKMMuW7d07aNCLL+7ZU1gYv6bHNugTNR1ATU9+n0dCfT3HjRx5++1r106eHLmaawEdf+65Vau+/hq+g2vWbN9eXJy4fUYQpK3T1GS3V1ZCZRZF2br1hRceeODRR6+8kuNMpvr6YKwa8rwTi9GoKD6fKLKsLFdVmUzZ2Z07nzs3bJjF4vPJssGQl6coL764Zo0gdOnyhz/k5vboce+9DofVevXVL7/scrHsmDEt3ZdI66XDCXokaq5Fq+nRbOeHQzPjGfQJMq3NA4YM8vj1FDU9SPvU9JSUCRO2b7fbp007exZe9agORAgholhQsGhRQcH11//vfzfccO2148bF09qjj7755rZtkRRIRVoPmNyCtBwNDYWFhOzd+3//d+rUf/+bk6MoDAM53JCMR+nFUoZ6AFnkkiRJUMU8SH29z0dIRoYolpdnZFRVff/911/bbJWVPD9lytat+fm/+lWvXq+8Ulo6Z46qZmWNGOH3GwyZmR6Py1VebjKx7NmzLd2TSOulAwl6tGquBTT93/8+fLh//8i3qK/+Jk5PE63pMPQQNT2Zmi7LbveZM6Ez4MKNYjw1fCoqXC6r9cUXt23LyIAlkDs+a9Z11w0YoNdRtCyY6IIgrZmUFJZdu7aq6n//Gz48I0NVBYEQRbFaCVEUmw2yvH+sKrk+WCyEeDzHjwtCv34Wyy9+cezYmDG///2gQZI0ePCiRU5nTk737oEApbW1HKcoDgfLwqRClBqNfj/DBP8VRZBQOpCgw8yjoOaQ+RptxG7hws2bx4xp35qujdPrVYkcykeCkl6q6bED/SAIZ868/jpqeiiqKgi1teHWclxWVvSPVkHNp05dtWr69Gef/eCD776DW1xYC5MKhZZNRBAEiQ1VJYTjGIZSrxeSSVTVYCgo2L798cc7dbLZDIbaWreb57OzCSGEZYPJLQwD091HUzQZMBhkmRCWlaSUFEIUxWxWFJb1+aA1VWUYv19VWbampq6ustLtHj/+t789fXrUqGefLSwkZPTo55+nNCcnJYXS1FSDgVJFkSRKZdlkkmVKeV5RKGUYSglRFEoJEcWW7mOk9dKBBH327L/+9aOPoEYETIACZd2ibad9a3piKpH/UEmD81PGq6SCcPLk889DUkdwsnqoQx9/7nXb1nRZdjgOHQq/tqkpsgGggFbNz51zOm02WA63uKDpoWUTYcbQyOcNbW1gHL317CEmt3RMIN4sywxjt/v9JlNGBiH19d9807u30Xj8OMNQ2tSkqjBsUq8tKgohLMvzpaUsy7LV1QwTCGRlpaTIssPBcYKQnX3iRCAwd+411zz5JM8XF3fr9vzzHo/dbjIRAlXNEUQfOpCgQ10IGJQGS+DRfPI1HSLKsCSeKHVyNF2/lpMxsynDWCzdu+s3RLKtajo8W4A2tcthCayNpJ3qarfbYglVcy2hmr59+7Jld91VUrJy5e9+19Cwfv1DDzU0fPzxgw9ifB1BkMjhOFWF4Z5GIyGS5HKlph479uqrKSmi2NQUCDAMDEzXL5XFYMjMTE8nhOfz8wVBUfLyJInnLZZrrvntb6uqcnN///va2uuue/llg+HChV69Hn9cUUwmEHen02JxuYzGlu4zpP3QgQQdgBoRP3w0H5+mb9lSUtK1a+SfkuX6+l279IpShyZ76BVFbruarnclk7ao6dDmrl0zZ0LLwddI65qDms+fv2HDhAnh1FwLaPqiRW+9tW2b1Woy8TxUIoa1IO6QZqZHjyEdBYydd2QgFYQQRZEkk0mWq6qqqz/4YP78+vrGRpPJ62WY9HRKKdUvUWTfvjNnTp584olnnjl69J131qw5c8Zuz8/v1OnYsYoKQlR15MjnnvP7ZblTJ7vd7//uO1WV5exsSVKU3Fyv12rVY9pEBAE6nKAD2pgfLIlnoBtUgI5W0/XVX22yh75RZNT0RO9zotuHG0J4jeT9WjXfsaO8PJqY9969xcUXLoRb27Nnly4tM0VI7GCiS+vfK6S9IsuS1K0bIRzndhNSWnrunNFosXz+Oc+nprpcFoskBQIsqygMw/McV1oafGXZsjKeZ9nycp5XlOpqi8Vg8HgURVUFISUlIyMzk5CUlOrqpqZAwGB45pklS0pKnn76+edra/Pz8/MnTXrood//vqDgwQfvvbd37xkzZs369FOjcdy4++7z+x2OigpCZJlSp5PnKaWUYRwOShmmoYHSQAAj6Ih+dFBBBy6v6bEOdANNX7/+1KkePSL/lL76mzg9RU1P9D43377FctVV77wD+8+ymZljxsCrHlu8SEmJw2G3x6bmQGOj2+33h1/rcvl8+u4zgiDtFYZhGKeTEJ73+fz+1NT8/FOnfL78fJaVZas1mC9OiM8ny7LcubMsS1JenixLUo8esiyK/fo1NWVleb2ynJWVm1tb29Q0adLEiWPG7Nt3/Pi3344da7EwTJ8+zzzz17+OHv3YY3/4g9EoijU1u3alpppMPXu63YR4PKdPGwy/+EVjI6VpaSxLKaWUqqrHw/OK4vW2dA8h7ZkOLehA8wPdom3tzjvXr580KTZNhwoqWv2NTShR0xPdD8nXdI7Lyho71mYbP37rVjgKeNWKezzba2rKyvrlL02m0aPXrz92zOGI5urVAiM9YOIh7XKHw+32+7UjQNoWmGiBA0OR5ENpIJCdTUggYLMRwjBXXHHqVE1NYeGOHWVlubmDB8+YUVIyePCNN1ZVjRo1dWp19ciR06aVl2/Y8PXXNlt9PcOMHm00Umq1ut1NTWVlGRmZmV99tXbt+vVXXjloUP/+J06YTCy7b5/H43KdOMHzDBMIpKZaLBkZPp+iHDr0n/+sX2+1nj2bnl5YSAjHWa2KIoper6oSwjCBAMv+WOIfgsQDCvr/JxGavnnz2bPdukX+KVE8e3b5cm1Nktas6XrXTkFNb759t/v0aYYxGC6tmwviDtuNbRsQNT940OOZOLFfv4KC7t03b16y5Pbb46m+AhMP9ep1xx3//OfkyQ8//N//9ux5++3//CfOEhotmFKCdGRUleerqwnhuJKSzMycHL9/5Mhhw3Jzx44dOtTvP3p09+7x4w8d2rFjwoSjRzdsmDOnuPjzz2+7berUwkKjsVs3g+HQIYOhoaFHj/R0Uezb12bzeLKz7XaPJyPDanU4Ro40GPz+bt2gDowoGo1OpyQpSqdOimI219f/9a9PP334MCGpqWfOEEKIKDKMqioKIZQajYSwbCLnaUYQFPRL0FfTf/rTjz66/vp9+y5c6Nw58k/pK5ShUwUFZTpeElM7BTX98u2rqt9fVRXuHaETEkUCqPn993/++bhxM2c++WRREcwPMHx43765ufFr+tmzlZUOx5YtBw6Uljaf+oIgWjB2jgCCYDLxfEaG05meXl8vihzXqZPTeeYMpbKclaWqkmSzgcb7fCkp1dVut8FQW8tx6ekM4/criqJAOx5PIOBwCILRWF/vdtts5865XGlpBw74fCZTXZ2iKEpaGqV+f0GBwUBIXZ3J5HLl5NTUmM3duhHidvM8papKiCSxrKJQqqo+H6Wi+GND7REkHlDQL4O+mj5p0sqVM2a0rKZrpwqCmKte+pgY8U2spus7s2mi9xlQFK/3/Plwa6GyfuStud2iyPNPP71r17Bh2lxzSEHRV9PbEx1THDGKj3QcoKa6IDCM1UppWlpODmS5I0jyQUEPS/vS9HBDD6+++v334++rxGm6z3f06KJFIKB6KW/ozKZ6PVVI5K3FiRPPPQe3Ftrl0OeQHBVJO6DmDzywefOYMatXFxf36hX6HtD0LVv27y8pAU0vLV216r77VHXr1kWLzpx5773f/hYrmicTVGQEIYRSSmVZlmWZYRiGCWsvsBaGczIaIt+S38+yZrPJZLdnZREiyzjfJ9ISoKD/CK1H0y+dg7N//0ceif5oLuqjoghCbS3HZWRcdZXJNHjw88/H31eJ0PTQGVhBeQ2Gnj0XLIh1Ty8/BLN1F0yUJKfT69279667nM6NG3v2hFfo80g+H4maa5k9+4knPvrI4/H7AwG73WoNlg+DUonwLeiYkfWOGUdPDti3SHhYlmVB0BO7HVUNBCjleVmmlOMIgbxzBEk2KOgRkQhNP3myvj4tLfJP6Sd8kuR0ut27dt16qyw7nd99ZzB07frTn7bmpJdQTYdbFJ7v1m3OnFj3tK3WNY+WaNUcgKxxmHIodC18CzCOnkySH0fHyD3SsnBcIOB0NjQYjXl5RmMgUFJSWLhw4e7dikKIy8UwlPI8IZSazTyvKDzPcaoKSs1xskwppYEAw3CcJFHKcZQyDM9Tqijhk1ZUlVJJ6tRJFMvLRbG8/NQpQng+ml9qBNELFPQo0FfTr78+Wk3XV/j8/ooKr3f//t/8Rt8EkmDrydB0s3nQoKefToSmWyzXXPPRR9AbRmO/fn/8Y6x73pKaHpuaRw4O/UT0AmPnyOVRFEJUlRBBUBSb7eTJEyeamoxGu71LF4ZR1R/7tDbFRZv0Ev4Tqmo0KgrLiqLF4nafPEmIyZSS0tK9gHREUNCjRi9NdzgEwWAATY8m6UVP4VNVn+/8+dAEEv00/cSJ557TJueAUsfTZqI1PZj8k5ZWWAi9YTT26nXvvcEbjHjbT46mC4LFUljIsmPH7thx5owsxzqlkXYaLy0wkBSqnidi/1s/KJQIkmigAGIwyURVbTZCunQZOrSx0eVSVZ6/WKdFz20aDIpCqSz/9rfTp+flEeJyBQIt3RNIRwQFPUb01XSYhTQ2TY8/Mztcnrce+vhDMeX53Nxp0+JvOXGazjBGY6dOoevgBiO++Tt/fJbQ+HqbECgoxvO7dzudkydnZ2dlde4cz3MeuM5HjLj33rfegqsd6pq33SmH2jrJSTvB5BakNaAohPA8pZQKAqUMEwhQ2rPntdd26mS3d+4MsXBZ5jiDQVVZVvvKsvA3IVCFBVJfCGEYQlQ1fIqLIBiNDQ02m8+XmfnHPz7wQK9emZkm0+TJqkqp2ayqlDLMxVdoH0ESAwp6XCRC048dq629dDKa8PxQ0yEz22b7yU/27bPbp007e9ZmGz++qIjjcnKmTWu+rXCaHkzwiIdExY8To+mJRhut9/kqKmCIavyVZEDNX3tt//6BA2fOXLasoQFm9Iw/HQsi5XC1Q13zlu5DpP2AzyKQaDlypLxcEGSZ49xujlMUiLPrhaLA8FCHo66urEyWa2r27IGho4QEFR9ecfAokkhQ0HVAX02//fa1aydPrqhwuazWSD51qaSqqqpq55uEKYTM5kGDnnoqkhhtqPJCgoceyts2NB3y5i+3Fa+3rAz2PL5+IIQQeJLAMGZzXh7ss99/4kSstXScTkEwGEDNn3xy587hw2E5zOgJ6SihVybUYOmYlVj0AuUSQZLPkCE33/zKK6pqNNpsJpMshxf0aEsuMgyUVaTUbE5PNxhcri5dXK516zhOUdzuoJpTyjAsq6pYfhFJJCjougGa/uijb7yxdWs8mn7unNNps02dumrV9OnRaLrXW1YG/wyFroWZJiFJI7LWEheZbu2aDsNbBeHMmddfh7rjoOzQMux/PPsJ+wP7BvsZjKY7nceORdsaqPmLL+7ZU1ioVXMt2umH4Mrcs+fVV3/5y4aG9esfeghen3327rsnTIjnuJBkkrgUFExuQVo/KSnjxv3ud36/1ztmDMeZTD8+WDRSWFZVJUkUCbFYTCZZrq9PSSkv377dYlFVr5cQKLwI/w3G1BEkMaCg68xzz73//u7d4WKWkbcTm6Y3D0h8NO/vuJouCCdPPv881B0HZYcBtfHsW+LUfNmyvXt/7NYLNL28vLbW6WTZH8aQHnlk7txrrsGyibGBcfTYwH5DYsPlMhrz8zMzx459+GFCeN5uVxSWZVlCWJbjKCWE53meEJ6XZUKCJRchcQVeGYZSg0FVoeSitjijqtrthPB8ba0kWSwFBZ9/vmpVQYGqulyKQojVWlGRmup2m82CYLcnuiI70rFBQU8IoTHLxGt6cN7Nxx4LXQfx4NgUs61rOixp2dz0llVzLV27duoUPs1p1qzrrhswIPn9g7QGMHaOtB0UhWV5fty4hQsPHz5/PvF1ylX1xImXXyakvt5qFQSOg+zzpqaW7gekPYOCnkBCNX316scfv/XWaLN+QdPnzPnoo+uvr652uy2WcO8MBM6ff/99l2vbtuuuAwV0u3fuvOkmiAfHcyygklA2EZaAblJqNnfrFl8/BW8tFi26XA2ZeOuma29akq/p+qo58M47R4/27RutmgP79586VVnZ3NqOWjaxLdJ2lRpj50h8SJLX6/HwfP/+Y8f+5jerV0fymehrol9kw4Z//KOwMCuLUqvV7zeZ3G5C/H6sj44kEhT0hKPV9OA06UuWRD9N+pEjtbUZGfPnb9gwYULzmg6Rclmur9+1Kx4R1MIwdvuVV0KVGFgC4ht/4gegjXnLstt9+jRoenzVxwkJ3rRoNd1k6t//0UdNpsGD47tpiQRt3XeXa/PmoUPjOSOgNYsWFRWNGhVbCzCUubHR5fL5tMvh+lyzZvv24uJE90l7BaUTQZIDpYEAxxGiKFVVfv8VV/zyl126jB//8cdWq8nEcVA9HeYQpRQSWhjGYAgWWAwmtFwstkipJBFCafhBnwMGZGaePl1fv2sX/I40NhLS2BhpvTUEiQUU9CSh1fThw/v2zc2NTdN37Cgvz8kBTS8pcTj0qJzdPBADBlGGwaYguyC++m6LZVNTr7ySZW223r1hSbiaKtES1PTvvnvySUp53m43GLp2/elPExdNhzKX8LfTuXFjz57xtHb+fP/+O3YYDBwXvoJvJECMvFevO+549VWoaH6xxjnWNW+bxB9Hb7uReKTjIkkQBZckUVQUo3HChCee2Lq1rGzAAIuFkIoKRVFVntdra1lZFsvw4VVVX3559dXduilKWhoh6emYg44kEhT0pKKvpt9//+efjxunn6ZznN0OUx0FX3v1+u1vg6ksiVXz0FQQSM7Rb1twdHl5N98M/w/qn4hj0VfNx49/992bburaNTs7K6umZu3aBx6IX9MbG91uvx8qmmNai75gHL15sH8QPYCYN/xFqclUW+t0ZmTcccfrr1dXOxwWy/XXM4wsC4Je23M6Jam+PiVFFA8edDiKih5/nBBRrK9v6X5A2jMo6C1AIjS9psbjCZ/00jyQR56SMmHC9u2QxAKvRmPv3vfdp6qS5HZ7vQcO3HdfctQ8/iztS+E4ux2eAEChSVBzqM2i77Hoq+a33PLBB1OmHDxYXd2pU1rajBlLlsBy0HSjkefj03QEQZC2CaWyfHHCIJZNTTWbDx+uqvL7+/TJzBw16qWXAgGPp7par+0FAhbL99/7fLJ85ZWHD3/22ZVX8nxp6blzLd0PSHsGBb3F0FfTFy0qKrrqKrdbFKN/qAfZ3hAj1y6nlGVNJklqaPj2W0mqqtq4Ud8eQDUPxz33fPrpdddt3VpampenXa7V9Orqjz5CTUeCxJamkszkFoydI/oB6SuUKgohDCMIfr/ff/XVhFitdXVW68SJzzzz9tvbtwtCIODxKIogiKLDQSkh6ek8T6nXSwjLGgxQz5zjVJXnOU6Swv9barF4PF26EMJxlZVpaSZTevoNN8jyRx+pqt9/4QLLKgrDWCySpF/MHkFQ0FsYvTR99eri4l69Hnhg8+YxY2LT9HBQyjD6tQYkX82hjGPrV3OQmP/9r7g4mIUfSqimf/DB4sW33abvcSHxgDKKIMmF4yorCZFls5njMjN79Xrmma+/HjWqutpoHDzY5RIESTIaVbWpSRAojW1eEaj4Istud0PDkSMrVrz1Vs+eVuvu3cuXS5LRaDR6PEYjZqUj+oGC3ipoWU2X5aam8Frc/NpoSbyaExKsnaJVc21NdL1IhJpH/n6tpv/kJ8OHFxSgpiMI0jERRZ73eAiRZaOxqam29uRJh8NiGTRo1KgHHigtTUsbOHDePEWBSYt+WFhRW34xXPuKQqmisKwsm0xpaSZTaqrBIEmSVFa2adMtt2RmUlpRQQghlz6FRpB4QEFvRbSUpkP6CtQ4h9lGQZ1heqP4a6gDyVFzqJ7O87m506ZdquaS5HTqtRV91XzlyuPHw8fLmydU0/U6RqQtEnnKCia3IO0JKJpIqaIwDMtSWlNDCMsGAm43w9x668CB48f/6U+SRKnZTAghwQGm0QBty7LZzLKSZLNxnCRZLAYDy+7cWV+/ZcvKlYQIArSPIHqAgt7q0FfTX3jhm2+GDvV4AoEf03RRPHt2+XK3u6ho/Hio2N0W1Rzy6duKmn/++Zkz3bv/5jeffXbddbG14HB88snDD8PfWllHWgMopgiSHCiVJLMZ/qsoipKRAX8R0qlTba3X26/fiy/abFOnbt5stXJc586EsKyiqCohGRmSRCnLyjIhRmO49mWZUoYJBDhOEESR530+QeB5QVAUv99iqa/ftGniRELKylatUlVKDQZVZdlAQFUJgbrskU2HhCBa8KJppeil6TDf5Guv7d8/cKC+uemRgGoejt27y8tzcn72s7VrJ0+OrQVUc6T1g7coSMtiNvt8RqPLxXFlZYQMGrRsWZ8+M2du2gQDQg0GQpxOjgsE0tIkyWCIpWyiKObnp6Tw/MaNmzY9/XTXroQoCssSIsuZmYQYDA4HIZReOjEcgkQCCnqrRi9Nf/LJnTuHD4doutMpCAZDovcc1TwcBw9WV2dlTZny/vs33hhbC1o1T0+/6SZU89ZN8iW1+fQVnJYI6TgEAhwHuelZWYRkZKiqqo4b9/jjv/jFo4+eOmWx9O6tqoQwjNtNCKV+f7TtU8qyDgfLKgrLXnGFxXL4MCH79//xj+npkuTzERIIZGQEq80gSHSgoLcB9I2mv/jinj2FhXppOtRQZ9nMzDFjGMZuv/LK9qHmcBT6qnmvXq++escd48e/++7MmbG1EBo1V1VV1atPEQRB2heyzDCSRKksKwqlsux0lpe73Sz71Vc8/8QTDz74zjs9elgslJaXp6dbraNHG42iaDYbDIGA2cyyisJxDENIIBC+fY5zuZxOrzc93Wo1GhVFVd97j5DGxiNHFi+2WFjWZjOb/f7wLSBIOLiW3gEkUrSTsd9zz/Tpw4aBpj/88Ouvb9nCcQzDMGfPVlY6HPAarh3QdPj7iSeuvXbv3tj2h+NycqZNuzjP6KWzmbZ1NYfjgiXxq/kVV7zxxpw5dXVebzQ3VFowoQWJHxwYiiCAwWC1yvJ//rNjR0rK7Nm9ehUWXn11WlplpSTxvNt98X2UUqooPE9IpFnkHg/HZWQcO7Z69Zw5Y8c+/3xJicNBaXY2pYREH6FHOjIYQW9jgKbv33/qVGUlRNO3bVu69M47N29esuSOO/bvX758/vxZs667bsCA5tsBTf/3vw8f7t8/tj0xmwcNeuqpUDUHfL7jxxcvRjUvL3e5rNaKCqcztsq7qObthdaW6IIgHZnGRkFoampooHTq1JtvfvNNk4mQ3NzRoz0eVZWkujqXC2YhlWWGUZRoarPU1vJ8bu7AgT7fqlUOx86dS5cSEgjgBEZI9KCgt0kgah66PC3NZjOZli9/8MGpUyNpZ+HCzZvHjIlN00NnHtWiqoJQV6fX8WrVHApBJlrNfb6jRx97LJ42L1xwu63WgQOXL58zJ7YWtGretevs2f/4h179iSAI0pGRJEpTU1lWUSoqqqsF4eqrKR069MMPKTUY+vdnWaMxPV1VobRidPnj3btLUiDg8/G8yVRfv3HjhAldusjy1q0tfcRI2wMFvU0CCS3h1qanp6REc8cfm6aDKMe2NnKMxn79/vhHUHNIm/F6Dxy4775Eq3kgcP78++/H1mZ1tcdjsQwY8Prreqh5jx5z577yitvt84li/MeLtCwtFUfH5BYE0UKpqoqiojCMIFCakqIolA4d+rvf3XDDE0+cO9e9u83m9bpclPbo4fPZ7d99F3nLPh/LnjsnSZKUk5OerqpnzzY2HjlSVKSqspyerqpms9drsfj9KSmEyHJKSkv3BNJ6QUFvkzSfZX727IULjY3RthmtpoMoa0UcBBoEV1V9vvPn4zlGUGejsVeve+9NREa7NocelsSv5pBl3rfva6/NnRtbC1o179375z9/9VWHw+3GzEUEQZDE09hI6dChFRWimJlpNKpqQ4PR6PPl5ETegqIoisUiy1AH3edzuQ4dWr/+1782mVQV6rpYrbLMsoKgqizrcrX0ESOtFxT0NgkI+oIFS5du3NjY6HIFa6yCms+e/de/fvRRbC2Dpm/ZUlLStWvz7wRRhomNIFcbpjeKR3CBRNeBgWozkEMPS+JXcyhkCXVaYmshNNe8rq6pyeuN/3gRJDlg7Bxp65w/z3GjR48aNX9+SUlmJsc1NTEMIX36RN4CywYCGRmCwPM+nyzLstGYm+vx7NqlKJWVn31GiM+XmRkI8LzPRwjLYn10JDwo6G2YN97YsOHgwYyMmTOXLqV04sSnnurV6+c/f/XV/ftPnaqqiqfl22778MMbbohE0/UlOWputY4a9e67kEMfv5rDJFBLlnzzTWFhbC3gMNCOBoosgrROVNVi8fkqKhobCwpEURAUpaaG5xsaIm/BYJBlnpcklhUEl4tlMzKMRpOJUlEsLy8q4nmTyW6HoaeEqGqsxQOQjgAKOhKWX//6iy9mzjx/vlOnYKQ5cbRFNfd4AgGOe/TRbduuvjq2FlDNEQRBWhOqWl/PMEOH/uxntbUcx7Lp6QwTTbqm2200CoLVKoo8zzAs6/V6vYT4fH37UgoV1aurbTavNy2NEIMhGvVHOhpYBx25DDAFEtRZHziwb9/c3G++2bKlsvKKK0TxlVfia5vj7HYY9BmsA8MwBoPRWFDwq1+1FTUXBFlm2S5dXnrpF7+IrQWtmo8f/8AD774b/5EibQuIo7ePYoj4TABpL0iS2Ww2qyrHGQyKYjSKoiAEAhxHaXzt9ujRqxchp05ZrSxLCNRax0GiSHOgoCOXoFVzqLMOM5guWLB0qc+3YcPs2V26jBvXvfuFC7G1D6LMsqmpwcmSAFWVZUFo/WoeCCgKpZ07//3v8+bF1oJWzadMeeSRVasOHTp9GmruIgiCIC2J3y+KdjvHUWqz8byqer2EWCyESFJ87QoC1EIPVmCD4o3xaj/SnkFB79AMH963b04OSDlkrl9ezYMzmE6fvnr11Klffnn77Z98MmJEly41NZFvi2UzM8eMCVXzIIoiiq1ZzVWVEEqzspYu/dWvYmtBq+a33PLnP69Z8803331XURH/8SJIS4Gx89hoH09OgPZ0DXBcVpbZXFn56aeff26xmEx+v88nyyxLiCQZDPG0LIowINTvVxRCKJVlQhgGIumXm+wPQVDQOygwmdE990yfPmwYLJFlRVEUlmUYhglVcy2TJq1cOWNGtJre/MRGlPK8Hg/7EqHmp041NKSmjhz59ts//WlsLWCuORKO9pTogiBtBVUlxGgkRFUh9CKKhDBMIKAo9fWKMmZM797ffuv3u929e5vNomi1iqLBENnMGzab3282V1enptbXWyyCYLHYbJQajbt3V1babCw7cKAguN0mkywTIkk2W0v3BNJ6wUGiHY577pk+fehQrZoDoOZQqDGcmmsBTd+378KFzp0j2a4sNzUdPQpZ5qFrRbGsbNWqeI4rEWpeWtrUlJKCao4gCNKegDlCCTEaGxpg6j9CRLFPH4Ohvv7gwf/856mnunc3mTyebt1qajIyzpyJvGVRZFlF4ThZNpkIcTjOnw8ERJHjCMnJGThQlkWRUpZVVaji0tL9gLRmUNA7HD175uampenVWuSaDlMXQZZ5IFBZuXGjJNXV7dwpCGfOvP6633/ixHPPxbYPBkPfvg89ZLVeffXKlXqpeUWFy2W1Dhny5puzZ8fWAqo50r5pT4kNSEeDYSj1eAhRFLudYQIBvz893e8/cOD++6+5prSUZSWprEySeN7vNxoDgWhm5pZljvN6jUZRTEmhVJYlqbqaYQYOTEnp23fsWEIotdk4TlEUhRC4SUCQy4MXR4djy5b9+0tKwq2NrYY61E0/ebK+/sfUH7LMfb6DB++7z+vdu/euuwTh5MnnnydEkiJ7gKgF1Nxk6t37d7+jlONsNr//5MkXXohfzadOXbVq+vTYWtCq+aJFb71VVBRbO0jHAWUXQZKJLHOc202I39+9e06Ooshy374GwyefPPfcHXdwXE5Or1433eRw2O3nzuXm1tVFM1ERqD/LyrLRaDDY7Wlpo0ffeef//udySZLFQoggKAoIOg4QRZoHBb3DsWXLgQOlpc89t2rV119rl+/ff+pUZeWjj7755tat0bbpcAiCwXD99StXzpjx3XcOR48eiT4KqJsOag5LJKmhYe9eUTxz5rXXYmtTq+bnzjmd0WcHatX82WdXrvz663/+c926ffsS3RsIgiAdGVXluEBAVRlGllWVUkgf4TiWFcXs7IvvcTrhnYQYDPn5Fosg7Nw5ciTP//e/mzY99lh2ttsty3a7JNXVVVaazYFAdrbbnZLicFBKCM+rqqKwLLQUfL3cnuTkyDIhZ84Q0r37NddUV3s8ViulHMdxlBoMDQ1eL89j7Bz5MXCQaAfl0UfffHPbtueeW7Vq925Y0tjodvv98bRJKc/b7SbTyJHvvedyyfLevSkpZ88++GD8ews6zjAWS/fulJpM2dkGQ17eLbfAWlBzr/ebb+bMia19fdUcpPzZZ394C4QgzdNWBoxivB9pbVgsgqAoUBlFlillGEmilOdV1Wr99luW9ft79yZEEAYMoJRhnM709BMntm8/fvyDD7p2zcoymbp1q6mprpYks5mQ+NTZYPB6RVGSLJa0tJ49r7pq48aUlNGjX3jB7SbE623pfkLaEijoHZr4pRzQVk8vLOzTJzeXEEJuvvnbb0+cWLeuXz+D4auvYmvZZLryyqeegomNQtfC0FK//9ixRYtia19fNU9Pv+mmJUugLgCCIAiSHLxeiyU/nxC/3+PhOKNRlgmpqzt3TpZTUgYOzMpimOLi+vp9+/70J6/3u+8eeKChoapq3z6j0eVSVb/f5era1WLh+XPnYPBmKFRDuH0QRVEURZ8vN5fjhg279trS0upqjsvMJMRsPn2aUlHs0qWl+wlpS6CgI3EROrFRY6PL5fPNnv3EEx99tG/f8eP5+Vu3/vznqam9eqWnX65+SzgoNZu7dQun5gAMMI1tz6ur3W6LZcGCTz8dPz5+Nc/MnDnzxRdRzZH2DcbOkdYJyzY1nT4tyx5PTY0knTixY8fdd9933+zZy5bNnVtcbDAYDBcuEOL3T5woy99/X1WVmUnpzJkXLuTk7N9vMEhSINC5c01NXp7fbzRGM78HoCiKoig2m81ms+XmjhpVWztw4NSpgwcHAl7vrbcGAn5/164uF8PgrBdINKCgI1EAFWCgUOOJE2Vl9fX33XfLLSNGaNV88uQ//GHlyouDTQ2GW25Zs2bKlM8+mzt3w4a8vJQUjyeSbUFCS/PvgZotUB8m8qMANZ8/f8OGCRN27Cgvz8mJth+0at658y23/P3vsqwoKOeIHrSVRBcE0QujUZZl2e/nOLOZEEpZlhBKVbVTJ5ZtbJSk2tqTJxsbjx3bupUQSXK5XnnlX/9asGDBgrvuuuGGqqozZ/buzcoyGvv0qa2tqjIYMjIsltmzCRGEmhqY28PvF4TMTEoJCQQISU2VZVmm9Ny5zEyXy25nGEUJBHw+k6mhgRCGuZhZLsuEqCrDqCrLShIUZxRFhqFUEAihVJJYVpKcTlHMzc3M7N//xhtPnhw7dtasG27YuHHv3qYmQnr2hGOpraUUfyGQ6EBBRyICpHz58gcfnDYtdO3l1TwIxKchjSRyTZfl+vpduxTF6y0rC5V1WB7tzKMlJQ6H3X7//Z9/Pm5c/Gq+bdvBg6WloihJspys84AgCNLe8PuNRqOR4/x+nrdYHI6tW53O06c3bjxy5OTJTZsMBperoCAjw2QaM4YQj6emhhCG6daNkO+/Lynp2pXjOnf2ep3OY8e6drXbDQZFEcVAgGU5zm53u1UVZuuMD1lmWb+f4whxOmWZYRRFkijlOErT0oYOvfHGhQsbGoYPnzJl+vR169avP3/eaBw5cvp0QVAUKNEIs4giSDTgOGIkIh55ZM6c0aPDrYXBps2XaNRqOmR+R7Ld0Lrp8Dcsj3z/9VXzb7757ruKiltuefzxDz5IXJ8jHZnWlkzS2vYHaeuoqqqqKsMwDMOkpvJ8Y2NurtO5alVx8Rtv3HCDqhYXv/RSTk4gcPy41Wo2BwL19QyTmlpZabP16+dymUzl5S4Xx1244HTK8rlzJhMhBoMsi6KiyLKiEOL3K0ogEG7rkE0OW9f+He79RqPVKkmCQKnBcOxYbW1W1sCBt91WXj5//iuvmEwFBaNGEbJu3WefHTpE6fDhU6eKoiSZTJD80tI9jbRVMIKORETPnl26pKeHW3v2bGWlwxFJO9FG0yF9Beqmx7bn8au5y/Xpp3/4AySxHDp0+nR19ZQpjzwS37ynCIIgHRtZlmVZdjgcDodjw4Y5cwhhmPx8QszmtLRTp86f5/muXVNSFMVkCgQcjsxMSaquJkRRPB6Ph5AePXheUUSR5wMBQZAklhVFSSIkEJBlhvF4ZDk4q6ce+xoIeL1du7700t//XlR06pSi9Ow5fPiNN951V3a23b59+xdffPjhNdcQ0qfPmDEGg6KcP0+pogQC8Gw1EMCSikgsoKAjEQHTG/3kJ8OHFxSEroUa6pG3BpoOAzTfemv69G3bsrNtNr1LUMWj5jD4taFh/fqHHoIlvXv//OevvnrmzIULjY369y+CtFYwdo7ohapSyjCEUGo02u1ms8fjdO7Z8/nnhKSl3X67qopit26y7HZXV/fsmZqqKJKkKBaLILAsz3McpVlZhChKWhrDEOL1Koosi6IoUhoISBLDCAJIP8vKsqJwnCxzHNRcURRKVVVVKaVUUQiRJJstEHA4FEVV/X4YP6QoisKyHk96enl5XV1tbU7Oa6+9/HJp6dmzp0516mQw9O0bCMhyfn52dnl5WVl5+bff7tmzbVtWVpcuP/tZXV3Pnvn5hKhqICCKlFoshLAsHDNsu6V7HmmLUElav57ntYtuuOHDD++668svy8oup2JIxwSEFXLQZ80aP37AgLNnL1xobIR66mvWbN9eXBxby/Pnjx3L808+OWOGz2e11tb+5z/x763bLYo8/8ADmzePGbN6dXFxr17RHqm2Ls2IEffe+/bb0d6EIAiCIFpgMKggMAxkZhPC84oiCIHA8eOrVn366YoVf/7z2LG9e6uq3Z6WxvN+v9/v9aqqoogix0Gdc0WRJEkiRBAolWVRpFSWAwFFgemHZFmWGebicvisoqiqKKoqIZKkKCD+kmQ0Ohwcx7KyLElpaVOmjB37wgs9ew4fPmCA1ZqT4/MZjZmZsuzzybIofvrp119XV4siy86cmZ6ekTF6dGMjz/fsSQjPl5YSwrIQLW9qolSWg0fXtlDVi7cVSDKZNKl795KSL7647bZ33tEuR0FHWozhw/v2zcnZvPmFF26/PT09JcVsLi5ev/7GG/PyOC5W3ddXzd94Y8OGAwcWLFi69LPPWrq3EARB2jaUQmWUUGRZUbKyCJHl2to9e156acyYiRNzc9eu/ec/n36aEJ/P6bTZOE5VzeaMjNRUVfV46uoURRT9fkJkWRAEgWHKysxms9lsbmhoaGhogKrkZrMkjRixe/e+fUeO/OEPixe//bbXK8uEXHnlwIFpaTk5PXv26tXQ4POJoiCoKqVud1WV11tUtGfP2bOEZGcPGZKR0b//6NFuN8d17SqKXq/XSynPX2pN7QMU9JYinKBjigvSAoSq+YIFS5du3FhcfOhQz54vvzxlSkVFQUFamtMZeZuo5giCIG0RVbXb/f7a2kAgJyctbcaMN97YvdvprKkpLLzvvtOnL1w4cmTjRkJqa/fvp9RqleXu3VNTrdbMzLQ0m81mM5kMBp5PSXE6s7KysrKyJEmSJMnv9/v9/u+/Lytbv/7UqeJipxNuEAgxmQgpKfn++6ysnByL5YorKOX5jAyPx+9XVadTUYxGk2natLw8v9/vV5SGBllmGIaRJKeTEJZFhUWSBQo6klTCqfkbb2zYcPAgIYTk5EDW+Pvv33rrpk02m8EQfiQ+gGqOIAjSdjEaHY7MTEVhGLfb5ZKkvXtVlWF8vgsXZLlzZ0L69p02jWV79Jg1i+NkmefPnbNaa2ouXGBZSllWVSUJSh8S0tBACAg6x3EcxwUCqakFBYSMGkVpUNABjisrq6pSVY4jRBB4nhBKOY4Qk0mSAgGn0+fjOEr9foj6SxKlPA+1Xlq6t5COAgo6kkCeffbuuydMgKGlFovRyPPdu2dnp6ZarSYTz/9QzYPAgE4Q7r//ffLkXbvCaXq0ag63B7NmXXfdgAF+vyBI0syZY8f261dY2Lt3dvaaNUVFxcWo5giCIMlEEIxGqBTOMITIcl4eIZJkNLIsIW63LLOszyfLZrPDARnmhMhyRkYgIAiCAHnpiiLLnToF25NlWQ4EKKWUEIPh/HlKCVEUhoFhqqqqKJIky2lphFAqCCxLCMTXAwFFUdX09KDuB4e0qioMLkWQZIKCjiQEUPNHHpk795prQtf+/e8ffLBnT6iaa9EKd6imR6vmIOWrV//lL7feql0uSbKsKFA8EW4YWrrnEARBOhYX9Re02OOBV1hKqaoyDCGSpB18KYpQzVxVCeE4SjnuYn0t7jJmA8oN7bEspYQEy/sqCiE8T4iq8jwhDCMIwUg7VF9RVUxrQVoCFHQkIUC6SLi1ohisEPtjhGo6REVeeOGbb4YOjTyhBWZCDV3OcSzLMB9/vHPnyZONjW6339/SPYcgCNI+wWGICBI5KOhIQmhsdLn0k12tiHfpkpLi9S5btnfvoEF6tW8yGY0cfhcQBEEQBGkV4HAHJCHAUMvQ5Y2NLpfP99xzq1bt3h1tm6Dpsal581XMYRqmlu4zBEEQBEEQQjCCjiSILVsOHCgt7dXrjjv++U9IL4GYOuSdJz+ZBCZUgr+16TewP7C3Ld1nCIIgCIIghKCgIwnl7NnKSodDK8ctS+vZEwRBEARBkHBgiguCIAiCIAiCtCJQ0BEEQRAEQRCkFYGCjiAIgiAIgiCtCBR0BEEQBEEQBGlFoKAjCIIgCIIgSCsCq7ggCNLGaGp6+OG33mr+Pdu2nTuXl1da6nCkpCxbtnfv4MGlpU1NKSnxtBlKauqSJfPna5f06JGa6nLNmzd48MmTN9/cr19JSUFBWprTCWtLShwOu72o6Ny5Ll0cDr/faFy8eMeOESMi36vQLWoZP7579wsXYLvjx+fnX7ig3Tpw8GBVVVZWUdG5c3l5hw5VV2dmrlt36lRBQSRbh/0vLPzXv2bN0mufI0HbnxMm5OdXVGj3Z926kycLCuAo4Iji2VYoaWlGoygeOnT33atXp6ebTIIAyxsb/X6jsbDwzTdnz3Y4BMFg0LdPwn0qtms1kq3Dkc6bN2TIiRNw/Wh7G4BvFvT5ihVHjvTrF+1RwBU4fvx7782cGcneFhX9/Ocffzx0aE5OXV3kRxH5+UpEf0Z7xpPT88n8/ur770AivoOhQGvw77P2X5XY9jl+UNARBGmHBH/e8vMJ+eUvhww5ceLf/z58uH//xYu/+mrkyOb/KY+NwsLs7Pr6detmzfrsM+1PiBbQZa00Ny/okQA/XStW3HTT1q2hP+qhgOhodSfyH07Y84ULr7rqyBG47dG3D0NZvHjcuH37Hnhg1KjDh8PtD6yF1/hvBkKBG4PQcwpLYG0kwtSagat3xYoZM7ZuDb2p0wLXGLzOmzd48IkTCxdu3jx2bOS3RnDtwc1kUVFZWZcu4d4J7wlV8+ZpW+crmT2f/O+vXiTnnEJrt9zSr19JCbz+4hfr10+c2FKajoKOIEibR6tl2hg2RKTgn13Q9LQ0k0kQ5s375JOJEyNvMxIWLrzqqsOHtT8hf/nLV1+NHKn9IQTh6NEjLc3lgh+V+I89VM0hQgnb1f60gAqkpRmNglBYmJNTV3fzzX37Rr8P8AO/YsXhw/37J+JWR0uoms+cuXr11KkgdnBEhYXZ2XV1evVnKCBD8DfEIOFv0B1Ym0zhC3dlxhOzXLZs8uSdO7WCCDe02qdP0NuLF1977bffwvUG6gyfjTwiDixcOGrUkSPNCzq8J9r+ifZ8JaI/I6clej5531+9SMR3UHs2IcwBPaP9N2fx4muv3bevpQQdc9ARBGlXwE8aRKbh0af2H3SIi4C+67tdaFm7JDRGBToCPyQ337xmzZQp8WwRjiI05ePmm9esmTo19EcFIm2wD7Bv0f60w0N2uAmBHzN9+zAUeOgcbi0ckV79GQqIkTaCC9vSqgCshXcmujcSAVxF2mNcu/bkyYKChQs3bx4zRpsYBr0N/QxXgrYHIv9OwVUK1y3csoa+B5bDe7Tf3+ZpW+cr+T2f/O9v/CTnnMKNSujzzOafaSQaFHQEQdot8M9uqCiPH//jqSDxA+kZiVOB0KOAI01cVGzZsj17gj0JTycg8pSIbQGQD6pdAk8MkiNY2rhdcOuHD/fvD6/Nv7OtEPrkYdmyvXuHDGn+UytWHD58abQy8icYkN0Lf4eLkWuXa9/fPG3rfCW/55P//Y2fZJ5T+BdbuyTym8NEgIKOIEg7J/QHPhK9gwfc4V5D36+NbAHwqHT79jvvXLfu0KFf/3rNGoha6SWXoTH7yFUmNiD6DnG+RMfhoOXQY4TtQq5/aE9GcqYiAcRFqz5w1HDzA6+wBNbCO1u/7oQSOm4hkpxmGGTcfDvh0N4ww6e05xH+huXw/CSSbOm2eL6S3/PJ/P7GT6LPaei/FdrkFrj2IkmGTBwo6AiCtHNCI8qJeHAJD6D//vc9ey4XA4MtPvHEtdd++61W2fWNBEdSxyDyW45wwEBb+DsRcTjIjIe+giWQVa9Nd9Fqerg0idBbpmj24YeD0kJvfrRLtIPV9OqH1kw8T2ngs5BpDUu0sU/t39DDkWyr45yv+J+PJfr7qxcte04v3sAcPtxS/YOCjiBIOweGjUb7KRhCFO413Kcgi3HIkDffnD0bZB1iPKG51BcrKlyuPklsJOeHBLJjQbDgZwyGr+nVfmhUD6pVQG59qKZ//PHs2Z99FpqJG5oeEzlaTYQthub0wxLt/rSGxIm2wooVR44EBR0GcMONFvwNyyOvNILnK3IS/f3Vi0Sf09B/1a+77t13b75ZG5WHJ3gt9ZwBBR1BkHZOaEwlnthqJGgHqsJD0vHj33135szQ7YamcEQOxJWbP1ItkdxgRA7IE/w0glTFdiMUSmhZPXj0f3Go3KWaDrz00vXX79wJf8Pa0CzVSAgdlAYSE+7JgzbC13oGIEZO6FUU7omEltD6P9F+p+Bsaj8FN1rwN+hj83MXAG33fLVUzwOJ+/7GT0udU7gmFy7ctGnsWO1yeM6Q/H5AQUcQpN2iLZ6lXZ7oXO1QQDXmzVu/Xr+MxtBsVDjSZMbRtRKcuDiTVlzgRxTq84QqDhBPtfv4o6qhLYQONWtexUIlLNyRxs+hQ9XVl7YciY7MmzdkiB7PK8J9E+MZGBotLRVHb9meT+b3N1pa2zkNN69FokFBRxCkXRGck2/w4JMni4ruvPPjj7X/vEK0KRFVq2G+Q6gDEKpf2pkCtcu1j1OjBWJgWnWDtBk4auiB0KiYvvHC0Dhc/G1qs5MBeAQfeiyhtyiwJzCDbLTbDR2UBkDCUrhkJ1irfX/oYLVQ3Qx3RHDlhKpS6JHqhfYMwhJ4qgNXsnYP4W+YUie0uGdszyvgm6i9gYFvaPP10RN9vpJDy/Z86D7o9f2Nh5Y9p9DPy5ZdfBYHJO72uHlwoiIEQdo8kQxzhH9kI49hR9KmNl1EO0NnuJkvtVysUPFjhdXCARFiSPkA4YOfWNB0bcpH4oB9AEWI5KgjAeLfMP2QtlcPH7777tWrod/CxbS0Wem///2mTWPHRn4zFjooDa6Z5hMtYC28E/YzdHZD0CCYHEo70QwcUfN7BcIa/4yzze8/XEXa+Sy187OG+6y20kU8gxebn3w++ecrEf3cOns+Ed/fcETyLyp8Z5NzTiMfHN9Ss65iBB1BkHYI/GMNsViYrhkm5UlcjXD4aYGIeLisUIh4wV5BVnrk03SHA44IJjeBWTah/XAVfGE57CfMdRoaf4oW0Ee9agbDEcH5gl7V9qf2xxuOAs5vuKz0yKdxuVzF5YsDGZsn9J3a1i7eSk2Zor1OQvcZlsBaeGciJmAKBa5DuCbhqgh3DcM3CwZAQ6JR/NdwbCTufCWT1tDz+n5/46H1nFP4DsKw0ZaaSZRK0vr1PK9ddMMNH354111ffllW1hI7hCAIgiAIgiAdgUmTuncvKfnii9tue+cd7XKMoCMIgiAIgiBIKwIFHUEQBEEQBEFaESjoCIIgCIIgCNKKQEFHEARBEARBkFYECjqCIAiCIAiCtCJQ0BEEQRAEQRCkFYGCjiAIgiAIgiCtCBR0BEEQBEEQBGlFoKAjCIIgCIIgSCsCBR1BEARBEARBWhEo6AiCIAiCIAjSiuBCF/30p336HD8+aVL37mfPtvTuIQiCIAiCIEj7JD3daPT5QpdTSVq/nudbevcQBEEQBEEQBCEEU1wQBEEQBEEQpFWBgo4gCIIgCIIgrYj/B6WcjiTomrJxAAAAJXRFWHRkYXRlOmNyZWF0ZQAyMDEyLTA3LTExVDE1OjA0OjE2LTA3OjAwWuZbyQAAACV0RVh0ZGF0ZTptb2RpZnkAMjAxMi0wNy0xMVQxNTowNDoxNi0wNzowMCu743UAAAAgdEVYdHBkZjpIaVJlc0JvdW5kaW5nQm94ADQ5NngxNTUrMCswL/j8PwAAABR0RVh0cGRmOlZlcnNpb24AUERGLTEuNCAcRzp4AAAAAElFTkSuQmCC" alt="VLSIDA"></a><a href="https://vlsida.github.io/OpenRAM"><img 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Am9buaRvKQTKBcsdGxwFPe+gbZ0Cmdi7yP44ZtCwFTyHK3LEFfjvJI++83IPb8YlgLlqh4aQQsCgz+sHuliDh4as/OOfodR0XkhLK03KRec8SPkQhiYE2Whnx5IhIGBf6dPnHguOvR85HoG/j5103f7pwfo5icO6lXHol/d3ffOfuk4SEFS1tq39/WEZHDYCZj72ISt85KPEX9kUS6Z8isC7vlq0prjbulQfzQ49cExuzsGmrdlCOE/S0vEBQq2QtYH+cqoAIDSc364MZ9YPxReyOFInB28sXfG4xO2xoQKLPB1kk23xTsKKD+3eeDfNw/kMdXliDUx5+PDy8XXW6+VV/t9k9EV0SR00+iYk/+buzo6tFwtXfSzJjP6zi8nl1S12nevTQFdoWTudkm0AkfBlENG4w/EnrVvtVVCiYCSwCgamID2Av3OdCPG5fAzEDVw2WA0ZEjcOOnfpsGx5O8XpCawiCHB6SsPKqCM+5Rb0Ak2u7DhXvJ3/mO0yuQXA09fb/kIoSFEP3/hID2IRN3yEVFF2O+sQ0hoqsslxAnlJasRYUecD7OPchEJvApBat9D6z5L9geepmkoFB8as+vOAfi7lC/UlFoQ8duVo9dnRbmentGxJ0dE5bPDpQdMRWLBwQuIXSshhAkFO4GLCCoISkI6/Ula0hUVJu56At3/lCl9bMK2Hw85oHySfP0PFLWHIMY0vjo5E9ObBXjzic7FzmGrY2DlPYMP3Dtsn0Fr4DZE20fgvjvDuKXP4eemblQidO4OyD6/dQB0+fcGpN/ZPz3c3yyEB4uXH4v94+oReF/c6Vadw3cGk+KHg1P5C0foHDjGSaM+5Z+PrR327x39jA5nJ2U+OXlrt/AyHp/ff1FFwHNbBqGp5YRg32oAfUZiFvsSdf6O3E7f+XJaTpnzBFPuD1Q/s+0AHeocHQgUB9JsbFKsWsAUjjv5qvNci9bPA+CWZGon94nlK4AYI/m8wErXjZNhM5AkAp0d+0i4EKQ2akJuLcBdL9nBsP0xtBU6CxCrudE3cMquMw7Kpt38Mlzf1vZT7k5X9CN3McmaRNSSIusl0N9LhJXqnzwR1BMLiTN5pW3Xl/O/cYc+OGbXhLhcfgPMHLvXN/b2xA2FFeb+Y8eGlvftdLpLSAWmXJ+Op9FNW1OzvA+cZoShgzsf7k8uqXIUzev+za68M0P9zgFhd/Q7aOAUxvh9y8YQMdQtovxcrSm7LKTRPA1RIRVf3LS4ZwfC6+T3RXQSOtTfrbRwmC5ndVZS1suzV7ezRDBxr4dXj3hnX8/7R+3+2dD9hjNTqJj8DmArbJvL/s77EBIPQL+p9xFF3fDFwwLoFGTeL8LUP7NpEJBtXINH4dHx2xLRt+jUSl550D+3DHzFsjLd1Pvw01O2GNvN3PLgO76YCqy7Px7XZ7YRoGNuow3HNlehNACc4J2mtUsSdkI5RSX34VlzPI7xEJASmNuQHpAbAB96FRJpAdA0Ak1plafEGGeFwL9KAwPgSfa8IZANmHr5Cd0Bt1NdqTEGMbT1JiB74Zv12nD+OgHJwyOwPwiJFtwnAWSHZHkusei9zY924cfbFnecnZT1r5nrlJMT2MXCwnBTYommDifMv/rq5GMPjNzdNbzcx1RnzcDQFUQBsR4ErCOGaWrPnvOBvN+M3KvbsLLulp7zfWVnv79uGAJfDDuB1sidX9hrc1bf0PuoYjOgqVHL3DJ/RuHZxlNe4ztZctvC9gFV6p0C6D/7ZgKKppmJWY9O2A4iKyzmNSFbxN367ObBRBq7+dbY2/1yeAqWvrLKAXTYORBZUeF8bd7Y04sACMPX+qzOPin3LJ9uzOrChtLYE+AK+vC6Zf07FamhQv58fTj+J4snsCNxczyuT2sjQMdqPrJCZII21i6wDjcdFi3IC6BDbkBkt+8uByFGyHmChY5xLUIXk5AS+BvRjAN5ADL0NN0CeSA4xwk6BRZBeY4DhQ0mNhPijpXt6Bx5Cbptp2x56Yl1yEtflowlwbjQUQ+u34bNp6pzdRcWIZP+yv1DZZ/RbVKTerpET0b5+/LsNYMjC5X2/FRlwP929fr7loHwJM17IgIXZyaeIIpveFQ+6TWM37l6eVklIY+sGz4/LbF5nV/JV42MPomwb3zXXPOGtl47dDriT2tGQB+7Py0Pjt6FswR7X3VSWBH42LqhkO+N9kAKl3fmrYDbUWcWnfV/aOVoQn7g9J+YuAXBiWJL+BTYXXM86pE1w/fkuwrct7njH8dtv3dYivIQ8BFrDJkA/PR4CBae/YXtiRI6qisXofXeunoFUUUWvMY/3P3HixqEHiS0+ef0jTf3OWzsZlD+4BD6YH9yo4/pzgltB+hkZSEDIhCsPJC2g7WgIROjDHAzIuNnUL8+jisUxbWg46wBsrZduflvXX2o7sIdIcTFganCgnSHLUJJ9gSyivjoTHq1/AW+CJoINXpFvr4D8JWDEkxEsQ5fGTnUPM/IGsPw6F8OmmRz4I7F4njgrGTtxEiPSNSih5oXGMdnXvJHIVUfGrsLnbJ6EpIi/XrpWCyaFj4Yu/uJ8TmzErOGReV3Ca4wIpWIQX9xe78nNzCrF1FD3x0VWkGiKwzPk2eCEGmUtyAnybf0YJDg3x1w8HejdgdZXhbk8l/WD4U2cdP29Peu+/7AtEfGbyPaSA0SAclLO/rSSaNjvqVPxpOTNnfUYxRAh4xT4T9aPFHxGFO65dDnoEhC9swmV05Z8He/nILItdFujRMQ4fx+zE7EVOpI0dkA0JyFR/0Tl+bfNgx6aafQ6ERCvDBjQ2yY2e3J+rEgPeH7X022vtd3+h18Zupm+HR1EJP/td19/rDKlZPf/aG2EaAjJoFvwdNokB5A53lGtPuP0NQz9ZUAwMUBCygDvvKi6wWvIeUZEsMAo0l5iC1Mwl7O9AsT9gMoR5kONHP9eZWVdFZHqmHwCQheIVGv/EVpWsg+hgSeflgDSDwQHiv7jIL98qeGB1VfG+pr9JEwDsPMd/lQsoB5Sf8EsiJwvHzLMD05acuPhxgJOggHjbhr4dRDp5osO3M4m/w+x8flYsGRDE/NfFWNF2To01YSNIcXXsiDINH3BqRN7ZbNaAlOyTsThM3LkpZaaOszx/07IuokGcnLzvmCVo1y1q3+FCNjTr4xd1V0yBllnEIuI9B+fXcvdOju3Aun91NTICsOguz6D1LLPxP09KZBLAmuL2eb9YOBaY9P3GJRs5gOnw675fMZGTp1Bs/26+F7fjo0RX3KEVJ0vZPSEzqI5G6uezY+vbP/wccmbkO2yBFiWeGCsNYHdD5lFkTWeaUUtsfXSkaah0bvuqF3BnCvnrmqVhEy53kCgv1qlt/+Ze+OxUpkea7W+72U5F8vG+vmYFyf1haADisCgX5ylw5hur1J4hSAD3kJChAOCsjqH0lziHF85Og44Gu2fNXlxjk6iAs/oxPo4DIWLoGgcPQsLZJuJVBDWwIyCplTL3Y3HL3Y2ozCra+j61m2/RTEF6lMjRDlLGmsIowB0Ccvo8hj9NP5FHGkA0Pe8uwMj2IgyNtZeC7TRsqnW/oeVvoWCPT39ve4d8m41n3Wr2/52mqD7IU0wnqD3Lr3alJvCRFlcAXX9TjCXwxNBbs8yF/y/BHIvjozxrrD347aTYxV5+BKomd/v2rEohbvY5o0Wk6Gqn7v2hUkF9QvNCFYfGjVqA/2u+t+5C2v/97nOEUVzPG6vzocj8Tw4KnGVA+a9sSkreSEMEx7ghIeWD7m68PmwDGG9Pa8lX06nlI/ZRSrTOCDq0Zvy3HLSAed6R8OHbaEB2OhYslnVXh43E6IF9WnDty9vzzU7dHx24mDU+jEbze3PAg2f9X5b6pnh+K/Td48OT5HrQfi/t3TmxQCTZ1wh+e3BaAjLyG5CvhFQ+yB4JoMiPDgHAdhOU46LQQt4JoYwkgAIcEtKkAQGcuaqzCEsWr5FFwD+8BH/oIRDecuHLqPoLMqKYfFzVXyUbD8iWSQZCnW2hgWGOaePum5DRuPQFobKBpGwt8RMrKJEbrGEi4sjA0Pi05GPwIphAOZeiAcvEzbf69ac0OvDENd8L/dfR5qpZ2pmjDsLPKNzEw8ruTPfAt2new4+d1r2nw6EVHcPTD1R0MO4HyzNyjwpAF29y0bawRejok9+Z9ZayFn+I7wu0GCef/yMfvyba34b/W5wKl/Tt8wJsZMHwPoT24c+spOt3SHDGxG4olXZ6+iPoYaJHzL0xsHvbBtgDtjhnl/dPxWEjyok4+Xhvzim/GGhp3vD65RBE4KkTmHjc5f1g11M+y+f+dTuOUHdS5U2A1D8q/tpIVJ/u9VqwZH4tuUmyJCxwf7+LqheETZTqlvLB+kFHT48dcTINmtnwIRLUJ1BJ1KQcsijR/+10vHrM1yS3TvekLaAtBxbALoQDYN2CVfCio9F434SRXUg16b3xwoLzRFvfg/4UmI6AEEMfCZb6R+Ug7UWAng1HSB4KXYcDCQWAZ2XlnsbD6EsYmTlYyp45+wQPAt7DYu0wbIvj1vxZzumcp9RMKWpzcNeWGr83RpzZoHGM87+h0ykjoRXjjzg6thLZrUGZXPIEYRR1bXeYMmpIKih9XHY46XOMmn77J30PmnQ/aPic3tEOQAzdWlsAq/WzGGQjzqnza0LOKKP64e+fa+Hm7y1y6H4+6HOB55X+O75ujAajpb44WeBL+om9e/cfWqa5KPGrkJcYDPeH+um/TaW1evRCxowUftUFH4tZ/Oto4ypS4dyVX66YllGA+5yBcdiv/+V5PciTBC5A4Lr6KKuJa6HP+3rR/JgZ+btokIUnVTzHZSCf1w0SRSIOAJMPtLNW1bTqffrhiz+6StA5bKSvwXgSxHnx0WCUSWRJwSwOzmdDk7rS0AHfzd9h9z4lmsS4J9Ejxh7nYviCAjUj8WpTWwLjD7va6VHQY+VRVVC6xfvg2PJaHSPdqXKHsnrzzwewunET/duk9MAMiXNy9Gmqa6LagIgKZfn9XFzbswtrsGpP10KHn1ypBCchVgIcZGrffBovCXd/Xld+4w5N1Z/yhw/jYZWr/YUEGAQPC2RDmCmEZ6EPyif1g96q29ZgUI6QDn37CEbCqqW4TSiDs/O5BImCIMw4VplCVCEnp7v0Nq5CwquDTdBHRcjvBFhrgbXyJh+rctmHbKDc1iuH/V89M3XNvzmPqe8LBkR2H7Yp2vkeADtOHTE08Y5yBKuX3BVHtXhM1c8cUAtX81fG8IRSr0z2De0d78d3efX43Y9+Bos6dUiSwfXDn6l8P3kqpMoTwzT/93fTkZwY9Nt0O6kB5g29iueZZcBdrGE1HsPpHJt/BltQWg4yTc+47ZQseCJkSo/x1icnqazQyQLpgwV6H19QZXnjRbKntcGY2QELI7qdBBQAntOZ6u5tm8LiaMTF4oI6/qnql+6njwlh/tevN8u3BiR110b1/6hzHbJ8Xn6gpoW+AElQDWtcej8GEidUD14agP22Nf3bxoTNc8azRHvYdAfuGh+N+P2TU0Kl+xQ8AlhW+ALXV9306n8DcMilS0AIE8QXctnIJh6CL8inCbxHZlnYNYA7xOngnc6bL+ju0oHf0b7dB9I/bcNTBNeTUxWvF5uJMh9q6B6chj9Nxeag5Npyv9WAk+Tk1yZ9L8ferwbLOsWuxi04asLggBif41hokTAly21pawdyENAFUvWCkdPY35GCslF7JhChAC3VRbr2WVhv5u5ailR7pe2/MoSbiMMFQ6ZPGGnyF9jXoQ1vUtOZH3Lh1HhSObW+DqQJZDkiKDdTlQGHH7gmlK++hiPI1+1BaATtbv/e9rVIaTRmmIflJKwlOgx/5dwbpQQYlQKb4aEEoBuoWOt/bKaERnkABdacWYgPRTET/4ajJ5V1r96V+es/bGnhkW8aLEs0x5t/FUl1TboITN4C4NuZbUwIRusBoisA5j+9KOPi82RgeT4uqpyZunJ2YpQFR9QN28m9Lz75sGFJ4NhO4ngbBaeOgWtydBhuo08rXeP2ovxIL6FICmqueL26Cn7Bl4uYJ9wMS4bDKYk+KVRFNwFMuPxlDxsiU1feiWBAAkAVd6bUa4OjPqxs9muVa5kIDlw+uXD+1SYLH+KO2NAAAgAElEQVSdTTgGyIVJ1ir3S0jzPbmzf5rSseCf/EhPNc6aZ/NVWXnHl0OiCo1lo7zaZ0Fawh/XjHCRxge8hnJBPhsbpq83Jo1NA8lbiPUfHp3/5tyVMXJcmlK4s6E09kn4dRceSnhiw1BSB9uMhH++MGM9VbMNySzn/ODryfbkjP2Fro+0BaDDGGChUxNZEeJEe1JFyNPsZ4CwWABdlf7gUzj0gd9zms7X/vJL/Mg9g1LxZRkhIRiqd7udrcn9R48LK3984lbiUXUTTNJ54926+3zhsH1vECw/GZJyt4Ut5QS+yyAIzK+fVy1SOevSOUA8KLDhBKZ6HI5KKiPbd8iRnw5JIcOUddJtMOKrQ3F/WjPqWEkIBP3H1y+zlmqsOR5z3SczBWM0jRx+AERfi5ADigZ5ycNrRjpU5k1LyL6t76FZiccDfcnSLR1QOofkrp8cSHpjb68m5TmxeZDHJ27DmDU0OSdKQ6BN9jqnEVhUHp2wo3/nIiPJLZ4S2GQCLx1OkbODb81bSVUTFbrJpmR+eiL1iexPxncKJUJuH0O5plQoJIO0P9k48pMhqb8dtVMXuUtjwXgTUcrKUQSm/d/Mdfg21VIE65J+Kpw/CVslGRzzSpoKNgEOdfSinJm4hfQ1xlYMRvGOL6Y1SR3vcMxtAehQLgc+1Su96Q1HH5SLO9VBHT6Bi4MiDVQxnCyutaIhOVso7DPx9MgW7cUhSjAuKppAyfvILwWlo03DASCKGm8Rpztr1EelQCinkd0XhoT6SnyDmrEFIeU6pTnQ6qjGgAkQjZ/k7LaX2XHqFVC1wMIam/LPBDy4alSrh3GSv+nB0bujQ8pFH1KvSZDIxsEv73RQAiXMv6p9wDnsL37APxx0YFzXXBXJoqa9rMqXTFILDiYgnvvTuO2jY/ONhHz6CSZSmrAmPb15MPwJOdntX9ZLs9fe2EskzOoj7LtN2V1QiSCG4wiLB/YvIKI+ZeEhtvAXFhFnj/bFf520dVoCNdLkc1YC0g2irrN3KtLDjwenEimjJHfGfoK/IMX76nA3nt11+WP7kRtHUJE/PXlzsCVvOIwToj1nxTMpuUmecRYqg9eGdN59shNrAPlPXNzF5iOk99RL0ncn8okub03+1dLx9s4Dvkt/m7Lljr4HjZhPeKGXd/bjjfMXh3dEM875j0zYbkS38VBM7L+3SxgRYpWfD0sxHBuwLizqYTy+zr9RnPrpjQP1/GIO9kl/Jvp0RArLv7pv/pnA6z+dSdZfh8Nw/2ArAbo5qWy1QCEAbY+V1iPC3UfFCbQuqiE0hHLp5K68SQ/g1KN7oN35Dw0M8f0gLIIZkFRE5SFauwQ5jeyM0DsqjyOArrICIHoB0PHEkjfGaFjBJOYFQMmfLnGe+rYMcTrhRe26azUVWnm+OY5U2ctoS6iBZ12Ig8WATAYlJyTLGEIUJkR+K2hsAkQiKf0kSrItHtZ9bwFqlt1viHJRNXpDeM5c2S8z7r/wS+dMojkenbBNpTECajH0SHnRqBerSc9HtN7Ph+0nD4khaMNC/POa4e+l9LSpVUbOAMQwpIKJDD5Lmg7ZKVslxYbqxa7/5ZLxXEVXUxOyb+qVQbpH3RiU37ZqYM3KzJi/bRhChQ2bcUJ/I/NI0HWHNMxAvGT/2dFnqV6Fg0IN/565fnpCliECQcLxiyXjDdMSTIR2QF+Bqctc8cVj5aNAD2IY40b492A2ru91lKWIPFaEe9jBjKnsnM/7+5MXpCduPBFpM0J3/klU0Ve3LKbgn6I14IsQ27xp8dxa94DGEQapdwcSpTUcZh9DJJHD1dTF3e8dnvKzISlRenkNGu+CHniJDi/p1+kU90WZru7LO1yVGQ3r4mzbRCfMGJrIuHChXNjOsEb+/Jvx+Gz5CDaGjZFRhwhyiVfMd0ONBMf44+uHvr23p8P6qHyXWMKtNqABuIhI9O9w2O4fbBagAzRgH7CFWa0mhkSJpCkXHWGgCAeDOmohUZI0EfiT/xCV1wtXgNkbEilwvOdtyXGofCBgcdKshtIQLsbOGgBonikUjAaXuRADHAimQ/5J1CWoSjAOWM+9+FOqFFlSJ1p3C8hSYNq6XmjOVqlWoZSU1mfydHQrum/9Zyl/6H8BlHlAeqD6Mw9LZl2yqBeiSLFoxm2egn7IToPWniKoHXprMY6/bTYXyT8PfS1lj1Q8Lc8bPUJK6Fn/CBxcc5kcGhpVQDwIFhzPg84XQ+/OL6e0+rOR/e6pKVs7BMg2nFdL2bPH1w1jp2xzIwx5DGT7ImQMLON06CcHun99KM5absyZuLxQboAdhj1I/1Q6/c3yMTYFbrjXc9M2fKffIXUmp4Ev9y4ZrxyV1OvA8kUsz49fvXnM89d29SZsx3qQkAk/H5oSGYLSsR5Qg4b++TcNKUQ4E/7992N3do8oMXhbNbGkIjofVf0/TE1+bXfvZiQpI4faJ9cvtfhmMVH9/7J++Bt7bJOxUDXw2SmbWPYMtSjWNCYqVMkja0e4cOTav30iae8bsRvew1jqyI6AwsdZQBPWNO+Rlc881eRarfJ/d18PMN2+c3UEmuuj65bh4VCzdLQ49BdLJigdFGIVcshAr6szYbrQOFkZB75PbRysezIcNIQ3ZJc08s8Q2YsrHl7OwalNOdQsQAfND34l2W4BTfK+gqoS8EK6EtCTxcmStIRxyBFMAWGUBHMhOsh1zvkI8gz05DiyRaPWj7PRw5akfyl2vQq0kd+fmCL66RaQbYBv3X53Bq/CXUyWaCajUaqU3DJGHgJnY7A+zgDgUigkTaJzpkLIbhUj5/JirmIB6DHPSZk9u2vZNzBXsiPRVxFsfCpol2VJQClJdxEIXb4NXvvFGevUN54fPDYRCvFWf1y0NGjmVEIovlAozAz7y/peD4zaA/9j/FaNj4h/eWTtsI9Tu9tbYRS8H9i5iHI8JBgIoHie2fT2fnNPT5ussJ2DK96/ZjkLmJk0qPdad7wLBfaYgdndj7MksDzoBLH+PafqZnnQn9aMBLKNYbCPub3voT+N36G2/0wXhTvuWDDdGBVMDiMh+xW8ucUmNlXVSjpZxhkfVmYAImYm2Pq3jUM+S0tqatIYNCHsM3p3MMu9YfDZVNnk3uF2eAt+Nmy/QWJAU0DyoNhphsd7TGweWxNYeDMQ1Ju25HRmLTzoPD8EpvEfx+3s2b5YbZ5AK0pXw7k7q2REopjnp683wlCPlYTd8OkMdTIY9O9Z67EJ9B2blnsmCL7FSOmOrxWtDmIkh19aVpTNd32GM0Z9ihtj4aG4O780e7kdXuLOwWYBOsGcoAywbgZQK1Rt5J5QyQFCy6jgT/mC6nVEB32/8ShNSlsQaGMuPdHIbSwfOxkYyAjDQ71Qo1EDj8pzEnqqN2WtWX4/DafZ/I3TYG8w9snNe/gbeSijye5BX8zsG2leWAZgThptLEh739ZOZTScSBRVh56SOZ19D4QPZA5joNYHHTaDo290AG16AsqNf89aqwI6dKgNH/76DZYlvHVGhsjspVlrKWKn0BbqmfS8eEQhxG1uQEL2d+Yth661Pg5uQnrO+mCui/gdYo5gS2E5DFHdidIgaigvOxqruiJDCL7Q2/sexJWqjvCwFMBEIQeI69WuG5qSQuIpxfJFymJ8wILEbuAPY3YZJSt1nfW0VL0oM41c8C9MX4871PDWshQtOxpDZnk0l38YuxO3qnILczJ3YfmEWbbJLmA1EMd/Rcf53jXLdKyUE9goUMrHujwbByE9KCg4MT5X0TIcwR/4o0XuFieyuTFaI0RKkuNe/63pFErMdZ/OdDw+/Wh78oj1P/SbEXuI61GnYdT/ZNEE2DCHV5FFEh264ds4dCps/NvXGbEFBDTdP3I3wZ+wXrV1XuEB5ww/56FTEezG0K067JaXu+z2L4d00QPm9ZZxOnz0m9e5o9R02KE62CxA51L00cCr2aS1NpP15IhikttxHYKSFlMa8oHQdhoI1WWQ0AiuaXduxO2EfNBtVaOJGe7oRuoEuGaSpRhJE63PbJ8sNZ1htFXLXC2US4PiO0zYIbh+qHBFwfNQEDX0IFnUjTHoKXypLkQRpcw1cjnPyJkQPh16CZlO3VHYGNm7NJhXcsOooVI4iUlw3XCH7nhV3wlZNZX+hZFwIxqgD/GVMFnYGPfZedf3vTg+hYD+6PplgyMLFDrgKMOwhapuxdGhc//1iH2GKgNc/peTbIto1AhHNOqaqjHAEVPc4D87+rkOOIR8/8WwfViv6ncCzbrsaFcIEzbv9DMzKeuh0TvBfWvgtn9GQBZXKpkJqBrx8YHkwgrb+GcM/JdnrUFioaYLzd/N86eBKaorZC3kjSL2R/2TMbB03fr5dLqVMSRm4YIeaikKyhF4D4iXpmbOoe7aW/NWQIMoeIWP+jg18VdLx1mDFOoaqmHgk1Aj4YexJTvyN8vHEqNr/9SNHiH6jIxgcDjm56r3YuPiUOJi3RURTNAdhmAcxwnVZf+xZaDD213T4+izUzdHBkv9OX7H+D+o7Gx4m8kYzPpEoi7sfTO86S9SJwnjONPFYv/3qRuh8oylgmpZ130628XewuHwbA42F9CxEEFY0mmRjhwLEShBLk0KwNAoLbybECMkZgGyOe7tI39iS/LqgEj+DxjF0JZsLToWt0+SDFOui8nh28zdpmVttIJvkwTa0C0fAdl8iyX3FsS6j7DVGMgwEnxK7eZz1IUokT9Rnhh5UfCI9rutIU/hsdXasVUNFA0xmcA0PZAUF5+kSp0Y3EW8r3m7tLydFg4Esr6LlEDK36vl7ZbLecbACK3ndeICBY45n3mgMBM2tcH/SHDseKGYGrWpWSF2vCyrhesm09tOQwAjjmW0t3p+m0sf3LEl371m5YzE48rkIYfRkiNxdy2cjK/J9Xy4+Skxop/dsARkUQjI1hsV9rT3rnaYpxDP28NjtxvuL27Bq4ZwBwjYU9vzLTZjeHUOSWmOGNYxvi824xtPSDyqKsIAUeti2OpesLHEXrqIOyWNAcAN6wKyINd5YVt/BVLg3X9mraP2kyWC0UR8FqyxQeVznPIUZDvB+2q2znTS5obPZjmTfzgcLRw6wTvzkomXEdONZSOzNAwjncwnxvnw19RQNpyB4N3/dvf664ZhNl5oh/3bH8Qt+fiEbew/1EesQxSf+2tjCZARIH1ywzLE+Ga7XjMRhXTjZzOJE7a/BUKXxbcs7N9ZCl2x/uGIJpHWET37OY06TU9M3AqPZHMhr+n3K0ciA7Xv0DjCVevu/BwrQc05oQa/XT4KR4KLSxr9qLmAjt0K0IDIoJ7DbH8qMRYAig0OIIIvOEsxV8F3xCdw1gagwyknz5UqFi4avYGYJzZqVSzFupkPdpMBJn6ywLQqxck6AYIzGPTaolRBA6P/8nHVcknRIS3jG3PudX7B5Fbsd2uDXISYTFYLM1VtkiUncZrjMs1pn0vyW8X8MIbIwZIq8uhy8QmrgSm8BrJVqi8e88gy8eWq1YtbB3UWvsWd+CAuSVugnWSp0Fc+rkUriS+acfIVkGnQp0I2N/Va54GaP07XTjKT6HwUSsnHl2pDlfHHsTtutJT+4jFw0/1syYRNzRJg2M/CtIQT/72KumXmnyLrBOE/f17rwDnWq0MxOj9IakNgR2+kbUkpaPfEuqGYuvadWx8BPlZ958uBkbo1oxMahH0S+cIPmH/iUnt33vKBkYWKQNdPkNfLC+RsToa6o+IPsaZwF8dKXOX6+OGg1IfH7bBUYiPlUyioDYX9qxF7kWaqBNx0nlMeQmgMhSNYI41x4p98ZuoWmB8jLIhVZ/r7bhCDVo+Kxua3o3cThoOzQX0Bsc3JoPv8tgFKicjarKed2WQ4igG+h1aOcqiEcT2r6lM8xq/PXUVZCfVPeiOA68kNg11fy1RQ1ZpklsYLJTYVEv9zOzBldSTA7bej9kSGVDBZeiBx7O0LphtTx/cTBy80js0dSfny/Jb+uCJcjIS8jE9P2TS4i3lDgy8BZ8zPvhnv4pJGP2ouoNMxKIMloCxB9+EDMAIQoeAFZ/UG89DzWpGLuG4Yy1QTlUzip3Q3LJXYugrsull4E8WL2lKIpax7JuG+1bVAZPoXsswYTlGGBAtECKuNncuClPqRVnzUzB1BrSTPEV0jop3TeBQUvHpLzqzEGeangTCBXi9MNX/KrdmRJM6UrYw7jYSLGcv0dYjOdX9D575mCb84olH76Cl/eRcsQlD57Bi6jhaD/dJvCATvG7nnnkFI8czaIVjjP68Z+WGqld60BY95fc8jhG7jwlJfXjyNty2YsSvPgRB4aFThY+O3woNbf82J/3xm4yBMMMVauBgIRQ9wFRox4liRZF1H/6AuQRMChT0j4YRF4EhkaSAmc6B3zdlaX7hsCjWwA0BW0WjhvQGRp56bugFtovJwskTBP6AERyw0N/mYZaPj9SmkxOKJ9gNGFvnijA2WQEcTDADgYuQstD/f4ZE/jduBpW/o5QEpdJDkCjdCnMiyANUQHYrDSX4vWPH4QslfOD89gb877NPFQUr/PDFha2SIuK/ojt0VBeHYyQG45N0Fr1ljWFCJ77eOsYJkIwDqoTEN5ThYCf66fghFZVk7rYeRGFFGLnX8E2r2+GjFsdib5lt+3Zo2IvokGyMjubkx1Koa7xe39yf9r4vBQ9c8NWWzEQ4GfqByYQ9KRVYXV7n+qAWAbnQssN6UN4G87xAiGUg0HQGxZJNmaDHuxYaxEiD8MJvS3qLLxhZGC9hoA4vT5jc4clkPYkYKatOIWUUdCDeiGuNhqQCU7TUkp49KSJRSs/DIAPqQH8n4saNzd5ofhzUA63vQ3Q0jQnR/cq+ZcuEqKg2RYBJlujuNUR1cKIyNatBKsSOFoWLfY1b4YMVVywoH74RTFxoH5aisQ015I+6MpC3OITfIb0fvMWq7IL5+YPnoRRnxrTKWP4/fjvBDsSh8g7dmd5rhREVDVSOMSiMmUN09rajduLeutY8vtx8bakKkcoZYEOYdktfQfuCNRD+jM0tyKXQ8m3rSKLIAFJyVLC7Ux3Ef6W7re5h6abF6li4eandeh/tXjP3J4BQIH1CeXyruVqLqEfbZjxPa5/W5q8EmM9TWe32e3o10C/ZnujhCoM0fxuw0lB6sXkTWPLy6oRwPYPrC9A039ckwokOhm1ML2pHhnWAoFz07/IhkCdYaRFblFce6jo/L4Umpv4wpEBNW4e9dU1HtC6bnlgGUJswCDG1vL41Mv13Dygx2iEyHMFSfpSeerfY2Fmle/XPTNpLy07J/MiFAumfRxLzyYDUe9iKwTDf1zrBRQLG0vLm3F7WqHQ5bHSRKmUgLOHo1Bsa8Lbcz5r9D5sdFP9YftQagu3kr4zTQTSx0s39GsKnbVIn0UY3HEo8fhIkjSLLmRjgffyCAjh6czLoumhSy2Cc8D05O1egfL2KPufIv4DL9c0tuGcicQC1+vHyK8WvTsnEFLxO/qGoY8r1v0PCvQqpkoXq0iNAhl9hzGOsBEnXcuYo2AWcj4rX+33U3qS9XUeH69DHzasF9WQkG39O4KMh26JfkvwkmfGjMLgXoLP4FZ4JIW/p+SrLrhEruPCqZpFB9TBEptNBZYMrSI+IkdHgtosD7RuwFqowdOoPBXp74zjUuCH38k2gu+3c6hayNbbUKHIXxwCC96qOrDIMRzufJyVtABKOOxzdH4lDaQF7LEZOkWnQ4KmcHX7tqNZJzpV9EygKnjJb/O/1JgihPyoJB9Omj64bZjxy/32c3Lu3X0az54YfISDDwjazrzu5ofRxGhWSznYLNiX+hXIiseeD86g3wS2S6T25nFsNwOQAKi33z/BlUGXTnLuoceBucE1dZgv4ZMJ6DimrvKN38Bz70Xa25qb8LuuivG4tbd9XWN4QF1Zk2Z0f+ftVIXhAnGLegpjMpChSgc/nmnC4/Wzze4NA5bVq3E/+YvjEurMwasZhnnAeuKReuZS3X5bACHSwzcD4PLB9FzgD3J8HmzAsO6DAe2du1I0saJCUYlfgVsbVVw/qGpkDLASzat4IUMYcbxIsmrWNPLW6iJAd30Ygmzd2hZW2yeCZxqIK580QCSCMHVvoCsdB5XTSwHpcmSG1oYIyeWYdO0IlFVwPpkTBVOHSCpDDDhRjRG3Y0PtWoYcIL0dgZ5O6y2O8mLTRGOnc/jzl7AjHwLTdFVzP4B+InuAIaGgAAPYqqZvrD8iPhx0bdgxYa6VhGSLZhGAh/x1LDcEUyTCX4/+xwEPHPfTEqYX6emLTFUKRxEEC/4bMZ2WUh6PDIYI7dzY98i57dF0EL9WhgA9B3k83Rx6vW4MdBHMoJvZdynjb5WV3tYMnJhTa8HQ46KJ3mvWGSMrKzUfpFMGLF0Rhsc6M+jnAgesEze6YINp8cs9jyat3iBPYH9yyaBHvg/khmJx0nZ5m8Mv2d6RY6cZvDDIhUXf15/A4Y/1D/c+rNCsjWeSEhZ+9CxSU3b0f90v/MWo+Fayy0rFKsgvaZL607ZE3liyRJ2+vrYbpZ+YzLKcoBG2YdCsTUfXDt8ukJ5hIoOE7e3NODDYe1bgcr/v1rl8HLWd+FW3yWloAc0/WzWKcUhfZ5YesAdipNckTb9H/BAZ37i5W9qUHyCJsMBYHsBNbilB6sz3cBnQmaDRXMCc7Ka9dfPT7Gg19op45YGAz4jQRhTghAddHQ2xSla4jNIV5ARhyzYXHiFKX2G7U9odeLM4WAVhQQ/YgYcbbW0a6Y4b53pR+F+5yGhQ77AaCzwGz/j6xD6iNWI9yeUPBKiynRnlsb7PeQLhIZ69oJbP0suA1YLRokleFaz6tFFnkFNHbur8xZC/KS8oIvBT/7qhqfT9MSIaDd/9nbzxOSD1DAnJi3XuOH9M2Rrmy3XWSjnp2U+cbVq6231elF7X6zfPTwqPx7JJH3WWxpLFnoEfn6+NTCRJP8z5BaqzFU15HZNRrr2DpZCsISfL939Dus1JM8I8PABmx2Wg89BmpXAAJ2/RdDCAxV6wabM+uSMYp03iPsozfVCB+fsPVHQ6jsIwYjv7qNWV3mfjwHBHS/keMb3T0qT7X4gU0Q09aUi+qKgJrvD0i7c0C6UeSB4zBLlAeZn55E6R937khUEVNHLVODslCVSUItucv1Tsi9IP9T3x+E6jxNTlkQlgELFWFWQ7sUGoVEWMMw0skBB11jDADK5a4B6Xg1uLCgIui+pWMoF2U9PMgxdkUzErOM3YB6FhikZzY7SKdjfS2OHKg/BFfAW2W1JByGVFR4584M2J/TGoAuFITJXRIAnheTs/CA2eQE8si2iD1bWarzHnmWIeq1RgFr7GUF6Ji9/B37HXUNskjDYsXgRYBoXVLO/ik5gpGO51Mu1L+eYC6XAMSY1SI3VN9ZyzcXWgNAt07Vovqk0BLGsoH7mPDsDOgKPy0jV1SMrEa6x1XpWOgfCx2PqxqwYtgRoZM5gD0BYI0vQSXAiWKPYv2VsDwGp7EzYMlR94Wh6tRPYmtds0wOJ+ESPMhO9vkZG3AfmQNz6vlRBb60s68z1XCjj4hymQoSALGxQQZ0noM8TUtSZYUd9oCMYfvdn6nEMuoEEAG93bwemZPiUb+Zm7HWW+++LR+aTpQFP7Z26McHzhN0IXXAoAYOFCqBKdjUj68f5iJJocMRGgfJ3/2P6RsMXSBBUiw2RioulOlzP5pjHZRk3RtWM4mo1LX8GFA3Tn1vXpN8dNAg5BFEeq9CK7G756d3u+fryQ7HjH7xB4PSDB+JOgfjl4yPiHAWH+56osyVtc6qTJkIviH8bngFOEI3ZUduz+lMCuJoXchYeDaAd9ohsIoXRwpyFozUwgiyVKJ5ZzdAEWoGic7k1j6spuYdMEsykGqtHYSmJ8k7z8Ut8E4jT6LwrM3jUKiIRGPWIije45IjXVG1uk7PwsDI6DKtG1l6hHf67+5eaJmaNOE2I2kZoFP8M3ubVAEFVeMnCOIAuw6pEuO2SLMPf91AQUBKxE8SHhwiO+X9BtaC89WSKn8q0Z4F2QV1LcjLX9GrkFS2cV1Hvbb9JTHJG2l6MgN2BgnTHSAm0arQ5Qa1Ir9a/tNpOesh4Sztd7sMjAZ3zyUiwNcbzwt8wzIxD1IP2pIvAfTHLWym3XUhuQHubC+w8YsONNj4PGziVC1ykLnPy/r/YH6JvSZ2A65ZoSTfe7QfGOk2tXfdmQZoDZQz+EINzQnWEGpIrEgKtjlUoKtu+3Y6vfDmRVaAbtp4ovO6rGh031HBFWzMrX/M1iPhq4FVCPOARxe9B1n6bITkBAQRCg/rrXMFgkrrs6LvWzbGmqV159GMcwhqZbqMaHhFrajhsd5QuPL7CyernYR9t8Q9UheUkC71ERMCC0xqdfszXRwBZH802JwVnceHmxr95vUOz2feiNRFP8rLtZ5AZoxgH3T6wDqVH5wF5c/pfhxHCNsj9cVglaIs34KD3XhNBGpBv3CEtYG7YBCA+7xr4jw3Z59XjgrvBaobIwYYqoRCptZbBAo6o3JRhBjvjlCAx9YNs3kciEGKdBtxBjw1mTWf2jgIvY3rrSRSLvIKUIbUz6eORAuS+nHDYNcZ5B3OpHGwBYAOriFWEYtVV6pIvlld4IGujoB4Fy1rg8RV4qgEBJFykwuFoBgohdRPz4v9cdGD9UeYusN+5tiDan0a6JnynoZMxXXjq8GzsMZAmNgvEjzyvvdEFWMN3/YdiibSUomC+YEjAr5dNwpYI62hXjZsD3OC7a/oGq4iz3DWOl3JblnG3Mx+4/qOl86no2NO/m70rglxOcqGZeAADXx3o/EjNo8ICXD/KHSQqUCAQWrzA8ZkJr8KJpuLKaEWxKJbvzbSj3AmggoG0L9TEYXqYW/6dy60LkyhQDynPAhMyTsTDMeC0w/b0J6+wEgkqOeHg/ezxmAdcAKZuSi4Q/xks6PASQGI3EX5RWV/a9lBYKJCF1Bjz34Y6tmpYfTqnL849gUAACAASURBVNWEjKr50c3M2F8vG9ekfLZQLr8Ybk4qy92zykIIUKIgn7PpZW7JQzsuNofaQ9bnoCDMKQ0iIp9E7SoIy6YHsrJQp4loe3U8syT0hs9m2mcMdnZfdZzkAcg6id1X/+SRuRfCRCPC84lJW9E4KrAGahcejP/ewqk2ff54SCpxZ+GW5A18P6kO+NruPioY2MUAOgdV3DNYShiG+p4jmf7Pl4xffDjOxfmNftQCQIfOBt2EetabMqixQMFB/guP1doli9oaoxgwJd4HkCojYNIkScmJsycnrXzXvCRjeI9rROvCmRizJcfEFDUYFb1rKwBV300LtHG7qOFmsUqjz4rKhbXEIKOtz5fB630im0GcTmoUe82iOh/eBq7fCPt0cFN0LN2EQ5eMj/zu8QAvbxDdOzhfP6QUNdwaz0ForAa+858y0pnnjKVagRWgy8KJ52CW8DZXRkPdDBAbZhS/K9KMUGUNdtj9CcBofWbKZrLaGtQ2v17Mc2rKLM6Ic+2JQq+y4+5PjHQr3BT4oMTMseIQegv2qyXjB6GYsAegMLKz4yVhbP+RuO062XhCVFgg9IKGTAJzHj6HdOcbs7uk5DuuhuH6qUkIzCJBgheb0zDMkYSzUXB2ObYtflHqgppZaT2Yi2IOlOVzdon9cVQf/5q53vCLYqsiHfn4gC1NYX0hbmR0RKNj86BKDDuXE/hNojhcdDjOYW53PXx3h8WxYTp8KnT4GzeqHYn9qJwdIeXvzX0yyHwQ5CMRCdwxszgUCfn/dptdaA+P3UlBZ0t+CAknvnvhJOvMmvRMSpY7+6fjEGZpx8H+YWp3NIsI+Z3d1Po4AXQUchkVc3LZkVjS7TJd7lzl7JwWADpMC1QAKbpokr/FItpTtwJqCYnE2iV0HnKZv4CYktWkTjgHFb2pzoSw7nOzTlCQyzJTXJTw0awTWLUgFwf5i5RFhswJkWtpQL9orgPFqk2+qnECXd0IpfbhJeJ3ZYFRwauwK7xA7gIHwi1AVXQv6G0wk501lgRiSkWKDm+nLwNquZGh6kklAWLIENBWNYbKGmCI3K27FcNJv1hmT4/SYtlDBAnhE9zpPB1L6sda/v7zZpj1DzRXgnR1IW7ky7dR3pdUJMTgqF+7/OpKQqnJ+02Gu0CDuUoKESLFFczRA/ntQKs39vbkp+sazZlXUh5+c9tXRhVjjuBYG//OdUapCkJplOF/pDgU4rhJrwI1NAlaJcOUbq4wNnqAcnl2szD77ovQjZvC54LLhhhcHccqJ8qRSXNB5rBuoSJHemio5tlh4NLERnb/ifhVLLx58ZiuJ5VQUk8L050MiI32APHyypw1k+Jz1N7COB/xyT+3DiTFgg1TBDv0XctQebqtOZEzP9CFyE1svFxWIEKE1DKG8BExO3JPRX8TCcWOh2BUZUvCy//w60n2RY4IJ05sV0KmMzgWHNruaz1Ri7IHDfE7l1bUnoTJTV2QbJ61BYBOT6ScBR/FoK4VCDaE2HITM845YiesLW5NQ/XR+6bzZCoY0arQBACHyxE0hJ9REAby4hQF9DkH6AT+VHy/m68Q7Cs9Lr2RNt07QHBZ1gmKTpCcQB8zakLXKVZgXVAuMgaWB1gRWQn0cE0WMFmxarXQLqLYgYAyGmsAGWBY/1Q8FMd5FlY74qHkQj9JnYg3Ao28X7hsDjDtyWxjpO7iKpYE0sWcN71qHQqWmQcGiFZFbMNqx8n8iT/58mpQjSSx+vnQfVLfS8+CROLptMJ2KF7gEA47z5WqpoGr8H2NjM43MI5VFGYDqhTPlTtThQGFfM06wpsUfXcsmEokiDuXuz6HXNuPjt9+HbE/lmoYYDp07drMKJQS67OicqxEF2RnRHKH+hBWp/Scb12dXXVqTSNtLxhk5CVXd2frQBSl6+puuEORRVN0zZ+CfLo2hKyN5A/ARnb9CDafvjF35TU9My3Se3EPOtP421wYE1qOp3Rc1zw9Y3CdhfnRSqv8H1ol6woUmbqkS8jZZ6dsuCrZnOqHoRJJQIJJ44QmDRipEmoTXMf0w3+55YE4J9F3Ms+4Q3mcGYknlDFBbshfLJ2ANd2k/p2djB3Qr9NpTAHeMunjnZ3m/vGWATr3QQiIbYuYDzEiaAIygjtievKX8zMjqkFhqqv8heqfGLaIvpGpANyXUBPDXC3YVoMGl4FXHsR+SSCKCjIdBp+/wIBDrcDRG6BPbyd3yUxCVRF2ZKN/Zz7FjbzDFtDNS6Y+AGabC1lgWOcIiYLFUpshjsjW4TJpPxh44OFxOw3PJNN2rs5nS3Yn8h1iqut7JQeN5H/Pz1gP2W1Q8JyErYd3i1K/LpLhWfeF2+rl2WuMcgR8BOD+YdWI1/fYaVsdDKHxQ4Q7EkVl5CUH0GkYa4wTMTh3oRgpaEuhHxSBHQIqyZzFrv/0WX/YJ4c2HXq4v0/biMDDuDduxsfWDSeqyPVoZpF5ccwuwosQfjCl1EH9y/phTS00+u9Z69gMWYK2hB+78bMZDsdpP5jEiJKRMQWDIgsYCfFfuDQx+StqfL88GE8xCqQvPDu7Kz6ipCfvxUhrTh5KwqDYOdn32egR1lQigQkg4i+sl6Q8/HB/d6J51ZgfHLOLdLsq/wwLBvw4eXEb7dOdE/CgQLUhnmHpItYM8l29eneudXhOiwFd9Yqf8NRhsTSxPZVCA7NaFaMQ+5eci34COvAq2KScbM4giJzDW8JEUezZR/E4HO+VeZBc7fxnqGvMk2C10TGTP7oQCGSndgdkFBsRZl7N/2Uxb3z1ycREBIe1IoIfWFZpMKE6H6QmR/hXMQHAEFWVYWMJ6rmu5xHEbUQSqfQmTAMngAskGiTzrWsFgvWcseNecfuXRvpZ6UejzFsCSRORr7R8diGC7xqYDqbjJbNeeOgZygI8pb4oxUWTIkq7ty9hb4HrD4hHEsObh5+xRwEy+c2/YQliD2OLDHkClw2H42K0VDfu2b6E2KI7+6exGAA0sMn/dJJX1lk/DOnGXof/MW2TyugCZQQ+Prlx6JdNSX3MXgruBXUKwhv9ecOYlnFdcxYdjn9td18KzJJC8v1rlpEEUT0gM4DbmXS1jWa8cTZsjhMihKCFaKPcsqDP0xMMPdJ3+6U/MWmbyp/OjT49kPTAijEQQS66cvMj5oofLd9nX8mRabJRQLnZifVprQTodCl2t04mqIYMEXKDTHGAOFE/YrTqpDNW6tFlepy9/iUE/aGtiZyE+vA0ZzOAo4LsvhS5VpOm5g0dOuXxMMlVbhnDjQxXQ25eUq4zt+o/Z91easdhG4G8Hw85YKTrUk8AtmLJUuO4utYEFYNbCfgG/XGiksfDGh9lL3Qm6NnNg744mNCkjBmkZX9z3sp4Sx0ydV8QhLpCW3JcBrW5PcnsJIhiR7nRo0OpIiuMS/mpsG6xmQDHQWRsdtYkxftjQlonTTQuAUwp5YMmXScKOEeDNrl/+Zj8ClcGLOQ1Oc1v63uQ+nAdA6uQuFABtUnh+GoAADHUzfi4PC8930B5le+/doib0WF1bBczFB1agfiHJ80sCaHeW1K7UkbIMrwtN3JAZ/IHrMalaXY81GvrsqJ+uniCa+m6i3upj5g3vk42FU7wW94/cg9LC05vROLU/0Pa2GhXbXJC6wG6m8OHLCb5OM5Pw4lKQee+tzmgKdzs8Eo4Df4dFh6PhTFpmN4shISMUmGVmClyC+N9ZRuErAjbnFgt5RiAT7enhi7ZGcOQmZt8nOKZiRGl/LTgBNhuW/MsAJ9sW3Qj3V4YTtw2GWWJSMJH19Q5uFvP4m3tZuQu5Mb71bJxh085ylHR1Bvo5yOluKHXUcxbZO84YAXW9ZAZo7Fi7S3ogIVIFVMWJLUxc3YrKUY64CB8OtlgduZ1enVXb3eClXCHElaKNBvoJ6P6OicFd5zdVB3HmL17YPp3+qXzmgiZwaBmwIj9VSSn62tdfIrKCMcAvAThQgQT/HRoqh5PIKYhqx0eAuSeLi5vyUdw+r06FkcFn2FD1lpLeEvG4+zaCw7oKEzIS05uE4VNfCUlNfnt5rQnzoZ5hR/H+s5PEfE+OYQBEtXY+lBFD5cyrTRL2Hl2OUR4mRl8BW6X28RhQKEGgU2mMAVJVEbG5EOnGLXTnD+tqaLGBwUxCkWiH52f5vQTcnyjbDOywnIeKIlLFh8j6VmcXtbcDwZ2LpxFQdGk4xAspBBQixPcBXJG3KQIIsn1aF8nz/5uTBS7GZ69soZQNXcbKAludg07Q508ZzGljfaF8zYqtEJJd44Vh8KEtBDNjTvyROhEicjHT2AOmNJMQDwc2kdNX6obfZBL64QLDuhMD3UqkGYrPTiGJKnDjcxcl9bkXeDRUvYPz7Oho8f7SgoBim5fwQ3xCXHzeMasK9kzH2rVEwMWLrDOpOehjXt6Y3PYAzW7BOijqCP8xLCXuUVGcfjvV41CXPEtvQEyjUyJz4YHB1urarwIZVpwMKElHLH744SngtzA49qooNP9PlvxTFyIFBAneApCCdct7sRFGXHvp/SAdWnFu1yKXV1wQMfYJCNKUZpekZkiy5FinrvQfV+Kk/otjRkpEVkhVS1WbgHBQlIzsrpf2Y3Q7Tv7HyQjK35Fft4KcMmvSx5EdGA4DIkd53dOXYKWYBPCsuenb7wqOdMISmLW4XCoIAFve2W/gbZ5ejJz/XRIKtJvPOGrj8fgLCWJfEtecds8Rmvf9YIDOoQvgE44u/LvoZgmV6J9XsOWP6cK1UG9R2Aq+hBUNBJ+qVfwQo1D+CVidiXpk/wqQZK5xVo83vIBtHoPAPqB+Q0p3fE/IxAy8si3+u0unQ7HxuaxtU9sV4oFTYAiIM5vG21ZC/1j1hOASA4vHwkCDbUMn2Kkrz0eTbxok/yrl868XtQjxYMC90JWS7JuZZcGZ5cHNzVx/EX9eM0d3AUHdPTUx9dqFaq+IoE87bXEWVqn1hHzmieBQFN2AOQoR9ktlZqJC/WSOB2Vm4V9OP9UYT4inEf2xV5Bj2/qSMLevg5SuDR3clv5Oohyci0YpfsYOUl0EyY3kjmnlQdxUXcH7GJKi2yxOKTsXCuoyqyfFqk4KUeMGqTqox15pPAeTwrDi3peLtPB4aNGmF9wJgDlScsFf5fHJDUX0HFpEvACnws42sfROJsb4LUgVWp7gqFKRe0XJAU2gdHWCiwiygmPK1WbwXGHTVQf+r3FuchvXw/fV40xsLRA6ONatC9X5LC31j2IcpzxMySH9StYqMgBcKagQbzIEkXSGGdpZ1p3bFd8b4QRfn3rogGdzbWe9W+Php7910vHOkteeMXP2bc+AYG+tXDoTSrB8a2PqU1v0CxAh80g7pFc3oAmfAVFMil8DAYZ0erOHonzVSk4w8yECKboD8GNhoDd2bXuHEeRTcHS7K1igBsKP6cX6oowA83VadAypLEF0xtNsO602+Z+cPqIVKqDCPINkClFSG4zBmaP5GXmanb6IoRLuet4rWvrBK01d9xXynX4CUl7/f2BpL02HplUTeG3fT7dRXaUK2V2PM95ccxAswAduFTFIsTOrRfvHDnQyRUFBjVaiIeUL1zbUPXYRyN3LulqW6UVH5XOSQemrG9liQvHoucOU9itAlklETlhTWSVJ/DBYqEzBvIQkM43LFYC9C9krBOG+d53zFUsGDD68S6DtPBuIioHtY0G60K5DDHS9SY0+hTJJu9pF2QGvtc/7dlpm61TR6EdfHDVKDxy5Ni7IEPw3MQzA65moFmAfjpDOI0SStFbQSHcCzldgUJ05YS3gPL2TUEqRDD+PXUtUItbD/ldy5vUJFogozIU7mwayN6Ft5O/QKlj4UKkkEeFDL1sFCDQfUPEU2pOm6XXSCJ3I5fI2HSq/YI1SjixFBkbF+5O6i5o/a5jBdNVA/R5Cox0rHizLs9b65Cs9f/OBRvmFX4jlBXkzoamN+YBYd8rO/sSs0MSqyt8cjyPfzHMQLMAHZUIgE4QPxADSjbkLtdBECSKGiIGO9w6uhEUJpic5BkXzr1SuHLE1NlbzKmmAPSEKZJ7pOVNcsymNAyGu7Nj6DbZwdKCnVtwQOQixOYwKpy0Iu42CcVBzkKymTN4MeQvYGNvkfLB+QWb9LRl7F1YgYT3JxNVueSRty5PygBJD9mf6khOkm6D+3Ktp7XODBBxs/57C6TmmaVB4BIDef/y0a3ug22dEXt6ucJmoFmAzhzh1UQOCGGNagV8pxmwDqaTmxusBy7Ba3ATQobkgp36S74X8IXU3hmL9YpFupiaxCMtt9CBcgJQESOqxn2hLEhKrvKnO3ypGPKcxm6Dip1GLVPWGzYZlNMjBe4Fa1QcJXYfI535MY8fWU6oPALlQ8nHK9wR0c2FGjU62FtYN3wYpF9n3TIId5ZY8W34yOZDDHk9hY6ntdIMLLntq1Ex+cbelAXz49Skny4eb1PVvpXu5unGMwNNm4HmArq6iwpJh7Mm1SJmL/8ER8xpuxWU6F5HAIXEI5JgJEwLaK+dyZPKGAp8QX9yvfa+sWmjtjkb8Qwdop9Riwq3w8TuMU+g2Z12cKGenFYl+9VL0PWYe+GCV0FzYBrXgvWKSNEPHMXsb8JiGp6AxySdC9nYG7ZE+ofMIfnTUbxA0Si+iMdBggmDhL6+VbzN7kzjlXHOr0fs+/2YHSqTKk9MKsT3UpIp0nZlPL3nKS/2GWgZoBtPh7Aka72ePtfv/CyvOleAgxHfI1V4KN0QFqdBLwj46hWOACPs0J7XiLHc7IY+5MAnlhBKk9ylx1UiFHGzQb7ve19SXKnGaJNmadHD3by6RaexfUn/UmxzYymi3gUeCOI/qVtk3+DQQX/+tPZeGKexvYAviuyv+YXJ9OI5ANMvpGvXfsCX3REClx4as3tu92N6qvF6UjWRGBZMv+we1PNAl+QMtBKgoxck2x+17eGmlamOmaxsc6l7WS/2OAjVsZdWeVo7uqqhBB3oSS4XrNGW0AIHPjM7OXkFbBFQfUDKN4kEJwEk+WnVGsOFMBitQus3+pXAPD+0UDtLTme9cWtmidBZqus5bOx+ClO1w99o5yimYeWRtj6ZPArMObsTdkXwMAB6S+bW4TCu7IM4RWcnZV2dfJQCDkSKLj8W604Wwyt7zjxPf4FmoJUA3RgtMf0wKirdOSy5qs7Dn7hGARoEG9DuUBwqhTdAA1FAQhLYmGY3BDMHv5J1goaZTzLehGnuki3GTZFRprxvdgawacCbmjznW7dtmSV8CexXjNpy8OY95zWSCIFtEAQXWhcYGKOZmS4LYw61lTzXHHB0IbU6zX6Jl9qFZGYnha+XV33+mUBPmOil9vYu5/G2NqBbzxWaFhDGJuSSUpx73tHKEBdK5ntRwvS6rhEIM/rEJpWIoTqpFk3RUSKboJ75C2yJmbLwEl02wvamNtwALDMApTRk4AFCBCG/ceZT5XZSw1o/s9ktZ5sEzRoRrUwFAU1QPVIv22UD0/e+q5XnNJwE2RIYIesZonWYdyx0xKOso57mmQHPDFxJM/BtArrDeQQK974t2hLFGGCTUq7IJhwJYKV8HasBkTV8BBOCsQ/wwZUXpIgdTUgqRwwcN24EwgqgT3Z4Z1cHEe3s/0CDADEa8Ar7wQYCGQmUCJLBGj3DFyQGxDT0NBgKmsONSBGJpivWWUKgngqQw+u+BFYRIvhxDjsjW84bfb2WtkBKXhjeUSYESQ/KHE8lP1ev2fOZZwYu8xm44ICOmITAotOHzYAOMiKjJneKaoLaGVrWRilfR8PFB1ZWFIlOHPDi7xj45pgaqxwsxjsCZLvP1qKHNfmlsWbs/0hctec16v2pEFOO6oQ1C4ZgN7J6XWKPTpy/cFNGxXGlVOEvnFtdJvXh4H/wzQKyXGjN6cOWsHgcW6lVovjUe6Yf8SW4PfKT+6RytDkQidwvOldDri5P88yAZwau4Bm44IDOXO97VyJFFS4DZFjouO9UK0zXstZJFWmz7amLZBy38z8S9iNIjNxe1zZTMEPADiWBIHDcbOJp9BKkNoYqf5HaZ/qj6XQ2II62B7ckpDba/Oih8hE7DKD/1EGtCIbH8nRsBRKniqLczcYSsvstrTzbPI3ciIwuLAme5pkBzwxcwTPQMkBHuwKpTSM6VCWnbXQquQQLHcepoJ4ebd/rerHEVUMkkz5fq9HrBJpVHNaAroM4iIk4UlnK/AnbgIsVj2vkQIlRakmDzzm6UjYEIndRxRwNvG5Jv/q1jJmNCHkIqKcKHKs9h9Er42dv0aS88NaRsawr7BiQx7Bp8DTPDHhm4EqdgRYAOrwzhvbRZaIxx5VH0Lw7HkI8mfC/IJo0k0TEDL67waZG+AF7jvwR4D6Tr1FRGooZKATcYT8wcoFvkIu4G0gGPsLvJzyMnvE8JLqlQTTcBV4e2xk7nc4BWSJIWXvg6xkDVjADkyQBao2x2z2Ite7kI/X14hFohqbF+M6poFDCU535YB1+Owlwxa1qrkjHBsVfAlw7D7DN0ejwWs9Bzwx4ZuBynIEWADpgRxYUbGpocaLMgwgaQvvcQ3KPSFJvb8fwiq6DmqIK1DgH1piM3g4btj8LBoAF3kFc0MA7YAtsbRLwOezc/YPE/kjadx9JREMKGkkaXCVjkNUlWDYHkqzGW0hwjleXyyqFTIUZYHEynJbm29mtARyHkEHcAgPe1MZgKM1qXhotAnxIG3ZLnuaZAc8MXJEz0AJAp2Yx6VPMEfP65GEmYzuD7JLIMECkIASjE7WIqSsQT67aWi3tMxGrqEZUes9rhSq5VBqbBgTv5yq04I7yUGQcU00BN+Q4+A64s4cg0Q0uVv7jCE8txjv5e+ssJrw+V0A/xj55tdBHNkOJby3AZxhsINgnIZ+Xbj3NMwOeGWj9Gejb8dQd/Q5rpvqMU2GLM+JzyoNa/x4t67EFgG5jIapxiKtQ8c4kRfEVCCM6FCMUm5r8XPAkEOhGJiz4E9EsXr5h0yxsxA1huYP1kDmkvaUqHiCuDHxSFIgXob24EJpRTwMiaPfr4l81N5OUGRl4V8u+D56rPTPgmQHHMzC4S+HfJm0eGlVIXdmSSt8FBxOe2zywFevWOr5rE4+2ANABqawN2sk9et5EbE/ubO3A1AeCHQrEK0aCiNDgLpJ0hSQB8hFY1kHrf4fT1K9NfJKL/XSse6gb1jalNEf3IrVM6wTcm21T73mrQQDK87M9GnS3W56Mi32yPOPzzMDFNQM+XnW/HL7v4bE7KFylj8yUVRr8pzUjPk9PuKgG2gJA5zmwQPETYiQC7girpQ4RanFvHar0xwa/KAONbgR2Imm6dvqYpCKBdNZnRDIBEA6DX9TTmjcDhxZpOZbM8vTAAgl7w4YA7zQBWcqR27yePVd5ZsAzA+fPwK+G7/vNyN0RAcgipBVX+r2+p/dj69yOHbkg89kyQLceIqhdAcVcIkwLyK5iQYmsIQZd4l/qxT6FpQH6VcNCp8IReQ2xKz2teTOQ+okUdzU2RqIyMom7QuKeOkk9JkgYPK5ob9Q+qXl38VzlmQHPDGjakC4FPxqcenVyZrBvNb+n6jqv5Udjf7l0HPl8Lp7paT1At34mbHCpZFQrhjngoppw7sssqUtMIkAkFga4abS0tHXP7AlYEtD/4XH1tAOfCuVl1krqLBZNcV/4SPkniSejR2o+umyfnZOneWagZTPg6yWZKqrrrtDv0vSEE09M2tKjfYmXiZ+ZCafoi9sGvLSjT8smtTWv/nYA3eEITx2SBFioRBQAQQigbwHTnZVPc9BJvSRrxCbFnUgpn4AwwamLPN+3qh+EuL40W7LBQJ1Lgpqk1oFXfBjU8zOE7SC4QnMWUbzQ5FVH8Uk5QCkdhahG92d4mmcGmjsDY7vmjYjO9/eq3ZPfYenRrrV1F/vXqVtE2Y8Hp8aGlp+qDPhgf9LmbIp/tagNjCx6adbavp0IlJFWU2eCdfntipbFM7ZoRLYXX0BAxxd66CsJ61cNcHE/uJH4UqpAoLmm4D0LA4DVdZwWEilorhgbPlJR+4hGxM1o1SB8pHiFXna5SbmrwGLoC4bNtgBMlMTu5zc0PDiEeRBjF8LnMEucj4HMMMqypQqo1KfGb6zHvnIyGVeoFGpdisi2X7f/TQ53MN3I18h16gEpAkWcl1KUkhEBvTx391jobs+r50T7GRgUWXhb30N3DTjoZapLL2qXVRby8o4+a49H8cWyP/liODI2Nu+xiduGRBaQ5Zhf3rGSsD+uHrHkSBwo3OzhsaT9deIWpkKZRlSU3XAiau5HaIUvlnYBAZ2Qd0ToEgWqN2gTBIsJUx0Apc3kQOBgh1JLU1QiBPjoteIkvMhPloQuQwSwcrZLYQ1IZLCSdAIsANik0DJU6eQ4n5IPC3qHOxL61OhXEKRm/Ti+QaskNJTCNJpcCKAr7bkUddO/E2qZ4Z84A+gcLoh7IQ8nOyMjYRgS7GqV7lw9FzkSYkfJ+dbLgM0ju/lPks+A6Q2hAHrKRkpzcOsmLV1u3s5z2pU6A1TH/tHg/b8asS/IV3599fWm0iq/zw8mvLi1H0B5Ec5Kl5CKG3oeeWLSVp0bkcZ+YlFG3AtbB2zLRS7czNan4+kXZqwfHp2v1gS6PlDY7ieLJ+45ebFE811AQIdDJ1MKgZeqgTigeaP5BTFycbEeX9dQAPq8d0HIuy77M6xUMJfIJoQ3QD9ArxKzAHkS14MA3F/r1Ecq3vGpi4ZRDztEUKjRhNjh9WGO+DQUz6NDVdYZVwFRsgA08A2sqzgjYTmMjDRGRyYR5lMUG+G5zU7CxXicfQSBTgIAc85FpsFLXNB9b3Eco+usE89xzww0NgNjY3MfHrdrTGwuQFZbr5VV+R0vCX0npcdXhwiusYTXNdbJhfw82Lfm5j6Hnpq8NcBH1QqWn+7uvI6PrRu6KtOqTm8Tx9QhsPLB0bu/NyBddQsAlFf7sUj83/a+Z2tcQkoTb9Ts0y8goOMRJaOhiNb1sEbSYsiGTwAAIABJREFUSCFxkeAa5w1cpiwyxrIgsl4QQ2hi85J73t+t+1BIyp/WkZnGCagkB9zpVKxN0BOUDhGeJB6QAh3i+tDvK2aJ84HqZ3gRCqsnXHTReHCCQmOGi2SzFTiQek3K7+3XjXQ9bRkEFLNqJDtzMRLPR54ZcG8G2gVUzel+/C8Tt0YEVClnYMGZgI9Sk17Z1Rc0v2iZ9Hk9Mh8dvzWpnZLVsaXwfW7LwMUZcelFEe49t+OzRkbnPzJh+8jokyjTOQNUOFIc/uNFE1pi+Du+U7OONhfQsUOxtaVQTnu37gsTfXyNVpBmNm+BP8pHoMHAceewgcX5KWIjY/OadeuchzYmuGFJIK8ABI6qxCaclnVmRAHgho4blgG9B/jluAkOjHRw/OhyjdITys2IBc3JmOTcBQNfOpE36HC8loN298W0B8Th0BvWIS8xz6nCAevS8sbk7HnDnDeGEcLnQDrhCPU0zwy00gxgls5JyvzzhB0dA88q7hjK5YuD8T//ZsKZanauF2mbFJ/z1OTNvTtKcUp+tOXn/N7Zl/z7VaNaONz2gZV39k9/eOxOP2/dxNS0snN+z2wa9OI2R1XdW3izpl/eLEDHEQf2AXxEsqgiDxiGwCv47qxRXgfCl0vMuEacenepJspVDhs4ThovlCHWACqV4YZI1QhIBhgbnJzUNiKlDGhLRjDkj1yF/1PMed0HKEa97ocEVQ0bn9uhAAHyuo4VzYnRIHYoFQ0DbtwRIoV8vICv0OJFelrzULHc+TudQ6nDsbCqkYRLES+KQuGmwu/DobeXQaoyzYX7tbI8rY4yHWo9wCHcSYgXNigB7VskPkH2g6tZHMJ6zwB6r2u0dt0dTuoVdTDEr8bPu7ai2rvy4tgLX9KTPyEu95fD9k5JyPbWKWm+xRAXd381+XSl8598Wz9wTOiZV+esHh17Uo0ZX+iijPhH1w7LON0ixTOAfnPvjMcnbvW3APrZGm/Q/MP9yUeK296d0ERAx0OYvVUqCpntYkvpNSAMixv4k7SIxLZUC8YppYd6r9AmUhuausY67gCIUMl9bnJgJqvzJcvuF6LzUw0yISxO69xHJCLmPQH0NHGp1XqkUr0cpE/xUqZJYizJh6VTLgrNgV3EjgKmFvuaAUN6RFJkrr2YzzwUewg4FprCXHpjrUq+SnoW6SEZdPWCc/g5eXYB9EhR2eOnpS623JGUkyHyOOrWiFis3ZKMBP9B9uYGrp+BAfrgL8VLY0bpssJmtaMrtKz1emiu3hjDyF87JZSadYdL4iLMJQo3YzmeKAvml5wQUZYUUTKoSyHWE3EfmSWhpyv9auu9Qv3O+XvXentp+wvaZZwOq6tXzq1L4hHbcpCERxL1fs+gA8rHyLx9fTj+O19MbcsxNXbv3h1PPTp+x7SEE4obYcxLjnR9csOQvfktdWDOTsp6asqm+PAy9e2BdMooDp+fnrDiaMzWnMjGxvXtft5EQMf+RVYBGSJYaZTm0Yco8O0v2nAgEsuXAHQsaEo6YDsjaAExT2wS0YiCS7LgxozWuk1yAOisGaB57k6tJKvBxG6XLCc3O0kAKF+UJlgP/hppCRgz8MeDyPKjc9A0cJZtB+IZ4J6tgFEbr+VvgRulfyE1UVX5DqNDBJFwL/JoJmHAm+opZR/Dhkn2InpjkSDhIosrvSmeR1ijyzkMJDq0YmDnQkzIEdEnT50NKKnyHdSlqENAFea5v09tda0XWF9W5VtV6x3gA5TXc7yqxju7LHj5sdgF6d0OFLbHnYX+zGHr0/FUYkRZfkVAm/9QHQ7vQh782dCU+0fu7RgkPjC2vSuOxv7g60mEv1/IMTTpXnwlnp6yCV2Kukq30Ls9u2lgywGddC6vXbXqmuRMb51GlwmpN+0vbPfC1v4fH2jjzXETAZ1kgRSdQAXIOwVEiJcxqOGGyVb1M2EeAqS2HDoWiAVkKgA6eKoaZAWWKRV27BuWMrY8+j/VACOsXShvLPqWNMk5kyfkiYRWkkrMgoA2fbLSJDWrKqmbY6MQaM6OhnngKtZFKTNNckp/2THETWyCRoW9wp63rRIu6guSLKihUpDPm2BRbxEy8haauk64+TgXwWkzErNemb1G99dpWGFl53zR2DEuBdH80kywBDrxZt342tZpXoUV/idKQ3ad7LjwULfVmbYpKG7tc+je4SlY+ifPBP19y8B39lkKJV4ET90mQ5h/45LJ8dnKSIdeuPXzaQjS22Qk7twUtfjz0zewS1Nvnje+r6Djz78Z13JA5+439Mp4dupmvAtqJHzxjpWEPrp2+BcHu7kztm/vnCYCOgMBlKEgMLohnUnIhdlbXyNWp8r3LSPVi7cpnMLwRKNNnAsWOnoVpenmFBGh99BF6Odz6GKep4rknJzpSl7NCfgPm5Eu3H7OGOGpI1rZCZHNSEHn860yBszGAm692xT7S1vtCOsKDAlVQWCTzovw1AeDtc76R9Uha3Lfxb0JWTowX/Y95zXdMSsApn+TYX6Yf7oVTNfXWoTzwvBcJmzDU1M2QwX4KsmBpmF9Y4kb82HZdp33rnnz1vheU+91qCj871sGzU9LMEgYggz/NWPd+K65nMnBf24diOOrsuZy3uu4+KKpj969ZsXspEyVbrDwbMBPF00gXrTRq9rwhFfnrAF5LfkRNRbm2xdM3d4CHbr1s3x9y6IxsXlqeVOayPuXj96Rp5fiabvWdEC3HqvSusCuwGUDxEA8bDXCRLBYAQqeQ/IpRsTLpyimqfYgvyz99wSngVMUQsZokNEUM2KRULivxN0Y5q2iBjHugkOV7ULudiGFjMZ4OmEdj21NjsXZS0WXQrgse4X8vbZjYHLgrJLnultclOUh7XOJRDXbow5vic0epnsg+guUw9rzJ1VHbExWh5de9AdD/Kq/uGnxsCgigaWBvIdOhWGTdwo6iyYpzP8cT1lb56UHB8o6d67Wu6TKDxq9Q2CVsV/mQiYeumbjiS5pRe3gYQorAugB/ALW+fRcrddb+3o9sPwiivBukzfz/rXLZycdVxBWUBF475LxizMuakAfFZP34XXLkV2q6aqo9vnbxiGtJUf566StPxy8X7lG+f4cOhVx/aczs0pD2uTVGDdtGaDbjp2UitWi44ZqP1ssLko4BCxxCBYolPTPtQpsSd1WgtiFRSHGx7q0NNQ8LLNEyetNyl/cKGKY1m0QLxmLxVS3BkG0KH1vleCgC9aIeCrYJxJyqZdN4Cs6HL2kERY060r8ZDGizTa0S1M6d5fUjTLCtWT8+g5J9h+WC0kdw86DZ2S2iWLlTziZy6LdNSD9r5O2AOs8DagNc/LB/mQoFHjz0TF5Q6MK4sLKCiqCjpcEV9T4FpwJLK/2OXwqvHNw5ZzuxxAUU4AmyLdWOBlLA6dOlAb/b0+vbTmd3563smeHYvUJTlQoYwj3y2LamvMQMFr/mL7hzn7p+CG4Hu3Qa7t7/3nNCGfuh+bco7WviQ45s+Cmb4yXyHL+7x19IUZa5T7sC9G6EMGkeiuu9L/n60nLjl5ADHH0GK0L6OffQZVe4xjYhL4QsCYzl2pwCwO+K+5H60aq9IylEttpNuHjpJ6Rmzp3R8/m4BjmOXwOAkojulKdBNjFjBTUM6rKObj4WzjEtEAusYYxAFIj4J+gRQ0VkoQjajDw4C6saYx0AF2IL+UVQBDZWXIeUB0Jikk5e9FHRo+QfQ8uEI4wpZcLpX7fiD1/Hr9D2YyHT4ffvmAaeI2/XtFpwDqh6lU1XvZRfMDT1cnH/jZ5S5eQM96y8AlIqTWQ/eOBwojfrRj92MTtQyLz1dyXn/N5ePXIN/e2zJHzLXyDLmSXvxqx94GRe9j3qJviWCY7yvz0xAs5hqbe67lpG1EZhvlX40g5W+2z9EjXF7f335HbCsTIiOiCV+asTogoVXYT7vdVmdE/WTyp6GxbSjm/TUC3nnuY9+0v6Umy9IaR2O+28zKhgz7ksUJCw8+KHxZGPbUaANlWbEAe5PWxFRIoJPy1YcPqBhqSxKhhsmlA2SIU84VqomHXqW0gGFwGc9maQDQxHsFok25NuzTSIeWZOqlVrReHQoQePURPUVAnTD2uafwQdMKGif0TUC7S+IsiTLnlU/z7MbuoOaBCPPIrAm/4dKb7Lq8BnYsoKkb6wN4di3t1OA30q8gxRpVbHvz4umGk7LhrQJpaLWrrTe+lJD+4clTFRRxK0/L5dN0DWQZfm7MG5Y9a5BAOvZfS475lY1xf1eaffn7jN6NjTvrrOQBKq/xf2dX7rb29WI1aPrCXZ8PRH0U3pbrKKw/6v+393tnXo7iqzTD9QgE6aJL6sSgRFdGB0y9h2nkBjdhUZODCcapOwIrsMVfomlZsGMIHvxIL3ZC4iOc2oCESldAhwBRNCMWVXARJteKQrLsCyhnbiQ2ycYFo8tKzj0lGsI7iQ3bRKHOB0FP5kB06JxquNdYwF91dSh8Rs4eVrSgXLPE/rhn56q4mJKcm5AS+pVt4Ob6+eT2O9e9UFOhbR2q+vDNBr+/p5e9Td++wfRDuakZ25nUiznBztstkFZfS5JnHGuJb3afT6W7hpb7edYUVgZuzI3EzOHwOCjv896rVM5OyVKgOi9zru3v9ffMgpsvh+RfDwcjgs/+bu2pc1zy1WkMQff7/7Z0JfFTV2cYnBAghEEggIUBCQhJIwr5vYQfZVcSlarV+frZaa1v31qq4tFq11qXWXVtbP1dUBGTfCfsSCEtYsidAEvYEEsKe7//eM3NzM3NnkgwhDDDnx0/hzr3nnnvuzHve87zP+7x7okHS049eVHqRerTBEQVodcUEQUgXQcdzF+ptPdjy4y0Js9OjSs9eHp/JLYMORUQJ0kqiY5D4s1V6fHYVpcHQ426yZyKS+5MxVzOv7HrrW0I7SxY74ExttYJkS85Sq8ouPi+wNZ3zICLfqDnpquHDAnqwP4BNWDcNW0y6KZAI9BvSUNnNkPnJSgMLSCy7y28Gfj0GXa+7jUFvGi5rYS0y6OtmEty6ywM9U58dvJl0Ia4+UtboyaUDp+92BwHAyYpqdoJ6NBNi9xIO9fW5sPdEwJc74rDyXUKOaPsjIUQSL2XBqP4mwK1nqruLoAY92DsVWZLwwNLWTU6evYB8VQjIuCODU40Jyv9LwzbcFJcJYEUjoWZWetQflw484Ekle+ymLzaoeOZt89s2KVG7CsLm6/eH/nLuCCIlFz/RTRqeefu6NTd2xEm30qCB6T/c3Om/2+IAAC++fzd6qLlBx/qQ9UNckdY8xhLQUswiJArXMluQ0BHn0nnoUMvjp0j+jrGBhKR+LYmXqoEexIyRBH23G2iGANAkQEFYzJDMfql6qtlurCTlNaBUQnsniosZpQnyqn2K/Gyn24SHUweNOSEziMWGlYxRSUVQPwFGqPsBQchuihzHg0D8zm8sJQdtaxKF/SKlVHRdokaOo6qTIx2Cix/pu+3OLumgIvxQdxwKfnpZ/5V7nagDVTUkVgXUVn/eOb2Br3wNgN1BzMlIurvrHmgSeOt8PbKLA19b0/ObnbUdqK9qbLX+OXuaEZH5j/ZPSWhR5C9Yk4TRWbTAf/+xsRsJMqZ3JOXylREbftF1t40Y6nPopB+oy4ebOxeUeKiTTtrw9zcvSGhxzBaH8skpCnhmxQB0Ik2fsaYHWRH/OHALaRBWJP1CvR92x1BoNP/E5ZmQmht0nhgCIgZaIbz8E7w7drwkCrloUOsQQwd4UeEqrFXP+xyKz5Vb9sywFKZYCdpYt+jRUsiimg12PIk2sDjgZbM2YB/PYCIpVgd8XGylVOpdAa10vUtoLcDKonmrFdA4kmEz6MFWEo4uWU63rArg2tWMmmKm4WjSpLzGYfkvKBNCNPLPgzJ1jBCrzUJCLBSJ4Ir8VU21sXm0JWKgoOFV2mXW14z5wsI0Qi4o6F4DJfpig45DM0AIUO2m8443IW45y93MDpD0l4evGxm5X3fl5mS0Kz7th1wfuUUtG5NCUr4+PwyQtLZsQTW/17V+Ghk3QFXjYvZCArGZOetNWBdTDrS4YdoEtiOm9+Xat8jWaXXExr+25J9oMnVF3x/c2hiZ3qLWD34ycQVOtA6doeQONPfD7vYlTp6xRgMYF5P31ujV7F3UVexyvt3Z4aH5Q2rUSS2e7JZBx6OEjoKBUw3LC8c5cqj8S2CKchHVEhPWVPBo1TBhG98VIRTVQKjjJ2sZ6pUbljdtpuVophzFTSbLEUgniH2ABlwC9WBYadhZ7Bd2EKgBk8cWgcGwZrBgKBa8FSVXQAr+h+akG1uTNpaud0p4UG/A0LnLRUKLxmrLJaRctuktd1c1ryHd83dSnOySoRjDWapgawWY+C9pVqDhMM3J8ucvzAbcHmR1ydsEo2dgjFwyW2BNc7BBJSkCbo17jjUH80ECF9SlOo3hUVyUZUM1CT9cLxU5rvYW0PDc/T1SH+u/Dd4FbzrrWLPHFg1cnuem2jX5pUjo/QKpa99z9IYIzPzMdiOj9uGe14PZ7lN+7rwPpdd+MWtUrcTTLtfLAVxixqhWEYxTaRZrR2/r1TU9cbqdjRA18KmJm0ICrEmSkLtfXt2bdc7Z+Zf9ONHvjyYkJbSQWC6/vENl/ggAfLzF6QPWaMDkFr07dqVNpFcqRxNX+MPSy5ay4JZBx1rhpJdQmw3kSDOa2HHMOt8PcWAxYcWSagS/gu0/LjZRPjxlDDoGVzWcUyiJjvmfWEA4Gyo0itHHz+Ul4E1jK7kEH1yBxSKYVSbGXcw09lr7YuqASZUvBGPNUoGHbtfyN4p2o3jQaiWgb1+xsJhgPGhuQqCyWYQU0GAAsgMokT0BYwAm4r8qFRMoXDHKlQSjdTNrfyvzfzMwrDlyiUZ6vvmphqOMdtN7FTA6WwEMesuEKq+7Ck6YEJv73thVQWRgS6mBBq+v7QFi4MZzQXEBwPl9320TYvJUUR5S2+EUD4koJFqojtAtpvzJJQPmZERV8xaYki4hR3FmgTJW72uDJHc1L7x0p2HQ/zFm9S3xWTo3g3tp/oVVqIzI3pc7Yn+/0KmPCd7y3+uXUC5ZEdLZxPwrJe7FlbVD7r4UDx7c6NTfR68lHKLSiQHTPtsad/E6umqosKTYspDQoIwQkfkPt3R5bsVlmw23DDqPAmKAIi5/dBtt+iqwUFjAwEgBHEBpFFTNmZh4IBfHBHcQZPokkxNbaedTq+XVehc9d8b0rg4HxUMXYFQ+oB/MJSlLjlJfrBDZizQajM2gO/SkOftapqvy+jlRBuZEGcbxchdHZK5Y/xLtY8UuLlEfCcd/RsWLYGVlt3RJBQyqHFJdnXBXlzQKLwT7Syogr4VM9CcWDwJ7qdH9IwJP3ByfA0OxTdPShvXIM5Krtx0M/iBZvM7H+2+NCYZrLF+JsrO+Ty0b+J9tVYi6YPLYid/fcxdsSBjQ1D0h6TzveNNpO6PB5SGH1Gh4pif3bXOod9hB//rnAK+3Hmi5q9qaKl1CjiEs1TG4iIR4HgkxA5j7B082xjA1aaAl1pb7QNL4zfyhUO9Nb9204dlXRqybEp8V0AB3qvz0+XqfbY1/d1PXy54kaTpadfDvo9ay91KoC0+9/WALSlLsrI00sbgWx54ckDI5LrdBPcEAyG5Dx23yd+PgdLoYz6X7yF2Dzohwnws3i/IiAIvVG608TrF0Gr87tIuQLohJWhOLfMTKOysbhCkHRs/TiNUuWiX7bjsPm8heAZ9a4ftwaUT2tqGlAT5+qAA+uM/ANS07mZeAYHECJxE0ycFA6963+ZDEwXH4hL1FYznMTelQqIfaL1kgl8r9Y4IBf9iFEKcFKpGapTVpaKWxYdJ1cpgZ+mHFugbaxNjcd8euQqJae1afLYUtnhJmYeVgu8t5wLe6rVPWLQmZOhGC04EdvtjR4c8r+5L0/+2URWPak+8uvYCQzk5v//TyfvnOWcyoBZBO+bNOGW0DT6plQBZ9bQzJBS2pP5l29KIq5kCVe7x/StfQY838pH4QFnlZbviflvWvpj0lYZ0UR2sFNYsPGbC4k8T03hi9VqXI461sLmj52wWDndk7Skbc2Tn9oT6pcIG0x/LJLmr63Io+s9Lba//0uAbb8t7ue14YulF56IyPWPfUpP746bUy1v/tvvvJgSkEJFRvvBFYLpcLdbkIg66Gj6sOTEFEETyEQByS4lJUU/Nh8TdR0AWtJgRKoA8NRUlf1AwfqDep9s6qW2DKUQ8/kGJTD1fm0vZf8Y41bUIVBhS0p4GlgZ/8lygiJZAA7sWGoqeHaliZ5pKjll69XCFw+QPbhdYtIU2tIqi6nKJxaqVhbLo5Vn2qf4rDbv1+C/rUqJmsYVhn8CKZEA2QYaikDrEKqpGrCeRC4HIcavYNXOVGQ/0m/SdrdEEup3hItKX7vW70dMVdMiUu668j1kO5Y+S8q00FIbiW1bSYcDZUicib4rKC/M8o40s/yHt9uyv2qaUDoBLjxk6/Zf7QiHy+Baqt3d+K9EgXAk9/HLj5oT47AxtWINS6QSfxBE4bOl9dQ492CCrGF2btqT7nD/P92z7b7+uxOzLwhD4eRoVi8HMryGKt2jxhx2ffJtI3Su0AwBexBCJ4d3TOeHHoBlxvNY2Hy/wx0F+lmmeBgEHdmpD1WP+tOhKFN4oGwKcp8cA1zr5CSBk3rn8OB5bghLNzLt3xn3XKRErXKOryr5SEZ1f0c+OOrArdWx1hkeDrAYEVnmJ405LPb1zaqxWzKv3xPVyXH3YjTvrlkHK7aIPOEwB8i6W+YFUIwWcHWcZkQwo0sqE3f1yRWIQTTf25iCFOU2ZwlkHSAbWlkctdX5x6haRjsFgeEBHEgmMNiZ0qbp840bXUkEYhxMof1gNwIXBt+OCEW4tzhONIzBYDrZB9rDzyjQyJxYnBKF87tLusK6ZLSOq3AulI85G9CyOnUAaxBObK7QZ/n5wsET6z7RKEdvmzOpWmcXvwF3EhBu7m+CwkUnUtl7kZkffOHqlJcVXR+E2Oito3rF0+4um4uoIiaxfB7qB0w5NLBsKF4J+tm5TCZZwSl20jdbChDrl/7vCcInMxHOgfH05YEd+iSFsefBgJiG3pGd8g/9NKxUnbPZRzAgWVzp73mZ/VjuVh34mqMSLc4RFR+cQzB7YtUNsF/QmxLKSwVkfdF4nwf01cFhpQpq5Fg+yBecMWZ4fT7eMDUsgwUsfJuYUA+t2uGGeTODJqP4R0PWUUVfSpK/p97kRemGIjSNWjS+5f//zeE02SC1qs2ecmtdTZeKo83rv1wTdHryWkwXvkV0KpEwIkyGeSLFbltZzAk/JmYUACpnUOOdIt9Kh/g/NHT/ptPtDyP1vjdx9pzmoxOc6K0cMUWpgVftes0YgBVKdzu3OYJQZZzbwkwEacktIz9U+eq9/S/xQB6os26HisUpwIWMNlGg6OPJXSjqTboAnUDTuJW4o5M23M+rFMjcdSoJEdz1uiRtUYXDbt+SIPsm7xLPxcESxkWQJ2JziMdWYBc83EV/clPAD0xAaCcGvEINGbvPi242vZUhgb2xc47G0uW2Tm4p+pmj1Q6/KtMatboa0o4G+9aTtjyER3VG6hN2KekJHDmpwEKA9vWopBBzpvRBaoFo6hYYCLTzVE24vax2AIagCcjzc6NXGj8NC1c9bta0XAMM1JniFKYRqgIXAqa8TKvNZQksMDS1DiDfQ7hy05e8GXn6uqocM5gPIvCUXEge6lbm/7LxIF8AV5WKBz3c2UW2i2iX3J44sHQcOvfJHJv94btxKRd11ONutY4LhvJrIc/nnoRmTlyRRlKliEVu9rDRMRaN6kC+0Qkmf/mrS8Z6vDKFZiv1IPBd/z0yh90tRV0UHHY5sXt2tWEhNUzELCJWTf8GrgDn2Z2oGZcda56+NBjU4FNTp75oIPQvauzzR+yopCAtqQiHy1Fqp3/db67m9XI4SOxfxtnx0QPSFTUeuK16dv5thjYUNX5rUhDQ2dOOLMTCA+O0vF6+tc0ridDL1/2wO9Wh1m+W/ud5oqSGR4OZa0JnDCBovVlzAvb61Nk5PkXvAK2HjNzWx3EQZd5FA060ZQDmxBFZ9zMlAL+S9pMyxFeRUGHbkSVVTT2SUc5xaokZBFicsMdCO3uMIbppwCfixRUuKjV+080a4fJOog1sbW2BywAWJ69aawoyt88hyHD10MPY2+rZWElk9hif9jixPhj9udScDq93238wfjxe9NS6Wp1Eh6RI4R9/mN9d3W7quk0f+rnjvJHIGHziVMMfG0e2ePIJDoOBh+UW9ftwpai3L2wVL/vq47rJvQxmX39dg1qUNe+2bHMeVGtASjv3pvq1/NGZ5f4jRxkYwnEIOnE5Ob+53RNwoMGFZPyoGW7PoXZ7dFG9J0GTMOEoIdu5m4Ftbys3wjuPy2H8dMis3506DNKFCqk+Fp/Hd73LPL+7sI6/28SxprQAvDnPxhyYC1+yvmDR15cPYB4QdCGp9i8sFb6FwmsNxy5oLv1gMtnkvqazfPjvNpd4TL2TANiyzAilE+cG5Gu2r61/RDuThAf0LojeufVfNPLPfzbXFPLHElREPhPaLHpArf0y2NqljGF2ccG3x2AhjxLdW2DA3neryRW6ePqfKJ7E4gFDQpNpd3gRvBF4NXjO//yMLBusY6K8q46LyOLYrbBZbwNjkN/IdF5ftdMXnHA9ANZWIvwqATFAVaISIKLoHkiCNpxDhe4AuUu3WWCwxrCpBSucIUl9AvxB3GAgohUkv49DbTGQCj3/GVfUFt4hakZZHBSzYAkD1LI1FZqyaMnTUz7fTKOAhvYdqURcPaVWQDTdsV89sFQ0Ez1AMgnUryN/8lLBbRtBL0rJ0gp504AxjacllOm1X7WmMjsGjGhyfu+s6YVVpikdgjBNPHfzPh2Cn7FAHcJdJWO4ccU/FGNEPwcO+eNXqvlmKOrBVsZXKX+NRu9lEsIDPTBdsSgvzro9bckpBtC0IL3n88AAAgAElEQVSiMAVHPoLf+eyMqIITjatJm3lq0JZH+m1lR6+ejvUGyg3Iw7OJyWD6tk2Dz+Eyv1dW9/o0xRXt9d7uu18culFVhqI3usIhRdRF9YyvisXv3uqon69VWtY4n/wdqB1hQnCt7KIqqirj4LOeIXSMMSUYC7EHW0YIt+RMww+SO83JjCJ8XZ0kfr4nhB8e7b8Nx1bZZazw2xu6ufCj2ZONj869o0s6K3SLRqcaNWD7YvWZ5H82jI6/svKhgcPOzxYD90nKa33b9DEuyqHwdYoLPtYl9BjfKHZ7FH6CrQT0x6r/1+Hrm9nyTun5o82dgLO4CwxdkDG+zDgl3AjOqPoi4aDMTm/HcNCl2HHoYgw6mSyII7LZZ1BCZekq2iPmuTDlgjNAW9SJK5A64ErraUd2L9z4z6vUtXTxxO58lL9BdMeM5BnWP/ZAQDpAQ8DrBAAQaagzdRp3nsGda9BdmTp4M9n5uuuaUtiCfFF8bfwXUHJA9kHhBzB5wCDW35vtpwiDhQLwmwtbYlYWZUeQIWk6Algl74xZDW7Ap/yS2QI/OG8YVxlPBsT406DkR/ptV2aR00AzXlvb81ubSADwK34lDEsVeDReC2SxNKft/XOHYdlNBwDeQo29jsHFKpLJUoFn/XwSgVnWHt9qWnN6pl4HoI0ij3NTXPsPkjtf137vTfEsFVZThZtPCOH5FX1cw/rYONaY/m0PqguZ0RW5re/5aSS5u//bfdfwyHzC1OqNmD4RB3nYxxYPmrGnvbMTOM4yc0OH7J93SQcpVoxDZkBZMbxXPH0Aq0MnG81Iiwa+d23WGQ86a/f32qlXttp/PACcihiGswHwyn7dK/XB3jsaaPrvNNYh/HpWU4S9MPfdQg+r1RGTerTMjxrlaqlgboGV7pgx2tgzm8JOLYsCGpxhG8e63ifsIEOq73uBbLVjpxsB9CXlhpETNyU+G0qodKVdzJJAxtZfVvXh78vumgXGpb4DakDqnLzipq+s6YmfUVDij0roRXjoEDZ2fVdRcwcLAq0FwVuiiJh19V/sCLAM7iGBu+zFFewO0GcMOrXWPNDvht3IwsPAgMX11H/jy/HAv7NJSv6oIlmUETJ+0k2pOk1TCuk8C3sd9ZEHPoK7QxobnYfgYmSzEhxYflH8tGAurt/f6t7uu6bE57TwL+NXxw9A2Rd+k/wFQ0CK0IKsyK9TY3cerqIqZkDDs99OXsQO15ZH0xBlXTsHFmT268mLMI7qHGBoOHyPLEw0yhZ2CC76eEJSj1aHbCFNfo/K1bPkFjfl5GW55jmuzw5OBsMFOWWGMJ0HSvz/sbHr+xpHvkYNg85uQ80DBjH9WHPsBXsXMmNtlsiysSD08UWDth8yX9uMt8MNJ1ysZNF4DOr13DNrBFg52bYcNKITGDhux1LRuMFZHb4vO+f7yZbOIPUuHgFxgjdGr8aw2u1p7C5hYcYzxfC5kB9gOWcFur1Tpp5OxYry6ppeKCM6GwDcla8mL+mGDbWdgRON5UVbYsehIKCkl4ZvnNQhh5WGB+Rbp/ZwnMvbx6DDtjK+ffzrnyVkdmt1JLTxSVVTRe9WBULA4tm1EKBmVqXSlnZTos3wXPmKPtpvG5seXQKMOzKfnHPsVMNvUmP/rFl81S7CoMP32DOromYF/QGMwKFmgNhrTAm6rxcQDiwSFVwS4mGtqFR4zsSyUOWSWmuXooHXk+2JRRPE7oT8IX8VgEjtDxgYrBJl2tTdEVykIJyMTWPN8xeOcAI4En9we8kLhdIOr8aTm6jJL61YMiHhoK5DgqtSeGeJtdIr+Rq4/oF48kOajI2f/TODNsW1LCYnCDoUntpfV/cimXNA2wMk7mPoCSceLPXvFHL0aJk/ReZW7Q3DqMG/3ljQqjp8GG755ujVd3e1/py4JCmvzXNJ/bYfrAhCshXA7BJoVR4r58A5eWZ5v1KDeDrUwOcGbwIFVsZO2ydYXT8oDS8m9SEYa/J4Fsv/3bAEc6BMIQvS97uioaaYnuniIFuHf09aBkSrlhzuDjWCtarCrEiEliJEnaqZ5YgsLQNDMp7J5HcGoA/5unfYIdx2m2/uU3rWt/iUH+aPLQU7mxvjclhR1BSxz9h7vCmoy4KsCGfD/sPALQDxUc1L9IniTMw3PnKLxohhWWePg/TGluhfWxMYvzNuCXRP4Gm2dOp22MTvd8c8unAQIzcdAELnr45cS/xDfcqatCQ3/MF5Q6EGqSPXd8h9fdTasIBSbCtMWdB2xeNkzwTbCpqQSnBr6nf2kb5bqaZCvEee3RaEd7wp8BHl8W7vlEFX6stReqYBSnC7Dzf/46AUfeRcyLv7bFsCgo5Fpxqs3NtGHxIfXYRBZ0Kx0VR/PnNcNAD4avBiK5qWS4l7ToNfCMkaNBxJAP01QASkaBFrQE0b/r4qi4xbaqkn9HCWDbYCQp3U+oIYo1jkcG/Al2UM2vdWLFq58MEhQeKuojaOvVOUcOHqaHgfSxEHrYn+1FPWhA9BKmAlwgVkicKyo8IoJ6uueEbPsI8kbW3/ysofZUg8YPsRsgdiiWX+r9LG9/6zScvYmGOn+PZRBuy73TGfbOmkWCi8mOigYlAOrA+bZX7qWw6E4ArVdDKwLMCXykfmWrb5/96agH+nqq/RPz/XPw/bCB1CfoflcM4aPp/UB9dJGXSGERpw8rd9Un/da4dyshgqPxgd6MBYwHwnrmjK0aaSJ3mn6mR8apYrF4C7s0fDmkCtG91+n+HLKr9Y7XwfbBAMnyU5bV5a1Yfq9c46sTuOL/lgr1QrylRuQRUdVF0np/Msc9LbEV8F11JcexAMkipVKJWusG15xU0wYY54PV45qwWguRaQEPYn2xrWCXF+syJnpUUSEaG+oF89696C3jDQ8HzYuLDrMh0/HjRLGtFatd7w5JsLQm6dPta0wBCvkkwrXqv+dJjs38wfYsw/ILz8yYTl7P6I7jKBpBdBTueXx9uE3Q+ewyaABY8aLAPaFKI7ZBsVRt0KHGn2UmSC1Ed8Mx9ZlAi/86E+4DzWpBbcc56aGIz+beFJEeXHc2dj5/ikF2PQtd4w0xBdgF9QWUG2kPQiI5Kr3xCHF8uIm6zn1EBY7HynZB7VqGHNj+6RwkPI3kKXhM7IWiJpRBTkVPOiZQNZm/6VNbuH9uMz+8DsmCxO2hKFfZQILT1riuo474odj9HnoKwW9QTiwLWv4wZSlD5HithZHwpiaGdLp5uvYmvOBEPw+vfEpSjBKreXLeqD84fiH9Xu3IPRs78mZiXfJ5SKzvvOSmuPfJWOpAP7gIr0CjsMPRkrLz/+eUNwS9UwMEY45i8M2Tg5LhttXs3mWyDV6IwL/gneggQg+wbHkf/n+qWTO+aonz02gnSYr3bUWHktNvg4E0WgssKj0u5UXi6SubMzIudltgOnwkl0HICzIw/0SqX+n85eh0CJyIF6Efyudh0Owks14kj4mJ9dvywxvNDmwsvdCV08uiiRMrDGu/xl2Mbf9CYgYf15sh4gM0D+FIjH59s7Ysjgn0APvTUhI7r5Ccm519xeQoiIEHBTZ3EFSKXoMSjUheWE13fdlzcIHufQ7uic/uqI9URf1ScHSxs/umggIWjjiRGBJWOi950574Mb8dSgFGyu2jRgfwnJ3DVzFFvDPwxMGRW1X2epcjmfAt2cPl+f+AdfFVYFHQVCPmjCNxNv75zxm947QvzJiJSHwsozsQra4nKsOQvkC0l9eGUOo5YDF23Q9V4RqCo7LEoAwhwnycUaTNfsIFUXWouTTv1MPS4KJgBXupUDW5NvN643VEigEowjWZQYTRTYi3PFcUbXEFFcPY3T9Jnq8qCy7OqOYuh5XMD3EEvksEryWCxyTMgl5eqggYNoAZOmN0IaCKO7rnZUl3N1ae71ycTlNwBlauQNqAtwLWAv1O6tbk3InDo4Geqb1WWQqFcEzqCuvU6lYGAZArBQubk1v/CXVvVi+2/9Xlgs7YNOPNF/C7tphXiAG/CTxqGzItrl5CuF3v7jGBYku5GTgvTZJKlVrS7kx/zEkoEEUd14wJW/mEFJJmVw1eX81Ah+/nNTV6qmubFxYWxU7ATaMhosesZWHi0TRv/f1va0K37E0ktKKlwgPXoMPwQnnT/6ExE9/tvItaQjWQdp8YGN9+3OGHYASbmtyWLVz1RkxFvjM5SYD/Zx/4km5FgR1zWdHwqYgIwpcg5ryep9YbA2gS/sToYX+MKQDeNj9lp9+XILMN0N301UGzLjyawlMNOx/pA49VKrmGw04gmicFzTerOma/HlwYiDk7C3Y+X+da+dd3ZOI79MLdV89PbGrn9d3Rs5aNilQO3K4WSV4kulu+fMJ9VuXSjy155B1x8U9AOH/Vi6wCBs/DHuTUKF0IKTju6unluEoUERECYGgABoyWnMN9bQV/4ChA1UIlKLGluRJ+Pvpo6/6XurOKitcUaHXSbJupepcFU4yI3U1kE8cT5xOKeKG1X+mA5ZrogcgGJDMmEqSg8LlV7ySIMsFPcgL7QW81rVzZlbws6iq641HgQJHcp0XNUNWhueGht/DcooB1SZlxnxXFJ/uySXi5yD8bF5Lw9bH938uPZ1Erz4+12x72zqAm6r90zmJGRzBThAmvx+d+yv5w3VP8WIQGaH7adlhcjrATzBNdPzXED5/7mx6z8ri9CSM/Ls4E2AuVbpFfba+aFwbNx4OkwPdR6GtSswGnTY0+8nd562K9YIwtZorsAZnhm8mRxFo+MP6wMU5eXVvUwFx2/rlPmXoRtaNSlT/iwL24sre0MHUmMAbKHwN4iKTqPcdyJg/DcTAWdMBzawbSGLSucQZFxltcXmgor8bsFgWB+O5wPxfzxheUywVIzjFeD4k/ZFqVi7M8dG70WQkk2VOg5EznoD0uXYobxIHwvfwOeHbNLjw6zKTyxODAkoU/FhdRVGqLDU/6PNneltaLv8hJbFUFkEorE2n/SjgbBZZqZFEa1BPSIiUO7O42DQ/SWpTZ6OTmCmAxO50O25BAbd+NwYYkAYzCXQMyAJGlJkz+sWFsiifmPxxxUkLZOsXVxhgo19mf1dDLTtOH9n/eBeKI+LXdMgEUBwnHrOkThtuJCy4cJDuMSechf573mByAHiwaC5CmsLWoLCuFKDoU9AHtxenkL9mq131O9qNip1jDMZDEac5UE9oGxW0ONtJPdlqIDyfApVnAETtoUX5NdcxulekxzUpRUGHWJop1uFd3RVN/IPnxggBAAd6yw52/Dt9V3f3NCdzWltPTo8PHIsoT2oDtnRz0mPfHhR4lED0RBzP23KQqBq3DpuTfT1L6t6K5kwrPaAtoWkNQ1vtx9Mhk44gRwobBl9KqeeIyAAsD6MafEoE/x99BoIi+q+eL5Lsl0RHF0/LxE87K/uGucWNUVVZmZae5gSri908SnGFOOrE+TVmWA4GEoKMTteyBrG6vtIv23Kp+Y3BT/k3eQuLGbsWjgfMwfewpZIxVqPnPKfurzfV05gcc4n6P1o/63ETvX6FaBSD8wdBr/e8e5hASdJcE2sqC/qsyKvNZk7dmGDm+MzXxi6CcI7PQCIA80/tGAICWWOHXKEndP741aiKaSQE74baFUuzA5/on8KY9PBJSIK7yd3Ivjx6YQVhLgrd0X0uD7Q//NJfVkC2cS8Pz5Jl/oyBM/JSvX9cEtn4uemI1EHL7FBN94Zi5m9RDAZHUaXTzWfp5pNmUh8T5WkylXYaw6yFVDINYWnRam8VMwiyIyoLWpKh/j7mHL4LaZEbDYE5D1hEDGvCDG2G2xl04PRS88+FtSvoF1KfBUCj1bBQ5YcJf51yrYgaTsJGVi1H0eeXruKIC1WnrvDsUFYmHHiXHM7Bi9km1bmw7abNOTMKDDNJdKtj+iUdb+nmvN6RZ9GvoyUa/C31gDjFwXEjEE5dNKlFkVNnhntbzzlHjYAGr8J7vMzy/rnG+quEW98YcimhJZk6MgXAI/yj8sGks3I38HWkbICZ2/oy/eGyF49XPvvd0fzawfS1UYul+B2UbzY6DACN380YYXmrKkvFeuEpJXitNZk+NZzIXeSv45XyLcDP/EfG7rBX3ajH+MlUCEndcg1eFWyVgGL3zd7eFaRSTItG6mHeu94rH8KqsL0w3TkHm+Kmg1RRNUtwgb0CUlUmUJg5f+ZNYLKyy7GifDvt1MWUq9DOhT9Bj+il6aoC6/mvXFJaMHrqxrEbTD3HyvT4e/usudPiVtUOSeWmbSjQRpvSl6lY8M6vzZiHTtF9RGxd3Zv7DNww3VrzndyVV7YbxYMO1bm9+nEZWz4dF8DwCf1cDCjhe1D1IFOeN2cQ6FXXpOx8bXZfij4l3OGm2Yp62fWoUHnnsACQl7k4a1fUDE9Ct+Q4fN3zVAam7J3+NqwBkn9B6zAZOPsi6CKZrkwtQLOaCz4+JvkU7smBJhCOQcwB0MP+GOEO4Dj9623FGzUTD8KLY0FpqAykV3LXSEjx8Rjbdv0k8Idqv4GR4D7uRaMhYWqOFvWBlFkrPwU9t25+LeqXt1CyoMotWFMfKtugtXgwkONd2ySslti2TNTgtL6ZCLGgEDxNdCwpO+PS4LHoj2rUOU+Ten0YlJvQkm19fRQFP4wYAvMa5ATvnGApPwIb58+Ws/Xb9m4DEbgayPX2YptWgpLAlCVQVuDMQCk4nPpGiynztVHv+W9TZ1Jmfld3+1RgccxczhiUOMJDxpdy/bNj39+w9KuoapKtdjKn9IjyVYHn6npo3ELZLkwvsrKMIZX1/TAQ69pP3bnE1og+1SPXvIpEAFKJnrWqGP/v+q566mBm1s2xv5aK8Ei1avrxuCbA16FNeFtyk8ICd/fza/IfXfsjSOk6nxx42KluMk/ITX+buEQ0iZNTybk+PKwDbwv9Snz8O6mzipzRz8f0veTA7cQF+EIYyAiQqoaHRpJqOpk3HNUegCRdGFe8JY31vdAqgENL2WQebWZx5rDelJrDLTOV4avJ4LK0k5+MqlVsKGOVo5FGyWO9VGhKLAgKxxlC9fVSuvWoBMvRUAREyyOJHOl6SbinyqOChAEyAP+NeZJIA6tYcTDqfmQIO62Y8PfR/NLVgiLiPdiizG1jg2MPnOBqH1hheMmCzVbbyAwfARtRi0kICEdbxAH2dhwlrf9nwR7aawcsRMs4QMcb2I9QuAXLBv9Gaj3yqzzX1mWlP/u9LrKH2jni3XWwgCwM7kv/juIUECYRhY6K1wa9hP8/eA2rdKIJtKrGsAOz4gk+tUeEeVxCSJhScFe+DszjVwi5vK7XbHs5as519U5DRPwyYQVCIkoeAGrAd5N0E9dix1nGK+OWKdiWRzEs/toC9Xf48kqhNzyOoxmm8YhIyTPc15GxI0dc55K3KLIM1zCdhv33KijTZyN+NhNNq1HbOX03dEw21zklDt7Fhzz+XfMQW5QnYC7R5iR5Bdn51fzOFEByIs60YWrCK6S40OgVclVOvYDBfNDw/KGD46HrowdYiYAUw/22umnCSSwJJPFw4QcLDXPoVWdo2j//viVqCGqnzB1Of6+vudb680D4yyroGc6DRTf+cc90cRRjVEERAKeTsSga3sIi8+eI81Ivl9oxpeHx0L8tl/bQ2qPohB89D7fGr0KcostAO77SUoC+wA1WkKghEYI+davd54Qtykazuq77n9+AMQTL9fWWM5Z7O+eOcqFxg7n1q1Bx/qgnI4jeXyvxAnBeREMaNDISmdEaxdOC0D2zmlSk1M1EO2Ok5xiwVmLxHFWhiwoWkyYYxUkPk2faylIFjwEs8hplDM11lA+liGdYNmxiSwqcTdWFrMtF44NN1LLBnsFdK8iR4jBNW1qk8ElkOUllmtz1QHiybFS/B9GIsYa6gtdmPrydO7kuPW+fNO0tZDT2BlYo7i2AbEFAX1CzfEaaKj6fTpRlP+U74kSy+vrepI0iKWoxafHZM+6bV6/1taNMIZg2s5KYU88REoo3BxnJbrw2olfTd8TjakKbHj21ZHruuNoa4xj/HokyJMLQiZ2ECUmpB9te3OpFPGnZf3mZVY4JfT5yx67VcBN4exYHxdq7C4eeeGds/Xxw/FYsx/0Zhi0EBeXVPkRy9gH45J0eh/nE5eGWIkhdiY3lhheAHnRtqOyHCptdP+8YUtzBPJmVb6ne9rDfbeRbX+hvPzEGb/5meG4z6ZWzzi2ebfPgWyjppG16t9b40lZcjZ4HPAn0ApW4u9aiY+fTR9jRLGQY0PfRu3GeJxpu2MfXpCIdrxjh7A2H+y1Q2m98WoPlfo/vVxkh0HSHumX0loL/BaWBrywUpISHC93doRspjevWzMxNseWVCwn8vZZzu+bM9zZVep43Rp0GZcW2IXrgtesNNMVWIFJUkgIxxENV+WkMV5gwdSwN5WIwVxu/a/QGWmcGdJFznRsQOQEY8lrVbYVpzV+itT00RuuNwxuYBzuwqKCIo2x8gZ7BRTMOUFB/1yOrURZDHTbtHEay5WECs5KXaRmUdpC4iP4yckjcpBwKxsFlIEZeclBOYJpVrFT68ZFexyavhiY3sjpQcTZW1k6TLwojXWnnXvcB9CBkToZKKirNdgo/m9mhGmSjtujx+zCBydPRPVArOzTrQkQyIwdQlNDrYWkcHUQo0mwC0cV64+vzRYegw47Df0Q4A70mFD0Rf+PAAC54OoSfrTszdleQFVWR5ATQBpMLypPiQxMhoscdxcPSGkn6ijprGfyQhdkRyAh60zExkVX+kdsO76bsoAUWd27AXNAXhhoiGcx7QFpGqKIqmQzJxDDRMeGlHf+DrSNJuK93XZT9Ung13KfItkJCanRWf4nV8Fdoapnt1ZWGjh+/RfbXdVEJSj6+fVL9PwmfHO0InTxdxxzNHl+12ebllLgQxIZCBIgnuOzgN1/dv1SvhjqIyw+Xjz7JyZ26pBkgHilOQGSBo/WMXnKsUP9CIT9pxM3U4xbZytqH/nwrb79R4OEqlkXdW7QzQZR6RgK4zu+tJY8xtJFDXdaHhNwJuW/mhy51sDQ426wFrsw9shpICrEYxVHm6pAYCbG+tQku2Lx1UqDTe9yRyUMnZXm8B5L2kyNQV8ulhe9GsTZcdUdG8j+ga3C2oRIw43YCkBicWwsV9TCxuizJtFYyaRKX7jsXVjPAP3hveB9M3LxvrXkKXOHvXLXsjD4Sr09fHNWrCtFiMZxfmpyBLDys0krKO2oLuL3M+br611LNdWke+u5iKd/f/PCeJv2LLLmyIDo+2h1kgp+QqO2FSa1brPw3XTbxn6ZokUkJakidqxGZLtMjM1TYTrgWjz0xTkROkpOrjyYBkWClLMGDfnl1b1R4HPjEdAneHfcKp0+QQ/QUd7e0N3IAXejW7zdJwYg4qghzuVSBfDxJYl24mXGblnw3rpuFXEFSe4ViKYBIUdQGnUOcWA+jWuhERC0DmemR0FDNAVwcPMRfpgSl4lt1TNUqcRNbODN9U7DA3xVvrpxSayNO6TKOr+2pqdeUwJz/ECPVFL2GQD+PlK9QGGO2blfTl48PlqeQo2cN0vkAOvPFuS1Ueuh/KvjLDBfp8Y8VEN0i5wG2D5tmiJ7UNFW5LW5Ydp442Q6/t3zDDpRypT/CBWdhvUE38BlNm2Y4G1fVORG4ukn3CzK7I4NH5yYIUq/2DvCqnb0j0M7ZU+gcBtQIGrjBVbmPKE2DiyuymFjNEkaIi4KbcaxsQ/Y+Z2Yfmw0dp/BO1pVzPTBVEvmfKs1pxP6xATTLRQabD2QPQ/OzoBORN4A7b5FBuEtAg++mvOOlbd58fRANJjKSkHtJfDbuJWb1ewcn8jjj+D8LrzjJ4i9ygRgIGBA6waitoY/OKIQgkRUM2u2C79z3C5IKQRIjbcgdZCw3o0ds3UWnf4pb+zU+fpA6h9vTiDRH7K2+gg5ctyxTiFF+IPInqze23pJTluqeh491QgH7ab4LHLQKXegTsZqIJmCSox+efUfEEoltEWyXpuJqRIzBNeFwaBL46ITMl84mXigs+1i26YlsLCHRxbgrQPuo7uAgrFR6MaxcwQA4BqqqCM9v7a2B5QbdRocTej8jFNnAaYdafbwoiHr94fq/bC2sf4hVwuycXNcRkjAKWSb1J6W90K6EKiUYow43poj6Jv/bdTagQLRyOcYdIIuX+yI04Mu4EjPJCaT/WRj7wiMzgpB9eesoqZIDqC/Pz4mj/CmrgbBbxju410zR8JuJEqPPCfTou7ORKMddssPY9hdmY7H2cHnhmxkr6A76cz/l6kdAeucna+Oe55BRycL4yscQaSyGouAFxwP04b3ip8LXU8hyOAYEYmW9iNNzsUcU/hUBVrRbY8ZV0m9vXivlHBTBHk8dAKe2GKjFBdDInAqKBBoRqgleqylRUeTuzAMkHpEsliTsMX4yKTCOuqosFEgMpy9rMLp5jGjRgiM46xtes9yolDO50xuTcoSdT/YBLDGICXGmMFYCJC6lqR31vmVf3zBHbMpSaN+n4AhiDTBATf16dx+VoACckE1/VLp4+x5xMTjiIs66mngY6LFwa9at+mEO4iRHitrODczElmC9fmhxrGB1aLT/asekhuFkC8rBMJegCrUgeNGwDiwIZECViMHeWDzDsveBdFFzYNjWiM9oPqEKA3grMYaFI2U5MKW7OKNhHp9ivA9EScIDywFC0aqF8/X2eyBR4+PySXiyjKDSjvp/sAOzk6GX4hbDcRM1n69euVHTjbiZRnL18FDfaDnTlvhb4my/m1dT3JZMbiseQAsaBYSMITcQkzSWKsEaGtLYQgS5+TxOrs7x/HQYS6SNYpTz4DhRL62pgfOr34JWDxhdiieOmeJ+7K+JuWFzcuIhHRIwBMhXJ3bg8lmv0WSJ4XF6QS55j8P29C3NS6p1XlnX8Xaz9pZI+YV6sGL75xlGIMFpZ03nO881Pg9z6BD2EDaG6CZnw7FnXv9ShiBzhoh1oz51roZnA8lMSbh+q8AAA6QSURBVHqMfSk47Dj2GlxFNWxilzsl+qo3PH2S5pEUFxa5VuoT+iO8Gr1BWdkzXQw6jjCYPoiNaTVnUHJl0NUCA90wZkwlbEfvEM577nIbZ5w+YywJU5yqORZskuEpyQTccOIEqlIrw2bVNlIwK0Z8Df0NHaWPJiSNjtqrTC2///c2dfmrKGeZY7huT40iqKkfGL/MT7ckoDxlqr4CKQ0Gy+DwAixd0Wk/vHIqhOHB4beasuNBDAjEBTY8gwPOyYtzwnEGWZkYas9Wh6idRmYTPik2+kBpYzS8EBUxfTrNlJcrn44RAkKzltg9L+vNO2NXIVyuzA02Pbc48M313b7YUclHQUqhdcBJJH8PlAbsP9GYdC27uh+O06hCo6BGjh8Zj0Q3L36433bEWCKaljBRqPg+tbQ/bjXoCqdhTIkrQJm3Bi0h91l84P9gzUnsJDrKLodtEFsWJkQnenMh05VZFPhBchcioq4HwKfUREX5i1UBF5v47cLsdnbrH0vFO2NXdxOlBKtRVrdAxgeGoi5jq92IjNNGhCJQelDbteBGp0i2erB3qoi1aVsHHmHbweBfzx0KC7PKseknkC2FD6Ey0TjIG0fH5uGFiQYAz6QzzzPoVMxAlRdcggYAIni3c8SQKOLW/0iZZtkQ+girD1aiMaRJJ9Bm8NDh9imBXHg1OPJKKFyfEIK0u3/Q+OMXBLJQYU/rp5qopJ6EibnnU1x4xwY8Qnk5RVfnU3YMQECmgydTCballUoPhjNU4gSsFqYtP1lOVhC/BBVGyB9vs80AXicsF9xD7ZdjQRvkzhmjkUap9Rkiv5H8IKUEQugP2wExsUZqVs6GhPEi0Tyk8Wn8PvJKqCSJ8irogTr/zdFrYE8DUED8YHl4Z0O3txzEajBt2HHNfMtfMENcjo1zNOh43P+4btWwyHydOs1dANORtfoqtSN4MSvWiMj9BGxZe3hMZG9rly/EBJIOijmGF8TfgX1QMcNY60vU6PZUAtnYIahY5dAaJg1VSJFDYYRGU84JwN8U4fthd8y0XdFQy53Ns/E4kA5cmno+F5goxmB3CbsT1hVWZRbUYH8CXRVmXZ3JXMsMl7PYNITLRCjbKIZDYhGwG8gS4nFqReUWJLtRUaQ6Y1PnoCgAOUp/TYwg7UhzQuIqgOysH88z6Ji51G+E9C3fz3qCt1AKA+No2opyLHtmWPFlftDUHQXlACU3NvL4Aaz5L+4tJEiQkBbsjCp7LsDo8FhE8wsZFo2KrkdNYSviI+vAjsLQAccdXWMWAys/UmPykArU+wHz7QUbi13Trfg4/bTDoA83fT4BVcjGKtxsOad9q8Sgj3R6snkXV/lRagmRWKSqlPGlJ/WO+JXOEK/Fhwf9gM0m9RZ8BAd4ZNFgqNy12L+zroiaIjyrNvj8JvaeaHr3zJFKyhGFFlULFIgDC0WaIsq9HOSLgkN9waKFHR0a6UUoZMXAJLG5n5yFedqwP3RGWnso0uAnGE3sO5zC5XltXODRDn3XwgGI+cjX3BKfOSD8oC7fqPerOW4VjWWAPQEv4tU1PVntauH2hi4Q/yJFiFJHuvCW/iFsd8ijaNOzd9lU0BJtd7tbs0LPum1+hyBRNqfxImAuUfjip4xIdPmrwywaG7MXXTYVaVCds34QuUEmwYUb4XkGnbFTfAfmn2qYYDRJSKIxbeQK4c6Lq6t9c0GTVd6Q0dsFbMlZYi1CRNgQGMRR25ZaevxRUAlkSoTaAUxU4yChTkASoHYCp2DrwPRtzCqtYHyptFeYrG0XLLJRYDB28VXVp8BKP1mDouRSUSgOgqNjI0jAxkJR4FWfbFm4O9Wlvc02A3h55McjqKS8Nn7hoNt4Q1Xu/Ws6hUGNzoCNciOyh/KONyXZBCmlmnbixvlsCx7vD2/aKqjNA+K/Q5VZnB0BFk/wACwYpQEIM8AsFN+A6gd8YRettbsvJAoimSSs2+J+8jmwQ9m5BqwHuJPk4iPzwqcomcAoN10Y3HiWal5Cau6Y9nkAF11Djjb1E7TaOE6tEx9Gy1RkIKKwKwZ5elNZ82rezsVpLG8Qje7rvou58mWJLJd0J6w5cQLSel0YVkLEb4xaQxEMA2jjc/YCw0aHqxmbCfSKoUgCIimxeMcxsJf6dMIy+PVqSVAnrN4bNvn78Ur3xvESmRfLiJdMP7hsB7HOEEV0gw5eDGrsmNCvxodPDXyBfcTa8tyc1mGCxAyNLX+TBllovwc8fYKKYT3to5okr6bNskZN5Y63VRh0uYwExAKBU5AQoB/MNOc40hbBf0BmCHgqyUP/5pLoZCqPtX+9RFkVZ5EIAURJ09PoUERxF1jxFgZC2hR3Nw3JVnrma+gf5P5h0JFbwaCrjTBwMHTgSzEFuGxI9VLbd/3+ECKcNeUtuDcksuS/nrywV9ghY4Y9wALlpxH/wlXHxMQGFcHUXJobAd4N1YQ0cdOgqHEAsDU+nrACRFsFUfWPVIo5ZfYorSAolpmP796D1Ogq1mmKkyAPCfQBaxM7yB6CpYsh8XdNq/ICObdfbO/wcUpnZ1qMNbqji5PRUCOISu0kyl4j7YKizpKccBdWVXX1yx47qWoC4VUDwSq6Z/z0sCCrXXhgCfllC7PaOdNHmxyX88G4FTojky648I4ZJjLLeu+eZ9Axc6AfMAVxjQlgIpUFvuGiYWHhrYsqr0Xc5y632xtHUngIKkJXx85yMlOLCLtUTzbEWrkXBh3ghQgqXjAW1tGLh+sC8MLlQPB2gjBqeOD+OSssGGsceZLvOQf8x3Qp2rfGkrnIusagVQDUDj5j2nDP6VDxc+iTnUr06GoV1zbt7Wo8iCr322NWDbCJGVEv9KllA3HSa/1ZSfon4QXyH1AmTmuVv+daHACwEmlBCDbprGetc/FS2StgxGGXI4T7454Y8nRMY6Gmg7k5LnN09D6YgtAx6ZkFo+SM7+bCkH+nJBCYNb2kjg/C9ADQZ+05cbrhuQtSNhpDj19MdJH1u/SML54ylrGOR1X9241uv5/YJvlo5AqxGCizzr4KsXiCE9TVAoehegYrk2mf0IHeG5tkqFaKYEMs0mOmJ6uDnmfQSavJWiDJmRhf6N6Ay4ASLhpmGswda0vDeiLn4ohyYNAhOIqzoUFwyJTDhjQK1WKCERvI0vTEg6MF03AEebDXLBtIyoDRm6aJArkApKiRcBeohNHXmRtfa5QVTTEfodMwZtMOJf9oteXwTkk1kuYjyjYwcKiB5222GYCogG4tPHEFufDb+Gxrguvqw25PnuYjS7zR7R7cvpCtN0WRCGZKWQz5Hss3GWwkt7gJZn367hiId1sK8dYrB4eqcT8mELiGzEmejggEgEDtJtlWYwiuTgHraAbFprweZPDYoBPIvFBpE1gJogtbE0faqKu+LtNnYU1Kb43PIpkZchHfT+AsEeQq80PIisknoussqwD609TBm1gP/Hwv4ECAvCPOBWPKxXN4nkGH+QcTEcYINg5fGAaIs4ioeiw8eow1bix2X8Rvh5hIioOPQxPEDYcVTsU4urWT36IrUjRBe0A5MJrA37jDjo01hj8MzNT+QpLZ/qVVioBrAfQJ5xo1BvQOde1yDLozxQJOBncCbyGcSyYRUQHSjuiNP6aai46jvWaOEDb8Rdc0VWwe5t/s9EjyxbFuV9kEwAzp0/ogGTFUh2jke+5ImT/+HRYN+BjBENcifFfZVFyJj0MUhNKyUI+qvwhBcUGogBRfNJZB2L7Y3pEKU66f3cMMOtYZJ5fseWV82/azxFaR6ipkxKNpgnGLKAp4yGATlAPVFJB0RLjwbcN6W4JjzCwymXzFougCOE6GjutVxHRSkeeFcqN76GwUkCJwhG7YDZDlBNSOtAvCZOh8OVPRIrsKMQCAIMg8oC6AM7jzbQdYlV5Mx3DtHcRjfXHoxnu6pancQtxViva+sqb3yr1h195keJ/4Wp8BDzPoBDnT51mgosvGsZ4lvL/kTzrDl9W7I53nWLYYcQwxbjUZ+XYQDbxDYp7kZ+LYElQkngmX3I62qLrC++ZkeISO+frV+Z5wOfzC3JWCoaPaiOWF8+7YMNMASuwqUGjhTOG8OxfjxaALjeeIPB2QEfsP4CDTtCbHG10bRwhUvnXdmpFR1nr2ZB6SKfpVagc36rRdGxPmfcqreQY8zKAr/IRUGuwvCrdk0FB01LV55RKAb9SsnPnU+LZKSAA76Oyc2nrF3AuOI6gRIr0EAExFIrHLoChH90hhDQw6qa2te5twZtSQQPaprQEchKdPtJZu+XOpn6K2ZqNO+iFkNDVx0x1dREdQ4w+Eoa+taNp1cn/vTbwz4EEz4EkGHWtIdQiS/rG/eMokxAfHmmEjHjR99kNhaWHHgE1vHCq4jWmBUNAk0UYvlqQhMCIwfccArN4vcwKPHopOaDcJ9sLMMVLs7W9/jf6b4gaTO2ZRwvHMhXoU6EIKNUdqCtc4PHiNTp/3sa+iGfAkgw5kAbZA4QvKOuONEngE8nZMyPTk2cegsxrhmIPqOLO8xF2LsiS4ynJlWuO00gPizudbTh8T3MlZqNaTJ6RuxwY5jMy6snO+aJ7U7Z29d/POgEfMgEcZ9POW00XCM8EgSoQTQDzwCjPovFMccKGbunQPlShu1dZc+4pAnmGRYCpcQ08e8XXyDsI7A94ZuJwz4EkGnXkAYeAPWAQ2HQwdyMKZn3s5J63u722nYFH3A/De0TsD3hm4AmbAwww6EU6ILrDF8UaBXLzW/Ar4CnmH6J0B7wx4ygx4mEFnWiSfEz4fSUBoWroELjxlDr3j8M6Adwa8M+ARM+B5Bl1NCwYda660DzxioryD8M6Adwa8M+DpM+CpBt3T5807Pu8MeGfAOwMeNwNeg+5xr8Q7IO8MeGfAOwPuzYDXoLs3b96rvDPgnQHvDHjcDHgNuse9Eu+AvDPgnQHvDLg3A16D7t68ea/yzoB3Brwz4HEz4DXoHvdKvAPyzoB3Brwz4N4M/D/7dRlr8OerHwAAAABJRU5ErkJggg=="="OpenRAM"></a><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">sram_2_16_scn4m_subm.html</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Compiled at: 2019-01-03 13:39:31.087652</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">DRC: skipped</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">LVS: skipped</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Git commit id: 55b01255ef603a3e2b5c8630974818d79a2e8d96</p><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p><table id="data">
-<thead><tr><th>Type</th><th>Description</th></tr></thead>
-<tbody>
-<tr><td>WORD_SIZE</td><td>2</td></tr>
-<tr><td>NUM_WORDS</td><td>16</td></tr>
-<tr><td>NUM_BANKS</td><td>1</td></tr>
-<tr><td>NUM_RW_PORTS</td><td>1</td></tr>
-<tr><td>NUM_R_PORTS</td><td>0</td></tr>
-<tr><td>NUM_W_PORTS</td><td>0</td></tr>
-<tr><td>Area</td><td>0</td></tr>
-</tbody>
-</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p><table id="data">
-<thead><tr><th>Parameter</th><th>Min</th><th>Typ</th><th>Max</th><th>Units</th></tr></thead>
-<tbody>
-<tr><td>Power supply (VDD) range</td><td>5.0</td><td>5.0</td><td>5.0</td><td>Volts</td></tr>
-<tr><td>Operating Temperature</td><td>25</td><td>25</td><td>25</td><td>Celsius</td></tr>
-<tr><td>Operating Frequency (F)</td><td></td><td></td><td>not available in netlist only</td><td>MHz</td></tr>
-</tbody>
-</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing and Current Data</p><table id="data">
-<thead><tr><th>Parameter</th><th>Min</th><th>Max</th><th>Units</th></tr></thead>
-<tbody>
-<tr><td>DIN0[1:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>DIN0[1:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>DIN0[1:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DIN0[1:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] cell rise</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] cell fall</td><td>0.079</td><td>0.079</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] rise transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>DOUT0[1:0] fall transition</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>CSb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>CSb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>ADDR0[3:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>WEb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>WEb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr>
-<tr><td>WEb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-<tr><td>WEb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr>
-</tbody>
-</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p><table id="data">
-<thead><tr><th>Corner Name</th><th>Process</th><th>Power Supply</th><th>Temperature</th><th>Library Name Suffix</th></tr></thead>
-<tbody>
-<tr><td>TT</td><td>Typical - Typical</td><td>5.0</td><td>25</td><td>_TT_5p0V_25C.lib</td></tr>
-</tbody>
-</table><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p><table id="data">
-<thead><tr><th>Type</th><th>Description</th><th>Link</th></tr></thead>
-<tbody>
-<tr><td>.sp</td><td>SPICE netlists</td><td><a href="sram_2_16_scn4m_subm.sp">sram_2_16_scn4m_subm.sp</a></td></tr>
-<tr><td>.v</td><td>Verilog simulation models</td><td><a href="sram_2_16_scn4m_subm.v">sram_2_16_scn4m_subm.v</a></td></tr>
-<tr><td>.html</td><td>This datasheet</td><td><a href="sram_2_16_scn4m_subm.html">sram_2_16_scn4m_subm.html</a></td></tr>
-<tr><td>.lib</td><td>Synthesis models</td><td><a href="sram_2_16_scn4m_subm_TT_5p0V_25C.lib">sram_2_16_scn4m_subm_TT_5p0V_25C.lib</a></td></tr>
-<tr><td>.py</td><td>OpenRAM configuration file</td><td><a href="sram_2_16_scn4m_subm.py">sram_2_16_scn4m_subm.py</a></td></tr>
-</tbody>
-</table>
\ No newline at end of file
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef
deleted file mode 100644
index c9c2b943..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.lef
+++ /dev/null
@@ -1,12857 +0,0 @@
-VERSION 5.4 ;
-NAMESCASESENSITIVE ON ;
-BUSBITCHARS "[]" ;
-DIVIDERCHAR "/" ;
-UNITS
-  DATABASE MICRONS 1000 ;
-END UNITS
-SITE  MacroSite
-   CLASS Core ;
-   SIZE 215000.0 by 336100.0 ;
-END  MacroSite
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-   END    sram_2_16_scn4m_subm
-END    LIBRARY
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.py b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.py
deleted file mode 100644
index bd4df95d..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.py
+++ /dev/null
@@ -1,18 +0,0 @@
-word_size = 2
-num_words = 16
-
-tech_name = "scn4m_subm"
-process_corners = ["TT"]
-supply_voltages = [ 5.0 ]
-temperatures = [ 25 ]
-
-output_path = "temp"
-output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
-
-#Setting for multiport
-netlist_only = True
-bitcell = "pbitcell"
-replica_bitcell="replica_pbitcell"
-num_rw_ports = 1
-num_r_ports = 0
-num_w_ports = 0
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp
deleted file mode 100644
index f5eb553a..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.sp
+++ /dev/null
@@ -1,559 +0,0 @@
-**************************************************
-* OpenRAM generated memory.
-* Words: 16
-* Data bits: 2
-* Banks: 1
-* Column mux: 1:1
-**************************************************
-*********************** "dff" ******************************
-* Positive edge-triggered FF
-.SUBCKT dff D Q clk vdd gnd
-
-* SPICE3 file created from dff.ext - technology: scmos
-
-M1000 vdd clk a_24_24# vdd p w=8u l=0.4u
-M1001 a_84_296# D vdd vdd p w=4u l=0.4u
-M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u
-M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u
-M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u
-M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u
-M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u
-M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u
-M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u
-M1009 vdd Q a_320_336# vdd p w=2u l=0.4u
-M1010 gnd clk a_24_24# gnd n w=4u l=0.4u
-M1011 Q a_280_24# vdd vdd p w=8u l=0.4u
-M1012 a_84_24# D gnd gnd n w=2u l=0.4u
-M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u
-M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u
-M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u
-M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u
-M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u
-M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u
-M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u
-M1020 gnd Q a_320_24# gnd n w=2u l=0.4u
-M1021 Q a_280_24# gnd gnd n w=4u l=0.4u
-
-.ENDS
-
-.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd
-Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff
-Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff
-Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff
-Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff
-.ENDS row_addr_dff
-
-.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd
-Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff
-Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff
-.ENDS data_dff
-
-* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-
-* ptx M{0} {1} p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
-
-* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-
-* ptx M{0} {1} n m=1 w=1.2000000000000002u l=0.4u pd=3.20u ps=3.20u as=1.20p ad=1.20p
-
-.SUBCKT pbitcell_1RW_0W_0R bl0 br0 wl0 vdd gnd
-Minverter_nmos_left Q Q_bar gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Minverter_nmos_right gnd Q Q_bar gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Minverter_pmos_left Q Q_bar vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
-Minverter_pmos_right vdd Q Q_bar vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
-Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-Mreadwrite_nmos_right0 Q_bar wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pbitcell_1RW_0W_0R
-
-.SUBCKT bitcell_array_16x2_1 bl0_0 br0_0 bl0_1 br0_1 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 vdd gnd
-Xbit_r0_c0 bl0_0 br0_0 wl0_0 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r1_c0 bl0_0 br0_0 wl0_1 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r2_c0 bl0_0 br0_0 wl0_2 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r3_c0 bl0_0 br0_0 wl0_3 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r4_c0 bl0_0 br0_0 wl0_4 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r5_c0 bl0_0 br0_0 wl0_5 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r6_c0 bl0_0 br0_0 wl0_6 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r7_c0 bl0_0 br0_0 wl0_7 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r8_c0 bl0_0 br0_0 wl0_8 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r9_c0 bl0_0 br0_0 wl0_9 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r10_c0 bl0_0 br0_0 wl0_10 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r11_c0 bl0_0 br0_0 wl0_11 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r12_c0 bl0_0 br0_0 wl0_12 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r13_c0 bl0_0 br0_0 wl0_13 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r14_c0 bl0_0 br0_0 wl0_14 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r15_c0 bl0_0 br0_0 wl0_15 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r0_c1 bl0_1 br0_1 wl0_0 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r1_c1 bl0_1 br0_1 wl0_1 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r2_c1 bl0_1 br0_1 wl0_2 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r3_c1 bl0_1 br0_1 wl0_3 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r4_c1 bl0_1 br0_1 wl0_4 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r5_c1 bl0_1 br0_1 wl0_5 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r6_c1 bl0_1 br0_1 wl0_6 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r7_c1 bl0_1 br0_1 wl0_7 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r8_c1 bl0_1 br0_1 wl0_8 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r9_c1 bl0_1 br0_1 wl0_9 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r10_c1 bl0_1 br0_1 wl0_10 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r11_c1 bl0_1 br0_1 wl0_11 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r12_c1 bl0_1 br0_1 wl0_12 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r13_c1 bl0_1 br0_1 wl0_13 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r14_c1 bl0_1 br0_1 wl0_14 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r15_c1 bl0_1 br0_1 wl0_15 vdd gnd pbitcell_1RW_0W_0R
-.ENDS bitcell_array_16x2_1
-
-* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-
-.SUBCKT precharge_1 bl br en_bar vdd
-Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS precharge_1
-
-.SUBCKT precharge_array_1 bl_0 br_0 bl_1 br_1 en_bar vdd
-Xpre_column_0 bl_0 br_0 en_bar vdd precharge_1
-Xpre_column_1 bl_1 br_1 en_bar vdd precharge_1
-.ENDS precharge_array_1
-*********************** "sense_amp" ******************************
-
-.SUBCKT sense_amp bl br dout en vdd gnd
-
-* SPICE3 file created from sense_amp.ext - technology: scmos
-
-M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u
-M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u
-M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u
-M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u
-M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u
-M1005 bl en dout vdd p w=4.8u l=0.4u
-M1006 a_48_304# en br vdd p w=4.8u l=0.4u
-
-.ENDS
-
-.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd
-Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp
-Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp
-.ENDS sense_amp_array
-*********************** Write_Driver ******************************
-.SUBCKT write_driver din bl br en vdd gnd
-
-**** Inverter to conver Data_in to data_in_bar ******
-* din_bar = inv(din)
-M_1 din_bar din gnd gnd n W=0.8u L=0.4u
-M_2 din_bar din vdd vdd p W=1.4u L=0.4u
-
-**** 2input nand gate follwed by inverter to drive BL ******
-* din_bar_gated = nand(en, din)
-M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u
-M_4 net_7 din gnd gnd n W=1.4u L=0.4u
-M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u
-M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u
-* din_bar_gated_bar = inv(din_bar_gated)
-M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u
-M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u
-
-**** 2input nand gate follwed by inverter to drive BR******
-* din_gated = nand(en, din_bar)
-M_9 din_gated en vdd vdd p W=1.4u L=0.4u
-M_10 din_gated en net_8 gnd n W=1.4u L=0.4u
-M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u
-M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u
-* din_gated_bar = inv(din_gated)
-M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u
-M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u
-
-************************************************
-* pull down with en enable
-M_15 bl din_gated_bar net_5 gnd n W=2.4u L=0.4u
-M_16 br din_bar_gated_bar net_5 gnd n W=2.4u L=0.4u
-M_17 net_5 en gnd gnd n W=2.4u L=0.4u
-
-
-
-.ENDS   $ write_driver
-
-.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd
-Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver
-Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver
-.ENDS write_driver_array
-
-* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-
-* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-
-.SUBCKT pinv_1 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_1
-
-* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-
-.SUBCKT pnand2_1 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pnand2_1
-
-.SUBCKT pnand3_1 A B C Z vdd gnd
-Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pnand3_1
-
-.SUBCKT pinv_2 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_2
-
-.SUBCKT pnand2_2 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pnand2_2
-
-.SUBCKT pre2x4_1 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd
-Xpre_inv_0 in_0 inbar_0 vdd gnd pinv_2
-Xpre_inv_1 in_1 inbar_1 vdd gnd pinv_2
-Xpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_2
-Xpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_2
-Xpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_2
-Xpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_2
-XXpre2x4_nand_0 inbar_0 inbar_1 Z_0 vdd gnd pnand2_2
-XXpre2x4_nand_1 in_0 inbar_1 Z_1 vdd gnd pnand2_2
-XXpre2x4_nand_2 inbar_0 in_1 Z_2 vdd gnd pnand2_2
-XXpre2x4_nand_3 in_0 in_1 Z_3 vdd gnd pnand2_2
-.ENDS pre2x4_1
-
-.SUBCKT pinv_3 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_3
-
-.SUBCKT pnand3_2 A B C Z vdd gnd
-Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pnand3_2
-
-.SUBCKT pre3x8_2 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd
-Xpre_inv_0 in_0 inbar_0 vdd gnd pinv_3
-Xpre_inv_1 in_1 inbar_1 vdd gnd pinv_3
-Xpre_inv_2 in_2 inbar_2 vdd gnd pinv_3
-Xpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_3
-Xpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_3
-Xpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_3
-Xpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_3
-Xpre_nand_inv_4 Z_4 out_4 vdd gnd pinv_3
-Xpre_nand_inv_5 Z_5 out_5 vdd gnd pinv_3
-Xpre_nand_inv_6 Z_6 out_6 vdd gnd pinv_3
-Xpre_nand_inv_7 Z_7 out_7 vdd gnd pinv_3
-XXpre3x8_nand_0 inbar_0 inbar_1 inbar_2 Z_0 vdd gnd pnand3_2
-XXpre3x8_nand_1 in_0 inbar_1 inbar_2 Z_1 vdd gnd pnand3_2
-XXpre3x8_nand_2 inbar_0 in_1 inbar_2 Z_2 vdd gnd pnand3_2
-XXpre3x8_nand_3 in_0 in_1 inbar_2 Z_3 vdd gnd pnand3_2
-XXpre3x8_nand_4 inbar_0 inbar_1 in_2 Z_4 vdd gnd pnand3_2
-XXpre3x8_nand_5 in_0 inbar_1 in_2 Z_5 vdd gnd pnand3_2
-XXpre3x8_nand_6 inbar_0 in_1 in_2 Z_6 vdd gnd pnand3_2
-XXpre3x8_nand_7 in_0 in_1 in_2 Z_7 vdd gnd pnand3_2
-.ENDS pre3x8_2
-
-.SUBCKT hierarchical_decoder_16rows_1 addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd
-Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd pre2x4_1
-Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd pre2x4_1
-XDEC_NAND_0 out_0 out_4 Z_0 vdd gnd pnand2_1
-XDEC_NAND_4 out_0 out_5 Z_4 vdd gnd pnand2_1
-XDEC_NAND_8 out_0 out_6 Z_8 vdd gnd pnand2_1
-XDEC_NAND_12 out_0 out_7 Z_12 vdd gnd pnand2_1
-XDEC_NAND_1 out_1 out_4 Z_1 vdd gnd pnand2_1
-XDEC_NAND_5 out_1 out_5 Z_5 vdd gnd pnand2_1
-XDEC_NAND_9 out_1 out_6 Z_9 vdd gnd pnand2_1
-XDEC_NAND_13 out_1 out_7 Z_13 vdd gnd pnand2_1
-XDEC_NAND_2 out_2 out_4 Z_2 vdd gnd pnand2_1
-XDEC_NAND_6 out_2 out_5 Z_6 vdd gnd pnand2_1
-XDEC_NAND_10 out_2 out_6 Z_10 vdd gnd pnand2_1
-XDEC_NAND_14 out_2 out_7 Z_14 vdd gnd pnand2_1
-XDEC_NAND_3 out_3 out_4 Z_3 vdd gnd pnand2_1
-XDEC_NAND_7 out_3 out_5 Z_7 vdd gnd pnand2_1
-XDEC_NAND_11 out_3 out_6 Z_11 vdd gnd pnand2_1
-XDEC_NAND_15 out_3 out_7 Z_15 vdd gnd pnand2_1
-XDEC_INV_0 Z_0 decode_0 vdd gnd pinv_1
-XDEC_INV_1 Z_1 decode_1 vdd gnd pinv_1
-XDEC_INV_2 Z_2 decode_2 vdd gnd pinv_1
-XDEC_INV_3 Z_3 decode_3 vdd gnd pinv_1
-XDEC_INV_4 Z_4 decode_4 vdd gnd pinv_1
-XDEC_INV_5 Z_5 decode_5 vdd gnd pinv_1
-XDEC_INV_6 Z_6 decode_6 vdd gnd pinv_1
-XDEC_INV_7 Z_7 decode_7 vdd gnd pinv_1
-XDEC_INV_8 Z_8 decode_8 vdd gnd pinv_1
-XDEC_INV_9 Z_9 decode_9 vdd gnd pinv_1
-XDEC_INV_10 Z_10 decode_10 vdd gnd pinv_1
-XDEC_INV_11 Z_11 decode_11 vdd gnd pinv_1
-XDEC_INV_12 Z_12 decode_12 vdd gnd pinv_1
-XDEC_INV_13 Z_13 decode_13 vdd gnd pinv_1
-XDEC_INV_14 Z_14 decode_14 vdd gnd pinv_1
-XDEC_INV_15 Z_15 decode_15 vdd gnd pinv_1
-.ENDS hierarchical_decoder_16rows_1
-
-.SUBCKT pinv_4 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_4
-
-.SUBCKT pinv_5 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_5
-
-.SUBCKT pnand2_3 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pnand2_3
-
-.SUBCKT wordline_driver in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en_bar vdd gnd
-Xwl_driver_nand0 en_bar in_0 wl_bar_0 vdd gnd pnand2_3
-Xwl_driver_inv0 wl_bar_0 wl_0 vdd gnd pinv_4
-Xwl_driver_nand1 en_bar in_1 wl_bar_1 vdd gnd pnand2_3
-Xwl_driver_inv1 wl_bar_1 wl_1 vdd gnd pinv_4
-Xwl_driver_nand2 en_bar in_2 wl_bar_2 vdd gnd pnand2_3
-Xwl_driver_inv2 wl_bar_2 wl_2 vdd gnd pinv_4
-Xwl_driver_nand3 en_bar in_3 wl_bar_3 vdd gnd pnand2_3
-Xwl_driver_inv3 wl_bar_3 wl_3 vdd gnd pinv_4
-Xwl_driver_nand4 en_bar in_4 wl_bar_4 vdd gnd pnand2_3
-Xwl_driver_inv4 wl_bar_4 wl_4 vdd gnd pinv_4
-Xwl_driver_nand5 en_bar in_5 wl_bar_5 vdd gnd pnand2_3
-Xwl_driver_inv5 wl_bar_5 wl_5 vdd gnd pinv_4
-Xwl_driver_nand6 en_bar in_6 wl_bar_6 vdd gnd pnand2_3
-Xwl_driver_inv6 wl_bar_6 wl_6 vdd gnd pinv_4
-Xwl_driver_nand7 en_bar in_7 wl_bar_7 vdd gnd pnand2_3
-Xwl_driver_inv7 wl_bar_7 wl_7 vdd gnd pinv_4
-Xwl_driver_nand8 en_bar in_8 wl_bar_8 vdd gnd pnand2_3
-Xwl_driver_inv8 wl_bar_8 wl_8 vdd gnd pinv_4
-Xwl_driver_nand9 en_bar in_9 wl_bar_9 vdd gnd pnand2_3
-Xwl_driver_inv9 wl_bar_9 wl_9 vdd gnd pinv_4
-Xwl_driver_nand10 en_bar in_10 wl_bar_10 vdd gnd pnand2_3
-Xwl_driver_inv10 wl_bar_10 wl_10 vdd gnd pinv_4
-Xwl_driver_nand11 en_bar in_11 wl_bar_11 vdd gnd pnand2_3
-Xwl_driver_inv11 wl_bar_11 wl_11 vdd gnd pinv_4
-Xwl_driver_nand12 en_bar in_12 wl_bar_12 vdd gnd pnand2_3
-Xwl_driver_inv12 wl_bar_12 wl_12 vdd gnd pinv_4
-Xwl_driver_nand13 en_bar in_13 wl_bar_13 vdd gnd pnand2_3
-Xwl_driver_inv13 wl_bar_13 wl_13 vdd gnd pinv_4
-Xwl_driver_nand14 en_bar in_14 wl_bar_14 vdd gnd pnand2_3
-Xwl_driver_inv14 wl_bar_14 wl_14 vdd gnd pinv_4
-Xwl_driver_nand15 en_bar in_15 wl_bar_15 vdd gnd pnand2_3
-Xwl_driver_inv15 wl_bar_15 wl_15 vdd gnd pinv_4
-.ENDS wordline_driver
-
-.SUBCKT pinv_6 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_6
-
-.SUBCKT bank dout0_0 dout0_1 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd
-Xbitcell_array bl0_0 br0_0 bl0_1 br0_1 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 vdd gnd bitcell_array_16x2_1
-Xprecharge_array0 bl0_0 br0_0 bl0_1 br0_1 p_en_bar0 vdd precharge_array_1
-Xsense_amp_array0 dout0_0 bl0_0 br0_0 dout0_1 bl0_1 br0_1 s_en0 vdd gnd sense_amp_array
-Xwrite_driver_array0 din0_0 din0_1 bl0_0 br0_0 bl0_1 br0_1 w_en0 vdd gnd write_driver_array
-Xrow_decoder0 addr0_0 addr0_1 addr0_2 addr0_3 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 vdd gnd hierarchical_decoder_16rows_1
-Xwordline_driver0 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 wl_en0 vdd gnd wordline_driver
-.ENDS bank
-
-* ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-
-.SUBCKT pinv_9 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pinv_9
-
-* ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-
-* ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-
-.SUBCKT pinv_10 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-.ENDS pinv_10
-
-.SUBCKT dff_buf_2 D Q Qb clk vdd gnd
-Xdff_buf_dff D qint clk vdd gnd dff
-Xdff_buf_inv1 qint Qb vdd gnd pinv_9
-Xdff_buf_inv2 Qb Q vdd gnd pinv_10
-.ENDS dff_buf_2
-
-.SUBCKT dff_buf_array_2x1_1 din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd
-Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_2
-Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_2
-.ENDS dff_buf_array_2x1_1
-
-.SUBCKT pnand2_4 A B Z vdd gnd
-Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pnand2_4
-
-.SUBCKT pinv_11 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-.ENDS pinv_11
-
-.SUBCKT pand2_4_1 A B Z vdd gnd
-Xpand2_nand A B zb_int vdd gnd pnand2_4
-Xpand2_inv zb_int Z vdd gnd pinv_11
-.ENDS pand2_4_1
-
-.SUBCKT pinv_12 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_12
-
-.SUBCKT pinv_13 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-.ENDS pinv_13
-
-.SUBCKT pbuf_4_1 A Z vdd gnd
-Xbuf_inv1 A zb_int vdd gnd pinv_12
-Xbuf_inv2 zb_int Z vdd gnd pinv_13
-.ENDS pbuf_4_1
-
-.SUBCKT pinv_14 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-.ENDS pinv_14
-
-* ptx M{0} {1} n m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
-
-* ptx M{0} {1} p m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p
-
-.SUBCKT pinv_15 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
-.ENDS pinv_15
-
-.SUBCKT pbuf_16_2 A Z vdd gnd
-Xbuf_inv1 A zb_int vdd gnd pinv_14
-Xbuf_inv2 zb_int Z vdd gnd pinv_15
-.ENDS pbuf_16_2
-
-.SUBCKT pinv_16 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
-Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-.ENDS pinv_16
-
-* ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-
-* ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
-
-.SUBCKT pinv_17 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
-Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-.ENDS pinv_17
-
-.SUBCKT pbuf_8_3 A Z vdd gnd
-Xbuf_inv1 A zb_int vdd gnd pinv_16
-Xbuf_inv2 zb_int Z vdd gnd pinv_17
-.ENDS pbuf_8_3
-
-.SUBCKT pinv_18 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_18
-
-.SUBCKT pinv_19 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
-Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
-.ENDS pinv_19
-
-.SUBCKT replica_pbitcell_1RW_0W_0R bl0 br0 wl0 vdd gnd
-Minverter_nmos_left Q vdd gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Minverter_nmos_right gnd Q vdd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Minverter_pmos_left Q vdd vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
-Minverter_pmos_right vdd Q vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
-Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-Mreadwrite_nmos_right0 vdd wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS replica_pbitcell_1RW_0W_0R
-
-.SUBCKT replica_pbitcell bl0 br0 wl0 vdd gnd
-Xpbitcell bl0 br0 wl0 vdd gnd replica_pbitcell_1RW_0W_0R
-.ENDS replica_pbitcell
-
-.SUBCKT bitcell_array_8x1_2 bl0_0 br0_0 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 vdd gnd
-Xbit_r0_c0 bl0_0 br0_0 wl0_0 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r1_c0 bl0_0 br0_0 wl0_1 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r2_c0 bl0_0 br0_0 wl0_2 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r3_c0 bl0_0 br0_0 wl0_3 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r4_c0 bl0_0 br0_0 wl0_4 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r5_c0 bl0_0 br0_0 wl0_5 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r6_c0 bl0_0 br0_0 wl0_6 vdd gnd pbitcell_1RW_0W_0R
-Xbit_r7_c0 bl0_0 br0_0 wl0_7 vdd gnd pbitcell_1RW_0W_0R
-.ENDS bitcell_array_8x1_2
-
-.SUBCKT pinv_20 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_20
-
-.SUBCKT delay_chain_1 in out vdd gnd
-Xdinv0 in dout_1 vdd gnd pinv_20
-Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_20
-Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_20
-Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_20
-Xdinv1 dout_1 dout_2 vdd gnd pinv_20
-Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_20
-Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_20
-Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_20
-Xdinv2 dout_2 dout_3 vdd gnd pinv_20
-Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_20
-Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_20
-Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_20
-Xdinv3 dout_3 out vdd gnd pinv_20
-Xdload_3_0 out n_3_0 vdd gnd pinv_20
-Xdload_3_1 out n_3_1 vdd gnd pinv_20
-Xdload_3_2 out n_3_2 vdd gnd pinv_20
-.ENDS delay_chain_1
-
-.SUBCKT pinv_21 A Z vdd gnd
-Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
-Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-.ENDS pinv_21
-
-* ptx M{0} {1} p m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-
-.SUBCKT replica_bitline_rw en out vdd gnd
-Xrbl_inv bl0_0 out vdd gnd pinv_21
-Mrbl_access_tx vdd delayed_en bl0_0 vdd p m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
-Xdelay_chain en delayed_en vdd gnd delay_chain_1
-Xbitcell bl0_0 br0_0 delayed_en vdd gnd replica_pbitcell
-Xload bl0_0 br0_0 gnd gnd gnd gnd gnd gnd gnd gnd vdd gnd bitcell_array_8x1_2
-.ENDS replica_bitline_rw
-
-.SUBCKT control_logic_rw csb web clk s_en w_en p_en_bar wl_en clk_buf vdd gnd
-Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array_2x1_1
-Xclkbuf clk clk_buf vdd gnd pbuf_4_1
-Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_18
-Xand2_gated_clk_bar cs clk_bar gated_clk_bar vdd gnd pand2_4_1
-Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2_4_1
-Xbuf_wl_en gated_clk_bar wl_en vdd gnd pbuf_16_2
-Xbuf_w_en_buf we w_en vdd gnd pbuf_8_3
-Xand2_rbl_in gated_clk_bar we_bar rbl_in vdd gnd pand2_4_1
-Xand2_pre_p_en gated_clk_buf we_bar pre_p_en vdd gnd pand2_4_1
-Xinv_p_en_bar pre_p_en p_en_bar vdd gnd pinv_19
-Xbuf_s_en pre_s_en s_en vdd gnd pbuf_8_3
-Xreplica_bitline rbl_in pre_s_en vdd gnd replica_bitline_rw
-.ENDS control_logic_rw
-
-.SUBCKT sram_2_16_scn4m_subm DIN0[0] DIN0[1] ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] csb0 web0 clk0 DOUT0[0] DOUT0[1] vdd gnd
-Xbank0 DOUT0[0] DOUT0[1] BANK_DIN0[0] BANK_DIN0[1] A0[0] A0[1] A0[2] A0[3] s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank
-Xcontrol0 csb0 web0 clk0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw
-Xrow_address0 ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] A0[0] A0[1] A0[2] A0[3] clk_buf0 vdd gnd row_addr_dff
-Xdata_dff0 DIN0[0] DIN0[1] BANK_DIN0[0] BANK_DIN0[1] clk_buf0 vdd gnd data_dff
-.ENDS sram_2_16_scn4m_subm
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.v b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.v
deleted file mode 100644
index 779fd6e9..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm.v
+++ /dev/null
@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 16
-// Word size: 2
-
-module sram_2_16_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 2 ;
-  parameter ADDR_WIDTH = 4 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_3p3V_25C.lib b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
deleted file mode 100644
index a516aa25..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
+++ /dev/null
@@ -1,321 +0,0 @@
-library (sram_2_16_scn4m_subm_TT_3p3V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 3.3 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 2;
-    bit_from : 0;
-    bit_to : 1;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 4;
-    bit_from : 0;
-    bit_to : 3;
-    }
-
-cell (sram_2_16_scn4m_subm){
-    memory(){ 
-    type : ram;
-    address_width : 4;
-    word_width : 2;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 69426.85;
-
-    leakage_power () {
-      when : "CSb0";
-      value : 0.000179;
-    }
-    cell_leakage_power : 0;
-    bus(DIN0){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR0; 
-            clocked_on  : clk0; 
-        }
-        pin(DIN0[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-    bus(DOUT0){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR0; 
-        }
-        pin(DOUT0[1:0]){
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk0"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
-            }
-        }
-        }
-    }
-
-    bus(ADDR0){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR0[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    pin(CSb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(WEb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(clk0){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb0 & clk0 & !WEb0"; 
-            rise_power(scalar){
-                values("2.46222038320038");
-            }
-            fall_power(scalar){
-                values("2.46222038320038");
-            }
-        }
-        internal_power(){
-            when : "!CSb0 & !clk0 & WEb0"; 
-            rise_power(scalar){
-                values("2.46222038320038");
-            }
-            fall_power(scalar){
-                values("2.46222038320038");
-            }
-        }
-        internal_power(){
-            when : "CSb0"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0.0"); 
-            }
-            fall_constraint(scalar) {
-                values("0.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0"); 
-            }
-            fall_constraint(scalar) {
-                values("0"); 
-            }
-         }
-    }
-
-    }
-}
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5V_25C.lib b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5V_25C.lib
deleted file mode 100644
index 18a74796..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5V_25C.lib
+++ /dev/null
@@ -1,321 +0,0 @@
-library (sram_2_16_scn4m_subm_TT_5V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 2;
-    bit_from : 0;
-    bit_to : 1;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 4;
-    bit_from : 0;
-    bit_to : 3;
-    }
-
-cell (sram_2_16_scn4m_subm){
-    memory(){ 
-    type : ram;
-    address_width : 4;
-    word_width : 2;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 68347.21;
-
-    leakage_power () {
-      when : "CSb0";
-      value : 0.000179;
-    }
-    cell_leakage_power : 0;
-    bus(DIN0){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR0; 
-            clocked_on  : clk0; 
-        }
-        pin(DIN0[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-    bus(DOUT0){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR0; 
-        }
-        pin(DOUT0[1:0]){
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk0"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
-            }
-        }
-        }
-    }
-
-    bus(ADDR0){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR0[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    pin(CSb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(WEb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(clk0){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb0 & clk0 & !WEb0"; 
-            rise_power(scalar){
-                values("2.46222038320038");
-            }
-            fall_power(scalar){
-                values("2.46222038320038");
-            }
-        }
-        internal_power(){
-            when : "!CSb0 & !clk0 & WEb0"; 
-            rise_power(scalar){
-                values("2.46222038320038");
-            }
-            fall_power(scalar){
-                values("2.46222038320038");
-            }
-        }
-        internal_power(){
-            when : "CSb0"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0.0"); 
-            }
-            fall_constraint(scalar) {
-                values("0.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0"); 
-            }
-            fall_constraint(scalar) {
-                values("0"); 
-            }
-         }
-    }
-
-    }
-}
diff --git a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib b/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
deleted file mode 100644
index e75a83e4..00000000
--- a/compiler/datasheet/server_scripts/files/test_files/contents2/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
+++ /dev/null
@@ -1,321 +0,0 @@
-library (sram_2_16_scn4m_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 2;
-    bit_from : 0;
-    bit_to : 1;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 4;
-    bit_from : 0;
-    bit_to : 3;
-    }
-
-cell (sram_2_16_scn4m_subm){
-    memory(){ 
-    type : ram;
-    address_width : 4;
-    word_width : 2;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 0;
-
-    leakage_power () {
-      when : "CSb0";
-      value : 0.000172;
-    }
-    cell_leakage_power : 0;
-    bus(DIN0){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR0; 
-            clocked_on  : clk0; 
-        }
-        pin(DIN0[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-    bus(DOUT0){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR0; 
-        }
-        pin(DOUT0[1:0]){
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk0"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079",\
-                   "0.079, 0.079, 0.079");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    bus(ADDR0){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR0[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    pin(CSb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(WEb0){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk0"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(clk0){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb0 & clk0 & !WEb0"; 
-            rise_power(scalar){
-                values("5.193773500000001");
-            }
-            fall_power(scalar){
-                values("5.193773500000001");
-            }
-        }
-        internal_power(){
-            when : "!CSb0 & !clk0 & WEb0"; 
-            rise_power(scalar){
-                values("5.193773500000001");
-            }
-            fall_power(scalar){
-                values("5.193773500000001");
-            }
-        }
-        internal_power(){
-            when : "CSb0"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0.0"); 
-            }
-            fall_constraint(scalar) {
-                values("0.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk0; 
-            rise_constraint(scalar) {
-                values("0"); 
-            }
-            fall_constraint(scalar) {
-                values("0"); 
-            }
-         }
-    }
-
-    }
-}
diff --git a/compiler/datasheet/server_scripts/index.html b/compiler/datasheet/server_scripts/index.html
deleted file mode 100644
index 6b1596ba..00000000
--- a/compiler/datasheet/server_scripts/index.html
+++ /dev/null
@@ -1,124 +0,0 @@
-
-</ul>
-    <link rel="stylesheet" href="static/index.css">
-
-    <button class="collapsible">files</button>
-    <div class="content">
-        
-        
-        
-        
-            
-
-        <button class="collapsible">./files/test_files</button>
-        <div class="content">
-            
-            <button class="collapsible">sram_2_16_scn4m_subm.py</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm.py">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm_TT_5V_25C.lib</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm_TT_3p3V_25C.lib</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm.sp</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm.sp">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm.v</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm.v">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm_TT_5p0V_25C.lib</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm.gds</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm.gds">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm.html</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm.html">link</a> 
-             </div>
-            
-            <button class="collapsible">sram_2_16_scn4m_subm.lef</button>
-            <div class="content">
-                <a href="./files/test_files/sram_2_16_scn4m_subm.lef">link</a> 
-             </div>
-            
-        </div>
-
-        
-        
-        
-            
-
-        <button class="collapsible">./files/test_files/testfolder</button>
-        <div class="content">
-            
-            <button class="collapsible">file2</button>
-            <div class="content">
-                <a href="./files/test_files/testfolder/file2">link</a> 
-             </div>
-            
-            <button class="collapsible">file1</button>
-            <div class="content">
-                <a href="./files/test_files/testfolder/file1">link</a> 
-             </div>
-            
-        </div>
-
-        
-        
-        
-            
-
-        <button class="collapsible">./files/test_files/testfolder2</button>
-        <div class="content">
-            
-            <button class="collapsible">file4</button>
-            <div class="content">
-                <a href="./files/test_files/testfolder2/file4">link</a> 
-             </div>
-            
-            <button class="collapsible">file3</button>
-            <div class="content">
-                <a href="./files/test_files/testfolder2/file3">link</a> 
-             </div>
-            
-        </div>
-
-        
-        
-    </div>
-
-
-    <script type="text/javascript">
-        var coll = document.getElementsByClassName("collapsible");
-        var i;
-
-        for (i = 0; i < coll.length; i++) {
-            coll[i].addEventListener("click", function() {
-        this.classList.toggle("active");
-        var content = this.nextElementSibling;
-        if (content.style.display === "block") {
-            content.style.display = "none";
-        } else {
-          content.style.display = "block";
-        }
-          });
-        }
-        </script>
-</ul>
\ No newline at end of file
diff --git a/compiler/datasheet/server_scripts/static/index.css b/compiler/datasheet/server_scripts/static/index.css
deleted file mode 100644
index 0c832b7f..00000000
--- a/compiler/datasheet/server_scripts/static/index.css
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Style the button that is used to open and close the collapsible content */
-.collapsible {
-  background-color: #eee;
-  color: #444;
-  cursor: pointer;
-  padding: 18px;
-  width: 100%;
-  border: none;
-  text-align: left;
-  outline: none;
-  font-size: 15px;
-}
-
-/* Add a background color to the button if it is clicked on (add the .active class with JS), and when you move the mouse over it (hover) */
-.active, .collapsible:hover {
-  background-color: #ccc;
-}
-
-/* Style the collapsible content. Note: hidden by default */
-.content {
-  padding: 0 18px;
-  display: none;
-  overflow: hidden;
-  background-color: #f1f1f1;
-}
diff --git a/compiler/datasheet/server_scripts/templates/index.html b/compiler/datasheet/server_scripts/templates/index.html
deleted file mode 100644
index 31eae12a..00000000
--- a/compiler/datasheet/server_scripts/templates/index.html
+++ /dev/null
@@ -1,42 +0,0 @@
-
-</ul>
-    <link rel="stylesheet" href="static/index.css">
-
-    <button class="collapsible">files</button>
-    <div class="content">
-        {% for root, dir, files in os.walk(filedir) %}
-        {% if root != filedir %}
-            
-
-        <button class="collapsible">{{ root }}</button>
-        <div class="content">
-            {% for f in files %}
-            <button class="collapsible">{{ f }}</button>
-            <div class="content">
-                <a href="{{ root }}/{{ f }}">link</a> 
-             </div>
-            {% endfor %}
-        </div>
-
-        {% endif  %}
-        {% endfor %}
-    </div>
-
-
-    <script type="text/javascript">
-        var coll = document.getElementsByClassName("collapsible");
-        var i;
-
-        for (i = 0; i < coll.length; i++) {
-            coll[i].addEventListener("click", function() {
-        this.classList.toggle("active");
-        var content = this.nextElementSibling;
-        if (content.style.display === "block") {
-            content.style.display = "none";
-        } else {
-          content.style.display = "block";
-        }
-          });
-        }
-        </script>
-</ul>
diff --git a/compiler/datasheet/table_gen.py b/compiler/datasheet/table_gen.py
new file mode 100644
index 00000000..18590739
--- /dev/null
+++ b/compiler/datasheet/table_gen.py
@@ -0,0 +1,43 @@
+class table_gen:
+    def __init__(self,name):
+        self.name = name
+        self.rows = []
+        self.table_id = 'data'
+
+    def add_row(self,row):
+        self.rows.append(row)
+
+    def gen_table_head(self):
+        html = ''
+
+        html += '<thead>'
+        html += '<tr>'
+        for col in self.rows[0]:
+            html += '<th>' + str(col) +  '</th>'
+        html += '</tr>'
+        html += '</thead>'
+        return html
+
+    def gen_table_body(self):
+        html = ''
+
+        html += '<tbody>'
+        html += '<tr>'
+        for row in self.rows[1:]:
+            html += '<tr>'
+            for col in row:
+                html += '<td>' + str(col) + '</td>'
+            html += '</tr>'
+        html += '</tr>'
+        html += '</tbody>'
+        return html
+ 
+    def to_html(self):
+       
+        html = ''
+        html += '<table id= \"'+self.table_id+'\">'
+        html += self.gen_table_head()
+        html += self.gen_table_body()
+        html += '</table>'
+        
+        return html

From 4d0a8b9c8a7fef56b3c972ab2bf518fb3eeaf919 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 9 Jan 2019 08:24:20 -0800
Subject: [PATCH 17/28] Check for coverage executable and run without if not
 found.

---
 compiler/tests/30_openram_test.py | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py
index 333fc542..55ab9457 100755
--- a/compiler/tests/30_openram_test.py
+++ b/compiler/tests/30_openram_test.py
@@ -45,14 +45,16 @@ class openram_test(openram_test):
         # Always perform code coverage
         if OPTS.coverage == 0:
             debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage")
-        exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) 
+            exe_name = "{0}/openram.py ".format(OPENRAM_HOME)
+        else:
+            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) 
         config_name = "{0}config_20_{1}.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name)
         cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
-                                                                                       out_file,
-                                                                                       out_path,
-                                                                                       verbosity,
-                                                                                       config_name,
-                                                                                       out_path)
+                                                                          out_file,
+                                                                          out_path,
+                                                                          verbosity,
+                                                                          config_name,
+                                                                          out_path)
         debug.info(1, cmd)
         os.system(cmd)
         

From 7e635d02bed088ed941afa8acad5e4087b554923 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 9 Jan 2019 12:00:00 -0800
Subject: [PATCH 18/28] Remove indices from pins in lib file

---
 compiler/characterizer/lib.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index ae1d3c82..f636d846 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -325,7 +325,7 @@ class lib:
         self.lib.write("        }\n")
         
 
-        self.lib.write("        pin(DOUT{1}[{0}:0]){{\n".format(self.sram.word_size - 1, read_port))
+        self.lib.write("        pin(DOUT{}){{\n".format(read_port))
         self.lib.write("        timing(){ \n")
         self.lib.write("            timing_sense : non_unate; \n")
         self.lib.write("            related_pin : \"clk{0}\"; \n".format(read_port))
@@ -358,7 +358,7 @@ class lib:
         self.lib.write("            address : ADDR{0}; \n".format(write_port))
         self.lib.write("            clocked_on  : clk{0}; \n".format(write_port))
         self.lib.write("        }\n") 
-        self.lib.write("        pin(DIN{1}[{0}:0]){{\n".format(self.sram.word_size - 1, write_port))
+        self.lib.write("        pin(DIN{}){{\n".format(write_port))
         self.write_FF_setuphold(write_port)
         self.lib.write("        }\n") # pin  
         self.lib.write("    }\n") #bus
@@ -378,7 +378,7 @@ class lib:
         self.lib.write("        direction  : input; \n")
         self.lib.write("        capacitance : {0};  \n".format(tech.spice["dff_in_cap"]))
         self.lib.write("        max_transition       : {0};\n".format(self.slews[-1]))
-        self.lib.write("        pin(ADDR{1}[{0}:0])".format(self.sram.addr_size - 1, port))
+        self.lib.write("        pin(ADDR{}])".format(port))
         self.lib.write("{\n")
         
         self.write_FF_setuphold(port)

From fe077a453a2507229d017b01ac9db644d4d51a2a Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 9 Jan 2019 12:00:14 -0800
Subject: [PATCH 19/28] Change capitalization of message to be consistent

---
 compiler/sram.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/compiler/sram.py b/compiler/sram.py
index 4db89eef..47e5176a 100644
--- a/compiler/sram.py
+++ b/compiler/sram.py
@@ -111,14 +111,14 @@ class sram():
         start_time = datetime.datetime.now()
         from shutil import copyfile
         copyfile(OPTS.config_file + '.py', OPTS.output_path + OPTS.output_name + '.py')
-        print("Config: writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
+        print("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
         print_time("Config", datetime.datetime.now(), start_time)
 
         # Write the datasheet
         start_time = datetime.datetime.now()
         from datasheet_gen import datasheet_gen
         dname = OPTS.output_path + self.s.name + ".html"
-        print("Datasheet: writing to {0}".format(dname))
+        print("Datasheet: Writing to {0}".format(dname))
         datasheet_gen.datasheet_write(self.s,dname)
         print_time("Datasheet", datetime.datetime.now(), start_time)
 

From 49d0b9d69c08ebf307d3d0e05f0f1428fb660ed9 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 9 Jan 2019 12:04:17 -0800
Subject: [PATCH 20/28] Remove old scn3me golden results. Remove indices from
 new golden results.

---
 .../sram_2_16_1_freepdk45_TT_1p0V_25C.lib     |    6 +-
 ..._16_1_freepdk45_TT_1p0V_25C_analytical.lib |    6 +-
 ...am_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib |    6 +-
 .../tests/golden/sram_2_16_1_scn3me_subm.lef  | 5533 -----------------
 .../tests/golden/sram_2_16_1_scn3me_subm.sp   |  681 --
 .../tests/golden/sram_2_16_1_scn3me_subm.v    |   47 -
 .../sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib   |  319 -
 ...6_1_scn3me_subm_TT_5p0V_25C_analytical.lib |  319 -
 ..._2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib |  319 -
 .../sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib    |    6 +-
 ...16_1_scn4m_subm_TT_5p0V_25C_analytical.lib |    6 +-
 ...m_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib |    6 +-
 12 files changed, 18 insertions(+), 7236 deletions(-)
 delete mode 100644 compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
 delete mode 100644 compiler/tests/golden/sram_2_16_1_scn3me_subm.sp
 delete mode 100644 compiler/tests/golden/sram_2_16_1_scn3me_subm.v
 delete mode 100644 compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
 delete mode 100644 compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
 delete mode 100644 compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib

diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
index 45813c16..868ed2b2 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0[1:0]){
+        pin(DIN0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0[1:0]){
+        pin(DOUT0){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
         direction  : input; 
         capacitance : 0.2091;  
         max_transition       : 0.04;
-        pin(ADDR0[3:0]){
+        pin(ADDR0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
index 13c6d975..60f4f9b3 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0[1:0]){
+        pin(DIN0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0[1:0]){
+        pin(DOUT0){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
         direction  : input; 
         capacitance : 0.2091;  
         max_transition       : 0.04;
-        pin(ADDR0[3:0]){
+        pin(ADDR0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
index 4d0defaf..4a809be2 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0[1:0]){
+        pin(DIN0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0[1:0]){
+        pin(DOUT0){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
         direction  : input; 
         capacitance : 0.2091;  
         max_transition       : 0.04;
-        pin(ADDR0[3:0]){
+        pin(ADDR0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
deleted file mode 100644
index 9d784677..00000000
--- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
+++ /dev/null
@@ -1,5533 +0,0 @@
-VERSION 5.4 ;
-NAMESCASESENSITIVE ON ;
-BUSBITCHARS "[]" ;
-DIVIDERCHAR "/" ;
-UNITS
-  DATABASE MICRONS 1000 ;
-END UNITS
-SITE  MacroSite
-   CLASS Core ;
-   SIZE 148050.0 by 461850.0 ;
-END  MacroSite
-MACRO sram_2_16_1_scn3me_subm
-   CLASS BLOCK ;
-   SIZE 148050.0 BY 461850.0 ;
-   SYMMETRY X Y R90 ;
-   SITE MacroSite ;
-   PIN DATA[0]
-      DIRECTION INOUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  120900.0 0.0 121800.0 1800.0 ;
-      END
-   END DATA[0]
-   PIN DATA[1]
-      DIRECTION INOUT ;
-      PORT
-         LAYER metal2 ;
-         RECT  131100.0 0.0 132000.0 1800.0 ;
-      END
-   END DATA[1]
-   PIN ADDR[0]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal3 ;
-         RECT  0.0 87600.0 10800.0 89100.0 ;
-      END
-   END ADDR[0]
-   PIN ADDR[1]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal3 ;
-         RECT  0.0 77400.0 10800.0 78900.0 ;
-      END
-   END ADDR[1]
-   PIN ADDR[2]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal3 ;
-         RECT  0.0 67200.0 10800.0 68700.0 ;
-      END
-   END ADDR[2]
-   PIN ADDR[3]
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal3 ;
-         RECT  0.0 57000.0 10800.0 58500.0 ;
-      END
-   END ADDR[3]
-   PIN CSb
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal3 ;
-         RECT  -38400.0 182700.0 -36600.0 184500.0 ;
-      END
-   END CSb
-   PIN WEb
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal3 ;
-         RECT  -28200.0 182700.0 -26400.0 184500.0 ;
-      END
-   END WEb
-   PIN OEb
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal3 ;
-         RECT  -48600.0 182700.0 -46800.0 184500.0 ;
-      END
-   END OEb
-   PIN clk
-      DIRECTION INPUT ;
-      PORT
-         LAYER metal1 ;
-         RECT  -10200.0 181800.0 -9000.0 185400.0 ;
-      END
-   END clk
-   PIN vdd
-      DIRECTION INOUT ;
-      USE POWER ; 
-      SHAPE ABUTMENT ; 
-      PORT
-         LAYER metal2 ;
-         RECT  4950.0 0.0 8550.0 461850.0 ;
-         LAYER metal2 ;
-         RECT  144450.0 0.0 148050.0 461850.0 ;
-         LAYER metal1 ;
-         RECT  0.0 4950.0 148050.0 8550.0 ;
-         LAYER metal1 ;
-         RECT  0.0 458250.0 148050.0 461850.0 ;
-      END
-   END vdd
-   PIN gnd
-      DIRECTION INOUT ;
-      USE GROUND ; 
-      SHAPE ABUTMENT ; 
-      PORT
-         LAYER metal2 ;
-         RECT  0.0 0.0 3600.0 461850.0 ;
-         LAYER metal2 ;
-         RECT  139500.0 0.0 143100.0 461850.0 ;
-         LAYER metal1 ;
-         RECT  0.0 0.0 148050.0 3600.0 ;
-         LAYER metal1 ;
-         RECT  0.0 453300.0 148050.0 456900.0 ;
-      END
-   END gnd
-   OBS
-   LAYER  metal1 ;
-      RECT  48300.0 215550.0 49200.0 216450.0 ;
-      RECT  48300.0 213150.0 49200.0 214050.0 ;
-      RECT  46950.0 215550.0 48750.0 216450.0 ;
-      RECT  48300.0 213600.0 49200.0 216000.0 ;
-      RECT  48750.0 213150.0 50700.0 214050.0 ;
-      RECT  100800.0 215550.0 101700.0 216450.0 ;
-      RECT  100800.0 211050.0 101700.0 211950.0 ;
-      RECT  86850.0 215550.0 101250.0 216450.0 ;
-      RECT  100800.0 211500.0 101700.0 216000.0 ;
-      RECT  101250.0 211050.0 115800.0 211950.0 ;
-      RECT  48300.0 229950.0 49200.0 230850.0 ;
-      RECT  48300.0 232350.0 49200.0 233250.0 ;
-      RECT  46950.0 229950.0 48750.0 230850.0 ;
-      RECT  48300.0 230400.0 49200.0 232800.0 ;
-      RECT  48750.0 232350.0 50700.0 233250.0 ;
-      RECT  100800.0 229950.0 101700.0 230850.0 ;
-      RECT  100800.0 234450.0 101700.0 235350.0 ;
-      RECT  86850.0 229950.0 101250.0 230850.0 ;
-      RECT  100800.0 230400.0 101700.0 234900.0 ;
-      RECT  101250.0 234450.0 115800.0 235350.0 ;
-      RECT  48300.0 243150.0 49200.0 244050.0 ;
-      RECT  48300.0 240750.0 49200.0 241650.0 ;
-      RECT  46950.0 243150.0 48750.0 244050.0 ;
-      RECT  48300.0 241200.0 49200.0 243600.0 ;
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-      RECT  100800.0 238650.0 101700.0 239550.0 ;
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-      RECT  100800.0 239100.0 101700.0 243600.0 ;
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-   END    sram_2_16_1_scn3me_subm
-END    LIBRARY
diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.sp b/compiler/tests/golden/sram_2_16_1_scn3me_subm.sp
deleted file mode 100644
index 258b4464..00000000
--- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.sp
+++ /dev/null
@@ -1,681 +0,0 @@
-* OpenRAM generated memory.
-* User: mrg
-.global vdd gnd
-*master-slave flip-flop with both output and inverted ouput
-
-.subckt ms_flop din dout dout_bar clk vdd gnd
-xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
-xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
-.ends flop
-
-.subckt dlatch din dout dout_bar clk clk_bar vdd gnd
-*clk inverter
-mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
-mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1
-
-*transmission gate 1
-mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1
-mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1
-
-*foward inverter
-mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1
-mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1
-
-*backward inverter
-mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1
-mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1
-
-*transmission gate 2
-mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
-mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
-.ends dlatch
-
-
-.SUBCKT inv_nmos11 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS inv_nmos11
-
-.SUBCKT inv_pmos12 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS inv_pmos12
-
-.SUBCKT pinv A Z vdd gnd
-Xpinv_nmos Z A gnd gnd inv_nmos11
-Xpinv_pmos Z A vdd vdd inv_pmos12
-.ENDS pinv
-
-.SUBCKT nand_2_nmos13 D G S B
-Mnmos D G S B n m=1 w=2.4u l=0.6u
-.ENDS nand_2_nmos13
-
-.SUBCKT nand_2_nmos24 D G S B
-Mnmos D G S B n m=1 w=2.4u l=0.6u
-.ENDS nand_2_nmos24
-
-.SUBCKT nand_2_pmos15 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_2_pmos15
-
-.SUBCKT nand_2_pmos26 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_2_pmos26
-
-.SUBCKT nand2 A B Z vdd gnd
-Xnmos1 Z A net1 gnd nand_2_nmos13
-Xnmos2 net1 B gnd gnd nand_2_nmos24
-Xpmos1 vdd A Z vdd nand_2_pmos15
-Xpmos2 Z B vdd vdd nand_2_pmos26
-.ENDS nand2
-
-.SUBCKT nand_3_nmos17 D G S B
-Mnmos D G S B n m=1 w=3.6u l=0.6u
-.ENDS nand_3_nmos17
-
-.SUBCKT nand_3_nmos28 D G S B
-Mnmos D G S B n m=1 w=3.6u l=0.6u
-.ENDS nand_3_nmos28
-
-.SUBCKT nand_3_nmos39 D G S B
-Mnmos D G S B n m=1 w=3.6u l=0.6u
-.ENDS nand_3_nmos39
-
-.SUBCKT nand_3_pmos110 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_3_pmos110
-
-.SUBCKT nand_3_pmos211 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_3_pmos211
-
-.SUBCKT nand_3_pmos312 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_3_pmos312
-
-.SUBCKT NAND3 A B C Z vdd gnd
-Xnmos1 net2 A gnd gnd nand_3_nmos17
-Xnmos2 net1 B net2 gnd nand_3_nmos28
-Xnmos3 Z C net1 gnd nand_3_nmos39
-Xpmos1 Z A vdd vdd nand_3_pmos110
-Xpmos2 vdd B Z vdd nand_3_pmos211
-Xpmos3 Z C vdd vdd nand_3_pmos312
-.ENDS NAND3
-
-.SUBCKT inv_nmos113 D G S B
-Mnmos D G S B n m=4 w=1.2u l=0.6u
-.ENDS inv_nmos113
-
-.SUBCKT inv_pmos114 D G S B
-Mpmos D G S B p m=4 w=2.4u l=0.6u
-.ENDS inv_pmos114
-
-.SUBCKT pinv4 A Z vdd gnd
-Xpinv_nmos Z A gnd gnd inv_nmos113
-Xpinv_pmos Z A vdd vdd inv_pmos114
-.ENDS pinv4
-
-.SUBCKT nor_2_nmos123 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS nor_2_nmos123
-
-.SUBCKT nor_2_nmos224 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS nor_2_nmos224
-
-.SUBCKT nor_2_pmos125 D G S B
-Mpmos D G S B p m=4 w=1.2u l=0.6u
-.ENDS nor_2_pmos125
-
-.SUBCKT nor_2_pmos226 D G S B
-Mpmos D G S B p m=4 w=1.2u l=0.6u
-.ENDS nor_2_pmos226
-
-.SUBCKT nor2 A B Z vdd gnd
-Xnmos1 Z A gnd gnd nor_2_nmos123
-Xnmos2 Z B gnd gnd nor_2_nmos224
-Xpmos1 vdd A net1 vdd nor_2_pmos125
-Xpmos2 net1 B Z vdd nor_2_pmos226
-.ENDS nor2
-
-.SUBCKT msf_control DATA[0] DATA[1] DATA[2] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] data_in[2] data_in_bar[2] clk vdd gnd
-XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop
-XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop
-XXdff2 DATA[2] data_in[2] data_in_bar[2] clk vdd gnd ms_flop
-.ENDS msf_control
-
-*********************** "cell_6t" ******************************
-.SUBCKT replica_cell_6t bl br wl vdd gnd
-M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u
-M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u
-M_3 br wl net_2 gnd n W='1.2u' L=0.6u
-M_4 bl wl gnd gnd n W='1.2u' L=0.6u
-M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u
-M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u
-.ENDS	$ replica_cell_6t
-
-*********************** "cell_6t" ******************************
-.SUBCKT cell_6t bl br wl vdd gnd
-M_1 net_1 net_2 vdd vdd p W='0.9u' L=1.2u
-M_2 net_2 net_1 vdd vdd p W='0.9u' L=1.2u
-M_3 br wl net_2 gnd n W='1.2u' L=0.6u
-M_4 bl wl net_1 gnd n W='1.2u' L=0.6u
-M_5 net_2 net_1 gnd gnd n W='2.4u' L=0.6u
-M_6 net_1 net_2 gnd gnd n W='2.4u' L=0.6u
-.ENDS	$ cell_6t
-
-.SUBCKT bitline_load bl[0] br[0] wl[0] wl[1] vdd gnd
-Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
-Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
-.ENDS bitline_load
-
-.SUBCKT inv_nmos127 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS inv_nmos127
-
-.SUBCKT inv_pmos128 D G S B
-Mpmos D G S B p m=1 w=3.6u l=0.6u
-.ENDS inv_pmos128
-
-.SUBCKT delay_chain_inv A Z vdd gnd
-Xpinv_nmos Z A gnd gnd inv_nmos127
-Xpinv_pmos Z A vdd vdd inv_pmos128
-.ENDS delay_chain_inv
-
-.SUBCKT delay_chain clk_in clk_out vdd gnd
-Xinv_chain0 clk_in s1 vdd gnd delay_chain_inv
-Xinv_chain1 s1 s2 vdd gnd delay_chain_inv
-Xinv_chain2 s2 s3 vdd gnd delay_chain_inv
-Xinv_chain3 s3 clk_out vdd gnd delay_chain_inv
-.ENDS delay_chain
-
-.SUBCKT inv_nmos129 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS inv_nmos129
-
-.SUBCKT inv_pmos130 D G S B
-Mpmos D G S B p m=1 w=3.6u l=0.6u
-.ENDS inv_pmos130
-
-.SUBCKT RBL_inv A Z vdd gnd
-Xpinv_nmos Z A gnd gnd inv_nmos129
-Xpinv_pmos Z A vdd vdd inv_pmos130
-.ENDS RBL_inv
-
-.SUBCKT nor_2_nmos139 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS nor_2_nmos139
-
-.SUBCKT nor_2_nmos240 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS nor_2_nmos240
-
-.SUBCKT nor_2_pmos141 D G S B
-Mpmos D G S B p m=4 w=1.2u l=0.6u
-.ENDS nor_2_pmos141
-
-.SUBCKT nor_2_pmos242 D G S B
-Mpmos D G S B p m=4 w=1.2u l=0.6u
-.ENDS nor_2_pmos242
-
-.SUBCKT replica_bitline_nor2 A B Z vdd gnd
-Xnmos1 Z A gnd gnd nor_2_nmos139
-Xnmos2 Z B gnd gnd nor_2_nmos240
-Xpmos1 vdd A net1 vdd nor_2_pmos141
-Xpmos2 net1 B Z vdd nor_2_pmos242
-.ENDS replica_bitline_nor2
-
-.SUBCKT access_tx43 D G S B
-Mpmos D G S B p m=1 w=1.2u l=0.6u
-.ENDS access_tx43
-
-.SUBCKT replica_bitline en out vdd gnd
-XBL_inv bl[0] out vdd gnd RBL_inv
-XBL_access_tx vdd delayed_en bl[0] vdd access_tx43
-Xdelay_chain en delayed_en vdd gnd delay_chain
-Xbitcell bl[0] br[0] delayed_en vdd gnd replica_cell_6t
-Xload bl[0] br[0] gnd gnd vdd gnd bitline_load
-.ENDS replica_bitline
-
-.SUBCKT control_logic CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd
-Xmsf_control CSb WEb OEb CS_bar CS WE_bar WE OE_bar OE clk vdd gnd msf_control
-Xclk_inverter clk clk_bar vdd gnd pinv4
-Xnor2 clk OE_bar tri_en vdd gnd nor2
-Xnand2_tri_en OE clk_bar tri_en_bar vdd gnd nand2
-Xreplica_bitline rblk pre_s_en vdd gnd replica_bitline
-Xinv_s_en1 pre_s_en_bar s_en vdd gnd pinv
-Xinv_s_en2 pre_s_en pre_s_en_bar vdd gnd pinv
-XNAND3_rblk_bar clk_bar OE CS rblk_bar vdd gnd NAND3
-XNAND3_w_en_bar clk_bar WE CS w_en_bar vdd gnd NAND3
-Xinv_rblk rblk_bar rblk vdd gnd pinv
-Xinv_w_en w_en_bar pre_w_en vdd gnd pinv
-Xinv_w_en1 pre_w_en pre_w_en1 vdd gnd pinv
-Xinv_w_en2 pre_w_en1 w_en vdd gnd pinv
-.ENDS control_logic
-
-.SUBCKT bitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd
-Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
-Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
-Xbit_r2_c0 bl[0] br[0] wl[2] vdd gnd cell_6t
-Xbit_r3_c0 bl[0] br[0] wl[3] vdd gnd cell_6t
-Xbit_r4_c0 bl[0] br[0] wl[4] vdd gnd cell_6t
-Xbit_r5_c0 bl[0] br[0] wl[5] vdd gnd cell_6t
-Xbit_r6_c0 bl[0] br[0] wl[6] vdd gnd cell_6t
-Xbit_r7_c0 bl[0] br[0] wl[7] vdd gnd cell_6t
-Xbit_r8_c0 bl[0] br[0] wl[8] vdd gnd cell_6t
-Xbit_r9_c0 bl[0] br[0] wl[9] vdd gnd cell_6t
-Xbit_r10_c0 bl[0] br[0] wl[10] vdd gnd cell_6t
-Xbit_r11_c0 bl[0] br[0] wl[11] vdd gnd cell_6t
-Xbit_r12_c0 bl[0] br[0] wl[12] vdd gnd cell_6t
-Xbit_r13_c0 bl[0] br[0] wl[13] vdd gnd cell_6t
-Xbit_r14_c0 bl[0] br[0] wl[14] vdd gnd cell_6t
-Xbit_r15_c0 bl[0] br[0] wl[15] vdd gnd cell_6t
-Xbit_r0_c1 bl[1] br[1] wl[0] vdd gnd cell_6t
-Xbit_r1_c1 bl[1] br[1] wl[1] vdd gnd cell_6t
-Xbit_r2_c1 bl[1] br[1] wl[2] vdd gnd cell_6t
-Xbit_r3_c1 bl[1] br[1] wl[3] vdd gnd cell_6t
-Xbit_r4_c1 bl[1] br[1] wl[4] vdd gnd cell_6t
-Xbit_r5_c1 bl[1] br[1] wl[5] vdd gnd cell_6t
-Xbit_r6_c1 bl[1] br[1] wl[6] vdd gnd cell_6t
-Xbit_r7_c1 bl[1] br[1] wl[7] vdd gnd cell_6t
-Xbit_r8_c1 bl[1] br[1] wl[8] vdd gnd cell_6t
-Xbit_r9_c1 bl[1] br[1] wl[9] vdd gnd cell_6t
-Xbit_r10_c1 bl[1] br[1] wl[10] vdd gnd cell_6t
-Xbit_r11_c1 bl[1] br[1] wl[11] vdd gnd cell_6t
-Xbit_r12_c1 bl[1] br[1] wl[12] vdd gnd cell_6t
-Xbit_r13_c1 bl[1] br[1] wl[13] vdd gnd cell_6t
-Xbit_r14_c1 bl[1] br[1] wl[14] vdd gnd cell_6t
-Xbit_r15_c1 bl[1] br[1] wl[15] vdd gnd cell_6t
-.ENDS bitcell_array
-
-.SUBCKT lower_pmos44 D G S B
-Mpmos D G S B p m=1 w=1.2u l=0.6u
-.ENDS lower_pmos44
-
-.SUBCKT upper_pmos45 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS upper_pmos45
-
-.SUBCKT precharge_cell bl br clk vdd
-Xlower_pmos bl clk br vdd lower_pmos44
-Xupper_pmos1 bl clk vdd vdd upper_pmos45
-Xupper_pmos2 br clk vdd vdd upper_pmos45
-.ENDS precharge_cell
-
-.SUBCKT precharge_array bl[0] br[0] bl[1] br[1] clk vdd
-Xpre_column_0 bl[0] br[0] clk vdd precharge_cell
-Xpre_column_1 bl[1] br[1] clk vdd precharge_cell
-.ENDS precharge_array
-*********************** "sense_amp" ******************************
-
-.SUBCKT sense_amp bl br dout sclk vdd gnd
-M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u
-M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u
-M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u
-M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u
-M_5 bl sclk dout vdd p W='7.2*1u' L=0.6u
-M_6 br sclk net_1 vdd p W='7.2*1u' L=0.6u
-M_7 net_2 sclk gnd gnd n W='2.7*1u' L=0.6u
-.ENDS	 sense_amp
-
-
-.SUBCKT sense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] sclk vdd gnd
-Xsa_d0 bl[0] br[0] data_out[0] sclk vdd gnd sense_amp
-Xsa_d1 bl[1] br[1] data_out[1] sclk vdd gnd sense_amp
-.ENDS sense_amp_array
-*********************** Write_Driver ******************************
-.SUBCKT write_driver din bl br wen vdd gnd
-
-**** Inverter to conver Data_in to data_in_bar ******
-M_1 net_3 din gnd gnd n W='1.2*1u' L=0.6u
-M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u
-
-**** 2input nand gate follwed by inverter to drive BL ******
-M_3 net_2 wen net_7 gnd n W='2.1*1u' L=0.6u
-M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u
-M_5 net_2 wen vdd vdd p W='2.1*1u' L=0.6u
-M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u
-
-
-M_7 net_1 net_2 vdd vdd p W='2.1*1u' L=0.6u
-M_8 net_1 net_2 gnd gnd n W='1.2*1u' L=0.6u
-
-**** 2input nand gate follwed by inverter to drive BR******
-
-M_9 net_4 wen vdd vdd p W='2.1*1u' L=0.6u
-M_10 net_4 wen net_8 gnd n W='2.1*1u' L=0.6u
-M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u
-M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u
-
-M_13 net_6 net_4 vdd vdd p W='2.1*1u' L=0.6u
-M_14 net_6 net_4 gnd gnd n W='1.2*1u' L=0.6u
-
-************************************************
-
-M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u
-M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u
-M_17 net_5 wen gnd gnd n W='3.6*1u' L=0.6u
-
-
-
-.ENDS	$ write_driver
-
-
-.SUBCKT write_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] wen vdd gnd
-XXwrite_driver0 data_in[0] bl[0] br[0] wen vdd gnd write_driver
-XXwrite_driver1 data_in[1] bl[1] br[1] wen vdd gnd write_driver
-.ENDS write_driver_array
-
-.SUBCKT inv_nmos147 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS inv_nmos147
-
-.SUBCKT inv_pmos148 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS inv_pmos148
-
-.SUBCKT INVERTER A Z vdd gnd
-Xpinv_nmos Z A gnd gnd inv_nmos147
-Xpinv_pmos Z A vdd vdd inv_pmos148
-.ENDS INVERTER
-
-.SUBCKT nand_2_nmos149 D G S B
-Mnmos D G S B n m=1 w=2.4u l=0.6u
-.ENDS nand_2_nmos149
-
-.SUBCKT nand_2_nmos250 D G S B
-Mnmos D G S B n m=1 w=2.4u l=0.6u
-.ENDS nand_2_nmos250
-
-.SUBCKT nand_2_pmos151 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_2_pmos151
-
-.SUBCKT nand_2_pmos252 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_2_pmos252
-
-.SUBCKT NAND2 A B Z vdd gnd
-Xnmos1 Z A net1 gnd nand_2_nmos149
-Xnmos2 net1 B gnd gnd nand_2_nmos250
-Xpmos1 vdd A Z vdd nand_2_pmos151
-Xpmos2 Z B vdd vdd nand_2_pmos252
-.ENDS NAND2
-
-.SUBCKT nand_2_nmos159 D G S B
-Mnmos D G S B n m=1 w=2.4u l=0.6u
-.ENDS nand_2_nmos159
-
-.SUBCKT nand_2_nmos260 D G S B
-Mnmos D G S B n m=1 w=2.4u l=0.6u
-.ENDS nand_2_nmos260
-
-.SUBCKT nand_2_pmos161 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_2_pmos161
-
-.SUBCKT nand_2_pmos262 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_2_pmos262
-
-.SUBCKT a_nand_2 A B Z vdd gnd
-Xnmos1 Z A net1 gnd nand_2_nmos159
-Xnmos2 net1 B gnd gnd nand_2_nmos260
-Xpmos1 vdd A Z vdd nand_2_pmos161
-Xpmos2 Z B vdd vdd nand_2_pmos262
-.ENDS a_nand_2
-
-.SUBCKT inv_nmos163 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS inv_nmos163
-
-.SUBCKT inv_pmos164 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS inv_pmos164
-
-.SUBCKT a_inv_1 A Z vdd gnd
-Xpinv_nmos Z A gnd gnd inv_nmos163
-Xpinv_pmos Z A vdd vdd inv_pmos164
-.ENDS a_inv_1
-
-.SUBCKT pre2x4 A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd
-XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1
-XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1
-XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1
-XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1
-XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1
-XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1
-XXpre2x4_nand[0] A[0] A[1] Z[3] vdd gnd a_nand_2
-XXpre2x4_nand[1] B[0] A[1] Z[2] vdd gnd a_nand_2
-XXpre2x4_nand[2] A[0] B[1] Z[1] vdd gnd a_nand_2
-XXpre2x4_nand[3] B[0] B[1] Z[0] vdd gnd a_nand_2
-.ENDS pre2x4
-
-.SUBCKT nand_3_nmos165 D G S B
-Mnmos D G S B n m=1 w=3.6u l=0.6u
-.ENDS nand_3_nmos165
-
-.SUBCKT nand_3_nmos266 D G S B
-Mnmos D G S B n m=1 w=3.6u l=0.6u
-.ENDS nand_3_nmos266
-
-.SUBCKT nand_3_nmos367 D G S B
-Mnmos D G S B n m=1 w=3.6u l=0.6u
-.ENDS nand_3_nmos367
-
-.SUBCKT nand_3_pmos168 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_3_pmos168
-
-.SUBCKT nand_3_pmos269 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_3_pmos269
-
-.SUBCKT nand_3_pmos370 D G S B
-Mpmos D G S B p m=1 w=2.4u l=0.6u
-.ENDS nand_3_pmos370
-
-.SUBCKT a_nand_3 A B C Z vdd gnd
-Xnmos1 net2 A gnd gnd nand_3_nmos165
-Xnmos2 net1 B net2 gnd nand_3_nmos266
-Xnmos3 Z C net1 gnd nand_3_nmos367
-Xpmos1 Z A vdd vdd nand_3_pmos168
-Xpmos2 vdd B Z vdd nand_3_pmos269
-Xpmos3 Z C vdd vdd nand_3_pmos370
-.ENDS a_nand_3
-
-.SUBCKT pre3x8 A[0] A[1] A[2] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] vdd gnd
-XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1
-XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1
-XXpre2x4_inv[2] A[2] B[2] vdd gnd a_inv_1
-XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1
-XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1
-XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1
-XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1
-XXpre2x4_nand_inv[4] Z[4] out[4] vdd gnd a_inv_1
-XXpre2x4_nand_inv[5] Z[5] out[5] vdd gnd a_inv_1
-XXpre2x4_nand_inv[6] Z[6] out[6] vdd gnd a_inv_1
-XXpre2x4_nand_inv[7] Z[7] out[7] vdd gnd a_inv_1
-XXpre3x8_nand[0] A[0] A[1] A[2] Z[7] vdd gnd a_nand_3
-XXpre3x8_nand[1] A[0] A[1] B[2] Z[6] vdd gnd a_nand_3
-XXpre3x8_nand[2] A[0] B[1] A[2] Z[5] vdd gnd a_nand_3
-XXpre3x8_nand[3] A[0] B[1] B[2] Z[4] vdd gnd a_nand_3
-XXpre3x8_nand[4] B[0] A[1] A[2] Z[3] vdd gnd a_nand_3
-XXpre3x8_nand[5] B[0] A[1] B[2] Z[2] vdd gnd a_nand_3
-XXpre3x8_nand[6] B[0] B[1] A[2] Z[1] vdd gnd a_nand_3
-XXpre3x8_nand[7] B[0] B[1] B[2] Z[0] vdd gnd a_nand_3
-.ENDS pre3x8
-
-.SUBCKT hierarchical_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd
-Xpre[0] A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd pre2x4
-Xpre[1] A[2] A[3] out[4] out[5] out[6] out[7] vdd gnd pre2x4
-XNAND2_[0] out[0] out[4] Z[0] vdd gnd NAND2
-XNAND2_[1] out[0] out[5] Z[1] vdd gnd NAND2
-XNAND2_[2] out[0] out[6] Z[2] vdd gnd NAND2
-XNAND2_[3] out[0] out[7] Z[3] vdd gnd NAND2
-XNAND2_[4] out[1] out[4] Z[4] vdd gnd NAND2
-XNAND2_[5] out[1] out[5] Z[5] vdd gnd NAND2
-XNAND2_[6] out[1] out[6] Z[6] vdd gnd NAND2
-XNAND2_[7] out[1] out[7] Z[7] vdd gnd NAND2
-XNAND2_[8] out[2] out[4] Z[8] vdd gnd NAND2
-XNAND2_[9] out[2] out[5] Z[9] vdd gnd NAND2
-XNAND2_[10] out[2] out[6] Z[10] vdd gnd NAND2
-XNAND2_[11] out[2] out[7] Z[11] vdd gnd NAND2
-XNAND2_[12] out[3] out[4] Z[12] vdd gnd NAND2
-XNAND2_[13] out[3] out[5] Z[13] vdd gnd NAND2
-XNAND2_[14] out[3] out[6] Z[14] vdd gnd NAND2
-XNAND2_[15] out[3] out[7] Z[15] vdd gnd NAND2
-XINVERTER_[0] Z[0] decode_out[0] vdd gnd INVERTER
-XINVERTER_[1] Z[1] decode_out[1] vdd gnd INVERTER
-XINVERTER_[2] Z[2] decode_out[2] vdd gnd INVERTER
-XINVERTER_[3] Z[3] decode_out[3] vdd gnd INVERTER
-XINVERTER_[4] Z[4] decode_out[4] vdd gnd INVERTER
-XINVERTER_[5] Z[5] decode_out[5] vdd gnd INVERTER
-XINVERTER_[6] Z[6] decode_out[6] vdd gnd INVERTER
-XINVERTER_[7] Z[7] decode_out[7] vdd gnd INVERTER
-XINVERTER_[8] Z[8] decode_out[8] vdd gnd INVERTER
-XINVERTER_[9] Z[9] decode_out[9] vdd gnd INVERTER
-XINVERTER_[10] Z[10] decode_out[10] vdd gnd INVERTER
-XINVERTER_[11] Z[11] decode_out[11] vdd gnd INVERTER
-XINVERTER_[12] Z[12] decode_out[12] vdd gnd INVERTER
-XINVERTER_[13] Z[13] decode_out[13] vdd gnd INVERTER
-XINVERTER_[14] Z[14] decode_out[14] vdd gnd INVERTER
-XINVERTER_[15] Z[15] decode_out[15] vdd gnd INVERTER
-.ENDS hierarchical_decoder
-
-.SUBCKT msf_address ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] addr_clk vdd gnd
-XXdff0 ADDR[0] A[0] A_bar[0] addr_clk vdd gnd ms_flop
-XXdff1 ADDR[1] A[1] A_bar[1] addr_clk vdd gnd ms_flop
-XXdff2 ADDR[2] A[2] A_bar[2] addr_clk vdd gnd ms_flop
-XXdff3 ADDR[3] A[3] A_bar[3] addr_clk vdd gnd ms_flop
-.ENDS msf_address
-
-.SUBCKT msf_data_in DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk vdd gnd
-XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop
-XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop
-.ENDS msf_data_in
-
-.SUBCKT msf_data_out data_out[0] data_out[1] tri_in[0] tri_in_bar[0] tri_in[1] tri_in_bar[1] sclk vdd gnd
-XXdff0 data_out[0] tri_in[0] tri_in_bar[0] sclk vdd gnd ms_flop
-XXdff1 data_out[1] tri_in[1] tri_in_bar[1] sclk vdd gnd ms_flop
-.ENDS msf_data_out
-*********************** tri_gate ******************************
-
-.SUBCKT tri_gate in out en en_bar vdd gnd
-
-M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u
-M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u
-M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u
-M_4 out en net_2 gnd n W='1.2*1u' L=0.6u
-M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u
-M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u
-
-
-.ENDS	
-
-.SUBCKT tri_gate_array tri_in[0] tri_in[1] DATA[0] DATA[1] en en_bar vdd gnd
-XXtri_gate0 tri_in[0] DATA[0] en en_bar vdd gnd tri_gate
-XXtri_gate1 tri_in[1] DATA[1] en en_bar vdd gnd tri_gate
-.ENDS tri_gate_array
-
-.SUBCKT wordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd
-XWordline_driver_inv_clk0 clk clk_bar[0] vdd gnd INVERTER
-XWordline_driver_nand0 decode_out[0] clk_bar[0] net[0] vdd gnd NAND2
-XWordline_driver_inv0 net[0] wl[0] vdd gnd INVERTER
-XWordline_driver_inv_clk1 clk clk_bar[1] vdd gnd INVERTER
-XWordline_driver_nand1 decode_out[1] clk_bar[1] net[1] vdd gnd NAND2
-XWordline_driver_inv1 net[1] wl[1] vdd gnd INVERTER
-XWordline_driver_inv_clk2 clk clk_bar[2] vdd gnd INVERTER
-XWordline_driver_nand2 decode_out[2] clk_bar[2] net[2] vdd gnd NAND2
-XWordline_driver_inv2 net[2] wl[2] vdd gnd INVERTER
-XWordline_driver_inv_clk3 clk clk_bar[3] vdd gnd INVERTER
-XWordline_driver_nand3 decode_out[3] clk_bar[3] net[3] vdd gnd NAND2
-XWordline_driver_inv3 net[3] wl[3] vdd gnd INVERTER
-XWordline_driver_inv_clk4 clk clk_bar[4] vdd gnd INVERTER
-XWordline_driver_nand4 decode_out[4] clk_bar[4] net[4] vdd gnd NAND2
-XWordline_driver_inv4 net[4] wl[4] vdd gnd INVERTER
-XWordline_driver_inv_clk5 clk clk_bar[5] vdd gnd INVERTER
-XWordline_driver_nand5 decode_out[5] clk_bar[5] net[5] vdd gnd NAND2
-XWordline_driver_inv5 net[5] wl[5] vdd gnd INVERTER
-XWordline_driver_inv_clk6 clk clk_bar[6] vdd gnd INVERTER
-XWordline_driver_nand6 decode_out[6] clk_bar[6] net[6] vdd gnd NAND2
-XWordline_driver_inv6 net[6] wl[6] vdd gnd INVERTER
-XWordline_driver_inv_clk7 clk clk_bar[7] vdd gnd INVERTER
-XWordline_driver_nand7 decode_out[7] clk_bar[7] net[7] vdd gnd NAND2
-XWordline_driver_inv7 net[7] wl[7] vdd gnd INVERTER
-XWordline_driver_inv_clk8 clk clk_bar[8] vdd gnd INVERTER
-XWordline_driver_nand8 decode_out[8] clk_bar[8] net[8] vdd gnd NAND2
-XWordline_driver_inv8 net[8] wl[8] vdd gnd INVERTER
-XWordline_driver_inv_clk9 clk clk_bar[9] vdd gnd INVERTER
-XWordline_driver_nand9 decode_out[9] clk_bar[9] net[9] vdd gnd NAND2
-XWordline_driver_inv9 net[9] wl[9] vdd gnd INVERTER
-XWordline_driver_inv_clk10 clk clk_bar[10] vdd gnd INVERTER
-XWordline_driver_nand10 decode_out[10] clk_bar[10] net[10] vdd gnd NAND2
-XWordline_driver_inv10 net[10] wl[10] vdd gnd INVERTER
-XWordline_driver_inv_clk11 clk clk_bar[11] vdd gnd INVERTER
-XWordline_driver_nand11 decode_out[11] clk_bar[11] net[11] vdd gnd NAND2
-XWordline_driver_inv11 net[11] wl[11] vdd gnd INVERTER
-XWordline_driver_inv_clk12 clk clk_bar[12] vdd gnd INVERTER
-XWordline_driver_nand12 decode_out[12] clk_bar[12] net[12] vdd gnd NAND2
-XWordline_driver_inv12 net[12] wl[12] vdd gnd INVERTER
-XWordline_driver_inv_clk13 clk clk_bar[13] vdd gnd INVERTER
-XWordline_driver_nand13 decode_out[13] clk_bar[13] net[13] vdd gnd NAND2
-XWordline_driver_inv13 net[13] wl[13] vdd gnd INVERTER
-XWordline_driver_inv_clk14 clk clk_bar[14] vdd gnd INVERTER
-XWordline_driver_nand14 decode_out[14] clk_bar[14] net[14] vdd gnd NAND2
-XWordline_driver_inv14 net[14] wl[14] vdd gnd INVERTER
-XWordline_driver_inv_clk15 clk clk_bar[15] vdd gnd INVERTER
-XWordline_driver_nand15 decode_out[15] clk_bar[15] net[15] vdd gnd NAND2
-XWordline_driver_inv15 net[15] wl[15] vdd gnd INVERTER
-.ENDS wordline_driver
-
-.SUBCKT inv_nmos181 D G S B
-Mnmos D G S B n m=4 w=1.2u l=0.6u
-.ENDS inv_nmos181
-
-.SUBCKT inv_pmos182 D G S B
-Mpmos D G S B p m=4 w=2.4u l=0.6u
-.ENDS inv_pmos182
-
-.SUBCKT pinv4x A Z vdd gnd
-Xpinv_nmos Z A gnd gnd inv_nmos181
-Xpinv_pmos Z A vdd vdd inv_pmos182
-.ENDS pinv4x
-
-.SUBCKT nor_2_nmos195 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS nor_2_nmos195
-
-.SUBCKT nor_2_nmos296 D G S B
-Mnmos D G S B n m=1 w=1.2u l=0.6u
-.ENDS nor_2_nmos296
-
-.SUBCKT nor_2_pmos197 D G S B
-Mpmos D G S B p m=4 w=1.2u l=0.6u
-.ENDS nor_2_pmos197
-
-.SUBCKT nor_2_pmos298 D G S B
-Mpmos D G S B p m=4 w=1.2u l=0.6u
-.ENDS nor_2_pmos298
-
-.SUBCKT NOR2 A B Z vdd gnd
-Xnmos1 Z A gnd gnd nor_2_nmos195
-Xnmos2 Z B gnd gnd nor_2_nmos296
-Xpmos1 vdd A net1 vdd nor_2_pmos197
-Xpmos2 net1 B Z vdd nor_2_pmos298
-.ENDS NOR2
-
-.SUBCKT test_bank1 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd
-Xbitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd bitcell_array
-Xprecharge_array bl[0] br[0] bl[1] br[1] clk_bar vdd precharge_array
-Xsense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] s_en vdd gnd sense_amp_array
-Xwrite_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] w_en vdd gnd write_driver_array
-Xdata_in_flop_array DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk_bar vdd gnd msf_data_in
-Xtrigate_data_array data_out[0] data_out[1] DATA[0] DATA[1] tri_en tri_en_bar vdd gnd tri_gate_array
-Xaddress_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd hierarchical_decoder
-Xwordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd wordline_driver
-Xaddress_flop_array ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] clk vdd gnd msf_address
-.ENDS test_bank1
-
-.SUBCKT testsram DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] CSb WEb OEb clk vdd gnd
-Xbank0 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd test_bank1
-Xcontrol CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd control_logic
-.ENDS testsram
diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.v b/compiler/tests/golden/sram_2_16_1_scn3me_subm.v
deleted file mode 100644
index fc2b6cd0..00000000
--- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.v
+++ /dev/null
@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 16
-// Word size: 2
-
-module sram_2_16_1_scn3me_subm(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 2 ;
-  parameter ADDR_WIDTH = 4 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule
diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
deleted file mode 100644
index 57d36974..00000000
--- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
+++ /dev/null
@@ -1,319 +0,0 @@
-library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 2;
-    bit_from : 0;
-    bit_to : 1;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 4;
-    bit_from : 0;
-    bit_to : 3;
-    }
-
-cell (sram_2_16_1_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 4;
-    word_width : 2;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 142800.38999999998;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.0252988;
-    }
-    cell_leakage_power : 0;
-    bus(DIN){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-    }
-    bus(DOUT){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DOUT[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.945, 0.976, 1.139",\
-                   "0.948, 0.98, 1.143",\
-                   "1.003, 1.036, 1.202");
-            }
-            cell_fall(CELL_TABLE) {
-            values("11.211, 11.266, 11.754",\
-                   "11.212, 11.267, 11.755",\
-                   "11.264, 11.319, 11.806");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.605, 0.629, 0.98",\
-                   "0.605, 0.629, 0.979",\
-                   "0.604, 0.628, 0.973");
-            }
-            fall_transition(CELL_TABLE) {
-            values("11.17, 11.175, 1.284",\
-                   "11.167, 11.173, 1.284",\
-                   "11.173, 11.179, 11.473");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("2.1762222222222225");
-            }
-            fall_power(scalar){
-                values("2.1762222222222225");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("2.167955555555556");
-            }
-            fall_power(scalar){
-                values("2.167955555555556");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("9.6875"); 
-            }
-            fall_constraint(scalar) {
-                values("9.6875"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("19.375"); 
-            }
-            fall_constraint(scalar) {
-                values("19.375"); 
-            }
-         }
-    }
-
-    }
-}
diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
deleted file mode 100644
index c79394e3..00000000
--- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
+++ /dev/null
@@ -1,319 +0,0 @@
-library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 2;
-    bit_from : 0;
-    bit_to : 1;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 4;
-    bit_from : 0;
-    bit_to : 3;
-    }
-
-cell (sram_2_16_1_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 4;
-    word_width : 2;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 142800.38999999998;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.000168;
-    }
-    cell_leakage_power : 0;
-    bus(DIN){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR0; 
-            clocked_on  : clk; 
-        }
-    }
-    bus(DOUT){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR0; 
-        }
-        pin(DOUT[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.54, 0.587, 1.028",\
-                   "0.54, 0.587, 1.028",\
-                   "0.54, 0.587, 1.028");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.54, 0.587, 1.028",\
-                   "0.54, 0.587, 1.028",\
-                   "0.54, 0.587, 1.028");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.024, 0.081, 0.61",\
-                   "0.024, 0.081, 0.61",\
-                   "0.024, 0.081, 0.61");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.024, 0.081, 0.61",\
-                   "0.024, 0.081, 0.61",\
-                   "0.024, 0.081, 0.61");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("10.559086132533329");
-            }
-            fall_power(scalar){
-                values("10.559086132533329");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("10.559086132533329");
-            }
-            fall_power(scalar){
-                values("10.559086132533329");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("0.0"); 
-            }
-            fall_constraint(scalar) {
-                values("0.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("0"); 
-            }
-            fall_constraint(scalar) {
-                values("0"); 
-            }
-         }
-    }
-
-    }
-}
diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
deleted file mode 100644
index ff297ad2..00000000
--- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
+++ /dev/null
@@ -1,319 +0,0 @@
-library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 2;
-    bit_from : 0;
-    bit_to : 1;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 4;
-    bit_from : 0;
-    bit_to : 3;
-    }
-
-cell (sram_2_16_1_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 4;
-    word_width : 2;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 142800.38999999998;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.0252988;
-    }
-    cell_leakage_power : 0;
-    bus(DIN){
-        bus_type  : DATA; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-    }
-    bus(DOUT){
-        bus_type  : DATA; 
-        direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DOUT[1:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : rising_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.928, 0.959, 1.113",\
-                   "0.931, 0.962, 1.116",\
-                   "0.985, 1.018, 1.176");
-            }
-            cell_fall(CELL_TABLE) {
-            values("11.214, 11.27, 11.756",\
-                   "11.22, 11.27, 11.761",\
-                   "11.268, 11.323, 11.809");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.599, 0.624, 0.968",\
-                   "0.599, 0.623, 0.97",\
-                   "0.598, 0.623, 0.967");
-            }
-            fall_transition(CELL_TABLE) {
-            values("11.157, 11.165, 11.446",\
-                   "11.159, 11.162, 1.271",\
-                   "11.158, 11.165, 11.47");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[3:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("2.033783461111111");
-            }
-            fall_power(scalar){
-                values("2.033783461111111");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("2.032705683333334");
-            }
-            fall_power(scalar){
-                values("2.032705683333334");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("9.6875"); 
-            }
-            fall_constraint(scalar) {
-                values("9.6875"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("19.375"); 
-            }
-            fall_constraint(scalar) {
-                values("19.375"); 
-            }
-         }
-    }
-
-    }
-}
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
index affdf7a9..7693e7e0 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0[1:0]){
+        pin(DIN0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0[1:0]){
+        pin(DOUT0){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
         direction  : input; 
         capacitance : 9.8242;  
         max_transition       : 0.4;
-        pin(ADDR0[3:0]){
+        pin(ADDR0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
index bb254713..963c15c5 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0[1:0]){
+        pin(DIN0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0[1:0]){
+        pin(DOUT0){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
         direction  : input; 
         capacitance : 9.8242;  
         max_transition       : 0.4;
-        pin(ADDR0[3:0]){
+        pin(ADDR0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
index 2ce6b2e9..c6d2fd1e 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0[1:0]){
+        pin(DIN0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0[1:0]){
+        pin(DOUT0){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
         direction  : input; 
         capacitance : 9.8242;  
         max_transition       : 0.4;
-        pin(ADDR0[3:0]){
+        pin(ADDR0){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 

From b0978e62f37f805c36623322477130a2cc9d9330 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Wed, 9 Jan 2019 12:32:17 -0800
Subject: [PATCH 21/28] removed openram placeholder logo to stage for public
 push

---
 compiler/datasheet/datasheet.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index b459d46c..ce84c22c 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -40,7 +40,7 @@ class datasheet():
             openram_logo = base64.b64encode(image_file.read())
 
 
-        self.html +=   '<a href="https://vlsida.soe.ucsc.edu/"><img src="data:image/png;base64,{0}" alt="VLSIDA"></a><a href="https://vlsida.github.io/OpenRAM"><img src="data:image/png;base64,{1}"="OpenRAM"></a>'.format(str(vlsi_logo)[2:-1],str(openram_logo)[2:-1])
+        self.html +=   '<a href="https://vlsida.soe.ucsc.edu/"><img src="data:image/png;base64,{0}" alt="VLSIDA"></a>'.format(str(vlsi_logo)[2:-1])
          
 
 

From 94a6cbc28b7d8fcaa369379122b44d1dbd96bf87 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 9 Jan 2019 13:44:25 -0800
Subject: [PATCH 22/28] Remove extra bracket in pin blokc

---
 compiler/characterizer/lib.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index f636d846..443b26fb 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -378,7 +378,7 @@ class lib:
         self.lib.write("        direction  : input; \n")
         self.lib.write("        capacitance : {0};  \n".format(tech.spice["dff_in_cap"]))
         self.lib.write("        max_transition       : {0};\n".format(self.slews[-1]))
-        self.lib.write("        pin(ADDR{}])".format(port))
+        self.lib.write("        pin(ADDR{})".format(port))
         self.lib.write("{\n")
         
         self.write_FF_setuphold(port)

From cdef5f0ecb58fe53ff065d63a6031a7bfa92489a Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg+openram@ucsc.edu>
Date: Wed, 9 Jan 2019 16:57:12 -0800
Subject: [PATCH 23/28] Change kbits to bits in output

---
 compiler/globals.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/globals.py b/compiler/globals.py
index 5843e41c..a6360e24 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -414,7 +414,7 @@ def report_status():
         debug.error("Tech name must be specified in config file.")
 
     print("Technology: {0}".format(OPTS.tech_name))
-    print("Total size: {} kbits".format(OPTS.word_size*OPTS.num_words*OPTS.num_banks))
+    print("Total size: {} bits".format(OPTS.word_size*OPTS.num_words*OPTS.num_banks))
     print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
                                                           OPTS.num_words,
                                                           OPTS.num_banks))

From f0ab155172580d12ca30218c8456d48284fb23ae Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 11 Jan 2019 09:51:05 -0800
Subject: [PATCH 24/28] Change dout to negative clock edge relative

---
 compiler/characterizer/lib.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 443b26fb..d65066fd 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -329,7 +329,7 @@ class lib:
         self.lib.write("        timing(){ \n")
         self.lib.write("            timing_sense : non_unate; \n")
         self.lib.write("            related_pin : \"clk{0}\"; \n".format(read_port))
-        self.lib.write("            timing_type : rising_edge; \n")
+        self.lib.write("            timing_type : negative_edge; \n")
         self.lib.write("            cell_rise(CELL_TABLE) {\n")
         self.write_values(self.char_port_results[read_port]["delay_lh"],len(self.loads),"            ")
         self.lib.write("            }\n") # rise delay

From 5de7ff377356e6cf7d4694fc134673a85f6ee198 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 11 Jan 2019 14:15:16 -0800
Subject: [PATCH 25/28] Updated Verilog to have multiport. Added 1rw,1rw/1r
 Verilog testbench.

---
 compiler/base/hierarchy_layout.py             |   3 +-
 compiler/base/hierarchy_spice.py              |   3 +-
 compiler/base/lef.py                          |   3 +-
 compiler/base/verilog.py                      | 185 ++++++++++++++----
 .../example_configs/big_config_scn4m_subm.py  |  14 ++
 .../example_config_1rw_1r_scn4m_subm.py       |  20 ++
 .../example_config_freepdk45.py               |   0
 .../example_config_scn4m_subm.py              |   0
 .../medium_config_scn4m_subm.py               |  14 ++
 compiler/openram.py                           |   2 +-
 compiler/sram.py                              |  11 +-
 compiler/sram_1bank.py                        |   2 +-
 compiler/sram_base.py                         |  10 +-
 compiler/tests/sram_1rw_1r_tb.v               | 143 ++++++++++++++
 compiler/tests/sram_1rw_tb.v                  | 103 ++++++++++
 15 files changed, 459 insertions(+), 54 deletions(-)
 create mode 100644 compiler/example_configs/big_config_scn4m_subm.py
 create mode 100644 compiler/example_configs/example_config_1rw_1r_scn4m_subm.py
 rename compiler/{ => example_configs}/example_config_freepdk45.py (100%)
 rename compiler/{ => example_configs}/example_config_scn4m_subm.py (100%)
 create mode 100644 compiler/example_configs/medium_config_scn4m_subm.py
 create mode 100644 compiler/tests/sram_1rw_1r_tb.v
 create mode 100644 compiler/tests/sram_1rw_tb.v

diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 9843dcef..c35f0709 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -10,7 +10,7 @@ from vector import vector
 from pin_layout import pin_layout
 import lef
 
-class layout(lef.lef):
+class layout():
     """
     Class consisting of a set of objs and instances for a module
     This provides a set of useful generic types for hierarchy
@@ -21,7 +21,6 @@ class layout(lef.lef):
     """
 
     def __init__(self, name):
-        lef.lef.__init__(self, ["metal1", "metal2", "metal3"])
         self.name = name
         self.width = None
         self.height = None
diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index ff87f9a5..3fda8598 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -2,9 +2,8 @@ import debug
 import re
 import os
 import math
-import verilog
 
-class spice(verilog.verilog):
+class spice():
     """
     This provides a set of useful generic types for hierarchy
     management. If a module is a custom designed cell, it will read from
diff --git a/compiler/base/lef.py b/compiler/base/lef.py
index fb790403..270057cb 100644
--- a/compiler/base/lef.py
+++ b/compiler/base/lef.py
@@ -9,7 +9,8 @@ from collections import defaultdict
 class lef:
     """
     SRAM LEF Class open GDS file, read pins information, obstruction
-    and write them to LEF file
+    and write them to LEF file.
+    This is inherited by the sram_base class.
     """
     def __init__(self,layers):
         # LEF db units per micron
diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index c4bbcd0c..7d713eca 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -1,60 +1,165 @@
 import debug
 
 class verilog:
-    """ Create a behavioral Verilog file for simulation."""
-
+    """ 
+    Create a behavioral Verilog file for simulation.
+    This is inherited by the sram_base class.
+    """
+    def __init__(self):
+        pass
+        
     def verilog_write(self,verilog_name):
         """ Write a behavioral Verilog model. """
-        
         self.vf = open(verilog_name, "w")
 
         self.vf.write("// OpenRAM SRAM model\n")
         self.vf.write("// Words: {0}\n".format(self.num_words))
         self.vf.write("// Word size: {0}\n\n".format(self.word_size))
-    
-        self.vf.write("module {0}(DATA,ADDR,CSb,WEb,OEb,clk);\n".format(self.name))
-        self.vf.write("\n")
+
+        self.vf.write("module {0}(\n".format(self.name))
+        for port in self.all_ports:
+            if port in self.readwrite_ports:
+                self.vf.write("// Port {0}: RW\n".format(port))
+            elif port in self.read_ports:
+                self.vf.write("// Port {0}: R\n".format(port))
+            elif port in self.write_ports:
+                self.vf.write("// Port {0}: W\n".format(port))
+            if port in self.readwrite_ports:
+                self.vf.write("    clk{0},csb{0},web{0},ADDR{0},DIN{0},DOUT{0}".format(port))
+            elif port in self.write_ports:
+                self.vf.write("    clk{0},csb{0},ADDR{0},DIN{0}".format(port))
+            elif port in self.read_ports:
+                self.vf.write("    clk{0},csb{0},ADDR{0},DOUT{0}".format(port))
+            # Continue for every port on a new line
+            if port != self.all_ports[-1]:
+                self.vf.write(",\n")
+        self.vf.write("\n  );\n\n")
+        
         self.vf.write("  parameter DATA_WIDTH = {0} ;\n".format(self.word_size))
         self.vf.write("  parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size))
         self.vf.write("  parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n")
+        self.vf.write("  // FIXME: This delay is arbitrary.\n")
         self.vf.write("  parameter DELAY = 3 ;\n")
-        self.vf.write("\n")    
-        self.vf.write("  inout [DATA_WIDTH-1:0] DATA;\n")
-        self.vf.write("  input [ADDR_WIDTH-1:0] ADDR;\n")
-        self.vf.write("  input CSb;             // active low chip select\n")
-        self.vf.write("  input WEb;             // active low write control\n")
-        self.vf.write("  input OEb;             // active output enable\n")
-        self.vf.write("  input clk;             // clock\n")
         self.vf.write("\n")
-        self.vf.write("  reg [DATA_WIDTH-1:0] data_out ;\n")
-        self.vf.write("  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];\n")
+
+        for port in self.all_ports:
+            self.add_inputs_outputs(port)
+
         self.vf.write("\n")
-        self.vf.write("  // Tri-State Buffer control\n")
-        self.vf.write("  // output : When WEb = 1, oeb = 0, csb = 0\n")
-        self.vf.write("  assign DATA = (!CSb && !OEb && WEb) ? data_out : {0}'bz;\n".format(self.word_size))
-        self.vf.write("\n")    
-        self.vf.write("  // Memory Write Block\n")
-        self.vf.write("  // Write Operation : When WEb = 0, CSb = 0\n")
-        self.vf.write("  always @ (posedge clk)\n")
-        self.vf.write("  begin : MEM_WRITE\n")
-        self.vf.write("  if ( !CSb && !WEb ) begin\n")
-        self.vf.write("    mem[ADDR] = DATA;\n")
-        self.vf.write("    $display($time,\" Writing %m ABUS=%b DATA=%b\",ADDR,DATA);\n")
-        self.vf.write("    end\n")
-        self.vf.write("  end\n\n")
-        self.vf.write("\n")    
-        self.vf.write("  // Memory Read Block\n")
-        self.vf.write("  // Read Operation : When WEb = 1, CSb = 0\n")
-        self.vf.write("  always @ (posedge clk)\n")
-        self.vf.write("  begin : MEM_READ\n")
-        self.vf.write("  if (!CSb && WEb) begin\n")
-        self.vf.write("    data_out <= #(DELAY) mem[ADDR];\n")
-        self.vf.write("    $display($time,\" Reading %m ABUS=%b DATA=%b\",ADDR,mem[ADDR]);\n")
-        self.vf.write("    end\n")
-        self.vf.write("  end\n")
+            
+        for port in self.all_ports:
+            self.register_inputs(port)
+
+        # This is the memory array itself
+        self.vf.write("reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];\n")
+
+        for port in self.all_ports:
+            if port in self.write_ports:
+                self.add_write_block(port)
+            if port in self.read_ports:
+                self.add_read_block(port)
+                
         self.vf.write("\n")    
         self.vf.write("endmodule\n")
-
-
         self.vf.close()
 
+
+    def register_inputs(self, port):
+        """
+        Register the control signal, address and data inputs.
+        """
+        self.add_regs(port)
+        self.add_flops(port)
+            
+    def add_regs(self, port):
+        """ 
+        Create the input regs for the given port.
+        """
+        self.vf.write("  reg 			   csb{0}_reg;\n".format(port))
+        if port in self.readwrite_ports:
+            self.vf.write("  reg 			   web{0}_reg;\n".format(port))
+        self.vf.write("  reg [ADDR_WIDTH-1:0]    ADDR{0}_reg;\n".format(port))
+        if port in self.write_ports:
+            self.vf.write("  reg [DATA_WIDTH-1:0]    DIN{0}_reg;\n".format(port))
+        if port in self.read_ports:
+            self.vf.write("  reg [DATA_WIDTH-1:0]    DOUT{0};\n".format(port))
+            
+    def add_flops(self, port):
+        """
+        Add the flop behavior logic for a port.
+        """
+        self.vf.write("\n")
+        self.vf.write("  // All inputs are registers\n")
+        self.vf.write("  always @(posedge clk{0})\n".format(port))
+        self.vf.write("  begin\n")
+        self.vf.write("    csb{0}_reg = csb{0};\n".format(port))
+        if port in self.readwrite_ports:
+            self.vf.write("    web{0}_reg = web{0};\n".format(port))
+        self.vf.write("    ADDR{0}_reg = ADDR{0};\n".format(port))
+        if port in self.write_ports:
+            self.vf.write("    DIN{0}_reg = DIN{0};\n".format(port))
+        if port in self.read_ports:
+            self.vf.write("    DOUT{0} = {1}'bx;\n".format(port,self.word_size))
+        if port in self.readwrite_ports:
+            self.vf.write("    if ( !csb{0}_reg && web{0}_reg ) \n".format(port))
+            self.vf.write("      $display($time,\" Reading %m ADDR{0}=%b DOUT{0}=%b\",ADDR{0}_reg,mem[ADDR{0}_reg]);\n".format(port))
+        elif port in self.read_ports:
+            self.vf.write("    if ( !csb{0}_reg ) \n".format(port))
+            self.vf.write("      $display($time,\" Reading %m ADDR{0}=%b DOUT{0}=%b\",ADDR{0}_reg,mem[ADDR{0}_reg]);\n".format(port))
+            
+        if port in self.readwrite_ports:
+            self.vf.write("    if ( !csb{0}_reg && !web{0}_reg )\n".format(port))
+            self.vf.write("      $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port))
+        elif port in self.write_ports:
+            self.vf.write("    if ( !csb{0}_reg )\n".format(port))
+            self.vf.write("      $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port))
+        self.vf.write("  end\n\n")
+            
+
+    def add_inputs_outputs(self, port):
+        """
+        Add the module input and output declaration for a port.
+        """
+        self.vf.write("  input 		   clk{0};             // clock\n".format(port))
+        self.vf.write("  input 		   csb{0};             // active low chip select\n".format(port))
+        if port in self.readwrite_ports:
+            self.vf.write("  input 		   web{0};             // active low write control\n".format(port))
+        self.vf.write("  input [ADDR_WIDTH-1:0]  ADDR{0};\n".format(port))
+        if port in self.write_ports:
+            self.vf.write("  input [DATA_WIDTH-1:0]  DIN{0};\n".format(port))
+        if port in self.read_ports:
+            self.vf.write("  output [DATA_WIDTH-1:0] DOUT{0};\n".format(port))
+
+    def add_write_block(self, port):
+        """
+        Add a write port block. Multiple simultaneous writes to the same address
+        have arbitrary priority and are not allowed.
+        """
+        self.vf.write("\n")
+        self.vf.write("  // Memory Write Block Port {0}\n".format(port))
+        self.vf.write("  // Write Operation : When web{0} = 0, csb{0} = 0\n".format(port))
+        self.vf.write("  always @ (negedge clk{0})\n".format(port))
+        self.vf.write("  begin : MEM_WRITE{0}\n".format(port))
+        if port in self.readwrite_ports:
+            self.vf.write("    if ( !csb{0}_reg && !web{0}_reg )\n".format(port))
+        else:
+            self.vf.write("    if (!csb{0}_reg)\n".format(port))
+        self.vf.write("        mem[ADDR{0}_reg] = DIN{0}_reg;\n".format(port))
+        self.vf.write("  end\n")
+        
+    def add_read_block(self, port):
+        """
+        Add a read port block.
+        """
+        self.vf.write("\n")
+        self.vf.write("  // Memory Read Block Port {0}\n".format(port))
+        self.vf.write("  // Read Operation : When web{0} = 1, csb{0} = 0\n".format(port))
+        self.vf.write("  always @ (negedge clk{0})\n".format(port))
+        self.vf.write("  begin : MEM_READ{0}\n".format(port))
+        if port in self.readwrite_ports:
+            self.vf.write("    if (!csb{0}_reg && web{0}_reg)\n".format(port))
+        else:
+            self.vf.write("    if (!csb{0}_reg)\n".format(port))
+        self.vf.write("       DOUT{0} <= #(DELAY) mem[ADDR{0}_reg];\n".format(port))
+        self.vf.write("  end\n")
+        
diff --git a/compiler/example_configs/big_config_scn4m_subm.py b/compiler/example_configs/big_config_scn4m_subm.py
new file mode 100644
index 00000000..0f71169b
--- /dev/null
+++ b/compiler/example_configs/big_config_scn4m_subm.py
@@ -0,0 +1,14 @@
+word_size = 8
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [ 5.0 ]
+temperatures = [ 25 ]
+
+output_path = "temp"
+output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
diff --git a/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py
new file mode 100644
index 00000000..4d09cfee
--- /dev/null
+++ b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py
@@ -0,0 +1,20 @@
+word_size = 2
+num_words = 16
+
+bitcell = "bitcell_1rw_1r"
+replica_bitcell = "replica_bitcell_1rw_1r"
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+output_path = "temp"
+output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
diff --git a/compiler/example_config_freepdk45.py b/compiler/example_configs/example_config_freepdk45.py
similarity index 100%
rename from compiler/example_config_freepdk45.py
rename to compiler/example_configs/example_config_freepdk45.py
diff --git a/compiler/example_config_scn4m_subm.py b/compiler/example_configs/example_config_scn4m_subm.py
similarity index 100%
rename from compiler/example_config_scn4m_subm.py
rename to compiler/example_configs/example_config_scn4m_subm.py
diff --git a/compiler/example_configs/medium_config_scn4m_subm.py b/compiler/example_configs/medium_config_scn4m_subm.py
new file mode 100644
index 00000000..5faebb58
--- /dev/null
+++ b/compiler/example_configs/medium_config_scn4m_subm.py
@@ -0,0 +1,14 @@
+word_size = 16
+num_words = 256
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [ 3.3 ]
+temperatures = [ 25 ]
+
+output_path = "temp"
+output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
diff --git a/compiler/openram.py b/compiler/openram.py
index 9c98037c..78241f6a 100755
--- a/compiler/openram.py
+++ b/compiler/openram.py
@@ -50,7 +50,7 @@ print("Words per row: {}".format(c.words_per_row))
 output_extensions = ["sp","v","lib","py","html"]
 if not OPTS.netlist_only:
     output_extensions.extend(["gds","lef"])
-output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in output_extensions]
+output_files = ["{0}{1}.{2}".format(OPTS.output_path,OPTS.output_name,x) for x in output_extensions]
 print("Output files are: ")
 print(*output_files,sep="\n")
 
diff --git a/compiler/sram.py b/compiler/sram.py
index 47e5176a..4971de08 100644
--- a/compiler/sram.py
+++ b/compiler/sram.py
@@ -48,6 +48,9 @@ class sram():
     def sp_write(self,name):
         self.s.sp_write(name)
 
+    def lef_write(self,name):
+        self.s.lef_write(name)
+
     def gds_write(self,name):
         self.s.gds_write(name)
 
@@ -63,21 +66,21 @@ class sram():
             start_time = datetime.datetime.now()
             gdsname = OPTS.output_path + self.s.name + ".gds"
             print("GDS: Writing to {0}".format(gdsname))
-            self.s.gds_write(gdsname)
+            self.gds_write(gdsname)
             print_time("GDS", datetime.datetime.now(), start_time)
 
             # Create a LEF physical model
             start_time = datetime.datetime.now()
             lefname = OPTS.output_path + self.s.name + ".lef"
             print("LEF: Writing to {0}".format(lefname))
-            self.s.lef_write(lefname)
+            self.lef_write(lefname)
             print_time("LEF", datetime.datetime.now(), start_time)
         
         # Save the spice file
         start_time = datetime.datetime.now()
         spname = OPTS.output_path + self.s.name + ".sp"
         print("SP: Writing to {0}".format(spname))
-        self.s.sp_write(spname)
+        self.sp_write(spname)
         print_time("Spice writing", datetime.datetime.now(), start_time)
 
         # Save the extracted spice file
@@ -126,5 +129,5 @@ class sram():
         start_time = datetime.datetime.now()
         vname = OPTS.output_path + self.s.name + ".v"
         print("Verilog: Writing to {0}".format(vname))
-        self.s.verilog_write(vname)
+        self.verilog_write(vname)
         print_time("Verilog", datetime.datetime.now(), start_time)
diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py
index 6b2caf30..cbfec653 100644
--- a/compiler/sram_1bank.py
+++ b/compiler/sram_1bank.py
@@ -21,7 +21,7 @@ class sram_1bank(sram_base):
     """
     def __init__(self, name, sram_config):
         sram_base.__init__(self, name, sram_config)
-        
+            
     def create_modules(self):
         """ 
         This adds the modules for a single bank SRAM with control
diff --git a/compiler/sram_base.py b/compiler/sram_base.py
index 9e2b6e2a..b51ebae9 100644
--- a/compiler/sram_base.py
+++ b/compiler/sram_base.py
@@ -8,14 +8,18 @@ from vector import vector
 from globals import OPTS, print_time
 import logical_effort
 from design import design
-        
-class sram_base(design):
+from verilog import verilog
+from lef import lef
+
+class sram_base(design, verilog, lef):
     """
     Dynamically generated SRAM by connecting banks to control logic. The
     number of banks should be 1 , 2 or 4
     """
     def __init__(self, name, sram_config):
         design.__init__(self, name)
+        lef.__init__(self, ["metal1", "metal2", "metal3"])
+        verilog.__init__(self)
         
         self.sram_config = sram_config
         sram_config.set_local_config(self)
@@ -531,4 +535,4 @@ class sram_base(design):
         return bank_sen_cin
     
     
-      
\ No newline at end of file
+      
diff --git a/compiler/tests/sram_1rw_1r_tb.v b/compiler/tests/sram_1rw_1r_tb.v
new file mode 100644
index 00000000..9c212e0a
--- /dev/null
+++ b/compiler/tests/sram_1rw_1r_tb.v
@@ -0,0 +1,143 @@
+`define assert(signal, value) \
+if (!(signal === value)) begin \
+   $display("ASSERTION FAILED in %m: signal != value"); \
+   $finish;\
+end
+
+module sram_1rw_1r_tb;
+   reg 	     clk;
+   
+   // 1rw port
+   reg [3:0] addr0;
+   reg [1:0] din0;
+   reg 	     csb0;
+   reg 	     web0;
+   wire [1:0] dout0;
+
+   // 1r port
+   reg [3:0] addr1;
+   reg 	     csb1;
+   wire [1:0] dout1;
+   
+   sram_1rw_1r_2_16_scn4m_subm U0 (.DIN0(din0),
+				   .DOUT0(dout0),
+				   .ADDR0(addr0),
+				   .csb0(csb0), 
+				   .web0(web0), 
+				   .clk0(clk),
+				   .DOUT1(dout1),
+				   .ADDR1(addr1),
+				   .csb1(csb1),
+				   .clk1(clk)
+				   ); 
+
+   
+   initial 
+     begin
+	
+	//$monitor("%g addr0=%b din0=%b dout0=%b addr1=%b dout1=%b",
+	//	 $time, addr0, din0, dout0, addr1, dout1);
+
+	clk = 1;
+	csb0 = 1;
+	web0 = 1;
+	addr0 = 0;
+	din0 = 0;
+
+	csb1 = 1;
+	addr1 = 0;
+
+	// write 
+	#10 din0=2'b10;
+	addr0=4'h1;
+	web0 = 0;
+	csb0 = 0;
+	// nop
+	csb1 = 1;
+	addr1 = 0;
+	
+	// write another
+	#10 din0=2'b01;
+	addr0=4'hC;
+	web0 = 0;
+	csb0 = 0;
+	// read last
+	csb1 = 0;
+	addr1 = 4'h1;
+
+	#10 `assert(dout1, 2'b10)
+	
+	// read undefined	
+	din0=2'b11;
+	addr0=4'h0;	
+	web0 = 1;
+	csb0 = 0;
+	// read another
+	csb1 = 0;
+	addr1 = 4'hC;
+	
+	#10 `assert(dout0, 2'bxx)
+	`assert(dout1, 2'b01)	
+
+	// read defined
+	din0=2'b11;
+	addr0=4'hC;	
+	web0 = 1;
+	csb0 = 0;
+	// read undefined
+	csb1 = 0;
+	addr1 = 4'hD;
+
+	#10 `assert(dout0, 2'b01)
+	`assert(dout1, 2'bxx)	
+	
+	// write another
+	din0=2'b11;
+	addr0=4'hA;
+	web0 = 0;
+	csb0 = 0;
+	// read the feedthrough value
+	csb1 = 0;
+	addr1 = 4'hA;
+
+	#10 `assert(dout1, 2'b11)
+	
+	// read defined
+	din0=2'b11;
+	addr0=4'h1;	
+	web0 = 1;
+	csb0 = 0;
+	// read old value
+	csb1 = 0;
+	addr1 = 4'h1;
+
+	#10 `assert(dout0, 2'b10)
+	`assert(dout1, 2'b10)
+	
+	// read defined
+	din0=2'b11;
+	addr0=4'hA;	
+	web0 = 1;
+	csb0 = 0;
+	// dual read
+	csb1 = 0;
+	addr1 = 4'hA;
+	#10 `assert(dout0, 2'b11)
+	`assert(dout1, 2'b11)	
+	
+	// read undefined	
+	din0=2'b11;
+	addr0=4'h0;	
+	web0 = 1;
+	csb0 = 0;
+
+	#10 `assert(dout0, 2'bxx)
+	
+	#10 $finish;
+	
+  end 
+    
+  always 
+    #5 clk = !clk; 
+    
+endmodule 
diff --git a/compiler/tests/sram_1rw_tb.v b/compiler/tests/sram_1rw_tb.v
new file mode 100644
index 00000000..31f120e8
--- /dev/null
+++ b/compiler/tests/sram_1rw_tb.v
@@ -0,0 +1,103 @@
+`define assert(signal, value) \
+if (!(signal === value)) begin \
+   $display("ASSERTION FAILED in %m: signal != value"); \
+   $finish;\
+end
+	  
+module sram_1rw_tb; 
+   reg 	     clk;
+   
+   reg [3:0] addr0;
+   reg [1:0] din0;
+   reg 	     csb0;
+   reg 	     web0;
+   wire [1:0] dout0;
+
+   sram_2_16_scn4m_subm U0 (.DIN0(din0),
+			    .DOUT0(dout0),
+			    .ADDR0(addr0),
+			    .csb0(csb0), 
+			    .web0(web0), 
+			    .clk0(clk)
+			     ); 
+
+   
+   initial 
+     begin
+	
+	//$monitor("%g addr0=%b din0=%b dout0=%b",
+	//	 $time, addr0, din0, dout0);
+
+
+	clk = 1;
+	csb0 = 1;
+	web0 = 1;
+	addr0 = 0;
+	din0 = 0;
+
+	// write 
+	#10 din0=2'b10;
+	addr0=4'h1;
+	web0 = 0;
+	csb0 = 0;
+	
+	// write another
+	#10 din0=2'b01;
+	addr0=4'hC;
+	web0 = 0;
+	csb0 = 0;
+
+	// read undefined	
+	#10 din0=2'b11;
+	addr0=4'h0;	
+	web0 = 1;
+	csb0 = 0;
+	
+	#10 `assert(dout0, 2'bxx)
+
+	// read defined
+	din0=2'b11;
+	addr0=4'hC;	
+	web0 = 1;
+	csb0 = 0;
+
+	#10 `assert(dout0, 2'b01)
+	
+	// write another
+	din0=2'b11;
+	addr0=4'hA;
+	web0 = 0;
+	csb0 = 0;
+
+	// read defined
+	#10 din0=2'b11;
+	addr0=4'h1;	
+	web0 = 1;
+	csb0 = 0;
+
+	#10 `assert(dout0, 2'b10)
+	
+	// read defined
+	din0=2'b11;
+	addr0=4'hA;	
+	web0 = 1;
+	csb0 = 0;
+	  
+	#10 `assert(dout0, 2'b11)
+	
+	// read undefined	
+	din0=2'b11;
+	addr0=4'h0;	
+	web0 = 1;
+	csb0 = 0;
+
+	#10 `assert(dout0, 2'bxx)
+	
+	#10 $finish;
+	
+  end 
+    
+  always 
+    #5 clk = !clk; 
+    
+endmodule 

From 20b869f8e166c20ec36bfe7a9b4845965d0efb38 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 11 Jan 2019 14:16:57 -0800
Subject: [PATCH 26/28] Remove tabs

---
 compiler/base/verilog.py | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index 7d713eca..a2ddcadf 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -75,14 +75,14 @@ class verilog:
         """ 
         Create the input regs for the given port.
         """
-        self.vf.write("  reg 			   csb{0}_reg;\n".format(port))
+        self.vf.write("  reg  csb{0}_reg;\n".format(port))
         if port in self.readwrite_ports:
-            self.vf.write("  reg 			   web{0}_reg;\n".format(port))
-        self.vf.write("  reg [ADDR_WIDTH-1:0]    ADDR{0}_reg;\n".format(port))
+            self.vf.write("  reg  web{0}_reg;\n".format(port))
+        self.vf.write("  reg [ADDR_WIDTH-1:0]  ADDR{0}_reg;\n".format(port))
         if port in self.write_ports:
-            self.vf.write("  reg [DATA_WIDTH-1:0]    DIN{0}_reg;\n".format(port))
+            self.vf.write("  reg [DATA_WIDTH-1:0]  DIN{0}_reg;\n".format(port))
         if port in self.read_ports:
-            self.vf.write("  reg [DATA_WIDTH-1:0]    DOUT{0};\n".format(port))
+            self.vf.write("  reg [DATA_WIDTH-1:0]  DOUT{0};\n".format(port))
             
     def add_flops(self, port):
         """
@@ -120,10 +120,10 @@ class verilog:
         """
         Add the module input and output declaration for a port.
         """
-        self.vf.write("  input 		   clk{0};             // clock\n".format(port))
-        self.vf.write("  input 		   csb{0};             // active low chip select\n".format(port))
+        self.vf.write("  input  clk{0}; // clock\n".format(port))
+        self.vf.write("  input   csb{0}; // active low chip select\n".format(port))
         if port in self.readwrite_ports:
-            self.vf.write("  input 		   web{0};             // active low write control\n".format(port))
+            self.vf.write("  input  web{0}; // active low write control\n".format(port))
         self.vf.write("  input [ADDR_WIDTH-1:0]  ADDR{0};\n".format(port))
         if port in self.write_ports:
             self.vf.write("  input [DATA_WIDTH-1:0]  DIN{0};\n".format(port))

From a7dd62b0e50b124e687499d215bbf64f3c86c07c Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 11 Jan 2019 15:17:27 -0800
Subject: [PATCH 27/28] falling_edge not negative_edge

---
 compiler/characterizer/lib.py                                   | 2 +-
 compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib     | 2 +-
 .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib     | 2 +-
 .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib   | 2 +-
 compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib    | 2 +-
 .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib    | 2 +-
 .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib  | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index d65066fd..7b10eb8f 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -329,7 +329,7 @@ class lib:
         self.lib.write("        timing(){ \n")
         self.lib.write("            timing_sense : non_unate; \n")
         self.lib.write("            related_pin : \"clk{0}\"; \n".format(read_port))
-        self.lib.write("            timing_type : negative_edge; \n")
+        self.lib.write("            timing_type : falling_edge; \n")
         self.lib.write("            cell_rise(CELL_TABLE) {\n")
         self.write_values(self.char_port_results[read_port]["delay_lh"],len(self.loads),"            ")
         self.lib.write("            }\n") # rise delay
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
index 868ed2b2..fc8d2be3 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
@@ -136,7 +136,7 @@ cell (sram_2_16_1_freepdk45){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
-            timing_type : rising_edge; 
+            timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
             values("0.235, 0.235, 0.239",\
                    "0.235, 0.236, 0.24",\
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
index 60f4f9b3..afb22057 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
@@ -136,7 +136,7 @@ cell (sram_2_16_1_freepdk45){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
-            timing_type : rising_edge; 
+            timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
             values("0.098, 0.098, 0.098",\
                    "0.098, 0.098, 0.098",\
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
index 4a809be2..b20f10be 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
@@ -136,7 +136,7 @@ cell (sram_2_16_1_freepdk45){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
-            timing_type : rising_edge; 
+            timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
             values("0.233, 0.233, 0.237",\
                    "0.233, 0.234, 0.237",\
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
index 7693e7e0..d6fc30aa 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
@@ -136,7 +136,7 @@ cell (sram_2_16_1_scn4m_subm){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
-            timing_type : rising_edge; 
+            timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
             values("1.556, 1.576, 1.751",\
                    "1.559, 1.579, 1.754",\
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
index 963c15c5..5c56ab1e 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
@@ -136,7 +136,7 @@ cell (sram_2_16_1_scn4m_subm){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
-            timing_type : rising_edge; 
+            timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
             values("0.268, 0.268, 0.268",\
                    "0.268, 0.268, 0.268",\
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
index c6d2fd1e..64340a5b 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
@@ -136,7 +136,7 @@ cell (sram_2_16_1_scn4m_subm){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
-            timing_type : rising_edge; 
+            timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
             values("1.542, 1.562, 1.738",\
                    "1.545, 1.565, 1.741",\

From e210ef2a4109fd6e8e946ab3d38db9624376aaa8 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 11 Jan 2019 16:42:50 -0800
Subject: [PATCH 28/28] Add assert to lef and verilog unit test. Fix verilog
 files in golden results.

---
 compiler/tests/24_lef_sram_test.py            |  5 +-
 compiler/tests/25_verilog_sram_test.py        |  4 +-
 compiler/tests/golden/sram_2_16_1_freepdk45.v | 72 +++++++++++--------
 .../tests/golden/sram_2_16_1_scn4m_subm.v     | 72 +++++++++++--------
 4 files changed, 88 insertions(+), 65 deletions(-)

diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py
index 2d90d12b..983038a2 100755
--- a/compiler/tests/24_lef_sram_test.py
+++ b/compiler/tests/24_lef_sram_test.py
@@ -36,10 +36,7 @@ class lef_test(openram_test):
 
         # let's diff the result with a golden model
         golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile)
-        self.isdiff(lefname,golden)
-
-        os.system("rm {0}".format(gdsname))
-        os.system("rm {0}".format(lefname))
+        self.assertTrue(self.isdiff(lefname,golden))
 
         globals.end_openram()
 
diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py
index 4aa2fce7..f98475b4 100755
--- a/compiler/tests/25_verilog_sram_test.py
+++ b/compiler/tests/25_verilog_sram_test.py
@@ -33,9 +33,7 @@ class verilog_test(openram_test):
 
         # let's diff the result with a golden model
         golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile)
-        self.isdiff(vname,golden)
-
-        os.system("rm {0}".format(vname))
+        self.assertTrue(self.isdiff(vname,golden))
 
         globals.end_openram()
         
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.v b/compiler/tests/golden/sram_2_16_1_freepdk45.v
index 94bd09e2..025350bc 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45.v
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45.v
@@ -2,46 +2,60 @@
 // Words: 16
 // Word size: 2
 
-module sram_2_16_1_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
+module sram_2_16_1_freepdk45(
+// Port 0: RW
+    clk0,csb0,web0,ADDR0,DIN0,DOUT0
+  );
 
   parameter DATA_WIDTH = 2 ;
   parameter ADDR_WIDTH = 4 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
   parameter DELAY = 3 ;
 
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  ADDR0;
+  input [DATA_WIDTH-1:0]  DIN0;
+  output [DATA_WIDTH-1:0] DOUT0;
 
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  ADDR0_reg;
+  reg [DATA_WIDTH-1:0]  DIN0_reg;
+  reg [DATA_WIDTH-1:0]  DOUT0;
 
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    ADDR0_reg = ADDR0;
+    DIN0_reg = DIN0;
+    DOUT0 = 2'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg);
   end
 
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
 
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg )
+        mem[ADDR0_reg] = DIN0_reg;
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       DOUT0 <= #(DELAY) mem[ADDR0_reg];
   end
 
 endmodule
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v
index de4c077c..7017b8a7 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v
@@ -2,46 +2,60 @@
 // Words: 16
 // Word size: 2
 
-module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk);
+module sram_2_16_1_scn4m_subm(
+// Port 0: RW
+    clk0,csb0,web0,ADDR0,DIN0,DOUT0
+  );
 
   parameter DATA_WIDTH = 2 ;
   parameter ADDR_WIDTH = 4 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
   parameter DELAY = 3 ;
 
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  ADDR0;
+  input [DATA_WIDTH-1:0]  DIN0;
+  output [DATA_WIDTH-1:0] DOUT0;
 
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  ADDR0_reg;
+  reg [DATA_WIDTH-1:0]  DIN0_reg;
+  reg [DATA_WIDTH-1:0]  DOUT0;
 
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    ADDR0_reg = ADDR0;
+    DIN0_reg = DIN0;
+    DOUT0 = 2'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg);
   end
 
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
 
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg )
+        mem[ADDR0_reg] = DIN0_reg;
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       DOUT0 <= #(DELAY) mem[ADDR0_reg];
   end
 
 endmodule