diff --git a/compiler/bitcells/col_cap_bitcell_1port.py b/compiler/bitcells/col_cap_bitcell_1port.py
new file mode 100644
index 00000000..5d34e2f5
--- /dev/null
+++ b/compiler/bitcells/col_cap_bitcell_1port.py
@@ -0,0 +1,22 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import debug
+from tech import cell_properties as props
+import bitcell_base
+
+
+class col_cap_bitcell_1port(bitcell_base.bitcell_base):
+    """
+    Column end cap cell. 
+    """
+
+    def __init__(self, name="col_cap_bitcell_1port"):
+        bitcell_base.bitcell_base.__init__(self, name, prop=props.col_cap_1port)
+        debug.info(2, "Create col_cap bitcell 1 port object")
+
+        self.no_instances = True
diff --git a/compiler/bitcells/row_cap_bitcell_1port.py b/compiler/bitcells/row_cap_bitcell_1port.py
new file mode 100644
index 00000000..c82b3782
--- /dev/null
+++ b/compiler/bitcells/row_cap_bitcell_1port.py
@@ -0,0 +1,22 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import debug
+from tech import cell_properties as props
+import bitcell_base
+
+
+class row_cap_bitcell_1port(bitcell_base.bitcell_base):
+    """
+    Row end cap cell. 
+    """
+
+    def __init__(self, name="row_cap_bitcell_1port"):
+        bitcell_base.bitcell_base.__init__(self, name, prop=props.row_cap_1port)
+        debug.info(2, "Create row_cap bitcell 1 port object")
+
+        self.no_instances = True