From 5e8dff1e909b8124cacd61369ebe59be9b627a98 Mon Sep 17 00:00:00 2001 From: mguthaus Date: Fri, 16 Feb 2018 13:54:05 -0800 Subject: [PATCH] Fix unit tests with newest RBL delays. Fix tech problem with new spice models. --- compiler/tests/21_hspice_delay_test.py | 36 ++-- compiler/tests/21_ngspice_delay_test.py | 18 +- compiler/tests/21_ngspice_setuphold_test.py | 8 +- .../tests/golden/sram_2_16_1_freepdk45.lef | 175 +++++------------- .../sram_2_16_1_freepdk45_TT_10V_25C.lib | 24 +-- ...2_16_1_freepdk45_TT_10V_25C_analytical.lib | 162 ++++++++-------- ...ram_2_16_1_freepdk45_TT_10V_25C_pruned.lib | 24 +-- .../tests/golden/sram_2_16_1_scn3me_subm.lef | 174 +++++------------ .../sram_2_16_1_scn3me_subm_TT_50V_25C.lib | 42 ++--- ...m_2_16_1_scn3me_subm_TT_50V_25C_pruned.lib | 30 +-- .../setup_openram_scn3me_subm.py | 2 + 11 files changed, 271 insertions(+), 424 deletions(-) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index d82c2be0..e863b4f6 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,25 +51,25 @@ class timing_sram_test(openram_test): data = d.analyze(probe_address, probe_data,slews,loads) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.0356004, - 'read0_power': 0.0364339, - 'write0_power': 0.0262249, - 'delay1': [0.0572987], - 'delay0': [0.0705677], - 'min_period': 0.41, - 'write1_power': 0.038824700000000004, - 'slew0': [0.028478], - 'slew1': [0.0190058]} + golden_data = {'read1_power': 0.032946500000000004, + 'read0_power': 0.0337812, + 'write0_power': 0.026179099999999997, + 'delay1': [0.0573055], + 'delay0': [0.070554], + 'min_period': 0.205, + 'write1_power': 0.0361529, + 'slew0': [0.0285185], + 'slew1': [0.0190073]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 10.3442, - 'read0_power': 10.5159, - 'write0_power': 6.9292, - 'delay1': [0.6536728], - 'delay0': [0.9019465999999999], - 'min_period': 4.531, - 'write1_power': 11.3108, - 'slew0': [0.8320245], - 'slew1': [0.5897582]} + golden_data = {'read1_power': 9.589, + 'read0_power': 9.7622, + 'write0_power': 6.928400000000001, + 'delay1': [0.6538954], + 'delay0': [0.9019090999999999], + 'min_period': 2.344, + 'write1_power': 10.2578, + 'slew0': [0.8321625], + 'slew1': [0.5896232]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index d0330830..cf821cbb 100644 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -59,15 +59,15 @@ class timing_sram_test(openram_test): 'slew0': [0.035826199999999996], 'slew1': [0.02059459]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 10.31395, - 'read0_power': 10.0321, - 'write0_power': 6.072756, - 'delay1': [1.042564], - 'delay0': [1.412224], - 'min_period': 4.688, - 'write1_power': 10.53758, - 'slew0': [1.355812], - 'slew1': [1.03401]} + golden_data = {'read1_power': 11.416549999999999, + 'read0_power': 11.44908, + 'write0_power': 8.250219, + 'delay1': [0.8018421], + 'delay0': [1.085861], + 'min_period': 2.734, + 'write1_power': 11.718020000000001, + 'slew0': [0.8273725], + 'slew1': [0.5730144]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index e26ce210..2ff97bad 100644 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -40,10 +40,10 @@ class timing_setup_test(openram_test): 'hold_times_HL': [-0.003662109], 'setup_times_HL': [0.008544922]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'setup_times_LH': [0.1855469], - 'hold_times_LH': [-0.009765625], - 'hold_times_HL': [-0.15625], - 'setup_times_HL': [0.12451169999999999]} + golden_data = {'setup_times_LH': [0.07568359], + 'hold_times_LH': [0.008544922], + 'hold_times_HL': [-0.05859374999999999], + 'setup_times_HL': [0.03295898]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.lef b/compiler/tests/golden/sram_2_16_1_freepdk45.lef index b2d656fe..38df91ec 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.lef +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.lef @@ -7,11 +7,11 @@ UNITS END UNITS SITE MacroSite CLASS Core ; - SIZE 21695.0 by 42337.5 ; + SIZE 24385.0 by 42337.5 ; END MacroSite MACRO sram_2_16_1_freepdk45 CLASS BLOCK ; - SIZE 21695.0 BY 42337.5 ; + SIZE 24385.0 BY 42337.5 ; SYMMETRY X Y R90 ; SITE MacroSite ; PIN DATA[0] @@ -4165,12 +4165,15 @@ MACRO sram_2_16_1_freepdk45 RECT 750.0 30905.0 685.0 30970.0 ; RECT 32.5 30615.0 -32.5 31175.0 ; RECT 1377.5 30615.0 1312.5 31175.0 ; - RECT 1377.5 39337.5 1312.5 36955.0 ; + RECT 1377.5 38217.5 1312.5 39645.0 ; RECT 1312.5 33907.5 1025.0 33972.5 ; RECT 1312.5 36317.5 1025.0 36382.5 ; + RECT 1312.5 36597.5 1025.0 36662.5 ; + RECT 1312.5 39007.5 1025.0 39072.5 ; RECT 1377.5 31862.5 935.0 31927.5 ; RECT 935.0 31862.5 230.0 31927.5 ; RECT 20.0 35112.5 935.0 35177.5 ; + RECT 20.0 37802.5 935.0 37867.5 ; RECT 20.0 32422.5 935.0 32487.5 ; RECT 2005.0 33435.0 1940.0 34135.0 ; RECT 2005.0 33627.5 1940.0 33692.5 ; @@ -4210,11 +4213,11 @@ MACRO sram_2_16_1_freepdk45 RECT 2330.0 33497.5 2465.0 33562.5 ; RECT 2330.0 33497.5 2465.0 33562.5 ; RECT 2330.0 33307.5 2465.0 33372.5 ; - RECT 1312.5 39272.5 1377.5 39337.5 ; - RECT 4002.5 39272.5 4067.5 39337.5 ; - RECT 1312.5 39175.0 1377.5 39305.0 ; - RECT 1345.0 39272.5 4035.0 39337.5 ; - RECT 4002.5 39175.0 4067.5 39305.0 ; + RECT 1312.5 38152.5 1377.5 38217.5 ; + RECT 4002.5 38152.5 4067.5 38217.5 ; + RECT 1312.5 38055.0 1377.5 38185.0 ; + RECT 1345.0 38152.5 4035.0 38217.5 ; + RECT 4002.5 38055.0 4067.5 38185.0 ; RECT 2875.0 34562.5 2690.0 34627.5 ; RECT 4035.0 34562.5 3850.0 34627.5 ; RECT 3917.5 34202.5 4067.5 34267.5 ; @@ -4361,90 +4364,6 @@ MACRO sram_2_16_1_freepdk45 RECT 2722.5 37495.0 2657.5 38055.0 ; RECT 4067.5 37495.0 4002.5 38055.0 ; RECT 3340.0 37620.0 3475.0 37685.0 ; - RECT 2875.0 38482.5 2690.0 38547.5 ; - RECT 4035.0 38482.5 3850.0 38547.5 ; - RECT 3917.5 38122.5 4067.5 38187.5 ; - RECT 3032.5 38122.5 2657.5 38187.5 ; - RECT 3917.5 38312.5 3032.5 38377.5 ; - RECT 3032.5 38122.5 2897.5 38187.5 ; - RECT 3032.5 38312.5 2897.5 38377.5 ; - RECT 3032.5 38312.5 2897.5 38377.5 ; - RECT 3032.5 38122.5 2897.5 38187.5 ; - RECT 3917.5 38122.5 3782.5 38187.5 ; - RECT 3917.5 38312.5 3782.5 38377.5 ; - RECT 3917.5 38312.5 3782.5 38377.5 ; - RECT 3917.5 38122.5 3782.5 38187.5 ; - RECT 2942.5 38482.5 2807.5 38547.5 ; - RECT 3917.5 38482.5 3782.5 38547.5 ; - RECT 3475.0 38180.0 3340.0 38245.0 ; - RECT 3475.0 38180.0 3340.0 38245.0 ; - RECT 3440.0 38345.0 3375.0 38410.0 ; - RECT 2722.5 38055.0 2657.5 38615.0 ; - RECT 4067.5 38055.0 4002.5 38615.0 ; - RECT 3340.0 38180.0 3475.0 38245.0 ; - RECT 2875.0 39042.5 2690.0 39107.5 ; - RECT 4035.0 39042.5 3850.0 39107.5 ; - RECT 3917.5 38682.5 4067.5 38747.5 ; - RECT 3032.5 38682.5 2657.5 38747.5 ; - RECT 3917.5 38872.5 3032.5 38937.5 ; - RECT 3032.5 38682.5 2897.5 38747.5 ; - RECT 3032.5 38872.5 2897.5 38937.5 ; - RECT 3032.5 38872.5 2897.5 38937.5 ; - RECT 3032.5 38682.5 2897.5 38747.5 ; - RECT 3917.5 38682.5 3782.5 38747.5 ; - RECT 3917.5 38872.5 3782.5 38937.5 ; - RECT 3917.5 38872.5 3782.5 38937.5 ; - RECT 3917.5 38682.5 3782.5 38747.5 ; - RECT 2942.5 39042.5 2807.5 39107.5 ; - RECT 3917.5 39042.5 3782.5 39107.5 ; - RECT 3475.0 38740.0 3340.0 38805.0 ; - RECT 3475.0 38740.0 3340.0 38805.0 ; - RECT 3440.0 38905.0 3375.0 38970.0 ; - RECT 2722.5 38615.0 2657.5 39175.0 ; - RECT 4067.5 38615.0 4002.5 39175.0 ; - RECT 3340.0 38740.0 3475.0 38805.0 ; - RECT 2505.0 38187.5 2690.0 38122.5 ; - RECT 1345.0 38187.5 1530.0 38122.5 ; - RECT 1462.5 38547.5 1312.5 38482.5 ; - RECT 2347.5 38547.5 2722.5 38482.5 ; - RECT 1462.5 38357.5 2347.5 38292.5 ; - RECT 2347.5 38547.5 2482.5 38482.5 ; - RECT 2347.5 38357.5 2482.5 38292.5 ; - RECT 2347.5 38357.5 2482.5 38292.5 ; - RECT 2347.5 38547.5 2482.5 38482.5 ; - RECT 1462.5 38547.5 1597.5 38482.5 ; - RECT 1462.5 38357.5 1597.5 38292.5 ; - RECT 1462.5 38357.5 1597.5 38292.5 ; - RECT 1462.5 38547.5 1597.5 38482.5 ; - RECT 2437.5 38187.5 2572.5 38122.5 ; - RECT 1462.5 38187.5 1597.5 38122.5 ; - RECT 1905.0 38490.0 2040.0 38425.0 ; - RECT 1905.0 38490.0 2040.0 38425.0 ; - RECT 1940.0 38325.0 2005.0 38260.0 ; - RECT 2657.5 38615.0 2722.5 38055.0 ; - RECT 1312.5 38615.0 1377.5 38055.0 ; - RECT 1905.0 38425.0 2040.0 38490.0 ; - RECT 2505.0 37627.5 2690.0 37562.5 ; - RECT 1345.0 37627.5 1530.0 37562.5 ; - RECT 1462.5 37987.5 1312.5 37922.5 ; - RECT 2347.5 37987.5 2722.5 37922.5 ; - RECT 1462.5 37797.5 2347.5 37732.5 ; - RECT 2347.5 37987.5 2482.5 37922.5 ; - RECT 2347.5 37797.5 2482.5 37732.5 ; - RECT 2347.5 37797.5 2482.5 37732.5 ; - RECT 2347.5 37987.5 2482.5 37922.5 ; - RECT 1462.5 37987.5 1597.5 37922.5 ; - RECT 1462.5 37797.5 1597.5 37732.5 ; - RECT 1462.5 37797.5 1597.5 37732.5 ; - RECT 1462.5 37987.5 1597.5 37922.5 ; - RECT 2437.5 37627.5 2572.5 37562.5 ; - RECT 1462.5 37627.5 1597.5 37562.5 ; - RECT 1905.0 37930.0 2040.0 37865.0 ; - RECT 1905.0 37930.0 2040.0 37865.0 ; - RECT 1940.0 37765.0 2005.0 37700.0 ; - RECT 2657.5 38055.0 2722.5 37495.0 ; - RECT 1312.5 38055.0 1377.5 37495.0 ; - RECT 1905.0 37865.0 2040.0 37930.0 ; RECT 2505.0 37067.5 2690.0 37002.5 ; RECT 1345.0 37067.5 1530.0 37002.5 ; RECT 1462.5 37427.5 1312.5 37362.5 ; @@ -4572,24 +4491,32 @@ MACRO sram_2_16_1_freepdk45 RECT 1312.5 34695.0 1377.5 34135.0 ; RECT 1905.0 34505.0 2040.0 34570.0 ; RECT 3340.0 34425.0 3475.0 34490.0 ; - RECT 3340.0 36665.0 3475.0 36730.0 ; - RECT 3340.0 38905.0 3475.0 38970.0 ; - RECT 1905.0 36580.0 2040.0 36645.0 ; + RECT 3340.0 36105.0 3475.0 36170.0 ; + RECT 3340.0 37785.0 3475.0 37850.0 ; + RECT 1905.0 36020.0 2040.0 36085.0 ; RECT 3340.0 34260.0 3475.0 34325.0 ; RECT 1940.0 34135.0 2005.0 34340.0 ; - RECT 2657.5 34135.0 2722.5 39175.0 ; - RECT 1312.5 34135.0 1377.5 39175.0 ; - RECT 4002.5 34135.0 4067.5 39175.0 ; + RECT 2657.5 34135.0 2722.5 38055.0 ; + RECT 1312.5 34135.0 1377.5 38055.0 ; + RECT 4002.5 34135.0 4067.5 38055.0 ; RECT 935.0 33800.0 225.0 32455.0 ; RECT 935.0 33800.0 230.0 35145.0 ; RECT 935.0 36490.0 230.0 35145.0 ; + RECT 935.0 36490.0 230.0 37835.0 ; + RECT 935.0 39180.0 230.0 37835.0 ; RECT 1025.0 33907.5 140.0 33972.5 ; RECT 1025.0 36317.5 140.0 36382.5 ; + RECT 1025.0 36597.5 140.0 36662.5 ; + RECT 1025.0 39007.5 140.0 39072.5 ; RECT 1025.0 35112.5 140.0 35177.5 ; + RECT 1025.0 37802.5 140.0 37867.5 ; RECT 1025.0 33767.5 140.0 33832.5 ; RECT 1025.0 36457.5 140.0 36522.5 ; + RECT 1025.0 39147.5 140.0 39212.5 ; RECT 1345.0 33872.5 1280.0 34007.5 ; RECT 1345.0 36282.5 1280.0 36417.5 ; + RECT 1345.0 36562.5 1280.0 36697.5 ; + RECT 1345.0 38972.5 1280.0 39107.5 ; RECT 1342.5 34135.0 1277.5 34270.0 ; RECT 1377.5 31760.0 1312.5 31895.0 ; RECT 867.5 31862.5 1002.5 31927.5 ; @@ -4600,7 +4527,7 @@ MACRO sram_2_16_1_freepdk45 RECT 682.5 32030.0 817.5 32095.0 ; RECT 3475.0 31335.0 3410.0 34260.0 ; RECT 2005.0 31335.0 1940.0 32100.0 ; - RECT 20.0 31335.0 -45.0 36577.5 ; + RECT 20.0 31335.0 -45.0 39267.5 ; RECT 2722.5 31335.0 2657.5 34135.0 ; RECT 1377.5 31335.0 1312.5 31895.0 ; RECT 4067.5 31335.0 4002.5 34135.0 ; @@ -5439,29 +5366,25 @@ MACRO sram_2_16_1_freepdk45 RECT 1610.0 26387.5 1540.0 26252.5 ; RECT 2315.0 25737.5 2245.0 25602.5 ; RECT 2315.0 26387.5 2245.0 26252.5 ; - RECT 1380.0 31895.0 1310.0 36955.0 ; - RECT 970.0 31895.0 900.0 36645.0 ; - RECT 265.0 31895.0 195.0 36645.0 ; + RECT 1380.0 31895.0 1310.0 39645.0 ; + RECT 970.0 31895.0 900.0 39335.0 ; + RECT 265.0 31895.0 195.0 39335.0 ; RECT 1207.5 32062.5 1137.5 32660.0 ; RECT 785.0 32062.5 715.0 32342.5 ; RECT 3372.5 34457.5 3442.5 34852.5 ; RECT 3372.5 34852.5 3442.5 35412.5 ; RECT 3372.5 35412.5 3442.5 35972.5 ; - RECT 3372.5 35972.5 3442.5 36532.5 ; - RECT 3372.5 36697.5 3442.5 37092.5 ; + RECT 3372.5 36137.5 3442.5 36532.5 ; + RECT 3372.5 36532.5 3442.5 37092.5 ; RECT 3372.5 37092.5 3442.5 37652.5 ; - RECT 3372.5 37652.5 3442.5 38212.5 ; - RECT 3372.5 38212.5 3442.5 38772.5 ; - RECT 2655.0 38902.5 2725.0 38972.5 ; - RECT 2655.0 38422.5 2725.0 38492.5 ; - RECT 2690.0 38902.5 3407.5 38972.5 ; - RECT 2655.0 38457.5 2725.0 38937.5 ; - RECT 1972.5 38422.5 2690.0 38492.5 ; - RECT 1937.5 37897.5 2007.5 38457.5 ; - RECT 1937.5 37337.5 2007.5 37897.5 ; + RECT 2655.0 37782.5 2725.0 37852.5 ; + RECT 2655.0 37302.5 2725.0 37372.5 ; + RECT 2690.0 37782.5 3407.5 37852.5 ; + RECT 2655.0 37337.5 2725.0 37817.5 ; + RECT 1972.5 37302.5 2690.0 37372.5 ; RECT 1937.5 36777.5 2007.5 37337.5 ; - RECT 1937.5 36217.5 2007.5 36612.5 ; - RECT 1937.5 35657.5 2007.5 36217.5 ; + RECT 1937.5 36217.5 2007.5 36777.5 ; + RECT 1937.5 35657.5 2007.5 36052.5 ; RECT 1937.5 35097.5 2007.5 35657.5 ; RECT 1937.5 34537.5 2007.5 35097.5 ; RECT 3340.0 34817.5 3475.0 34887.5 ; @@ -5470,10 +5393,6 @@ MACRO sram_2_16_1_freepdk45 RECT 3340.0 36497.5 3475.0 36567.5 ; RECT 3340.0 37057.5 3475.0 37127.5 ; RECT 3340.0 37617.5 3475.0 37687.5 ; - RECT 3340.0 38177.5 3475.0 38247.5 ; - RECT 3340.0 38737.5 3475.0 38807.5 ; - RECT 1905.0 38422.5 2040.0 38492.5 ; - RECT 1905.0 37862.5 2040.0 37932.5 ; RECT 1905.0 37302.5 2040.0 37372.5 ; RECT 1905.0 36742.5 2040.0 36812.5 ; RECT 1905.0 36182.5 2040.0 36252.5 ; @@ -5481,18 +5400,22 @@ MACRO sram_2_16_1_freepdk45 RECT 1905.0 35062.5 2040.0 35132.5 ; RECT 1905.0 34502.5 2040.0 34572.5 ; RECT 3340.0 34422.5 3475.0 34492.5 ; - RECT 3340.0 36662.5 3475.0 36732.5 ; - RECT 3340.0 38902.5 3475.0 38972.5 ; - RECT 1905.0 36577.5 2040.0 36647.5 ; + RECT 3340.0 36102.5 3475.0 36172.5 ; + RECT 3340.0 37782.5 3475.0 37852.5 ; + RECT 1905.0 36017.5 2040.0 36087.5 ; RECT 935.0 33800.0 225.0 32455.0 ; RECT 935.0 33800.0 230.0 35145.0 ; RECT 935.0 36490.0 230.0 35145.0 ; - RECT 785.0 33700.0 715.0 36645.0 ; - RECT 450.0 33700.0 380.0 36645.0 ; - RECT 970.0 33700.0 900.0 36645.0 ; - RECT 265.0 33700.0 195.0 36645.0 ; + RECT 935.0 36490.0 230.0 37835.0 ; + RECT 935.0 39180.0 230.0 37835.0 ; + RECT 785.0 33700.0 715.0 39335.0 ; + RECT 450.0 33700.0 380.0 39335.0 ; + RECT 970.0 33700.0 900.0 39335.0 ; + RECT 265.0 33700.0 195.0 39335.0 ; RECT 1347.5 33872.5 1277.5 34007.5 ; RECT 1347.5 36282.5 1277.5 36417.5 ; + RECT 1347.5 36562.5 1277.5 36697.5 ; + RECT 1347.5 38972.5 1277.5 39107.5 ; RECT 1345.0 34135.0 1275.0 34270.0 ; RECT 1380.0 31760.0 1310.0 31895.0 ; RECT 867.5 31860.0 1002.5 31930.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C.lib index 68458eba..30ae4d23 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 918.5120625; + area : 1032.3999375; bus(DATA){ bus_type : DATA; @@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("0.042347092"); + values("0.039688322"); } fall_power(scalar){ - values("0.029908723"); + values("0.029868294"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("0.054779642"); + values("0.049703133"); } fall_power(scalar){ - values("0.060081573"); + values("0.055020041"); } } timing(){ @@ -145,9 +145,9 @@ cell (sram_2_16_1_freepdk45){ "0.061, 0.062, 0.069"); } cell_fall(CELL_TABLE) { - values("0.522, 0.523, 0.533",\ - "0.523, 0.524, 0.533",\ - "0.528, 0.529, 0.539"); + values("0.429, 0.43, 0.439",\ + "0.429, 0.431, 0.439",\ + "0.435, 0.436, 0.446"); } rise_transition(CELL_TABLE) { values("0.013, 0.015, 0.026",\ @@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("0.5275"); + values("0.4295"); } fall_constraint(scalar) { - values("0.5275"); + values("0.4295"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("1.055"); + values("0.859"); } fall_constraint(scalar) { - values("1.055"); + values("0.859"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_analytical.lib index 22715e9f..e9d059e4 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_analytical.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 918.5120625; + area : 1032.3999375; bus(DATA){ bus_type : DATA; @@ -92,47 +92,47 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("0.039115101"); + values("0"); } fall_power(scalar){ - values("0.026662611"); + values("0"); } } timing(){ timing_type : setup_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("0.036300681"); + values("0"); } fall_power(scalar){ - values("0.041472985"); + values("0"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.054, 0.055, 0.061",\ - "0.055, 0.055, 0.062",\ - "0.06, 0.061, 0.067"); + values("0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133"); } cell_fall(CELL_TABLE) { - values("0.519, 0.52, 0.529",\ - "0.519, 0.52, 0.53",\ - "0.525, 0.526, 0.535"); + values("0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133"); } rise_transition(CELL_TABLE) { - values("0.013, 0.014, 0.026",\ - "0.013, 0.014, 0.026",\ - "0.013, 0.015, 0.026"); + values("0.006, 0.007, 0.018",\ + "0.006, 0.007, 0.018",\ + "0.006, 0.007, 0.018"); } fall_transition(CELL_TABLE) { - values("0.027, 0.029, 0.043",\ - "0.027, 0.029, 0.043",\ - "0.027, 0.029, 0.043"); + values("0.006, 0.007, 0.018",\ + "0.006, 0.007, 0.018",\ + "0.006, 0.007, 0.018"); } } } @@ -174,28 +174,28 @@ cell (sram_2_16_1_freepdk45){ timing_type : setup_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } @@ -208,28 +208,28 @@ cell (sram_2_16_1_freepdk45){ timing_type : setup_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } @@ -241,28 +241,28 @@ cell (sram_2_16_1_freepdk45){ timing_type : setup_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } @@ -274,28 +274,28 @@ cell (sram_2_16_1_freepdk45){ timing_type : setup_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021",\ - "0.009, 0.015, 0.021"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); } } timing(){ timing_type : hold_rising; related_pin : "clk"; rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("0.5275"); + values("0.0"); } fall_constraint(scalar) { - values("0.5275"); + values("0.0"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("1.055"); + values("0.0"); } fall_constraint(scalar) { - values("1.055"); + values("0.0"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_pruned.lib index 22715e9f..50b0949f 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_pruned.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 918.5120625; + area : 1032.3999375; bus(DATA){ bus_type : DATA; @@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("0.039115101"); + values("0.036463566"); } fall_power(scalar){ - values("0.026662611"); + values("0.026623993"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("0.036300681"); + values("0.033688925"); } fall_power(scalar){ - values("0.041472985"); + values("0.038865319"); } } timing(){ @@ -145,9 +145,9 @@ cell (sram_2_16_1_freepdk45){ "0.06, 0.061, 0.067"); } cell_fall(CELL_TABLE) { - values("0.519, 0.52, 0.529",\ - "0.519, 0.52, 0.53",\ - "0.525, 0.526, 0.535"); + values("0.425, 0.426, 0.436",\ + "0.426, 0.427, 0.436",\ + "0.432, 0.433, 0.442"); } rise_transition(CELL_TABLE) { values("0.013, 0.014, 0.026",\ @@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("0.5275"); + values("0.4295"); } fall_constraint(scalar) { - values("0.5275"); + values("0.4295"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("1.055"); + values("0.859"); } fall_constraint(scalar) { - values("1.055"); + values("0.859"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef index 7a2a54f2..c634c07b 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef @@ -7,11 +7,11 @@ UNITS END UNITS SITE MacroSite CLASS Core ; - SIZE 277800.0 by 440700.0 ; + SIZE 305400.0 by 440700.0 ; END MacroSite MACRO sram_2_16_1_scn3me_subm CLASS BLOCK ; - SIZE 277800.0 BY 440700.0 ; + SIZE 305400.0 BY 440700.0 ; SYMMETRY X Y R90 ; SITE MacroSite ; PIN DATA[0] @@ -4105,12 +4105,15 @@ MACRO sram_2_16_1_scn3me_subm RECT 16050.0 358350.0 15150.0 359250.0 ; RECT 8850.0 353400.0 7950.0 363000.0 ; RECT 22650.0 353400.0 21750.0 363000.0 ; - RECT 22650.0 499050.0 21750.0 430200.0 ; + RECT 22650.0 479850.0 21750.0 457800.0 ; RECT 21750.0 397050.0 17400.0 397950.0 ; RECT 21750.0 420450.0 17400.0 421350.0 ; + RECT 21750.0 424650.0 17400.0 425550.0 ; + RECT 21750.0 448050.0 17400.0 448950.0 ; RECT 22650.0 371550.0 16800.0 372450.0 ; RECT 16800.0 371550.0 6600.0 372450.0 ; RECT 4500.0 408600.0 16800.0 409500.0 ; + RECT 4500.0 436200.0 16800.0 437100.0 ; RECT 4500.0 381000.0 16800.0 381900.0 ; RECT 29250.0 397800.0 28350.0 410400.0 ; RECT 29250.0 392850.0 28350.0 393750.0 ; @@ -4150,11 +4153,11 @@ MACRO sram_2_16_1_scn3me_subm RECT 32550.0 398400.0 33750.0 399600.0 ; RECT 32550.0 398400.0 33750.0 399600.0 ; RECT 32550.0 396000.0 33750.0 397200.0 ; - RECT 21750.0 498150.0 22650.0 499050.0 ; - RECT 49350.0 498150.0 50250.0 499050.0 ; - RECT 21750.0 496800.0 22650.0 498600.0 ; - RECT 22200.0 498150.0 49800.0 499050.0 ; - RECT 49350.0 496800.0 50250.0 498600.0 ; + RECT 21750.0 478950.0 22650.0 479850.0 ; + RECT 49350.0 478950.0 50250.0 479850.0 ; + RECT 21750.0 477600.0 22650.0 479400.0 ; + RECT 22200.0 478950.0 49800.0 479850.0 ; + RECT 49350.0 477600.0 50250.0 479400.0 ; RECT 37950.0 417000.0 36000.0 418200.0 ; RECT 49800.0 417000.0 47850.0 418200.0 ; RECT 48450.0 412200.0 50250.0 413400.0 ; @@ -4301,90 +4304,6 @@ MACRO sram_2_16_1_scn3me_subm RECT 36450.0 468000.0 35550.0 477600.0 ; RECT 50250.0 468000.0 49350.0 477600.0 ; RECT 42600.0 470400.0 43800.0 471600.0 ; - RECT 37950.0 484200.0 36000.0 485400.0 ; - RECT 49800.0 484200.0 47850.0 485400.0 ; - RECT 48450.0 479400.0 50250.0 480600.0 ; - RECT 39150.0 479400.0 35550.0 480600.0 ; - RECT 48450.0 482100.0 39150.0 483000.0 ; - RECT 39150.0 479400.0 37950.0 480600.0 ; - RECT 39150.0 481800.0 37950.0 483000.0 ; - RECT 39150.0 481800.0 37950.0 483000.0 ; - RECT 39150.0 479400.0 37950.0 480600.0 ; - RECT 48450.0 479400.0 47250.0 480600.0 ; - RECT 48450.0 481800.0 47250.0 483000.0 ; - RECT 48450.0 481800.0 47250.0 483000.0 ; - RECT 48450.0 479400.0 47250.0 480600.0 ; - RECT 38550.0 484200.0 37350.0 485400.0 ; - RECT 48450.0 484200.0 47250.0 485400.0 ; - RECT 43800.0 480000.0 42600.0 481200.0 ; - RECT 43800.0 480000.0 42600.0 481200.0 ; - RECT 43650.0 482550.0 42750.0 483450.0 ; - RECT 36450.0 477600.0 35550.0 487200.0 ; - RECT 50250.0 477600.0 49350.0 487200.0 ; - RECT 42600.0 480000.0 43800.0 481200.0 ; - RECT 37950.0 493800.0 36000.0 495000.0 ; - RECT 49800.0 493800.0 47850.0 495000.0 ; - RECT 48450.0 489000.0 50250.0 490200.0 ; - RECT 39150.0 489000.0 35550.0 490200.0 ; - RECT 48450.0 491700.0 39150.0 492600.0 ; - RECT 39150.0 489000.0 37950.0 490200.0 ; - RECT 39150.0 491400.0 37950.0 492600.0 ; - RECT 39150.0 491400.0 37950.0 492600.0 ; - RECT 39150.0 489000.0 37950.0 490200.0 ; - RECT 48450.0 489000.0 47250.0 490200.0 ; - RECT 48450.0 491400.0 47250.0 492600.0 ; - RECT 48450.0 491400.0 47250.0 492600.0 ; - RECT 48450.0 489000.0 47250.0 490200.0 ; - RECT 38550.0 493800.0 37350.0 495000.0 ; - RECT 48450.0 493800.0 47250.0 495000.0 ; - RECT 43800.0 489600.0 42600.0 490800.0 ; - RECT 43800.0 489600.0 42600.0 490800.0 ; - RECT 43650.0 492150.0 42750.0 493050.0 ; - RECT 36450.0 487200.0 35550.0 496800.0 ; - RECT 50250.0 487200.0 49350.0 496800.0 ; - RECT 42600.0 489600.0 43800.0 490800.0 ; - RECT 34050.0 480600.0 36000.0 479400.0 ; - RECT 22200.0 480600.0 24150.0 479400.0 ; - RECT 23550.0 485400.0 21750.0 484200.0 ; - RECT 32850.0 485400.0 36450.0 484200.0 ; - RECT 23550.0 482700.0 32850.0 481800.0 ; - RECT 32850.0 485400.0 34050.0 484200.0 ; - RECT 32850.0 483000.0 34050.0 481800.0 ; - RECT 32850.0 483000.0 34050.0 481800.0 ; - RECT 32850.0 485400.0 34050.0 484200.0 ; - RECT 23550.0 485400.0 24750.0 484200.0 ; - RECT 23550.0 483000.0 24750.0 481800.0 ; - RECT 23550.0 483000.0 24750.0 481800.0 ; - RECT 23550.0 485400.0 24750.0 484200.0 ; - RECT 33450.0 480600.0 34650.0 479400.0 ; - RECT 23550.0 480600.0 24750.0 479400.0 ; - RECT 28200.0 484800.0 29400.0 483600.0 ; - RECT 28200.0 484800.0 29400.0 483600.0 ; - RECT 28350.0 482250.0 29250.0 481350.0 ; - RECT 35550.0 487200.0 36450.0 477600.0 ; - RECT 21750.0 487200.0 22650.0 477600.0 ; - RECT 28200.0 483600.0 29400.0 484800.0 ; - RECT 34050.0 471000.0 36000.0 469800.0 ; - RECT 22200.0 471000.0 24150.0 469800.0 ; - RECT 23550.0 475800.0 21750.0 474600.0 ; - RECT 32850.0 475800.0 36450.0 474600.0 ; - RECT 23550.0 473100.0 32850.0 472200.0 ; - RECT 32850.0 475800.0 34050.0 474600.0 ; - RECT 32850.0 473400.0 34050.0 472200.0 ; - RECT 32850.0 473400.0 34050.0 472200.0 ; - RECT 32850.0 475800.0 34050.0 474600.0 ; - RECT 23550.0 475800.0 24750.0 474600.0 ; - RECT 23550.0 473400.0 24750.0 472200.0 ; - RECT 23550.0 473400.0 24750.0 472200.0 ; - RECT 23550.0 475800.0 24750.0 474600.0 ; - RECT 33450.0 471000.0 34650.0 469800.0 ; - RECT 23550.0 471000.0 24750.0 469800.0 ; - RECT 28200.0 475200.0 29400.0 474000.0 ; - RECT 28200.0 475200.0 29400.0 474000.0 ; - RECT 28350.0 472650.0 29250.0 471750.0 ; - RECT 35550.0 477600.0 36450.0 468000.0 ; - RECT 21750.0 477600.0 22650.0 468000.0 ; - RECT 28200.0 474000.0 29400.0 475200.0 ; RECT 34050.0 461400.0 36000.0 460200.0 ; RECT 22200.0 461400.0 24150.0 460200.0 ; RECT 23550.0 466200.0 21750.0 465000.0 ; @@ -4512,22 +4431,29 @@ MACRO sram_2_16_1_scn3me_subm RECT 21750.0 420000.0 22650.0 410400.0 ; RECT 28200.0 416400.0 29400.0 417600.0 ; RECT 42600.0 415200.0 43800.0 416400.0 ; - RECT 42600.0 453600.0 43800.0 454800.0 ; - RECT 42600.0 492000.0 43800.0 493200.0 ; - RECT 28200.0 452400.0 29400.0 453600.0 ; + RECT 42600.0 444000.0 43800.0 445200.0 ; + RECT 42600.0 472800.0 43800.0 474000.0 ; + RECT 28200.0 442800.0 29400.0 444000.0 ; RECT 42600.0 412800.0 43800.0 414000.0 ; RECT 28350.0 410400.0 29250.0 414150.0 ; - RECT 35550.0 410400.0 36450.0 496800.0 ; - RECT 21750.0 410400.0 22650.0 496800.0 ; - RECT 49350.0 410400.0 50250.0 496800.0 ; + RECT 35550.0 410400.0 36450.0 477600.0 ; + RECT 21750.0 410400.0 22650.0 477600.0 ; + RECT 49350.0 410400.0 50250.0 477600.0 ; RECT 16800.0 395400.0 6600.0 381600.0 ; RECT 16800.0 395400.0 6600.0 409200.0 ; RECT 16800.0 423000.0 6600.0 409200.0 ; + RECT 16800.0 423000.0 6600.0 436800.0 ; + RECT 16800.0 450600.0 6600.0 436800.0 ; RECT 17400.0 396900.0 6000.0 398100.0 ; RECT 17400.0 420300.0 6000.0 421500.0 ; + RECT 17400.0 424500.0 6000.0 425700.0 ; + RECT 17400.0 447900.0 6000.0 449100.0 ; RECT 17400.0 408600.0 6000.0 409500.0 ; + RECT 17400.0 436200.0 6000.0 437100.0 ; RECT 22350.0 396900.0 21150.0 398100.0 ; RECT 22350.0 420300.0 21150.0 421500.0 ; + RECT 22350.0 424500.0 21150.0 425700.0 ; + RECT 22350.0 447900.0 21150.0 449100.0 ; RECT 22200.0 410400.0 21000.0 411600.0 ; RECT 22800.0 370800.0 21600.0 372000.0 ; RECT 16200.0 371400.0 17400.0 372600.0 ; @@ -4538,7 +4464,7 @@ MACRO sram_2_16_1_scn3me_subm RECT 12600.0 375600.0 13800.0 376800.0 ; RECT 43800.0 362400.0 42900.0 412800.0 ; RECT 29250.0 362400.0 28350.0 375750.0 ; - RECT 4500.0 362400.0 3600.0 425250.0 ; + RECT 4500.0 362400.0 3600.0 452850.0 ; RECT 36450.0 362400.0 35550.0 410400.0 ; RECT 22650.0 362400.0 21750.0 372000.0 ; RECT 50250.0 362400.0 49350.0 410400.0 ; @@ -5348,29 +5274,25 @@ MACRO sram_2_16_1_scn3me_subm RECT 10800.0 288450.0 9600.0 287250.0 ; RECT 31200.0 263100.0 30000.0 261900.0 ; RECT 31200.0 288450.0 30000.0 287250.0 ; - RECT 22650.0 372000.0 21750.0 430200.0 ; - RECT 17250.0 372000.0 16350.0 425400.0 ; - RECT 7050.0 372000.0 6150.0 425400.0 ; + RECT 22650.0 372000.0 21750.0 457800.0 ; + RECT 17250.0 372000.0 16350.0 453000.0 ; + RECT 7050.0 372000.0 6150.0 453000.0 ; RECT 20400.0 376200.0 19500.0 384300.0 ; RECT 13650.0 376200.0 12750.0 381000.0 ; RECT 42750.0 415800.0 43650.0 423000.0 ; RECT 42750.0 423000.0 43650.0 432600.0 ; RECT 42750.0 432600.0 43650.0 442200.0 ; - RECT 42750.0 442200.0 43650.0 451800.0 ; - RECT 42750.0 454200.0 43650.0 461400.0 ; + RECT 42750.0 444600.0 43650.0 451800.0 ; + RECT 42750.0 451800.0 43650.0 461400.0 ; RECT 42750.0 461400.0 43650.0 471000.0 ; - RECT 42750.0 471000.0 43650.0 480600.0 ; - RECT 42750.0 480600.0 43650.0 490200.0 ; - RECT 35550.0 492150.0 36450.0 493050.0 ; - RECT 35550.0 483750.0 36450.0 484650.0 ; - RECT 36000.0 492150.0 43200.0 493050.0 ; - RECT 35550.0 484200.0 36450.0 492600.0 ; - RECT 28800.0 483750.0 36000.0 484650.0 ; - RECT 28350.0 474600.0 29250.0 484200.0 ; - RECT 28350.0 465000.0 29250.0 474600.0 ; + RECT 35550.0 472950.0 36450.0 473850.0 ; + RECT 35550.0 464550.0 36450.0 465450.0 ; + RECT 36000.0 472950.0 43200.0 473850.0 ; + RECT 35550.0 465000.0 36450.0 473400.0 ; + RECT 28800.0 464550.0 36000.0 465450.0 ; RECT 28350.0 455400.0 29250.0 465000.0 ; - RECT 28350.0 445800.0 29250.0 453000.0 ; - RECT 28350.0 436200.0 29250.0 445800.0 ; + RECT 28350.0 445800.0 29250.0 455400.0 ; + RECT 28350.0 436200.0 29250.0 443400.0 ; RECT 28350.0 426600.0 29250.0 436200.0 ; RECT 28350.0 417000.0 29250.0 426600.0 ; RECT 42600.0 422400.0 43800.0 423600.0 ; @@ -5379,10 +5301,6 @@ MACRO sram_2_16_1_scn3me_subm RECT 42600.0 451200.0 43800.0 452400.0 ; RECT 42600.0 460800.0 43800.0 462000.0 ; RECT 42600.0 470400.0 43800.0 471600.0 ; - RECT 42600.0 480000.0 43800.0 481200.0 ; - RECT 42600.0 489600.0 43800.0 490800.0 ; - RECT 28200.0 483600.0 29400.0 484800.0 ; - RECT 28200.0 474000.0 29400.0 475200.0 ; RECT 28200.0 464400.0 29400.0 465600.0 ; RECT 28200.0 454800.0 29400.0 456000.0 ; RECT 28200.0 445200.0 29400.0 446400.0 ; @@ -5390,18 +5308,22 @@ MACRO sram_2_16_1_scn3me_subm RECT 28200.0 426000.0 29400.0 427200.0 ; RECT 28200.0 416400.0 29400.0 417600.0 ; RECT 42600.0 415200.0 43800.0 416400.0 ; - RECT 42600.0 453600.0 43800.0 454800.0 ; - RECT 42600.0 492000.0 43800.0 493200.0 ; - RECT 28200.0 452400.0 29400.0 453600.0 ; + RECT 42600.0 444000.0 43800.0 445200.0 ; + RECT 42600.0 472800.0 43800.0 474000.0 ; + RECT 28200.0 442800.0 29400.0 444000.0 ; RECT 16800.0 395400.0 6600.0 381600.0 ; RECT 16800.0 395400.0 6600.0 409200.0 ; RECT 16800.0 423000.0 6600.0 409200.0 ; - RECT 13800.0 396000.0 12600.0 426600.0 ; - RECT 10800.0 394800.0 9600.0 425400.0 ; - RECT 17400.0 394800.0 16200.0 425400.0 ; - RECT 7200.0 394800.0 6000.0 425400.0 ; + RECT 16800.0 423000.0 6600.0 436800.0 ; + RECT 16800.0 450600.0 6600.0 436800.0 ; + RECT 13800.0 396000.0 12600.0 454200.0 ; + RECT 10800.0 394800.0 9600.0 453000.0 ; + RECT 17400.0 394800.0 16200.0 453000.0 ; + RECT 7200.0 394800.0 6000.0 453000.0 ; RECT 22350.0 396900.0 21150.0 398100.0 ; RECT 22350.0 420300.0 21150.0 421500.0 ; + RECT 22350.0 424500.0 21150.0 425700.0 ; + RECT 22350.0 447900.0 21150.0 449100.0 ; RECT 22200.0 410400.0 21000.0 411600.0 ; RECT 22800.0 370800.0 21600.0 372000.0 ; RECT 16200.0 371400.0 17400.0 372600.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C.lib index b6fc4525..7b2aae89 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 122426.46; + area : 134589.78; bus(DATA){ bus_type : DATA; @@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("11.756062"); + values("11.763876"); } fall_power(scalar){ - values("7.1840422"); + values("8.1710129"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("10.730552"); + values("12.162858"); } fall_power(scalar){ - values("10.584523"); + values("10.926647"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.458, 0.503, 0.87",\ - "0.461, 0.505, 0.873",\ - "0.5, 0.544, 0.911"); + values("0.473, 0.519, 0.888",\ + "0.476, 0.522, 0.891",\ + "0.516, 0.56, 0.928"); } cell_fall(CELL_TABLE) { - values("0.573, 0.649, 1.249",\ - "0.576, 0.651, 1.252",\ - "0.616, 0.69, 1.289"); + values("0.582, 0.655, 1.256",\ + "0.585, 0.658, 1.259",\ + "0.625, 0.697, 1.295"); } rise_transition(CELL_TABLE) { - values("0.153, 0.232, 1.084",\ - "0.153, 0.233, 1.084",\ - "0.156, 0.236, 1.084"); + values("0.154, 0.233, 1.086",\ + "0.155, 0.234, 1.086",\ + "0.158, 0.237, 1.086"); } fall_transition(CELL_TABLE) { - values("0.277, 0.355, 1.499",\ - "0.277, 0.357, 1.499",\ - "0.278, 0.362, 1.499"); + values("0.278, 0.359, 1.499",\ + "0.278, 0.361, 1.499",\ + "0.28, 0.367, 1.5"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_scn3me_subm){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("2.344"); + values("1.875"); } fall_constraint(scalar) { - values("2.344"); + values("1.875"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("4.688"); + values("3.75"); } fall_constraint(scalar) { - values("4.688"); + values("3.75"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_pruned.lib index b6fc4525..077c4cfc 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_pruned.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 122426.46; + area : 134589.78; bus(DATA){ bus_type : DATA; @@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("11.756062"); + values("10.4925"); } fall_power(scalar){ - values("7.1840422"); + values("7.1836643"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("10.730552"); + values("10.203608"); } fall_power(scalar){ - values("10.584523"); + values("10.057386"); } } timing(){ @@ -145,9 +145,9 @@ cell (sram_2_16_1_scn3me_subm){ "0.5, 0.544, 0.911"); } cell_fall(CELL_TABLE) { - values("0.573, 0.649, 1.249",\ - "0.576, 0.651, 1.252",\ - "0.616, 0.69, 1.289"); + values("0.573, 0.645, 1.246",\ + "0.576, 0.648, 1.249",\ + "0.616, 0.687, 1.286"); } rise_transition(CELL_TABLE) { values("0.153, 0.232, 1.084",\ @@ -155,9 +155,9 @@ cell (sram_2_16_1_scn3me_subm){ "0.156, 0.236, 1.084"); } fall_transition(CELL_TABLE) { - values("0.277, 0.355, 1.499",\ - "0.277, 0.357, 1.499",\ - "0.278, 0.362, 1.499"); + values("0.277, 0.36, 1.499",\ + "0.277, 0.362, 1.499",\ + "0.278, 0.37, 1.5"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_scn3me_subm){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("2.344"); + values("1.875"); } fall_constraint(scalar) { - values("2.344"); + values("1.875"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("4.688"); + values("3.75"); } fall_constraint(scalar) { - values("4.688"); + values("3.75"); } } } diff --git a/technology/setup_scripts/setup_openram_scn3me_subm.py b/technology/setup_scripts/setup_openram_scn3me_subm.py index 7fa4dbf9..e763007c 100644 --- a/technology/setup_scripts/setup_openram_scn3me_subm.py +++ b/technology/setup_scripts/setup_openram_scn3me_subm.py @@ -20,6 +20,7 @@ os.environ["MGC_TMPDIR"] = "/tmp" ########################### # OpenRAM Paths + try: DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME")) except: @@ -30,6 +31,7 @@ os.environ["DRCLVS_HOME"] = DRCLVS_HOME # try: # SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) # except: +OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) ##########################