From c31d71bf238c58f37a28a484468d34a9753bc81c Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Mon, 23 Nov 2020 16:43:48 -0800 Subject: [PATCH 01/78] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index d6b948ef..a63d00eb 100644 --- a/README.md +++ b/README.md @@ -169,7 +169,7 @@ The default for openram.py is specified in the configuration file. # Porting to a New Technology -If you want to support a enw technology, you will need to create: +If you want to support a new technology, you will need to create: + a setup script for each technology you want to use + a technology directory for each technology with the base cells From 028d2a2954a48d2ebab77157af0156950dfc29c8 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 15 Dec 2020 10:56:45 -0800 Subject: [PATCH 02/78] v1.1.10 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index a18c6119..32cca4ec 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.9" +VERSION = "1.1.10" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 0bd169708cf2c2eaffe22d5d7df81f7827c4d94a Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 15 Dec 2020 14:38:54 -0800 Subject: [PATCH 03/78] v1.1.11 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 32cca4ec..5e96dc5a 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.10" +VERSION = "1.1.11" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From bcd837205b1abfd8d16c3003a14202d98393d54a Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 18 Dec 2020 13:05:42 -0800 Subject: [PATCH 04/78] v1.1.12 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 5e96dc5a..20bd1d68 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.11" +VERSION = "1.1.12" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 81220068f71776fea7032ceaf30f691e118f7b3f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 23 Dec 2020 11:59:54 -0800 Subject: [PATCH 05/78] v1.1.13 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 07820c83..00f1a2da 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.12" +VERSION = "1.1.13" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From f428ff4bfd01e719a6ff9caeebf7f45678c3cb77 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 7 Jan 2021 10:33:21 -0800 Subject: [PATCH 06/78] v1.1.14 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 00f1a2da..7ec3ed15 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.13" +VERSION = "1.1.14" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From b0c27225838ab78ca038cd44db9704de150ba1b6 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 19 Jan 2021 15:22:50 -0800 Subject: [PATCH 07/78] Changed lib file to only contain reference to the operating voltage and removed nominal voltage references. --- compiler/characterizer/lib.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index e5628c5d..9040f2e3 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,10 +224,6 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") - self.lib.write(" nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"])) - self.lib.write(" nom_temperature : {};\n".format(tech.spice["nom_temperature"])) - self.lib.write(" nom_process : {};\n".format(1.0)) - self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") @@ -238,7 +234,7 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") - self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"])) + self.lib.write(" voltage_map ( VDD, {} );\n".format(self.voltage)) self.lib.write(" voltage_map ( GND, 0 );\n\n") def create_list(self,values): From 31ad1963f67499a30d3235c67059d1fbd8f7ec14 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 12:47:18 -0800 Subject: [PATCH 08/78] Removed nominal pvt corners from golden lib files. --- .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 --- .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 --- 10 files changed, 30 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index b3ef0e0a..6ba1e114 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 34be4fe4..2bde8e2b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cca9c1ed..82231d5d 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 26028892..3f79ce08 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index 5817211b..bdaeab71 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index 6912aec7..c9d811b4 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index a7605cb3..605f88cc 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 7b649d0d..0616f75e 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From d1b240dfb5859bf5710e60b4d37d100201672f3f Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 13:52:55 -0800 Subject: [PATCH 09/78] Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files. --- compiler/characterizer/lib.py | 3 +++ .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 +++ 11 files changed, 33 insertions(+) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 9040f2e3..05db4147 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,6 +224,9 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") + self.lib.write(" nom_voltage : {};\n".format(self.voltage)) + self.lib.write(" nom_temperature : {};\n".format(self.temperature)) + self.lib.write(" nom_process : 1.0;\n") self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index 6ba1e114..b3ef0e0a 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 2bde8e2b..34be4fe4 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index 82231d5d..cca9c1ed 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 3f79ce08..26028892 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index bdaeab71..5817211b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index c9d811b4..6912aec7 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index 605f88cc..a7605cb3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 0616f75e..7b649d0d 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From 3dfc039f6f287e3e014dca80abcac25c73d40829 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Tue, 9 Feb 2021 09:32:35 +0100 Subject: [PATCH 10/78] add technology option passtrough in test 30 --- compiler/tests/30_openram_back_end_test.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index f88f5670..3bda98f1 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -46,6 +46,9 @@ class openram_back_end_test(openram_test): if OPTS.spice_name: options += " -s {}".format(OPTS.spice_name) + if OPTS.tech_name: + options += " -t {}".format(OPTS.tech_name) + # Always perform code coverage if OPTS.coverage == 0: debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") From d14a68847e31ff58900c7e57051a29cd04e97ad3 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Tue, 9 Feb 2021 13:09:26 +0100 Subject: [PATCH 11/78] added cell label checker and cell labels to the freepdk technology --- .gitignore | 1 + compiler/base/geometry.py | 4 +++- technology/freepdk45/gds_lib/cell_1rw.gds | Bin 19116 -> 20480 bytes 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 3d6e4f92..e31298d6 100644 --- a/.gitignore +++ b/.gitignore @@ -10,3 +10,4 @@ **/model_data outputs technology/freepdk45/ncsu_basekit +.idea diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index debeceee..0f970747 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -359,7 +359,9 @@ class instance(geometry): for offset in range(len(normalized_br_offsets)): for port in range(len(br_names)): cell_br_meta.append([br_names[offset], row, col, port]) - + + if normalized_storage_nets == []: + debug.error("normalized storage nets should not be empty! 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zb~2rR8-K*l@u!aC?=&6kd42g=oYwK?i`<7dU*&&V$_`rpJF=BpR~SbYKC_J$9%H-3mglzs5#ujhZPp1-`cH?$z1IFx^ADf{5bL(jiG z8Mz(bfdVb@29v)WXej&by}8@d+b>0iNG6L5bq2n(ns5i=<(c6;+ zTxW!izuchSD0@=h?<%%3QGTJLew596nf zaf`C&^voNtBdKHFMA--W&F=cgC-u|A(2?H(u?9Aj{cx}UD}DFb&NZqDk1+QE0V zAKA%V{;l1{k6MnOQ}%iK)%ah|^>4r2zX&Tt8NN?j4uUUtG7fPG5%WxBYShb!z0k32#ws|3u23tY7BOYmoQ9<<`%=*00v@ wy<5LI_WF4Ju!j62JDI+JFLC~Sxx0UZx8}c%FQK0C5t{~VD|vQb!)Fry3m2V+LI3~& From 1c6de4591dc4e9078b22721aba58ee62087f4186 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Feb 2021 13:32:00 -0800 Subject: [PATCH 12/78] Remove vertical power pin vias. --- compiler/modules/sense_amp_array.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index c26347c6..01b74c84 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -146,10 +146,10 @@ class sense_amp_array(design.design): inst = self.local_insts[i] for gnd_pin in inst.get_pins("gnd"): - self.copy_power_pin(gnd_pin, directions=("V", "V")) + self.copy_power_pin(gnd_pin) for vdd_pin in inst.get_pins("vdd"): - self.copy_power_pin(vdd_pin, directions=("V", "V")) + self.copy_power_pin(vdd_pin) bl_pin = inst.get_pin(inst.mod.get_bl_names()) br_pin = inst.get_pin(inst.mod.get_br_names()) From 549112fcf88fc3e925a3241dff209d50b5be4c15 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Feb 2021 13:32:13 -0800 Subject: [PATCH 13/78] PEP8 cleanup --- compiler/router/direction.py | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/compiler/router/direction.py b/compiler/router/direction.py index 8237f679..c13abdd3 100644 --- a/compiler/router/direction.py +++ b/compiler/router/direction.py @@ -7,6 +7,8 @@ # from enum import Enum from vector3d import vector3d +import debug + class direction(Enum): NORTH = 1 @@ -20,31 +22,30 @@ class direction(Enum): SOUTHEAST = 9 SOUTHWEST = 10 - def get_offset(direct): """ Returns the vector offset for a given direction. """ if direct==direction.NORTH: - offset = vector3d(0,1,0) + offset = vector3d(0, 1, 0) elif direct==direction.SOUTH: - offset = vector3d(0,-1,0) + offset = vector3d(0, -1 ,0) elif direct==direction.EAST: - offset = vector3d(1,0,0) + offset = vector3d(1, 0, 0) elif direct==direction.WEST: - offset = vector3d(-1,0,0) + offset = vector3d(-1, 0, 0) elif direct==direction.UP: - offset = vector3d(0,0,1) + offset = vector3d(0, 0, 1) elif direct==direction.DOWN: - offset = vector3d(0,0,-1) + offset = vector3d(0, 0, -1) elif direct==direction.NORTHEAST: - offset = vector3d(1,1,0) + offset = vector3d(1, 1, 0) elif direct==direction.NORTHWEST: - offset = vector3d(-1,1,0) + offset = vector3d(-1, 1, 0) elif direct==direction.SOUTHEAST: - offset = vector3d(1,-1,0) + offset = vector3d(1, -1, 0) elif direct==direction.SOUTHWEST: - offset = vector3d(-1,-1,0) + offset = vector3d(-1, -1, 0) else: debug.error("Invalid direction {}".format(direct)) @@ -67,8 +68,8 @@ class direction(Enum): return [direction.get_offset(d) for d in direction.all_directions()] def all_neighbors(cell): - return [cell+x for x in direction.all_offsets()] + return [cell + x for x in direction.all_offsets()] def cardinal_neighbors(cell): - return [cell+x for x in direction.cardinal_offsets()] + return [cell + x for x in direction.cardinal_offsets()] From 013836bb3d66e5857feb281ffe53978ef34f3629 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Feb 2021 13:33:14 -0800 Subject: [PATCH 14/78] PEP8 cleanup --- compiler/router/supply_tree_router.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index ff65b4f9..0b29119d 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -37,12 +37,12 @@ class supply_tree_router(router): """ Route the two nets in a single layer) """ - debug.info(1,"Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) + debug.info(1, "Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) self.vdd_name = vdd_name self.gnd_name = gnd_name # Clear the pins if we have previously routed - if (hasattr(self,'rg')): + if (hasattr(self, 'rg')): self.clear_pins() else: # Creat a routing grid over the entire area @@ -53,14 +53,14 @@ class supply_tree_router(router): # Get the pin shapes start_time = datetime.now() self.find_pins_and_blockages([self.vdd_name, self.gnd_name]) - print_time("Finding pins and blockages",datetime.now(), start_time, 3) + print_time("Finding pins and blockages", datetime.now(), start_time, 3) # Route the supply pins to the supply rails # Route vdd first since we want it to be shorter start_time = datetime.now() self.route_pins(vdd_name) self.route_pins(gnd_name) - print_time("Maze routing supplies",datetime.now(), start_time, 3) + print_time("Maze routing supplies", datetime.now(), start_time, 3) # self.write_debug_gds("final_tree_router.gds",False) @@ -79,11 +79,11 @@ class supply_tree_router(router): """ remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name]) - debug.info(1,"Routing {0} with {1} pin components to connect.".format(pin_name, - remaining_components)) + debug.info(1, "Routing {0} with {1} pin components to connect.".format(pin_name, + remaining_components)) # Create full graph - debug.info(2,"Creating adjacency matrix") + debug.info(2, "Creating adjacency matrix") pin_size = len(self.pin_groups[pin_name]) adj_matrix = [[0] * pin_size for i in range(pin_size)] @@ -95,7 +95,7 @@ class supply_tree_router(router): adj_matrix[index1][index2] = dist # Find MST - debug.info(2,"Finding MinimumSpanning Tree") + debug.info(2, "Finding MinimumSpanning Tree") X = csr_matrix(adj_matrix) Tcsr = minimum_spanning_tree(X) mst = Tcsr.toarray().astype(int) @@ -144,6 +144,7 @@ class supply_tree_router(router): self.add_pin_component_source(pin_name, src_idx) # Marks all pin components except index as target + # which unmarks it as a blockage too self.add_pin_component_target(pin_name, dest_idx) # Actually run the A* router From 2a9b5db6d47c11e4205479e56c431978f7f327a0 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 11:14:08 -0800 Subject: [PATCH 15/78] Rewrite enclose grids to be cleaner --- compiler/router/pin_group.py | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 01a8b074..5f9da465 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -34,7 +34,6 @@ class pin_group: # Remove any redundant pins (i.e. contained in other pins) self.remove_redundant_pins() - self.router = router # These are the corresponding pin grids for each pin group. self.grids = set() @@ -101,13 +100,11 @@ class pin_group: if local_debug: debug.info(0, "INITIAL: {}".format(pin_list)) - new_pin_list = pin_list.copy() - - remove_indices = set() + add_indices = set(range(len(pin_list))) # This is n^2, but the number is small for index1, pin1 in enumerate(pin_list): # If we remove this pin, it can't contain other pins - if index1 in remove_indices: + if index1 not in add_indices: continue for index2, pin2 in enumerate(pin_list): @@ -117,17 +114,15 @@ class pin_group: if index1 == index2: continue # If we already removed it, can't remove it again... - if index2 in remove_indices: + if index2 not in add_indices: continue if pin1.contains(pin2): if local_debug: debug.info(0, "{0} contains {1}".format(pin1, pin2)) - remove_indices.add(index2) + add_indices.remove(index2) - # Remove them in decreasing order to not invalidate the indices - for i in sorted(remove_indices, reverse=True): - del new_pin_list[i] + new_pin_list = [pin_list[x] for x in add_indices] if local_debug: debug.info(0, "FINAL : {}".format(new_pin_list)) @@ -423,13 +418,15 @@ class pin_group: # We may have started with an empty set debug.check(len(self.grids) > 0, "Cannot seed an grid empty set.") + common_blockages = self.router.get_blocked_grids() & self.grids + # Start with the ll and make the widest row row = [ll] # Move in dir1 while we can while True: next_cell = row[-1] + offset1 # Can't move if not in the pin shape - if next_cell in self.grids and next_cell not in self.router.get_blocked_grids(): + if next_cell in self.grids and next_cell not in common_blockages: row.append(next_cell) else: break @@ -438,7 +435,7 @@ class pin_group: next_row = [x + offset2 for x in row] for cell in next_row: # Can't move if any cell is not in the pin shape - if cell not in self.grids or cell in self.router.get_blocked_grids(): + if cell not in self.grids or cell in common_blockages: break else: row = next_row @@ -619,6 +616,11 @@ class pin_group: # Set of track adjacent to or paritally overlap a pin (not full DRC connection) partial_set = set() + # for pin in self.pins: + # lx = pin.lx() + # ly = pin.by() + # if lx > 87.9 and lx < 87.99 and ly > 18.56 and ly < 18.6: + # breakpoint() for pin in self.pins: debug.info(4, " Converting {0}".format(pin)) # Determine which tracks the pin overlaps @@ -632,7 +634,8 @@ class pin_group: blockage_in_tracks = self.router.convert_blockage(pin) # Must include the pins here too because these are computed in a different # way than blockages. - self.blockages.update(sufficient | insufficient | blockage_in_tracks) + blockages = sufficient | insufficient | blockage_in_tracks + self.blockages.update(blockages) # If we have a blockage, we must remove the grids # Remember, this excludes the pin blockages already From 9f0ab0d081f6a9904dfe591be5831d8084195cc4 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 11:14:39 -0800 Subject: [PATCH 16/78] Route perimeter signals before power grid --- compiler/sram/sram_1bank.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index be3e16e8..d831c047 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -325,13 +325,13 @@ class sram_1bank(sram_base): # they might create some blockages self.add_layout_pins() - # Route the supplies first since the MST is not blockage aware - # and signals can route to anywhere on sides (it is flexible) - self.route_supplies() - # Route the pins to the perimeter if OPTS.perimeter_pins: self.route_escape_pins() + + # Route the supplies first since the MST is not blockage aware + # and signals can route to anywhere on sides (it is flexible) + self.route_supplies() def route_dffs(self, add_routes=True): From 0c2ed487d9dcc4abb7e7331b8d86476a83c5ca29 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 11:16:19 -0800 Subject: [PATCH 17/78] Redundant check if pin contains another --- compiler/router/router.py | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index cd20d858..8da1d265 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -504,14 +504,21 @@ class router(router_tech): ll = vector(boundary[0], boundary[1]) ur = vector(boundary[2], boundary[3]) rect = [ll, ur] - new_pin = pin_layout("blockage{}".format(len(self.blockages)), - rect, - lpp) + new_shape = pin_layout("blockage{}".format(len(self.blockages)), + rect, + lpp) + # If there is a rectangle that is the same in the pins, # it isn't a blockage! - if new_pin not in self.all_pins: - self.blockages.append(new_pin) + if new_shape not in self.all_pins and not self.pin_contains(new_shape): + self.blockages.append(new_shape) + def pin_contains(self, shape): + for pin in self.all_pins: + if pin.contains(shape): + return True + return False + def convert_point_to_units(self, p): """ Convert a path set of tracks to center line path. From dc3c293575eab2a782ccc8f4430f19f024aa314c Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 16:17:45 -0800 Subject: [PATCH 18/78] Add temp workspace path --- .github/workflows/ci.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6a7cd73b..9a09f511 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -11,14 +11,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t scn4m_subm + export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: $OPENRAM_TMP/ + path: ${{ github.workspace }}/scn4me_subm/ freepdk45: runs-on: self-hosted steps: @@ -29,14 +29,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t freepdk45 + export OPENRAM_TMP="${{ github.workspace }}/freepdk45" + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: $OPENRAM_TMP/ + path: ${{ github.workspace }}/freepdk45/ coverage: if: ${{ always() }} needs: [scn4me_subm, freepdk45] From a57a443a4c95502fc0e73c8a2eb6f98c18065bbc Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 16:31:41 -0800 Subject: [PATCH 19/78] Change coverage report location --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 9a09f511..6d55448b 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -46,10 +46,10 @@ jobs: run: | python3-coverage combine python3-coverage report - python3-coverage html -d coverage_html + python3-coverage html -d ${{ github.workspace }}/coverage_html - name: Archive coverage uses: actions/upload-artifact@v2 with: name: code-coverage-report - path: coverage_html/ + path: ${{ github.workspace }}/coverage_html/ From 8403749fec41b070596d98f2f10eb16a14b525f4 Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 18:27:08 -0500 Subject: [PATCH 20/78] Add Q and Qbar labels --- technology/freepdk45/gds_lib/cell_1rw.gds | Bin 19116 -> 20480 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/freepdk45/gds_lib/cell_1rw.gds b/technology/freepdk45/gds_lib/cell_1rw.gds index 38e53e27872bed4854cc2320d02e6eb82977cffc..1a138c4abdc970d88930c04d79afd23c1a36f64b 100644 GIT binary patch literal 20480 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From 15e57d89ca5859227f22fa9a389d4f054ff8f2d2 Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 18:28:07 -0500 Subject: [PATCH 21/78] fix end subckt typo --- technology/freepdk45/sp_lib/dummy_cell_1rw.sp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/technology/freepdk45/sp_lib/dummy_cell_1rw.sp b/technology/freepdk45/sp_lib/dummy_cell_1rw.sp index 9181645a..6057ff1c 100644 --- a/technology/freepdk45/sp_lib/dummy_cell_1rw.sp +++ b/technology/freepdk45/sp_lib/dummy_cell_1rw.sp @@ -11,5 +11,5 @@ MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n * Access transistors MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n -.ENDS cell_1rw +.ENDS dummy_cell_1rw From 48bc47c6868f87d08177838aacc1bcea71edb8fd Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 18:30:57 -0500 Subject: [PATCH 22/78] Set pin label size to use zoom factor from tech specifications --- compiler/base/pin_layout.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index c476c19b..a86aa07b 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -399,6 +399,7 @@ class pin_layout: newLayout.addText(text=self.name, layerNumber=layer_num, purposeNumber=label_purpose, + magnification=GDS["zoom"], offsetInMicrons=self.center()) def compute_overlap(self, other): From 9a2987ad07bc4248438398e12888e5959665164c Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 19:25:00 -0500 Subject: [PATCH 23/78] Add spectre simulator --- compiler/characterizer/charutils.py | 3 +++ compiler/characterizer/delay.py | 3 +++ compiler/characterizer/stimuli.py | 35 ++++++++++++++++++++++++++++- 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py index 4ceafbcf..b618f0db 100644 --- a/compiler/characterizer/charutils.py +++ b/compiler/characterizer/charutils.py @@ -5,6 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import os import re import debug from globals import OPTS @@ -20,6 +21,8 @@ def parse_spice_list(filename, key): if OPTS.spice_name == "xa" : # customsim has a different output file name full_filename="{0}xa.meas".format(OPTS.openram_temp) + elif OPTS.spice_name == "spectre": + full_filename = os.path.join(OPTS.openram_temp, "delay_stim.measure") else: # ngspice/hspice using a .lis file full_filename="{0}{1}.lis".format(OPTS.openram_temp, filename) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index e2d7e1d2..4c7f8f8f 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -387,6 +387,9 @@ class delay(simulation): self.delay_stim_sp = "delay_stim.sp" temp_stim = "{0}/{1}".format(OPTS.openram_temp, self.delay_stim_sp) self.sf = open(temp_stim, "w") + + if OPTS.spice_name == "spectre": + self.sf.write("simulator lang=spice\n") self.sf.write("* Delay stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(self.period, self.load, self.slew)) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 035e9e58..5855f236 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -247,16 +247,39 @@ class stimuli(): timestep = 10 # ps, was 5ps but ngspice was complaining the timestep was too small in certain tests. # UIC is needed for ngspice to converge - self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) + self.sf.write(".TEMP {}\n".format(self.temperature)) if OPTS.spice_name == "ngspice": # ngspice sometimes has convergence problems if not using gear method # which is more accurate, but slower than the default trapezoid method # Do not remove this or it may not converge due to some "pa_00" nodes # unless you figure out what these are. + self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear\n".format(reltol)) + elif OPTS.spice_name == "spectre": + self.sf.write("simulator lang=spectre\n") + if OPTS.use_pex: + nestlvl = 1 + spectre_save = "selected" + else: + nestlvl = 10 + spectre_save = "lvlpub" + self.sf.write('saveOptions options save={} nestlvl={} pwr=total \n'.format( + spectre_save, nestlvl)) + self.sf.write("simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp={0} try_fast_op=no " + "rforce=10m maxnotes=10 maxwarns=10 " + " preservenode=all topcheck=fixall " + "digits=5 cols=80 dc_pivot_check=yes pivrel=1e-3 " + " \n".format(self.temperature)) + self.sf.write('tran tran step={} stop={}n ic=node write=spectre.dc errpreset=moderate ' + ' annotate=status maxiters=5 \n'.format("5p", end_time)) + self.sf.write("simulator lang=spice\n") else: + self.sf.write(".TRAN 5p {0}n \n".format(end_time)) self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl)) + if OPTS.spice_name == "hspice": # for cadence plots + self.sf.write(".OPTIONS PSF=1 \n") + self.sf.write(".OPTIONS HIER_DELIM=1 \n") # create plots for all signals self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n") @@ -314,6 +337,16 @@ class stimuli(): OPTS.openram_temp, OPTS.num_sim_threads) valid_retcode=0 + elif OPTS.spice_name == "spectre": + if OPTS.use_pex: + extra_options = " +dcopt +postlayout " + else: + extra_options = "" + cmd = ("{0} -64 {1} -format psfbin -raw {2} {3} -maxwarnstolog 1000 " + " +mt={4} -maxnotestolog 1000 " + .format(OPTS.spice_exe, temp_stim, OPTS.openram_temp, extra_options, + OPTS.num_sim_threads)) + valid_retcode = 0 elif OPTS.spice_name == "hspice": # TODO: Should make multithreading parameter a configuration option cmd = "{0} -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, From 9d025604ff718e932f64b6af79c14c11c681023a Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 19:29:18 -0500 Subject: [PATCH 24/78] Simulate calibre extracted netlists without requiring extra layout ports --- compiler/characterizer/delay.py | 67 +++++++++++++++++++++++++++- compiler/characterizer/simulation.py | 6 +-- compiler/characterizer/stimuli.py | 21 ++++----- compiler/example_configs/test_45.py | 28 ++++++++++++ compiler/sram/sram_base.py | 2 +- compiler/verify/__init__.py | 1 + compiler/verify/calibre.py | 12 +++++ 7 files changed, 122 insertions(+), 15 deletions(-) create mode 100644 compiler/example_configs/test_45.py diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 4c7f8f8f..081400a7 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -220,7 +220,7 @@ class delay(simulation): storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - if not OPTS.use_pex: + if not OPTS.use_pex or OPTS.calibre_pex: q_name = cell_name + '.' + str(storage_names[0]) qbar_name = cell_name + '.' + str(storage_names[1]) else: @@ -418,7 +418,9 @@ class delay(simulation): t_rise=self.slew, t_fall=self.slew) + self.load_all_measure_nets() self.write_delay_measures() + self.write_simulation_saves() # run until the end of the cycle time self.stim.write_control(self.cycle_times[-1] + self.period) @@ -596,6 +598,69 @@ class delay(simulation): self.sf.write("* Write ports {}\n".format(write_port)) self.write_delay_measures_write_port(write_port) + def load_pex_net(self, net: str): + from subprocess import check_output, CalledProcessError + prefix = (self.sram_instance_name + ".").lower() + if not net.lower().startswith(prefix) or not OPTS.use_pex or not OPTS.calibre_pex: + return net + original_net = net + net = net[len(prefix):] + net = net.replace(".", "_").replace("[", "\[").replace("]", "\]") + for pattern in ["\sN_{}_[MXmx]\S+_[gsd]".format(net), net]: + try: + match = check_output(["grep", "-m1", "-o", "-iE", pattern, self.sp_file]) + return prefix + match.decode().strip() + except CalledProcessError: + pass + return original_net + + def load_all_measure_nets(self): + measurement_nets = set() + for port, meas in zip(self.targ_read_ports*len(self.read_meas_lists) + + self.targ_write_ports * len(self.write_meas_lists), + self.read_meas_lists + self.write_meas_lists): + for measurement in meas: + visited = getattr(measurement, 'pex_visited', False) + for prop in ["trig_name_no_port", "targ_name_no_port"]: + if hasattr(measurement, prop): + net = getattr(measurement, prop).format(port) + if not visited: + net = self.load_pex_net(net) + setattr(measurement, prop, net) + measurement_nets.add(net) + measurement.pex_visited = True + self.measurement_nets = measurement_nets + return measurement_nets + + def write_simulation_saves(self): + for net in self.measurement_nets: + self.sf.write(".plot V({0}) \n".format(net)) + probe_nets = set() + sram_name = self.sram_instance_name + col = self.bitline_column + row = self.wordline_row + for port in set(self.targ_read_ports + self.targ_write_ports): + probe_nets.add("WEB{}".format(port)) + probe_nets.add("{}.w_en{}".format(self.sram_instance_name, port)) + probe_nets.add("{0}.Xbank0.Xport_data{1}.Xwrite_driver_array{1}.Xwrite_driver{2}.en_bar".format( + self.sram_instance_name, port, self.bitline_column)) + probe_nets.add("{}.Xbank0.br_{}_{}".format(self.sram_instance_name, port, + self.bitline_column)) + if not OPTS.use_pex: + continue + probe_nets.add( + "{0}.vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name, row, col - 1)) + probe_nets.add( + "{0}.p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name, port, col)) + probe_nets.add( + "{0}.vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name, port, col)) + probe_nets.add("{0}.vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name, + port, col)) + probe_nets.update(self.measurement_nets) + for net in probe_nets: + debug.info(2, "Probe: {}".format(net)) + self.sf.write(".plot V({}) \n".format(self.load_pex_net(net))) + def write_power_measures(self): """ Write the measure statements to quantify the leakage power only. diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 0617bfcd..6327348f 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -467,7 +467,7 @@ class simulation(): """ port = self.read_ports[0] - if not OPTS.use_pex: + if not OPTS.use_pex or OPTS.calibre_pex: # pex names handled post extraction self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -523,7 +523,7 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: sen_name = sen_name.split('.')[-1] return sen_name @@ -581,7 +581,7 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] return bl_names[0], bl_names[1] diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 5855f236..4ab1fe4f 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -52,7 +52,7 @@ class stimuli(): def inst_model(self, pins, model_name): """ Function to instantiate a generic model with a set of pins """ - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: self.inst_pex_model(pins, model_name) else: self.sf.write("X{0} ".format(model_name)) @@ -282,15 +282,16 @@ class stimuli(): self.sf.write(".OPTIONS HIER_DELIM=1 \n") # create plots for all signals - self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n") - if OPTS.verbose_level>0: - if OPTS.spice_name in ["hspice", "xa"]: - self.sf.write(".probe V(*)\n") + if not OPTS.use_pex: # Don't save all for extracted simulations + self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n") + if OPTS.verbose_level>0: + if OPTS.spice_name in ["hspice", "xa"]: + self.sf.write(".probe V(*)\n") + else: + self.sf.write(".plot V(*)\n") else: - self.sf.write(".plot V(*)\n") - else: - self.sf.write("*.probe V(*)\n") - self.sf.write("*.plot V(*)\n") + self.sf.write("*.probe V(*)\n") + self.sf.write("*.plot V(*)\n") # end the stimulus file self.sf.write(".end\n\n") @@ -349,7 +350,7 @@ class stimuli(): valid_retcode = 0 elif OPTS.spice_name == "hspice": # TODO: Should make multithreading parameter a configuration option - cmd = "{0} -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, + cmd = "{0} -d -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, OPTS.num_sim_threads, temp_stim, OPTS.openram_temp) diff --git a/compiler/example_configs/test_45.py b/compiler/example_configs/test_45.py new file mode 100644 index 00000000..732186d7 --- /dev/null +++ b/compiler/example_configs/test_45.py @@ -0,0 +1,28 @@ +word_size = 64 +num_words = 64 + +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 +num_banks = 1 +words_per_row = 1 +spice_name = "hspice" + + +tech_name = "freepdk45" +process_corners = ["TT"] +supply_voltages = [1.0] +temperatures = [25] + +route_supplies = True +perimeter_pins = False +check_lvsdrc = True +nominal_corner_only = True +load_scales = [0.5] +slew_scales = [0.5] +use_pex = False +analytical_delay = False + +output_name = "sram_w_{0}_{1}_{2}".format(word_size, num_words, tech_name) +output_path = "macro/{}".format(output_name) + diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 883b16dc..852eca46 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,7 +201,7 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), ur=vector(self.width, self.height)) diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 326771f8..b8e5175c 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -72,6 +72,7 @@ elif "magic"==OPTS.pex_exe[0]: else: debug.warning("Did not find a supported PEX tool." + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) +OPTS.calibre_pex = len(OPTS.pex_exe) > 0 and OPTS.pex_exe[0] == "calibre" # if OPTS.tech_name == "sky130": # if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]: diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 700815cd..053ee916 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -21,6 +21,7 @@ import os import shutil import re import debug +import utils from globals import OPTS from run_script import run_script @@ -166,6 +167,17 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu 'pexPexReportFile': cell_name + ".pex.report", 'pexMaskDBFile': cell_name + ".maskdb", 'cmnFDIDEFLayoutPath': cell_name + ".def", + 'cmnRunMT': "1", + 'cmnNumTurbo': "16", + 'pexPowerNames': "vdd", + 'pexGroundNames': "gnd", + 'pexPexGroundName': "1", + 'pexPexGroundNameValue': "gnd", + 'pexPexSeparator': "1", + 'pexPexSeparatorValue': "_", + 'pexPexNetlistNameSource': 'SOURCENAMES', + 'pexSVRFCmds': '{SOURCE CASE YES} {LAYOUT CASE YES}', + 'pexIncludeCmdsType': 'SVRF', } # write the runset file From f6afef8d4afd20b250312c15476076974ddd252b Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 19:30:37 -0500 Subject: [PATCH 25/78] rbl_bl_delay_bar to rbl_bl_delay for write enable --- compiler/modules/control_logic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 0c9d50bf..58f6e83f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -636,7 +636,7 @@ class control_logic(design.design): self.w_en_gate_inst = self.add_inst(name="w_en_and", mod=self.wen_and) # Only drive the writes in the second half of the clock cycle during a write operation. - self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"]) + self.connect_inst([input_name, "rbl_bl_delay", "gated_clk_bar", "w_en", "vdd", "gnd"]) def place_wen_row(self, row): x_offset = self.control_x_offset @@ -652,7 +652,7 @@ class control_logic(design.design): # No we for write-only reports, so use cs input_name = "cs" - wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"]) + wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay", "gated_clk_bar"]) self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus) self.connect_output(self.w_en_gate_inst, "Z", "w_en") From fde8794282729e0fe7de6844e47571baa13d6821 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Mon, 1 Mar 2021 09:56:25 +0100 Subject: [PATCH 26/78] calibre pex modifications to run hierarchical pex --- compiler/characterizer/delay.py | 16 +++-- compiler/characterizer/simulation.py | 9 ++- compiler/characterizer/stimuli.py | 2 +- compiler/sram/sram.py | 1 + compiler/sram/sram_base.py | 4 +- compiler/verify/calibre.py | 99 ++++++++++++++++++++++------ 6 files changed, 99 insertions(+), 32 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 5d2dd09a..a7114293 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -185,10 +185,10 @@ class delay(simulation): meas.targ_name_no_port)) self.dout_volt_meas[-1].meta_str = meas.meta_str - if not OPTS.use_pex: - self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name + "{}", "FALL", "RISE", measure_scale=1e9) - else: + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9) + else: + self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name + "{}", "FALL", "RISE", measure_scale=1e9) self.sen_meas.meta_str = sram_op.READ_ZERO self.sen_meas.meta_add_delay = True @@ -235,13 +235,15 @@ class delay(simulation): storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - if not OPTS.use_pex: - q_name = cell_name + '.' + str(storage_names[0]) - qbar_name = cell_name + '.' + str(storage_names[1]) - else: + + #todo: bob vanhoof's modification: hierarchical pex + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) + else: + q_name = cell_name + '.' + str(storage_names[0]) + qbar_name = cell_name + '.' + str(storage_names[1]) # Bit measures, measurements times to be defined later. The measurement names must be unique # but they is enforced externally. {} added to names to differentiate between ports allow the diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index f6ee260d..965dd087 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -426,7 +426,8 @@ class simulation(): """ port = self.read_ports[0] - if not OPTS.use_pex: + #todo: modified by bob vanhoof to take into account calibre pex + if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == 'calibre'): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -482,7 +483,8 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - if OPTS.use_pex: + # todo: modified by bob vanhoof + if OPTS.use_pex and (OPTS.pex_exe[0] != 'calibre'): sen_name = sen_name.split('.')[-1] return sen_name @@ -540,7 +542,8 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - if OPTS.use_pex: + #todo modified by bob vanhoof + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] return bl_names[0], bl_names[1] diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index b7a84cb6..046a3faf 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -52,7 +52,7 @@ class stimuli(): def inst_model(self, pins, model_name): """ Function to instantiate a generic model with a set of pins """ - if OPTS.use_pex: + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': self.inst_pex_model(pins, model_name) else: self.sf.write("X{0} ".format(model_name)) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index d5e223f8..d872e118 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -136,6 +136,7 @@ class sram(): if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested + #todo: bob vanhoof: re-generate the layout so that it now does include the pex labels pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index a3beacfa..3d91dbb1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,7 +201,9 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - if OPTS.use_pex: + #todo: bob vanhoof: this now does not automatically propagate the pex labels when the lvs tool is calibre + if OPTS.use_pex and not OPTS.lvs_exe[0] == "calibre": + debug.info(2,"adding global pex labels") self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), ur=vector(self.width, self.height)) diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 852451ce..71989911 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -125,6 +125,8 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out run_file = output_path + "run_lvs.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") + #PDK_DIR=os.environ.get("PDK_DIR") + #f.write("export PDK_DIR={}\n".format(PDK_DIR)) cmd = "{0} -gui -lvs lvs_runset -batch".format(OPTS.lvs_exe[1]) f.write(cmd) @@ -154,38 +156,80 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu from tech import drc pex_rules = drc["xrc_rules"] - pex_runset = { - 'pexRulesFile': pex_rules, - 'pexRunDir': output_path, - 'pexLayoutPaths': cell_name + ".gds", - 'pexLayoutPrimary': cell_name, - 'pexSourcePath': cell_name + ".sp", - 'pexSourcePrimary': cell_name, - 'pexReportFile': cell_name + ".pex.report", - 'pexPexNetlistFile': output, - 'pexPexReportFile': cell_name + ".pex.report", - 'pexMaskDBFile': cell_name + ".maskdb", - 'cmnFDIDEFLayoutPath': cell_name + ".def", - } - # write the runset file - f = open(output_path + "pex_runset", "w") - for k in sorted(iter(pex_runset.keys())): - f.write("*{0}: {1}\n".format(k, pex_runset[k])) + # write the rules file + f = open(OPTS.openram_temp + "pex_rules", "w") + f.write('// Rules file, created by OpenRAM, (c) Bob Vanhoof\n') + f.write('\n') + f.write('LAYOUT PATH "' + OPTS.openram_temp + cell_name + '.gds"\n') + f.write('LAYOUT PRIMARY ' + cell_name + '\n') + f.write('LAYOUT SYSTEM GDSII\n') + f.write('\n') + f.write('SOURCE PATH "' + OPTS.openram_temp + cell_name + '.sp"\n') + f.write('SOURCE PRIMARY ' + cell_name +'\n') + f.write('SOURCE SYSTEM SPICE\n') + f.write('SOURCE CASE YES\n') + f.write('\n') + f.write('MASK SVDB DIRECTORY "svdb" QUERY XRC\n') + f.write('\n') + f.write('LVS REPORT "' + OPTS.openram_temp + cell_name + '.pex.report"\n') + f.write('LVS REPORT OPTION NONE\n') + f.write('LVS FILTER UNUSED OPTION NONE SOURCE\n') + f.write('LVS FILTER UNUSED OPTION NONE LAYOUT\n') + f.write('LVS POWER NAME vdd\n') + f.write('LVS GROUND NAME gnd\n') + f.write('LVS RECOGNIZE GATES ALL\n') + f.write('LVS CELL SUPPLY YES\n') + f.write('LVS PUSH DEVICES SEPARATE PROPERTIES YES\n') + f.write('\n') + f.write('PEX NETLIST "' + output + '" HSPICE 1 SOURCENAMES GROUND gnd\n') + f.write('PEX REDUCE ANALOG NO\n') + f.write('PEX NETLIST UPPERCASE KEYWORDS NO\n') + f.write('PEX NETLIST VIRTUAL CONNECT YES\n') + f.write('PEX NETLIST NOXREF NET NAMES YES\n') + f.write('PEX NETLIST MUTUAL RESISTANCE YES\n') + f.write('PEX NETLIST EXPORT PORTS YES\n') + f.write('PEX PROBE FILE "probe_file"\n') + f.write('\n') + f.write('VIRTUAL CONNECT COLON NO\n') + f.write('VIRTUAL CONNECT REPORT NO\n') + f.write('VIRTUAL CONNECT NAME vdd gnd\n') + f.write('\n') + f.write('DRC ICSTATION YES\n') + f.write('\n') + f.write('INCLUDE "'+ pex_rules +'"\n') + f.close() + + # write probe file + #TODO: get from cell name + f = open(OPTS.openram_temp + "probe_file", "w") + f.write('CELL cell_1rw\n') + f.write(' Q 0.100 0.510 11\n') + f.write(' Q_bar 0.520 0.510 11\n') f.close() # Create an auxiliary script to run calibre with the runset run_file = output_path + "run_pex.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") - cmd = "{0} -gui -pex pex_runset -batch".format(OPTS.pex_exe[1]) - + cmd = "{0} -lvs -hier -genhcells -spice svdb/{1}.sp -turbo -hyper cmp {2}".format(OPTS.pex_exe[1], + cell_name, + 'pex_rules') + f.write(cmd) + f.write("\n") + cmd = "sed '/dummy/d' svdb/{0}.hcells | sed '/replica_column/d' | sed '/replica_cell/d' > hcell_file".format(cell_name) + f.write(cmd) + f.write("\n") + cmd = "{0} -xrc -pdb -turbo -xcell hcell_file -full -rc {1}".format(OPTS.pex_exe[1], 'pex_rules') + f.write(cmd) + f.write("\n") + cmd = "{0} -xrc -fmt -full {1}".format(OPTS.pex_exe[1],'pex_rules') f.write(cmd) f.write("\n") f.close() os.system("chmod u+x {}".format(run_file)) - return pex_runset + return None def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=False): @@ -194,6 +238,9 @@ def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=Fals global num_drc_runs num_drc_runs += 1 + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # hutil.copy(gds_name, OPTS.openram_temp) drc_runset = write_drc_script(cell_name, gds_name, extract, final_verification, OPTS.openram_temp) @@ -237,6 +284,12 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): lvs_runset = write_lvs_script(cell_name, gds_name, sp_name, final_verification, OPTS.openram_temp) + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # shutil.copy(gds_name, OPTS.openram_temp) + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): + # shutil.copy(sp_name, OPTS.openram_temp) + (outfile, errfile, resultsfile) = run_script(cell_name, "lvs") # check the result for these lines in the summary: @@ -318,6 +371,12 @@ def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False) write_pex_script(cell_name, True, output, final_verification, OPTS.openram_temp) + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # shutil.copy(gds_name, OPTS.openram_temp) + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): + # shutil.copy(sp_name, OPTS.openram_temp) + (outfile, errfile, resultsfile) = run_script(cell_name, "pex") From f5a9ab3b2ce4b7556c0928b665e70032a9a4cc83 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Mon, 1 Mar 2021 15:23:57 +0100 Subject: [PATCH 27/78] cleanup clutter --- compiler/characterizer/delay.py | 1 - compiler/characterizer/simulation.py | 3 --- compiler/sram/sram.py | 1 - compiler/sram/sram_base.py | 3 +-- compiler/verify/calibre.py | 17 ----------------- 5 files changed, 1 insertion(+), 24 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index a7114293..5858afb2 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -236,7 +236,6 @@ class delay(simulation): debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - #todo: bob vanhoof's modification: hierarchical pex if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 965dd087..3d62b28a 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -426,7 +426,6 @@ class simulation(): """ port = self.read_ports[0] - #todo: modified by bob vanhoof to take into account calibre pex if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == 'calibre'): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -483,7 +482,6 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - # todo: modified by bob vanhoof if OPTS.use_pex and (OPTS.pex_exe[0] != 'calibre'): sen_name = sen_name.split('.')[-1] return sen_name @@ -542,7 +540,6 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - #todo modified by bob vanhoof if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index d872e118..d5e223f8 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -136,7 +136,6 @@ class sram(): if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested - #todo: bob vanhoof: re-generate the layout so that it now does include the pex labels pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 3d91dbb1..e84abbf1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,8 +201,7 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - #todo: bob vanhoof: this now does not automatically propagate the pex labels when the lvs tool is calibre - if OPTS.use_pex and not OPTS.lvs_exe[0] == "calibre": + if OPTS.use_pex and OPTS.lvs_exe[0] != "calibre": debug.info(2,"adding global pex labels") self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 71989911..619cbdbf 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -125,8 +125,6 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out run_file = output_path + "run_lvs.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") - #PDK_DIR=os.environ.get("PDK_DIR") - #f.write("export PDK_DIR={}\n".format(PDK_DIR)) cmd = "{0} -gui -lvs lvs_runset -batch".format(OPTS.lvs_exe[1]) f.write(cmd) @@ -238,9 +236,6 @@ def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=Fals global num_drc_runs num_drc_runs += 1 - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # hutil.copy(gds_name, OPTS.openram_temp) drc_runset = write_drc_script(cell_name, gds_name, extract, final_verification, OPTS.openram_temp) @@ -284,12 +279,6 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): lvs_runset = write_lvs_script(cell_name, gds_name, sp_name, final_verification, OPTS.openram_temp) - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # shutil.copy(gds_name, OPTS.openram_temp) - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): - # shutil.copy(sp_name, OPTS.openram_temp) - (outfile, errfile, resultsfile) = run_script(cell_name, "lvs") # check the result for these lines in the summary: @@ -371,12 +360,6 @@ def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False) write_pex_script(cell_name, True, output, final_verification, OPTS.openram_temp) - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # shutil.copy(gds_name, OPTS.openram_temp) - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): - # shutil.copy(sp_name, OPTS.openram_temp) - (outfile, errfile, resultsfile) = run_script(cell_name, "pex") From ef78ad7249613b51612586d55a29740102272178 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:12:37 -0800 Subject: [PATCH 28/78] Upload workflow --- .github/workflows/ci.yml | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6d55448b..fb6d96e1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,7 +1,15 @@ name: ci on: [push] + coverage_cleanup: + if: ${{ always() }} + runs-on: self-hosted + steps: + - name: Coverage cleanup + run: | + python3-coverage erase jobs: scn4me_subm: + needs: [coverage_cleaup] runs-on: self-hosted steps: - name: Check out repository @@ -12,14 +20,16 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" + rm -rf $OPENRAM_TMP python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: ${{ github.workspace }}/scn4me_subm/ + path: ${{ github.workspace }}/scn4me_subm/*/ freepdk45: + needs: [coverage_cleaup] runs-on: self-hosted steps: - name: Check out repository @@ -30,14 +40,15 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45" + rm -rf $OPENRAM_TMP python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: ${{ github.workspace }}/freepdk45/ - coverage: + path: ${{ github.workspace }}/freepdk45/*/ + coverage_stats: if: ${{ always() }} needs: [scn4me_subm, freepdk45] runs-on: self-hosted @@ -52,4 +63,7 @@ jobs: with: name: code-coverage-report path: ${{ github.workspace }}/coverage_html/ + - name: Cleanup + run: | + python3-coverage erase From ab0b9ca37bae70d5c01f3a58f22d476f03074bd2 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:15:33 -0800 Subject: [PATCH 29/78] Fix syntax error in workflow --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index fb6d96e1..48778ce8 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,5 +1,6 @@ name: ci on: [push] +jobs: coverage_cleanup: if: ${{ always() }} runs-on: self-hosted @@ -7,7 +8,6 @@ on: [push] - name: Coverage cleanup run: | python3-coverage erase -jobs: scn4me_subm: needs: [coverage_cleaup] runs-on: self-hosted From 59915962a05f5b3ac6de080961eea671104e7d45 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:19:36 -0800 Subject: [PATCH 30/78] Update workflow syntax --- .github/workflows/ci.yml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 48778ce8..2cd6b6fe 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -2,11 +2,12 @@ name: ci on: [push] jobs: coverage_cleanup: - if: ${{ always() }} runs-on: self-hosted steps: - name: Coverage cleanup run: | + echo "Cleaning up previous run" + rm -rf "${{ github.workspace }}" python3-coverage erase scn4me_subm: needs: [coverage_cleaup] @@ -20,8 +21,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" - rm -rf $OPENRAM_TMP - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -40,8 +40,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45" - rm -rf $OPENRAM_TMP - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From 26eed77de0d86a017257426f651f65b6aebf8904 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:20:48 -0800 Subject: [PATCH 31/78] Update workflow syntax --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2cd6b6fe..b9447b17 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -29,7 +29,7 @@ jobs: name: scn4me_subm Archives path: ${{ github.workspace }}/scn4me_subm/*/ freepdk45: - needs: [coverage_cleaup] + needs: [coverage_cleanup] runs-on: self-hosted steps: - name: Check out repository From ec783f58b89d7001461fc6cee3315e8756dbe337 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:22:30 -0800 Subject: [PATCH 32/78] Update workflow syntax --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index b9447b17..87313c28 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,7 +10,7 @@ jobs: rm -rf "${{ github.workspace }}" python3-coverage erase scn4me_subm: - needs: [coverage_cleaup] + needs: [coverage_cleanup] runs-on: self-hosted steps: - name: Check out repository From 0556b931a9f30ed075c6a79cf1293d98a9f84702 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:27:56 -0800 Subject: [PATCH 33/78] Update workflow syntax --- .github/workflows/ci.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 87313c28..95a0abbb 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,8 +7,11 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" + echo ${{ github.workspace }} + ls ${{ github.workspace }} + echo ${{ github.home }} + ls ${{ github.home }} rm -rf "${{ github.workspace }}" - python3-coverage erase scn4me_subm: needs: [coverage_cleanup] runs-on: self-hosted From 7355fc91f82a4e95eb3ddd14e81d287ac478b4ae Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:28:47 -0800 Subject: [PATCH 34/78] Update workflow syntax --- .github/workflows/ci.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 95a0abbb..06c093ea 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,10 +7,10 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" - echo ${{ github.workspace }} - ls ${{ github.workspace }} - echo ${{ github.home }} - ls ${{ github.home }} + echo "${{ github.workspace }}" + ls "${{ github.workspace }}" + echo "${{ github.home }}" + ls "${{ github.home }}" rm -rf "${{ github.workspace }}" scn4me_subm: needs: [coverage_cleanup] From f7d66b7d2c68aabccf2c6fc786f3b602172ed1ac Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:31:32 -0800 Subject: [PATCH 35/78] Update workflow syntax --- .github/workflows/ci.yml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 06c093ea..3aab9322 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,10 +7,8 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" - echo "${{ github.workspace }}" - ls "${{ github.workspace }}" - echo "${{ github.home }}" - ls "${{ github.home }}" + echo "github.workspace = ${{ github.workspace }}" + echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" rm -rf "${{ github.workspace }}" scn4me_subm: needs: [coverage_cleanup] From 0ba1ceff6a93492820124681a6bafbc093546834 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:33:57 -0800 Subject: [PATCH 36/78] Separate checkout step --- .github/workflows/ci.yml | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 3aab9322..54a0215a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,12 +10,15 @@ jobs: echo "github.workspace = ${{ github.workspace }}" echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" rm -rf "${{ github.workspace }}" - scn4me_subm: + checkout_code: needs: [coverage_cleanup] + runs-on: self-hosted + - name: Checkout code + uses: actions/checkout@v1 + scn4me_subm: + needs: [checkout_code] runs-on: self-hosted steps: - - name: Check out repository - uses: actions/checkout@v1 - name: SCMOS test run: | . /home/github-runner/setup-paths.sh @@ -30,11 +33,9 @@ jobs: name: scn4me_subm Archives path: ${{ github.workspace }}/scn4me_subm/*/ freepdk45: - needs: [coverage_cleanup] + needs: [checkout_code] runs-on: self-hosted steps: - - name: Check out repository - uses: actions/checkout@v1 - name: FreePDK45 test run: | . /home/github-runner/setup-paths.sh @@ -63,7 +64,4 @@ jobs: with: name: code-coverage-report path: ${{ github.workspace }}/coverage_html/ - - name: Cleanup - run: | - python3-coverage erase From c6baef1c59b3ec73453b45e807deee156a411594 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:34:46 -0800 Subject: [PATCH 37/78] Remove tabs --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 54a0215a..879f3984 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,8 +7,8 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" - echo "github.workspace = ${{ github.workspace }}" - echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" + echo "github.workspace = ${{ github.workspace }}" + echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" rm -rf "${{ github.workspace }}" checkout_code: needs: [coverage_cleanup] From 5b6bfce7e068f8da163674236c3c97cf47981548 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:37:33 -0800 Subject: [PATCH 38/78] Add steps --- .github/workflows/ci.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 879f3984..8e5b38ca 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -13,7 +13,8 @@ jobs: checkout_code: needs: [coverage_cleanup] runs-on: self-hosted - - name: Checkout code + steps: + - name: Checkout code uses: actions/checkout@v1 scn4me_subm: needs: [checkout_code] From 27c197026ff67d00caca4f15d97b36b237872c67 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:50:37 -0800 Subject: [PATCH 39/78] Only remove temp dirs, erase coverage --- .github/workflows/ci.yml | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8e5b38ca..f213eafd 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -8,8 +8,9 @@ jobs: run: | echo "Cleaning up previous run" echo "github.workspace = ${{ github.workspace }}" - echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" - rm -rf "${{ github.workspace }}" + rm -rf "${{ github.workspace }}/scn4me_subm_temp" + rm -rf "${{ github.workspace }}/freepdk45_temp" + python3-coverage erase checkout_code: needs: [coverage_cleanup] runs-on: self-hosted @@ -25,14 +26,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" + export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: ${{ github.workspace }}/scn4me_subm/*/ + path: ${{ github.workspace }}/scn4me_subm_temp/*/ freepdk45: needs: [checkout_code] runs-on: self-hosted @@ -42,14 +43,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="${{ github.workspace }}/freepdk45" + export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: ${{ github.workspace }}/freepdk45/*/ + path: ${{ github.workspace }}/freepdk45_temp/*/ coverage_stats: if: ${{ always() }} needs: [scn4me_subm, freepdk45] From 7c15773e173c5c6fc6ff7d87fcc040eca2eff409 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:51:09 -0800 Subject: [PATCH 40/78] Only remove temp dirs, erase coverage --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index f213eafd..8e719306 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,7 +10,7 @@ jobs: echo "github.workspace = ${{ github.workspace }}" rm -rf "${{ github.workspace }}/scn4me_subm_temp" rm -rf "${{ github.workspace }}/freepdk45_temp" - python3-coverage erase + python3-coverage erase checkout_code: needs: [coverage_cleanup] runs-on: self-hosted From 5ab67214e5fd039169dfce1772b8b765c007bf0e Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 11:37:42 -0800 Subject: [PATCH 41/78] Make sure to add path when source and target --- compiler/router/router.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/router/router.py b/compiler/router/router.py index 8da1d265..dc0c8e8d 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -1055,6 +1055,7 @@ class router(router_tech): # Double check source and taget are not same node, if so, we are done! for k, v in self.rg.map.items(): if v.source and v.target: + self.paths.append([k]) return True # returns the path in tracks From bedd1b3d154ee7679fd530a2ed22b568e4bbb1d4 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 11:40:58 -0800 Subject: [PATCH 42/78] Don't need to cleanup as checkout does it. --- .github/workflows/ci.yml | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8e719306..6d3b4a2a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,18 +1,7 @@ name: ci on: [push] jobs: - coverage_cleanup: - runs-on: self-hosted - steps: - - name: Coverage cleanup - run: | - echo "Cleaning up previous run" - echo "github.workspace = ${{ github.workspace }}" - rm -rf "${{ github.workspace }}/scn4me_subm_temp" - rm -rf "${{ github.workspace }}/freepdk45_temp" - python3-coverage erase checkout_code: - needs: [coverage_cleanup] runs-on: self-hosted steps: - name: Checkout code From 01094ae4f0744dbe7add97d5f47bdbe3c3795dd3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 14:56:56 -0800 Subject: [PATCH 43/78] Don't upload coverage artifacts --- .github/workflows/ci.yml | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6d3b4a2a..17901f2d 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -16,7 +16,8 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm + #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm + $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -33,26 +34,27 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 + #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 + $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives path: ${{ github.workspace }}/freepdk45_temp/*/ - coverage_stats: - if: ${{ always() }} - needs: [scn4me_subm, freepdk45] - runs-on: self-hosted - steps: - - name: Coverage stats - run: | - python3-coverage combine - python3-coverage report - python3-coverage html -d ${{ github.workspace }}/coverage_html - - name: Archive coverage - uses: actions/upload-artifact@v2 - with: - name: code-coverage-report - path: ${{ github.workspace }}/coverage_html/ + # coverage_stats: + # if: ${{ always() }} + # needs: [scn4me_subm, freepdk45] + # runs-on: self-hosted + # steps: + # - name: Coverage stats + # run: | + # python3-coverage combine + # python3-coverage report + # python3-coverage html -d ${{ github.workspace }}/coverage_html + # - name: Archive coverage + # uses: actions/upload-artifact@v2 + # with: + # name: code-coverage-report + # path: ${{ github.workspace }}/coverage_html/ From 96faf06b7cc7f66be9a337efb73817a187fe94c3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 14:58:55 -0800 Subject: [PATCH 44/78] Each job must checkout with multiple runners --- .github/workflows/ci.yml | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 17901f2d..ab4a7527 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,15 +1,11 @@ name: ci on: [push] jobs: - checkout_code: - runs-on: self-hosted + scn4me_subm: + runs-on: self-hosted steps: - name: Checkout code uses: actions/checkout@v1 - scn4me_subm: - needs: [checkout_code] - runs-on: self-hosted - steps: - name: SCMOS test run: | . /home/github-runner/setup-paths.sh @@ -25,9 +21,10 @@ jobs: name: scn4me_subm Archives path: ${{ github.workspace }}/scn4me_subm_temp/*/ freepdk45: - needs: [checkout_code] runs-on: self-hosted steps: + - name: Checkout code + uses: actions/checkout@v1 - name: FreePDK45 test run: | . /home/github-runner/setup-paths.sh From 1614dc140d00bfd32e338c666e1fb018244a4894 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 14:59:49 -0800 Subject: [PATCH 45/78] Remove tab --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index ab4a7527..8103d1eb 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -32,7 +32,7 @@ jobs: export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 + $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From 049d3ffcaf0b2131427b9fadf3ae8f0bea03ffba Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 15:25:39 -0800 Subject: [PATCH 46/78] Remove extra test file --- compiler/example_configs/test_45.py | 28 ---------------------------- 1 file changed, 28 deletions(-) delete mode 100644 compiler/example_configs/test_45.py diff --git a/compiler/example_configs/test_45.py b/compiler/example_configs/test_45.py deleted file mode 100644 index 732186d7..00000000 --- a/compiler/example_configs/test_45.py +++ /dev/null @@ -1,28 +0,0 @@ -word_size = 64 -num_words = 64 - -num_rw_ports = 1 -num_r_ports = 0 -num_w_ports = 0 -num_banks = 1 -words_per_row = 1 -spice_name = "hspice" - - -tech_name = "freepdk45" -process_corners = ["TT"] -supply_voltages = [1.0] -temperatures = [25] - -route_supplies = True -perimeter_pins = False -check_lvsdrc = True -nominal_corner_only = True -load_scales = [0.5] -slew_scales = [0.5] -use_pex = False -analytical_delay = False - -output_name = "sram_w_{0}_{1}_{2}".format(word_size, num_words, tech_name) -output_path = "macro/{}".format(output_name) - From fb953c19e8d9586ccc0466ec9df9958ed46b62c0 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 16:36:27 -0800 Subject: [PATCH 47/78] Remove option that causes errors and is unused. --- compiler/verify/__init__.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index b8e5175c..326771f8 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -72,7 +72,6 @@ elif "magic"==OPTS.pex_exe[0]: else: debug.warning("Did not find a supported PEX tool." + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) -OPTS.calibre_pex = len(OPTS.pex_exe) > 0 and OPTS.pex_exe[0] == "calibre" # if OPTS.tech_name == "sky130": # if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]: From 90cb9f581f0f7d85f8aa4943dcbae239e8c0cc0e Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Mar 2021 09:28:41 -0800 Subject: [PATCH 48/78] Fixes to get hspice delay test to pass. --- compiler/characterizer/delay.py | 6 +++--- compiler/characterizer/stimuli.py | 9 ++++----- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 296027c2..f491d8b0 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -418,9 +418,9 @@ class delay(simulation): t_rise=self.slew, t_fall=self.slew) - self.load_all_measure_nets() + # self.load_all_measure_nets() self.write_delay_measures() - self.write_simulation_saves() + # self.write_simulation_saves() # run until the end of the cycle time self.stim.write_control(self.cycle_times[-1] + self.period) @@ -616,7 +616,7 @@ class delay(simulation): def load_all_measure_nets(self): measurement_nets = set() - for port, meas in zip(self.targ_read_ports*len(self.read_meas_lists) + + for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists) + self.targ_write_ports * len(self.write_meas_lists), self.read_meas_lists + self.write_meas_lists): for measurement in meas: diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index c6ef0fa5..4eee9e5c 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -246,15 +246,14 @@ class stimuli(): reltol = 0.001 # 0.1% timestep = 10 # ps, was 5ps but ngspice was complaining the timestep was too small in certain tests. - # UIC is needed for ngspice to converge - self.sf.write(".TEMP {}\n".format(self.temperature)) if OPTS.spice_name == "ngspice": + # UIC is needed for ngspice to converge + self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) # ngspice sometimes has convergence problems if not using gear method # which is more accurate, but slower than the default trapezoid method # Do not remove this or it may not converge due to some "pa_00" nodes # unless you figure out what these are. - self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear\n".format(reltol)) elif OPTS.spice_name == "spectre": self.sf.write("simulator lang=spectre\n") @@ -275,7 +274,7 @@ class stimuli(): ' annotate=status maxiters=5 \n'.format("5p", end_time)) self.sf.write("simulator lang=spice\n") else: - self.sf.write(".TRAN 5p {0}n \n".format(end_time)) + self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl)) if OPTS.spice_name == "hspice": # for cadence plots self.sf.write(".OPTIONS PSF=1 \n") @@ -350,7 +349,7 @@ class stimuli(): valid_retcode = 0 elif OPTS.spice_name == "hspice": # TODO: Should make multithreading parameter a configuration option - cmd = "{0} -d -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, + cmd = "{0} -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, OPTS.num_sim_threads, temp_stim, OPTS.openram_temp) From da3a1003019e31fb8cf8089bb568b093486a23c2 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Mar 2021 09:28:59 -0800 Subject: [PATCH 49/78] Try new wildcard for archive path. --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8103d1eb..262e65ca 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -19,7 +19,7 @@ jobs: uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: ${{ github.workspace }}/scn4me_subm_temp/*/ + path: ${{ github.workspace }}/scn4me_subm_temp/*/* freepdk45: runs-on: self-hosted steps: @@ -38,7 +38,7 @@ jobs: uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: ${{ github.workspace }}/freepdk45_temp/*/ + path: ${{ github.workspace }}/freepdk45_temp/*/* # coverage_stats: # if: ${{ always() }} # needs: [scn4me_subm, freepdk45] From db118beeba1ba8d50e0d8e54eaecd7f19e8e8848 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Mar 2021 13:38:09 -0800 Subject: [PATCH 50/78] Zoom parameter should be optional in tech files. --- compiler/base/pin_layout.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index a86aa07b..eb4cb2ad 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -396,10 +396,14 @@ class pin_layout: # Add the text in the middle of the pin. # This fixes some pin label offsetting when GDS gets # imported into Magic. + try: + zoom = GDS["zoom"] + except KeyError: + zoom = None newLayout.addText(text=self.name, layerNumber=layer_num, purposeNumber=label_purpose, - magnification=GDS["zoom"], + magnification=zoom, offsetInMicrons=self.center()) def compute_overlap(self, other): From b6f3fbdd1f5d8e79d705f2dfca4908c74d4c005b Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Mar 2021 09:44:14 -0700 Subject: [PATCH 51/78] Use OPTS.precharge instead of hard coded precharge. --- compiler/modules/port_data.py | 2 +- compiler/modules/precharge_array.py | 2 +- compiler/options.py | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 8afa8d06..71c8449a 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -275,7 +275,7 @@ class port_data(design.design): self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() # used for bl/br names - self.precharge = factory.create(module_type="precharge", + self.precharge = factory.create(module_type=OPTS.precharge, bitcell_bl=self.bl_names[0], bitcell_br=self.br_names[0]) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 498ba815..8718dfd0 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -72,7 +72,7 @@ class precharge_array(design.design): self.DRC_LVS() def add_modules(self): - self.pc_cell = factory.create(module_type="precharge", + self.pc_cell = factory.create(module_type=OPTS.precharge, size=self.size, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) diff --git a/compiler/options.py b/compiler/options.py index 4c04cdb0..e3a9a76e 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -171,6 +171,7 @@ class options(optparse.Values): nand2_dec = "pnand2" nand3_dec = "pnand3" nand4_dec = "pnand4" # Not available right now + precharge = "precharge" precharge_array = "precharge_array" ptx = "ptx" replica_bitline = "replica_bitline" From 671470f5f2d249547f4ce80c54b93dc8ed6104ca Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 8 Mar 2021 14:40:36 -0800 Subject: [PATCH 52/78] Skywater changes. Default 1 thread and no temp subdirectory. Add skywater setup/hold golden data Add CLI option for simulation threads (-m) Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading. Make subdir when using default /tmp dir. Pass num_threads so temp subdirs are created. --- .github/workflows/ci.yml | 4 +-- compiler/characterizer/charutils.py | 2 ++ compiler/characterizer/stimuli.py | 2 ++ compiler/debug.py | 15 +++++++++- ...1r.py => riscv_scn4m_subm_2kbyte_1rw1r.py} | 0 compiler/globals.py | 29 ++++++++++++++++--- compiler/modules/bank.py | 3 ++ compiler/modules/hierarchical_predecode.py | 19 +++++++----- compiler/modules/hierarchical_predecode2x4.py | 4 +-- compiler/modules/hierarchical_predecode3x8.py | 4 +-- .../modules/hierarchical_predecode4x16.py | 4 +-- compiler/options.py | 2 +- compiler/tests/21_hspice_setuphold_test.py | 10 ++++--- compiler/tests/21_ngspice_setuphold_test.py | 10 ++++--- compiler/tests/30_openram_back_end_test.py | 3 ++ compiler/tests/30_openram_front_end_test.py | 3 ++ compiler/tests/regress.py | 3 +- compiler/tests/testutils.py | 10 +++---- 18 files changed, 91 insertions(+), 36 deletions(-) rename compiler/example_configs/{riscv_scn4m_subm_2skbyte_1rw1r.py => riscv_scn4m_subm_2kbyte_1rw1r.py} (100%) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 262e65ca..d50b93d2 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -19,7 +19,7 @@ jobs: uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: ${{ github.workspace }}/scn4me_subm_temp/*/* + path: $OPENRAM_HOME/*.zip freepdk45: runs-on: self-hosted steps: @@ -38,7 +38,7 @@ jobs: uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: ${{ github.workspace }}/freepdk45_temp/*/* + path: $OPENRAM_HOME/*.zip # coverage_stats: # if: ${{ always() }} # needs: [scn4me_subm, freepdk45] diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py index b618f0db..8f33c279 100644 --- a/compiler/characterizer/charutils.py +++ b/compiler/characterizer/charutils.py @@ -31,6 +31,8 @@ def parse_spice_list(filename, key): f = open(full_filename, "r") except IOError: debug.error("Unable to open spice output file: {0}".format(full_filename),1) + debug.archive() + contents = f.read() f.close() # val = re.search(r"{0}\s*=\s*(-?\d+.?\d*\S*)\s+.*".format(key), contents) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 4eee9e5c..06b6058d 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -360,6 +360,8 @@ class stimuli(): # -r {2}timing.raw ng_cfg = open("{}.spiceinit".format(OPTS.openram_temp), "w") ng_cfg.write("set num_threads={}\n".format(OPTS.num_sim_threads)) + ng_cfg.write("set ngbehavior=hsa\n") + ng_cfg.write("set ng_nomodcheck\n") ng_cfg.close() cmd = "{0} -b -o {2}timing.lis {1}".format(OPTS.spice_exe, diff --git a/compiler/debug.py b/compiler/debug.py index f14b1224..f8a4807d 100644 --- a/compiler/debug.py +++ b/compiler/debug.py @@ -43,7 +43,7 @@ def error(str, return_value=0): if globals.OPTS.debug: pdb.set_trace() - + assert return_value == 0 @@ -108,7 +108,20 @@ def info(lev, str): print_raw("[{0}/{1}]: {2}".format(class_name, frm[0].f_code.co_name, str)) + +def archive(): + from globals import OPTS + try: + OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) + except: + error("$OPENRAM_HOME is not properly defined.", 1) + import shutil + zip_file = "{0}/{1}_{2}".format(OPENRAM_HOME, "fail_", os.getpid()) + info(0, "Archiving failed files to {}.zip".format(zip_file)) + shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + + def bp(): """ An empty function so you can set soft breakpoints in pdb. diff --git a/compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_2kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_2kbyte_1rw1r.py diff --git a/compiler/globals.py b/compiler/globals.py index b977e8e3..1a4bd5c5 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -61,8 +61,13 @@ def parse_args(): optparse.make_option("-j", "--threads", action="store", type="int", - help="Specify the number of threads (default: 2)", + help="Specify the number of threads (default: 1)", dest="num_threads"), + optparse.make_option("-m", "--sim_threads", + action="store", + type="int", + help="Specify the number of spice simulation threads (default: 2)", + dest="num_sim_threads"), optparse.make_option("-v", "--verbose", action="count", @@ -381,6 +386,10 @@ def purge_temp(): """ Remove the temp directory. """ debug.info(1, "Purging temp directory: {}".format(OPTS.openram_temp)) + #import inspect + #s = inspect.stack() + #print("Purge {0} in dir {1}".format(s[3].filename, OPTS.openram_temp)) + # This annoyingly means you have to re-cd into # the directory each debug iteration # shutil.rmtree(OPTS.openram_temp, ignore_errors=True) @@ -429,9 +438,15 @@ def setup_paths(): if "__pycache__" not in full_path: sys.path.append("{0}".format(full_path)) - # Use a unique temp subdirectory - OPTS.openram_temp += "/openram_{0}_{1}_temp/".format(getpass.getuser(), - os.getpid()) + # Use a unique temp subdirectory if multithreaded + if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp": + + # Make a unique subdir + tempdir = "/openram_{0}_{1}_temp".format(getpass.getuser(), + os.getpid()) + # Only add the unique subdir one time + if tempdir not in OPTS.openram_temp: + OPTS.openram_temp += tempdir if not OPTS.openram_temp.endswith('/'): OPTS.openram_temp += "/" @@ -470,6 +485,12 @@ def init_paths(): except OSError as e: if e.errno == 17: # errno.EEXIST os.chmod(OPTS.openram_temp, 0o750) + #import inspect + #s = inspect.stack() + #from pprint import pprint + #pprint(s) + #print("Test {0} in dir {1}".format(s[2].filename, OPTS.openram_temp)) + # Don't delete the output dir, it may have other files! # make the directory if it doesn't exist diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 7f7fb0d4..488439fd 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -526,13 +526,16 @@ class bank(design.design): height=self.dff.height) elif self.col_addr_size == 2: self.column_decoder = factory.create(module_type="hierarchical_predecode2x4", + column_decoder=True, height=self.dff.height) elif self.col_addr_size == 3: self.column_decoder = factory.create(module_type="hierarchical_predecode3x8", + column_decoder=True, height=self.dff.height) elif self.col_addr_size == 4: self.column_decoder = factory.create(module_type="hierarchical_predecode4x16", + column_decoder=True, height=self.dff.height) else: # No error checking before? diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index bd192694..c2ed5949 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -18,19 +18,17 @@ class hierarchical_predecode(design.design): """ Pre 2x4 and 3x8 and TBD 4x16 decoder shared code. """ - def __init__(self, name, input_number, height=None): + def __init__(self, name, input_number, column_decoder=False, height=None): self.number_of_inputs = input_number b = factory.create(module_type=OPTS.bitcell) if not height: self.cell_height = b.height - self.column_decoder = False else: self.cell_height = height - # If we are pitch matched to the bitcell, it's a predecoder - # otherwise it's a column decoder (out of pgates) - self.column_decoder = (height != b.height) + + self.column_decoder = column_decoder self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) super().__init__(name) @@ -87,8 +85,15 @@ class hierarchical_predecode(design.design): self.bus_layer = layer_props.hierarchical_predecode.bus_layer self.bus_directions = layer_props.hierarchical_predecode.bus_directions - self.bus_pitch = getattr(self, self.bus_layer + "_pitch") - self.bus_space = layer_props.hierarchical_predecode.bus_space_factor * getattr(self, self.bus_layer + "_space") + + if self.column_decoder: + # Column decoders may be routed on M2/M3 if there's a write mask + self.bus_pitch = self.m3_pitch + self.bus_space = self.m3_space + else: + self.bus_pitch = getattr(self, self.bus_layer + "_pitch") + self.bus_space = getattr(self, self.bus_layer + "_space") + self.bus_space = layer_props.hierarchical_predecode.bus_space_factor * self.bus_space self.input_layer = layer_props.hierarchical_predecode.input_layer self.output_layer = layer_props.hierarchical_predecode.output_layer self.output_layer_pitch = getattr(self, self.output_layer + "_pitch") diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index c212a3c6..941a0756 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -13,8 +13,8 @@ class hierarchical_predecode2x4(hierarchical_predecode): """ Pre 2x4 decoder used in hierarchical_decoder. """ - def __init__(self, name, height=None): - super().__init__( name, 2, height) + def __init__(self, name, column_decoder=False, height=None): + super().__init__(name, 2, column_decoder, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index 61c25094..ef70a282 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -13,8 +13,8 @@ class hierarchical_predecode3x8(hierarchical_predecode): """ Pre 3x8 decoder used in hierarchical_decoder. """ - def __init__(self, name, height=None): - super().__init__(name, 3, height) + def __init__(self, name, column_decoder=False, height=None): + super().__init__(name, 3, column_decoder, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/hierarchical_predecode4x16.py b/compiler/modules/hierarchical_predecode4x16.py index fe1426d8..64eef96d 100644 --- a/compiler/modules/hierarchical_predecode4x16.py +++ b/compiler/modules/hierarchical_predecode4x16.py @@ -13,8 +13,8 @@ class hierarchical_predecode4x16(hierarchical_predecode): """ Pre 4x16 decoder used in hierarchical_decoder. """ - def __init__(self, name, height=None): - super().__init__(name, 4, height) + def __init__(self, name, column_decoder=False, height=None): + super().__init__(name, 4, column_decoder, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/options.py b/compiler/options.py index e3a9a76e..551c3950 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -133,7 +133,7 @@ class options(optparse.Values): magic_exe = None # Number of threads to use - num_threads = 2 + num_threads = 1 # Number of threads to use in ngspice/hspice num_sim_threads = 2 diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index e97a8aca..634b2982 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -12,8 +12,7 @@ import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS -from sram_factory import factory -import debug + class timing_setup_test(openram_test): @@ -29,14 +28,12 @@ class timing_setup_test(openram_test): import characterizer reload(characterizer) from characterizer import setup_hold - import sram import tech slews = [tech.spice["rise_time"]*2] corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) sh = setup_hold(corner) data = sh.analyze(slews,slews) - #print data if OPTS.tech_name == "freepdk45": golden_data = {'hold_times_HL': [-0.0158691], 'hold_times_LH': [-0.0158691], @@ -47,6 +44,11 @@ class timing_setup_test(openram_test): 'hold_times_LH': [-0.11718749999999999], 'setup_times_HL': [0.16357419999999998], 'setup_times_LH': [0.1757812]} + elif OPTS.tech_name == "sky130": + golden_data = {'hold_times_HL': [-0.05615234], + 'hold_times_LH': [-0.03173828], + 'setup_times_HL': [0.078125], + 'setup_times_LH': [0.1025391]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index da6d07ff..dab02e7d 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -12,8 +12,7 @@ import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS -from sram_factory import factory -import debug + class timing_setup_test(openram_test): @@ -29,14 +28,12 @@ class timing_setup_test(openram_test): import characterizer reload(characterizer) from characterizer import setup_hold - import sram import tech slews = [tech.spice["rise_time"]*2] corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) sh = setup_hold(corner) data = sh.analyze(slews,slews) - #print data if OPTS.tech_name == "freepdk45": golden_data = {'hold_times_HL': [-0.01586914], 'hold_times_LH': [-0.01586914], @@ -47,6 +44,11 @@ class timing_setup_test(openram_test): 'hold_times_LH': [-0.1293945], 'setup_times_HL': [0.1757812], 'setup_times_LH': [0.1879883]} + elif OPTS.tech_name == "sky130": + golden_data = {'hold_times_HL': [-0.05615234], + 'hold_times_LH': [-0.03173828], + 'setup_times_HL': [0.078125], + 'setup_times_LH': [0.1025391]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index c2060656..74232db0 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -49,6 +49,9 @@ class openram_back_end_test(openram_test): if OPTS.tech_name: options += " -t {}".format(OPTS.tech_name) + if OPTS.num_threads: + options += " -j {}".format(OPTS.num_threads) + # Always perform code coverage if OPTS.coverage == 0: debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 1c190840..9c134152 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -49,6 +49,9 @@ class openram_front_end_test(openram_test): if OPTS.tech_name: options += " -t {}".format(OPTS.tech_name) + if OPTS.num_threads: + options += " -j {}".format(OPTS.num_threads) + # Always perform code coverage if OPTS.coverage == 0: debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") diff --git a/compiler/tests/regress.py b/compiler/tests/regress.py index 878182a5..ea7e1991 100755 --- a/compiler/tests/regress.py +++ b/compiler/tests/regress.py @@ -13,7 +13,6 @@ import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from subunit import ProtocolTestCase, TestProtocolClient -from subunit.test_results import AutoTimingTestResultDecorator from testtools import ConcurrentTestSuite (OPTS, args) = globals.parse_args() @@ -71,7 +70,7 @@ def fork_tests(num_threads): stream = os.fdopen(c2pwrite, 'wb', 0) os.close(c2pread) sys.stdin.close() - test_suite_result = AutoTimingTestResultDecorator(TestProtocolClient(stream)) + test_suite_result = TestProtocolClient(stream) test_suite.run(test_suite_result) except EBADF: try: diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index b6468749..4d8bf573 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -28,10 +28,9 @@ class openram_test(unittest.TestCase): result=verify.run_drc(w.name, tempgds, None) if result != 0: self.fail("DRC failed: {}".format(w.name)) - - if not OPTS.keep_temp: + elif not OPTS.keep_temp: self.cleanup() - + def local_check(self, a, final_verification=False): self.reset() @@ -74,10 +73,10 @@ class openram_test(unittest.TestCase): # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) self.fail("LVS mismatch: {}".format(a.name)) + if lvs_result == 0 and drc_result == 0 and not OPTS.keep_temp: + self.cleanup() # For debug... # import pdb; pdb.set_trace() - if not OPTS.keep_temp: - self.cleanup() def run_pex(self, a, output=None): tempspice = "{}.sp".format(a.name) @@ -104,6 +103,7 @@ class openram_test(unittest.TestCase): def cleanup(self): """ Reset the duplicate checker and cleanup files. """ + files = glob.glob(OPTS.openram_temp + '*') for f in files: # Only remove the files From 7b270514e1b528a76bdcf1729383f88e79665b2f Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 22 Mar 2021 15:51:07 -0700 Subject: [PATCH 53/78] Update multithreaded regression. Only do 2 threads for 30 tests. Don't archive results since they are purged anyways. 16 threads for regression. Purge temp during regression. --- .github/workflows/ci.yml | 28 ++++++++++----------- compiler/tests/30_openram_back_end_test.py | 3 +-- compiler/tests/30_openram_front_end_test.py | 3 +-- 3 files changed, 16 insertions(+), 18 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index d50b93d2..a95db618 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -13,13 +13,13 @@ jobs: export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm - $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm - - name: Archive - if: ${{ failure() }} - uses: actions/upload-artifact@v2 - with: - name: scn4me_subm Archives - path: $OPENRAM_HOME/*.zip + $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm + # - name: Archive + # if: ${{ failure() }} + # uses: actions/upload-artifact@v2 + # with: + # name: scn4me_subm Archives + # path: ${{ github.workspace }}/scn4me_subm_temp/ freepdk45: runs-on: self-hosted steps: @@ -32,13 +32,13 @@ jobs: export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - - name: Archive - if: ${{ failure() }} - uses: actions/upload-artifact@v2 - with: - name: FreePDK45 Archives - path: $OPENRAM_HOME/*.zip + $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 + # - name: Archive + # if: ${{ failure() }} + # uses: actions/upload-artifact@v2 + # with: + # name: FreePDK45 Archives + # path: ${{ github.workspace }}/freepdk45_temp/ # coverage_stats: # if: ${{ always() }} # needs: [scn4me_subm, freepdk45] diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 74232db0..c67b8249 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -49,8 +49,7 @@ class openram_back_end_test(openram_test): if OPTS.tech_name: options += " -t {}".format(OPTS.tech_name) - if OPTS.num_threads: - options += " -j {}".format(OPTS.num_threads) + options += " -j 2" # Always perform code coverage if OPTS.coverage == 0: diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 9c134152..87b280dc 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -49,8 +49,7 @@ class openram_front_end_test(openram_test): if OPTS.tech_name: options += " -t {}".format(OPTS.tech_name) - if OPTS.num_threads: - options += " -j {}".format(OPTS.num_threads) + options += " -j 2" # Always perform code coverage if OPTS.coverage == 0: From fae72ca993ca55fe1198f3cceab6bea8684cc7d7 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Mar 2021 13:06:36 -0700 Subject: [PATCH 54/78] Test new archive options for github actions. --- .github/workflows/ci.yml | 32 ++++++++++++++++---------------- compiler/tests/testutils.py | 17 +++++++++++++++++ 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index a95db618..894cbd55 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -9,17 +9,17 @@ jobs: - name: SCMOS test run: | . /home/github-runner/setup-paths.sh - export OPENRAM_HOME="`pwd`/compiler" - export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" + export OPENRAM_HOME="${{ github.workspace }}/compiler" + export OPENRAM_TECH="${{ github.workspace }}/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm - # - name: Archive - # if: ${{ failure() }} - # uses: actions/upload-artifact@v2 - # with: - # name: scn4me_subm Archives - # path: ${{ github.workspace }}/scn4me_subm_temp/ + - name: Archive + if: ${{ failure() }} + uses: actions/upload-artifact@v2 + with: + name: scn4me_subm Archives + path: ${{ github.workspace }}/*.zip freepdk45: runs-on: self-hosted steps: @@ -28,17 +28,17 @@ jobs: - name: FreePDK45 test run: | . /home/github-runner/setup-paths.sh - export OPENRAM_HOME="`pwd`/compiler" - export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" + export OPENRAM_HOME="${{ github.workspace }}/compiler" + export OPENRAM_TECH="${{ github.workspace }}/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 - # - name: Archive - # if: ${{ failure() }} - # uses: actions/upload-artifact@v2 - # with: - # name: FreePDK45 Archives - # path: ${{ github.workspace }}/freepdk45_temp/ + - name: Archive + if: ${{ failure() }} + uses: actions/upload-artifact@v2 + with: + name: FreePDK45 Archives + path: ${{ github.workspace }}/*.zip # coverage_stats: # if: ${{ always() }} # needs: [scn4me_subm, freepdk45] diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 4d8bf573..ed24f8cf 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -17,6 +17,23 @@ import traceback class openram_test(unittest.TestCase): """ Base unit test that we have some shared classes in. """ + def fail(self, msg): + import inspect + s = inspect.stack() + base_filename = os.path.splitext(os.path.basename(s[2].filename))[0] + + try: + OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) + except: + debug.error("$OPENRAM_HOME is not properly defined.", 1) + + import shutil + zip_file = "{0}/../{1}_{2}".format(OPENRAM_HOME, base_filename, os.getpid()) + debug.info(0, "Archiving failed temp files {0} to {1}".format(OPTS.openram_temp, zip_file)) + shutil.make_archive(zip_file, 'zip', OPTS.openram_temp) + + super().fail(msg) + def local_drc_check(self, w): self.reset() From e144f03b23c9a821cf5a0c67dc09bb5f8c55e9df Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Mar 2021 11:15:59 -0700 Subject: [PATCH 55/78] Add status for supply routing. --- compiler/router/supply_tree_router.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index 0b29119d..e0455602 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -79,8 +79,8 @@ class supply_tree_router(router): """ remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name]) - debug.info(1, "Routing {0} with {1} pin components to connect.".format(pin_name, - remaining_components)) + debug.info(1, "Routing {0} with {1} pins.".format(pin_name, + remaining_components)) # Create full graph debug.info(2, "Creating adjacency matrix") @@ -108,7 +108,9 @@ class supply_tree_router(router): connections.append((x, y)) # Route MST components - for (src, dest) in connections: + for index, (src, dest) in enumerate(connections): + if not (index % 100): + debug.info(0, "{0} supply segments routed, {1} remaining.".format(index, len(connections) - index)) self.route_signal(pin_name, src, dest) # if pin_name == "gnd": # print("\nSRC {}: ".format(src) + str(self.pin_groups[pin_name][src].grids) + str(self.pin_groups[pin_name][src].blockages)) From 4a40e96f6d3522335f3ad7ed5a7cdc5c5d5f2ec9 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 24 Mar 2021 14:32:10 -0700 Subject: [PATCH 56/78] Control logic route changes. Move wl_en to top control signal. Route wl_en directly to port_address. Reorder input bus to bank. --- compiler/modules/bank.py | 25 +++------ compiler/modules/control_logic.py | 10 ++-- compiler/sram/sram_1bank.py | 42 ++++++++++++++ .../tests/20_sram_1bank_4mux_1rw_1r_test.py | 56 +++++++++++++++++++ 4 files changed, 110 insertions(+), 23 deletions(-) create mode 100755 compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 488439fd..9c2b2add 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -329,13 +329,13 @@ class bank(design.design): self.input_control_signals = [] port_num = 0 for port in range(OPTS.num_rw_ports): - self.input_control_signals.append(["s_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) + self.input_control_signals.append(["p_en_bar{}".format(port_num), "s_en{}".format(port_num), "w_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_w_ports): - self.input_control_signals.append(["w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) + self.input_control_signals.append(["p_en_bar{}".format(port_num), "w_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_r_ports): - self.input_control_signals.append(["s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) + self.input_control_signals.append(["p_en_bar{}".format(port_num), "s_en{}".format(port_num)]) port_num += 1 # Number of control lines in the bus for each port @@ -691,6 +691,8 @@ class bank(design.design): make_pins=(self.num_banks==1), pitch=self.m3_pitch) + self.copy_layout_pin(self.port_address_inst[0], "wl_en", self.prefix + "wl_en0") + # Port 1 if len(self.all_ports)==2: # The other control bus is routed up to two pitches above the bitcell array @@ -706,6 +708,8 @@ class bank(design.design): make_pins=(self.num_banks==1), pitch=self.m3_pitch) + self.copy_layout_pin(self.port_address_inst[1], "wl_en", self.prefix + "wl_en1") + def route_port_data_to_bitcell_array(self, port): """ Routing of BL and BR between port data and bitcell array """ @@ -1054,21 +1058,6 @@ class bank(design.design): to_layer="m2", offset=control_pos) - # clk to wordline_driver - control_signal = self.prefix + "wl_en{}".format(port) - if port % 2: - pin_pos = self.port_address_inst[port].get_pin("wl_en").uc() - control_y_offset = self.bus_pins[port][control_signal].by() - mid_pos = vector(pin_pos.x, control_y_offset + self.m1_pitch) - else: - pin_pos = self.port_address_inst[port].get_pin("wl_en").bc() - control_y_offset = self.bus_pins[port][control_signal].uy() - mid_pos = vector(pin_pos.x, control_y_offset - self.m1_pitch) - control_x_offset = self.bus_pins[port][control_signal].cx() - control_pos = vector(control_x_offset, mid_pos.y) - self.add_wire(self.m1_stack, [pin_pos, mid_pos, control_pos]) - self.add_via_center(layers=self.m1_stack, - offset=control_pos) def graph_exclude_precharge(self): """ diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 0c9d50bf..5aec6872 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -333,8 +333,9 @@ class control_logic(design.design): row += 1 self.place_gated_clk_buf_row(row) row += 1 - self.place_wlen_row(row) - row += 1 + if (self.port_type == "rw") or (self.port_type == "r"): + self.place_sen_row(row) + row += 1 if (self.port_type == "rw") or (self.port_type == "w"): self.place_wen_row(row) height = self.w_en_gate_inst.uy() @@ -345,9 +346,8 @@ class control_logic(design.design): if (self.port_type == "rw") or (self.port_type == "w"): self.place_rbl_delay_row(row) row += 1 - if (self.port_type == "rw") or (self.port_type == "r"): - self.place_sen_row(row) - row += 1 + self.place_wlen_row(row) + row += 1 self.place_delay(row) height = self.delay_inst.uy() control_center_y = self.delay_inst.by() diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index d831c047..6bc2cd43 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -340,6 +340,15 @@ class sram_1bank(sram_base): def route_dff(self, port, add_routes): + # This is only done when we add_routes because the data channel will be larger + # so that can be used for area estimation. + if add_routes: + self.route_col_addr_dffs(port) + + self.route_data_dffs(port, add_routes) + + def route_col_addr_dffs(self, port): + route_map = [] # column mux dff is routed on it's own since it is to the far end @@ -351,6 +360,38 @@ class sram_1bank(sram_base): bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] route_map.extend(list(zip(bank_pins, dff_pins))) + if len(route_map) > 0: + + layer_stack = self.m1_stack + + if port == 0: + offset = vector(self.control_logic_insts[port].rx() + self.dff.width, + - self.data_bus_size[port] + 2 * self.m3_pitch) + cr = channel_route(netlist=route_map, + offset=offset, + layer_stack=layer_stack, + parent=self) + # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # with no active devices. + self.add_inst(cr.name, cr) + self.connect_inst([]) + #self.add_flat_inst(cr.name, cr) + else: + offset = vector(0, + self.bank.height + self.m3_pitch) + cr = channel_route(netlist=route_map, + offset=offset, + layer_stack=layer_stack, + parent=self) + # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # with no active devices. + self.add_inst(cr.name, cr) + self.connect_inst([]) + #self.add_flat_inst(cr.name, cr) + + def route_data_dffs(self, port, add_routes): + route_map = [] + # wmask dff if self.num_wmasks > 0 and port in self.write_ports: dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] @@ -377,6 +418,7 @@ class sram_1bank(sram_base): if len(route_map) > 0: + # The write masks will have blockages on M1 if self.num_wmasks > 0 and port in self.write_ports: layer_stack = self.m3_stack else: diff --git a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py new file mode 100755 index 00000000..8bcc0415 --- /dev/null +++ b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class sram_1bank_4mux_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + c = sram_config(word_size=4, + num_words=64, + num_banks=1) + + c.words_per_row=4 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 6e2f60353c3ccf86d6cfd1ed78961817bafbc635 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Mar 2021 10:00:24 -0700 Subject: [PATCH 57/78] Add wells to driver stages. Remove unnecessary height/center in control logic. --- compiler/modules/control_logic.py | 2 -- compiler/pgates/pdriver.py | 4 +--- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 5aec6872..eb9a21ed 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -338,8 +338,6 @@ class control_logic(design.design): row += 1 if (self.port_type == "rw") or (self.port_type == "w"): self.place_wen_row(row) - height = self.w_en_gate_inst.uy() - control_center_y = self.w_en_gate_inst.uy() row += 1 self.place_pen_row(row) row += 1 diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 4662577b..bbadb9ab 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -87,13 +87,11 @@ class pdriver(pgate.pgate): def add_modules(self): self.inv_list = [] - add_well = self.add_wells for size in self.size_list: temp_inv = factory.create(module_type="pinv", size=size, height=self.height, - add_wells=add_well) - add_well=False + add_wells=self.add_wells) self.inv_list.append(temp_inv) self.add_mod(temp_inv) From e681806f0dd2641113585a9c6a1faf8b7a9e576c Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Mar 2021 10:02:34 -0700 Subject: [PATCH 58/78] Update to 24 threads. --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 894cbd55..ef2ef6a6 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -13,7 +13,7 @@ jobs: export OPENRAM_TECH="${{ github.workspace }}/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm - $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm + $OPENRAM_HOME/tests/regress.py -j 24 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -32,7 +32,7 @@ jobs: export OPENRAM_TECH="${{ github.workspace }}/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 + $OPENRAM_HOME/tests/regress.py -j 24 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From b9086dbbe5746264dc7c3e29f983d0d9afba34d1 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Mar 2021 06:56:58 -0700 Subject: [PATCH 59/78] Add unit test times to output. --- compiler/tests/testutils.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index ed24f8cf..987b64e4 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -12,11 +12,19 @@ from globals import OPTS import debug import pdb import traceback +import time class openram_test(unittest.TestCase): """ Base unit test that we have some shared classes in. """ + def setUp(self): + self.start_time = time.time() + + def tearDown(self): + duration = time.time() - self.start_time + print('%s: %.3fs' % (self.id(), duration)) + def fail(self, msg): import inspect s = inspect.stack() From 7e29dd7ff2cc78df18d229cce05cf33bb0514c7e Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 31 Mar 2021 09:38:06 -0700 Subject: [PATCH 60/78] Reduce verbosity of routing info --- compiler/router/supply_tree_router.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index e0455602..ba54ee39 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -110,7 +110,7 @@ class supply_tree_router(router): # Route MST components for index, (src, dest) in enumerate(connections): if not (index % 100): - debug.info(0, "{0} supply segments routed, {1} remaining.".format(index, len(connections) - index)) + debug.info(1, "{0} supply segments routed, {1} remaining.".format(index, len(connections) - index)) self.route_signal(pin_name, src, dest) # if pin_name == "gnd": # print("\nSRC {}: ".format(src) + str(self.pin_groups[pin_name][src].grids) + str(self.pin_groups[pin_name][src].blockages)) From c7f99aef2c1dc211bac1ae854b8c4d7ea6b78a3f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 31 Mar 2021 12:14:20 -0700 Subject: [PATCH 61/78] Add functional comment to aid debugging checks. --- compiler/characterizer/functional.py | 33 ++++++++++++++++++---------- compiler/characterizer/setup_hold.py | 8 ++++++- compiler/characterizer/stimuli.py | 25 +++++++++------------ 3 files changed, 38 insertions(+), 28 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index fb0a176f..dad4fd96 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -227,18 +227,18 @@ class functional(simulation): def add_read_check(self, word, port): """ Add to the check array to ensure a read works. """ try: - self.check + self.check_count except: - self.check = 0 - self.read_check.append([word, "{0}{1}".format(self.dout_name, port), self.t_current + self.period, self.check]) - self.check += 1 + self.check_count = 0 + self.read_check.append([word, "{0}{1}".format(self.dout_name, port), self.t_current + self.period, self.check_count]) + self.check_count += 1 def read_stim_results(self): # Extract dout values from spice timing.lis - for (word, dout_port, eo_period, check) in self.read_check: + for (word, dout_port, eo_period, check_count) in self.read_check: sp_read_value = "" for bit in range(self.word_size + self.num_spare_cols): - value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(), bit, check)) + value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(), bit, check_count)) try: value = float(value) if value > self.v_high: @@ -260,7 +260,7 @@ class functional(simulation): return (0, error) - self.read_results.append([sp_read_value, dout_port, eo_period, check]) + self.read_results.append([sp_read_value, dout_port, eo_period, check_count]) return (1, "SUCCESS") def check_stim_results(self): @@ -432,12 +432,21 @@ class functional(simulation): # Generate dout value measurements self.sf.write("\n * Generation of dout measurements\n") for (word, dout_port, eo_period, check) in self.read_check: - t_intital = eo_period - 0.01 * self.period + t_initial = eo_period - 0.01 * self.period t_final = eo_period + 0.01 * self.period - for bit in range(self.word_size + self.num_spare_cols): - self.stim.gen_meas_value(meas_name="V{0}_{1}ck{2}".format(dout_port, bit, check), - dout="{0}_{1}".format(dout_port, bit), - t_intital=t_intital, + num_bits = self.word_size + self.num_spare_cols + for bit in range(num_bits): + measure_name = "V{0}_{1}ck{2}".format(dout_port, bit, check) + signal_name = "{0}_{1}".format(dout_port, bit) + voltage_value = self.stim.get_voltage(word[num_bits - bit - 1]) + + self.stim.add_comment("* CHECK {0} {1} = {2} time = {3}".format(signal_name, + measure_name, + voltage_value, + eo_period)) + self.stim.gen_meas_value(meas_name=measure_name, + dout=signal_name, + t_initial=t_initial, t_final=t_final) self.stim.write_control(self.cycle_times[-1] + self.period) diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index 83ec835b..b323078a 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -82,7 +82,13 @@ class setup_hold(): """ self.sf.write("\n* Generation of the data and clk signals\n") - incorrect_value = self.stim.get_inverse_value(correct_value) + if correct_value == 1: + incorrect_value = 0 + elif correct_value == 0: + incorrect_value = 1 + else: + debug.error("Invalid value {}".format(correct_value)) + if mode=="HOLD": init_value = incorrect_value start_value = correct_value diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 06b6058d..0895d57e 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -169,22 +169,14 @@ class stimuli(): def gen_constant(self, sig_name, v_val): """ Generates a constant signal with reference voltage and the voltage value """ self.sf.write("V{0} {0} 0 DC {1}\n".format(sig_name, v_val)) - - def get_inverse_voltage(self, value): - if value > 0.5 * self.voltage: + + def get_voltage(self, value): + if value == "0" or value == 0: return 0 - elif value <= 0.5 * self.voltage: + elif value == "1" or value == 1: return self.voltage else: - debug.error("Invalid value to get an inverse of: {0}".format(value)) - - def get_inverse_value(self, value): - if value > 0.5: - return 0 - elif value <= 0.5: - return 1 - else: - debug.error("Invalid value to get an inverse of: {0}".format(value)) + debug.error("Invalid value to get a voltage of: {0}".format(value)) def gen_meas_delay(self, meas_name, trig_name, targ_name, trig_val, targ_val, trig_dir, targ_dir, trig_td, targ_td): """ Creates the .meas statement for the measurement of delay """ @@ -228,8 +220,8 @@ class stimuli(): t_initial, t_final)) - def gen_meas_value(self, meas_name, dout, t_intital, t_final): - measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t_intital, t_final) + def gen_meas_value(self, meas_name, dout, t_initial, t_final): + measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t_initial, t_final) self.sf.write(measure_string) def write_control(self, end_time, runlvl=4): @@ -310,6 +302,9 @@ class stimuli(): for item in list(includes): self.sf.write(".include \"{0}\"\n".format(item)) + def add_comment(self, msg): + self.sf.write(msg + "\n") + def write_supply(self): """ Writes supply voltage statements """ gnd_node_name = "0" From 014c95f761fa77e579e7cafee3902716d519c9b5 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 1 Apr 2021 16:48:15 -0700 Subject: [PATCH 62/78] Add accounting output to ngspice --- compiler/characterizer/functional.py | 2 +- compiler/characterizer/stimuli.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index dad4fd96..35444b15 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -439,7 +439,7 @@ class functional(simulation): measure_name = "V{0}_{1}ck{2}".format(dout_port, bit, check) signal_name = "{0}_{1}".format(dout_port, bit) voltage_value = self.stim.get_voltage(word[num_bits - bit - 1]) - + self.stim.add_comment("* CHECK {0} {1} = {2} time = {3}".format(signal_name, measure_name, voltage_value, diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 0895d57e..d60cab85 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -246,7 +246,7 @@ class stimuli(): # which is more accurate, but slower than the default trapezoid method # Do not remove this or it may not converge due to some "pa_00" nodes # unless you figure out what these are. - self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear\n".format(reltol)) + self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear ACCT\n".format(reltol)) elif OPTS.spice_name == "spectre": self.sf.write("simulator lang=spectre\n") if OPTS.use_pex: From e0024fa79a5851c4876c4f33890807da6a511394 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 6 Apr 2021 12:52:50 -0700 Subject: [PATCH 63/78] Add verbosity to error output --- compiler/router/pin_group.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 5f9da465..7a5d8817 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -148,8 +148,9 @@ class pin_group: enclosure = self.router.compute_pin_enclosure(ll, ur, ll.z) pin_list.append(enclosure) - debug.check(len(pin_list) > 0, - "Did not find any enclosures.") + if len(pin_list) == 0: + debug.error("Did not find any enclosures for {}".format(self.name)) + self.router.write_debug_gds("pin_enclosure_error.gds") # Now simplify the enclosure list new_pin_list = self.remove_redundant_shapes(pin_list) From 31d3e6cb26022e4cab05413daae63a55af2aa55c Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 6 Apr 2021 12:53:10 -0700 Subject: [PATCH 64/78] Change LWL layers --- compiler/modules/local_bitcell_array.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 67eac001..f0427c51 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -239,7 +239,12 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): out_loc = out_pin.lc() mid_loc = vector(self.wl_insts[port].lx() - 1.5 * self.m3_pitch, out_loc.y) in_loc = in_pin.rc() - self.add_path(out_pin.layer, [out_loc, mid_loc, in_loc]) + + self.add_path(out_pin.layer, [out_loc, mid_loc]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=mid_loc) + self.add_path(in_pin.layer, [mid_loc, in_loc]) def get_main_array_top(self): return self.bitcell_array_inst.by() + self.bitcell_array.get_main_array_top() From d609e4ea04774dcf574ba7b64b36b81ac965276b Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 6 Apr 2021 17:01:52 -0700 Subject: [PATCH 65/78] Reimplement trim options (except on unit tests). Allow trim netlist to be used for delay and functional simulation. Each class implements a "trim_insts" set of instances that can be removed. By default far left, right, top and bottom cells in the bitcell arrays are kept. Use lvs option in sp_write Fix lvs option in sram. --- compiler/base/hierarchy_design.py | 6 +- compiler/base/hierarchy_spice.py | 33 +++++----- compiler/characterizer/delay.py | 10 +-- compiler/characterizer/functional.py | 30 ++++++--- compiler/characterizer/lib.py | 7 +-- compiler/characterizer/simulation.py | 5 +- compiler/characterizer/trim_spice.py | 26 ++++---- compiler/modules/bitcell_array.py | 6 +- compiler/sram/sram.py | 7 +-- compiler/sram/sram_base.py | 9 ++- compiler/tests/21_hspice_delay_test.py | 63 +++++++++---------- compiler/tests/21_ngspice_delay_test.py | 58 ++++++++--------- .../tests/22_psram_1bank_2mux_func_test.py | 6 +- .../tests/22_psram_1bank_4mux_func_test.py | 6 +- .../tests/22_psram_1bank_8mux_func_test.py | 6 +- .../tests/22_psram_1bank_nomux_func_test.py | 6 +- .../tests/22_sram_1bank_2mux_func_test.py | 6 +- .../22_sram_1bank_2mux_global_func_test.py | 6 +- .../22_sram_1bank_2mux_sparecols_func_test.py | 6 +- .../tests/22_sram_1bank_4mux_func_test.py | 6 +- .../tests/22_sram_1bank_8mux_func_test.py | 6 +- .../22_sram_1bank_nomux_1rw_1r_func_test.py | 6 +- .../tests/22_sram_1bank_nomux_func_test.py | 5 +- ...22_sram_1bank_nomux_sparecols_func_test.py | 5 +- .../22_sram_1bank_wmask_1rw_1r_func_test.py | 6 +- compiler/tests/22_sram_wmask_func_test.py | 6 +- compiler/tests/23_lib_sram_test.py | 1 - compiler/tests/26_sram_pex_test.py | 2 +- compiler/tests/50_riscv_func_test.py | 6 +- compiler/tests/testutils.py | 2 +- 30 files changed, 147 insertions(+), 206 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index fe1f4c55..d99c7363 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -53,7 +53,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): elif (OPTS.inline_lvsdrc or force_check or final_verification): tempspice = "{}.sp".format(self.name) - self.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice)) + self.sp_write("{0}{1}".format(OPTS.openram_temp, tempspice), lvs=True) tempgds = "{}.gds".format(self.name) self.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) # Final verification option does not allow nets to be connected by label. @@ -82,7 +82,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): return elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempspice = "{}.sp".format(self.name) - self.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice)) + self.sp_write("{0}{1}".format(OPTS.openram_temp, tempspice), lvs=True) tempgds = "{}.gds".format(self.cell_name) self.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) num_errors = verify.run_drc(self.cell_name, tempgds, tempspice, final_verification=final_verification) @@ -102,7 +102,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): return elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): tempspice = "{}.sp".format(self.cell_name) - self.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice)) + self.sp_write("{0}{1}".format(OPTS.openram_temp, tempspice), lvs=True) tempgds = "{}.gds".format(self.name) self.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 51d2c3b7..2f2d3ec9 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -63,6 +63,8 @@ class spice(): self.conns = [] # If this is set, it will out output subckt or isntances of this (for row/col caps etc.) self.no_instances = False + # If we are doing a trimmed netlist, these are the instance that will be filtered + self.trim_insts = set() # Keep track of any comments to add the the spice try: self.commments @@ -312,10 +314,11 @@ class spice(): return True return False - def sp_write_file(self, sp, usedMODS, lvs_netlist=False): + def sp_write_file(self, sp, usedMODS, lvs=False, trim=False): """ Recursive spice subcircuit write; - Writes the spice subcircuit from the library or the dynamically generated one + Writes the spice subcircuit from the library or the dynamically generated one. + Trim netlist is intended ONLY for bitcell arrays. """ if self.no_instances: @@ -328,7 +331,7 @@ class spice(): if self.contains(i, usedMODS): continue usedMODS.append(i) - i.sp_write_file(sp, usedMODS, lvs_netlist) + i.sp_write_file(sp, usedMODS, lvs, trim) if len(self.insts) == 0: return @@ -371,10 +374,16 @@ class spice(): # these are wires and paths if self.conns[i] == []: continue + # Instance with no devices in it needs no subckt/instance if self.insts[i].mod.no_instances: continue - if lvs_netlist and hasattr(self.insts[i].mod, "lvs_device"): + + # If this is a trimmed netlist, skip it by adding comment char + if trim and self.insts[i].name in self.trim_insts: + sp.write("* ") + + if lvs and hasattr(self.insts[i].mod, "lvs_device"): sp.write(self.insts[i].mod.lvs_device.format(self.insts[i].name, " ".join(self.conns[i]))) sp.write("\n") @@ -394,30 +403,20 @@ class spice(): # Including the file path makes the unit test fail for other users. # if os.path.isfile(self.sp_file): # sp.write("\n* {0}\n".format(self.sp_file)) - if lvs_netlist and hasattr(self, "lvs"): + if lvs and hasattr(self, "lvs"): sp.write("\n".join(self.lvs)) else: sp.write("\n".join(self.spice)) sp.write("\n") - def sp_write(self, spname): + def sp_write(self, spname, lvs=False, trim=False): """Writes the spice to files""" debug.info(3, "Writing to {0}".format(spname)) spfile = open(spname, 'w') spfile.write("*FIRST LINE IS A COMMENT\n") usedMODS = list() - self.sp_write_file(spfile, usedMODS) - del usedMODS - spfile.close() - - def lvs_write(self, spname): - """Writes the lvs to files""" - debug.info(3, "Writing to {0}".format(spname)) - spfile = open(spname, 'w') - spfile.write("*FIRST LINE IS A COMMENT\n") - usedMODS = list() - self.sp_write_file(spfile, usedMODS, True) + self.sp_write_file(spfile, usedMODS, lvs=lvs, trim=trim) del usedMODS spfile.close() diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index f491d8b0..168a73e9 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1100,14 +1100,8 @@ class delay(simulation): # Set up to trim the netlist here if that is enabled if OPTS.trim_netlist: - self.trim_sp_file = "{}reduced.sp".format(OPTS.openram_temp) - self.trimsp=trim_spice(self.sp_file, self.trim_sp_file) - self.trimsp.set_configuration(self.num_banks, - self.num_rows, - self.num_cols, - self.word_size, - self.num_spare_rows) - self.trimsp.trim(self.probe_address, self.probe_data) + self.trim_sp_file = "{}trimmed.sp".format(OPTS.openram_temp) + self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True) else: # The non-reduced netlist file when it is disabled self.trim_sp_file = "{}sram.sp".format(OPTS.openram_temp) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 35444b15..0435d22e 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -21,13 +21,17 @@ class functional(simulation): for successful SRAM operation. """ - def __init__(self, sram, spfile, corner=None, cycles=15, period=None, output_path=None): + def __init__(self, sram, spfile=None, corner=None, cycles=15, period=None, output_path=None): super().__init__(sram, spfile, corner) # Seed the characterizer with a constant seed for unit tests if OPTS.is_unit_test: random.seed(12345) + if not spfile: + # self.sp_file is assigned in base class + sram.sp_write(self.sp_file, trim=OPTS.trim_netlist) + if not corner: corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) @@ -46,7 +50,18 @@ class functional(simulation): if not self.num_spare_cols: self.num_spare_cols = 0 + if self.num_spare_cols > 0: + debug.error("Functional simulation not debugged with spare columns.") + # FIXME: we need to remember the correct value of the spare columns + self.max_value = 2 ** (self.word_size + self.num_spare_cols) - 1 + # If trim is set, specify the valid addresses + self.valid_addresses = set() + self.max_address = 2**self.addr_size - 1 + (self.num_spare_rows * self.words_per_row) + if OPTS.trim_netlist: + for i in range(self.words_per_row): + self.valid_addresses.add(i) + self.valid_addresses.add(self.max_address - i) self.probe_address, self.probe_data = '0' * self.addr_size, 0 self.set_corner(corner) self.set_spice_constants() @@ -300,21 +315,16 @@ class functional(simulation): def gen_data(self): """ Generates a random word to write. """ - if not self.num_spare_cols: - random_value = random.randint(0, (2 ** self.word_size) - 1) - else: - random_value1 = random.randint(0, (2 ** self.word_size) - 1) - random_value2 = random.randint(0, (2 ** self.num_spare_cols) - 1) - random_value = random_value1 + random_value2 + random_value = random.randint(0, self.max_value) data_bits = self.convert_to_bin(random_value, False) return data_bits def gen_addr(self): """ Generates a random address value to write to. """ - if self.num_spare_rows==0: - random_value = random.randint(0, (2 ** self.addr_size) - 1) + if self.valid_addresses: + random_value = random.sample(self.valid_addresses, 1)[0] else: - random_value = random.randint(0, ((2 ** (self.addr_size - 1) - 1)) + (self.num_spare_rows * self.words_per_row)) + random_value = random.randint(0, self.max_address) addr_bits = self.convert_to_bin(random_value, True) return addr_bits diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index d37119a9..aa892b3d 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -5,9 +5,8 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import os,sys,re +import os import debug -import math import datetime from .setup_hold import * from .delay import * @@ -16,6 +15,7 @@ import tech import numpy as np from globals import OPTS + class lib: """ lib file generation.""" @@ -601,7 +601,6 @@ class lib: from .elmore import elmore as model else: debug.error("{} model not recognized. See options.py for available models.".format(OPTS.model_name)) - import math m = model(self.sram, self.sp_file, self.corner) char_results = m.get_lib_values(self.slews,self.loads) @@ -834,4 +833,4 @@ class lib: #FIXME: should be read_fall_power datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), read0_power)) - \ No newline at end of file + diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 0afe2459..5becbacf 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -27,7 +27,10 @@ class simulation(): self.num_spare_cols = 0 else: self.num_spare_cols = self.sram.num_spare_cols - self.sp_file = spfile + if not spfile: + self.sp_file = OPTS.openram_temp + "sram.sp" + else: + self.sp_file = spfile self.all_ports = self.sram.all_ports self.readwrite_ports = self.sram.readwrite_ports diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py index d659212c..e8499d5c 100644 --- a/compiler/characterizer/trim_spice.py +++ b/compiler/characterizer/trim_spice.py @@ -9,6 +9,7 @@ import debug from math import log,ceil import re + class trim_spice(): """ A utility to trim redundant parts of an SRAM spice netlist. @@ -29,7 +30,6 @@ class trim_spice(): for i in range(len(self.spice)): self.spice[i] = self.spice[i].rstrip(" \n") - self.sp_buffer = self.spice def set_configuration(self, banks, rows, columns, word_size): @@ -46,21 +46,23 @@ class trim_spice(): self.col_addr_size = int(log(self.words_per_row, 2)) self.bank_addr_size = self.col_addr_size + self.row_addr_size self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) - - + def trim(self, address, data_bit): - """ Reduce the spice netlist but KEEP the given bits at the - address (and things that will add capacitive load!)""" + """ + Reduce the spice netlist but KEEP the given bits at the + address (and things that will add capacitive load!) + """ # Always start fresh if we do multiple reductions self.sp_buffer = self.spice # Split up the address and convert to an int - wl_address = int(address[self.col_addr_size:],2) - if self.col_addr_size>0: - col_address = int(address[0:self.col_addr_size],2) + wl_address = int(address[self.col_addr_size:], 2) + if self.col_addr_size > 0: + col_address = int(address[0:self.col_addr_size], 2) else: col_address = 0 + # 1. Keep cells in the bitcell array based on WL and BL wl_name = "wl_{}".format(wl_address) bl_name = "bl_{}".format(int(self.words_per_row*data_bit + col_address)) @@ -81,7 +83,6 @@ class trim_spice(): self.sp_buffer.insert(0, "* It should NOT be used for LVS!!") self.sp_buffer.insert(0, "* WARNING: This is a TRIMMED NETLIST.") - wl_regex = r"wl\d*_{}".format(wl_address) bl_regex = r"bl\d*_{}".format(int(self.words_per_row*data_bit + col_address)) self.remove_insts("bitcell_array",[wl_regex,bl_regex]) @@ -91,11 +92,11 @@ class trim_spice(): #self.remove_insts("sense_amp_array",[bl_regex]) # 3. Keep column muxes basd on BL - self.remove_insts("column_mux_array",[bl_regex]) + self.remove_insts("column_mux_array", [bl_regex]) # 4. Keep write driver based on DATA data_regex = r"data_{}".format(data_bit) - self.remove_insts("write_driver_array",[data_regex]) + self.remove_insts("write_driver_array", [data_regex]) # 5. Keep wordline driver based on WL # Need to keep the gater too @@ -111,7 +112,6 @@ class trim_spice(): sp.write("\n".join(self.sp_buffer)) sp.close() - def remove_insts(self, subckt_name, keep_inst_list): """This will remove all of the instances in the list from the named subckt that DO NOT contain a term in the list. It just does a @@ -119,7 +119,7 @@ class trim_spice(): net connection, the instance name, anything.. """ removed_insts = 0 - #Expects keep_inst_list are regex patterns. Compile them here. + # Expects keep_inst_list are regex patterns. Compile them here. compiled_patterns = [re.compile(pattern) for pattern in keep_inst_list] start_name = ".SUBCKT {}".format(subckt_name) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index c7d8ff81..9d1cc0de 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -64,7 +64,11 @@ class bitcell_array(bitcell_base_array): self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell) self.connect_inst(self.get_bitcell_pins(row, col)) - + + # If it is a "core" cell, it could be trimmed for sim time + if col>0 and col0 and row Date: Tue, 6 Apr 2021 19:01:33 -0700 Subject: [PATCH 66/78] Remove lvs_write from sram --- compiler/sram/sram.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index 00fbd4df..599ef666 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -120,7 +120,7 @@ class sram(): start_time = datetime.datetime.now() lvsname = OPTS.output_path + self.s.name + ".lvs.sp" debug.print_raw("LVS: Writing to {0}".format(lvsname)) - self.lvs_write(lvsname) + self.sp_write(lvsname, lvs=True) if not OPTS.netlist_only and OPTS.check_lvsdrc: verify.write_lvs_script(cell_name=self.s.name, gds_name=os.path.basename(gdsname), From 5843aa037c5f72d88053acf8b4c02558b244ed35 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 7 Apr 2021 10:33:48 -0700 Subject: [PATCH 67/78] Update functional test to use spare columns separately. Fix no spare columns data width error. --- compiler/characterizer/functional.py | 58 +++++++++++++++------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 0435d22e..7deee2ef 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -50,11 +50,10 @@ class functional(simulation): if not self.num_spare_cols: self.num_spare_cols = 0 - if self.num_spare_cols > 0: - debug.error("Functional simulation not debugged with spare columns.") - # FIXME: we need to remember the correct value of the spare columns - self.max_value = 2 ** (self.word_size + self.num_spare_cols) - 1 + self.max_data = 2 ** self.word_size - 1 + self.max_col_data = 2 ** self.num_spare_cols - 1 + self.words_per_row_bits = int(math.log(self.words_per_row) / math.log(2)) # If trim is set, specify the valid addresses self.valid_addresses = set() self.max_address = 2**self.addr_size - 1 + (self.num_spare_rows * self.words_per_row) @@ -81,6 +80,7 @@ class functional(simulation): self.num_cycles = cycles # This is to have ordered keys for random selection self.stored_words = collections.OrderedDict() + self.stored_spares = collections.OrderedDict() self.read_check = [] self.read_results = [] @@ -136,10 +136,11 @@ class functional(simulation): # 1. Write all the write ports first to seed a bunch of locations. for port in self.write_ports: addr = self.gen_addr() - word = self.gen_data() + (word, spare) = self.gen_data() comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current) - self.add_write_one_port(comment, addr, word, "1" * self.num_wmasks, port) + self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port) self.stored_words[addr] = word + self.stored_spares[addr[:-self.words_per_row_bits]] = spare # All other read-only ports are noops. for port in self.read_ports: @@ -185,27 +186,31 @@ class functional(simulation): if addr in w_addrs: self.add_noop_one_port(port) else: - word = self.gen_data() + (word, spare) = self.gen_data() comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current) - self.add_write_one_port(comment, addr, word, "1" * self.num_wmasks, port) + self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port) self.stored_words[addr] = word + self.stored_spares[addr[:-self.words_per_row_bits]] = spare w_addrs.append(addr) elif op == "partial_write": # write only to a word that's been written to - (addr, old_word) = self.get_data() + (addr, old_word, old_spares) = self.get_data() # two ports cannot write to the same address if addr in w_addrs: self.add_noop_one_port(port) else: - word = self.gen_data() + (word, spare) = self.gen_data() wmask = self.gen_wmask() new_word = self.gen_masked_data(old_word, word, wmask) comment = self.gen_cycle_comment("partial_write", word, addr, wmask, port, self.t_current) - self.add_write_one_port(comment, addr, word, wmask, port) + self.add_write_one_port(comment, addr, word + spare, wmask, port) self.stored_words[addr] = new_word + self.stored_spares[addr[:-self.words_per_row_bits]] = spare w_addrs.append(addr) else: (addr, word) = random.choice(list(self.stored_words.items())) + spare = self.stored_spares[addr[:-self.words_per_row_bits]] + combined_word = word + spare # The write driver is not sized sufficiently to drive through the two # bitcell access transistors to the read port. So, for now, we do not allow # a simultaneous write and read to the same address on different ports. This @@ -213,9 +218,9 @@ class functional(simulation): if addr in w_addrs: self.add_noop_one_port(port) else: - comment = self.gen_cycle_comment("read", word, addr, "0" * self.num_wmasks, port, self.t_current) + comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current) self.add_read_one_port(comment, addr, port) - self.add_read_check(word, port) + self.add_read_check(combined_word, port) self.cycle_times.append(self.t_current) self.t_current += self.period @@ -315,9 +320,14 @@ class functional(simulation): def gen_data(self): """ Generates a random word to write. """ - random_value = random.randint(0, self.max_value) - data_bits = self.convert_to_bin(random_value, False) - return data_bits + random_value = random.randint(0, self.max_data) + data_bits = self.convert_to_bin(random_value, self.word_size) + if self.num_spare_cols>0: + random_value = random.randint(0, self.max_col_data) + spare_bits = self.convert_to_bin(random_value, self.num_spare_cols) + else: + spare_bits = "" + return data_bits, spare_bits def gen_addr(self): """ Generates a random address value to write to. """ @@ -325,7 +335,7 @@ class functional(simulation): random_value = random.sample(self.valid_addresses, 1)[0] else: random_value = random.randint(0, self.max_address) - addr_bits = self.convert_to_bin(random_value, True) + addr_bits = self.convert_to_bin(random_value, self.addr_size) return addr_bits def get_data(self): @@ -333,19 +343,13 @@ class functional(simulation): # Used for write masks since they should be writing to previously written addresses addr = random.choice(list(self.stored_words.keys())) word = self.stored_words[addr] - return (addr, word) + spare = self.stored_spares[addr[:-self.words_per_row_bits]] + return (addr, word, spare) - def convert_to_bin(self, value, is_addr): - """ Converts addr & word to usable binary values. """ + def convert_to_bin(self, value, size): new_value = str.replace(bin(value), "0b", "") - if(is_addr): - expected_value = self.addr_size - else: - expected_value = self.word_size + self.num_spare_cols - for i in range(expected_value - len(new_value)): + for i in range(size - len(new_value)): new_value = "0" + new_value - - # print("Binary Conversion: {} to {}".format(value, new_value)) return new_value def write_functional_stimulus(self): From 229b0059c4035b3a6c0e5a7e6d59e8ce3531222f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 7 Apr 2021 12:17:16 -0700 Subject: [PATCH 68/78] Add perimeter margin to expand pins outside perimeter for OpenRoad router. --- compiler/router/router.py | 17 ++++++++++------- compiler/router/signal_escape_router.py | 13 +++++++++---- compiler/sram/sram_base.py | 4 +++- 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index dc0c8e8d..aa01c71f 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -28,7 +28,7 @@ class router(router_tech): route on a given layer. This is limited to two layer routes. It populates blockages on a grid class. """ - def __init__(self, layers, design, gds_filename=None, bbox=None, route_track_width=1): + def __init__(self, layers, design, gds_filename=None, bbox=None, margin=0, route_track_width=1): """ This will instantiate a copy of the gds file or the module at (0,0) and route on top of this. The blockages from the gds/module will be @@ -83,9 +83,11 @@ class router(router_tech): # A list of path blockages (they might be expanded for wide metal DRC) self.path_blockages = [] - self.init_bbox(bbox) + # The perimeter pins should be placed outside the SRAM macro by a distance + self.margin = margin + self.init_bbox(bbox, margin) - def init_bbox(self, bbox=None): + def init_bbox(self, bbox=None, margin=0): """ Initialize the ll,ur values with the paramter or using the layout boundary. """ @@ -99,18 +101,19 @@ class router(router_tech): else: self.ll, self.ur = bbox - self.bbox = (self.ll, self.ur) + margin_offset = vector(margin, margin) + self.bbox = (self.ll - margin_offset, self.ur + margin_offset) size = self.ur - self.ll - debug.info(1, "Size: {0} x {1}".format(size.x, size.y)) + debug.info(1, "Size: {0} x {1} with perimeter margin {2}".format(size.x, size.y, margin)) def get_bbox(self): return self.bbox - def create_routing_grid(self, router_type, bbox=None): + def create_routing_grid(self, router_type): """ Create a sprase routing grid with A* expansion functions. """ - self.init_bbox(bbox) + self.init_bbox(self.bbox, self.margin) self.rg = router_type(self.ll, self.ur, self.track_width) def clear_pins(self): diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py index 846925bd..a9531290 100644 --- a/compiler/router/signal_escape_router.py +++ b/compiler/router/signal_escape_router.py @@ -17,12 +17,17 @@ class signal_escape_router(router): A router that routes signals to perimeter and makes pins. """ - def __init__(self, layers, design, bbox=None, gds_filename=None): + def __init__(self, layers, design, bbox=None, margin=0, gds_filename=None): """ This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). """ - router.__init__(self, layers, design, gds_filename, bbox) + router.__init__(self, + layers=layers, + design=design, + gds_filename=gds_filename, + bbox=bbox, + margin=margin) def perimeter_dist(self, pin_name): """ @@ -54,8 +59,8 @@ class signal_escape_router(router): start_time = datetime.now() for pin_name in ordered_pin_names: self.route_signal(pin_name) - #if pin_name == "dout1[1]": - # self.write_debug_gds("postroute.gds", False) + # if pin_name == "dout0[1]": + # self.write_debug_gds("postroute.gds", True) print_time("Maze routing pins",datetime.now(), start_time, 3) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index b683dbbc..fa0692e0 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -306,7 +306,9 @@ class sram_base(design, verilog, lef): pins_to_route.append("spare_wen{0}[{1}]".format(port, bit)) from signal_escape_router import signal_escape_router as router - rtr=router(self.m3_stack, self) + rtr=router(layers=self.m3_stack, + design=self, + margin=4 * self.m3_pitch) rtr.escape_route(pins_to_route) def compute_bus_sizes(self): From 61b1b90dd3f8fe0a7141cb003ef4768cc6adfed8 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 7 Apr 2021 14:23:47 -0700 Subject: [PATCH 69/78] Use built in binary conversion. Improve spare debug output. --- compiler/characterizer/functional.py | 52 ++++++++++++++++------------ 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 7deee2ef..f93de85c 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -9,6 +9,7 @@ import collections import debug import random import math +from numpy import binary_repr from .stimuli import * from .charutils import * from globals import OPTS @@ -53,7 +54,13 @@ class functional(simulation): self.max_data = 2 ** self.word_size - 1 self.max_col_data = 2 ** self.num_spare_cols - 1 - self.words_per_row_bits = int(math.log(self.words_per_row) / math.log(2)) + if self.words_per_row>1: + # This will truncate bits for word addressing in a row_addr_dff + # This makes one set of spares per row by using top bits of the address + self.addr_spare_index = -int(math.log(self.words_per_row) / math.log(2)) + else: + # This will select the entire address when one word per row + self.addr_spare_index = self.addr_size # If trim is set, specify the valid addresses self.valid_addresses = set() self.max_address = 2**self.addr_size - 1 + (self.num_spare_rows * self.words_per_row) @@ -137,10 +144,11 @@ class functional(simulation): for port in self.write_ports: addr = self.gen_addr() (word, spare) = self.gen_data() - comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current) + combined_word = "{}+{}".format(word, spare) + comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current) self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port) self.stored_words[addr] = word - self.stored_spares[addr[:-self.words_per_row_bits]] = spare + self.stored_spares[addr[:self.addr_spare_index]] = spare # All other read-only ports are noops. for port in self.read_ports: @@ -158,7 +166,9 @@ class functional(simulation): if port in self.write_ports: self.add_noop_one_port(port) else: - comment = self.gen_cycle_comment("read", word, addr, "0" * self.num_wmasks, port, self.t_current) + (addr, word, spare) = self.get_data() + combined_word = "{}+{}".format(word, spare) + comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current) self.add_read_one_port(comment, addr, port) self.add_read_check(word, port) self.cycle_times.append(self.t_current) @@ -187,14 +197,15 @@ class functional(simulation): self.add_noop_one_port(port) else: (word, spare) = self.gen_data() - comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current) + combined_word = "{}+{}".format(word, spare) + comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current) self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port) self.stored_words[addr] = word - self.stored_spares[addr[:-self.words_per_row_bits]] = spare + self.stored_spares[addr[:self.addr_spare_index]] = spare w_addrs.append(addr) elif op == "partial_write": # write only to a word that's been written to - (addr, old_word, old_spares) = self.get_data() + (addr, old_word, old_spare) = self.get_data() # two ports cannot write to the same address if addr in w_addrs: self.add_noop_one_port(port) @@ -202,15 +213,16 @@ class functional(simulation): (word, spare) = self.gen_data() wmask = self.gen_wmask() new_word = self.gen_masked_data(old_word, word, wmask) - comment = self.gen_cycle_comment("partial_write", word, addr, wmask, port, self.t_current) + combined_word = "{}+{}".format(word, spare) + comment = self.gen_cycle_comment("partial_write", combined_word, addr, wmask, port, self.t_current) self.add_write_one_port(comment, addr, word + spare, wmask, port) self.stored_words[addr] = new_word - self.stored_spares[addr[:-self.words_per_row_bits]] = spare + self.stored_spares[addr[:self.addr_spare_index]] = spare w_addrs.append(addr) else: (addr, word) = random.choice(list(self.stored_words.items())) - spare = self.stored_spares[addr[:-self.words_per_row_bits]] - combined_word = word + spare + spare = self.stored_spares[addr[:self.addr_spare_index]] + combined_word = "{}+{}".format(word, spare) # The write driver is not sized sufficiently to drive through the two # bitcell access transistors to the read port. So, for now, we do not allow # a simultaneous write and read to the same address on different ports. This @@ -220,7 +232,7 @@ class functional(simulation): else: comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current) self.add_read_one_port(comment, addr, port) - self.add_read_check(combined_word, port) + self.add_read_check(word + spare, port) self.cycle_times.append(self.t_current) self.t_current += self.period @@ -286,7 +298,7 @@ class functional(simulation): def check_stim_results(self): for i in range(len(self.read_check)): if self.read_check[i][0] != self.read_results[i][0]: - str = "FAILED: {0} value {1} does not match written value {2} read during cycle {3} at time {4}n" + str = "FAILED: {0} read value {1} does not match written value {2} during cycle {3} at time {4}n" error = str.format(self.read_results[i][1], self.read_results[i][0], self.read_check[i][0], @@ -321,10 +333,10 @@ class functional(simulation): def gen_data(self): """ Generates a random word to write. """ random_value = random.randint(0, self.max_data) - data_bits = self.convert_to_bin(random_value, self.word_size) + data_bits = binary_repr(random_value, self.word_size) if self.num_spare_cols>0: random_value = random.randint(0, self.max_col_data) - spare_bits = self.convert_to_bin(random_value, self.num_spare_cols) + spare_bits = binary_repr(random_value, self.num_spare_cols) else: spare_bits = "" return data_bits, spare_bits @@ -335,7 +347,7 @@ class functional(simulation): random_value = random.sample(self.valid_addresses, 1)[0] else: random_value = random.randint(0, self.max_address) - addr_bits = self.convert_to_bin(random_value, self.addr_size) + addr_bits = binary_repr(random_value, self.addr_size) return addr_bits def get_data(self): @@ -343,15 +355,9 @@ class functional(simulation): # Used for write masks since they should be writing to previously written addresses addr = random.choice(list(self.stored_words.keys())) word = self.stored_words[addr] - spare = self.stored_spares[addr[:-self.words_per_row_bits]] + spare = self.stored_spares[addr[:self.addr_spare_index]] return (addr, word, spare) - def convert_to_bin(self, value, size): - new_value = str.replace(bin(value), "0b", "") - for i in range(size - len(new_value)): - new_value = "0" + new_value - return new_value - def write_functional_stimulus(self): """ Writes SPICE stimulus. """ self.stim_sp = "functional_stim.sp" From b510925bdb3d980eafdcba2068d08a00a51b1f04 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 7 Apr 2021 15:19:12 -0700 Subject: [PATCH 70/78] Enable pruning by default (except on unit tests) --- compiler/options.py | 2 +- compiler/tests/22_psram_1bank_2mux_func_test.py | 3 ++- compiler/tests/22_psram_1bank_4mux_func_test.py | 3 ++- compiler/tests/22_psram_1bank_8mux_func_test.py | 3 ++- compiler/tests/22_psram_1bank_nomux_func_test.py | 3 ++- compiler/tests/22_sram_1bank_2mux_func_test.py | 3 ++- compiler/tests/22_sram_1bank_2mux_global_func_test.py | 3 ++- compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py | 1 + compiler/tests/22_sram_1bank_4mux_func_test.py | 3 ++- compiler/tests/22_sram_1bank_8mux_func_test.py | 3 ++- compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py | 2 ++ compiler/tests/22_sram_1bank_nomux_func_test.py | 1 + compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py | 1 + compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py | 2 ++ compiler/tests/22_sram_wmask_func_test.py | 1 + 15 files changed, 25 insertions(+), 9 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index 551c3950..67ac14d7 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -102,7 +102,7 @@ class options(optparse.Values): # This determines whether LVS and DRC is checked for every submodule. inline_lvsdrc = False # Remove noncritical memory cells for characterization speed-up - trim_netlist = False + trim_netlist = True # Run with extracted parasitics use_pex = False # Output config with all options diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index ef42fec1..f5f4cd8f 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -23,7 +23,8 @@ class psram_1bank_2mux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" OPTS.dummy_bitcell="dummy_pbitcell" diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 7e4e11b9..f422728b 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -24,7 +24,8 @@ class psram_1bank_4mux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" OPTS.dummy_bitcell="dummy_pbitcell" diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index d44f1326..f0247808 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -24,7 +24,8 @@ class psram_1bank_8mux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" OPTS.dummy_bitcell="dummy_pbitcell" diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index a6b666d3..203fd0ac 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -23,7 +23,8 @@ class psram_1bank_nomux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" OPTS.dummy_bitcell="dummy_pbitcell" diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index ba9e4129..cca6aeeb 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -24,7 +24,8 @@ class sram_1bank_2mux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer diff --git a/compiler/tests/22_sram_1bank_2mux_global_func_test.py b/compiler/tests/22_sram_1bank_2mux_global_func_test.py index f5f875b9..14de7ba8 100755 --- a/compiler/tests/22_sram_1bank_2mux_global_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_global_func_test.py @@ -24,7 +24,8 @@ class sram_1bank_2mux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py index 2242a002..c84c70a5 100755 --- a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py @@ -24,6 +24,7 @@ class sram_1bank_2mux_sparecols_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True + OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 8633f7fa..4f7035cc 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -24,7 +24,8 @@ class sram_1bank_4mux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index 1f50b579..cc6456cf 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -24,7 +24,8 @@ class sram_1bank_8mux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True - + OPTS.trim_netlist = False + # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer diff --git a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py index af465e62..c0518957 100755 --- a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py @@ -23,6 +23,8 @@ class psram_1bank_nomux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True + OPTS.trim_netlist = False + OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 4c2910f5..ff33ead5 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -24,6 +24,7 @@ class sram_1bank_nomux_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True + OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py index eec158d6..0d649ace 100755 --- a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py @@ -24,6 +24,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True + OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload diff --git a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py index 775597e1..6808462e 100755 --- a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py @@ -23,6 +23,8 @@ class sram_wmask_1w_1r_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True + OPTS.trim_netlist = False + OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index 3927bca2..f41b3d98 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -24,6 +24,7 @@ class sram_wmask_func_test(openram_test): globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True + OPTS.trim_netlist = False # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload From e706f776ebe98b052621461b6779b186f856368f Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 13 Apr 2021 16:24:13 -0700 Subject: [PATCH 71/78] Offset macro to 0,0 which was accidentally comented by a PR --- compiler/sram/sram_base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index fa0692e0..753200b8 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -196,7 +196,7 @@ class sram_base(design, verilog, lef): self.add_lvs_correspondence_points() - # self.offset_all_coordinates() + self.offset_all_coordinates() highest_coord = self.find_highest_coords() self.width = highest_coord[0] From 0e48e020c1764d89fe20168ec89ac57fed00a759 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 13 Apr 2021 16:24:28 -0700 Subject: [PATCH 72/78] Use pins in computing bbox offsets --- compiler/base/hierarchy_layout.py | 61 ++++++++++++++----------------- 1 file changed, 27 insertions(+), 34 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index fad5c8ae..f10280aa 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -15,6 +15,7 @@ from tech import layer_indices from tech import layer_stacks from tech import preferred_directions import os +import sys from globals import OPTS from vector import vector from pin_layout import pin_layout @@ -111,52 +112,44 @@ class layout(): Finds the lowest set of 2d cartesian coordinates within this layout """ + lowestx = lowesty = sys.maxsize if len(self.objs) > 0: - lowestx1 = min(obj.lx() for obj in self.objs if obj.name != "label") - lowesty1 = min(obj.by() for obj in self.objs if obj.name != "label") - else: - lowestx1 = lowesty1 = None + lowestx = min(min(obj.lx() for obj in self.objs if obj.name != "label"), lowestx) + lowesty = min(min(obj.by() for obj in self.objs if obj.name != "label"), lowesty) + if len(self.insts) > 0: - lowestx2 = min(inst.lx() for inst in self.insts) - lowesty2 = min(inst.by() for inst in self.insts) - else: - lowestx2 = lowesty2 = None + lowestx = min(min(inst.lx() for inst in self.insts), lowestx) + lowesty = min(min(inst.by() for inst in self.insts), lowesty) - if lowestx1 == None and lowestx2 == None: - return None - elif lowestx1 == None: - return vector(lowestx2, lowesty2) - elif lowestx2 == None: - return vector(lowestx1, lowesty1) - else: - return vector(min(lowestx1, lowestx2), min(lowesty1, lowesty2)) + if len(self.pin_map) > 0: + for pin_set in self.pin_map.values(): + lowestx = min(min(pin.lx() for pin in pin_set), lowestx) + lowesty = min(min(pin.by() for pin in pin_set), lowesty) + + return vector(lowestx, lowesty) def find_highest_coords(self): """ Finds the highest set of 2d cartesian coordinates within this layout """ + highestx = highesty = -sys.maxsize - 1 + if len(self.objs) > 0: - highestx1 = max(obj.rx() for obj in self.objs if obj.name != "label") - highesty1 = max(obj.uy() for obj in self.objs if obj.name != "label") - else: - highestx1 = highesty1 = None - if len(self.insts) > 0: - highestx2 = max(inst.rx() for inst in self.insts) - highesty2 = max(inst.uy() for inst in self.insts) - else: - highestx2 = highesty2 = None + highestx = max(max(obj.rx() for obj in self.objs if obj.name != "label"), highestx) + highesty = max(max(obj.uy() for obj in self.objs if obj.name != "label"), highesty) - if highestx1 == None and highestx2 == None: - return None - elif highestx1 == None: - return vector(highestx2, highesty2) - elif highestx2 == None: - return vector(highestx1, highesty1) - else: - return vector(max(highestx1, highestx2), - max(highesty1, highesty2)) + if len(self.insts) > 0: + highestx = max(max(inst.rx() for inst in self.insts), highestx) + highesty = max(max(inst.uy() for inst in self.insts), highesty) + + if len(self.pin_map) > 0: + for pin_set in self.pin_map.values(): + highestx = max(max(pin.rx() for pin in pin_set), highestx) + highesty = max(max(pin.uy() for pin in pin_set), highesty) + + return vector(highestx, highesty) def find_highest_layer_coords(self, layer): """ From a730fd0f10768171e165125f2b884a89c7fcee2a Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 14 Apr 2021 10:01:43 -0700 Subject: [PATCH 73/78] Use magic for LEF abstract. Fix supply perimter pin. --- compiler/base/hierarchy_layout.py | 4 +++ compiler/base/lef.py | 51 +++++++++++++++++++++++++++++-- compiler/router/router.py | 3 +- compiler/sram/sram_base.py | 18 +++++++---- 4 files changed, 67 insertions(+), 9 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index f10280aa..36a54937 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -124,6 +124,8 @@ class layout(): if len(self.pin_map) > 0: for pin_set in self.pin_map.values(): + if len(pin_set) == 0: + continue lowestx = min(min(pin.lx() for pin in pin_set), lowestx) lowesty = min(min(pin.by() for pin in pin_set), lowesty) @@ -146,6 +148,8 @@ class layout(): if len(self.pin_map) > 0: for pin_set in self.pin_map.values(): + if len(pin_set) == 0: + continue highestx = max(max(pin.rx() for pin in pin_set), highestx) highesty = max(max(pin.uy() for pin in pin_set), highesty) diff --git a/compiler/base/lef.py b/compiler/base/lef.py index 942a8ac2..8ca4918b 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -7,6 +7,9 @@ # import debug from tech import layer_names +import os +import shutil +from globals import OPTS class lef: @@ -23,9 +26,53 @@ class lef: # Round to ensure float values are divisible by 0.0025 (the manufacturing grid) self.round_grid = 4 + def magic_lef_write(self, lef_name): + """ Use a magic script to perform LEF creation. """ + debug.info(3, "Writing abstracted LEF to {0}".format(lef_name)) + + # Copy .magicrc file into the output directory + magic_file = OPTS.openram_tech + "tech/.magicrc" + if os.path.exists(magic_file): + shutil.copy(magic_file, OPTS.openram_temp) + else: + debug.warning("Could not locate .magicrc file: {}".format(magic_file)) + + gds_name = OPTS.openram_temp + "{}.gds".format(self.name) + self.gds_write(gds_name) + + run_file = OPTS.openram_temp + "run_lef.sh" + f = open(run_file, "w") + f.write("#!/bin/sh\n") + f.write('export OPENRAM_TECH="{}"\n'.format(os.environ['OPENRAM_TECH'])) + f.write('echo "$(date): Starting GDS to MAG using Magic {}"\n'.format(OPTS.drc_exe[1])) + f.write('\n') + f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1])) + f.write("drc off\n") + f.write("gds polygon subcell true\n") + f.write("gds warning default\n") + f.write("gds flatten true\n") + f.write("gds ordering true\n") + f.write("gds readonly true\n") + f.write("gds read {}\n".format(gds_name)) + f.write('puts "Finished reading gds {}"\n'.format(gds_name)) + f.write("load {}\n".format(self.name)) + f.write('puts "Finished loading cell {}"\n'.format(self.name)) + f.write("cellname delete \\(UNNAMED\\)\n") + f.write("lef write {} -hide\n".format(lef_name)) + f.write('puts "Finished writing LEF cell {}"\n'.format(self.name)) + f.close() + os.system("chmod u+x {}".format(run_file)) + from run_script import run_script + (outfile, errfile, resultsfile) = run_script(self.name, "lef") + def lef_write(self, lef_name): - """Write the entire lef of the object to the file.""" - debug.info(3, "Writing to {0}".format(lef_name)) + """ Write the entire lef of the object to the file. """ + + if OPTS.drc_exe[0] == "magic": + self.magic_lef_write(lef_name) + return + + debug.info(3, "Writing detailed LEF to {0}".format(lef_name)) self.indent = "" # To maintain the indent level easily diff --git a/compiler/router/router.py b/compiler/router/router.py index aa01c71f..5213af4a 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -1215,8 +1215,9 @@ class router(router_tech): return None - def get_pin(self, pin_name): + def get_ll_pin(self, pin_name): """ Return the lowest, leftest pin group """ + keep_pin = None for index,pg in enumerate(self.pin_groups[pin_name]): for pin in pg.enclosures: diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 753200b8..6dacdd90 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -248,21 +248,27 @@ class sram_base(design, verilog, lef): # Find the lowest leftest pin for vdd and gnd for pin_name in ["vdd", "gnd"]: - # Copy the pin shape to rectangles + # Copy the pin shape(s) to rectangles for pin in self.get_pins(pin_name): self.add_rect(pin.layer, pin.ll(), pin.width(), pin.height()) - # Remove the pins + + # Remove the pin shape(s) self.remove_layout_pin(pin_name) - pin = rtr.get_pin(pin_name) - + # Get the lowest, leftest pin + pin = rtr.get_ll_pin(pin_name) + + # Add it as an IO pin to the perimeter + lowest_coord = self.find_lowest_coords() + pin_width = pin.rx() - lowest_coord.x + pin_offset = vector(lowest_coord.x, pin.by()) self.add_layout_pin(pin_name, pin.layer, - pin.ll(), - pin.width(), + pin_offset, + pin_width, pin.height()) def route_escape_pins(self): From 3eed6bb8ff0fc2c6761064c63f9aadc23c8db4aa Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 14 Apr 2021 11:07:38 -0700 Subject: [PATCH 74/78] Check for None before checking DRC tool --- compiler/base/lef.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/lef.py b/compiler/base/lef.py index 8ca4918b..a5c1910a 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -68,7 +68,7 @@ class lef: def lef_write(self, lef_name): """ Write the entire lef of the object to the file. """ - if OPTS.drc_exe[0] == "magic": + if OPTS.drc_exe and OPTS.drc_exe[0] == "magic": self.magic_lef_write(lef_name) return From 41226087bac97962b590037c649fb6ae362ac0b6 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 14 Apr 2021 13:55:21 -0700 Subject: [PATCH 75/78] Use separate mXp pin layer if it exists --- compiler/base/pin_layout.py | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index eb4cb2ad..e8c6f0a5 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -369,11 +369,23 @@ class pin_layout: debug.info(4, "writing pin (" + str(self.layer) + "):" + str(self.width()) + "x" + str(self.height()) + " @ " + str(self.ll())) - (layer_num, purpose) = layer[self.layer] + + # Try to use the pin layer if it exists, otherwise + # use the regular layer try: - from tech import pin_purpose + (pin_layer_num, pin_purpose) = layer[self.layer + "p"] + except KeyError: + (pin_layer_num, pin_purpose) = layer[self.layer] + (layer_num, purpose) = layer[self.layer] + + # Try to use a global pin purpose if it exists, + # otherwise, use the regular purpose + try: + from tech import pin_purpose as global_pin_purpose + pin_purpose = global_pin_purpose except ImportError: - pin_purpose = purpose + pass + try: from tech import label_purpose except ImportError: @@ -385,9 +397,9 @@ class pin_layout: width=self.width(), height=self.height(), center=False) - # Draw a second pin shape too - if pin_purpose != purpose: - newLayout.addBox(layerNumber=layer_num, + # Draw a second pin shape too if it is different + if not self.same_lpp((pin_layer_num, pin_purpose), (layer_num, purpose)): + newLayout.addBox(layerNumber=pin_layer_num, purposeNumber=pin_purpose, offsetInMicrons=self.ll(), width=self.width(), From 1d657abebc82d5939d2c1be45e0c5704e5ca8c47 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Thu, 15 Apr 2021 22:33:57 +0200 Subject: [PATCH 76/78] Add VERBOSE parameter to generated verilog model This allows disabling the $display commands that are generated for every read and write access to the model. The verilog output has been tested with the following example script from compiler.base.verilog import verilog v = verilog() v.num_words = 256 v.word_size = 32 v.write_size = 8 v.name = "sky130_sram_1kbyte_1rw1r_32x256_8" v.all_ports = [0,1] v.readwrite_ports = [0] v.read_ports = [0,1] v.write_ports = [0] v.addr_size=8 v.verilog_write("mymodule.v") Signed-off-by: Olof Kindgren --- compiler/base/verilog.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 989d9d9c..00ca1610 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -61,6 +61,7 @@ class verilog: self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n") self.vf.write(" // FIXME: This delay is arbitrary.\n") self.vf.write(" parameter DELAY = 3 ;\n") + self.vf.write(" parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n") self.vf.write("\n") for port in self.all_ports: @@ -130,19 +131,19 @@ class verilog: if port in self.read_ports: self.vf.write(" dout{0} = {1}'bx;\n".format(port, self.word_size)) if port in self.readwrite_ports: - self.vf.write(" if ( !csb{0}_reg && web{0}_reg ) \n".format(port)) + self.vf.write(" if ( !csb{0}_reg && web{0}_reg && VERBOSE ) \n".format(port)) self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port)) elif port in self.read_ports: - self.vf.write(" if ( !csb{0}_reg ) \n".format(port)) + self.vf.write(" if ( !csb{0}_reg && VERBOSE ) \n".format(port)) self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port)) if port in self.readwrite_ports: - self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) + self.vf.write(" if ( !csb{0}_reg && !web{0}_reg && VERBOSE )\n".format(port)) if self.write_size: self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port)) else: self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b\",addr{0}_reg,din{0}_reg);\n".format(port)) elif port in self.write_ports: - self.vf.write(" if ( !csb{0}_reg )\n".format(port)) + self.vf.write(" if ( !csb{0}_reg && VERBOSE )\n".format(port)) if self.write_size: self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port)) else: From 688a1f1e6076305f706dac6756c2f844d90a8c66 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Thu, 15 Apr 2021 22:39:49 +0200 Subject: [PATCH 77/78] Add HOLD_DELAY parameter for dout in verilog model Signed-off-by: Olof Kindgren --- compiler/base/verilog.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 00ca1610..a1eab007 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -62,6 +62,7 @@ class verilog: self.vf.write(" // FIXME: This delay is arbitrary.\n") self.vf.write(" parameter DELAY = 3 ;\n") self.vf.write(" parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n") + self.vf.write(" parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n") self.vf.write("\n") for port in self.all_ports: @@ -129,7 +130,7 @@ class verilog: if port in self.write_ports: self.vf.write(" din{0}_reg = din{0};\n".format(port)) if port in self.read_ports: - self.vf.write(" dout{0} = {1}'bx;\n".format(port, self.word_size)) + self.vf.write(" #(T_HOLD) dout{0} = {1}'bx;\n".format(port, self.word_size)) if port in self.readwrite_ports: self.vf.write(" if ( !csb{0}_reg && web{0}_reg && VERBOSE ) \n".format(port)) self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port)) From 5b556e6ef575bf863a2260f10c41b5244c66e0c6 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 15 Apr 2021 15:48:20 -0700 Subject: [PATCH 78/78] Update unit test results with new Verilog models. --- compiler/tests/golden/sram_2_16_1_freepdk45.v | 8 +++++--- compiler/tests/golden/sram_2_16_1_scn4m_subm.v | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.v b/compiler/tests/golden/sram_2_16_1_freepdk45.v index 5edd2fee..46f89fa5 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.v +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.v @@ -12,6 +12,8 @@ module sram_2_16_1_freepdk45( parameter RAM_DEPTH = 1 << ADDR_WIDTH; // FIXME: This delay is arbitrary. parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary input clk0; // clock input csb0; // active low chip select @@ -33,10 +35,10 @@ module sram_2_16_1_freepdk45( web0_reg = web0; addr0_reg = addr0; din0_reg = din0; - dout0 = 2'bx; - if ( !csb0_reg && web0_reg ) + #(T_HOLD) dout0 = 2'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); - if ( !csb0_reg && !web0_reg ) + if ( !csb0_reg && !web0_reg && VERBOSE ) $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); end diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v index cec47c19..cb95036b 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v @@ -12,6 +12,8 @@ module sram_2_16_1_scn4m_subm( parameter RAM_DEPTH = 1 << ADDR_WIDTH; // FIXME: This delay is arbitrary. parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary input clk0; // clock input csb0; // active low chip select @@ -33,10 +35,10 @@ module sram_2_16_1_scn4m_subm( web0_reg = web0; addr0_reg = addr0; din0_reg = din0; - dout0 = 2'bx; - if ( !csb0_reg && web0_reg ) + #(T_HOLD) dout0 = 2'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); - if ( !csb0_reg && !web0_reg ) + if ( !csb0_reg && !web0_reg && VERBOSE ) $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); end