From 81ab1f1f82fc376b0c8297182737ddafd7c9713b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 17 Nov 2016 14:05:50 -0800 Subject: [PATCH 1/2] Change layer order for add_wire --- compiler/bank.py | 6 +++--- compiler/control_logic.py | 6 +++--- compiler/hierarchy_layout.py | 2 +- compiler/logic_effort_dc.py | 2 +- compiler/nor_2.py | 2 +- compiler/replica_bitline.py | 22 +++++++++++----------- compiler/sram.py | 4 ++-- compiler/wire.py | 2 +- 8 files changed, 23 insertions(+), 23 deletions(-) diff --git a/compiler/bank.py b/compiler/bank.py index 924d5ba9..8c60c9d9 100644 --- a/compiler/bank.py +++ b/compiler/bank.py @@ -913,7 +913,7 @@ class bank(design.design): mid2 = col_decoder_out_position + vector(connection_width, -self.central_line_y_offset) - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[col_decoder_out_position,mid1,mid2], offset=col_decoder_out_position) @@ -1150,7 +1150,7 @@ class bank(design.design): start = self.bank_select_inv_position + self.inv4x.A_position end = vector(self.left_vdd_x_offset, start.y + 3 * drc["minwidth_metal3"]) mid = vector(start.x, end.y) - self.add_wire(("metal1", "via1", "metal2"), [start, mid, end]) + self.add_wire(("metal2", "via1", "metal1"), [start, mid, end]) # save position self.bank_select_position = end - vector(0, 0.5 * drc["minwidth_metal2"]) @@ -1235,7 +1235,7 @@ class bank(design.design): correct_y = (2 * self.NOR2.A_position.y + drc["minwidth_metal1"] - self.m1m2_via.width) end = start + vector(0, correct_y) - self.add_wire(("metal2", "via2", "metal3"), [start, mid, end]) + self.add_wire(("metal3", "via2", "metal2"), [start, mid, end]) # Save position setattr(self,"{0}_position".format(self.control_signals[i]), diff --git a/compiler/control_logic.py b/compiler/control_logic.py index 635f7132..b7905e4b 100644 --- a/compiler/control_logic.py +++ b/compiler/control_logic.py @@ -457,7 +457,7 @@ class control_logic(design.design): rotate=90) # OE_bar [Bus # 1] to nor2 B input - layer_stack = ("metal2", "via1", "metal1") + layer_stack = ("metal3", "via1", "metal2") start = self.nor2_1_B_position mid1 = vector(self.nor2_1_B_position.x+ 2 * drc["minwidth_metal2"], start.y) @@ -497,7 +497,7 @@ class control_logic(design.design): rotate=90) # Replica bitline (rblk to replica bitline input) - layer_stack = ("metal2", "via1", "metal1") + layer_stack = ("metal1", "via1", "metal2") start = vector(self.rail_2_x_offsets[1] + 0.5 * drc["minwidth_metal2"], self.output_port_gap) mid1 = vector(start.x, 0.5 * drc["minwidth_metal1"]) @@ -605,7 +605,7 @@ class control_logic(design.design): self.clk_position = vector(0, clk_y) # clk port to inv1 A - layer_stack = ("metal2", "via1", "metal1") + layer_stack = ("metal1", "via1", "metal2") start = self.inv1_A_position + vector(0, 0.5 * drc["minwidth_metal1"]) mid1 = vector(self.inv1_A_position.x- 2 * drc["minwidth_metal2"], start.y) diff --git a/compiler/hierarchy_layout.py b/compiler/hierarchy_layout.py index 8b136b47..a9ea8aab 100644 --- a/compiler/hierarchy_layout.py +++ b/compiler/hierarchy_layout.py @@ -175,7 +175,7 @@ class layout: def add_wire(self, layers, coordinates, offset=None): """Connects a routing path on given layer,coordinates,width. - The layers are the (vertical, via, horizontal). """ + The layers are the (horizontal, via, vertical). """ import wire debug.info(3,"add wire " + str(layers) + " " + str(coordinates)) # Wires/paths are created so that the first point is (0,0) diff --git a/compiler/logic_effort_dc.py b/compiler/logic_effort_dc.py index 706623b2..8d0431e4 100644 --- a/compiler/logic_effort_dc.py +++ b/compiler/logic_effort_dc.py @@ -169,7 +169,7 @@ class logic_effort_dc(design.design): if start_inv < half_length and end_inv >= half_length: mid = [half_length * self.inv.width \ - 0.5 * drc["minwidth_metal2"], M2_start[1]] - self.add_wire(("metal3", "via2", "metal2"), + self.add_wire(("metal2", "via2", "metal3"), [M2_start, mid, M2_end]) else: self.add_path(("metal2"), [M2_start, M2_end]) diff --git a/compiler/nor_2.py b/compiler/nor_2.py index 6d7be2f9..b2de66fd 100644 --- a/compiler/nor_2.py +++ b/compiler/nor_2.py @@ -413,7 +413,7 @@ class nor_2(design.design): self.add_via(layers=("metal1", "via1", "metal2"), offset=offset) mid = [pmos_contact.x, self.Z_position.y] - self.add_wire(("metal2", "via1", "metal1"), + self.add_wire(("metal1", "via1", "metal2"), [self.Z_position, mid, pmos_contact]) def extend_wells(self): diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py index a032294c..6d562937 100644 --- a/compiler/replica_bitline.py +++ b/compiler/replica_bitline.py @@ -221,7 +221,7 @@ class replica_bitline(design.design): self.replica_bitline_offset.y - self.replica_bitcell.height - 0.5 * (self.m1m2_via.height + drc["metal1_to_metal1"]) - 2 * drc["metal1_to_metal1"]) - self.add_wire(layers=("metal1", "via1", "metal2"), + self.add_wire(layers=("metal2", "via1", "metal1"), coordinates=[BL_inv_in, mid1, mid2, mid3]) # need to fix the mid point as this is done with two wire @@ -233,7 +233,7 @@ class replica_bitline(design.design): height=drc["minwidth_metal1"]) mid4 = [BL_offset.x, mid3.y] - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[BL_offset, mid4, mid3]) def route_access_tx(self, delay_chain_output, BL_inv_in, vdd_offset): @@ -265,7 +265,7 @@ class replica_bitline(design.design): mid1 = vector(offset.x, self.delay_chain_offset.y - 3 * m2rail_space) mid2 = [delay_chain_output.x, mid1.y] # Note the inverted wire stack - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[offset, mid1, mid2, delay_chain_output]) self.add_via(layers=("metal1", "via1", "metal2"), offset=delay_chain_output, @@ -310,7 +310,7 @@ class replica_bitline(design.design): self.add_path("metal1", [drain_offset, close_Vdd_offset]) mid = [vdd_offset.x, close_Vdd_offset.y] - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[close_Vdd_offset, mid, vdd_offset]) def route_tx_source(self, BL_inv_in): @@ -337,7 +337,7 @@ class replica_bitline(design.design): end = [mid2.x, vdd_offset.y] self.add_path(layer=("metal1"), coordinates=[start, mid1, mid2]) - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[mid1, mid2, end]) def route_gnd(self): @@ -354,7 +354,7 @@ class replica_bitline(design.design): share_gnd = vector(self.gnd_position.x, mid2.y) # Note the inverted stacks lst = [BL_gnd_offset, mid1, mid2, share_gnd, self.gnd_position] - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=lst) self.add_label(text="gnd", layer="metal1", @@ -384,13 +384,13 @@ class replica_bitline(design.design): + self.bitline_load.WL_positions[i].scale(0,1)) mid = [self.delay_chain_offset.x + 6 * drc["minwidth_metal2"], gnd_offset.y] - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[gnd_offset, mid, WL_offset]) if i % 2 == 0: load_vdd_offset = (self.replica_bitline_offset + self.bitline_load.vdd_positions[i]) mid = [vdd_offset.x, load_vdd_offset.y] - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[vdd_offset, mid, load_vdd_offset]) def route_RC(self,vdd_offset): @@ -399,17 +399,17 @@ class replica_bitline(design.design): RC_vdd = self.replica_bitline_offset + vector(1,-1).scale(self.bitcell_chars["vdd"]) mid = [vdd_offset.x, RC_vdd.y] # Note the inverted stacks - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[vdd_offset, mid, RC_vdd]) gnd_offset = self.BL_inv_offset - vector(self.inv.width, 0) load_gnd = self.replica_bitline_offset + vector(self.bitcell_chars["gnd"][0], self.bitline_load.height) mid = [load_gnd.x, gnd_offset.y] - self.add_wire(layers=("metal2", "via1", "metal1"), + self.add_wire(layers=("metal1", "via1", "metal2"), coordinates=[gnd_offset, mid, load_gnd]) load_gnd = self.replica_bitline_offset + vector(0, self.bitline_load.height) mid = [load_gnd.x, gnd_offset.y] - self.add_wire(("metal2", "via1", "metal1"), [gnd_offset, mid, load_gnd]) + self.add_wire(("metal1", "via1", "metal2"), [gnd_offset, mid, load_gnd]) diff --git a/compiler/sram.py b/compiler/sram.py index 5826fed6..420ac873 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -803,7 +803,7 @@ class sram(design.design): start.y) end = vector(mid1.x, self.msf_msb_address_position.y + 4 * (i + 1) * drc["minwidth_metal2"]) - self.add_wire(("metal1", "via1", "metal2"), [start, mid1, end]) + self.add_wire(("metal2", "via1", "metal1"), [start, mid1, end]) x_off = self.vertical_line_positions[bank_select_line].x contact_pos = vector(x_off, @@ -831,7 +831,7 @@ class sram(design.design): + 3*drc["minwidth_metal3"], mid2.y) - layer_stack = ("metal1", "via1", "metal2") + layer_stack = ("metal2", "via1", "metal1") self.add_wire(layer_stack, [start, mid1, mid2, end]) self.add_rect(layer="metal1", diff --git a/compiler/wire.py b/compiler/wire.py index 51a2ae91..821dc3bd 100644 --- a/compiler/wire.py +++ b/compiler/wire.py @@ -37,7 +37,7 @@ class wire(path): # wires and paths should not be offset to (0,0) def setup_layers(self): - (vert_layer, via_layer, horiz_layer) = self.layer_stack + (horiz_layer, via_layer, vert_layer) = self.layer_stack if (via_layer != None): self.via_layer_name = via_layer else: From 19e7100f80b3c8ef840d7abccd05c02d13961f9d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 17 Nov 2016 16:04:01 -0800 Subject: [PATCH 2/2] Fix error in metal stack --- compiler/control_logic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/control_logic.py b/compiler/control_logic.py index b7905e4b..93430f34 100644 --- a/compiler/control_logic.py +++ b/compiler/control_logic.py @@ -457,7 +457,7 @@ class control_logic(design.design): rotate=90) # OE_bar [Bus # 1] to nor2 B input - layer_stack = ("metal3", "via1", "metal2") + layer_stack = ("metal1", "via1", "metal2") start = self.nor2_1_B_position mid1 = vector(self.nor2_1_B_position.x+ 2 * drc["minwidth_metal2"], start.y)