From 5b556e6ef575bf863a2260f10c41b5244c66e0c6 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 15 Apr 2021 15:48:20 -0700 Subject: [PATCH] Update unit test results with new Verilog models. --- compiler/tests/golden/sram_2_16_1_freepdk45.v | 8 +++++--- compiler/tests/golden/sram_2_16_1_scn4m_subm.v | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.v b/compiler/tests/golden/sram_2_16_1_freepdk45.v index 5edd2fee..46f89fa5 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.v +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.v @@ -12,6 +12,8 @@ module sram_2_16_1_freepdk45( parameter RAM_DEPTH = 1 << ADDR_WIDTH; // FIXME: This delay is arbitrary. parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary input clk0; // clock input csb0; // active low chip select @@ -33,10 +35,10 @@ module sram_2_16_1_freepdk45( web0_reg = web0; addr0_reg = addr0; din0_reg = din0; - dout0 = 2'bx; - if ( !csb0_reg && web0_reg ) + #(T_HOLD) dout0 = 2'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); - if ( !csb0_reg && !web0_reg ) + if ( !csb0_reg && !web0_reg && VERBOSE ) $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); end diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v index cec47c19..cb95036b 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v @@ -12,6 +12,8 @@ module sram_2_16_1_scn4m_subm( parameter RAM_DEPTH = 1 << ADDR_WIDTH; // FIXME: This delay is arbitrary. parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary input clk0; // clock input csb0; // active low chip select @@ -33,10 +35,10 @@ module sram_2_16_1_scn4m_subm( web0_reg = web0; addr0_reg = addr0; din0_reg = din0; - dout0 = 2'bx; - if ( !csb0_reg && web0_reg ) + #(T_HOLD) dout0 = 2'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); - if ( !csb0_reg && !web0_reg ) + if ( !csb0_reg && !web0_reg && VERBOSE ) $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); end