diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 3e105d09..18ced346 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -289,13 +289,14 @@ class bank(design.design):
         """  Computes the required sizes to create the bank """
 
         self.num_cols = int(self.words_per_row*self.word_size)
-        self.num_rows = int(self.num_words / self.words_per_row)
+        self.num_rows_temp = int(self.num_words / self.words_per_row)
+        self.num_rows = self.num_rows_temp + self.num_spare_rows
 
-        self.row_addr_size = int(log(self.num_rows, 2))
+        self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
         self.addr_size = self.col_addr_size + self.row_addr_size
 
-        debug.check(self.num_rows*self.num_cols==self.word_size*self.num_words,"Invalid bank sizes.")
+        debug.check(self.num_rows_temp*self.num_cols==self.word_size*self.num_words,"Invalid bank sizes.")
         debug.check(self.addr_size==self.col_addr_size + self.row_addr_size,"Invalid address break down.")
 
         # The order of the control signals on the control bus:
diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py
index 0a624c60..11035f30 100644
--- a/compiler/modules/port_address.py
+++ b/compiler/modules/port_address.py
@@ -5,7 +5,7 @@
 #
 import sys
 from tech import drc, parameter
-from math import log
+from math import log, ceil
 import debug
 import design
 from sram_factory import factory
@@ -22,7 +22,7 @@ class port_address(design.design):
         
         self.num_cols = cols
         self.num_rows = rows
-        self.addr_size = int(log(self.num_rows, 2))
+        self.addr_size = ceil(log(self.num_rows, 2))
         
         if name == "":
             name = "port_address_{0}_{1}".format(cols,rows)
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index 639d0714..0f922eb0 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -264,8 +264,9 @@ class replica_bitcell_array(design.design):
 
         # Far top dummy row (first row above array is NOT flipped)
         flip_dummy = self.right_rbl%2
-        self.dummy_row_top_inst.place(offset=offset.scale(0,self.right_rbl+flip_dummy)+self.bitcell_array_inst.ul(),
-                                         mirror="MX" if flip_dummy else "R0")
+        odd_rows = self.row_size%2
+        self.dummy_row_top_inst.place(offset=offset.scale(0,self.right_rbl+(flip_dummy ^ odd_rows))+self.bitcell_array_inst.ul(),
+                                         mirror="MX" if (flip_dummy ^ odd_rows) else "R0")
         # Far bottom dummy row (first row below array IS flipped)
         flip_dummy = (self.left_rbl+1)%2
         self.dummy_row_bot_inst.place(offset=offset.scale(0,-self.left_rbl-1+flip_dummy),
@@ -280,8 +281,8 @@ class replica_bitcell_array(design.design):
             self.dummy_row_replica_inst[bit].place(offset=offset.scale(0,-bit-bit%2),
                                                    mirror="R0" if bit%2 else "MX")
         for bit in range(self.right_rbl):
-            self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2)+self.bitcell_array_inst.ul(),
-                                                                 mirror="MX" if bit%2 else "R0")
+            self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2+odd_rows)+self.bitcell_array_inst.ul(),
+                                                                 mirror="MX" if (bit%2 or odd_rows) else "R0")
             
 
         self.translate_all(offset.scale(-1-self.left_rbl,-1-self.left_rbl))
diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py
index 376bf42b..265cdba8 100644
--- a/compiler/sram/sram_config.py
+++ b/compiler/sram/sram_config.py
@@ -14,11 +14,12 @@ from sram_factory import factory
 class sram_config:
     """ This is a structure that is used to hold the SRAM configuration options. """
     
-    def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None):
+    def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None, num_spare_rows=0):
         self.word_size = word_size
         self.num_words = num_words
         self.write_size = write_size
         self.num_banks = num_banks
+        self.num_spare_rows = num_spare_rows
 
         # This will get over-written when we determine the organization
         self.words_per_row = words_per_row
@@ -78,11 +79,12 @@ class sram_config:
         
         # Fix the number of columns and rows
         self.num_cols = int(self.words_per_row*self.word_size)
-        self.num_rows = int(self.num_words_per_bank/self.words_per_row)
+        self.num_rows_temp = int(self.num_words_per_bank/self.words_per_row)
+        self.num_rows = self.num_rows_temp + self.num_spare_rows
         debug.info(1,"Rows: {} Cols: {}".format(self.num_rows,self.num_cols))
 
         # Compute the address and bank sizes
-        self.row_addr_size = int(log(self.num_rows, 2))
+        self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
         self.bank_addr_size = self.col_addr_size + self.row_addr_size
         self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))