From 5b0f97860a738fe5a8012b82c39d5c085c334b2e Mon Sep 17 00:00:00 2001 From: Eren Dogan Date: Wed, 2 Aug 2023 09:30:50 -0700 Subject: [PATCH] Calculate bbox inside the router --- compiler/modules/rom_bank.py | 20 +++++--------------- compiler/modules/sram_1bank.py | 22 +++++----------------- compiler/router/router.py | 8 +++----- compiler/router/signal_escape_router.py | 4 ++-- compiler/router/supply_router.py | 6 +++--- 5 files changed, 18 insertions(+), 42 deletions(-) diff --git a/compiler/modules/rom_bank.py b/compiler/modules/rom_bank.py index 86a2215a..aa790d6f 100644 --- a/compiler/modules/rom_bank.py +++ b/compiler/modules/rom_bank.py @@ -111,20 +111,12 @@ class rom_bank(design,rom_verilog): self.place_top_level_pins() self.route_output_buffers() - rt = router_tech(self.supply_stack, 1) - init_bbox = self.get_bbox(side="ring", - margin=rt.track_width) - # We need the initial bbox for the supply rings later - # because the perimeter pins will change the bbox + self.route_supplies() # Route the pins to the perimeter if OPTS.perimeter_pins: # We now route the escape routes far enough out so that they will # reach past the power ring or stripes on the sides - bbox = self.get_bbox(side="ring", - margin=11*rt.track_width) - self.route_escape_pins(bbox) - - self.route_supplies(init_bbox) + self.route_escape_pins() def setup_layout_constants(self): @@ -449,7 +441,7 @@ class rom_bank(design,rom_verilog): pin_num = msb - self.col_bits self.add_io_pin(self.decode_inst, "A{}".format(pin_num), name) - def route_supplies(self, bbox=None): + def route_supplies(self): for pin_name in ["vdd", "gnd"]: for inst in self.insts: @@ -462,7 +454,6 @@ class rom_bank(design,rom_verilog): from openram.router import supply_router as router rtr = router(layers=self.supply_stack, design=self, - bbox=bbox, pin_type=OPTS.supply_pin_type) rtr.route() @@ -488,7 +479,7 @@ class rom_bank(design,rom_verilog): pin.width(), pin.height()) - def route_escape_pins(self, bbox): + def route_escape_pins(self): pins_to_route = [] for bit in range(self.col_bits): @@ -504,6 +495,5 @@ class rom_bank(design,rom_verilog): pins_to_route.append("cs") from openram.router import signal_escape_router as router rtr = router(layers=self.m3_stack, - design=self, - bbox=bbox) + design=self) rtr.route(pins_to_route) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index a230936f..95ea9b87 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -243,7 +243,7 @@ class sram_1bank(design, verilog, lef): def create_modules(self): debug.error("Must override pure virtual function.", -1) - def route_supplies(self, bbox=None): + def route_supplies(self): """ Route the supply grid and connect the pins to them. """ # Copy the pins to the top level @@ -259,7 +259,6 @@ class sram_1bank(design, verilog, lef): from openram.router import supply_router as router rtr = router(layers=self.supply_stack, design=self, - bbox=bbox, pin_type=OPTS.supply_pin_type) rtr.route() @@ -323,7 +322,7 @@ class sram_1bank(design, verilog, lef): # Grid is left with many top level pins pass - def route_escape_pins(self, bbox): + def route_escape_pins(self): """ Add the top-level pins for a single bank SRAM with control. """ @@ -368,8 +367,7 @@ class sram_1bank(design, verilog, lef): from openram.router import signal_escape_router as router rtr = router(layers=self.m3_stack, - design=self, - bbox=bbox) + design=self) rtr.route(pins_to_route) def compute_bus_sizes(self): @@ -1075,23 +1073,13 @@ class sram_1bank(design, verilog, lef): self.add_dnwell(inflate=2.5) # Route the supplies together and/or to the ring/stripes. - # This is done with the original bbox since the escape routes need to - # be outside of the ring for OpenLane - rt = router_tech(self.supply_stack, 1) - init_bbox = self.get_bbox(side="ring", - margin=rt.track_width) - - # We need the initial bbox for the supply rings later - # because the perimeter pins will change the bbox # Route the pins to the perimeter if OPTS.perimeter_pins: # We now route the escape routes far enough out so that they will # reach past the power ring or stripes on the sides - bbox = self.get_bbox(side="ring", - margin=11*rt.track_width) - self.route_escape_pins(bbox) + self.route_escape_pins() - self.route_supplies(init_bbox) + self.route_supplies() def route_dffs(self, add_routes=True): diff --git a/compiler/router/router.py b/compiler/router/router.py index a6c02620..acf1a00c 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -20,7 +20,7 @@ class router(router_tech): This is the base class for routers that use the Hanan grid graph method. """ - def __init__(self, layers, design, bbox=None): + def __init__(self, layers, design): # `router_tech` contains tech constants for the router router_tech.__init__(self, layers, route_track_width=1) @@ -31,10 +31,8 @@ class router(router_tech): self.design = design # Temporary GDSII file name to find pins and blockages self.gds_filename = OPTS.openram_temp + "temp.gds" - # Bounding box can be given with margin, or created by default - if bbox is None: - bbox = self.design.get_bbox() - self.bbox = bbox + # Calculate the bounding box for routing around the perimeter + self.bbox = self.design.get_bbox(margin=11 * self.track_width) # Dictionary for vdd and gnd pins self.pins = {} # Set of all the pins diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py index d0bd99ca..8e6479cb 100644 --- a/compiler/router/signal_escape_router.py +++ b/compiler/router/signal_escape_router.py @@ -16,10 +16,10 @@ class signal_escape_router(router): This is the signal escape router that uses the Hanan grid graph method. """ - def __init__(self, layers, design, bbox=None, pin_type=None): + def __init__(self, layers, design): # `router_tech` contains tech constants for the router - router.__init__(self, layers, design, bbox) + router.__init__(self, layers, design) # New pins are the side supply pins self.new_pins = {} diff --git a/compiler/router/supply_router.py b/compiler/router/supply_router.py index 06f8fbb8..aa774731 100644 --- a/compiler/router/supply_router.py +++ b/compiler/router/supply_router.py @@ -16,10 +16,10 @@ class supply_router(router): This is the supply router that uses the Hanan grid graph method. """ - def __init__(self, layers, design, bbox=None, pin_type=None): + def __init__(self, layers, design, pin_type=None): # `router_tech` contains tech constants for the router - router.__init__(self, layers, design, bbox) + router.__init__(self, layers, design) # Side supply pin type # (can be "top", "bottom", "right", "left", and "ring") @@ -106,7 +106,7 @@ class supply_router(router): def calculate_ring_bbox(self, num_vias=3): """ Calculate the ring-safe bounding box of the layout. """ - ll, ur = self.design.get_bbox() + ll, ur = self.bbox # Calculate the "wideness" of a side supply pin wideness = self.track_wire * num_vias + self.track_space * (num_vias - 1) # Total wideness is used to find it any pin overlaps in this region. If