From 82abd327852b8be2bd6674c79e58d49a731cd279 Mon Sep 17 00:00:00 2001 From: Jennifer Sowash Date: Mon, 12 Nov 2018 09:53:21 -0800 Subject: [PATCH 01/22] Added pbuf.py to create a single buffer. --- compiler/pgates/pbuf.py | 131 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 compiler/pgates/pbuf.py diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py new file mode 100644 index 00000000..21cc7a70 --- /dev/null +++ b/compiler/pgates/pbuf.py @@ -0,0 +1,131 @@ +import debug +import design +from tech import drc +from math import log +from vector import vector +from globals import OPTS +from pinv import pinv + +class pbuf(design.design): + """ + This is a simple buffer used for driving loads. + """ + from importlib import reload + c = reload(__import__(OPTS.bitcell)) + bitcell = getattr(c, OPTS.bitcell) + + unique_id = 1 + + def __init__(self, driver_size=4, height=bitcell.height, name=""): + + stage_effort = 4 + # FIXME: Change the number of stages to support high drives. + + if name=="": + name = "pbuf_{0}_{1}".format(driver_size, pbuf.unique_id) + pbuf.unique_id += 1 + + design.design.__init__(self, name) + debug.info(1, "Creating {}".format(self.name)) + + + # Shield the cap, but have at least a stage effort of 4 + input_size = max(1,int(driver_size/stage_effort)) + self.inv = pinv(size=input_size, height=height) # 1 + self.add_mod(self.inv) + + self.inv1 = pinv(size=driver_size, height=height) # 2 + self.add_mod(self.inv1) + + self.width = 2*self.inv1.width + self.inv2.width + self.height = 2*self.inv1.height + + self.create_layout() + + self.offset_all_coordinates() + + self.DRC_LVS() + + def create_layout(self): + self.add_pins() + self.add_insts() + self.add_wires() + self.add_layout_pins() + + def add_pins(self): + self.add_pin("A") + self.add_pin("Z") + self.add_pin("vdd") + self.add_pin("gnd") + + def add_insts(self): + # Add INV1 to the right + self.inv1_inst=self.add_inst(name="buf_inv1", + mod=self.inv, + offset=vector(0,0)) + self.connect_inst(["A", "zb_int", "vdd", "gnd"]) + + + # Add INV2 to the right + self.inv2_inst=self.add_inst(name="buf_inv2", + mod=self.inv1, + offset=vector(self.inv1_inst.rx(),0)) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + + def add_wires(self): + # inv1 Z to inv2 A + z1_pin = self.inv1_inst.get_pin("Z") + a2_pin = self.inv2_inst.get_pin("A") + mid_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()]) + + + def add_layout_pins(self): + # Continous vdd rail along with label. + vdd_pin=self.inv1_inst.get_pin("vdd") + self.add_layout_pin(text="vdd", + layer="metal1", + offset=vdd_pin.ll().scale(0,1), + width=self.width, + height=vdd_pin.height()) + + # Continous vdd rail along with label. + gnd_pin=self.inv4_inst.get_pin("gnd") + self.add_layout_pin(text="gnd", + layer="metal1", + offset=gnd_pin.ll().scale(0,1), + width=self.width, + height=gnd_pin.height()) + + # Continous gnd rail along with label. + gnd_pin=self.inv1_inst.get_pin("gnd") + self.add_layout_pin(text="gnd", + layer="metal1", + offset=gnd_pin.ll().scale(0,1), + width=self.width, + height=vdd_pin.height()) + + z_pin = self.inv4_inst.get_pin("Z") + self.add_layout_pin_rect_center(text="Z", + layer="metal2", + offset=z_pin.center()) + self.add_via_center(layers=("metal1","via1","metal2"), + offset=z_pin.center()) + + a_pin = self.inv1_inst.get_pin("A") + self.add_layout_pin_rect_center(text="A", + layer="metal2", + offset=a_pin.center()) + self.add_via_center(layers=("metal1","via1","metal2"), + offset=a_pin.center()) + + + + def analytical_delay(self, slew, load=0.0): + """ Calculate the analytical delay of DFF-> INV -> INV """ + inv1_delay = self.inv1.analytical_delay(slew=slew, load=self.inv2.input_load()) + inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load) + return inv1_delay + inv2_delay + + \ No newline at end of file From b6f1409fb9ea870fde209fa0af7612a6152a9d05 Mon Sep 17 00:00:00 2001 From: Jennifer Sowash Date: Mon, 12 Nov 2018 13:24:27 -0800 Subject: [PATCH 02/22] Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. --- compiler/pgates/pbuf.py | 16 ++++++++-------- compiler/tests/04_pbuf_test.py | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 8 deletions(-) create mode 100644 compiler/tests/04_pbuf_test.py diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 21cc7a70..28a15868 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -31,18 +31,18 @@ class pbuf(design.design): # Shield the cap, but have at least a stage effort of 4 input_size = max(1,int(driver_size/stage_effort)) - self.inv = pinv(size=input_size, height=height) # 1 + self.inv1 = pinv(size=input_size, height=height) # 1 self.add_mod(self.inv) - self.inv1 = pinv(size=driver_size, height=height) # 2 + self.inv2 = pinv(size=driver_size, height=height) # 2 self.add_mod(self.inv1) - self.width = 2*self.inv1.width + self.inv2.width - self.height = 2*self.inv1.height + self.width = self.inv1.width + self.inv2.width + self.height = self.inv1.height self.create_layout() - self.offset_all_coordinates() + #self.offset_all_coordinates() self.DRC_LVS() @@ -61,14 +61,14 @@ class pbuf(design.design): def add_insts(self): # Add INV1 to the right self.inv1_inst=self.add_inst(name="buf_inv1", - mod=self.inv, + mod=self.inv1, offset=vector(0,0)) self.connect_inst(["A", "zb_int", "vdd", "gnd"]) # Add INV2 to the right self.inv2_inst=self.add_inst(name="buf_inv2", - mod=self.inv1, + mod=self.inv2, offset=vector(self.inv1_inst.rx(),0)) self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) @@ -106,7 +106,7 @@ class pbuf(design.design): width=self.width, height=vdd_pin.height()) - z_pin = self.inv4_inst.get_pin("Z") + z_pin = self.inv2_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", layer="metal2", offset=z_pin.center()) diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py new file mode 100644 index 00000000..8549f262 --- /dev/null +++ b/compiler/tests/04_pbuf_test.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +""" +Run a regression test on a 2-row buffer cell +""" + +import unittest +from testutils import header,openram_test +import sys,os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +class pinvbuf_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + global verify + import verify + + import pinv + + debug.info(2, "Testing inverter/buffer 4x 8x") + a = pbuf.pbuf(8) + self.local_check(a) + + globals.end_openram() + +# instantiate a copdsay of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() From bb7773ca7fe9db9ba7c67a82d57b9b0ce452327b Mon Sep 17 00:00:00 2001 From: Jennifer Eve Sowash Date: Tue, 20 Nov 2018 14:39:11 -0800 Subject: [PATCH 03/22] Editted pbuf.py to pass regression. --- compiler/pgates/pbuf.py | 14 +++----------- compiler/tests/04_pbuf_test.py | 4 ++-- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 28a15868..0d30a89b 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -32,10 +32,10 @@ class pbuf(design.design): # Shield the cap, but have at least a stage effort of 4 input_size = max(1,int(driver_size/stage_effort)) self.inv1 = pinv(size=input_size, height=height) # 1 - self.add_mod(self.inv) + self.add_mod(self.inv1) self.inv2 = pinv(size=driver_size, height=height) # 2 - self.add_mod(self.inv1) + self.add_mod(self.inv2) self.width = self.inv1.width + self.inv2.width self.height = self.inv1.height @@ -89,14 +89,6 @@ class pbuf(design.design): offset=vdd_pin.ll().scale(0,1), width=self.width, height=vdd_pin.height()) - - # Continous vdd rail along with label. - gnd_pin=self.inv4_inst.get_pin("gnd") - self.add_layout_pin(text="gnd", - layer="metal1", - offset=gnd_pin.ll().scale(0,1), - width=self.width, - height=gnd_pin.height()) # Continous gnd rail along with label. gnd_pin=self.inv1_inst.get_pin("gnd") @@ -128,4 +120,4 @@ class pbuf(design.design): inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load) return inv1_delay + inv2_delay - \ No newline at end of file + diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 8549f262..f784c671 100644 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -11,14 +11,14 @@ import globals from globals import OPTS import debug -class pinvbuf_test(openram_test): +class pbuf_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) global verify import verify - import pinv + import pbuf debug.info(2, "Testing inverter/buffer 4x 8x") a = pbuf.pbuf(8) From d6bcba432630220e558507a65df749eaba887132 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:12:14 -0800 Subject: [PATCH 04/22] Add first attempt at code coverage. --- .coveragerc | 6 ++++++ .gitlab-ci.yml | 21 +++++++++++++++++++-- README.md | 12 +++++++++--- 3 files changed, 34 insertions(+), 5 deletions(-) create mode 100644 .coveragerc diff --git a/.coveragerc b/.coveragerc new file mode 100644 index 00000000..9b08c31b --- /dev/null +++ b/.coveragerc @@ -0,0 +1,6 @@ +[run] +omit = + # omit anything in a .local directory anywhere + */.local/* + # omit everything in /usr + /usr/* diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 96e30d2d..b1f0a569 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,6 +1,23 @@ +stages: + - test + - analyze + freepdk45: - script: "/home/gitlab-runner/regress_freepdk45.sh" + stage: test + script: + - /home/gitlab-runner/regress_freepdk45.sh scn4m_subm: - script: "/home/gitlab-runner/regress_scn4m_subm.sh" + stage: test + script: + - /home/gitlab-runner/regress_scn4m_subm.sh +analyze: + stage: analyze + script: + - coverage report -m + artifacts: + paths: + - public + expire_in: 30 days + coverage: '/TOTAL.+ ([0-9]{1,3}%)/' diff --git a/README.md b/README.md index 91e00bbd..75f8cf75 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,15 @@ # OpenRAM -Master: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) -Dev: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) -[![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) + [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) +Master: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) +[![coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?job=coverage)] +[![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) + +Dev: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) +[![coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?job=coverage)] +[![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) + An open-source static random access memory (SRAM) compiler. # What is OpenRAM? From b5d9a0e5eedb6e12624d8397c331c6ce8d80744b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:19:36 -0800 Subject: [PATCH 05/22] Do only coverage with scn4m_subm --- .gitlab-ci.yml | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b1f0a569..b51e7a29 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,23 +1,10 @@ -stages: - - test - - analyze - freepdk45: - stage: test script: - /home/gitlab-runner/regress_freepdk45.sh scn4m_subm: - stage: test script: - /home/gitlab-runner/regress_scn4m_subm.sh - -analyze: - stage: analyze - script: - coverage report -m - artifacts: - paths: - - public - expire_in: 30 days coverage: '/TOTAL.+ ([0-9]{1,3}%)/' + From 0bb612d9e409228f01fc71ad51e0bf9945705e6a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:20:55 -0800 Subject: [PATCH 06/22] Remove tabs in yml file --- .gitlab-ci.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b51e7a29..a881301c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,10 +1,10 @@ freepdk45: script: - - /home/gitlab-runner/regress_freepdk45.sh + - /home/gitlab-runner/regress_freepdk45.sh scn4m_subm: script: - - /home/gitlab-runner/regress_scn4m_subm.sh - - coverage report -m + - /home/gitlab-runner/regress_scn4m_subm.sh + - coverage report -m coverage: '/TOTAL.+ ([0-9]{1,3}%)/' From 8fde15a7e37b8c96d8a17dc516d0159716205619 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:25:00 -0800 Subject: [PATCH 07/22] Add coverage artifact --- .gitlab-ci.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a881301c..b2c989f3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -7,4 +7,8 @@ scn4m_subm: - /home/gitlab-runner/regress_scn4m_subm.sh - coverage report -m coverage: '/TOTAL.+ ([0-9]{1,3}%)/' + artifacts: + paths: + - .coverage + expire_in: 1 week From 770e824c4978508541c827b587fa74d8031a40af Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:37:09 -0800 Subject: [PATCH 08/22] Add entire wqscript to yml file --- .gitlab-ci.yml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b2c989f3..bb5f178e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,10 +1,14 @@ +before_script: + - export OPENRAM_HOME="$(pwd)/compiler" + - export OPENRAM_TECH="$(pwd)/technology" + freepdk45: script: - - /home/gitlab-runner/regress_freepdk45.sh + - $OPENRAM_HOME/tests/regress.py -t freepdk45 scn4m_subm: script: - - /home/gitlab-runner/regress_scn4m_subm.sh + - $OPENRAM_HOME/tests/regress.py -t scn4m_subm - coverage report -m coverage: '/TOTAL.+ ([0-9]{1,3}%)/' artifacts: From 5eedce7dc36234976c0574f84d3857fff54a8253 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:39:53 -0800 Subject: [PATCH 09/22] Change pwd to backticks --- .gitlab-ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index bb5f178e..5fb43e92 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,6 +1,6 @@ before_script: - - export OPENRAM_HOME="$(pwd)/compiler" - - export OPENRAM_TECH="$(pwd)/technology" + - export OPENRAM_HOME="`pwd`/compiler" + - export OPENRAM_TECH="`pwd`/technology" freepdk45: script: From 043e468818482f1f1bf725641cc956e8cf05aaa6 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:41:05 -0800 Subject: [PATCH 10/22] Forgot coverge run statement --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 5fb43e92..91b7f73c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -8,7 +8,7 @@ freepdk45: scn4m_subm: script: - - $OPENRAM_HOME/tests/regress.py -t scn4m_subm + - coverage run $OPENRAM_HOME/tests/regress.py -t scn4m_subm - coverage report -m coverage: '/TOTAL.+ ([0-9]{1,3}%)/' artifacts: From 05ee7745c67ebb7ea01fcb587d6db173e74970d1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:42:46 -0800 Subject: [PATCH 11/22] Source tool setup before script --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 91b7f73c..1f87c2b4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,4 +1,5 @@ before_script: + - . /home/gitlab-runner/setup-paths.sh - export OPENRAM_HOME="`pwd`/compiler" - export OPENRAM_TECH="`pwd`/technology" From 0c045815d24fc1352cc1a463c1a1a4ba9ab5b02c Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:51:17 -0800 Subject: [PATCH 12/22] Add python badge --- README.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 75f8cf75..f2ea440d 100644 --- a/README.md +++ b/README.md @@ -1,13 +1,14 @@ # OpenRAM +[![Python 3.5](https://img.shields.io/badge/Python-3.5-green.svg)(https://www.python.org/) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) -Master: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) -[![coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?job=coverage)] +Master: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) +[![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)] [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) -Dev: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) -[![coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?job=coverage)] +Dev: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) +[![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)] [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) An open-source static random access memory (SRAM) compiler. From a4a97ceb27cf606b750b3a2f7dd8810858330646 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 15:52:46 -0800 Subject: [PATCH 13/22] Missing bracket --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index f2ea440d..bb68c004 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # OpenRAM -[![Python 3.5](https://img.shields.io/badge/Python-3.5-green.svg)(https://www.python.org/) +[![Python 3.5](https://img.shields.io/badge/Python-3.5-green.svg)](https://www.python.org/) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) Master: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) From 1659f66070446ac88cbd6603563e10be8a4362b2 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 16:02:11 -0800 Subject: [PATCH 14/22] Add local badges --- README.md | 8 ++++---- images/Python-3.5-green.svg | 1 + images/download-stable-blue.svg | 1 + images/download-unstable-blue.svg | 1 + images/download.svg | 2 -- 5 files changed, 7 insertions(+), 6 deletions(-) create mode 100644 images/Python-3.5-green.svg create mode 100644 images/download-stable-blue.svg create mode 100644 images/download-unstable-blue.svg delete mode 100644 images/download.svg diff --git a/README.md b/README.md index bb68c004..b9d794ab 100644 --- a/README.md +++ b/README.md @@ -4,12 +4,12 @@ [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) Master: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) -[![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)] -[![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) +![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV) +[![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) Dev: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) -[![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)] -[![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) +![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV) +[![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) An open-source static random access memory (SRAM) compiler. diff --git a/images/Python-3.5-green.svg b/images/Python-3.5-green.svg new file mode 100644 index 00000000..5856e0ee --- /dev/null +++ b/images/Python-3.5-green.svg @@ -0,0 +1 @@ + PythonPython3.53.5 \ No newline at end of file diff --git a/images/download-stable-blue.svg b/images/download-stable-blue.svg new file mode 100644 index 00000000..2fbc3649 --- /dev/null +++ b/images/download-stable-blue.svg @@ -0,0 +1 @@ + downloaddownloadstablestable \ No newline at end of file diff --git a/images/download-unstable-blue.svg b/images/download-unstable-blue.svg new file mode 100644 index 00000000..a233df6b --- /dev/null +++ b/images/download-unstable-blue.svg @@ -0,0 +1 @@ + downloaddownloadunstableunstable \ No newline at end of file diff --git a/images/download.svg b/images/download.svg deleted file mode 100644 index 95d978ed..00000000 --- a/images/download.svg +++ /dev/null @@ -1,2 +0,0 @@ - -download download latestlatest From f1022d0cb0fdd11dd8337c73377577b9fc490def Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 16:49:03 -0800 Subject: [PATCH 15/22] Multiple stages to gitlab-ci. Combine coverage artifacts to generate html coverage. --- .gitlab-ci.yml | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 1f87c2b4..f6b9ea83 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -3,17 +3,36 @@ before_script: - export OPENRAM_HOME="`pwd`/compiler" - export OPENRAM_TECH="`pwd`/technology" +stages: + - test + - coverage + freepdk45: + stage: test script: - - $OPENRAM_HOME/tests/regress.py -t freepdk45 - -scn4m_subm: - script: - - coverage run $OPENRAM_HOME/tests/regress.py -t scn4m_subm - - coverage report -m - coverage: '/TOTAL.+ ([0-9]{1,3}%)/' + - coverage run -p $OPENRAM_HOME/tests/regress.py -t freepdk45 artifacts: paths: - - .coverage + - .coverage* expire_in: 1 week +scn4m_subm: + stage: test + script: + - coverage run -p $OPENRAM_HOME/tests/regress.py -t scn4m_subm + artifacts: + paths: + - .coverage* + expire_in: 1 week + +coverage: + stage: coverage + script: + - coverage combine + - coverage html -d coverage_html + artifacts: + paths: + - coverage_html + expire_in: 1 week + coverage: '/TOTAL.+ ([0-9]{1,3}%)/' + From 9a24ce8bc926f876ca48257e0fdbfa25a841273a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 17:39:37 -0800 Subject: [PATCH 16/22] Add gitlab paths to combine different source locations --- .coveragerc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/.coveragerc b/.coveragerc index 9b08c31b..04832373 100644 --- a/.coveragerc +++ b/.coveragerc @@ -4,3 +4,12 @@ omit = */.local/* # omit everything in /usr /usr/* +[paths] +source = + /home/gitlab-runner/builds/2fd64746/0 + /home/gitlab-runner/builds/2fd64746/1 + /home/gitlab-runner/builds/2fd64746/2 + /home/gitlab-runner/builds/2fd64746/3 + /home/gitlab-runner/builds/2fd64746/4 + /home/gitlab-runner/builds/2fd64746/5 + \ No newline at end of file From d34583093e8249df7a4e9724222a3b7806b26181 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 17:41:31 -0800 Subject: [PATCH 17/22] Add coverage job to badges --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index b9d794ab..7bbef133 100644 --- a/README.md +++ b/README.md @@ -4,11 +4,11 @@ [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) Master: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV) +![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?job=coverage?private_token=ynB6rSFLzvKUseoBPcwV) [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) Dev: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV) +![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?job=coverage?private_token=ynB6rSFLzvKUseoBPcwV) [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) An open-source static random access memory (SRAM) compiler. From 20a65fe7b211670aa015b254aa6e192574300f78 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 17:47:18 -0800 Subject: [PATCH 18/22] Add source path with env variables --- .coveragerc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/.coveragerc b/.coveragerc index 04832373..dd2f0de5 100644 --- a/.coveragerc +++ b/.coveragerc @@ -6,10 +6,6 @@ omit = /usr/* [paths] source = - /home/gitlab-runner/builds/2fd64746/0 - /home/gitlab-runner/builds/2fd64746/1 - /home/gitlab-runner/builds/2fd64746/2 - /home/gitlab-runner/builds/2fd64746/3 - /home/gitlab-runner/builds/2fd64746/4 - /home/gitlab-runner/builds/2fd64746/5 - \ No newline at end of file + $OPENRAM_HOME + $OPENRAM_TECH + From e242d18dcb75cb468c95144669bf81ae55843e83 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 18:17:36 -0800 Subject: [PATCH 19/22] Specify period in artifact filename --- .gitlab-ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f6b9ea83..2105a092 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -13,7 +13,7 @@ freepdk45: - coverage run -p $OPENRAM_HOME/tests/regress.py -t freepdk45 artifacts: paths: - - .coverage* + - .coverage.* expire_in: 1 week scn4m_subm: @@ -22,7 +22,7 @@ scn4m_subm: - coverage run -p $OPENRAM_HOME/tests/regress.py -t scn4m_subm artifacts: paths: - - .coverage* + - .coverage.* expire_in: 1 week coverage: From c9f2b0e45544d2c7fe1d9a7039a256683a2d76a7 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 19:48:33 -0800 Subject: [PATCH 20/22] Revert source paths to build dir --- .coveragerc | 9 ++++++--- README.md | 6 ++++-- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/.coveragerc b/.coveragerc index dd2f0de5..5a8c6f66 100644 --- a/.coveragerc +++ b/.coveragerc @@ -6,6 +6,9 @@ omit = /usr/* [paths] source = - $OPENRAM_HOME - $OPENRAM_TECH - + /home/gitlab-runner/builds/2fd64746/0 + /home/gitlab-runner/builds/2fd64746/1 + /home/gitlab-runner/builds/2fd64746/2 + /home/gitlab-runner/builds/2fd64746/3 + /home/gitlab-runner/builds/2fd64746/4 + /home/gitlab-runner/builds/2fd64746/5 diff --git a/README.md b/README.md index 7bbef133..9f125842 100644 --- a/README.md +++ b/README.md @@ -3,11 +3,13 @@ [![Python 3.5](https://img.shields.io/badge/Python-3.5-green.svg)](https://www.python.org/) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) -Master: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) +Master: +[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) ![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?job=coverage?private_token=ynB6rSFLzvKUseoBPcwV) [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) -Dev: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) +Dev: +[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) ![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?job=coverage?private_token=ynB6rSFLzvKUseoBPcwV) [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) From 3864e45aec4cfc3fa9be153b9505f3c6a4b171a3 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 20 Nov 2018 20:58:52 -0800 Subject: [PATCH 21/22] Duh. Forgot coverage report. --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2105a092..27c341aa 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,6 +29,7 @@ coverage: stage: coverage script: - coverage combine + - coverage report - coverage html -d coverage_html artifacts: paths: From 21fec02dc77f675291602af2c27b08d5f7f46053 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 21 Nov 2018 06:38:39 -0800 Subject: [PATCH 22/22] Remove job from coverage badge URL. --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 9f125842..693d32ef 100644 --- a/README.md +++ b/README.md @@ -5,12 +5,12 @@ Master: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?job=coverage?private_token=ynB6rSFLzvKUseoBPcwV) +![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV) [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) Dev: [![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?job=coverage?private_token=ynB6rSFLzvKUseoBPcwV) +![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV) [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) An open-source static random access memory (SRAM) compiler.