From 599e5457a00ebc54ba6693f79b7cde2477b5841f Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 22 Feb 2019 17:40:49 -0800 Subject: [PATCH] Fix all libs to have pin indices --- .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 6 +++--- .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 6 +++--- .../sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 6 +++--- .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index afb22057..a06ff5b5 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){ address : ADDR0; clocked_on : clk0; } - pin(DIN0){ + pin(DIN0[1:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){ memory_read(){ address : ADDR0; } - pin(DOUT0){ + pin(DOUT0[1:0]){ timing(){ timing_sense : non_unate; related_pin : "clk0"; @@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){ direction : input; capacitance : 0.2091; max_transition : 0.04; - pin(ADDR0){ + pin(ADDR0[3:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index b20f10be..d7d7de7e 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){ address : ADDR0; clocked_on : clk0; } - pin(DIN0){ + pin(DIN0[1:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){ memory_read(){ address : ADDR0; } - pin(DOUT0){ + pin(DOUT0[1:0]){ timing(){ timing_sense : non_unate; related_pin : "clk0"; @@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){ direction : input; capacitance : 0.2091; max_transition : 0.04; - pin(ADDR0){ + pin(ADDR0[3:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 5c56ab1e..72a106ac 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){ address : ADDR0; clocked_on : clk0; } - pin(DIN0){ + pin(DIN0[1:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){ memory_read(){ address : ADDR0; } - pin(DOUT0){ + pin(DOUT0[1:0]){ timing(){ timing_sense : non_unate; related_pin : "clk0"; @@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){ direction : input; capacitance : 9.8242; max_transition : 0.4; - pin(ADDR0){ + pin(ADDR0[3:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 64340a5b..124f80ff 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){ address : ADDR0; clocked_on : clk0; } - pin(DIN0){ + pin(DIN0[1:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0"; @@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){ memory_read(){ address : ADDR0; } - pin(DOUT0){ + pin(DOUT0[1:0]){ timing(){ timing_sense : non_unate; related_pin : "clk0"; @@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){ direction : input; capacitance : 9.8242; max_transition : 0.4; - pin(ADDR0){ + pin(ADDR0[3:0]){ timing(){ timing_type : setup_rising; related_pin : "clk0";