From c24879162aec2c7f1d0096f1ec9e882927267b1d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 8 May 2019 16:06:21 -0700 Subject: [PATCH 01/11] Add back scn3me_subm tech files --- compiler/base/contact.py | 7 +- compiler/tests/config_scn3me_subm.py | 22 + compiler/tests/config_scn3me_subm_back_end.py | 22 + .../tests/config_scn3me_subm_front_end.py | 19 + technology/scn3me_subm/__init__.py | 43 + .../scn3me_subm/gds_lib/cell_1rw_1r.gds | Bin 0 -> 6330 bytes technology/scn3me_subm/gds_lib/cell_1w_1r.gds | Bin 0 -> 8192 bytes technology/scn3me_subm/gds_lib/cell_6t.gds | Bin 0 -> 5916 bytes technology/scn3me_subm/gds_lib/dff.gds | Bin 0 -> 16622 bytes technology/scn3me_subm/gds_lib/ms_flop.gds | Bin 0 -> 18934 bytes .../gds_lib/replica_cell_1rw_1r.gds | Bin 0 -> 6282 bytes .../gds_lib/replica_cell_1w_1r.gds | Bin 0 -> 8192 bytes .../scn3me_subm/gds_lib/replica_cell_6t.gds | Bin 0 -> 6060 bytes technology/scn3me_subm/gds_lib/sense_amp.gds | Bin 0 -> 8312 bytes technology/scn3me_subm/gds_lib/tri_gate.gds | Bin 0 -> 4576 bytes .../scn3me_subm/gds_lib/write_driver.gds | Bin 0 -> 11804 bytes technology/scn3me_subm/mag_lib/.magicrc | 5 + .../scn3me_subm/mag_lib/cell_1rw_1r.gds | Bin 0 -> 6330 bytes .../scn3me_subm/mag_lib/cell_1rw_1r.mag | 142 + technology/scn3me_subm/mag_lib/cell_6t.mag | 117 + technology/scn3me_subm/mag_lib/convertall.sh | 14 + technology/scn3me_subm/mag_lib/dff.mag | 279 + technology/scn3me_subm/mag_lib/ms_flop.mag | 294 + .../mag_lib/replica_cell_1rw_1r.gds | Bin 0 -> 6282 bytes .../mag_lib/replica_cell_1rw_1r.mag | 145 + .../scn3me_subm/mag_lib/replica_cell_6t.mag | 118 + technology/scn3me_subm/mag_lib/sense_amp.mag | 136 + technology/scn3me_subm/mag_lib/setup.tcl | 15 + technology/scn3me_subm/mag_lib/tri_gate.mag | 98 + .../scn3me_subm/mag_lib/write_driver.mag | 224 + technology/scn3me_subm/models/ff/nmos.sp | 10 + technology/scn3me_subm/models/ff/pmos.sp | 9 + technology/scn3me_subm/models/nom/nmos.sp | 9 + technology/scn3me_subm/models/nom/pmos.sp | 9 + technology/scn3me_subm/models/ss/nmos.sp | 10 + technology/scn3me_subm/models/ss/pmos.sp | 9 + technology/scn3me_subm/sp_lib/cell_6t.sp | 10 + technology/scn3me_subm/sp_lib/dff.sp | 27 + technology/scn3me_subm/sp_lib/ms_flop.sp | 29 + .../scn3me_subm/sp_lib/replica_cell_6t.sp | 10 + technology/scn3me_subm/sp_lib/sense_amp.sp | 12 + technology/scn3me_subm/sp_lib/tri_gate.sp | 13 + technology/scn3me_subm/sp_lib/write_driver.sp | 38 + technology/scn3me_subm/sue_lib/cell_6t.sue | 46 + technology/scn3me_subm/sue_lib/ms_flop.sue | 84 + .../scn3me_subm/sue_lib/replica_cell_6t.sue | 49 + technology/scn3me_subm/sue_lib/sense_amp.sue | 52 + technology/scn3me_subm/sue_lib/tri_gate.sue | 37 + .../scn3me_subm/sue_lib/write_driver.sue | 44 + technology/scn3me_subm/tech/README | 10 + .../scn3me_subm/tech/SCN3ME_SUBM.30.tech | 7891 +++++++++++++++++ technology/scn3me_subm/tech/__init__.py | 6 + .../tech/calibreDRC_scn3me_subm.rul | 225 + .../tech/calibreLVS_scn3me_subm.rul | 123 + technology/scn3me_subm/tech/tech.py | 311 + technology/scn3me_subm/tf/README | 19 + technology/scn3me_subm/tf/display.drf | 714 ++ .../scn3me_subm/tf/glade_scn3me_subm.py | 7 + technology/scn3me_subm/tf/layers.map | 16 + technology/scn3me_subm/tf/mosis.tf | 848 ++ technology/scn4m_subm/tech/tech.py | 2 +- 61 files changed, 12376 insertions(+), 3 deletions(-) create mode 100644 compiler/tests/config_scn3me_subm.py create mode 100644 compiler/tests/config_scn3me_subm_back_end.py create mode 100644 compiler/tests/config_scn3me_subm_front_end.py create mode 100644 technology/scn3me_subm/__init__.py create mode 100644 technology/scn3me_subm/gds_lib/cell_1rw_1r.gds create mode 100644 technology/scn3me_subm/gds_lib/cell_1w_1r.gds create mode 100644 technology/scn3me_subm/gds_lib/cell_6t.gds create mode 100644 technology/scn3me_subm/gds_lib/dff.gds create mode 100644 technology/scn3me_subm/gds_lib/ms_flop.gds create mode 100644 technology/scn3me_subm/gds_lib/replica_cell_1rw_1r.gds create mode 100644 technology/scn3me_subm/gds_lib/replica_cell_1w_1r.gds create mode 100644 technology/scn3me_subm/gds_lib/replica_cell_6t.gds create mode 100644 technology/scn3me_subm/gds_lib/sense_amp.gds create mode 100644 technology/scn3me_subm/gds_lib/tri_gate.gds create mode 100644 technology/scn3me_subm/gds_lib/write_driver.gds create mode 100644 technology/scn3me_subm/mag_lib/.magicrc create mode 100644 technology/scn3me_subm/mag_lib/cell_1rw_1r.gds create mode 100644 technology/scn3me_subm/mag_lib/cell_1rw_1r.mag create mode 100644 technology/scn3me_subm/mag_lib/cell_6t.mag create mode 100755 technology/scn3me_subm/mag_lib/convertall.sh create mode 100644 technology/scn3me_subm/mag_lib/dff.mag create mode 100644 technology/scn3me_subm/mag_lib/ms_flop.mag create mode 100644 technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.gds create mode 100644 technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag create mode 100644 technology/scn3me_subm/mag_lib/replica_cell_6t.mag create mode 100644 technology/scn3me_subm/mag_lib/sense_amp.mag create mode 100644 technology/scn3me_subm/mag_lib/setup.tcl create mode 100644 technology/scn3me_subm/mag_lib/tri_gate.mag create mode 100644 technology/scn3me_subm/mag_lib/write_driver.mag create mode 100644 technology/scn3me_subm/models/ff/nmos.sp create mode 100644 technology/scn3me_subm/models/ff/pmos.sp create mode 100644 technology/scn3me_subm/models/nom/nmos.sp create mode 100644 technology/scn3me_subm/models/nom/pmos.sp create mode 100644 technology/scn3me_subm/models/ss/nmos.sp create mode 100644 technology/scn3me_subm/models/ss/pmos.sp create mode 100644 technology/scn3me_subm/sp_lib/cell_6t.sp create mode 100644 technology/scn3me_subm/sp_lib/dff.sp create mode 100644 technology/scn3me_subm/sp_lib/ms_flop.sp create mode 100644 technology/scn3me_subm/sp_lib/replica_cell_6t.sp create mode 100644 technology/scn3me_subm/sp_lib/sense_amp.sp create mode 100644 technology/scn3me_subm/sp_lib/tri_gate.sp create mode 100644 technology/scn3me_subm/sp_lib/write_driver.sp create mode 100644 technology/scn3me_subm/sue_lib/cell_6t.sue create mode 100644 technology/scn3me_subm/sue_lib/ms_flop.sue create mode 100644 technology/scn3me_subm/sue_lib/replica_cell_6t.sue create mode 100644 technology/scn3me_subm/sue_lib/sense_amp.sue create mode 100644 technology/scn3me_subm/sue_lib/tri_gate.sue create mode 100644 technology/scn3me_subm/sue_lib/write_driver.sue create mode 100644 technology/scn3me_subm/tech/README create mode 100644 technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech create mode 100755 technology/scn3me_subm/tech/__init__.py create mode 100755 technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul create mode 100755 technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul create mode 100755 technology/scn3me_subm/tech/tech.py create mode 100644 technology/scn3me_subm/tf/README create mode 100644 technology/scn3me_subm/tf/display.drf create mode 100644 technology/scn3me_subm/tf/glade_scn3me_subm.py create mode 100644 technology/scn3me_subm/tf/layers.map create mode 100644 technology/scn3me_subm/tf/mosis.tf diff --git a/compiler/base/contact.py b/compiler/base/contact.py index de1afec6..396b2a6d 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -8,7 +8,7 @@ import hierarchy_design import debug import utils -from tech import drc +from tech import drc,layer from vector import vector @@ -196,5 +196,8 @@ active = factory.create(module_type="contact", layer_stack=("active", "contact", poly = factory.create(module_type="contact", layer_stack=("poly", "contact", "metal1"), directions=("V","H")) m1m2 = factory.create(module_type="contact", layer_stack=("metal1", "via1", "metal2"), directions=("H","V")) m2m3 = factory.create(module_type="contact", layer_stack=("metal2", "via2", "metal3"), directions=("V","H")) -m3m4 = factory.create(module_type="contact", layer_stack=("metal3", "via3", "metal4"), directions=("H","V")) +if "metal4" in layer.keys(): + m3m4 = factory.create(module_type="contact", layer_stack=("metal3", "via3", "metal4"), directions=("H","V")) +else: + m3m4 = None diff --git a/compiler/tests/config_scn3me_subm.py b/compiler/tests/config_scn3me_subm.py new file mode 100644 index 00000000..2cd02b5e --- /dev/null +++ b/compiler/tests/config_scn3me_subm.py @@ -0,0 +1,22 @@ +# See LICENSE for licensing information. +# +#Copyright (c) 2016-2019 Regents of the University of California and The Board +#of Regents for the Oklahoma Agricultural and Mechanical College +#(acting for and on behalf of Oklahoma State University) +#All rights reserved. +# +word_size = 1 +num_words = 16 + +tech_name = "scn3me_subm" +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + +route_supplies = True +check_lvsdrc = True + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + diff --git a/compiler/tests/config_scn3me_subm_back_end.py b/compiler/tests/config_scn3me_subm_back_end.py new file mode 100644 index 00000000..5586ebca --- /dev/null +++ b/compiler/tests/config_scn3me_subm_back_end.py @@ -0,0 +1,22 @@ +# See LICENSE for licensing information. +# +#Copyright (c) 2016-2019 Regents of the University of California and The Board +#of Regents for the Oklahoma Agricultural and Mechanical College +#(acting for and on behalf of Oklahoma State University) +#All rights reserved. +# +word_size = 1 +num_words = 16 + +tech_name = "scn3me_subm" +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + +route_supplies = True +check_lvsdrc = True +inline_lvsdrc = True + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" diff --git a/compiler/tests/config_scn3me_subm_front_end.py b/compiler/tests/config_scn3me_subm_front_end.py new file mode 100644 index 00000000..7b39e46d --- /dev/null +++ b/compiler/tests/config_scn3me_subm_front_end.py @@ -0,0 +1,19 @@ +# See LICENSE for licensing information. +# +#Copyright (c) 2016-2019 Regents of the University of California and The Board +#of Regents for the Oklahoma Agricultural and Mechanical College +#(acting for and on behalf of Oklahoma State University) +#All rights reserved. +# +word_size = 1 +num_words = 16 + +tech_name = "scn3me_subm" +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + diff --git a/technology/scn3me_subm/__init__.py b/technology/scn3me_subm/__init__.py new file mode 100644 index 00000000..87b26056 --- /dev/null +++ b/technology/scn3me_subm/__init__.py @@ -0,0 +1,43 @@ +# See LICENSE for licensing information. +# +#Copyright (c) 2016-2019 Regents of the University of California and The Board +#of Regents for the Oklahoma Agricultural and Mechanical College +#(acting for and on behalf of Oklahoma State University) +#All rights reserved. +# +#!/usr/bin/python +""" +This type of setup script should be placed in the setup_scripts directory in the trunk +""" + +import sys +import os + +TECHNOLOGY = "scn3me_subm" + + +########################## +# CDK paths + +# os.environ["CDK_DIR"] = CDK_DIR #PDK path +# os.environ["SYSTEM_CDS_LIB_DIR"] = "{0}/cdssetup".format(CDK_DIR) +# os.environ["CDS_SITE"] = CDK_DIR +os.environ["MGC_TMPDIR"] = "/tmp" + +########################### +# OpenRAM Paths + + +try: + DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME")) +except: + OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) + DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech" +os.environ["DRCLVS_HOME"] = DRCLVS_HOME + +# try: +# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) +# except: +OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) +os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) + diff --git a/technology/scn3me_subm/gds_lib/cell_1rw_1r.gds b/technology/scn3me_subm/gds_lib/cell_1rw_1r.gds new file mode 100644 index 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X>hW&S)jQv+$GeZ~IWOyDJQMl{QEIs5 literal 0 HcmV?d00001 diff --git a/technology/scn3me_subm/mag_lib/cell_1rw_1r.mag b/technology/scn3me_subm/mag_lib/cell_1rw_1r.mag new file mode 100644 index 00000000..9aec1c5d --- /dev/null +++ b/technology/scn3me_subm/mag_lib/cell_1rw_1r.mag @@ -0,0 +1,142 @@ +magic +tech scmos +timestamp 1542220294 +<< nwell >> +rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 25 17 29 23 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 6 33 9 37 +rect 45 33 48 37 +rect 25 23 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< pdm12contact >> +rect 25 54 29 58 +<< ndm12contact >> +rect 9 17 13 21 +rect 41 17 45 21 +<< nsm12contact >> +rect 25 68 29 72 +<< metal2 >> +rect 2 37 6 72 +rect 2 0 6 33 +rect 9 21 13 72 +rect 25 58 29 68 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 72 +rect 41 0 45 17 +rect 48 37 52 72 +rect 48 0 52 33 +<< comment >> +rect 0 0 54 70 +<< labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +<< end >> diff --git a/technology/scn3me_subm/mag_lib/cell_6t.mag b/technology/scn3me_subm/mag_lib/cell_6t.mag new file mode 100644 index 00000000..f2e9906a --- /dev/null +++ b/technology/scn3me_subm/mag_lib/cell_6t.mag @@ -0,0 +1,117 @@ +magic +tech scmos +timestamp 1536091415 +<< nwell >> +rect -8 29 42 51 +<< pwell >> +rect -8 -8 42 29 +<< ntransistor >> +rect 7 10 9 18 +rect 29 10 31 18 +rect 10 3 14 5 +rect 24 3 28 5 +<< ptransistor >> +rect 7 37 11 40 +rect 27 37 31 40 +<< ndiffusion >> +rect -2 16 7 18 +rect 2 12 7 16 +rect -2 10 7 12 +rect 9 14 10 18 +rect 9 10 14 14 +rect 28 14 29 18 +rect 24 10 29 14 +rect 31 16 36 18 +rect 31 12 32 16 +rect 31 10 36 12 +rect 10 5 14 10 +rect 24 5 28 10 +rect 10 2 14 3 +rect 24 2 28 3 +<< pdiffusion >> +rect 2 37 7 40 +rect 11 37 12 40 +rect 26 37 27 40 +rect 31 37 32 40 +<< ndcontact >> +rect -2 12 2 16 +rect 10 14 14 18 +rect 24 14 28 18 +rect 32 12 36 16 +rect 10 -2 14 2 +rect 24 -2 28 2 +<< pdcontact >> +rect -2 36 2 40 +rect 12 36 16 40 +rect 22 36 26 40 +rect 32 36 36 40 +<< psubstratepcontact >> +rect -2 22 2 26 +rect 32 22 36 26 +<< nsubstratencontact >> +rect 32 44 36 48 +<< polysilicon >> +rect 7 40 11 42 +rect 27 40 31 42 +rect 7 35 11 37 +rect 7 21 9 35 +rect 27 34 31 37 +rect 15 33 31 34 +rect 19 32 31 33 +rect 7 20 21 21 +rect 7 19 24 20 +rect 7 18 9 19 +rect 29 18 31 32 +rect 7 8 9 10 +rect 17 5 21 6 +rect 29 8 31 10 +rect -2 3 10 5 +rect 14 3 24 5 +rect 28 3 36 5 +<< polycontact >> +rect 15 29 19 33 +rect 21 20 25 24 +rect 17 6 21 10 +<< metal1 >> +rect -2 44 15 48 +rect 19 44 32 48 +rect -2 40 2 44 +rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 26 2 29 +rect -2 16 2 22 +rect 11 18 15 36 +rect 23 24 27 36 +rect 25 20 27 24 +rect 14 14 15 18 +rect 23 18 27 20 +rect 32 26 36 29 +rect 23 14 24 18 +rect 32 16 36 22 +rect -2 6 17 9 +rect 21 6 36 9 +rect -2 5 36 6 +<< m2contact >> +rect 15 44 19 48 +rect -2 29 2 33 +rect 32 29 36 33 +rect 6 -2 10 2 +rect 20 -2 24 2 +<< metal2 >> +rect -2 33 2 48 +rect -2 -2 2 29 +rect 6 2 10 48 +rect 24 -2 28 48 +rect 32 33 36 48 +rect 32 -2 36 29 +<< bb >> +rect 0 0 34 46 +<< labels >> +rlabel metal2 0 0 0 0 1 gnd +rlabel metal2 34 0 34 0 1 gnd +rlabel m2contact 17 46 17 46 5 vdd +rlabel metal2 8 43 8 43 1 bl +rlabel metal2 26 43 26 43 1 br +rlabel metal1 4 7 4 7 1 wl +<< end >> diff --git a/technology/scn3me_subm/mag_lib/convertall.sh b/technology/scn3me_subm/mag_lib/convertall.sh new file mode 100755 index 00000000..f5e2482c --- /dev/null +++ b/technology/scn3me_subm/mag_lib/convertall.sh @@ -0,0 +1,14 @@ +magic -dnull -noconsole << EOF +load dff +gds write dff.gds +load cell_6t +gds write cell_6t.gds +load replica_cell_6t +gds write replica_cell_6t.gds +load sense_amp +gds write sense_amp.gds +load tri_gate +gds write tri_gate.gds +load write_driver +gds write write_driver.gds +EOF diff --git a/technology/scn3me_subm/mag_lib/dff.mag b/technology/scn3me_subm/mag_lib/dff.mag new file mode 100644 index 00000000..46d22c84 --- /dev/null +++ b/technology/scn3me_subm/mag_lib/dff.mag @@ -0,0 +1,279 @@ +magic +tech scmos +timestamp 1536089597 +<< nwell >> +rect 0 48 109 103 +<< pwell >> +rect 0 -3 109 48 +<< ntransistor >> +rect 11 6 13 26 +rect 19 6 21 16 +rect 24 6 26 16 +rect 33 6 35 16 +rect 38 6 40 16 +rect 47 6 49 16 +rect 63 6 65 16 +rect 68 6 70 16 +rect 78 6 80 16 +rect 83 6 85 16 +rect 91 6 93 26 +<< ptransistor >> +rect 11 54 13 94 +rect 19 74 21 94 +rect 25 74 27 94 +rect 33 74 35 94 +rect 39 74 41 94 +rect 47 74 49 94 +rect 63 74 65 94 +rect 68 74 70 94 +rect 78 84 80 94 +rect 83 84 85 94 +rect 91 54 93 94 +<< ndiffusion >> +rect 6 25 11 26 +rect 10 6 11 25 +rect 13 25 18 26 +rect 13 6 14 25 +rect 86 25 91 26 +rect 18 6 19 16 +rect 21 6 24 16 +rect 26 15 33 16 +rect 26 6 28 15 +rect 32 6 33 15 +rect 35 6 38 16 +rect 40 15 47 16 +rect 40 6 41 15 +rect 45 6 47 15 +rect 49 15 54 16 +rect 49 6 50 15 +rect 58 15 63 16 +rect 62 6 63 15 +rect 65 6 68 16 +rect 70 15 78 16 +rect 70 6 72 15 +rect 76 6 78 15 +rect 80 6 83 16 +rect 85 6 86 16 +rect 90 6 91 25 +rect 93 25 98 26 +rect 93 6 94 25 +<< pdiffusion >> +rect 6 93 11 94 +rect 10 54 11 93 +rect 13 55 14 94 +rect 18 74 19 94 +rect 21 74 25 94 +rect 27 93 33 94 +rect 27 74 28 93 +rect 32 74 33 93 +rect 35 74 39 94 +rect 41 93 47 94 +rect 41 74 42 93 +rect 46 74 47 93 +rect 49 93 54 94 +rect 49 74 50 93 +rect 58 93 63 94 +rect 62 74 63 93 +rect 65 74 68 94 +rect 70 93 78 94 +rect 70 74 72 93 +rect 76 84 78 93 +rect 80 84 83 94 +rect 85 93 91 94 +rect 85 84 86 93 +rect 76 74 77 84 +rect 13 54 18 55 +rect 90 54 91 93 +rect 93 93 98 94 +rect 93 54 94 93 +<< ndcontact >> +rect 6 6 10 25 +rect 14 6 18 25 +rect 28 6 32 15 +rect 41 6 45 15 +rect 50 6 54 15 +rect 58 6 62 15 +rect 72 6 76 15 +rect 86 6 90 25 +rect 94 6 98 25 +<< pdcontact >> +rect 6 54 10 93 +rect 14 55 18 94 +rect 28 74 32 93 +rect 42 74 46 93 +rect 50 74 54 93 +rect 58 74 62 93 +rect 72 74 76 93 +rect 86 54 90 93 +rect 94 54 98 93 +<< psubstratepcontact >> +rect 102 6 106 10 +<< nsubstratencontact >> +rect 102 89 106 93 +<< polysilicon >> +rect 11 94 13 96 +rect 19 94 21 96 +rect 25 94 27 96 +rect 33 94 35 96 +rect 39 94 41 96 +rect 47 94 49 96 +rect 63 94 65 96 +rect 68 94 70 96 +rect 78 94 80 96 +rect 83 94 85 96 +rect 91 94 93 96 +rect 11 37 13 54 +rect 19 46 21 74 +rect 11 26 13 33 +rect 19 16 21 42 +rect 25 38 27 74 +rect 33 54 35 74 +rect 33 29 35 50 +rect 24 27 35 29 +rect 39 71 41 74 +rect 24 16 26 27 +rect 39 23 41 67 +rect 47 61 49 74 +rect 63 73 65 74 +rect 54 71 65 73 +rect 34 19 35 23 +rect 33 16 35 19 +rect 38 19 39 23 +rect 38 16 40 19 +rect 47 16 49 57 +rect 53 19 55 67 +rect 68 63 70 74 +rect 78 67 80 84 +rect 76 65 80 67 +rect 63 61 70 63 +rect 61 24 63 33 +rect 68 31 70 61 +rect 83 53 85 84 +rect 79 51 85 53 +rect 78 31 80 47 +rect 91 45 93 54 +rect 89 41 93 45 +rect 68 29 75 31 +rect 61 22 70 24 +rect 53 17 65 19 +rect 63 16 65 17 +rect 68 16 70 22 +rect 73 19 75 29 +rect 78 27 79 31 +rect 73 17 80 19 +rect 78 16 80 17 +rect 83 16 85 31 +rect 91 26 93 41 +rect 11 4 13 6 +rect 19 4 21 6 +rect 24 4 26 6 +rect 33 4 35 6 +rect 38 4 40 6 +rect 47 4 49 6 +rect 63 4 65 6 +rect 68 4 70 6 +rect 78 4 80 6 +rect 83 4 85 6 +rect 91 4 93 6 +<< polycontact >> +rect 17 42 21 46 +rect 10 33 14 37 +rect 31 50 35 54 +rect 25 34 29 38 +rect 39 67 43 71 +rect 45 57 49 61 +rect 30 19 34 23 +rect 39 19 43 23 +rect 53 67 57 71 +rect 59 59 63 63 +rect 74 61 78 65 +rect 59 33 63 37 +rect 77 47 81 51 +rect 85 41 89 45 +rect 79 27 83 31 +<< metal1 >> +rect 0 97 109 103 +rect 14 94 18 97 +rect 6 93 10 94 +rect 28 93 32 94 +rect 22 74 28 77 +rect 42 93 46 97 +rect 50 93 54 94 +rect 58 93 62 97 +rect 71 93 77 94 +rect 71 74 72 93 +rect 76 74 77 93 +rect 86 93 90 97 +rect 50 71 53 74 +rect 43 68 53 71 +rect 26 57 45 60 +rect 52 60 59 63 +rect 52 54 55 60 +rect 71 56 74 65 +rect 10 50 31 52 +rect 35 51 55 54 +rect 62 53 74 56 +rect 94 93 98 94 +rect 102 93 106 97 +rect 6 49 34 50 +rect 21 43 38 46 +rect 18 34 25 37 +rect 62 37 65 53 +rect 94 51 98 54 +rect 81 48 94 51 +rect 74 41 85 44 +rect 29 34 59 37 +rect 6 25 10 26 +rect 14 25 18 26 +rect 31 23 34 34 +rect 63 34 65 37 +rect 94 31 98 47 +rect 83 28 98 31 +rect 94 25 98 28 +rect 43 19 53 22 +rect 50 16 53 19 +rect 22 15 32 16 +rect 22 13 28 15 +rect 41 15 46 16 +rect 45 6 46 15 +rect 50 15 54 16 +rect 58 15 62 16 +rect 70 15 77 16 +rect 70 13 72 15 +rect 71 6 72 13 +rect 76 6 77 15 +rect 14 3 18 6 +rect 41 3 46 6 +rect 58 3 62 6 +rect 86 3 90 6 +rect 102 3 106 6 +rect 0 -3 109 3 +<< m2contact >> +rect 22 70 26 74 +rect 70 70 74 74 +rect 22 57 26 61 +rect 6 50 10 54 +rect 38 43 42 47 +rect 14 33 18 37 +rect 94 47 98 51 +rect 70 40 74 44 +rect 6 26 10 30 +rect 22 16 26 20 +rect 70 16 74 20 +<< metal2 >> +rect 22 61 26 70 +rect 6 30 10 50 +rect 22 20 26 57 +rect 70 44 74 70 +rect 70 20 74 40 +<< bb >> +rect 0 0 109 100 +<< labels >> +rlabel m2contact 15 34 15 34 4 clk +rlabel m2contact 40 45 40 45 4 D +rlabel m2contact 96 49 96 49 4 Q +rlabel metal1 32 98 32 98 4 vdd +rlabel metal1 44 1 44 1 4 gnd +<< properties >> +string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000 +<< end >> diff --git a/technology/scn3me_subm/mag_lib/ms_flop.mag b/technology/scn3me_subm/mag_lib/ms_flop.mag new file mode 100644 index 00000000..713d264f --- /dev/null +++ b/technology/scn3me_subm/mag_lib/ms_flop.mag @@ -0,0 +1,294 @@ +magic +tech scmos +timestamp 1536089622 +<< nwell >> +rect -2 0 18 200 +<< pwell >> +rect 18 0 40 200 +<< ntransistor >> +rect 24 178 27 180 +rect 24 162 27 164 +rect 24 138 27 140 +rect 24 130 27 132 +rect 24 112 27 114 +rect 24 93 27 95 +rect 24 77 27 79 +rect 24 50 27 52 +rect 24 42 27 44 +rect 24 24 27 26 +<< ptransistor >> +rect 6 178 12 180 +rect 6 162 12 164 +rect 6 138 12 140 +rect 6 130 12 132 +rect 6 112 12 114 +rect 6 93 12 95 +rect 6 77 12 79 +rect 6 50 12 52 +rect 6 42 12 44 +rect 6 24 12 26 +<< ndiffusion >> +rect 24 180 27 181 +rect 24 177 27 178 +rect 24 164 27 165 +rect 24 161 27 162 +rect 28 157 32 161 +rect 24 140 27 141 +rect 24 137 27 138 +rect 24 132 27 133 +rect 24 129 27 130 +rect 24 114 27 115 +rect 24 111 27 112 +rect 24 95 27 96 +rect 24 92 27 93 +rect 24 79 27 80 +rect 24 76 27 77 +rect 28 72 32 76 +rect 24 52 27 53 +rect 24 49 27 50 +rect 24 44 27 45 +rect 24 41 27 42 +rect 24 26 27 27 +rect 24 23 27 24 +<< pdiffusion >> +rect 6 180 12 181 +rect 6 177 12 178 +rect 6 164 12 165 +rect 6 161 12 162 +rect 6 140 12 141 +rect 6 137 12 138 +rect 6 132 12 133 +rect 6 129 12 130 +rect 6 114 12 115 +rect 6 111 12 112 +rect 6 95 12 96 +rect 6 92 12 93 +rect 6 79 12 80 +rect 6 76 12 77 +rect 6 52 12 53 +rect 6 49 12 50 +rect 6 44 12 45 +rect 6 41 12 42 +rect 6 26 12 27 +rect 6 23 12 24 +rect 8 18 12 19 +<< ndcontact >> +rect 24 181 28 185 +rect 24 173 28 177 +rect 24 165 28 169 +rect 24 157 28 161 +rect 24 141 28 145 +rect 24 133 28 137 +rect 24 125 28 129 +rect 24 115 28 119 +rect 24 107 28 111 +rect 24 96 28 100 +rect 24 88 28 92 +rect 24 80 28 84 +rect 24 72 28 76 +rect 24 53 28 57 +rect 24 45 28 49 +rect 24 37 28 41 +rect 24 27 28 31 +rect 24 19 28 23 +<< pdcontact >> +rect 6 181 12 185 +rect 6 173 12 177 +rect 6 165 12 169 +rect 6 157 12 161 +rect 6 141 12 145 +rect 6 133 12 137 +rect 6 125 12 129 +rect 6 115 12 119 +rect 6 107 12 111 +rect 6 96 12 100 +rect 6 88 12 92 +rect 6 80 12 84 +rect 6 72 12 76 +rect 6 53 12 57 +rect 6 45 12 49 +rect 6 37 12 41 +rect 6 27 12 31 +rect 6 19 12 23 +<< psubstratepcontact >> +rect 32 157 36 161 +rect 32 72 36 76 +<< nsubstratencontact >> +rect 8 14 12 18 +<< polysilicon >> +rect 4 178 6 180 +rect 12 178 24 180 +rect 27 178 29 180 +rect 17 173 19 178 +rect 4 162 6 164 +rect 12 163 24 164 +rect 12 162 17 163 +rect 21 162 24 163 +rect 27 162 29 164 +rect 3 148 13 150 +rect 3 140 5 148 +rect 3 138 6 140 +rect 12 138 14 140 +rect 17 138 24 140 +rect 27 138 29 140 +rect 17 132 19 138 +rect 3 130 6 132 +rect 12 130 19 132 +rect 22 130 24 132 +rect 27 130 31 132 +rect 3 114 5 130 +rect 29 122 31 130 +rect 20 120 31 122 +rect 3 112 6 114 +rect 12 112 24 114 +rect 27 112 29 114 +rect 4 93 6 95 +rect 12 93 24 95 +rect 27 93 29 95 +rect 19 89 21 93 +rect 4 77 6 79 +rect 12 78 24 79 +rect 12 77 17 78 +rect 21 77 24 78 +rect 27 77 29 79 +rect 3 60 13 62 +rect 3 52 5 60 +rect 3 50 6 52 +rect 12 50 14 52 +rect 17 50 24 52 +rect 27 50 29 52 +rect 17 44 19 50 +rect 3 42 6 44 +rect 12 42 19 44 +rect 22 42 24 44 +rect 27 42 31 44 +rect 3 26 5 42 +rect 29 34 31 42 +rect 20 32 31 34 +rect 3 24 6 26 +rect 12 24 24 26 +rect 27 24 29 26 +rect 16 14 18 24 +<< polycontact >> +rect 16 169 20 173 +rect 17 159 21 163 +rect 13 148 17 152 +rect 16 118 20 122 +rect 15 108 19 112 +rect 17 85 21 89 +rect 17 74 21 78 +rect 13 60 17 64 +rect 16 30 20 34 +rect 15 10 19 14 +<< metal1 >> +rect 16 182 24 185 +rect -2 173 6 177 +rect 28 173 36 177 +rect -2 164 2 173 +rect 12 166 20 169 +rect 2 160 6 161 +rect -2 157 6 160 +rect 33 161 36 173 +rect -2 111 2 157 +rect 28 157 32 161 +rect 12 142 24 145 +rect 12 134 20 137 +rect 12 126 20 129 +rect 20 118 24 119 +rect 16 116 24 118 +rect -2 107 6 111 +rect 33 111 36 153 +rect -2 92 2 107 +rect 28 107 36 111 +rect 12 97 24 100 +rect 33 92 36 107 +rect -2 88 6 92 +rect -2 76 2 88 +rect 28 88 36 92 +rect 6 84 20 85 +rect 12 82 20 84 +rect -2 72 6 76 +rect 33 76 36 88 +rect -2 41 2 72 +rect 28 72 32 76 +rect 12 54 24 57 +rect 12 46 20 49 +rect 12 38 20 41 +rect -2 22 2 37 +rect 20 30 24 31 +rect 16 28 24 30 +rect 33 23 36 68 +rect -2 19 6 22 +rect 28 20 36 23 +rect 8 18 12 19 +rect -2 10 15 11 +rect 19 10 36 11 +rect -2 8 36 10 +<< m2contact >> +rect 12 181 16 185 +rect 20 166 24 170 +rect -2 160 2 164 +rect 17 155 21 159 +rect 32 153 36 157 +rect 6 145 10 149 +rect 17 148 21 152 +rect 20 133 24 137 +rect 20 125 24 129 +rect 12 115 16 119 +rect 15 104 19 108 +rect 6 100 10 104 +rect 20 81 24 85 +rect 17 70 21 74 +rect 32 68 36 72 +rect 6 57 10 61 +rect 17 60 21 64 +rect 20 45 24 49 +rect -2 37 2 41 +rect 20 37 24 41 +rect 12 27 16 31 +<< metal2 >> +rect 6 185 10 200 +rect 15 196 19 200 +rect 15 192 24 196 +rect 6 181 12 185 +rect 6 149 9 181 +rect 20 170 24 192 +rect 21 155 27 159 +rect 18 143 21 148 +rect 13 140 21 143 +rect 13 119 16 140 +rect 24 133 27 155 +rect 5 100 6 104 +rect 5 61 8 100 +rect 15 93 19 104 +rect 11 90 19 93 +rect 11 67 14 90 +rect 24 81 27 129 +rect 21 70 27 74 +rect 11 64 16 67 +rect 5 57 6 61 +rect 13 60 17 64 +rect 13 31 16 60 +rect 24 45 27 70 +rect 24 8 27 41 +rect 19 4 27 8 +rect 15 0 19 4 +<< m3contact >> +rect 15 4 19 8 +<< metal3 >> +rect 14 8 20 9 +rect 14 4 15 8 +rect 19 4 20 8 +rect 14 3 20 4 +<< bb >> +rect 0 0 34 200 +<< labels >> +rlabel metal1 0 8 0 8 2 clk +rlabel metal3 15 4 15 4 1 din +rlabel metal2 6 196 6 196 5 dout_bar +rlabel metal2 15 196 15 196 5 dout +rlabel m2contact 34 70 34 70 1 gnd +rlabel m2contact 34 154 34 154 1 gnd +rlabel m2contact 0 162 0 162 3 vdd +rlabel m2contact 0 38 0 38 3 vdd +<< end >> diff --git a/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.gds b/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.gds new file mode 100644 index 0000000000000000000000000000000000000000..7e79ef75c1b506e9ff63e91e1509fefb2054bd75 GIT binary patch literal 6282 zcmbW5J&aXF7=}OY-o4zwvMdO=kVP^60vFhYHT(upi9Zn|(Tx&gg31y#xiMs8SPKdZ z3r#F6EJ(DVAfch4pxDBK!Waq*3kwSi3knMh3JMDgzlS+*&YZJ+L-ZtfpPP5)op0uw zxifRtde*TKn_AJa3%1(EZIumd!WM1R`nJ|K+6tTO^cK#YAAWrH{WE9J4TooD78d~MXoq2rv`1*CT$Ns4~_nsNL=;fjRp})+Y|JiKv`G(8ZFUezJD)i}XX|s>;LuulhR0n*E_BZJ~?am(Wl9jGek7 zeMc8v5B*tZr%ufAow(XaiZ_b*bi(Vf3 zS1*}8{hQhNM9m%3X6T}qhyIO|$@lR2n)uMglAqXos4M2*tMV}Z%z@qS5FhF9df+J&wc{fwRcLL~3_ zMAwUc#!XC-cJPa>@$bohf5bR&JmpI~bScFaUC-k;{A0JxrpL@UE5*I@X6T~pp`SkD zW4{pbp^GIy9zN6+^Y2x87++^Rx#KPX`7NP~u7`f^*!YMe;zJi({=Iqr8TWs@KP>aJ zZ!?dg_IeOiU!=W$)bB9t`H-^!U35Jkf5U%pn0)M&_#r-YvE=8@M&3AkMe>F& zmh!i~n|$0K@k4y*V#&`w%~{KSC+glHx*m@If1Lk~{4q{)&G<#;09|xFjL$gnF>Vnb zy4dp1}J~V)Bb82gxtGp7+1u*ZG;BceH~pw)WqKpFGib z?rI|MJ?NtAVSLsMKJq8xLl;Ya;;`mfD`-$-my4)@QbvAE|%sG4tz_enkA}qU)ibc_we|`x82Otja?_amZW# z{{!-dE|&6V{*Y^aD!E-B&D2-cJ$=^tM`!-3^3c!x;^V$6YTiZHLqGG(!~Bc% z8(nlg^mAwCVf~8u&_&mC|FL}j@bHj3@eQ9t9?`$v^Lv;0|F!@AH}U`LG5&wez2TK# zt-raqIGlb!J#WwJU6`LQ)Z@<7y`I{ec|bkC<9mA_e$r~s*Js^7Z;SuWdc6> +rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 29 54 33 58 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 6 33 9 37 +rect 45 33 48 37 +rect 25 23 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 +<< metal2 >> +rect 2 37 6 72 +rect 2 0 6 33 +rect 9 21 13 72 +rect 25 58 29 68 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 72 +rect 41 0 45 17 +rect 48 37 52 72 +rect 48 0 52 33 +<< comment >> +rect 0 0 54 70 +<< labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +<< end >> diff --git a/technology/scn3me_subm/mag_lib/replica_cell_6t.mag b/technology/scn3me_subm/mag_lib/replica_cell_6t.mag new file mode 100644 index 00000000..d0dc472f --- /dev/null +++ b/technology/scn3me_subm/mag_lib/replica_cell_6t.mag @@ -0,0 +1,118 @@ +magic +tech scmos +timestamp 1536091380 +<< nwell >> +rect -8 29 42 51 +<< pwell >> +rect -8 -8 42 29 +<< ntransistor >> +rect 7 10 9 18 +rect 29 10 31 18 +rect 10 3 14 5 +rect 24 3 28 5 +<< ptransistor >> +rect 7 37 11 40 +rect 27 37 31 40 +<< ndiffusion >> +rect -2 16 7 18 +rect 2 12 7 16 +rect -2 10 7 12 +rect 9 14 10 18 +rect 9 10 14 14 +rect 28 14 29 18 +rect 24 10 29 14 +rect 31 16 36 18 +rect 31 12 32 16 +rect 31 10 36 12 +rect 10 5 14 10 +rect 24 5 28 10 +rect 10 2 14 3 +rect 24 2 28 3 +<< pdiffusion >> +rect 2 37 7 40 +rect 11 37 12 40 +rect 26 37 27 40 +rect 31 37 32 40 +<< ndcontact >> +rect -2 12 2 16 +rect 10 14 14 18 +rect 24 14 28 18 +rect 32 12 36 16 +rect 10 -2 14 2 +rect 24 -2 28 2 +<< pdcontact >> +rect -2 36 2 40 +rect 12 36 16 40 +rect 22 36 26 40 +rect 32 36 36 40 +<< psubstratepcontact >> +rect -2 22 2 26 +rect 32 22 36 26 +<< nsubstratencontact >> +rect 32 44 36 48 +<< polysilicon >> +rect 7 40 11 42 +rect 27 40 31 42 +rect 7 35 11 37 +rect 7 21 9 35 +rect 27 34 31 37 +rect 15 33 31 34 +rect 19 32 31 33 +rect 7 20 21 21 +rect 7 19 24 20 +rect 7 18 9 19 +rect 29 18 31 32 +rect 7 8 9 10 +rect 17 5 21 6 +rect 29 8 31 10 +rect -2 3 10 5 +rect 14 3 24 5 +rect 28 3 36 5 +<< polycontact >> +rect 15 29 19 33 +rect 21 20 25 24 +rect 17 6 21 10 +<< metal1 >> +rect -2 44 15 48 +rect 19 44 32 48 +rect -2 40 2 44 +rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 26 2 29 +rect 11 22 15 36 +rect 23 24 27 36 +rect -2 18 15 22 +rect 25 20 27 24 +rect -2 16 2 18 +rect 14 14 15 18 +rect 23 18 27 20 +rect 32 26 36 29 +rect 23 14 24 18 +rect 32 16 36 22 +rect -2 6 17 9 +rect 21 6 36 9 +rect -2 5 36 6 +<< m2contact >> +rect 15 44 19 48 +rect -2 29 2 33 +rect 32 29 36 33 +rect 6 -2 10 2 +rect 20 -2 24 2 +<< metal2 >> +rect -2 33 2 48 +rect -2 -2 2 29 +rect 6 2 10 48 +rect 24 -2 28 48 +rect 32 33 36 48 +rect 32 -2 36 29 +<< bb >> +rect 0 0 34 46 +<< labels >> +rlabel metal2 0 0 0 0 1 gnd +rlabel metal2 34 0 34 0 1 gnd +rlabel m2contact 17 46 17 46 5 vdd +rlabel metal2 8 43 8 43 1 bl +rlabel metal2 26 43 26 43 1 br +rlabel metal1 4 7 4 7 1 wl +<< end >> diff --git a/technology/scn3me_subm/mag_lib/sense_amp.mag b/technology/scn3me_subm/mag_lib/sense_amp.mag new file mode 100644 index 00000000..e5fa4373 --- /dev/null +++ b/technology/scn3me_subm/mag_lib/sense_amp.mag @@ -0,0 +1,136 @@ +magic +tech scmos +timestamp 1536089670 +<< nwell >> +rect 0 0 40 102 +<< pwell >> +rect 0 102 40 163 +<< ntransistor >> +rect 21 130 23 139 +rect 12 108 14 117 +rect 20 108 22 117 +<< ptransistor >> +rect 12 78 14 96 +rect 20 78 22 96 +rect 11 20 13 44 +rect 27 20 29 44 +<< ndiffusion >> +rect 20 130 21 139 +rect 23 130 24 139 +rect 11 108 12 117 +rect 14 108 15 117 +rect 19 108 20 117 +rect 22 108 23 117 +<< pdiffusion >> +rect 7 94 12 96 +rect 11 80 12 94 +rect 7 78 12 80 +rect 14 94 20 96 +rect 14 80 15 94 +rect 19 80 20 94 +rect 14 78 20 80 +rect 22 94 27 96 +rect 22 80 23 94 +rect 22 78 27 80 +rect 10 20 11 44 +rect 13 20 14 44 +rect 26 20 27 44 +rect 29 20 30 44 +<< ndcontact >> +rect 16 130 20 139 +rect 24 130 28 139 +rect 7 108 11 117 +rect 15 108 19 117 +rect 23 108 27 117 +<< pdcontact >> +rect 7 80 11 94 +rect 15 80 19 94 +rect 23 80 27 94 +rect 6 20 10 44 +rect 14 20 18 44 +rect 22 20 26 44 +rect 30 20 34 44 +<< psubstratepcontact >> +rect 32 137 36 141 +<< nsubstratencontact >> +rect 27 70 31 74 +<< polysilicon >> +rect 21 139 23 149 +rect 21 129 23 130 +rect 3 127 23 129 +rect 3 47 5 127 +rect 12 122 34 124 +rect 12 117 14 122 +rect 20 117 22 119 +rect 12 96 14 108 +rect 20 96 22 108 +rect 32 105 34 122 +rect 30 101 34 105 +rect 12 76 14 78 +rect 20 69 22 78 +rect 13 67 22 69 +rect 9 55 11 65 +rect 32 55 34 101 +rect 33 51 34 55 +rect 3 45 13 47 +rect 11 44 13 45 +rect 27 44 29 46 +rect 11 19 13 20 +rect 27 19 29 20 +rect 11 17 29 19 +<< polycontact >> +rect 20 149 24 153 +rect 26 101 30 105 +rect 9 65 13 69 +rect 9 51 13 55 +rect 29 51 33 55 +<< metal1 >> +rect -2 149 20 153 +rect 24 149 36 153 +rect 28 133 32 137 +rect 16 117 19 130 +rect 7 94 11 108 +rect 23 105 27 108 +rect 23 101 26 105 +rect 7 69 11 80 +rect 15 94 19 96 +rect 15 78 19 80 +rect 23 94 27 101 +rect 23 78 27 80 +rect 15 75 18 78 +rect 15 74 31 75 +rect 15 72 27 74 +rect 7 65 9 69 +rect 6 44 9 54 +rect 33 51 34 55 +rect 31 44 34 51 +rect 3 20 6 23 +rect 3 15 7 20 +<< m2contact >> +rect 32 133 36 137 +rect 27 66 31 70 +rect 13 44 17 48 +rect 22 44 26 48 +rect 3 11 7 15 +<< metal2 >> +rect 10 48 14 163 +rect 20 48 24 163 +rect 32 129 36 133 +rect 27 62 31 66 +rect 10 44 13 48 +rect 20 44 22 48 +rect 3 0 7 11 +rect 10 0 14 44 +rect 20 0 24 44 +<< bb >> +rect 0 0 34 163 +<< labels >> +flabel metal1 0 149 0 149 4 FreeSans 26 0 0 0 en +rlabel metal2 34 131 34 131 1 gnd +rlabel metal2 29 64 29 64 1 vdd +rlabel metal2 12 161 12 161 5 bl +rlabel metal2 22 161 22 161 5 br +rlabel metal2 5 3 5 3 1 dout +<< properties >> +string path 270.000 468.000 270.000 486.000 288.000 486.000 288.000 468.000 270.000 468.000 +<< end >> diff --git a/technology/scn3me_subm/mag_lib/setup.tcl b/technology/scn3me_subm/mag_lib/setup.tcl new file mode 100644 index 00000000..af55a416 --- /dev/null +++ b/technology/scn3me_subm/mag_lib/setup.tcl @@ -0,0 +1,15 @@ +# Setup file for netgen +ignore class c +equate class {-circuit1 nfet} {-circuit2 n} +equate class {-circuit1 pfet} {-circuit2 p} +# This circuit has symmetries and needs to be flattened to resolve them +# or the banks won't pass +flatten class {-circuit1 precharge_array_1} +flatten class {-circuit1 precharge_array_2} +flatten class {-circuit1 precharge_array_3} +flatten class {-circuit1 precharge_array_4} +property {-circuit1 nfet} remove as ad ps pd +property {-circuit1 pfet} remove as ad ps pd +property {-circuit2 n} remove as ad ps pd +property {-circuit2 p} remove as ad ps pd +permute transistors diff --git a/technology/scn3me_subm/mag_lib/tri_gate.mag b/technology/scn3me_subm/mag_lib/tri_gate.mag new file mode 100644 index 00000000..bda635c7 --- /dev/null +++ b/technology/scn3me_subm/mag_lib/tri_gate.mag @@ -0,0 +1,98 @@ +magic +tech scmos +timestamp 1536089695 +<< nwell >> +rect -2 45 38 73 +<< pwell >> +rect -2 0 38 45 +<< ntransistor >> +rect 9 27 11 31 +rect 17 27 19 31 +rect 25 27 27 31 +<< ptransistor >> +rect 9 53 11 61 +rect 17 53 19 61 +rect 25 53 27 61 +<< ndiffusion >> +rect 8 27 9 31 +rect 11 27 12 31 +rect 16 27 17 31 +rect 19 27 20 31 +rect 24 27 25 31 +rect 27 27 28 31 +<< pdiffusion >> +rect 8 53 9 61 +rect 11 53 12 61 +rect 16 53 17 61 +rect 19 53 20 61 +rect 24 53 25 61 +rect 27 53 28 61 +<< ndcontact >> +rect 4 27 8 31 +rect 12 27 16 31 +rect 20 27 24 31 +rect 28 27 32 31 +<< pdcontact >> +rect 4 53 8 61 +rect 12 53 16 61 +rect 20 53 24 61 +rect 28 53 32 61 +<< psubstratepcontact >> +rect 12 19 16 23 +<< nsubstratencontact >> +rect 12 65 16 69 +<< polysilicon >> +rect 25 63 35 65 +rect 9 61 11 63 +rect 17 61 19 63 +rect 25 61 27 63 +rect 9 50 11 53 +rect 9 31 11 46 +rect 17 42 19 53 +rect 25 51 27 53 +rect 17 31 19 38 +rect 25 31 27 33 +rect 9 25 11 27 +rect 17 25 19 27 +rect 25 16 27 27 +rect 33 8 35 63 +rect 32 6 35 8 +<< polycontact >> +rect 9 46 13 50 +rect 16 38 20 42 +rect 25 12 29 16 +rect 28 4 32 8 +<< metal1 >> +rect 16 65 23 69 +rect 12 61 16 65 +rect 3 53 4 61 +rect 3 42 6 53 +rect 13 46 15 50 +rect 3 38 16 42 +rect 3 31 6 38 +rect 29 31 32 53 +rect 3 27 4 31 +rect 12 23 16 27 +rect 16 19 24 23 +rect 0 12 25 16 +rect 29 12 36 16 +rect 0 4 28 8 +rect 32 4 36 8 +<< m2contact >> +rect 23 65 27 69 +rect 15 46 19 50 +rect 25 34 29 38 +rect 24 19 28 23 +<< metal2 >> +rect 15 34 25 38 +rect 15 0 19 34 +<< bb >> +rect 0 0 34 73 +<< labels >> +rlabel metal1 0 12 0 12 3 en +rlabel metal1 0 4 0 4 2 en_bar +rlabel metal2 16 1 16 1 1 out +rlabel m2contact 26 21 26 21 1 gnd +rlabel m2contact 25 67 25 67 1 vdd +rlabel m2contact 17 48 17 48 1 in +<< end >> diff --git a/technology/scn3me_subm/mag_lib/write_driver.mag b/technology/scn3me_subm/mag_lib/write_driver.mag new file mode 100644 index 00000000..ab2014aa --- /dev/null +++ b/technology/scn3me_subm/mag_lib/write_driver.mag @@ -0,0 +1,224 @@ +magic +tech scmos +timestamp 1536089714 +<< nwell >> +rect -3 101 37 138 +rect -3 0 37 51 +<< pwell >> +rect -3 138 37 202 +rect -3 51 37 101 +<< ntransistor >> +rect 9 177 11 189 +rect 17 177 19 189 +rect 15 162 27 164 +rect 9 144 11 148 +rect 17 144 19 148 +rect 10 82 12 89 +rect 18 82 20 89 +rect 8 57 10 64 +rect 16 57 18 64 +rect 24 60 26 64 +<< ptransistor >> +rect 9 125 11 132 +rect 17 125 19 132 +rect 10 107 12 114 +rect 18 107 20 114 +rect 8 38 10 45 +rect 16 38 18 45 +rect 24 38 26 45 +<< ndiffusion >> +rect 8 177 9 189 +rect 11 177 12 189 +rect 16 177 17 189 +rect 19 177 20 189 +rect 15 164 27 165 +rect 15 161 27 162 +rect 12 157 15 160 +rect 12 156 16 157 +rect 8 144 9 148 +rect 11 144 12 148 +rect 16 144 17 148 +rect 19 144 20 148 +rect 9 82 10 89 +rect 12 82 13 89 +rect 17 82 18 89 +rect 20 82 21 89 +rect 25 82 26 86 +rect 7 57 8 64 +rect 10 57 11 64 +rect 15 57 16 64 +rect 18 57 19 64 +rect 23 60 24 64 +rect 26 60 27 64 +<< pdiffusion >> +rect 8 125 9 132 +rect 11 125 12 132 +rect 16 125 17 132 +rect 19 125 20 132 +rect 12 122 16 125 +rect 9 107 10 114 +rect 12 107 13 114 +rect 17 107 18 114 +rect 20 107 21 114 +rect 7 38 8 45 +rect 10 38 11 45 +rect 15 38 16 45 +rect 18 38 19 45 +rect 23 38 24 45 +rect 26 38 27 45 +rect 3 35 7 38 +<< ndcontact >> +rect 4 177 8 189 +rect 12 177 16 189 +rect 20 177 24 189 +rect 15 165 27 169 +rect 15 157 27 161 +rect 4 144 8 148 +rect 12 144 16 148 +rect 20 144 24 148 +rect 5 82 9 89 +rect 13 82 17 89 +rect 21 82 25 89 +rect 3 57 7 64 +rect 11 57 15 64 +rect 19 57 23 64 +rect 27 60 31 64 +<< pdcontact >> +rect 4 125 8 132 +rect 12 125 16 132 +rect 20 125 24 132 +rect 5 107 9 114 +rect 13 107 17 114 +rect 21 107 25 114 +rect 3 38 7 45 +rect 11 38 15 45 +rect 19 38 23 45 +rect 27 38 31 45 +<< psubstratepcontact >> +rect 12 152 16 156 +rect 26 82 30 86 +<< nsubstratencontact >> +rect 12 118 16 122 +rect 3 31 7 35 +<< polysilicon >> +rect 9 194 30 196 +rect 9 189 11 194 +rect 17 189 19 191 +rect 28 185 30 194 +rect 9 175 11 177 +rect 17 172 19 177 +rect 6 170 19 172 +rect 6 167 8 170 +rect 13 162 15 164 +rect 27 162 33 164 +rect 9 148 11 150 +rect 17 148 19 150 +rect 9 132 11 144 +rect 17 132 19 144 +rect 9 124 11 125 +rect 2 122 11 124 +rect 17 124 19 125 +rect 17 122 28 124 +rect 2 75 4 122 +rect 10 114 12 116 +rect 18 114 20 116 +rect 10 89 12 107 +rect 18 106 20 107 +rect 16 104 20 106 +rect 16 92 18 104 +rect 26 100 28 122 +rect 27 96 28 100 +rect 16 90 20 92 +rect 18 89 20 90 +rect 10 81 12 82 +rect 10 79 13 81 +rect 2 71 3 75 +rect 11 71 13 79 +rect 18 79 20 82 +rect 18 77 23 79 +rect 31 71 33 162 +rect 11 69 33 71 +rect 11 67 13 69 +rect 8 65 13 67 +rect 8 64 10 65 +rect 16 64 18 66 +rect 24 64 26 66 +rect 8 45 10 57 +rect 16 52 18 57 +rect 24 52 26 60 +rect 16 50 26 52 +rect 16 45 18 50 +rect 24 45 26 50 +rect 8 28 10 38 +rect 16 14 18 38 +rect 24 36 26 38 +<< polycontact >> +rect 28 181 32 185 +rect 4 163 8 167 +rect 23 96 27 100 +rect 3 71 7 75 +rect 23 75 27 79 +rect 7 24 11 28 +rect 15 10 19 14 +<< metal1 >> +rect 5 192 10 196 +rect 5 189 8 192 +rect 32 181 33 185 +rect 13 169 16 177 +rect 13 165 15 169 +rect 4 148 8 163 +rect 12 157 15 161 +rect 12 156 16 157 +rect 12 148 16 152 +rect 4 132 8 144 +rect 20 142 24 144 +rect 30 142 33 181 +rect 20 138 33 142 +rect 20 132 24 138 +rect 12 122 16 125 +rect 13 114 17 118 +rect 5 104 9 107 +rect 21 104 25 107 +rect 5 101 25 104 +rect 5 89 9 101 +rect 21 100 25 101 +rect 21 96 23 100 +rect 25 82 26 90 +rect 4 64 7 71 +rect 27 64 31 79 +rect 3 51 7 57 +rect 3 48 15 51 +rect 11 45 15 48 +rect 27 45 31 60 +rect 3 35 7 38 +rect 19 35 23 38 +rect 7 31 19 35 +rect 0 24 7 28 +rect 11 24 36 28 +<< m2contact >> +rect 10 192 14 196 +rect 20 189 24 193 +rect 23 153 27 157 +rect 16 118 20 122 +rect 26 86 30 90 +rect 19 64 23 68 +rect 19 31 23 35 +rect 15 6 19 10 +<< metal2 >> +rect 10 196 14 202 +rect 20 193 24 202 +rect 20 177 24 189 +rect 15 0 19 6 +<< bb >> +rect 0 0 34 202 +<< labels >> +rlabel metal2 15 1 15 1 1 din +rlabel metal1 2 25 2 25 3 en +rlabel metal2 12 200 12 200 5 bl +rlabel metal2 22 200 22 200 5 br +rlabel m2contact 21 66 21 66 1 gnd +rlabel m2contact 28 88 28 88 1 gnd +rlabel m2contact 21 33 21 33 1 vdd +rlabel m2contact 18 120 18 120 1 vdd +rlabel m2contact 25 155 25 155 1 gnd +<< end >> diff --git a/technology/scn3me_subm/models/ff/nmos.sp b/technology/scn3me_subm/models/ff/nmos.sp new file mode 100644 index 00000000..9711c533 --- /dev/null +++ b/technology/scn3me_subm/models/ff/nmos.sp @@ -0,0 +1,10 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN3ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0) + diff --git a/technology/scn3me_subm/models/ff/pmos.sp b/technology/scn3me_subm/models/ff/pmos.sp new file mode 100644 index 00000000..e08967e4 --- /dev/null +++ b/technology/scn3me_subm/models/ff/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN3ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/nom/nmos.sp b/technology/scn3me_subm/models/nom/nmos.sp new file mode 100644 index 00000000..59f88cfd --- /dev/null +++ b/technology/scn3me_subm/models/nom/nmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN3ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/nom/pmos.sp b/technology/scn3me_subm/models/nom/pmos.sp new file mode 100644 index 00000000..69f3aacd --- /dev/null +++ b/technology/scn3me_subm/models/nom/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN3ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/ss/nmos.sp b/technology/scn3me_subm/models/ss/nmos.sp new file mode 100644 index 00000000..4e8a531f --- /dev/null +++ b/technology/scn3me_subm/models/ss/nmos.sp @@ -0,0 +1,10 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN3ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0) + diff --git a/technology/scn3me_subm/models/ss/pmos.sp b/technology/scn3me_subm/models/ss/pmos.sp new file mode 100644 index 00000000..e08967e4 --- /dev/null +++ b/technology/scn3me_subm/models/ss/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN3ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/sp_lib/cell_6t.sp b/technology/scn3me_subm/sp_lib/cell_6t.sp new file mode 100644 index 00000000..76c40f31 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/cell_6t.sp @@ -0,0 +1,10 @@ + +*********************** "cell_6t" ****************************** +.SUBCKT cell_6t bl br wl vdd gnd +M_1 Q Qb vdd vdd p W='0.9u' L=1.2u +M_2 Qb Q vdd vdd p W='0.9u' L=1.2u +M_3 br wl Qb gnd n W='1.2u' L=0.6u +M_4 bl wl Q gnd n W='1.2u' L=0.6u +M_5 Qb Q gnd gnd n W='2.4u' L=0.6u +M_6 Q Qb gnd gnd n W='2.4u' L=0.6u +.ENDS $ cell_6t diff --git a/technology/scn3me_subm/sp_lib/dff.sp b/technology/scn3me_subm/sp_lib/dff.sp new file mode 100644 index 00000000..d3fa7635 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/dff.sp @@ -0,0 +1,27 @@ +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd +M0 vdd clk a_2_6# vdd p w=12u l=0.6u +M1 a_17_74# D vdd vdd p w=6u l=0.6u +M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u +M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u +M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u +M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u +M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u +M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u +M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u +M9 vdd Q a_76_84# vdd p w=3u l=0.6u +M10 gnd clk a_2_6# gnd n w=6u l=0.6u +M11 Q a_66_6# vdd vdd p w=12u l=0.6u +M12 a_17_6# D gnd gnd n w=3u l=0.6u +M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u +M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u +M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u +M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u +M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u +M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u +M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u +M20 gnd Q a_76_6# gnd n w=3u l=0.6u +M21 Q a_66_6# gnd gnd n w=6u l=0.6u + +.ENDS dff diff --git a/technology/scn3me_subm/sp_lib/ms_flop.sp b/technology/scn3me_subm/sp_lib/ms_flop.sp new file mode 100644 index 00000000..abf664e7 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/ms_flop.sp @@ -0,0 +1,29 @@ +*master-slave flip-flop with both output and inverted ouput + +.subckt dlatch din dout dout_bar clk clk_bar vdd gnd +*clk inverter +mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1 +mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1 + +*transmission gate 1 +mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1 +mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1 + +*foward inverter +mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1 +mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1 + +*backward inverter +mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1 +mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1 + +*transmission gate 2 +mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1 +mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1 +.ends dlatch + +.subckt ms_flop din dout dout_bar clk vdd gnd +xmaster din mout mout_bar clk clk_bar vdd gnd dlatch +xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch +.ends flop + diff --git a/technology/scn3me_subm/sp_lib/replica_cell_6t.sp b/technology/scn3me_subm/sp_lib/replica_cell_6t.sp new file mode 100644 index 00000000..1fa75a55 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/replica_cell_6t.sp @@ -0,0 +1,10 @@ + +*********************** "cell_6t" ****************************** +.SUBCKT replica_cell_6t bl br wl vdd gnd +M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u +M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u +M_3 br wl net_2 gnd n W='1.2u' L=0.6u +M_4 bl wl gnd gnd n W='1.2u' L=0.6u +M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u +M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u +.ENDS $ replica_cell_6t diff --git a/technology/scn3me_subm/sp_lib/sense_amp.sp b/technology/scn3me_subm/sp_lib/sense_amp.sp new file mode 100644 index 00000000..1399228d --- /dev/null +++ b/technology/scn3me_subm/sp_lib/sense_amp.sp @@ -0,0 +1,12 @@ +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd +M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u +M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u +M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u +M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u +M_5 bl en dout vdd p W='7.2*1u' L=0.6u +M_6 br en net_1 vdd p W='7.2*1u' L=0.6u +M_7 net_2 en gnd gnd n W='2.7*1u' L=0.6u +.ENDS sense_amp + diff --git a/technology/scn3me_subm/sp_lib/tri_gate.sp b/technology/scn3me_subm/sp_lib/tri_gate.sp new file mode 100644 index 00000000..0d298172 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/tri_gate.sp @@ -0,0 +1,13 @@ +*********************** tri_gate ****************************** + +.SUBCKT tri_gate in out en en_bar vdd gnd + +M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u +M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u +M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u +M_4 out en net_2 gnd n W='1.2*1u' L=0.6u +M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u +M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u + + +.ENDS diff --git a/technology/scn3me_subm/sp_lib/write_driver.sp b/technology/scn3me_subm/sp_lib/write_driver.sp new file mode 100644 index 00000000..88f80361 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/write_driver.sp @@ -0,0 +1,38 @@ +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=1.2u L=0.6u +M_2 din_bar din vdd vdd p W=2.1u L=0.6u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=2.1u L=0.6u +M_4 net_7 din gnd gnd n W=2.1u L=0.6u +M_5 din_bar_gated en vdd vdd p W=2.1u L=0.6u +M_6 din_bar_gated din vdd vdd p W=2.1u L=0.6u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=2.1u L=0.6u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=1.2u L=0.6u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=2.1u L=0.6u +M_10 din_gated en net_8 gnd n W=2.1u L=0.6u +M_11 net_8 din_bar gnd gnd n W=2.1u L=0.6u +M_12 din_gated din_bar vdd vdd p W=2.1u L=0.6u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=2.1u L=0.6u +M_14 din_gated_bar din_gated gnd gnd n W=1.2u L=0.6u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar net_5 gnd n W=3.6u L=0.6u +M_16 br din_bar_gated_bar net_5 gnd n W=3.6u L=0.6u +M_17 net_5 en gnd gnd n W=3.6u L=0.6u + + + +.ENDS $ write_driver + diff --git a/technology/scn3me_subm/sue_lib/cell_6t.sue b/technology/scn3me_subm/sue_lib/cell_6t.sue new file mode 100644 index 00000000..427b1d05 --- /dev/null +++ b/technology/scn3me_subm/sue_lib/cell_6t.sue @@ -0,0 +1,46 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_cell_6t {} { + make inout -name BL -origin {190 360} + make inout -name BR -origin {830 360} + make input -name WL -origin {240 120} + make global -orient RXY -name vdd -origin {520 160} + make global -name gnd -origin {510 600} + make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} + make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} + make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} + make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} + make nmos -W 2.4u -L 0.6u -origin {630 490} + make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} + make_wire 630 550 630 530 + make_wire 400 530 400 550 + make_wire 400 190 400 170 + make_wire 630 170 630 190 + make_wire 400 360 400 270 + make_wire 310 360 400 360 + make_wire 630 360 630 450 + make_wire 630 360 700 360 + make_wire 270 300 270 120 + make_wire 270 120 740 120 + make_wire 740 120 740 300 + make_wire 230 360 190 360 + make_wire 780 360 830 360 + make_wire 510 550 400 550 + make_wire 510 550 630 550 + make_wire 510 550 510 600 + make_wire 520 170 400 170 + make_wire 520 170 630 170 + make_wire 520 160 520 170 + make_wire 240 120 270 120 + make_wire 460 290 630 290 + make_wire 460 290 460 490 + make_wire 460 290 460 230 + make_wire 630 290 630 360 + make_wire 630 290 630 270 + make_wire 570 420 400 420 + make_wire 570 420 570 490 + make_wire 570 420 570 230 + make_wire 400 420 400 360 + make_wire 400 420 400 450 +} + diff --git a/technology/scn3me_subm/sue_lib/ms_flop.sue b/technology/scn3me_subm/sue_lib/ms_flop.sue new file mode 100644 index 00000000..85cc8e03 --- /dev/null +++ b/technology/scn3me_subm/sue_lib/ms_flop.sue @@ -0,0 +1,84 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_ms_flop {} { + make pmos -orient R90X -W 1.8u -L 0.6u -origin {40 250} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {40 380} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {-270 540} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {310 310} + make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {430 730} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {190 670} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {190 780} + make input -name clk -origin {-380 540} + make input -name din -origin {-370 320} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {720 250} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {720 380} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {990 310} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {870 670} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {870 780} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {620 540} + make output -name dout -origin {1410 310} + make output -name dout_bar -origin {1430 930} + make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {1110 730} + make_wire -330 160 40 160 + make_wire 40 160 40 190 + make_wire -370 320 0 320 + make_wire 360 310 480 310 + make_wire 460 730 480 730 + make_wire 230 730 380 730 + make_wire 100 310 100 720 + make_wire 100 720 150 720 + make_wire 100 310 80 310 + make_wire 100 310 280 310 + make_wire 0 250 0 320 + make_wire 0 320 0 380 + make_wire 80 250 80 310 + make_wire 80 310 80 380 + make_wire 40 440 40 540 + make_wire -330 840 190 840 + make_wire 230 670 230 730 + make_wire 230 730 230 780 + make_wire 150 670 150 720 + make_wire 150 720 150 780 + make_wire 190 540 190 610 + make_wire -330 540 -330 840 + make_wire -220 540 40 540 + make_wire 40 540 190 540 + make_wire -380 540 -330 540 + make_wire -330 540 -300 540 + make_wire -330 540 -330 160 + make_wire 720 160 720 190 + make_wire 1140 730 1160 730 + make_wire 780 310 780 720 + make_wire 780 720 830 720 + make_wire 780 310 760 310 + make_wire 780 310 960 310 + make_wire 680 320 680 380 + make_wire 760 250 760 310 + make_wire 760 310 760 380 + make_wire 720 440 720 540 + make_wire 910 670 910 730 + make_wire 910 730 910 780 + make_wire 830 670 830 720 + make_wire 830 720 830 780 + make_wire 870 540 870 610 + make_wire 720 540 870 540 + make_wire 670 540 720 540 + make_wire 480 310 480 730 + make_wire 1160 310 1160 730 + make_wire 530 540 530 160 + make_wire 530 160 720 160 + make_wire 530 540 190 540 + make_wire 530 540 590 540 + make_wire 530 540 530 840 + make_wire 530 840 870 840 + make_wire 680 310 480 310 + make_wire 680 310 680 250 + make_wire 680 310 680 320 + make_wire 950 730 910 730 + make_wire 950 730 1060 730 + make_wire 1040 310 1160 310 + make_wire 1160 310 1410 310 + make_wire 950 930 1430 930 + make_wire 950 730 950 930 +} + diff --git a/technology/scn3me_subm/sue_lib/replica_cell_6t.sue b/technology/scn3me_subm/sue_lib/replica_cell_6t.sue new file mode 100644 index 00000000..56e72056 --- /dev/null +++ b/technology/scn3me_subm/sue_lib/replica_cell_6t.sue @@ -0,0 +1,49 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_replica_cell_6t {} { + make inout -name BL -origin {190 360} + make inout -name BR -origin {830 360} + make input -name WL -origin {240 120} + make global -orient RXY -name vdd -origin {520 160} + make global -name gnd -origin {510 600} + make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} + make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} + make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} + make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} + make nmos -W 2.4u -L 0.6u -origin {630 490} + make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} + make_wire 630 550 630 530 + make_wire 400 530 400 550 + make_wire 400 190 400 170 + make_wire 630 170 630 190 + make_wire 400 360 400 270 + make_wire 630 360 630 450 + make_wire 630 360 700 360 + make_wire 270 300 270 120 + make_wire 270 120 740 120 + make_wire 740 120 740 300 + make_wire 230 360 190 360 + make_wire 780 360 830 360 + make_wire 510 550 400 550 + make_wire 510 550 630 550 + make_wire 510 550 510 600 + make_wire 520 170 400 170 + make_wire 520 170 630 170 + make_wire 520 160 520 170 + make_wire 240 120 270 120 + make_wire 460 290 630 290 + make_wire 460 290 460 490 + make_wire 460 290 460 230 + make_wire 630 290 630 360 + make_wire 630 290 630 270 + make_wire 570 420 400 420 + make_wire 570 420 570 490 + make_wire 570 420 570 230 + make_wire 400 420 400 360 + make_wire 400 420 400 450 + make_wire 320 360 320 550 + make_wire 320 550 400 550 + make_wire 320 360 310 360 + make_wire 320 360 400 360 +} + diff --git a/technology/scn3me_subm/sue_lib/sense_amp.sue b/technology/scn3me_subm/sue_lib/sense_amp.sue new file mode 100644 index 00000000..4d29e11a --- /dev/null +++ b/technology/scn3me_subm/sue_lib/sense_amp.sue @@ -0,0 +1,52 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_sense_amp {} { + make inout -name BL -origin {260 10} + make global -orient RXY -name vdd -origin {490 170} + make global -name gnd -origin {480 660} + make input -name sclk -origin {180 610} + make nmos -W 3.9u -L 0.6u -origin {600 500} + make nmos -orient RX -W 3.9u -L 0.6u -origin {370 500} + make pmos -orient RY -W 3u -L 0.6u -origin {600 240} + make pmos -orient RXY -W 3u -L 0.6u -origin {370 240} + make nmos -W 3.9u -L 0.6u -origin {480 610} + make inout -name BR -origin {710 20} + make pmos -W 3.9u -L 0.6u -origin {710 90} + make pmos -orient RX -W 3.9u -L 0.6u -origin {260 90} + make output -orient RXY -name dout -origin {110 370} + make_wire 600 560 600 540 + make_wire 370 540 370 560 + make_wire 370 200 370 180 + make_wire 600 180 600 200 + make_wire 490 180 370 180 + make_wire 490 180 600 180 + make_wire 490 170 490 180 + make_wire 430 300 600 300 + make_wire 430 300 430 500 + make_wire 430 300 430 240 + make_wire 600 300 600 280 + make_wire 540 430 370 430 + make_wire 540 430 540 500 + make_wire 540 430 540 240 + make_wire 370 430 370 460 + make_wire 480 560 600 560 + make_wire 480 560 370 560 + make_wire 480 560 480 570 + make_wire 480 650 480 660 + make_wire 420 610 180 610 + make_wire 650 90 320 90 + make_wire 600 360 710 360 + make_wire 710 360 710 130 + make_wire 600 360 600 300 + make_wire 600 360 600 460 + make_wire 370 370 260 370 + make_wire 260 370 260 130 + make_wire 370 370 370 430 + make_wire 370 370 370 280 + make_wire 260 10 260 50 + make_wire 710 20 710 50 + make_wire 320 90 180 90 + make_wire 180 90 180 610 + make_wire 110 370 260 370 +} + diff --git a/technology/scn3me_subm/sue_lib/tri_gate.sue b/technology/scn3me_subm/sue_lib/tri_gate.sue new file mode 100644 index 00000000..d296171f --- /dev/null +++ b/technology/scn3me_subm/sue_lib/tri_gate.sue @@ -0,0 +1,37 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_tri_gate {} { + make global -orient RXY -name vdd -origin {630 150} + make global -name gnd -origin {630 570} + make input -name tri_in -origin {320 340} + make output -name tri_out -origin {690 360} + make input -name en -origin {570 410} + make input -name en_bar -origin {570 310} + make nmos -W 1.2u -L 0.6u -origin {630 490} + make nmos -W 1.2u -L 0.6u -origin {630 410} + make pmos -orient RY -W 2.4u -L 0.6u -origin {630 310} + make pmos -orient RY -W 2.4u -L 0.6u -origin {630 230} + make pmos -orient RY -W 2.4u -L 0.6u -origin {380 290} + make nmos -W 1.2u -L 0.6u -origin {380 400} + make_wire 570 490 470 490 + make_wire 470 230 570 230 + make_wire 630 550 380 550 + make_wire 380 550 380 440 + make_wire 630 550 630 570 + make_wire 630 550 630 530 + make_wire 630 170 380 170 + make_wire 380 170 380 250 + make_wire 630 170 630 190 + make_wire 630 170 630 150 + make_wire 320 340 320 400 + make_wire 320 340 320 290 + make_wire 380 340 470 340 + make_wire 380 340 380 330 + make_wire 380 340 380 360 + make_wire 470 340 470 490 + make_wire 470 340 470 230 + make_wire 630 360 630 350 + make_wire 630 360 630 370 + make_wire 630 360 690 360 +} + diff --git a/technology/scn3me_subm/sue_lib/write_driver.sue b/technology/scn3me_subm/sue_lib/write_driver.sue new file mode 100644 index 00000000..de3909a7 --- /dev/null +++ b/technology/scn3me_subm/sue_lib/write_driver.sue @@ -0,0 +1,44 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_write_driver {} { + make inout -name BL -origin {550 260} + make inout -name BR -origin {830 250} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {280 520} + make nand2 -WP 2.1u -WN 2.1u -origin {90 360} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {270 360} + make nmos -W 3.6u -L 0.6u -origin {830 410} + make nmos -W 3.6u -L 0.6u -origin {710 610} + make global -name gnd -origin {710 690} + make nand2 -WP 2.1u -WN 2.1u -origin {90 520} + make nmos -W 3.6u -L 0.6u -origin {550 410} + make input -name wen -origin {-290 340} + make input -name din -origin {-290 380} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {-80 540} + make_wire 160 360 240 360 + make_wire 830 250 830 370 + make_wire 550 260 550 370 + make_wire 550 450 550 560 + make_wire 550 560 710 560 + make_wire 710 560 710 570 + make_wire 710 560 830 560 + make_wire 830 560 830 450 + make_wire 710 650 710 690 + make_wire 250 520 160 520 + make_wire 770 410 770 520 + make_wire 770 520 330 520 + make_wire 320 360 490 360 + make_wire 490 360 490 410 + make_wire -180 380 -290 380 + make_wire -180 380 70 380 + make_wire -180 540 -110 540 + make_wire -180 380 -180 540 + make_wire -30 540 70 540 + make_wire 20 340 20 500 + make_wire 20 500 70 500 + make_wire 20 340 70 340 + make_wire -240 340 -240 610 + make_wire -240 610 650 610 + make_wire -240 340 20 340 + make_wire -240 340 -290 340 +} + diff --git a/technology/scn3me_subm/tech/README b/technology/scn3me_subm/tech/README new file mode 100644 index 00000000..0d923fcb --- /dev/null +++ b/technology/scn3me_subm/tech/README @@ -0,0 +1,10 @@ +The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following +license information: +--------------------------------------------------------------- +Tim Edwards +Open Circuit Design +v1.0 April 2013 +v1.1 May 2015 +v1.2 April 2017 +--------------------------------------------------------------- +GPL Copyright (c) 2017 diff --git a/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech b/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech new file mode 100644 index 00000000..be511001 --- /dev/null +++ b/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech @@ -0,0 +1,7891 @@ +tech + format 32 + scmos +end + +version + version 2002a + description "SCMOS: Submit as technology.lambda: SCN3ME_SUBM.30 [to process: AMIc5]" +end + +planes + well,w + implant,i + select,s + cap,c + active,a + metal1,m1 + metal2,m2 + metal3,m3 + oxide,ox + comment + xp + contact + via1,v1 + via2,v2 + fill +end + +types + well nwell,nw + well pwell,pw + implant n_field_implant,nfi + implant p_field_implant,pfi + select nselect,ns + select pselect,ps + cap electrode,poly2,el,p2 + cap electrodecontact,poly2contact,poly2c,p2c,elc + cap p2m12contact,p2m12c + cap electrodecap,ecap,poly2cap,p2cap,pcap + contact genericpoly2contact,gc2 + active ntransistor,nfet + active ptransistor,pfet + active diffusion,diff + active transistor,fet + active ndiffusion,ndif,green + active pdiffusion,pdif,brown + active ndcontact,ndc + active pdcontact,pdc + active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd + active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd + active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc + active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc + active polysilicon,red,poly,p + active polycontact,pcontact,polycut,pc + contact genericcontact,gcontact,gc + metal1 metal1,m1,blue + metal1 pseudo_rmetal1,prm1 + metal1 rmetal1,rm1 + metal1 fillm1,fm1 + metal1 m2contact,m2cut,m2c,via1,v1 + metal2 metal2,m2,purple + metal2 pseudo_rmetal2,prm2 + metal2 rmetal2,rm2 + metal2 fillm2,fm2 + via1 gv1 + metal2 m3contact,m3cut,m3c,via2,v2 + metal3 metal3,m3,cyan + metal3 pseudo_rmetal3,prm3 + metal3 rmetal3,rm3 + metal3 fillm3,fm3 + via2 gv2 + metal3 pad + oxide glass + cap high_resist,hr + cap poly2_high_resist,phr + active pseudo_rpoly,prp + active rpoly,rp + cap pseudo_rpoly2,prp2 + cap rpoly2,rp2 + active pseudo_rndiffusion,prnd + active rndiffusion,rndiff,rnd + active pseudo_rpdiffusion,prpd + active rpdiffusion,rpdiff,rpd + active pseudo_rnwell,prnwell,prnw + active rnwell,rnw + implant filln,fn + fill filla,fa + fill fillb,fb + active fillp,fp + active fillapm,fapm + xp xp + xp m1p + xp m2p + xp m3p + comment comment + comment bb +end + +contact + pc poly metal1 + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + psc psd metal1 + m2c metal1 metal2 + m3c metal2 metal3 + stackable pc m2c pm12contact,pm12c + stackable pdc m2c pdm12contact,pdm12c + stackable psc m2c psm12contact,psm12c,pom12c,pwm12c + stackable ndc m2c ndm12contact,ndm12c + stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c + stackable m2c m3c m123contact,m123c +end + +styles + styletype mos + nwell 12 + pwell 13 + nfi 53 + pfi 54 + nselect 43 + pselect 44 + diff 25 + tran 2 4 + ndiff 2 + pdiff 4 + nsd 3 + psd 5 + nfet 6 7 + pfet 8 9 + ndc 2 20 32 + pdc 4 20 32 + nsc 3 20 32 + psc 5 20 32 + poly 1 + pcontact 1 20 32 + gc 32 + metal1 20 + rm1 20 48 + prm1 48 + m1p 20 34 + fm1 20 34 + fp 1 34 + fa 32 + fb 45 34 + fn 45 34 + fapm 1 20 21 34 + gv1 55 + m2contact 20 21 55 + p2m12contact 14 20 21 32 55 + metal2 21 + rm2 21 48 + prm2 48 + m2p 21 34 + fm2 21 34 + gv2 56 + m3contact 21 22 56 + metal3 22 + rm3 22 48 + prm3 48 + m3p 22 34 + fm3 22 34 + pad 22 23 34 38 + glass 34 + xp 25 34 + ecap 10 14 + poly2 14 + p2c 14 20 32 + gc2 19 + hr 10 + phr 14 48 + rp 47 48 + prp 48 + rp2 14 48 + prp2 48 + rnd 2 48 + prnd 48 + rpd 4 53 + prpd 53 + rnw 12 53 + prnw 54 + comment 45 + bb 32 + error_p 42 + error_s 42 + error_ps 42 + magnet 54 + rotate 57 + fence 59 +end + +compose + compose nfet poly ndiff + compose pfet poly pdiff + paint diff nselect ndiff + paint diff pselect pdiff + compose tran poly diff + paint tran nselect nfet + paint tran pselect pfet + paint psd ns ndiff + paint nsd ps pdiff + paint ndiff ps psd + paint pdiff ns nsd + paint pad m1 pad + paint pad m2 pad + paint pad m2c pad + paint pfi nwell nfi + paint nfi pwell pfi + paint ndc nwell pdc + paint nfet nwell pfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint pdc pwell ndc + paint pfet pwell nfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint poly2 poly ecap + erase ecap poly poly2 + paint p2c poly2 p2c + paint p2c ecap p2c + paint p2m12c poly2 p2m12c + paint p2m12c ecap p2m12c + paint pad m3 pad + compose phr poly2 hr + paint hr poly2 phr + paint poly2 hr phr + erase phr hr poly2 +#CRE/CRM + compose rm1 prm1 m1 + compose rm2 prm2 m2 + compose rm3 prm3 m3 + compose rp prp poly + compose rp2 prp2 poly2 + compose rnd prnd ndiff + compose rpd prpd pdiff + paint nwell rnw space + paint nwell prnw space + paint poly fp fp + paint m1 fm1 fm1 + paint m2 fm2 fm2 + paint m3 fm3 fm3 +end + +connect + nwell,nsc/a,nsd nwell,nsc/a,nsd + pwell,psc/a,psd pwell,psc/a,psd + m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 + m3,fm3,fapm,m3c/m3 m3,fm3,fapm,m3c/m3 + ndiff,ndc/a,pdiff,pdc/a ndiff,ndc/a,pdiff,pdc/a + poly,fp,nfet,pfet,fet,fapm,pc/a poly,fp,nfet,pfet,fet,fapm,pc/a + gc2 poly2,ecap,metal1 + p2c poly2,ecap,m1,fm1,fapm,m2c/m1 + p2m12c poly2,ecap,m1,fm1,fapm,m2c/m1,m2,fm2,fapm,m2c/m2,m3c/m2 + poly2,ecap,p2c,p2m12c poly2,ecap,p2c,p2m12c + gc2 poly2,ecap,m1,fm1,fapm,m2c/m1 + gc poly,fp,ndiff,pdiff,nsd,psd,m1,fm1,fapm,m2c/m1 + gv1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2,fm2,fapm,m3c/m2 + gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm + pad m1,fm1,m2,fm2,m3,fm3 + rm1 prm1 + rm2 prm2 + rm3 prm3 + rnw prnw + rp prp + rp2 prp2 + rnd prnd + rpd prpd + phr hr +end + +cifoutput + +style lambda=0.30(p) + scalefactor 30 15 + + # This is a custom section to add bounding boxes in OpenRAM + layer BB bb + labels bb + calma 63 0 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + layer CWP pwell + bloat-or ndiff,rnd,ndc/a,nfet * 180 + bloat-or psd,psc/a * 90 + bloat-or pfi * 120 + grow 90 + shrink 90 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCA ndc/m1,nsc/m1 + squares 30 60 90 + calma 48 0 + + layer CCA pdc/m1,psc/m1 + squares 30 60 90 + calma 48 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCP pc/m1 + squares 30 60 90 + calma 47 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCE p2c,p2m12c + squares 30 60 90 + calma 55 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +style fill-only + scalefactor 30 15 + + layer 100 fp + calma 100 0 + + layer 101 fm1 + calma 101 0 + + layer 102 fm2 + calma 102 0 + + layer 103 fm3 + calma 103 0 + + layer 109 fa + or fb + calma 109 0 + + layer 119 fn + calma 119 0 + +style fapm-boxes + +# this output style creates fill boxes automatically (to meet minimum +# density requirements for poly and metal layers) 5 microns outside of +# drawn layout IF: 1. you have a flattened version of your chip +# 2. over which you paint the special fill layer 'fa', preferably with +# a size that is a multiple of 7 + n * (7 + 4), 3. set 'cif +# ostype fapm-boxes' and cif out to a file (this actually creates the +# fill boxes on cif/strm layer '110' using the magic 'squares' +# command), 4. cif in the resulting file (which creates boxes on magic +# layer 'fapm') and place this cell onto your chip (and verify absence +# of drc errors or shorts), then 5. cif out under your regular cif out +# style, where the 'fapm' layer creates fill boxes on poly and all +# metal layers. + + scalefactor 30 15 + + templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c + or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + or fm3,m3,rm3,m3c/m3 + or glass,pad + grow 510 + and fa + + layer 110 fa + squares 0 210 120 + and-not CRIT + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + +style fapm-stripes + scalefactor 30 15 + +# this output style creates the above layer 110 as stripes for reduced size +# HOWEVER it requires each 'fa' box to first be an exact multiple as above +# and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box +# to be a 1-lambda wide layer 'fb' box -- else you won't get strips! + + templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c + or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + or fm3,m3,rm3,m3c/m3 + or glass,pad + grow 510 + and fa + + templayer FB fa + or fb + squares 0 210 120 + and-not CRIT + + layer 110 fa + squares 0 210 120 + and-not CRIT + or FB + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + + +style lambda=0.30(cp) + scalefactor 30 15 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + layer CWP pwell + bloat-or ndiff,rnd,ndc/a,nfet * 180 + bloat-or psd,psc/a * 90 + bloat-or pfi * 120 + grow 90 + shrink 90 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCC ndc/m1,nsc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC pdc/m1,psc/m1 + squares 30 60 90 + calma 25 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCC pc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC p2c,p2m12c + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.30(c) + scalefactor 30 15 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCC ndc/m1,nsc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC pdc/m1,psc/m1 + squares 30 60 90 + calma 25 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCC pc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC p2c,p2m12c + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.30() + scalefactor 30 15 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCA ndc/m1,nsc/m1 + squares 30 60 90 + calma 48 0 + + layer CCA pdc/m1,psc/m1 + squares 30 60 90 + calma 48 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCP pc/m1 + squares 30 60 90 + calma 47 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCE p2c,p2m12c + squares 30 60 90 + calma 55 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +end + +cifinput + +style lambda=0.30(p) + scalefactor 30 + + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma 63 0 + +layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(s) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(ps) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN 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+ and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30() + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(c) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(cs) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(cps) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(cp) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + +style fill-only + scalefactor 30 +# scalefactor 100 + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + or fb + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + +end + +mzrouter + style irouter +# layer hCost vCost jogCost hintCost + layer metal3 1 2 2 1 + layer metal2 2 1 2 1 + layer metal1 2 3 2 1 + layer poly 10 10 11 1 + contact m3contact metal3 metal2 5 + contact m2contact metal2 metal1 6 + contact pcontact metal1 poly 7 + notactive poly pcontact + +style garouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + contact m2contact metal1 metal2 1024 + +end + +drc + width nwell 12 \ + "N-well width < 12 (Mosis #1.1)" + + width rnw 12 \ + "rnwell (for resistor L/W extraction) width < 12 (Mosis #1.1)" + + width pwell 12 \ + "P-well width < 12 (Mosis #1.1)" + + width diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 \ + "Diffusion width < 3 (Mosis #2.1)" + + width poly,fp,rp,pc/a,nfet,pfet,fet 2 \ + "Poly width < 2 (Mosis #3.1)" + + width nselect 2 \ + "N-Select width < 2 (Mosis #4.4)" + + width pselect 2 \ + "P-Select width < 2 (Mosis #4.4)" + + width pc/m1 4 \ + "Poly contact width < 4 (Mosis #5.1)" + + + width gc 2 \ + "GC contact width < 2 (Mosis #6.1)" + + width ndc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width nsc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width pdc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width psc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 \ + "Metal1 width < 3 (Mosis #7.1)" + + width gv1 2 \ + "GV1 via width < 2 (Mosis #8.1)" + + width m2c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + + + + + + + width p2m12c 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width p2m12c 4 \ + "stacked p2m12c width < 4 (Mosis #8.1)" + + width m2,fm2,rm2,m2c/m2,m3c/m2 3 \ + "Metal2 width < 3 (Mosis #9.1)" + + width poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c 5 \ + "Poly2 width < 5 (Mosis #11.1)" + + width gc2 2 \ + "Generic contact2 width < 2 (Mosis #13.1)" + + width p2c 4 \ + "Poly2 contact width < 4 (Mosis #13.1)" + + width p2m12c 4 \ + "Poly2 contact width < 4 (Mosis #13.1)" + + width gv2 2 \ + "GV2 via width < 2 (Mosis #14.1)" + + width m3c/m2 4 \ + "Metal3 contact width < 4 (Mosis #14.1)" + + + width m3,fm3,rm3,m3c/m3,pad 5 \ + "Metal3 width < 5 (Mosis #15.1)" + + width hr,phr 4 \ + "High-Resist width < 4 (Mosis #27.1)" + + width phr 5 \ + "High-Resist poly2R width < 5 (Mosis #27.7)" + + width nfi,pfi 4 \ + "N/P_field-implant width < 4 (Mosis #29.1)" + + spacing nwell nwell 6 touching_ok \ + "N-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing pwell pwell 6 touching_ok \ + "P-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing rnw nwell 18 touching_illegal \ + "rnw (for resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" + + edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ + "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active + + spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 touching_ok \ + "Diffusion spacing < 3 (Mosis #2.2)" + + spacing nwell ndiff,rnd,nfet,ndc/a 6 touching_illegal \ + "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" + + spacing pwell pdiff,rpd,pfet,pdc/a 6 touching_illegal \ + "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" + + spacing ndiff,rnd,nfet,ndc/a pdiff,rpd,pfet,pdc/a 12 touching_illegal \ + "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" + + edge4way ~(nwell)/well nwell 6 ~(pdiff,rpd,pfet,pdc/a)/active nwell 6 \ + "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 6 ~(ndiff,rnd,nfet,ndc/a)/active pwell 6 \ + "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(nwell)/well nwell 3 ~(nsd,nsc/a)/active nwell 3 \ + "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 3 ~(psd,psc/a)/active pwell 3 \ + "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active + + spacing ndiff,rnd,ndc/a nsd,nsc/a 9 touching_illegal \ + "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing pdiff,rpd,pdc/a psd,psc/a 9 touching_illegal \ + "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing nwell psd,psc/a 3 touching_illegal \ + "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" + + spacing pwell nsd,nsc/a 3 touching_illegal \ + "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" + + spacing psd,psc/a rnw,prnw 3 touching_illegal \ + "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" + + spacing nsd,nsc/a psd,psc/a 6 touching_illegal \ + "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" + + spacing ndiff,rnd,nfet,ndc/a,nfet psd,psc/a 4 touching_ok \ + "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" + + spacing pdiff,rpd,pfet,pdc/a,pfet nsd,nsc/a 4 touching_ok \ + "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" + + spacing poly,rp,pc/a,nfet,pfet,fet poly,rp,pc/a,nfet,pfet,fet 3 touching_ok \ + "Poly spacing < 3 (Mosis #3.2)" + + spacing poly,rp,pc/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ + "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" + + spacing fp fp 4 touching_ok \ + "Poly fill layer (fp) spacing < 4 (Mosis #0)" + + edge4way nfet,pfet,fet space/active,poly,fp,rp,pc/a 2 poly,fp,rp,pc/a 0 0 \ + "Poly overhang of Transistor < 2 (Mosis #3.3)" active + + edge4way nfet,pfet,fet space/active,ndiff,rnd,ndc/a,pdiff,rpd,pdc/a 3 ndiff,rnd,ndc/a,pdiff,rpd,pdc/a,nfet,pfet,fet 0 0 \ + "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active + + edge4way poly,fp,rp,pc/a ~(poly,fp,rp,pc/a,nfet,pfet,fet,prp)/active 1 space space 1 \ + "Poly spacing to Diffusion < 1 (Mosis #3.5)" + + edge4way nfet ~(nfet)/active 3 ~(pselect)/select ~(nfet)/active 3 \ + "N-Transistor space to P-Select < 3 (Mosis #4.1)" select + + edge4way pfet ~(pfet)/active 3 ~(nselect)/select ~(pfet)/active 3 \ + "P-Transistor space to N-Select < 3 (Mosis #4.1)" select + + edge4way nfet ~(nfet)/active 3 ~(psd,psc/a)/active ~(nfet)/active 2 \ + "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active + + edge4way pfet ~(pfet)/active 3 ~(nsd,nsc/a)/active ~(pfet)/active 2 \ + "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active + +#PEZ edge4way psd,psc/a space ~(nfet)/active space \ +#PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active + +#PEZ edge4way nsd,nsc/a space ~(pfet)/active space \ +#PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active + + edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active nselect,pselect 2 \ + "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active + + edge4way space nselect,pselect 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active + + edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active + + edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active space,nselect,pselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active + + edge4way space nselect,pselect 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active + + edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active + + edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active space,nselect,pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active + + edge4way diff space 2 nselect space 2 \ + "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way diff space 2 pselect space 2 \ + "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way ndiff,rnd,nfet,ndc/a space 2 ~(pselect)/select space 2 \ + "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select + + edge4way pdiff,rpd,pfet,pdc/a space 2 ~(nselect)/select space 2 \ + "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select + + edge4way ~(pdiff,rpd,pfet,pdc/a,psd,psc/a)/active pdiff,rpd,pfet,pdc/a,psd,psc/a 1 ~(nselect)/select 0 0 \ + "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select + + edge4way ~(ndiff,rnd,nfet,ndc/a,nsd,nsc/a)/active ndiff,rnd,nfet,ndc/a,nsd,nsc/a 1 ~(pselect)/select 0 0 \ + "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select + + width nsd,nsc/a,psd,psc/a 2 \ + "N-Ohmic,P-Ohmic width < 2 (Mosis #4.1)" + + spacing nselect nselect 2 touching_ok \ + "N-Select spacing < 2 (Mosis #4.4)" + + spacing pselect pselect 2 touching_ok \ + "P-Select spacing < 2 (Mosis #4.4)" + + edge4way ndiff,rnd,ndc/a psd,psc/a 2 ~(ndiff,rnd,ndc/a)/active 0 0 \ + "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" + + edge4way pdiff,rpd,pdc/a nsd,nsc/a 2 ~(pdiff,rpd,pdc/a)/active 0 0 \ + "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" + + edge4way gc ~(gc)/contact 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a ~(gc)/contact 1 \ + "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active + + edge4way gc space 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a space 1 \ + "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active + + edge4way ~(poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 1 ~(gc)/contact 0 0 \ + "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact + + spacing gc gc 3 touching_ok \ + "Generic contact spacing < 3 (Mosis #5.3)" + + edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ + "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 + + edge4way ~(gc2)/contact gc2 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ + "Generic contact2 cannot touch Metal1 contacts (Mosis #0)" metal1 + + spacing gv1 m2c/m2 2 touching_illegal \ + "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" + + spacing poly,fp,rp,pc/a pc/a 4 touching_ok \ + "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" + + edge4way gc ~(gc)/contact 1 diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,poly,fp,rp,pc/a ~(gc)/contact 1 \ + "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active + + spacing gc pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ + "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" + + spacing nsc/m1 pdc/m1 1 touching_illegal \ + "nsc spacing to pdc < 1 (Mosis #6.3)" + + spacing psc/m1 ndc/m1 1 touching_illegal \ + "psc spacing to ndc < 1 (Mosis #6.3)" + + + + + + + + spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 1 touching_illegal \ + "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" + + spacing nfet,pfet gc 2 touching_illegal \ + "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" + + spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a pc/a 1 touching_illegal \ + "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" + + spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 4 touching_ok \ + "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" + + spacing pc/a ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ + "pc/a,pm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a < 2 (Mosis #6.7)" + + spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 touching_ok \ + "Metal1 spacing < 3 (Mosis #7.2)" + + spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 fm1,fapm 3 touching_illegal \ + "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" + + spacing fm1 fm1 4 touching_ok \ + "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" + + edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ + "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact + + spacing gv1 gv1 3 touching_ok \ + "GV1 via spacing < 3 (Mosis #8.2)" + + edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 ~(gv1)/via1 1 \ + "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 + + edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ + "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 + + spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 3 touching_ok \ + "Metal2 spacing < 3 (Mosis #9.2)" + + spacing m2,rm2,m2c/m2,m3c/m2 fm2,fapm 3 touching_illegal \ + "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" + + spacing fm2 fm2 4 touching_ok \ + "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" + + edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ + "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv1)/via1 0 0 \ + "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 + + width glass 10 \ + "COG width < 10 (Mosis #10.2)" + + edge4way ~(pad)/metal3 pad 20 ~(glass)/oxide pad 20 \ + "pad overlap of COG < 20 (Mosis #10.3)" oxide + + spacing ecap ecap 3 touching_ok \ + "Ecap spacing < 3 (Mosis #11.2)" + + edge4way ecap ~(ecap)/cap 5 poly,fp,rp,pc/a ~(ecap)/cap 5 \ + "Poly overlap of Ecap < 5 (Mosis #11.3)" active + + edge4way ~(ecap)/cap ecap 1 poly,fp,rp,pc/a 0 0 \ + "Ecap must touch Poly (Mosis #11.3x)" active + + edge4way poly2,phr,p2c,p2m12c space 5 ~(poly,fp,rp,pc/a)/active space 5 \ + "Poly2 spacing to Poly < 5 (Mosis #11.3c)" active + + spacing ecap pc/a 2 touching_illegal \ + "Ecap spacing to Poly contact < 2 (Mosis #11.5)" + + spacing ecap gc 3 touching_illegal \ + "Ecap spacing to Generic contact < 3 (Mosis #11.5)" + + spacing poly2,ecap,phr,p2c,p2m12c poly2,ecap,phr,p2c,p2m12c 3 touching_ok \ + "Poly2 spacing < 3 (Mosis #11.2)" + + spacing poly2,ecap,phr,p2c,p2m12c pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ + "Poly2 spacing to Poly contact,Diffusion contact < 2 (Mosis #11.5)" + + spacing poly2,ecap,phr,p2c,p2m12c gc,gc 3 touching_illegal \ + "Poly2 spacing to GC contact < 3 (Mosis #11.5)" + + spacing gc2 gc2 3 touching_ok \ + "Generic contact2 spacing < 3 (Mosis #13.2)" + + edge4way ~(ecap)/cap ecap 3 ~(gc2)/contact ecap 3 \ + "Ecap overlap of Generic contact2 < 3 (Mosis #13.3)" contact + + edge4way ~(ecap)/cap ecap 2 ~(p2c,p2m12c)/cap ecap 2 \ + "Ecap overlap of Poly2 contact < 2 (Mosis #13.3)" cap + + edge4way gc2 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap Generic contact2 by 1 (Mosis #13.4)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc2)/contact 0 0 \ + "Metal1(edge) cannot touch Generic contact2 (Mosis #13.4)" contact + + edge4way ~(poly2,ecap,phr,p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 ~(p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 \ + "Poly2 overlap of Poly2 contact < 1 (Mosis #13.4)" cap + + spacing gv2 gv2 3 touching_ok \ + "GV2 via spacing < 3 (Mosis #14.2)" + + spacing gv2 m3c/m2 2 touching_illegal \ + "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" + + edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ + "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ + "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 + + spacing m3,rm3,m3c/m3,pad m3,rm3,m3c/m3,pad 3 touching_ok \ + "Metal3 spacing < 3 (Mosis #15.2)" + + spacing m3,rm3,m3c/m3,pad fm3,fapm 3 touching_illegal \ + "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" + + spacing fm3 fm3 4 touching_ok \ + "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" + + edge4way m3c/m2 ~(m3c/m2)/metal2 1 m3,fm3,rm3,m3c/m3,pad ~(m3c/m2)/metal2 1 \ + "Metal3 overlap of Metal3 contact < 1 (Mosis #15.3)" metal3 + + edge4way gv2 space 2 m3,fm3,rm3,m3c/m3,pad space 2 \ + "Metal3 must overlap GV2 via by 2 (Mosis #15.3)" metal3 + + edge4way ~(m3,fm3,rm3,m3c/m3,pad)/metal3 m3,fm3,rm3,m3c/m3,pad 1 ~(gv2)/via2 0 0 \ + "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 + + spacing hr,phr hr,phr 4 touching_ok \ + "High-Resist spacing < 4 (Mosis #27.2)" + + spacing hr,phr,phr p2c,p2m12c 2 touching_illegal \ + "High-Resist spacing to Poly2 contact < 2 (Mosis #27.3)" + + spacing hr,phr,phr gc 2 touching_illegal \ + "High-Resist spacing to GC contact < 2 (Mosis #27.3)" + + edge4way hr,phr space 2 ~(ndiff,rnd,ndc/a,pdiff,rpd,pdc/a)/active 0 2 \ + "High-Resist space to Diffusion < 2 (Mosis #27.4)" active + + spacing hr,phr,phr poly2,ecap,phr,p2c,p2m12c 2 touching_ok \ + "High-Resist spacing to other Poly2 < 2 (Mosis #27.5)" + + edge4way hr,phr space 2 ~(poly2,ecap,phr,p2c,p2m12c)/contact hr,phr 2 \ + "High-Resist space to Poly2 < 2 (Mosis #27.5x)" contact + + spacing nwell phr 4 touching_illegal \ + "N-well spacing to Silicide-Block poly2R < 4 (Mosis #27.6)" + + spacing phr phr 7 touching_ok \ + "High-Resist poly2R spacing < 7 (Mosis #27.13)" + + edge4way phr space/active,hr 2 hr hr 2 \ + "High-Resist overlap of High-Resist poly2R < 2 (Mosis #27.15)" + + spacing nfi nfi 4 touching_ok \ + "N_field-implant spacing < 4 (Mosis #35.2)" + + spacing pfi pfi 4 touching_ok \ + "P_field-implant spacing < 4 (Mosis #35.2)" + + spacing nfi pfi 4 touching_illegal \ + "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" + + spacing nwell,pdiff,rpd,pfet,pdc/a pfi 4 touching_illegal \ + "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" + + spacing pwell,ndiff,rnd,nfet,ndc/a nfi 4 touching_illegal \ + "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" + + edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ + "N-well overlap of N_field-implant < 4 (Mosis #21.2)" implant + + edge4way ~(pwell)/well pwell 4 ~(pfi)/implant pwell 4 \ + "P-well overlap of P_field-implant < 4 (Mosis #21.2)" implant + + spacing fa fapm 4 touching_illegal \ + "fill layer fa spacing to fill layer fapm < 4 (Mosis #0)" + + width fa 7 \ + "filla width < 7 (Mosis #0)" + + width fapm 7 \ + "fillapm width < 7 (Mosis #0)" + + width fp 7 \ + "fillp width < 7 (Mosis #0)" + + width fm1 7 \ + "fillm1 width < 7 (Mosis #0)" + + width fm2 7 \ + "fillm2 width < 7 (Mosis #0)" + + width fm3 7 \ + "fillm3 width < 7 (Mosis #0)" + + edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ + "Contact not rectangular (Magic rule)" + + edge4way rp space/active 1 prp 0 0 \ + "prp overhang of rpoly (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rp2 space/cap 1 prp2 0 0 \ + "prp2 overhang of rpoly2 (for resistor L/W extraction) < 1 (Mosis #0)" cap + + edge4way rnw space/active 1 prnw 0 0 \ + "prnw overhang of rnwell (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rpd space/active 1 prpd 0 0 \ + "prpd overhang of rpdiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rnd space/active 1 prnd 0 0 \ + "prnd overhang of rndiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rm1 space/metal1 1 prm1 0 0 \ + "prm1 overhang of rmetal1 (for resistor L/W extraction) < 1 (Mosis #0)" metal1 + + edge4way rm2 space/metal2 1 prm2 0 0 \ + "prm2 overhang of rmetal2 (for resistor L/W extraction) < 1 (Mosis #0)" metal2 + + edge4way rm3 space/metal3 1 prm3 0 0 \ + "prm3 overhang of rmetal3 (for resistor L/W extraction) < 1 (Mosis #0)" metal3 + + edge4way ndc/a,nsc/a ~(ndc/a,nsc/a)/active 1 ~(ndc/a,nsc/a)/active (~(ndc/a,nsc/a),ndc/a,nsc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pdc/a,psc/a ~(pdc/a,psc/a)/active 1 ~(pdc/a,psc/a)/active (~(pdc/a,psc/a),pdc/a,psc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pc/a ~(pc/a)/active 1 ~(pc/a)/active (~(pc/a),pc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gc2 ~(gc2)/contact 1 ~(gc2)/contact (~(gc2),gc2)/contact 1 \ + "Contact not rectangular (Magic rule)" + + edge4way p2c,p2m12c ~(p2c,p2m12c)/cap 1 ~(p2c,p2m12c)/cap (~(p2c,p2m12c),p2c,p2m12c)/cap 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m2c/m1 ~(m2c/m1)/metal1 1 ~(m2c/m1)/metal1 (~(m2c/m1),m2c/m1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m3c/m2 ~(m3c/m2)/metal2 1 ~(m3c/m2)/metal2 (~(m3c/m2),m3c/m2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,gc,pc/a,gc + + exact_overlap gc2,p2c,p2m12c + + edge4way pad ~(pad)/m3 1 ~(pad)/m3 (~(pad),pad)/m3 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1 + + exact_overlap m2c/m2 + + exact_overlap m3c/m3 + + exact_overlap gv1 + + exact_overlap gv2 + + + width m1p 4 \ + "Metal1 PIN width < 4 (do_pins)" + + spacing m1p m1p 4 touching_ok \ + "Metal1 PIN spacing < 4 (do_pins)" + + width m2p 4 \ + "Metal2 PIN width < 4 (do_pins)" + + spacing m2p m2p 4 touching_ok \ + "Metal2 PIN spacing < 4 (do_pins)" + + width m3p 6 \ + "Metal3 PIN width < 6 (do_pins)" + + spacing m3p m3p 4 touching_ok \ + "Metal3 PIN spacing < 4 (do_pins)" + +#CC cifstyle lambda=0.30(p) +#CC cifwidth CWN 360 \ +#CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" +#CC cifspacing CWN CWN 180 touching_ok \ +#CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" +#CC cifwidth CWP 360 \ +#CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" +#CC cifspacing CWP CWP 180 touching_ok \ +#CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" +#CC cifwidth CSN 60 \ +#CC "generated CIF layer CSN width will be < 2 (';cif see CSN')" +#CC cifspacing CSN CSN 60 touching_ok \ +#CC "generated CIF layer CSN spacing will be < 2 (';cif see CSN')" +#CC cifwidth CSP 60 \ +#CC "generated CIF layer CSP width will be < 2 (';cif see CSP')" +#CC cifspacing CSP CSP 60 touching_ok \ +#CC "generated CIF layer CSP spacing will be < 2 (';cif see CSP')" + + stepsize 400 + +end + +#--------------------------------------------------- +# LEF format definitions +#--------------------------------------------------- + +lef + +ignore PC +ignore CA + +routing m1 M1 m1 met1 +routing m2 M2 m2 met2 +routing m3 M3 m3 met3 + +contact m2c via via1 V1 v1 +contact m3c via2 V2 v2 + +end + +extract + style AMI0.5um(amic5)from:T24H + cscale 1 + lambda 30 + step 100 + sidehalo 8 + planeorder well 0 + planeorder implant 1 + planeorder select 2 + planeorder cap 3 + planeorder active 4 + planeorder metal1 5 + planeorder metal2 6 + planeorder metal3 7 + planeorder oxide 8 + planeorder xp 9 + planeorder comment 10 + planeorder contact 11 + planeorder via1 12 + planeorder via2 13 + planeorder fill 14 + + resist (ndiff,rnd,ndc,nsd,nsc)/active 82200 + resist (pdiff,rpd,pdc,psd,psc)/active 105200 + resist (nwell)/well 808000 + resist (rnw)/active 808000 + resist (pwell)/well 1 + resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 22000 + resist (poly2,ecap,p2c,p2m12c,p2c,p2m12c)/cap 40300 + resist (phr)/cap 40300 + resist (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c,m2c)/metal1 90 + resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 90 + resist (m3,fm3,rm3,m3c,pad)/metal3 50 + + contact ndc 4 62700 + contact pdc 4 160000 + contact pc 4 15600 + contact p2c 4 26100 + contact m2c 4 910 + contact m3c 4 830 + + +#poly2 + overlap (poly,fp,rp,pc,pc)/active (poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c)/cap 84.960 + +#nwell,cwell,pwell + areacap (nwell)/well 3.600 + +#rnw + areacap (rnw)/active 3.600 + +#ndiff +# MODEL HANDLES THIS: areacap (ndiff,ndc)/active 38.430 +# MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 38.430 +# MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 94.800 +# MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 94.800 + + areacap (rnd)/active 38.430 + overlap (rnd)/active ~space/w 38.430 + perimc (rnd)/active ~(rnd)/active 94.800 + sideoverlap (rnd)/active ~(rnd)/active ~space/w 94.800 + +#pdiff +# MODEL HANDLES THIS: areacap (pdiff,pdc)/active 65.880 +# MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 65.880 +# MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 75.300 +# MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 75.300 + + areacap (rpd)/active 65.880 + overlap (rpd)/active ~space/w 65.880 + perimc (rpd)/active ~(rpd)/active 75.300 + sideoverlap (rpd)/active ~(rpd)/active ~space/w 75.300 + +#rnw + +#poly +# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,rnd,ndc)/active 221.670 +# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,rnd,ndc)/active 58.500 +# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,rpd,pdc)/active 213.480 +# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,rpd,pdc)/active 82.800 + + areacap (poly,fp,rp,pc)/active 7.740 + overlap (poly,fp,rp,pc)/active ~space/w 7.740 + +#poly2 + +#rnw + +#metal1 + areacap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 2.700 + +#metal1-sub blocked by ~space/a,~space/c + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.700 ~space/a,~space/c + perimc (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 20.700 + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 20.700 ~space/a,~space/c + +#rnw + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 2.700 ~space/c + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 20.700 ~space/c + +#metal1-diff blocked by ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 3.150 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 20.700 ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 3.150 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 20.700 ~space/c + +#metal1-poly blocked by ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 4.590 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 15.900 ~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 15.900 ~space/c + +#metal1-poly2 not blocked + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly2,ecap,phr,p2c,p2m12c)/cap 3.960 + +#metal2 + areacap (m2,fm2,rm2,m3c)/metal2 1.350 + +#metal2-sub blocked by + overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 1.350 ~space/a,~space/m1,~space/c + perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 15.900 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 15.900 ~space/a,~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 rnw/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw/active 15.900 ~space/m1,~space/c + +#metal2-*diff blocked by ~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,rnd,ndc)/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,rnd,ndc)/active 15.900 ~space/m1,~space/c + overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 15.900 ~space/m1,~space/c + +#metal2-poly blocked by ~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 10.800 ~space/m1,~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 10.800 ~space/m1,~space/c + +#metal2-poly2 blocked by ~space/m1 + +#M2->M1 + overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 2.520 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 14.700 + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 14.700 + +#metal3 + areacap (m3,fm3,rm3,pad)/metal3 0.900 + +#metal3-sub blocked by ~space/a,~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 ~space/w 0.900 ~space/a,~space/m1,~space/m2,~space/c + perimc (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 10.500 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 ~space/w 10.500 ~space/a,~space/m1,~space/m2,~space/c + +#rnw + overlap (m3,fm3,rm3,pad)/metal3 rnw/active 0.900 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 rnw/active 10.500 ~space/m1,~space/m2,~space/c + +#metal3-*diff blocked by ~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 (ndiff,rnd,ndc)/active 0.990 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (ndiff,rnd,ndc)/active 10.500 ~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 (pdiff,rpd,pdc)/active 0.990 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (pdiff,rpd,pdc)/active 10.500 ~space/m1,~space/m2,~space/c + +#metal3-poly blocked by ~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 0.810 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 8.100 ~space/m1,~space/m2,~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,pad)/metal3 8.100 ~space/m1,~space/m2,~space/c + +#metal3-poly2 blocked by ~space/m1,~space/m2 + +#M3->M1 + overlap (m3,fm3,rm3,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 1.080 ~space/m2 + +#metal3-metal1 blocked by ~space/m2 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 9.900 ~space/m2 + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m3,fm3,rm3,m3c,pad)/metal3 9.900 ~space/m2 + +#M3->M2 + overlap (m3,fm3,rm3,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 3.060 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 16.800 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,pad)/metal3 16.800 + +#metal4 + +#metal5 + +#metal6 + +#metal7 + +#metali + +#fets + +# fet pfet pdiff,pdc 2 pfet Vdd! nwell 83 213 +# fet pfet pdiff,pdc 1 pfet Vdd! nwell 83 213 + + device mosfet pfet pfet pdiff,pdc nwell $VDD 83 213 + +# fet nfet ndiff,ndc 2 nfet Gnd! pwell 59 222 +# fet nfet ndiff,ndc 1 nfet Gnd! pwell 59 222 + + device mosfet nfet nfet ndiff,ndc pwell $GND 59 222 + + fetresis pfet linear 20996 + fetresis pfet saturation 20996 + fetresis nfet linear 6144 + fetresis nfet saturation 6144 + +# fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 +# fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 +# fet rpoly2 poly2,p2c 2 poly2Resistor Gnd! nwell,pwell 0 0 +# fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 +# fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 + + device resistor None rnwell nsd,nsc + device resistor None rpoly poly,pc + device resistor None rpoly2 poly2,p2c + device resistor None rndiff ndiff,ndc + device resistor None rpdiff pdiff,pdc + +# fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 +# fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 +# fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 +# fet phr poly2,p2c 2 phrResistor Gnd! nwell,pwell 0 0 + + device resistor None rmetal1 *metal1 + device resistor None rmetal2 *metal2 + device resistor None rmetal3 *metal3 + device resistor None phr poly2,p2c + +end + +wiring + contact pdcontact 4 metal1 0 pdiff 0 + contact ndcontact 4 metal1 0 ndiff 0 + contact pcontact 4 metal1 0 poly 0 + contact m2contact 4 metal1 0 metal2 0 + contact m3contact 5 metal2 0 metal3 1 + +end + +router + layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,rp,ndiff,rnd,nsd,pdiff,rpd,psd,m1,fm1,rm1 1 + layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 + contacts m2contact 4 + gridspacing 8 + +end + +plowing + fixed nfet,pfet,glass,pad + covered nfet,pfet + drag nfet,pfet + +end + +plot +style colorversatec + ndiff,rnd,ndc/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + ndiff,rnd,ndc/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + nsd,nsc/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + nsd,nsc/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + pdiff,rpd,pdc/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + pdiff,rpd,pdc/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + pdiff,rpd,pdc/a magenta \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + psd,psc/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + psd,psc/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + psd,psc/a magenta \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 + poly,fp,rp,pc/a magenta \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + nfet yellow \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 + nfet cyan \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 + nfet magenta \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A + pfet yellow \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 + pfet cyan \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 + pfet magenta \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 + poly2,ecap,phr,p2c,p2m12c yellow \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF + m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 cyan \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + m2,fm2,rm2,m2c/m2,m3c/m2 cyan \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 + m2,fm2,rm2,m2c/m2,m3c/m2 magenta \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 + m2c/m1,gv1 black \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 + pad,glass black \ + 0300 0700 0E00 1C00 \ + 3800 7000 E000 C000 \ + 00C0 00E0 0070 0038 \ + 001C 000E 0007 0003 + nwell yellow \ + 0800 1000 2000 4000 \ + 8000 0001 0002 0004 \ + 0008 0010 0020 0040 \ + 0080 0010 0200 0400 + nwell cyan \ + 1000 2000 4000 8000 \ + 0001 0002 0004 0008 \ + 0010 0020 0040 0080 \ + 0100 0200 0400 0800 + pwell yellow \ + 1000 0400 0400 0100 \ + 0100 0040 0040 0010 \ + 0010 0004 0004 0001 \ + 0001 4000 4000 1000 + pwell cyan \ + 0000 0800 0000 0200 \ + 0000 0080 0000 0020 \ + 0000 0008 0000 0002 \ + 0000 8000 0000 2000 + pwell magenta \ + 0800 0000 0200 0000 \ + 0080 0000 0020 0000 \ + 0008 0000 0002 0000 \ + 8000 0000 2000 0000 + m3c/m2,gv2 black \ + 0100 0000 0000 0000 \ + 1010 0000 0000 0000 \ + 0001 0000 0000 0000 \ + 1010 0000 0000 0000 + m3c/m2,gv2 cyan \ + 0280 0000 0820 0000 \ + 2008 0000 8002 0000 \ + 8002 0000 2008 0000 \ + 0820 0000 0280 0000 + m3c/m2,gv2 magenta \ + 0100 06C0 0440 1830 \ + 1010 600C 4004 8003 \ + 0001 C006 4004 3018 \ + 1010 0C60 0440 0380 + m3c/m2,gv2 black \ + 0820 0820 0820 0FE0 \ + E00F 2008 2008 2008 \ + 2008 2008 2008 E00F \ + 0000 0FE0 0820 0820 + error_p,error_s,error_ps black \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 + magnet yellow \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 + fence magenta \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 + rotate cyan \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X + +style versatec + pfet \ + 07c0 0f80 1f00 3e00 \ + 7c00 f800 f001 e003 \ + c007 800f 001f 003e \ + 00c7 00f8 01f0 03e0 + nfet \ + 1f00 0f80 07c0 03e0 \ + 01f0 00f8 007c 003e \ + 001f 800f c007 e003 \ + f001 f800 7c00 3e00 + gv1 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 + pwell \ + 2020 2020 2020 2020 \ + 2020 2020 2020 2020 \ + 0000 0000 0000 0000 \ + 0000 0000 0000 0000 + nwell \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 + poly,fp,rp,pc/a,nfet,pfet \ + 0808 0400 0202 0101 \ + 8080 4000 2020 1010 \ + 0808 0004 0202 0101 \ + 8080 0040 2020 1010 + m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 + pad,glass \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 + nsd,nsc/a \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 + m2,fm2,rm2,m2c/m2,m3c/m2 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 + pdiff,rpd,pdc/a,pfet \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 + psd,psc/a \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 + ndiff,rnd,ndc/a,nfet \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X + +style gremlin + pfet 9 + nfet 10 + gv1 11 + pwell 15 + nwell 16 + poly,fp,rp,pc/a,nfet,pfet 19 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc 22 + pad,glass 23 + nsd,nsc/a 24 + gv1 28 + pdiff,rpd,pdc/a,pfet 29 + psd,psc/a 30 + ndiff,rnd,ndc/a,nfet 31 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc,gv1 X + +end + diff --git a/technology/scn3me_subm/tech/__init__.py b/technology/scn3me_subm/tech/__init__.py new file mode 100755 index 00000000..2573d2c2 --- /dev/null +++ b/technology/scn3me_subm/tech/__init__.py @@ -0,0 +1,6 @@ +""" +Import tech specific modules. +""" + +from .tech import * + diff --git a/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul b/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul new file mode 100755 index 00000000..91d35fb4 --- /dev/null +++ b/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul @@ -0,0 +1,225 @@ +//////////////////////////////////////////////////////////// +// DEFINE BOOLEAN LAYERS +//////////////////////////////////////////////////////////// +LAYOUT USE DATABASE PRECISION YES + +layer pwell 41 +layer nwell 42 +layer active 43 +layer poly 46 +layer nimplant 45 +layer pimplant 44 +layer contact 25 +layer active_contact 48 +layer poly_contact 47 +layer metal1 49 +layer via1 50 +layer metal2 51 +layer via2 61 +layer metal3 62 +layer glass 52 +layer pad 26 + +//Enabling incremental connectivity for antenna rule checks +DRC Incremental Connect Yes + +well = nwell OR pwell +gate = poly AND active +implant = nimplant OR pimplant +fieldpoly = poly NOT active + +contactenc1 = active OR poly +contactenc = contactenc1 AND metal1 +diode = contact AND active +act_poly = interact poly active + +GROUP mask_check +//Well.2 Well.4 +Poly.1 Poly.2 Poly.3 Poly.4 Poly.5 +Active.1 Active.2 // Active.3 +Contact.1 Contact.2 Contact.3 Contact.4 +Contact.5 Contact.6 Metal1.1 Metal1.2 Metal1.3 + + + +//Well.1 { +//@Nwell and Pwell must not overlap +//AND nwell pwell +//} + +//Well.2 { +//@Min spacing of pwell to nwell = 0.00 +//EXTERNAL nwell pwell < 0.00 +//} + +//Well.4 { +//@Min width of nwell = 3.6 +//INTERNAL nwell < 3.6 +//} + +Poly.1 { +@Min width of poly = 0.6 +INTERNAL poly < 0.6 +} + +Poly.2 { +@Min spacing of gate poly = 0.9 +EXTERNAL gate < 0.9 +} + +Poly.3 { +@Min extension of poly past active = 0.6 +ENCLOSURE active poly < 0.6 +} + +Poly.4 { +@Minimum active enclosure of gate =0.6 +ENCLOSURE poly active < 0.6 +} + +Poly.5 { +@Minimum spacing of poly to active = 0.3 +EXTERNAL act_poly active < 0.3 +} + +Active.1 { +@Minimum width of active = 0.9 +INTERNAL active < 0.9 +} + +Active.2 { +@Minimum spacing of active areas = 0.9 +EXTERNAL active < 0.9 +} + +//Active.3 { +//@Minimum well enclosure of active = 1.8 +//ENCLOSURE active well < 1.8 +//} + +Contact.1 { +@Minimum width of contact = 0.6 +INTERNAL contact < 0.6 +} + +Contact.2 { +@Minimum spacing of contact = 0.9 +EXTERNAL contact < 0.9 +} + +Contact.3 { +@Contact must be inside metal1 and active or poly +NOT contact contactenc +} + +Contact.4 { +@Minimum active enclosure of contact = 0.3 +ENCLOSURE contact active < 0.3 +} + +Contact.5 { +@Minimum poly enclosure of contact = 0.3 +ENCLOSURE contact poly < 0.3 +} + +Contact.6 { +@Minimum spacing of contact to poly = 0.6 +EXTERNAL poly contact < 0.6 +} + +Metal1.1 { +@Minimum width of metal1 = 0.9 +INTERNAL metal1 < 0.9 +} + +Metal1.2 { +@Minimum spacing of metal1 = 0.9 +EXTERNAL metal1 < 0.9 +} + +Metal1.3 { +@Metal1 must extend past contact by 0.3 on two opposite sides +RECTANGLE ENCLOSURE contact metal1 +GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE +} + +Metal1.4 { +@Metal1 must extend past via1 by 0.3 on two opposite sides +RECTANGLE ENCLOSURE via1 metal1 +GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE +} + +Via1.1 { +@Minimum width of via1 = 0.6 +INTERNAL via1 < 0.6 +} + +Via1.2 { +@Minimum spacing of via1 = 0.6 +EXTERNAL via1 < 0.6 +} + +Via1.3 { +@Via1 must be inside metal1 +NOT via1 metal1 +} + + +Metal2.1 { +@Minimum width of metal2 = 0.9 +INTERNAL metal2 < 0.9 +} + +Metal2.2 { +@Minimum spacing of metal2 = 0.9 +EXTERNAL metal2 < 0.9 +} + +Metal2.3 { +@Metal2 must extend past via1 by 0.3 on two opposite sides +RECTANGLE ENCLOSURE via1 metal2 +GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE +} + +Metal2.4 { +@Metal2 must extend past via2 by 0.3 on two opposite sides +RECTANGLE ENCLOSURE via2 metal2 +GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE +} + +Via2.1 { +@Minimum width of via2 = 0.6 +INTERNAL via2 < 0.6 +} + +Via2.2 { +@Minimum spacing of via2 = 0.9 +EXTERNAL via2 < 0.9 +} + +Via2.3 { +@Via2 must be inside metal2 +NOT via2 metal2 +} + +Via2.4 { +@Via2 must be inside metal3 +NOT via2 metal3 +} + +Metal3.1 { +@Minimum width of metal3 = 1.5 +INTERNAL metal3 < 1.5 +} + +Metal3.2 { +@Minimum spacing of metal3 = 0.9 +EXTERNAL metal3 < 0.9 +} + +Metal3.3 { +@Metal3 must extend past via2 by 0.6 on two opposite sides +RECTANGLE ENCLOSURE via2 metal3 +GOOD 0.00 0.6 OPPOSITE 0.00 0.6 OPPOSITE +} + diff --git a/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul b/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul new file mode 100755 index 00000000..5d3516a6 --- /dev/null +++ b/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul @@ -0,0 +1,123 @@ +TITLE "LVS Rule File for scn3me_subm" + +LVS POWER NAME vdd +LVS GROUND NAME gnd GROUND +LVS REDUCE PARALLEL MOS yes +LVS REDUCE SERIES MOS yes +LVS REDUCE SEMI SERIES MOS yes +LVS FILTER UNUSED MOS no +LVS RECOGNIZE GATES all +LVS COMPONENT TYPE PROPERTY element +LVS COMPONENT SUBTYPE PROPERTY model +LVS IGNORE PORTS no + +LVS REPORT mask.lvs.rep +LVS REPORT OPTION N +LVS REPORT MAXIMUM 50 +MASK RESULTS DATABASE maskdb + +precision 1000 +resolution 250 + +TEXT LAYER metal1 metal2 metal3 +PORT LAYER TEXT metal1 metal2 metal3 + + +layer pwell 41 +layer nwell 42 +layer active 43 +layer poly 46 +layer nimplant 45 +layer pimplant 44 +layer contact 25 +layer active_contact 48 +layer poly_contact 47 +layer metal1 49 +layer via1 50 +layer metal2 51 +layer via2 61 +layer metal3 62 +layer glass 52 +layer pad 26 + +connect metal1 metal2 by via1 +connect metal2 metal3 by via2 + +pdif = active and pimplant // P-diffusion +ndif = active and nimplant // N-diffusion + +ngate = poly and ndif // N-Transistor +pgate = poly and pdif // P-transistor + +nsrcdrn = ndif not ngate // N-tansistor Source and Drain contacts diffusion region +psrcdrn = pdif not pgate // P-tansistor Source and Drain contacts diffusion region + +pcont = psrcdrn and pwell + +ntapcont = active not interact pimplant +ptapcont = active not interact nimplant + +bulk = extent +nsub = (bulk not pwell) and nwell +ncont = nsrcdrn and nsub + +connect metal1 poly psrcdrn nsrcdrn by contact mask +connect psrcdrn pwell by pcont mask +connect nsrcdrn nsub by ncont mask + +ncont1= ntapcont and nsub +pcont1= ptapcont and pwell +connect metal1 ncont1 by contact mask +connect metal1 pcont1 by contact mask +connect ncont1 nsub +connect pcont1 pwell + +connect psrcdrn metal1 by contact +connect nsrcdrn metal1 by contact + +connect psrcdrn metal1 by active_contact +connect nsrcdrn metal1 by active_contact + +connect poly metal1 by contact + +connect poly metal1 by poly_contact + +device mp (p) pgate poly (G) psrcdrn (S) psrcdrn (D) nsub CMACRO FET_PROPERTIES pgate nsub +device mn (n) ngate poly (G) nsrcdrn (S) nsrcdrn (D) pwell CMACRO FET_PROPERTIES ngate pwell + +VARIABLE trace_delta 4e-9 + +DMACRO FET_TRACE device_type device_name { +TRACE PROPERTY device_type(device_name) l l trace_delta ABSOLUTE +TRACE PROPERTY device_type(device_name) w w trace_delta ABSOLUTE + +} + +CMACRO FET_TRACE MN n +CMACRO FET_TRACE MP p + +DMACRO FET_PROPERTIES seed well{ +[ +PROPERTY W, L, AS, AD, PS, PD + + AS = area(S) + AD = area(D) + PS = perimeter(S) + PD = perimeter(D) + if ( AS == 0 ) { + AD = area(D) / 2 + AS = AD + PD = perimeter(D) / 2 + PS = PD + } + if ( AD == 0 ) { + AS = area(S) / 2 + AD = AS + PS = perimeter(S) / 2 + PD = PS + } + W = (perim_co(seed,S) + perim_co(seed,D) ) * 0.5 + L = (perim(seed) - perim_co(seed,S) - perim_in(seed,S) - perim_co(seed,D) - perim_in(seed,D) ) * 0.5 + +] +} diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py new file mode 100755 index 00000000..fb7524c1 --- /dev/null +++ b/technology/scn3me_subm/tech/tech.py @@ -0,0 +1,311 @@ +import os +from design_rules import * + +""" +File containing the process technology parameters for SCMOS 3me, subm, 180nm. +""" + +#GDS file info +GDS={} +# gds units +# gds units +# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first +#is the size of a database unit in user units. The second is the size +#of a database unit in meters. For example, if your library was +#created with the default units (user unit = 1 m and 1000 database +#units per user unit), then the first number would be 0.001 and the +#second number would be 10-9. Typically, the first number is less than +#1, since you use more than 1 database unit per user unit. To +#calculate the size of a user unit in meters, divide the second number +#by the first." +GDS["unit"]=(0.001,1e-6) +# default label zoom +GDS["zoom"] = 0.5 + + +################################################### +##GDS Layer Map +################################################### + +# create the GDS layer map +layer={} +layer["vtg"] = -1 +layer["vth"] = -1 +layer["contact"] = 47 +layer["pwell"] = 41 +layer["nwell"] = 42 +layer["active"] = 43 +layer["pimplant"] = 44 +layer["nimplant"] = 45 +layer["poly"] = 46 +layer["active_contact"] = 48 +layer["metal1"] = 49 +layer["via1"] = 50 +layer["metal2"] = 51 +layer["via2"] = 61 +layer["metal3"] = 62 +layer["text"] = 63 +layer["boundary"] = 63 +layer["blockage"] = 83 + +################################################### +##END GDS Layer Map +################################################### + +################################################### +##DRC/LVS Rules Setup +################################################### +_lambda_ = 0.3 + +#technology parameter +parameter={} +parameter["min_tx_size"] = 4*_lambda_ +parameter["beta"] = 2 + +parameter["6T_inv_nmos_size"] = 8*_lambda_ +parameter["6T_inv_pmos_size"] = 3*_lambda_ +parameter["6T_access_size"] = 4*_lambda_ + +drclvs_home=os.environ.get("DRCLVS_HOME") + +drc = design_rules("scn3me_subm") + +drc["body_tie_down"] = 0 +drc["has_pwell"] = True +drc["has_nwell"] = True + + +#grid size is 1/2 a lambda +drc["grid"]=0.5*_lambda_ +#DRC/LVS test set_up +drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" +drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" +drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" + + +# minwidth_tx with contact (no dog bone transistors) +drc["minwidth_tx"] = 4*_lambda_ +drc["minlength_channel"] = 2*_lambda_ + +# 1.3 Minimum spacing between wells of same type (if both are drawn) +drc["well_to_well"] = 6*_lambda_ +# 1.4 Minimum spacing between wells of different type (if both are drawn) +drc["pwell_to_nwell"] = 0 +# 1.1 Minimum width +drc["minwidth_well"] = 12*_lambda_ + +# 3.1 Minimum width +drc["minwidth_poly"] = 2*_lambda_ +# 3.2 Minimum spacing over active +drc["poly_to_poly"] = 3*_lambda_ +# 3.3 Minimum gate extension of active +drc["poly_extend_active"] = 2*_lambda_ +# 5.5.b Minimum spacing between poly contact and other poly (alternative rules) +drc["poly_to_polycontact"] = 4*_lambda_ +# ?? +drc["active_enclosure_gate"] = 0.0 +# 3.5 Minimum field poly to active +drc["poly_to_active"] = _lambda_ +# 3.2.a Minimum spacing over field poly +drc["poly_to_field_poly"] = 3*_lambda_ +# Not a rule +drc["minarea_poly"] = 0.0 + +# ?? +drc["active_to_body_active"] = 4*_lambda_ # Fix me +# 2.1 Minimum width +drc["minwidth_active"] = 3*_lambda_ +# 2.2 Minimum spacing +drc["active_to_active"] = 3*_lambda_ +# 2.3 Source/drain active to well edge +drc["well_enclosure_active"] = 6*_lambda_ +# Reserved for asymmetric enclosures +drc["well_extend_active"] = 6*_lambda_ +# Not a rule +drc["minarea_active"] = 0.0 + +# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width +drc["implant_to_channel"] = 3*_lambda_ +# 4.2 Minimum select overlap of active +drc["implant_enclosure_active"] = 2*_lambda_ +# 4.3 Minimum select overlap of contact +drc["implant_enclosure_contact"] = _lambda_ +# Not a rule +drc["implant_to_contact"] = 0 +# Not a rule +drc["implant_to_implant"] = 0 +# Not a rule +drc["minwidth_implant"] = 0 + +# 6.1 Exact contact size +drc["minwidth_contact"] = 2*_lambda_ +# 5.3 Minimum contact spacing +drc["contact_to_contact"] = 3*_lambda_ +# 6.2.b Minimum active overlap +drc["active_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["active_extend_contact"] = _lambda_ +# 5.2.b Minimum poly overlap +drc["poly_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosures +drc["poly_extend_contact"] = _lambda_ +# Reserved for other technologies +drc["contact_to_gate"] = 2*_lambda_ +# 5.4 Minimum spacing to gate of transistor +drc["contact_to_poly"] = 2*_lambda_ + +# 7.1 Minimum width +drc["minwidth_metal1"] = 3*_lambda_ +# 7.2 Minimum spacing +drc["metal1_to_metal1"] = 3*_lambda_ +# 7.3 Minimum overlap of any contact +drc["metal1_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["metal1_extend_contact"] = _lambda_ +# 8.3 Minimum overlap by metal1 +drc["metal1_enclosure_via1"] = _lambda_ +# Reserve for asymmetric enclosures +drc["metal1_extend_via1"] = _lambda_ +# Not a rule +drc["minarea_metal1"] = 0 + +# 8.1 Exact size +drc["minwidth_via1"] = 2*_lambda_ +# 8.2 Minimum via1 spacing +drc["via1_to_via1"] = 3*_lambda_ + +# 9.1 Minimum width +drc["minwidth_metal2"] = 3*_lambda_ +# 9.2 Minimum spacing +drc["metal2_to_metal2"] = 3*_lambda_ +# 9.3 Minimum overlap of via1 +drc["metal2_extend_via1"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal2_enclosure_via1"] = _lambda_ +# 14.3 Minimum overlap by metal2 +drc["metal2_extend_via2"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal2_enclosure_via2"] = _lambda_ +# Not a rule +drc["minarea_metal2"] = 0 + +# 14.1 Exact size +drc["minwidth_via2"] = 2*_lambda_ +# 14.2 Minimum spacing +drc["via2_to_via2"] = 3*_lambda_ + +# 15.1 Minimum width +drc["minwidth_metal3"] = 5*_lambda_ +# 15.2 Minimum spacing to metal3 +drc["metal3_to_metal3"] = 3*_lambda_ +# 15.3 Minimum overlap of via 2 +drc["metal3_extend_via2"] = 2*_lambda_ +# Reserved for asymmetric enclosures +drc["metal3_enclosure_via2"] = 2*_lambda_ +# Not a rule +drc["minarea_metal3"] = 0 + +################################################### +##END DRC/LVS Rules +################################################### + +################################################### +##Spice Simulation Parameters +################################################### + +# spice model info +spice={} +spice["nmos"]="n" +spice["pmos"]="p" +# This is a map of corners to model files +SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR") +# FIXME: Uncomment when we have the new spice models +#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] } +spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], + "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], + "SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + "SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], + "ST" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], + "TS" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], + "FT" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], + "TF" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + } + + +#spice stimulus related variables +spice["feasible_period"] = 10 # estimated feasible period in ns +spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts] +spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts] +spice["rise_time"] = 0.05 # rise time in [Nano-seconds] +spice["fall_time"] = 0.05 # fall time in [Nano-seconds] +spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius) +spice["nom_temperature"] = 25 # Nominal temperature (celcius) + +#sram signal names +#FIXME: We don't use these everywhere... +spice["vdd_name"] = "vdd" +spice["gnd_name"] = "gnd" +spice["control_signals"] = ["CSB", "WEB"] +spice["data_name"] = "DATA" +spice["addr_name"] = "ADDR" +spice["minwidth_tx"] = drc["minwidth_tx"] +spice["channel"] = drc["minlength_channel"] +spice["clk"] = "clk" + +# analytical delay parameters +# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45. +spice["vdd_nominal"] = 5.0 # Typical Threshold voltage in Volts +spice["temp_nominal"] = 25.0 # Typical Threshold voltage in Volts +spice["v_threshold_typical"] = 1.3 # Typical Threshold voltage in Volts +spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square +spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2 +spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms +spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff +spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff +spice["msflop_setup"] = 9 # DFF setup time in ps +spice["msflop_hold"] = 1 # DFF hold time in ps +spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] +spice["dff_setup"] = 9 # DFF setup time in ps +spice["dff_hold"] = 1 # DFF hold time in ps +spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] + +# analytical power parameters, many values are temporary +spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW +spice["inv_leakage"] = 1 # Leakage power of inverter in nW +spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW +spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW +spice["msflop_leakage"] = 1 # Leakage power of flop in nW +spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF + +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transition_prob"] = .5 # Transition probability of inverter. +spice["inv_transition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. + +#Logical Effort relative values for the Handmade cells +parameter['le_tau'] = 23 #In pico-seconds. +parameter["min_inv_para_delay"] = .73 #In relative delay units +parameter['cap_relative_per_ff'] = .91 #Units of Relative Capacitance/ Femto-Farad +parameter["static_delay_stages"] = 4 +parameter["static_fanout_per_stage"] = 3 +parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]] +parameter["dff_clk_cin"] = 27.5 #In relative capacitance units +parameter["6tcell_wl_cin"] = 2 #In relative capacitance units +parameter["sa_en_pmos_size"] = 24*_lambda_ +parameter["sa_en_nmos_size"] = 9*_lambda_ +parameter["sa_inv_pmos_size"] = 18*_lambda_ +parameter["sa_inv_nmos_size"] = 9*_lambda_ +parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array +parameter['bitcell_drain_cap'] = 0.2 #In Femto-Farad, approximation of drain capacitance + +################################################### +##END Spice Simulation Parameters +################################################### diff --git a/technology/scn3me_subm/tf/README b/technology/scn3me_subm/tf/README new file mode 100644 index 00000000..400cfe98 --- /dev/null +++ b/technology/scn3me_subm/tf/README @@ -0,0 +1,19 @@ +;; NCSU CDK v. 1.6.0.beta +;; Last Modified: 2007-07-12 + +The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, +2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long +as this notice appears in the modified package. The NCSU CDK is +provided with NO WARRANTY. + +As of version 1.5.1, all documentation for the NCSU CDK is provided +by the NCSU EDA Wiki which can be found at: + + http://www.eda.ncsu.edu/ + +This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1 +for OpenAccess. Details of the conversion of the CDK from the CDB version can +be found in the file cdb2oa/OA_Conversion.txt. + +This kit is not yet fully supported. Please post problems and solutions at +http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1 diff --git a/technology/scn3me_subm/tf/display.drf b/technology/scn3me_subm/tf/display.drf new file mode 100644 index 00000000..4bd251e8 --- /dev/null +++ b/technology/scn3me_subm/tf/display.drf @@ -0,0 +1,714 @@ +drDefineDisplay( +;( DisplayName ) + ( display ) +) +drDefineColor( +;( DisplayName ColorsName Red Green Blue ) + ( display white 255 255 255 ) + ( display yellow 255 255 0 ) + ( display silver 217 230 255 ) + ( display cream 255 255 204 ) + ( display pink 255 191 242 ) + ( display magenta 255 0 255 ) + ( display lime 0 255 0 ) + ( display tan 255 230 191 ) + ( display cyan 0 255 255 ) + ( display cadetBlue 57 191 255 ) + ( display orange 255 128 0 ) + ( display red 255 51 51 ) + ( display purple 153 0 230 ) + ( display green 0 204 102 ) + ( display brown 191 64 38 ) + ( display blue 51 77 255 ) + ( display slate 140 140 166 ) + ( display gold 217 204 0 ) + ( display maroon 230 31 13 ) + ( display violet 94 0 230 ) + ( display forest 38 140 107 ) + ( display chocolate 128 38 38 ) + ( display navy 51 51 153 ) + ( display black 0 0 0 ) + ( display gray 204 204 217 ) + ( display winColor1 166 166 166 ) + ( display winColor2 115 115 115 ) + ( display winColor3 189 204 204 ) + ( display winColor4 204 204 204 ) + ( display winColor5 199 199 199 ) + ( display blinkRed 255 0 0 t ) + ( display blinkYellow 255 255 0 t ) + ( display blinkWhite 255 255 255 t ) + ( display winBack 224 224 224 ) + ( display winFore 128 0 0 ) + ( display winText 51 51 51 ) +) +drDefineStipple( +;( DisplayName StippleName Bitmap ) + ( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) + ( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) ) + ( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) ) + ( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) + ( display slash ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 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RowLbl blank solid cyan cyan outline ) + ( display edgeLayerPin stipple0 solid yellow yellow solid ) + ( display instance blank solid winBack red outline ) + ( display Nselect dots4 solid green green outlineStipple) + ( display snap stipple0 solid yellow yellow solid ) + ( display pinAnt stipple0 solid red red solid ) + ( display winAttentionText solid solid winText winText solid ) + ( display designFlow2 stipple1 lineStyle0 purple purple outlineStipple) + ( display Unrouted2 stipple0 lineStyle1 red red solid ) + ( display hilite blank solid white white outline ) + ( display P2Con solid lineStyle0 orange orange solid ) + ( display designFlow1 stipple1 lineStyle0 red red outlineStipple) + ( display grid1 stipple0 solid gray gray solid ) + ( display Unrouted3 stipple0 lineStyle1 pink pink solid ) + ( display ViaNet x solid magenta magenta outlineStipple) + ( display select stipple0 solid tan tan solid ) + ( display Poly2Net dots4 lineStyle0 orange orange outlineStipple) + ( display winText solid solid winText winText solid ) + ( display Unrouted4 stipple0 lineStyle1 orange orange solid ) + ( display wireLbl solid lineStyle0 cyan cyan solid ) + ( display designFlow7 stipple1 lineStyle0 cyan cyan outlineStipple) + ( display align stipple0 solid tan tan solid ) + ( display Poly2Pin blank solid yellow yellow outline ) + ( display Unrouted5 stipple0 lineStyle1 green green solid ) + ( display unset stipple0 solid forest forest solid ) + ( display Poly1Net dots4 lineStyle0 red red outlineStipple) + ( display Resistor dots2 lineStyle0 cyan cyan outlineStipple) + ( display DiodeNet dots4 lineStyle0 cream cream outlineStipple) + ( display designFlow6 stipple1 lineStyle0 tan tan outlineStipple) + ( display Unrouted6 stipple0 lineStyle1 blue blue solid ) + ( display resist stipple0 solid cyan cyan solid ) + ( display designFlow5 stipple1 lineStyle0 silver silver outlineStipple) + ( display CapWellNet brick solid slate slate outlineStipple) + ( display Unrouted7 stipple0 lineStyle1 purple purple solid ) + ( display CannotoccupyBnd blank solid red red outline ) + ( display winTopShadow solid solid white white solid ) + ( display designFlow4 stipple1 lineStyle0 black black outlineStipple) + ( display softFence stipple0 solid yellow yellow solid ) + ( display ResistorNet dots4 solid cyan cyan outlineStipple) + ( display winError solid solid winColor5 winColor5 solid ) + ( display changedLayerTl1 stipple0 solid yellow yellow solid ) + ( display prBoundaryLbl stipple0 solid purple purple solid ) + ( display ActXNet x solid yellow yellow outlineStipple) + ( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple) + ( display Active dots2 lineStyle0 yellow yellow outlineStipple) + ( display changedLayerTl0 stipple0 solid red red solid ) + ( display spike stipple0 solid purple purple solid ) + ( display Metal3 grid solid navy violet outlineStipple) + ( display text blank solid white white outline ) + ( display Poly1Pin stipple0 lineStyle0 red red solid ) + ( display Row blank solid cyan cyan outline ) + ( display Pwell stipple9 lineStyle0 slate slate outlineStipple) + ( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple) + ( display wire solid lineStyle0 cyan cyan solid ) + ( display ActX solid solid yellow yellow solid ) + ( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple) + ( display Cannotoccupy blank solid red red outline ) + ( display GroupLbl stipple0 solid green green solid ) + ( display axis stipple0 solid slate slate solid ) + ( display SiBlockNet x dashed tan tan outlineStipple) + ( display edgeLayer stipple0 solid gray gray solid ) + ( display annotate2 stipple0 solid lime lime solid ) + ( display Metal1Pin stipple0 lineStyle0 blue blue solid ) + ( display Diode stipple7 lineStyle0 cream cream outlineStipple) + ( display Glass X lineStyle0 white white X ) + ( display ViaXNet x solid magenta magenta outlineStipple) + ( display annotate3 stipple0 solid cyan cyan solid ) + ( display Poly2 dots1 lineStyle0 orange orange outlineStipple) + ( display deviceAnt stipple0 solid yellow yellow solid ) + ( display winBottomShadow solid solid winColor1 winColor1 solid ) + ( display PselectNet dots4 solid brown brown outlineStipple) + ( display comment stipple0 lineStyle0 winBack winBack outlineStipple) + ( display Poly1 dots lineStyle0 red red outlineStipple) + ( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid ) + ( display stretch stipple0 solid yellow yellow solid ) + ( display XP blank lineStyle0 winBack gold outline ) + ( display annotate1 stipple0 solid pink pink solid ) + ( display Group stipple2 solid green green outlineStipple) + ( display deviceLbl stipple0 solid green green solid ) + ( display annotate6 stipple0 solid silver silver solid ) + ( display GlassNet blank solid yellow yellow outline ) + ( display Canplace blank solid cyan cyan outline ) + ( display annotate7 stipple0 solid red red solid ) + ( display Via2 solid solid navy navy solid ) + ( display Metal2Pin stipple0 lineStyle0 magenta magenta solid ) + ( display annotate4 stipple0 solid yellow yellow solid ) + ( display device1 stipple1 lineStyle0 green green outlineStipple) + ( display "90" blank solid white white outline ) + ( display markerWarn x solid yellow yellow outlineStipple) + ( display text2 stipple1 lineStyle0 white white outlineStipple) + ( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple) + ( display designFlow stipple1 lineStyle0 green green outlineStipple) + ( display hilite1 stipple0 solid silver silver solid ) + ( display device blank solid green green outline ) + ( display prBoundary stipple0 solid purple purple solid ) + ( display annotate5 stipple0 solid white white solid ) + ( display text1 stipple0 dashed white white solid ) + ( display Via solid solid magenta magenta solid ) + ( display Capacitor stipple7 lineStyle0 tan tan outlineStipple) + ( display markerErr x solid white white outlineStipple) + ( display unknown stipple0 solid yellow yellow solid ) + ( display annotate stipple0 solid orange orange solid ) + ( display P1ConNet x solid red red outlineStipple) + ( display hilite3 stipple0 solid cyan cyan solid ) + ( display winActiveBanner solid solid winColor3 winColor3 solid ) + ( display pinLbl stipple0 solid red red solid ) + ( display device2 stipple0 lineStyle1 green green solid ) + ( display grid stipple0 solid slate slate solid ) + ( display winBackground solid solid winBack winBack solid ) + ( display Metal1Net dots4 lineStyle0 blue blue outlineStipple) + ( display hilite2 stipple0 solid tan tan solid ) + ( display annotate8 stipple0 solid tan tan solid ) + ( display hilite5 stipple0 solid lime lime solid ) + ( display annotate9 stipple0 solid green green solid ) + ( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple) + ( display Metal3Pin stipple0 solid navy navy solid ) + ( display hilite4 stipple0 solid gray gray solid ) + ( display y0 stipple0 solid gray gray solid ) + ( display supply stipple0 solid lime lime solid ) + ( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple) + ( display hilite7 stipple0 solid cream cream solid ) + ( display y1 stipple0 solid brown brown solid ) + ( display defaultPacket x solid chocolate winColor2 outlineStipple) + ( display Via2Net cross solid navy navy outlineStipple) + ( display NselectNet dots4 solid green green outlineStipple) + ( display Unrouted8 stipple0 lineStyle1 gold gold solid ) + ( display hilite6 stipple0 solid orange orange solid ) + ( display y2 stipple0 solid red red solid ) + ( display winBorder solid solid winColor2 winColor2 solid ) + ( display Nwell dats5 thickLine slate slate outlineStipple) + ( display Unrouted9 stipple0 lineStyle1 silver silver solid ) + ( display hilite9 stipple0 solid pink pink solid ) + ( display SiBlock blank dashed tan tan outline ) + ( display y3 stipple0 solid orange orange solid ) + ( display prBoundaryBnd stipple0 solid cyan cyan solid ) + ( display winForeground solid solid winFore winFore solid ) + ( display hilite8 stipple0 solid magenta magenta solid ) + ( display y4 stipple0 solid yellow yellow solid ) + ( display Pselect dots1 solid brown brown outlineStipple) + ( display winInactiveBanner solid solid winColor4 winColor4 solid ) + ( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple) + ( display winButton solid solid winFore winFore solid ) + ( display y5 stipple0 solid green green solid ) + ( display hiz stipple0 solid orange orange solid ) + ( display drive stipple0 solid blue blue solid ) + ( display wireFlt stipple0 dashed red red solid ) + ( display instanceLbl stipple0 solid gold gold solid ) + ( display P2ConNet x lineStyle0 orange orange outlineStipple) + ( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple) + ( display y6 stipple0 solid blue blue solid ) + ( display PwellNet dots4 lineStyle0 slate slate outlineStipple) + ( display P1Con solid solid red red solid ) + ( display CapWell dagger solid slate slate outlineStipple) + ( display y7 stipple0 solid purple purple solid ) + ( display ViaX solid solid magenta magenta solid ) + ( display HR x solid chocolate winColor2 outlineStipple) + ( display HRnet x solid chocolate winColor2 outlineStipple) +) diff --git a/technology/scn3me_subm/tf/glade_scn3me_subm.py b/technology/scn3me_subm/tf/glade_scn3me_subm.py new file mode 100644 index 00000000..d2f9aa7e --- /dev/null +++ b/technology/scn3me_subm/tf/glade_scn3me_subm.py @@ -0,0 +1,7 @@ +import os +CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf" +ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map") + + + + diff --git a/technology/scn3me_subm/tf/layers.map b/technology/scn3me_subm/tf/layers.map new file mode 100644 index 00000000..b5440f23 --- /dev/null +++ b/technology/scn3me_subm/tf/layers.map @@ -0,0 +1,16 @@ +Pwell drawing 41 0 +Nwell drawing 42 0 +Active drawing 43 0 +Poly1 drawing 46 0 +Pselect drawing 45 0 +Nselect drawing 44 0 +contact drawing 25 0 +P1Con drawing 47 0 +ActX drawing 48 0 +Metal1 drawing 49 0 +Via drawing 50 0 +Metal2 drawing 51 0 +Via2 drawing 61 0 +Metal3 drawing 62 0 +Glass drawing 52 0 +comment drawing 63 0 diff --git a/technology/scn3me_subm/tf/mosis.tf b/technology/scn3me_subm/tf/mosis.tf new file mode 100644 index 00000000..759221f1 --- /dev/null +++ b/technology/scn3me_subm/tf/mosis.tf @@ -0,0 +1,848 @@ +; Generated on Sep 28 16:05:23 1998 +; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $ +; +; Matt Clapp fixed: October 10, 2002 +; added via devices, deleted useless app-specific crap, +; added lxExtractRules so undo in layout editor doesn't +; complain. + + +;******************************** +; LAYER DEFINITION +;******************************** + +layerDefinitions( + techLayers( + ;( LayerName Layer# Abbreviation ) + ;( --------- ------ ------------ ) + ;User-Defined Layers: + ( P2Con 3 P2Con ) + ( Poly2 7 Poly2 ) + ( Pbase 10 Pbase ) + ( Resistor 16 Resisto ) + ( Capacitor 17 Capacit ) + ( Diode 18 Diode ) + ( SiBlock 29 SiBlock ) + ( HR 34 HR ) + ( Pwell 41 Pwell ) + ( Nwell 42 Nwell ) + ( Active 43 Active ) + ( Pselect 44 Pselect ) + ( Nselect 45 Nselect ) + ( Poly1 46 Poly1 ) + ( P1Con 47 P1Con ) + ( ActX 48 ActX ) + ( Metal1 49 Metal1 ) + ( Via 50 Via ) + ( Metal2 51 Metal2 ) + ( Glass 52 Glass ) + ( CapWell 59 CapWell ) + ( XP 60 XP ) + ( Via2 61 Via2 ) + ( Metal3 62 Metal3 ) + ( A1 80 A1 ) + ( A2 81 A2 ) + ( comment 117 comment ) + ;System-Reserved Layers: + ( Unrouted 200 Unroute ) + ( Row 201 Row ) + ( Group 202 Group ) + ( Cannotoccupy 203 Cannoto ) + ( Canplace 204 Canplac ) + ( hardFence 205 hardFen ) + ( softFence 206 softFen ) + ( y0 207 y0 ) + ( y1 208 y1 ) + ( y2 209 y2 ) + ( y3 210 y3 ) + ( y4 211 y4 ) + ( y5 212 y5 ) + ( y6 213 y6 ) + ( y7 214 y7 ) + ( y8 215 y8 ) + ( y9 216 y9 ) + ( designFlow 217 designF ) + ( stretch 218 stretch ) + ( edgeLayer 219 edgeLay ) + ( changedLayer 220 changed ) + ( unset 221 unset ) + ( unknown 222 unknown ) + ( spike 223 spike ) + ( hiz 224 hiz ) + ( resist 225 resist ) + ( drive 226 drive ) + ( supply 227 supply ) + ( wire 228 wire ) + ( pin 229 pin ) + ( text 230 text ) + ( device 231 device ) + ( border 232 border ) + ( snap 233 snap ) + ( align 234 align ) + ( prBoundary 235 prBound ) + ( instance 236 instanc ) + ( annotate 237 annotat ) + ( marker 238 marker ) + ( select 239 select ) + ( grid 251 grid ) + ( axis 252 axis ) + ( hilite 253 hilite ) + ( background 254 backgro ) + ) ;techLayers + + techPurposes( + ;( PurposeName Purpose# Abbreviation ) + ;( ----------- -------- ------------ ) + ;User-Defined Purposes: + ;System-Reserved Purposes: + ( warning 234 wng ) + ( tool1 235 tl1 ) + ( tool0 236 tl0 ) + ( label 237 lbl ) + ( flight 238 flt ) + ( error 239 err ) + ( annotate 240 ant ) + ( drawing1 241 dr1 ) + ( drawing2 242 dr2 ) + ( drawing3 243 dr3 ) + ( drawing4 244 dr4 ) + ( drawing5 245 dr5 ) + ( drawing6 246 dr6 ) + ( drawing7 247 dr7 ) + ( drawing8 248 dr8 ) + ( drawing9 249 dr9 ) + ( boundary 250 bnd ) + ( pin 251 pin ) + ( drawing 252 drw ) + ( net 253 net ) + ( cell 254 cel ) + ( all 255 all ) + ) ;techPurposes + + techLayerPurposePriorities( + ;layers are ordered from lowest to highest priority + ; (higher priority is drawn on top of lower priority) + ;( LayerName Purpose ) + ;( --------- ------- ) + ( background drawing ) + ( grid drawing ) + ( grid drawing1 ) + ( Nwell drawing ) + ( Pwell drawing ) + ( CapWell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( annotate drawing ) + ( annotate drawing1 ) + ( annotate drawing2 ) + ( annotate drawing3 ) + ( annotate drawing4 ) + ( annotate drawing5 ) + ( annotate drawing6 ) + ( annotate drawing7 ) + ( annotate drawing8 ) + ( annotate drawing9 ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Glass drawing ) + ( XP drawing ) + ( prBoundary drawing ) + ( prBoundary boundary ) + ( instance drawing ) + ( prBoundary label ) + ( instance label ) + ( Row drawing ) + ( Nwell net ) + ( align drawing ) + ( Pwell net ) + ( CapWell net ) + ( hardFence drawing ) + ( Active net ) + ( softFence drawing ) + ( Row label ) + ( Group drawing ) + ( Group label ) + ( Cannotoccupy drawing ) + ( Cannotoccupy boundary ) + ( Canplace drawing ) + ( ActX net ) + ( A2 drawing ) + ( A1 drawing ) + ( comment drawing ) + ( border drawing ) + ( Pselect net ) + ( Nselect net ) + ( SiBlock net ) + ( HR net ) + ( wire drawing ) + ( Poly1 net ) + ( wire label ) + ( P1Con net ) + ( wire flight ) + ( Metal1 net ) + ( device annotate ) + ( Metal2 net ) + ( device label ) + ( Via net ) + ( Metal3 net ) + ( Via2 net ) + ( pin label ) + ( text drawing ) + ( pin drawing ) + ( text drawing1 ) + ( pin annotate ) + ( device drawing ) + ( axis drawing ) + ( edgeLayer drawing ) + ( edgeLayer pin ) + ( snap drawing ) + ( stretch drawing ) + ( y0 drawing ) + ( y1 drawing ) + ( y2 drawing ) + ( y3 drawing ) + ( y4 drawing ) + ( y5 drawing ) + ( y6 drawing ) + ( y7 drawing ) + ( y8 drawing ) + ( y9 drawing ) + ( hilite drawing ) + ( hilite drawing1 ) + ( hilite drawing2 ) + ( hilite drawing3 ) + ( hilite drawing4 ) + ( hilite drawing5 ) + ( hilite drawing6 ) + ( hilite drawing7 ) + ( hilite drawing8 ) + ( hilite drawing9 ) + ( select drawing ) + ( drive drawing ) + ( hiz drawing ) + ( resist drawing ) + ( spike drawing ) + ( supply drawing ) + ( unknown drawing ) + ( unset drawing ) + ( designFlow drawing ) + ( designFlow drawing1 ) + ( designFlow drawing2 ) + ( designFlow drawing3 ) + ( designFlow drawing4 ) + ( designFlow drawing5 ) + ( designFlow drawing6 ) + ( designFlow drawing7 ) + ( designFlow drawing8 ) + ( designFlow drawing9 ) + ( changedLayer tool0 ) + ( changedLayer tool1 ) + ( marker warning ) + ( marker error ) + ( device drawing1 ) + ( Pbase drawing ) + ( Pbase net ) + ( Resistor net ) + ( Resistor drawing ) + ( Capacitor net ) + ( Capacitor drawing ) + ( Diode net ) + ( Diode drawing ) + ( Poly2 net ) + ( P2Con net ) + ( device drawing2 ) + ( Unrouted drawing ) + ( text drawing2 ) + ( Unrouted drawing1 ) + ( Unrouted drawing2 ) + ( Unrouted drawing3 ) + ( Unrouted drawing4 ) + ( Unrouted drawing5 ) + ( Unrouted drawing6 ) + ( Unrouted drawing7 ) + ( Unrouted drawing8 ) + ( Unrouted drawing9 ) + ) ;techLayerPurposePriorities + + techDisplays( + ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) + ;( --------- ------- ------ --- --- --------- ------- ----- ) + ( background drawing background t nil nil nil nil ) + ( grid drawing grid t nil nil nil nil ) + ( grid drawing1 grid1 t nil nil nil nil ) + ( Nwell drawing Nwell t t t t t ) + ( Pwell drawing Pwell t t t t nil ) + ( Active drawing Active t t t t t ) + ( ActX drawing ActX t t t t t ) + ( Pselect drawing Pselect t t t t t ) + ( Nselect drawing Nselect t t t t t ) + ( SiBlock drawing SiBlock t t t t t ) + ( HR drawing HR t t t t t ) + ( CapWell drawing CapWell t t t t t ) + ( Poly1 drawing Poly1 t t t t t ) + ( P1Con drawing P1Con t t t t t ) + ( Metal1 drawing Metal1 t t t t t ) + ( Via drawing Via t t t t t ) + ( Metal2 drawing Metal2 t t t t t ) + ( annotate drawing annotate t t nil t nil ) + ( annotate drawing1 annotate1 t t nil t nil ) + ( annotate drawing2 annotate2 t t nil t nil ) + ( annotate drawing3 annotate3 t t nil t nil ) + ( annotate drawing4 annotate4 t t nil t nil ) + ( annotate drawing5 annotate5 t t nil t nil ) + ( annotate drawing6 annotate6 t t nil t nil ) + ( annotate drawing7 annotate7 t t nil t nil ) + ( annotate drawing8 annotate8 t t nil t nil ) + ( annotate drawing9 annotate9 t t nil t nil ) + ( Via2 drawing Via2 t t t t t ) + ( Metal3 drawing Metal3 t t t t t ) + ( Glass drawing Glass t t t nil t ) + ( XP drawing XP t t t nil t ) + ( Metal1 pin Metal1Pin t t t nil t ) + ( Metal2 pin Metal2Pin t t t nil t ) + ( Metal3 pin Metal3Pin t t t nil t ) + ( Poly1 pin Poly1Pin t t t nil t ) + ( prBoundary drawing prBoundary t t nil t nil ) + ( prBoundary boundary prBoundaryBnd t t nil t nil ) + ( instance drawing instance t t nil t t ) + ( prBoundary label prBoundaryLbl t t t t nil ) + ( instance label instanceLbl t t t t nil ) + ( Row drawing Row t t t t nil ) + ( Nwell net NwellNet t t t nil nil ) + ( align drawing align t t nil t nil ) + ( Pwell net PwellNet t t t nil nil ) + ( CapWell net CapWellNet t t t nil nil ) + ( SiBlock net SiBlockNet t t t nil nil ) + ( HR net HRnet t t t nil nil ) + ( hardFence drawing hardFence t t t t nil ) + ( Active net ActiveNet t t t nil nil ) + ( softFence drawing softFence t t t t nil ) + ( Row label RowLbl t t t t nil ) + ( Group drawing Group t t t t nil ) + ( Group label GroupLbl t t t t nil ) + ( Cannotoccupy drawing Cannotoccupy t t t t nil ) + ( Cannotoccupy boundary CannotoccupyBnd t t t t nil ) + ( Canplace drawing Canplace t t t t nil ) + ( ActX net ActXNet t t t nil nil ) + ( A2 drawing A2 t t t t nil ) + ( A1 drawing A1 t t t t nil ) + ( comment drawing comment t t t t nil ) + ( border drawing border t t t t nil ) + ( Pselect net PselectNet t t t nil nil ) + ( Nselect net NselectNet t t t nil nil ) + ( wire drawing wire t t t t nil ) + ( Poly1 net Poly1Net t t t nil nil ) + ( wire label wireLbl t t t t nil ) + ( P1Con net P1ConNet t t t nil nil ) + ( wire flight wireFlt t t t t nil ) + ( Metal1 net Metal1Net t t t nil nil ) + ( device annotate deviceAnt t t t t nil ) + ( Metal2 net Metal2Net t t t nil nil ) + ( Metal3 net Metal3Net t t t nil nil ) + ( device label deviceLbl t t t t nil ) + ( Via net ViaNet t t t nil nil ) + ( Via2 net Via2Net t t t nil nil ) + ( pin label pinLbl t t t t nil ) + ( text drawing text t t t t t ) + ( pin drawing pin t t t t nil ) + ( text drawing1 text1 t t t t nil ) + ( pin annotate pinAnt t t t t nil ) + ( device drawing device t t t t nil ) + ( axis drawing axis t t t t nil ) + ( edgeLayer drawing edgeLayer t t nil t nil ) + ( edgeLayer pin edgeLayerPin t t nil t nil ) + ( snap drawing snap t t nil t nil ) + ( stretch drawing stretch t t nil t nil ) + ( y0 drawing y0 t t nil t nil ) + ( y1 drawing y1 t t nil t nil ) + ( y2 drawing y2 t t nil t nil ) + ( y3 drawing y3 t t nil t nil ) + ( y4 drawing y4 t t nil t nil ) + ( y5 drawing y5 t t nil t nil ) + ( y6 drawing y6 t t nil t nil ) + ( y7 drawing y7 t t nil t nil ) + ( y8 drawing y8 t t nil t nil ) + ( y9 drawing y9 t t nil t nil ) + ( hilite drawing hilite t t nil t nil ) + ( hilite drawing1 hilite1 t t t t nil ) + ( hilite drawing2 hilite2 t t nil t nil ) + ( hilite drawing3 hilite3 t t t t nil ) + ( hilite drawing4 hilite4 t t t t nil ) + ( hilite drawing5 hilite5 t t t t nil ) + ( hilite drawing6 hilite6 t t t t nil ) + ( hilite drawing7 hilite7 t t t t nil ) + ( hilite drawing8 hilite8 t t t t nil ) + ( hilite drawing9 hilite9 t t t t nil ) + ( select drawing select t t nil t nil ) + ( drive drawing drive t t t t nil ) + ( hiz drawing hiz t t t t nil ) + ( resist drawing resist t t t t nil ) + ( spike drawing spike t t t t nil ) + ( supply drawing supply t t t t nil ) + ( unknown drawing unknown t t t t nil ) + ( unset drawing unset t t t t nil ) + ( designFlow drawing designFlow t t t nil nil ) + ( designFlow drawing1 designFlow1 t t t nil nil ) + ( designFlow drawing2 designFlow2 t t t nil nil ) + ( designFlow drawing3 designFlow3 t t t nil nil ) + ( designFlow drawing4 designFlow4 t t t nil nil ) + ( designFlow drawing5 designFlow5 t t t nil nil ) + ( designFlow drawing6 designFlow6 t t t nil nil ) + ( designFlow drawing7 designFlow7 t t t nil nil ) + ( designFlow drawing8 designFlow8 t t t nil nil ) + ( designFlow drawing9 designFlow9 t t t nil nil ) + ( changedLayer tool0 changedLayerTl0 nil nil nil nil nil ) + ( changedLayer tool1 changedLayerTl1 nil nil t nil nil ) + ( marker warning markerWarn t t t t nil ) + ( marker error markerErr t t t t nil ) + ( device drawing1 device1 t t t t nil ) + ( Poly2 net Poly2Net t t t nil nil ) + ( Poly2 drawing Poly2 t t t t t ) + ( P2Con net P2ConNet t t t nil nil ) + ( P2Con drawing P2Con t t t t t ) + ( Pbase net PbaseNet t t t nil nil ) + ( Pbase drawing Pbase t t t t t ) + ( Resistor net ResistorNet t t t nil nil ) + ( Resistor drawing Resistor t t t t t ) + ( Capacitor net CapacitorNet t t t nil nil ) + ( Capacitor drawing Capacitor t t t t t ) + ( Diode net DiodeNet t t t nil nil ) + ( Diode drawing Diode t t t t t ) + ( device drawing2 device2 t t t t nil ) + ( Unrouted drawing Unrouted t t t t nil ) + ( text drawing2 text2 t t t t nil ) + ( Unrouted drawing1 Unrouted1 t t t t nil ) + ( Unrouted drawing2 Unrouted2 t t t t nil ) + ( Unrouted drawing3 Unrouted3 t t t t nil ) + ( Unrouted drawing4 Unrouted4 t t t t nil ) + ( Unrouted drawing5 Unrouted5 t t t t nil ) + ( Unrouted drawing6 Unrouted6 t t t t nil ) + ( Unrouted drawing7 Unrouted7 t t t t nil ) + ( Unrouted drawing8 Unrouted8 t t t t nil ) + ( Unrouted drawing9 Unrouted9 t t t t nil ) + ) ;techDisplays + +; I don't think the following is necessary (or used!) +techLayerProperties( +;( PropName Layer1 [ Layer2 ] PropValue ) + ( contactLimit P2Con 10000 ) + ( eqPinLimit P2Con 10000 ) + ( horizontalJogLength P2Con 2147483648.000000 ) + ( routingGrid P2Con 1.000000 ) + ( verticalJogLength P2Con 2147483648.000000 ) + ( routingGrid Poly2 1.000000 ) + ( contactLimit Active 10000 ) + ( eqPinLimit Active 10000 ) + ( horizontalJogLength Active 2147483648.000000 ) + ( routingGrid Active 1.000000 ) + ( verticalJogLength Active 2147483648.000000 ) + ( routingGrid Poly1 1.000000 ) + ( contactLimit P1Con 10000 ) + ( eqPinLimit P1Con 10000 ) + ( horizontalJogLength P1Con 2147483648.000000 ) + ( routingGrid P1Con 1.000000 ) + ( verticalJogLength P1Con 2147483648.000000 ) + ( contactLimit ActX 10000 ) + ( eqPinLimit ActX 10000 ) + ( horizontalJogLength ActX 2147483648.000000 ) + ( routingGrid ActX 1.000000 ) + ( verticalJogLength ActX 2147483648.000000 ) + ( routingGrid Metal1 1.000000 ) + ( contactLimit Via 10000 ) + ( eqPinLimit Via 10000 ) + ( horizontalJogLength Via 2147483648.000000 ) + ( routingGrid Via 1.000000 ) + ( verticalJogLength Via 2147483648.000000 ) + ( routingGrid Metal2 1.000000 ) +) + +) ;layerDefinitions + + +;******************************** +; DEVICE RULES +;******************************** + +devices( + tcCreateCDSDeviceClass() + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA Via drawing + + ; layer1 purpose1 [implant1] + Metal1 drawing + + ; layer2 purpose2 [implant2] + Metal2 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 1 _NA_) + ) ;symContactDevice + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA2 Via2 drawing + + ; layer1 purpose1 [implant1] + Metal2 drawing + + ; layer2 purpose2 [implant2] + Metal3 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 2 _NA_) + ) ;symContactDevice + +) ;devices + + +;******************************** +; LAYER RULES +;******************************** + +layerRules( + streamLayers( + ;( layer streamNumber dataType translate ) + ;( ----- ------------ -------- --------- ) + ( ("background" "drawing") 0 0 nil ) + ( ("grid" "drawing") 0 0 nil ) + ( ("grid" "drawing1") 0 0 nil ) + ( ("Nwell" "drawing") 42 0 t ) + ( ("Pwell" "drawing") 41 0 t ) + ( ("Active" "drawing") 43 0 t ) + ( ("ActX" "drawing") 48 0 t ) + ( ("Pselect" "drawing") 44 0 t ) + ( ("Nselect" "drawing") 45 0 t ) + ( ("Poly1" "drawing") 46 0 t ) + ( ("P1Con" "drawing") 47 0 t ) + ( ("Metal1" "drawing") 49 0 t ) + ( ("Metal2" "drawing") 51 0 t ) + ( ("annotate" "drawing") 0 0 nil ) + ( ("annotate" "drawing1") 0 0 nil ) + ( ("annotate" "drawing2") 0 0 nil ) + ( ("annotate" "drawing3") 0 0 nil ) + ( ("annotate" "drawing4") 0 0 nil ) + ( ("annotate" "drawing5") 0 0 nil ) + ( ("annotate" "drawing6") 0 0 nil ) + ( ("annotate" "drawing7") 0 0 nil ) + ( ("annotate" "drawing8") 0 0 nil ) + ( ("annotate" "drawing9") 0 0 nil ) + ( ("Via" "drawing") 50 0 t ) + ( ("Glass" "drawing") 52 0 t ) + ( ("XP" "drawing") 60 0 t ) + ( ("Metal2" "pin") 0 0 nil ) + ( ("Poly1" "pin") 0 0 nil ) + ( ("prBoundary" "drawing") 0 0 nil ) + ( ("Metal1" "pin") 0 0 nil ) + ( ("prBoundary" "boundary") 0 0 nil ) + ( ("instance" "drawing") 246 0 nil ) + ( ("instance" "label") 0 0 nil ) + ( ("Nwell" "net") 0 0 nil ) + ( ("align" "drawing") 0 0 nil ) + ( ("Pwell" "net") 0 0 nil ) + ( ("hardFence" "drawing") 0 0 nil ) + ( ("Active" "net") 0 0 nil ) + ( ("softFence" "drawing") 0 0 nil ) + ( ("ActX" "net") 0 0 nil ) + ( ("A2" "drawing") 5 0 nil ) + ( ("A1" "drawing") 2 0 nil ) + ( ("comment" "drawing") 0 0 nil ) + ( ("border" "drawing") 0 0 nil ) + ( ("Pselect" "net") 0 0 nil ) + ( ("Nselect" "net") 0 0 nil ) + ( ("wire" "drawing") 0 0 nil ) + ( ("Poly1" "net") 0 0 nil ) + ( ("P1Con" "net") 0 0 nil ) + ( ("Metal1" "net") 0 0 nil ) + ( ("Metal2" "net") 0 0 nil ) + ( ("device" "label") 0 0 nil ) + ( ("Via" "net") 0 0 nil ) + ( ("pin" "label") 0 0 nil ) + ( ("text" "drawing") 63 0 t ) + ( ("pin" "drawing") 0 0 nil ) + ( ("device" "drawing") 0 0 nil ) + ( ("axis" "drawing") 0 0 nil ) + ( ("edgeLayer" "drawing") 0 0 nil ) + ( ("edgeLayer" "pin") 0 0 nil ) + ( ("snap" "drawing") 0 0 nil ) + ( ("stretch" "drawing") 0 0 nil ) + ( ("y0" "drawing") 0 0 nil ) + ( ("y1" "drawing") 0 0 nil ) + ( ("y2" "drawing") 0 0 nil ) + ( ("y3" "drawing") 0 0 nil ) + ( ("y4" "drawing") 0 0 nil ) + ( ("y5" "drawing") 0 0 nil ) + ( ("y6" "drawing") 0 0 nil ) + ( ("y7" "drawing") 0 0 nil ) + ( ("y8" "drawing") 0 0 nil ) + ( ("y9" "drawing") 0 0 nil ) + ( ("hilite" "drawing") 0 0 nil ) + ( ("hilite" "drawing2") 0 0 nil ) + ( ("select" "drawing") 0 0 nil ) + ( ("drive" "drawing") 0 0 nil ) + ( ("hiz" "drawing") 0 0 nil ) + ( ("resist" "drawing") 0 0 nil ) + ( ("spike" "drawing") 0 0 nil ) + ( ("supply" "drawing") 0 0 nil ) + ( ("unknown" "drawing") 0 0 nil ) + ( ("unset" "drawing") 0 0 nil ) + ( ("changedLayer" "tool0") 0 0 nil ) + ( ("Resistor" "net") 0 0 nil ) + ( ("Resistor" "drawing") 0 0 nil ) + ( ("Capacitor" "net") 0 0 nil ) + ( ("Capacitor" "drawing") 0 0 nil ) + ( ("Diode" "net") 0 0 nil ) + ( ("Diode" "drawing") 0 0 nil ) + ( ("Poly2" "net") 0 0 nil ) + ( ("Poly2" "drawing") 0 0 nil ) + ( ("P2Con" "net") 0 0 nil ) + ( ("P2Con" "drawing") 0 0 nil ) + ( ("Pbase" "drawing") 0 0 nil ) + ( ("Pbase" "net") 0 0 nil ) + ( P2Con 0 0 nil ) + ( Poly2 0 0 nil ) + ( Pwell 0 0 nil ) + ( Nwell 0 0 nil ) + ( Active 0 0 nil ) + ( Pselect 0 0 nil ) + ( Nselect 0 0 nil ) + ( Poly1 0 0 nil ) + ( P1Con 0 0 nil ) + ( ActX 0 0 nil ) + ( Metal1 0 0 nil ) + ( Via 0 0 nil ) + ( Metal2 0 0 nil ) + ( Glass 0 0 nil ) + ( XP 0 0 nil ) + ( ("Via2" "drawing") 50 0 t ) + ( ("Via2" "net") 0 0 nil ) + ( ("Metal3" "drawing") 50 0 t ) + ( ("Metal3" "net") 0 0 nil ) + ( ("Metal3" "pin") 0 0 nil ) + ( ("CapWell" "drawing") 0 0 nil ) + ( ("CapWell" "net") 0 0 nil ) + ( ("SiBlock" "drawing") 0 0 nil ) + ( ("SiBlock" "net") 0 0 nil ) + ( ("HR" "drawing") 0 0 nil ) + ( ("HR" "net") 0 0 nil ) + ) ;streamLayers + + viaLayers( + ;( layer1 viaLayer layer2 ) + ;( ------ -------- ------ ) + ( Metal2 Via2 Metal3 ) + ( Metal1 Via Metal2 ) + ( Active ActX Poly1 ) + ( Poly1 P1Con Metal1 ) + ( Poly2 P2Con Metal1 ) + ) ;viaLayers + +) ;layerRules + + +;******************************** +; PHYSICAL RULES +;******************************** + +physicalRules( + orderedSpacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minEnclosure "prBoundary" "Metal1" 0.0 ) + ( minEnclosure "Metal2" "Via" 1.0 ) + ( minEnclosure "Metal1" "Via" 1.0 ) + ( minEnclosure "Metal1" "P1Con" 1.0 ) + ( minEnclosure "Metal1" "ActX" 1.0 ) + ( minEnclosure "Nselect" "Active" 2.0 ) + ( minEnclosure "Pselect" "Active" 2.0 ) + ( minEnclosure "Active" "ActX" 1.0 ) + ( minEnclosure "Pwell" "Active" 5.0 ) + ( minEnclosure "Nwell" "Active" 5.0 ) + ) ;orderedSpacingRules + + spacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minSpacing "P2Con" 2.0 ) + ( minSpacing "Poly2" 3.0 ) + ( minSpacing "Pwell" 9.0 ) + ( minSpacing "Nwell" 9.0 ) + ( minSpacing "Active" 3.0 ) + ( minSpacing "Pselect" 2.0 ) + ( minSpacing "Nselect" 2.0 ) + ( minSpacing "Poly1" 2.0 ) + ( minSpacing "P1Con" 2.0 ) + ( minSpacing "ActX" 2.0 ) + ( minSpacing "Metal1" 3.0 ) + ( minSpacing "Via" 3.0 ) + ( minSpacing "Via2" 3.0 ) + ( minSpacing "Metal2" 3.0 ) + ( minSpacing "Metal3" 4.0 ) + ( minSpacing "Glass" 75.0 ) + ( minSpacing "XP" 100.0 ) + ( minSpacing "Metal2" 4.0 ) + ( minSpacing "P1Con" "Via" 2.0 ) + ( minSpacing "ActX" "Via" 2.0 ) + ( minSpacing "ActX" "P2Con" 2.0 ) + ( minSpacing "Poly2" "P2Con" 4.0 ) + ( minSpacing "Poly1" "P1Con" 4.0 ) + ( minSpacing "ActX" "P1Con" 2.0 ) + ( minSpacing "Active" "P1Con" 2.0 ) + ( minSpacing "Active" "Poly2" 2.0 ) + ( minSpacing "Poly1" "Poly2" 2.0 ) + ( minSpacing "Active" "Poly1" 2.0 ) + ( minSpacing "ActX" "Poly1" 2.0 ) + ( minSpacing "Pselect" "Nselect" 0.0 ) + ( minSpacing "Nwell" "Pwell" 9.0 ) + ( minWidth "P2Con" 2.0 ) + ( minWidth "Poly2" 3.0 ) + ( minWidth "Pwell" 10.0 ) + ( minWidth "Nwell" 10.0 ) + ( minWidth "Active" 3.0 ) + ( minWidth "Pselect" 2.0 ) + ( minWidth "Nselect" 2.0 ) + ( minWidth "Poly1" 2.0 ) + ( minWidth "P1Con" 2.0 ) + ( minWidth "ActX" 2.0 ) + ( minWidth "Metal1" 4.0 ) + ( minWidth "Via" 2.0 ) + ( minWidth "Metal2" 4.0 ) + ( minWidth "Glass" 75.0 ) + ( minWidth "XP" 100.0 ) + ( minWidth "Metal3" 6.0 ) + ) ;spacingRules + + mfgGridResolution( + ( 1.000000 ) + ) ;mfgGridResolution + +) ;physicalRules + + +;******************************** +; ELECTRICAL RULES +;******************************** + +electricalRules( + characterizationRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( areaCap "P2Con" 0.0 ) + ( areaCap "Poly2" 0.0 ) + ( areaCap "Active" 0.0 ) + ( areaCap "Poly1" 6e-05 ) + ( areaCap "P1Con" 0.0 ) + ( areaCap "ActX" 0.0 ) + ( areaCap "Metal1" 2.6e-05 ) + ( areaCap "Via" 0.0 ) + ( areaCap "Metal2" 1.6e-05 ) + ( edgeCapacitance "P2Con" 0.0 ) + ( edgeCapacitance "Poly2" 0.0 ) + ( edgeCapacitance "Active" 0.0 ) + ( edgeCapacitance "Poly1" 0.0 ) + ( edgeCapacitance "P1Con" 0.0 ) + ( edgeCapacitance "ActX" 0.0 ) + ( edgeCapacitance "Metal1" 0.0 ) + ( edgeCapacitance "Via" 0.0 ) + ( edgeCapacitance "Metal2" 0.0 ) + ( sheetRes "P2Con" 0.0 ) + ( sheetRes "Poly2" 0.0 ) + ( sheetRes "Active" 0.0 ) + ( sheetRes "Poly1" 23.0 ) + ( sheetRes "P1Con" 0.0 ) + ( sheetRes "ActX" 0.0 ) + ( sheetRes "Metal1" 0.04 ) + ( sheetRes "Via" 0.0 ) + ( sheetRes "Metal2" 0.07 ) + ( currentDensity "P2Con" 1.0 ) + ( currentDensity "Poly2" 1.0 ) + ( currentDensity "Active" 1.0 ) + ( currentDensity "Poly1" 1.0 ) + ( currentDensity "P1Con" 1.0 ) + ( currentDensity "ActX" 1.0 ) + ( currentDensity "Metal1" 1.0 ) + ( currentDensity "Via" 1.0 ) + ( currentDensity "Metal2" 1.0 ) + ) ;characterizationRules + +) ;electricalRules + + +;******************************** +; LAYOUT EDITOR RULES +;******************************** +; specifies the ordering of the layers in the LSW + +leRules( + leLswLayers( + ;( layer purpose ) + ; ----- ------- ) + ( Nwell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( instance drawing ) + ( text drawing ) + ( CapWell drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Pbase drawing ) + ( Resistor drawing ) + ( Capacitor drawing ) + ( Diode drawing ) + ( Glass drawing ) + ( XP drawing ) + + ) ;leLswLayers +) ;leRules + + +;******************************** +; VIRTUOSO XL RULES +;******************************** +; specifies the ordering of the layers in the LSW + +lxRules( + lxExtractLayers( + (Metal1 Metal2 Metal3) + ) ;lxExtractLayers +) ;lxRules + diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 15278c7b..882e16d5 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -9,7 +9,7 @@ import os from design_rules import * """ -File containing the process technology parameters for SCMOS 3me, subm, 180nm. +File containing the process technology parameters for SCMOS 4m, 0.35um """ #GDS file info From aca46beb743489a770e3a4b30f646c76aab70171 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 8 May 2019 16:17:19 -0700 Subject: [PATCH 02/11] Add multiport bitcell spice --- technology/scn3me_subm/sp_lib/cell_1rw_1r.sp | 14 ++++++++++++++ technology/scn3me_subm/sp_lib/cell_1w_1r.sp | 14 ++++++++++++++ .../scn3me_subm/sp_lib/replica_cell_1rw_1r.sp | 14 ++++++++++++++ .../scn3me_subm/sp_lib/replica_cell_1w_1r.sp | 14 ++++++++++++++ 4 files changed, 56 insertions(+) create mode 100644 technology/scn3me_subm/sp_lib/cell_1rw_1r.sp create mode 100644 technology/scn3me_subm/sp_lib/cell_1w_1r.sp create mode 100644 technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp create mode 100644 technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp diff --git a/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp b/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp new file mode 100644 index 00000000..1c4c1bc3 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.6u +MM1 Q Q_bar gnd gnd n w=2.4u l=0.6u +MM0 Q_bar Q gnd gnd n w=2.4u l=0.6u +MM3 Q Q_bar vdd vdd p w=1.2u l=0.6u +MM2 Q_bar Q vdd vdd p w=1.2u l=0.6u +.ENDS + diff --git a/technology/scn3me_subm/sp_lib/cell_1w_1r.sp b/technology/scn3me_subm/sp_lib/cell_1w_1r.sp new file mode 100644 index 00000000..aed7466b --- /dev/null +++ b/technology/scn3me_subm/sp_lib/cell_1w_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.6u +MM1 Q Q_bar gnd gnd n w=2.4u l=0.6u +MM0 Q_bar Q gnd gnd n w=2.4u l=0.6u +MM3 Q Q_bar vdd vdd p w=1.2u l=0.6u +MM2 Q_bar Q vdd vdd p w=1.2u l=0.6u +.ENDS + diff --git a/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp b/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp new file mode 100644 index 00000000..e90dd033 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left vdd gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 vdd wl0 br0 gnd n w=1.2u l=0.6u +MM1 Q vdd gnd gnd n w=2.4u l=0.6u +MM0 vdd Q gnd gnd n w=2.4u l=0.6u +MM3 Q vdd vdd vdd p w=1.2u l=0.6u +MM2 vdd Q vdd vdd p w=1.2u l=0.6u +.ENDS + diff --git a/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp b/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp new file mode 100644 index 00000000..bd2e5eb5 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left vdd gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 vdd wl0 br0 gnd n w=0.8u l=0.6u +MM1 Q vdd gnd gnd n w=2.4u l=0.6u +MM0 vdd Q gnd gnd n w=2.4u l=0.6u +MM3 Q vdd vdd vdd p w=0.6u l=0.6u +MM2 vdd Q vdd vdd p w=0.6u l=0.6u +.ENDS + From 94e736881fdc22242ddfcf829c4edb040421597e Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 8 May 2019 16:19:48 -0700 Subject: [PATCH 03/11] Multiport scn3me_subm has drc errors --- .../gds_lib/{ => incorrect}/cell_1rw_1r.gds | Bin .../gds_lib/{ => incorrect}/cell_1w_1r.gds | Bin .../gds_lib/{ => incorrect}/replica_cell_1rw_1r.gds | Bin .../gds_lib/{ => incorrect}/replica_cell_1w_1r.gds | Bin .../sp_lib/{ => incorrect}/cell_1rw_1r.sp | 0 .../sp_lib/{ => incorrect}/cell_1w_1r.sp | 0 .../sp_lib/{ => incorrect}/replica_cell_1rw_1r.sp | 0 .../sp_lib/{ => incorrect}/replica_cell_1w_1r.sp | 0 8 files changed, 0 insertions(+), 0 deletions(-) rename technology/scn3me_subm/gds_lib/{ => incorrect}/cell_1rw_1r.gds (100%) rename technology/scn3me_subm/gds_lib/{ => incorrect}/cell_1w_1r.gds (100%) rename technology/scn3me_subm/gds_lib/{ => incorrect}/replica_cell_1rw_1r.gds (100%) rename technology/scn3me_subm/gds_lib/{ => incorrect}/replica_cell_1w_1r.gds (100%) rename technology/scn3me_subm/sp_lib/{ => incorrect}/cell_1rw_1r.sp (100%) rename technology/scn3me_subm/sp_lib/{ => incorrect}/cell_1w_1r.sp (100%) rename technology/scn3me_subm/sp_lib/{ => incorrect}/replica_cell_1rw_1r.sp (100%) rename technology/scn3me_subm/sp_lib/{ => incorrect}/replica_cell_1w_1r.sp (100%) diff --git a/technology/scn3me_subm/gds_lib/cell_1rw_1r.gds b/technology/scn3me_subm/gds_lib/incorrect/cell_1rw_1r.gds similarity index 100% rename from technology/scn3me_subm/gds_lib/cell_1rw_1r.gds rename to technology/scn3me_subm/gds_lib/incorrect/cell_1rw_1r.gds diff --git a/technology/scn3me_subm/gds_lib/cell_1w_1r.gds b/technology/scn3me_subm/gds_lib/incorrect/cell_1w_1r.gds similarity index 100% rename from technology/scn3me_subm/gds_lib/cell_1w_1r.gds rename to technology/scn3me_subm/gds_lib/incorrect/cell_1w_1r.gds diff --git a/technology/scn3me_subm/gds_lib/replica_cell_1rw_1r.gds b/technology/scn3me_subm/gds_lib/incorrect/replica_cell_1rw_1r.gds similarity index 100% rename from technology/scn3me_subm/gds_lib/replica_cell_1rw_1r.gds rename to technology/scn3me_subm/gds_lib/incorrect/replica_cell_1rw_1r.gds diff --git a/technology/scn3me_subm/gds_lib/replica_cell_1w_1r.gds b/technology/scn3me_subm/gds_lib/incorrect/replica_cell_1w_1r.gds similarity index 100% rename from technology/scn3me_subm/gds_lib/replica_cell_1w_1r.gds rename to technology/scn3me_subm/gds_lib/incorrect/replica_cell_1w_1r.gds diff --git a/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp b/technology/scn3me_subm/sp_lib/incorrect/cell_1rw_1r.sp similarity index 100% rename from technology/scn3me_subm/sp_lib/cell_1rw_1r.sp rename to technology/scn3me_subm/sp_lib/incorrect/cell_1rw_1r.sp diff --git a/technology/scn3me_subm/sp_lib/cell_1w_1r.sp b/technology/scn3me_subm/sp_lib/incorrect/cell_1w_1r.sp similarity index 100% rename from technology/scn3me_subm/sp_lib/cell_1w_1r.sp rename to technology/scn3me_subm/sp_lib/incorrect/cell_1w_1r.sp diff --git a/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp b/technology/scn3me_subm/sp_lib/incorrect/replica_cell_1rw_1r.sp similarity index 100% rename from technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp rename to technology/scn3me_subm/sp_lib/incorrect/replica_cell_1rw_1r.sp diff --git a/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp b/technology/scn3me_subm/sp_lib/incorrect/replica_cell_1w_1r.sp similarity index 100% rename from technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp rename to technology/scn3me_subm/sp_lib/incorrect/replica_cell_1w_1r.sp From eb40e2fdae2fa0e0f5b60377713aac4a841e6b91 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 21 May 2019 09:23:25 -0700 Subject: [PATCH 04/11] Added remaining gds/sp files for multiport in scn3m. --- .../{mag_lib => gds_lib}/cell_1rw_1r.gds | Bin 6330 -> 6330 bytes technology/scn3me_subm/gds_lib/cell_1w_1r.gds | Bin 0 -> 6326 bytes .../replica_cell_1rw_1r.gds | Bin 6282 -> 6282 bytes .../gds_lib/replica_cell_1w_1r.gds | Bin 0 -> 6278 bytes technology/scn3me_subm/sp_lib/cell_1rw_1r.sp | 14 ++++++++++++++ technology/scn3me_subm/sp_lib/cell_1w_1r.sp | 14 ++++++++++++++ .../scn3me_subm/sp_lib/replica_cell_1rw_1r.sp | 14 ++++++++++++++ .../scn3me_subm/sp_lib/replica_cell_1w_1r.sp | 14 ++++++++++++++ 8 files changed, 56 insertions(+) rename technology/scn3me_subm/{mag_lib => gds_lib}/cell_1rw_1r.gds (97%) create mode 100644 technology/scn3me_subm/gds_lib/cell_1w_1r.gds rename technology/scn3me_subm/{mag_lib => gds_lib}/replica_cell_1rw_1r.gds (97%) create mode 100644 technology/scn3me_subm/gds_lib/replica_cell_1w_1r.gds create mode 100644 technology/scn3me_subm/sp_lib/cell_1rw_1r.sp create mode 100644 technology/scn3me_subm/sp_lib/cell_1w_1r.sp create mode 100644 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zAG+A`5AyYA{_y_8-CyLrhevF^|E%-B@P6`(r~1h+x}NvH;n(?@pLeu_F1GgHhMzpq zckXH;?>*?E>tTG>3_kKF;zJipe&Vp^St}y#s9#li7@u;^Db5a&cGPZFUi8y<;)}GS zcA@K`pYJT^9A1(Bql>PGe%`S-d+>|2gD#fl4-bFT6`6NFi~c!`Pd|yB|KUX!y)5*1 z&ZPHD_IutpA#I_Ht@qb;>kl96PsCT{{WeQ}-M^SW&OFFoUbufX;`7c*Ecz|d7j)6} zaQv)uyuAO4^dDVxJ@hkX{-`VFpR4lF&$&q*e)|#eql>PGe&(6HweL^p`mQx@tI9(^^NWxBuBdqzT@U@tGY|7G z(r Date: Tue, 21 May 2019 13:59:44 -0700 Subject: [PATCH 05/11] Add 1w 1r magic just copied --- technology/scn4m_subm/mag_lib/cell_1w_1r.mag | 142 +++++++++++++++++ .../scn4m_subm/mag_lib/replica_cell_1w_1r.mag | 145 ++++++++++++++++++ 2 files changed, 287 insertions(+) create mode 100644 technology/scn4m_subm/mag_lib/cell_1w_1r.mag create mode 100644 technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag diff --git a/technology/scn4m_subm/mag_lib/cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/cell_1w_1r.mag new file mode 100644 index 00000000..9aec1c5d --- /dev/null +++ b/technology/scn4m_subm/mag_lib/cell_1w_1r.mag @@ -0,0 +1,142 @@ +magic +tech scmos +timestamp 1542220294 +<< nwell >> +rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 25 17 29 23 +<< pdcontact >> +rect 17 54 21 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 6 33 9 37 +rect 45 33 48 37 +rect 25 23 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< pdm12contact >> +rect 25 54 29 58 +<< ndm12contact >> +rect 9 17 13 21 +rect 41 17 45 21 +<< nsm12contact >> +rect 25 68 29 72 +<< metal2 >> +rect 2 37 6 72 +rect 2 0 6 33 +rect 9 21 13 72 +rect 25 58 29 68 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 72 +rect 41 0 45 17 +rect 48 37 52 72 +rect 48 0 52 33 +<< comment >> +rect 0 0 54 70 +<< labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +<< end >> diff --git a/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag new file mode 100644 index 00000000..f215ff04 --- /dev/null +++ b/technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag @@ -0,0 +1,145 @@ +magic +tech scmos +timestamp 1542221056 +<< nwell >> +rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 29 54 33 58 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 6 33 9 37 +rect 45 33 48 37 +rect 25 23 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 +<< metal2 >> +rect 2 37 6 72 +rect 2 0 6 33 +rect 9 21 13 72 +rect 25 58 29 68 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 72 +rect 41 0 45 17 +rect 48 37 52 72 +rect 48 0 52 33 +<< comment >> +rect 0 0 54 70 +<< labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +<< end >> From 9bb5041d93f26f199c3782700f3a42fcb3487895 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 26 May 2019 17:05:00 -0700 Subject: [PATCH 06/11] Fix pc to p DRC in scn3me_subm --- .../scn3me_subm/gds_lib/cell_1rw_1r.gds | Bin 6330 -> 6458 bytes technology/scn3me_subm/gds_lib/cell_1w_1r.gds | Bin 6326 -> 6454 bytes .../gds_lib/replica_cell_1rw_1r.gds | Bin 6282 -> 6410 bytes .../gds_lib/replica_cell_1w_1r.gds | Bin 6278 -> 6406 bytes .../scn3me_subm/mag_lib/cell_1rw_1r.mag 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-rect 0 46 54 75 +rect 0 48 54 77 << pwell >> -rect 0 0 54 46 +rect 0 0 54 48 << ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 +rect 14 34 16 38 +rect 22 30 24 38 +rect 30 30 32 38 +rect 38 34 40 38 rect 14 17 16 23 rect 22 17 24 23 rect 30 17 32 23 rect 38 17 40 23 << ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 +rect 22 56 24 59 +rect 30 56 32 59 << ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 +rect 13 34 14 38 +rect 16 34 17 38 +rect 21 34 22 38 +rect 17 30 22 34 +rect 24 30 25 38 +rect 29 30 30 38 +rect 32 34 33 38 +rect 37 34 38 38 +rect 40 34 41 38 +rect 32 30 37 34 rect 9 21 14 23 rect 13 17 14 21 rect 16 17 22 23 @@ -37,65 +37,76 @@ rect 32 17 38 23 rect 40 21 45 23 rect 40 17 41 21 << pdiffusion >> -rect 21 54 22 57 -rect 24 54 25 57 -rect 29 54 30 57 -rect 32 54 33 57 +rect 21 56 22 59 +rect 24 56 25 59 +rect 29 56 30 59 +rect 32 56 33 59 << ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 +rect 9 34 13 38 +rect 17 34 21 38 +rect 25 30 29 38 +rect 33 34 37 38 +rect 41 34 45 38 +rect 9 17 13 21 rect 25 17 29 23 +rect 41 17 45 21 << pdcontact >> -rect 17 54 21 58 -rect 33 54 37 58 +rect 17 56 21 60 +rect 25 56 29 60 +rect 33 56 37 60 << psubstratepcontact >> rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 70 29 74 << polysilicon >> -rect 22 57 24 60 -rect 30 57 32 60 -rect 22 44 24 54 -rect 30 51 32 54 -rect 31 47 32 51 -rect 14 37 16 44 -rect 22 40 23 44 -rect 22 37 24 40 -rect 30 37 32 47 -rect 38 37 40 44 -rect 14 31 16 33 -rect 38 31 40 33 +rect 22 59 24 62 +rect 30 59 32 62 +rect 22 45 24 56 +rect 30 53 32 56 +rect 13 41 16 45 +rect 14 38 16 41 +rect 22 38 24 41 +rect 30 38 32 49 +rect 38 41 41 45 +rect 38 38 40 41 +rect 14 32 16 34 +rect 38 32 40 34 rect 14 23 16 24 -rect 22 23 24 29 -rect 30 23 32 29 +rect 22 23 24 30 +rect 30 23 32 30 rect 38 23 40 24 rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 << polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 +rect 28 49 32 53 +rect 9 41 13 45 +rect 22 41 26 45 +rect 41 41 45 45 rect 12 24 16 28 rect 38 24 42 28 << metal1 >> -rect 0 68 25 72 -rect 29 68 54 72 -rect 0 61 54 65 -rect 10 44 14 61 -rect 17 51 20 54 -rect 17 47 27 51 -rect 17 37 20 47 -rect 34 44 37 54 -rect 27 40 37 44 -rect 40 44 44 61 -rect 34 37 37 40 -rect 6 33 9 37 -rect 45 33 48 37 -rect 25 23 29 29 +rect 0 70 25 74 +rect 29 70 54 74 +rect 0 63 54 67 +rect 6 45 10 63 +rect 16 56 17 60 +rect 37 56 38 60 +rect 16 53 20 56 +rect 16 49 28 53 +rect 6 41 9 45 +rect 16 38 19 49 +rect 35 45 38 56 +rect 44 45 48 63 +rect 26 41 38 45 +rect 45 41 48 45 +rect 35 38 38 41 +rect 6 34 9 38 +rect 16 34 17 38 +rect 37 34 38 38 +rect 45 34 48 38 +rect 25 23 29 30 rect 25 13 29 17 rect 0 9 25 13 rect 29 9 54 13 @@ -103,40 +114,37 @@ rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 << m2contact >> -rect 2 33 6 37 -rect 48 33 52 37 +rect 25 70 29 74 +rect 25 56 29 60 +rect 2 34 6 38 +rect 48 34 52 38 rect 16 24 20 28 rect 34 24 38 28 -rect 16 2 20 6 -rect 34 2 38 6 -<< pdm12contact >> -rect 25 54 29 58 -<< ndm12contact >> rect 9 17 13 21 rect 41 17 45 21 -<< nsm12contact >> -rect 25 68 29 72 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> -rect 2 37 6 72 -rect 2 0 6 33 -rect 9 21 13 72 -rect 25 58 29 68 +rect 2 38 6 74 +rect 2 0 6 34 +rect 9 21 13 74 +rect 25 60 29 70 rect 9 0 13 17 rect 16 6 20 24 rect 34 6 38 24 -rect 41 21 45 72 +rect 41 21 45 74 rect 41 0 45 17 -rect 48 37 52 72 -rect 48 0 52 33 +rect 48 38 52 74 +rect 48 0 52 34 << comment >> -rect 0 0 54 70 +rect 0 0 54 72 << labels >> -rlabel metal1 19 63 19 63 1 wl0 -rlabel metal1 19 70 19 70 5 vdd rlabel metal1 27 4 27 4 1 wl1 rlabel psubstratepcontact 27 11 27 11 1 gnd rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel metal1 19 72 19 72 5 vdd +rlabel metal1 19 65 19 65 1 wl0 << end >> diff --git a/technology/scn3me_subm/mag_lib/cell_1w_1r.mag b/technology/scn3me_subm/mag_lib/cell_1w_1r.mag new file mode 100644 index 00000000..e87557e9 --- /dev/null +++ b/technology/scn3me_subm/mag_lib/cell_1w_1r.mag @@ -0,0 +1,150 @@ +magic +tech scmos +timestamp 1558915277 +<< nwell >> +rect 0 48 54 77 +<< pwell >> +rect 0 0 54 48 +<< ntransistor >> +rect 14 34 16 38 +rect 22 30 24 38 +rect 30 30 32 38 +rect 38 34 40 38 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 56 24 59 +rect 30 56 32 59 +<< ndiffusion >> +rect 13 34 14 38 +rect 16 34 17 38 +rect 21 34 22 38 +rect 17 30 22 34 +rect 24 30 25 38 +rect 29 30 30 38 +rect 32 34 33 38 +rect 37 34 38 38 +rect 40 34 41 38 +rect 32 30 37 34 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 56 22 59 +rect 24 56 25 59 +rect 29 56 30 59 +rect 32 56 33 59 +<< ndcontact >> +rect 9 34 13 38 +rect 17 34 21 38 +rect 25 30 29 38 +rect 33 34 37 38 +rect 41 34 45 38 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 56 21 60 +rect 25 56 29 60 +rect 33 56 37 60 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 70 29 74 +<< polysilicon >> +rect 22 59 24 62 +rect 30 59 32 62 +rect 22 45 24 56 +rect 30 53 32 56 +rect 13 41 16 45 +rect 14 38 16 41 +rect 22 38 24 41 +rect 30 38 32 49 +rect 38 41 41 45 +rect 38 38 40 41 +rect 14 32 16 34 +rect 38 32 40 34 +rect 14 23 16 24 +rect 22 23 24 30 +rect 30 23 32 30 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 28 49 32 53 +rect 9 41 13 45 +rect 22 41 26 45 +rect 41 41 45 45 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 70 25 74 +rect 29 70 54 74 +rect 0 63 54 67 +rect 6 45 10 63 +rect 16 56 17 60 +rect 37 56 38 60 +rect 16 53 20 56 +rect 16 49 28 53 +rect 6 41 9 45 +rect 16 38 19 49 +rect 35 45 38 56 +rect 44 45 48 63 +rect 26 41 38 45 +rect 45 41 48 45 +rect 35 38 38 41 +rect 6 34 9 38 +rect 16 34 17 38 +rect 37 34 38 38 +rect 45 34 48 38 +rect 25 23 29 30 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 25 70 29 74 +rect 25 56 29 60 +rect 2 34 6 38 +rect 48 34 52 38 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 +<< metal2 >> +rect 2 38 6 74 +rect 2 0 6 34 +rect 9 21 13 74 +rect 25 60 29 70 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 74 +rect 41 0 45 17 +rect 48 38 52 74 +rect 48 0 52 34 +<< comment >> +rect 0 0 54 72 +<< labels >> +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +rlabel metal1 19 72 19 72 5 vdd +rlabel metal1 19 65 19 65 1 wl0 +<< end >> diff --git a/technology/scn3me_subm/mag_lib/convertall.sh b/technology/scn3me_subm/mag_lib/convertall.sh index f5e2482c..43de584f 100755 --- a/technology/scn3me_subm/mag_lib/convertall.sh +++ b/technology/scn3me_subm/mag_lib/convertall.sh @@ -11,4 +11,12 @@ load tri_gate gds write tri_gate.gds load write_driver gds write write_driver.gds +load replica_cell_1w_1r +gds write replica_cell_1w_1r +load replica_cell_1rw_1r +gds write replica_cell_1rw_1r +load cell_1rw_1r +gds write cell_1rw_1r +load cell_1w_1r +gds write cell_1w_1r EOF diff --git a/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag b/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag index f215ff04..48a3f4c1 100644 --- a/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag +++ b/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag @@ -1,33 +1,33 @@ magic tech scmos -timestamp 1542221056 +timestamp 1558915332 << nwell >> -rect 0 46 54 75 +rect 0 48 54 77 << pwell >> -rect 0 0 54 46 +rect 0 0 54 48 << ntransistor >> -rect 14 33 16 37 -rect 22 29 24 37 -rect 30 29 32 37 -rect 38 33 40 37 +rect 14 34 16 38 +rect 22 30 24 38 +rect 30 30 32 38 +rect 38 34 40 38 rect 14 17 16 23 rect 22 17 24 23 rect 30 17 32 23 rect 38 17 40 23 << ptransistor >> -rect 22 54 24 57 -rect 30 54 32 57 +rect 22 56 24 59 +rect 30 56 32 59 << ndiffusion >> -rect 13 33 14 37 -rect 16 33 17 37 -rect 21 33 22 37 -rect 17 29 22 33 -rect 24 29 25 37 -rect 29 29 30 37 -rect 32 33 33 37 -rect 37 33 38 37 -rect 40 33 41 37 -rect 32 29 37 33 +rect 13 34 14 38 +rect 16 34 17 38 +rect 21 34 22 38 +rect 17 30 22 34 +rect 24 30 25 38 +rect 29 30 30 38 +rect 32 34 33 38 +rect 37 34 38 38 +rect 40 34 41 38 +rect 32 30 37 34 rect 9 21 14 23 rect 13 17 14 21 rect 16 17 22 23 @@ -37,71 +37,77 @@ rect 32 17 38 23 rect 40 21 45 23 rect 40 17 41 21 << pdiffusion >> -rect 21 54 22 57 -rect 24 54 25 57 -rect 29 54 30 57 -rect 32 54 33 57 +rect 21 56 22 59 +rect 24 56 25 59 +rect 29 56 30 59 +rect 32 56 33 59 << ndcontact >> -rect 9 33 13 37 -rect 17 33 21 37 -rect 25 29 29 37 -rect 33 33 37 37 -rect 41 33 45 37 +rect 9 34 13 38 +rect 17 34 21 38 +rect 25 30 29 38 +rect 33 34 37 38 +rect 41 34 45 38 rect 9 17 13 21 rect 25 17 29 23 rect 41 17 45 21 << pdcontact >> -rect 17 54 21 58 -rect 25 54 29 58 -rect 33 54 37 58 +rect 17 56 21 60 +rect 25 56 29 60 +rect 33 56 37 60 << psubstratepcontact >> rect 25 9 29 13 << nsubstratencontact >> -rect 25 68 29 72 +rect 25 70 29 74 << polysilicon >> -rect 22 57 24 60 -rect 30 57 32 60 -rect 22 44 24 54 -rect 30 51 32 54 -rect 31 47 32 51 -rect 14 37 16 44 -rect 22 40 23 44 -rect 22 37 24 40 -rect 30 37 32 47 -rect 38 37 40 44 -rect 14 31 16 33 -rect 38 31 40 33 +rect 22 59 24 62 +rect 30 59 32 62 +rect 22 45 24 56 +rect 30 53 32 56 +rect 13 41 16 45 +rect 14 38 16 41 +rect 22 38 24 41 +rect 30 38 32 49 +rect 38 41 41 45 +rect 38 38 40 41 +rect 14 32 16 34 +rect 38 32 40 34 rect 14 23 16 24 -rect 22 23 24 29 -rect 30 23 32 29 +rect 22 23 24 30 +rect 30 23 32 30 rect 38 23 40 24 rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 << polycontact >> -rect 27 47 31 51 -rect 10 40 14 44 -rect 23 40 27 44 -rect 40 40 44 44 +rect 28 49 32 53 +rect 9 41 13 45 +rect 22 41 26 45 +rect 41 41 45 45 rect 12 24 16 28 rect 38 24 42 28 << metal1 >> -rect 0 68 25 72 -rect 29 68 54 72 -rect 0 61 54 65 -rect 10 44 14 61 -rect 29 54 33 58 -rect 17 51 20 54 -rect 17 47 27 51 -rect 17 37 20 47 -rect 34 44 37 54 -rect 27 40 37 44 -rect 40 44 44 61 -rect 34 37 37 40 -rect 6 33 9 37 -rect 45 33 48 37 -rect 25 23 29 29 +rect 0 70 25 74 +rect 29 70 54 74 +rect 0 63 54 67 +rect 6 45 10 63 +rect 16 56 17 60 +rect 29 56 33 60 +rect 37 56 38 60 +rect 16 53 20 56 +rect 16 49 28 53 +rect 6 41 9 45 +rect 16 38 19 49 +rect 35 45 38 56 +rect 44 45 48 63 +rect 26 41 38 45 +rect 45 41 48 45 +rect 35 38 38 41 +rect 6 34 9 38 +rect 16 34 17 38 +rect 37 34 38 38 +rect 45 34 48 38 +rect 25 23 29 30 rect 25 13 29 17 rect 0 9 25 13 rect 29 9 54 13 @@ -109,10 +115,10 @@ rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 << m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 -rect 2 33 6 37 -rect 48 33 52 37 +rect 25 70 29 74 +rect 25 56 29 60 +rect 2 34 6 38 +rect 48 34 52 38 rect 16 24 20 28 rect 34 24 38 28 rect 9 17 13 21 @@ -120,26 +126,26 @@ rect 41 17 45 21 rect 16 2 20 6 rect 34 2 38 6 << metal2 >> -rect 2 37 6 72 -rect 2 0 6 33 -rect 9 21 13 72 -rect 25 58 29 68 +rect 2 38 6 74 +rect 2 0 6 34 +rect 9 21 13 74 +rect 25 60 29 70 rect 9 0 13 17 rect 16 6 20 24 rect 34 6 38 24 -rect 41 21 45 72 +rect 41 21 45 74 rect 41 0 45 17 -rect 48 37 52 72 -rect 48 0 52 33 +rect 48 38 52 74 +rect 48 0 52 34 << comment >> -rect 0 0 54 70 +rect 0 0 54 72 << labels >> -rlabel metal1 19 63 19 63 1 wl0 -rlabel metal1 19 70 19 70 5 vdd rlabel metal1 27 4 27 4 1 wl1 rlabel psubstratepcontact 27 11 27 11 1 gnd rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 +rlabel metal1 19 72 19 72 5 vdd +rlabel metal1 19 65 19 65 1 wl0 << end >> diff --git a/technology/scn3me_subm/mag_lib/replica_cell_1w_1r.mag b/technology/scn3me_subm/mag_lib/replica_cell_1w_1r.mag new file mode 100644 index 00000000..48a3f4c1 --- /dev/null +++ b/technology/scn3me_subm/mag_lib/replica_cell_1w_1r.mag @@ -0,0 +1,151 @@ +magic +tech scmos +timestamp 1558915332 +<< nwell >> +rect 0 48 54 77 +<< pwell >> +rect 0 0 54 48 +<< ntransistor >> +rect 14 34 16 38 +rect 22 30 24 38 +rect 30 30 32 38 +rect 38 34 40 38 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 56 24 59 +rect 30 56 32 59 +<< ndiffusion >> +rect 13 34 14 38 +rect 16 34 17 38 +rect 21 34 22 38 +rect 17 30 22 34 +rect 24 30 25 38 +rect 29 30 30 38 +rect 32 34 33 38 +rect 37 34 38 38 +rect 40 34 41 38 +rect 32 30 37 34 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 56 22 59 +rect 24 56 25 59 +rect 29 56 30 59 +rect 32 56 33 59 +<< ndcontact >> +rect 9 34 13 38 +rect 17 34 21 38 +rect 25 30 29 38 +rect 33 34 37 38 +rect 41 34 45 38 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 56 21 60 +rect 25 56 29 60 +rect 33 56 37 60 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 70 29 74 +<< polysilicon >> +rect 22 59 24 62 +rect 30 59 32 62 +rect 22 45 24 56 +rect 30 53 32 56 +rect 13 41 16 45 +rect 14 38 16 41 +rect 22 38 24 41 +rect 30 38 32 49 +rect 38 41 41 45 +rect 38 38 40 41 +rect 14 32 16 34 +rect 38 32 40 34 +rect 14 23 16 24 +rect 22 23 24 30 +rect 30 23 32 30 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 28 49 32 53 +rect 9 41 13 45 +rect 22 41 26 45 +rect 41 41 45 45 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 70 25 74 +rect 29 70 54 74 +rect 0 63 54 67 +rect 6 45 10 63 +rect 16 56 17 60 +rect 29 56 33 60 +rect 37 56 38 60 +rect 16 53 20 56 +rect 16 49 28 53 +rect 6 41 9 45 +rect 16 38 19 49 +rect 35 45 38 56 +rect 44 45 48 63 +rect 26 41 38 45 +rect 45 41 48 45 +rect 35 38 38 41 +rect 6 34 9 38 +rect 16 34 17 38 +rect 37 34 38 38 +rect 45 34 48 38 +rect 25 23 29 30 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 25 70 29 74 +rect 25 56 29 60 +rect 2 34 6 38 +rect 48 34 52 38 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 +rect 16 2 20 6 +rect 34 2 38 6 +<< metal2 >> +rect 2 38 6 74 +rect 2 0 6 34 +rect 9 21 13 74 +rect 25 60 29 70 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 74 +rect 41 0 45 17 +rect 48 38 52 74 +rect 48 0 52 34 +<< comment >> +rect 0 0 54 72 +<< labels >> +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +rlabel metal1 19 72 19 72 5 vdd +rlabel metal1 19 65 19 65 1 wl0 +<< end >> From 26146b6838881f0d5a42dddba9399bc0489607ff Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 26 May 2019 22:28:16 -0700 Subject: [PATCH 07/11] Fix SCN3ME_SUBM stuff. Update cells to be DRC clean with rule 5.5.b Allow magic for FreePDK45 but not debugged. Revert to older Magic tech file for SCN3ME_SUBM --- compiler/verify/__init__.py | 3 - .../scn3me_subm/gds_lib/cell_1rw_1r.gds | Bin 6458 -> 6394 bytes technology/scn3me_subm/gds_lib/cell_1w_1r.gds | Bin 6454 -> 6390 bytes technology/scn3me_subm/gds_lib/cell_6t.gds | Bin 5916 -> 5916 bytes technology/scn3me_subm/gds_lib/dff.gds | Bin 16622 -> 16622 bytes .../gds_lib/incorrect/cell_1rw_1r.gds | Bin 6330 -> 0 bytes .../gds_lib/incorrect/cell_1w_1r.gds | Bin 8192 -> 0 bytes .../gds_lib/incorrect/replica_cell_1rw_1r.gds | Bin 6282 -> 0 bytes .../gds_lib/incorrect/replica_cell_1w_1r.gds | Bin 8192 -> 0 bytes .../gds_lib/replica_cell_1rw_1r.gds | Bin 6410 -> 6346 bytes .../gds_lib/replica_cell_1w_1r.gds | Bin 6406 -> 6342 bytes .../scn3me_subm/gds_lib/replica_cell_6t.gds | Bin 6060 -> 6060 bytes technology/scn3me_subm/gds_lib/sense_amp.gds | Bin 8312 -> 8312 bytes technology/scn3me_subm/gds_lib/tri_gate.gds | Bin 4576 -> 4576 bytes .../scn3me_subm/gds_lib/write_driver.gds | Bin 11804 -> 11804 bytes .../scn3me_subm/mag_lib/cell_1rw_1r.mag | 56 +- technology/scn3me_subm/mag_lib/cell_1w_1r.mag | 56 +- .../mag_lib/replica_cell_1rw_1r.mag | 56 +- .../mag_lib/replica_cell_1w_1r.mag | 56 +- technology/scn3me_subm/mag_lib/setup.tcl | 10 +- technology/scn3me_subm/sp_lib/cell_1rw_1r.sp | 20 +- technology/scn3me_subm/sp_lib/cell_1w_1r.sp | 20 +- .../scn3me_subm/sp_lib/replica_cell_1rw_1r.sp | 20 +- .../scn3me_subm/sp_lib/replica_cell_1w_1r.sp | 20 +- .../scn3me_subm/tech/SCN3ME_SUBM.30.tech | 1555 ++++------------- technology/scn4m_subm/tech/SCN4M_SUBM.20.tech | 72 +- technology/scn4m_subm/tech/tech.py | 4 +- 27 files changed, 515 insertions(+), 1433 deletions(-) delete mode 100644 technology/scn3me_subm/gds_lib/incorrect/cell_1rw_1r.gds delete mode 100644 technology/scn3me_subm/gds_lib/incorrect/cell_1w_1r.gds delete mode 100644 technology/scn3me_subm/gds_lib/incorrect/replica_cell_1rw_1r.gds delete mode 100644 technology/scn3me_subm/gds_lib/incorrect/replica_cell_1w_1r.gds diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 04fa9746..c7bec114 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -33,9 +33,6 @@ else: OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], OPTS.lvs_name) OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], OPTS.pex_name) -if OPTS.check_lvsdrc and OPTS.tech_name == "freepdk45": - debug.check(OPTS.drc_exe[0]!="magic","Magic does not support FreePDK45 for DRC.") - if OPTS.drc_exe == None: from .none import run_drc,print_drc_stats elif "calibre"==OPTS.drc_exe[0]: diff --git a/technology/scn3me_subm/gds_lib/cell_1rw_1r.gds b/technology/scn3me_subm/gds_lib/cell_1rw_1r.gds index f9cec56965719c38ebb10025fb5ffa5cf8f57f68..a4fea073f7794ef11cbd2daa04f721b08f919b4f 100644 GIT binary patch delta 428 zcmZXOy-EW?6ot=hCUG4i?go==f>;a^P{SrJDbs0TD#1TcL?mo&scp&>X~MjLMG6ZM zrV;T0ti&P@5G+zyr_#o`4C59Sm+x{o=brnLeD6vW;30=~=HU)`)KS4Q;=f&>HI}XL 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delta 37 icmez2@WWw(ICmKXCj$!u4}&3t(L^O(O diff --git a/technology/scn3me_subm/gds_lib/write_driver.gds b/technology/scn3me_subm/gds_lib/write_driver.gds index fdd3ad883b0f7ba91571eb508c5a78e27876802e..0bef7b7973766b293c75f95a3892e39ed2b0dc5f 100644 GIT binary patch delta 37 icmbOeGbd((ICnV%D}xk+AcFvd+(ac)WbVeKUAh31LI*kk delta 37 icmbOeGbd((ICmKXCj$!u4}%c{=R_q_WbVeKUAh2~vj-#q diff --git a/technology/scn3me_subm/mag_lib/cell_1rw_1r.mag b/technology/scn3me_subm/mag_lib/cell_1rw_1r.mag index e87557e9..6a6fbc86 100644 --- a/technology/scn3me_subm/mag_lib/cell_1rw_1r.mag +++ b/technology/scn3me_subm/mag_lib/cell_1rw_1r.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1558915277 +timestamp 1558933786 << nwell >> rect 0 48 54 77 << pwell >> @@ -22,8 +22,10 @@ rect 13 34 14 38 rect 16 34 17 38 rect 21 34 22 38 rect 17 30 22 34 -rect 24 30 25 38 -rect 29 30 30 38 +rect 24 36 30 38 +rect 24 32 25 36 +rect 29 32 30 36 +rect 24 30 30 32 rect 32 34 33 38 rect 37 34 38 38 rect 40 34 41 38 @@ -31,8 +33,10 @@ rect 32 30 37 34 rect 9 21 14 23 rect 13 17 14 21 rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 +rect 24 22 30 23 +rect 24 18 25 22 +rect 29 18 30 22 +rect 24 17 30 18 rect 32 17 38 23 rect 40 21 45 23 rect 40 17 41 21 @@ -44,11 +48,11 @@ rect 32 56 33 59 << ndcontact >> rect 9 34 13 38 rect 17 34 21 38 -rect 25 30 29 38 +rect 25 32 29 36 rect 33 34 37 38 rect 41 34 45 38 rect 9 17 13 21 -rect 25 17 29 23 +rect 25 18 29 22 rect 41 17 45 21 << pdcontact >> rect 17 56 21 60 @@ -57,17 +61,17 @@ rect 33 56 37 60 << psubstratepcontact >> rect 25 9 29 13 << nsubstratencontact >> -rect 25 70 29 74 +rect 37 70 41 74 << polysilicon >> rect 22 59 24 62 rect 30 59 32 62 rect 22 45 24 56 rect 30 53 32 56 -rect 13 41 16 45 +rect 13 41 16 43 rect 14 38 16 41 rect 22 38 24 41 rect 30 38 32 49 -rect 38 41 41 45 +rect 38 41 41 43 rect 38 38 40 41 rect 14 32 16 34 rect 38 32 40 34 @@ -88,26 +92,26 @@ rect 12 24 16 28 rect 38 24 42 28 << metal1 >> rect 0 70 25 74 -rect 29 70 54 74 +rect 29 70 37 74 +rect 41 70 54 74 rect 0 63 54 67 -rect 6 45 10 63 +rect 9 45 13 63 rect 16 56 17 60 rect 37 56 38 60 rect 16 53 20 56 rect 16 49 28 53 -rect 6 41 9 45 rect 16 38 19 49 rect 35 45 38 56 -rect 44 45 48 63 rect 26 41 38 45 -rect 45 41 48 45 +rect 41 45 45 63 rect 35 38 38 41 rect 6 34 9 38 rect 16 34 17 38 +rect 25 36 29 38 rect 37 34 38 38 rect 45 34 48 38 -rect 25 23 29 30 -rect 25 13 29 17 +rect 25 22 29 32 +rect 25 13 29 18 rect 0 9 25 13 rect 29 9 54 13 rect 0 2 16 6 @@ -139,12 +143,14 @@ rect 48 0 52 34 << comment >> rect 0 0 54 72 << labels >> -rlabel metal1 27 4 27 4 1 wl1 -rlabel psubstratepcontact 27 11 27 11 1 gnd -rlabel metal2 4 7 4 7 2 bl0 -rlabel metal2 11 7 11 7 1 bl1 -rlabel metal2 43 7 43 7 1 br1 -rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 72 19 72 5 vdd -rlabel metal1 19 65 19 65 1 wl0 +rlabel metal1 27 4 27 4 4 wl1 +rlabel psubstratepcontact 27 11 27 11 4 gnd +rlabel metal2 4 7 4 7 4 bl0 +rlabel metal2 50 7 50 7 4 br0 +rlabel metal1 19 65 19 65 4 wl0 +rlabel metal2 11 7 11 7 4 bl1 +rlabel metal2 43 7 43 7 4 br1 +rlabel metal1 18 72 18 72 1 vdd +<< properties >> +string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000 << end >> diff --git a/technology/scn3me_subm/mag_lib/cell_1w_1r.mag b/technology/scn3me_subm/mag_lib/cell_1w_1r.mag index e87557e9..6a6fbc86 100644 --- a/technology/scn3me_subm/mag_lib/cell_1w_1r.mag +++ b/technology/scn3me_subm/mag_lib/cell_1w_1r.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1558915277 +timestamp 1558933786 << nwell >> rect 0 48 54 77 << pwell >> @@ -22,8 +22,10 @@ rect 13 34 14 38 rect 16 34 17 38 rect 21 34 22 38 rect 17 30 22 34 -rect 24 30 25 38 -rect 29 30 30 38 +rect 24 36 30 38 +rect 24 32 25 36 +rect 29 32 30 36 +rect 24 30 30 32 rect 32 34 33 38 rect 37 34 38 38 rect 40 34 41 38 @@ -31,8 +33,10 @@ rect 32 30 37 34 rect 9 21 14 23 rect 13 17 14 21 rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 +rect 24 22 30 23 +rect 24 18 25 22 +rect 29 18 30 22 +rect 24 17 30 18 rect 32 17 38 23 rect 40 21 45 23 rect 40 17 41 21 @@ -44,11 +48,11 @@ rect 32 56 33 59 << ndcontact >> rect 9 34 13 38 rect 17 34 21 38 -rect 25 30 29 38 +rect 25 32 29 36 rect 33 34 37 38 rect 41 34 45 38 rect 9 17 13 21 -rect 25 17 29 23 +rect 25 18 29 22 rect 41 17 45 21 << pdcontact >> rect 17 56 21 60 @@ -57,17 +61,17 @@ rect 33 56 37 60 << psubstratepcontact >> rect 25 9 29 13 << nsubstratencontact >> -rect 25 70 29 74 +rect 37 70 41 74 << polysilicon >> rect 22 59 24 62 rect 30 59 32 62 rect 22 45 24 56 rect 30 53 32 56 -rect 13 41 16 45 +rect 13 41 16 43 rect 14 38 16 41 rect 22 38 24 41 rect 30 38 32 49 -rect 38 41 41 45 +rect 38 41 41 43 rect 38 38 40 41 rect 14 32 16 34 rect 38 32 40 34 @@ -88,26 +92,26 @@ rect 12 24 16 28 rect 38 24 42 28 << metal1 >> rect 0 70 25 74 -rect 29 70 54 74 +rect 29 70 37 74 +rect 41 70 54 74 rect 0 63 54 67 -rect 6 45 10 63 +rect 9 45 13 63 rect 16 56 17 60 rect 37 56 38 60 rect 16 53 20 56 rect 16 49 28 53 -rect 6 41 9 45 rect 16 38 19 49 rect 35 45 38 56 -rect 44 45 48 63 rect 26 41 38 45 -rect 45 41 48 45 +rect 41 45 45 63 rect 35 38 38 41 rect 6 34 9 38 rect 16 34 17 38 +rect 25 36 29 38 rect 37 34 38 38 rect 45 34 48 38 -rect 25 23 29 30 -rect 25 13 29 17 +rect 25 22 29 32 +rect 25 13 29 18 rect 0 9 25 13 rect 29 9 54 13 rect 0 2 16 6 @@ -139,12 +143,14 @@ rect 48 0 52 34 << comment >> rect 0 0 54 72 << labels >> -rlabel metal1 27 4 27 4 1 wl1 -rlabel psubstratepcontact 27 11 27 11 1 gnd -rlabel metal2 4 7 4 7 2 bl0 -rlabel metal2 11 7 11 7 1 bl1 -rlabel metal2 43 7 43 7 1 br1 -rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 72 19 72 5 vdd -rlabel metal1 19 65 19 65 1 wl0 +rlabel metal1 27 4 27 4 4 wl1 +rlabel psubstratepcontact 27 11 27 11 4 gnd +rlabel metal2 4 7 4 7 4 bl0 +rlabel metal2 50 7 50 7 4 br0 +rlabel metal1 19 65 19 65 4 wl0 +rlabel metal2 11 7 11 7 4 bl1 +rlabel metal2 43 7 43 7 4 br1 +rlabel metal1 18 72 18 72 1 vdd +<< properties >> +string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000 << end >> diff --git a/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag b/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag index 48a3f4c1..a7387b7e 100644 --- a/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag +++ b/technology/scn3me_subm/mag_lib/replica_cell_1rw_1r.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1558915332 +timestamp 1558933826 << nwell >> rect 0 48 54 77 << pwell >> @@ -22,8 +22,10 @@ rect 13 34 14 38 rect 16 34 17 38 rect 21 34 22 38 rect 17 30 22 34 -rect 24 30 25 38 -rect 29 30 30 38 +rect 24 36 30 38 +rect 24 32 25 36 +rect 29 32 30 36 +rect 24 30 30 32 rect 32 34 33 38 rect 37 34 38 38 rect 40 34 41 38 @@ -31,8 +33,10 @@ rect 32 30 37 34 rect 9 21 14 23 rect 13 17 14 21 rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 +rect 24 22 30 23 +rect 24 18 25 22 +rect 29 18 30 22 +rect 24 17 30 18 rect 32 17 38 23 rect 40 21 45 23 rect 40 17 41 21 @@ -44,11 +48,11 @@ rect 32 56 33 59 << ndcontact >> rect 9 34 13 38 rect 17 34 21 38 -rect 25 30 29 38 +rect 25 32 29 36 rect 33 34 37 38 rect 41 34 45 38 rect 9 17 13 21 -rect 25 17 29 23 +rect 25 18 29 22 rect 41 17 45 21 << pdcontact >> rect 17 56 21 60 @@ -57,17 +61,17 @@ rect 33 56 37 60 << psubstratepcontact >> rect 25 9 29 13 << nsubstratencontact >> -rect 25 70 29 74 +rect 37 70 41 74 << polysilicon >> rect 22 59 24 62 rect 30 59 32 62 rect 22 45 24 56 rect 30 53 32 56 -rect 13 41 16 45 +rect 13 41 16 43 rect 14 38 16 41 rect 22 38 24 41 rect 30 38 32 49 -rect 38 41 41 45 +rect 38 41 41 43 rect 38 38 40 41 rect 14 32 16 34 rect 38 32 40 34 @@ -88,27 +92,27 @@ rect 12 24 16 28 rect 38 24 42 28 << metal1 >> rect 0 70 25 74 -rect 29 70 54 74 +rect 29 70 37 74 +rect 41 70 54 74 rect 0 63 54 67 -rect 6 45 10 63 +rect 9 45 13 63 rect 16 56 17 60 rect 29 56 33 60 rect 37 56 38 60 rect 16 53 20 56 rect 16 49 28 53 -rect 6 41 9 45 rect 16 38 19 49 rect 35 45 38 56 -rect 44 45 48 63 rect 26 41 38 45 -rect 45 41 48 45 +rect 41 45 45 63 rect 35 38 38 41 rect 6 34 9 38 rect 16 34 17 38 +rect 25 36 29 38 rect 37 34 38 38 rect 45 34 48 38 -rect 25 23 29 30 -rect 25 13 29 17 +rect 25 22 29 32 +rect 25 13 29 18 rect 0 9 25 13 rect 29 9 54 13 rect 0 2 16 6 @@ -140,12 +144,14 @@ rect 48 0 52 34 << comment >> rect 0 0 54 72 << labels >> -rlabel metal1 27 4 27 4 1 wl1 -rlabel psubstratepcontact 27 11 27 11 1 gnd -rlabel metal2 4 7 4 7 2 bl0 -rlabel metal2 11 7 11 7 1 bl1 -rlabel metal2 43 7 43 7 1 br1 -rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 72 19 72 5 vdd -rlabel metal1 19 65 19 65 1 wl0 +rlabel metal1 27 4 27 4 4 wl1 +rlabel psubstratepcontact 27 11 27 11 4 gnd +rlabel metal2 4 7 4 7 4 bl0 +rlabel metal2 50 7 50 7 4 br0 +rlabel metal1 19 65 19 65 4 wl0 +rlabel metal2 11 7 11 7 4 bl1 +rlabel metal2 43 7 43 7 4 br1 +rlabel metal1 18 72 18 72 1 vdd +<< properties >> +string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000 << end >> diff --git a/technology/scn3me_subm/mag_lib/replica_cell_1w_1r.mag b/technology/scn3me_subm/mag_lib/replica_cell_1w_1r.mag index 48a3f4c1..a7387b7e 100644 --- a/technology/scn3me_subm/mag_lib/replica_cell_1w_1r.mag +++ b/technology/scn3me_subm/mag_lib/replica_cell_1w_1r.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1558915332 +timestamp 1558933826 << nwell >> rect 0 48 54 77 << pwell >> @@ -22,8 +22,10 @@ rect 13 34 14 38 rect 16 34 17 38 rect 21 34 22 38 rect 17 30 22 34 -rect 24 30 25 38 -rect 29 30 30 38 +rect 24 36 30 38 +rect 24 32 25 36 +rect 29 32 30 36 +rect 24 30 30 32 rect 32 34 33 38 rect 37 34 38 38 rect 40 34 41 38 @@ -31,8 +33,10 @@ rect 32 30 37 34 rect 9 21 14 23 rect 13 17 14 21 rect 16 17 22 23 -rect 24 17 25 23 -rect 29 17 30 23 +rect 24 22 30 23 +rect 24 18 25 22 +rect 29 18 30 22 +rect 24 17 30 18 rect 32 17 38 23 rect 40 21 45 23 rect 40 17 41 21 @@ -44,11 +48,11 @@ rect 32 56 33 59 << ndcontact >> rect 9 34 13 38 rect 17 34 21 38 -rect 25 30 29 38 +rect 25 32 29 36 rect 33 34 37 38 rect 41 34 45 38 rect 9 17 13 21 -rect 25 17 29 23 +rect 25 18 29 22 rect 41 17 45 21 << pdcontact >> rect 17 56 21 60 @@ -57,17 +61,17 @@ rect 33 56 37 60 << psubstratepcontact >> rect 25 9 29 13 << nsubstratencontact >> -rect 25 70 29 74 +rect 37 70 41 74 << polysilicon >> rect 22 59 24 62 rect 30 59 32 62 rect 22 45 24 56 rect 30 53 32 56 -rect 13 41 16 45 +rect 13 41 16 43 rect 14 38 16 41 rect 22 38 24 41 rect 30 38 32 49 -rect 38 41 41 45 +rect 38 41 41 43 rect 38 38 40 41 rect 14 32 16 34 rect 38 32 40 34 @@ -88,27 +92,27 @@ rect 12 24 16 28 rect 38 24 42 28 << metal1 >> rect 0 70 25 74 -rect 29 70 54 74 +rect 29 70 37 74 +rect 41 70 54 74 rect 0 63 54 67 -rect 6 45 10 63 +rect 9 45 13 63 rect 16 56 17 60 rect 29 56 33 60 rect 37 56 38 60 rect 16 53 20 56 rect 16 49 28 53 -rect 6 41 9 45 rect 16 38 19 49 rect 35 45 38 56 -rect 44 45 48 63 rect 26 41 38 45 -rect 45 41 48 45 +rect 41 45 45 63 rect 35 38 38 41 rect 6 34 9 38 rect 16 34 17 38 +rect 25 36 29 38 rect 37 34 38 38 rect 45 34 48 38 -rect 25 23 29 30 -rect 25 13 29 17 +rect 25 22 29 32 +rect 25 13 29 18 rect 0 9 25 13 rect 29 9 54 13 rect 0 2 16 6 @@ -140,12 +144,14 @@ rect 48 0 52 34 << comment >> rect 0 0 54 72 << labels >> -rlabel metal1 27 4 27 4 1 wl1 -rlabel psubstratepcontact 27 11 27 11 1 gnd -rlabel metal2 4 7 4 7 2 bl0 -rlabel metal2 11 7 11 7 1 bl1 -rlabel metal2 43 7 43 7 1 br1 -rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 72 19 72 5 vdd -rlabel metal1 19 65 19 65 1 wl0 +rlabel metal1 27 4 27 4 4 wl1 +rlabel psubstratepcontact 27 11 27 11 4 gnd +rlabel metal2 4 7 4 7 4 bl0 +rlabel metal2 50 7 50 7 4 br0 +rlabel metal1 19 65 19 65 4 wl0 +rlabel metal2 11 7 11 7 4 bl1 +rlabel metal2 43 7 43 7 4 br1 +rlabel metal1 18 72 18 72 1 vdd +<< properties >> +string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000 << end >> diff --git a/technology/scn3me_subm/mag_lib/setup.tcl b/technology/scn3me_subm/mag_lib/setup.tcl index af55a416..01639fe2 100644 --- a/technology/scn3me_subm/mag_lib/setup.tcl +++ b/technology/scn3me_subm/mag_lib/setup.tcl @@ -4,10 +4,12 @@ equate class {-circuit1 nfet} {-circuit2 n} equate class {-circuit1 pfet} {-circuit2 p} # This circuit has symmetries and needs to be flattened to resolve them # or the banks won't pass -flatten class {-circuit1 precharge_array_1} -flatten class {-circuit1 precharge_array_2} -flatten class {-circuit1 precharge_array_3} -flatten class {-circuit1 precharge_array_4} +flatten class {-circuit1 bitcell_array_0} +flatten class {-circuit1 bitcell_array_1} +#flatten class {-circuit1 precharge_array_0} +#flatten class {-circuit1 precharge_array_1} +#flatten class {-circuit1 precharge_array_2} +#flatten class {-circuit1 precharge_array_3} property {-circuit1 nfet} remove as ad ps pd property {-circuit1 pfet} remove as ad ps pd property {-circuit2 n} remove as ad ps pd diff --git a/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp b/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp index 37f25f75..f58867a7 100644 --- a/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp +++ b/technology/scn3me_subm/sp_lib/cell_1rw_1r.sp @@ -1,14 +1,14 @@ .SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u -MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u -MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u -MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u -MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u -MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u -MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u -MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u -MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u -MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.6u +MM1 Q Q_bar gnd gnd n w=2.4u l=0.6u +MM0 Q_bar Q gnd gnd n w=2.4u l=0.6u +MM3 Q Q_bar vdd vdd p w=0.9u l=0.6u +MM2 Q_bar Q vdd vdd p w=0.9u l=0.6u .ENDS diff --git a/technology/scn3me_subm/sp_lib/cell_1w_1r.sp b/technology/scn3me_subm/sp_lib/cell_1w_1r.sp index b40f589a..fe981d6d 100644 --- a/technology/scn3me_subm/sp_lib/cell_1w_1r.sp +++ b/technology/scn3me_subm/sp_lib/cell_1w_1r.sp @@ -1,14 +1,14 @@ .SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u -MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u -MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u -MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u -MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u -MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u -MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u -MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u -MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u -MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.6u +MM1 Q Q_bar gnd gnd n w=2.4u l=0.6u +MM0 Q_bar Q gnd gnd n w=2.4u l=0.6u +MM3 Q Q_bar vdd vdd p w=0.9u l=0.6u +MM2 Q_bar Q vdd vdd p w=0.9u l=0.6u .ENDS diff --git a/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp b/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp index 94bdb75e..a8654c83 100644 --- a/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp +++ b/technology/scn3me_subm/sp_lib/replica_cell_1rw_1r.sp @@ -1,14 +1,14 @@ .SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u -MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u -MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u -MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u -MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u -MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u -MM1 Q vdd gnd gnd n w=1.6u l=0.4u -MM0 vdd Q gnd gnd n w=1.6u l=0.4u -MM3 Q vdd vdd vdd p w=0.6u l=0.4u -MM2 vdd Q vdd vdd p w=0.6u l=0.4u +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left vdd gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 vdd wl0 br0 gnd n w=1.2u l=0.6u +MM1 Q vdd gnd gnd n w=2.4u l=0.6u +MM0 vdd Q gnd gnd n w=2.4u l=0.6u +MM3 Q vdd vdd vdd p w=0.9u l=0.6u +MM2 vdd Q vdd vdd p w=0.9u l=0.6u .ENDS diff --git a/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp b/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp index 6c2d3c1b..5b9c9b18 100644 --- a/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp +++ b/technology/scn3me_subm/sp_lib/replica_cell_1w_1r.sp @@ -1,14 +1,14 @@ .SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u -MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u -MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u -MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u -MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u -MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u -MM1 Q vdd gnd gnd n w=1.6u l=0.4u -MM0 vdd Q gnd gnd n w=1.6u l=0.4u -MM3 Q vdd vdd vdd p w=0.6u l=0.4u -MM2 vdd Q vdd vdd p w=0.6u l=0.4u +MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u +MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u +MM7 RA_to_R_left vdd gnd gnd n w=1.8u l=0.6u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u +MM4 vdd wl0 br0 gnd n w=1.2u l=0.6u +MM1 Q vdd gnd gnd n w=2.4u l=0.6u +MM0 vdd Q gnd gnd n w=2.4u l=0.6u +MM3 Q vdd vdd vdd p w=0.9u l=0.6u +MM2 vdd Q vdd vdd p w=0.9u l=0.6u .ENDS diff --git a/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech b/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech index be511001..bc447205 100644 --- a/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech +++ b/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech @@ -1,10 +1,10 @@ tech - format 32 + format 29 scmos end version - version 2002a + version 2001a description "SCMOS: Submit as technology.lambda: SCN3ME_SUBM.30 [to process: AMIc5]" end @@ -34,8 +34,7 @@ types select nselect,ns select pselect,ps cap electrode,poly2,el,p2 - cap electrodecontact,poly2contact,poly2c,p2c,elc - cap p2m12contact,p2m12c + metal1 electrodecontact,poly2contact,poly2c,p2c,elc cap electrodecap,ecap,poly2cap,p2cap,pcap contact genericpoly2contact,gc2 active ntransistor,nfet @@ -104,12 +103,7 @@ contact psc psd metal1 m2c metal1 metal2 m3c metal2 metal3 - stackable pc m2c pm12contact,pm12c - stackable pdc m2c pdm12contact,pdm12c - stackable psc m2c psm12contact,psm12c,pom12c,pwm12c - stackable ndc m2c ndm12contact,ndm12c - stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c - stackable m2c m3c m123contact,m123c + stackable end styles @@ -147,7 +141,6 @@ styles fapm 1 20 21 34 gv1 55 m2contact 20 21 55 - p2m12contact 14 20 21 32 55 metal2 21 rm2 21 48 prm2 48 @@ -218,10 +211,6 @@ compose paint nsc pwell psc paint poly2 poly ecap erase ecap poly poly2 - paint p2c poly2 p2c - paint p2c ecap p2c - paint p2m12c poly2 p2m12c - paint p2m12c ecap p2m12c paint pad m3 pad compose phr poly2 hr paint hr poly2 phr @@ -246,18 +235,15 @@ end connect nwell,nsc/a,nsd nwell,nsc/a,nsd pwell,psc/a,psd pwell,psc/a,psd - m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m3,fm3,fapm,m3c/m3 m3,fm3,fapm,m3c/m3 ndiff,ndc/a,pdiff,pdc/a ndiff,ndc/a,pdiff,pdc/a poly,fp,nfet,pfet,fet,fapm,pc/a poly,fp,nfet,pfet,fet,fapm,pc/a + poly2,ecap,p2c poly2,ecap,p2c gc2 poly2,ecap,metal1 - p2c poly2,ecap,m1,fm1,fapm,m2c/m1 - p2m12c poly2,ecap,m1,fm1,fapm,m2c/m1,m2,fm2,fapm,m2c/m2,m3c/m2 - poly2,ecap,p2c,p2m12c poly2,ecap,p2c,p2m12c - gc2 poly2,ecap,m1,fm1,fapm,m2c/m1 gc poly,fp,ndiff,pdiff,nsd,psd,m1,fm1,fapm,m2c/m1 - gv1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2,fm2,fapm,m3c/m2 + gv1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2,fm2,fapm,m3c/m2 gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm pad m1,fm1,m2,fm2,m3,fm3 rm1 prm1 @@ -275,12 +261,8 @@ cifoutput style lambda=0.30(p) scalefactor 30 15 + options calma-permissive-labels - # This is a custom section to add bounding boxes in OpenRAM - layer BB bb - labels bb - calma 63 0 - layer CWN nwell,rnw bloat-or pdiff,rpd,pdc/a,pfet * 180 bloat-or nsd,nsc/a * 90 @@ -377,7 +359,7 @@ style lambda=0.30(p) squares 0 60 90 calma 55 0 - layer CCE p2c,p2m12c + layer CCE p2c squares 30 60 90 calma 55 0 @@ -389,7 +371,7 @@ style lambda=0.30(p) squares 0 60 90 calma 25 0 - layer CV1 m2c/m1,p2m12c + layer CV1 m2c/m1 squares 30 60 90 calma 50 0 @@ -431,12 +413,12 @@ style lambda=0.30(p) layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -527,8 +509,8 @@ style lambda=0.30(p) labels hr,phr calma 34 0 - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c + layer CEL poly2,ecap,phr,p2c + labels poly2,ecap,phr,p2c calma 56 0 #CRE/CRM @@ -559,8 +541,8 @@ style lambda=0.30(p) #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 - layer CX comment - labels comment + layer CX comment,bb + labels comment,bb calma 63 0 layer XP pad,xp @@ -606,9 +588,9 @@ style fapm-boxes scalefactor 30 15 - templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c - or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c + or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 or fm3,m3,rm3,m3c/m3 or glass,pad grow 510 @@ -631,9 +613,9 @@ style fapm-stripes # and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box # to be a 1-lambda wide layer 'fb' box -- else you won't get strips! - templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c - or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c + or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 or fm3,m3,rm3,m3c/m3 or glass,pad grow 510 @@ -754,7 +736,7 @@ style lambda=0.30(cp) squares 0 60 90 calma 25 0 - layer CCC p2c,p2m12c + layer CCC p2c squares 30 60 90 calma 25 0 @@ -766,7 +748,7 @@ style lambda=0.30(cp) squares 0 60 90 calma 25 0 - layer CV1 m2c/m1,p2m12c + layer CV1 m2c/m1 squares 30 60 90 calma 50 0 @@ -808,12 +790,12 @@ style lambda=0.30(cp) layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -904,8 +886,8 @@ style lambda=0.30(cp) labels hr,phr calma 34 0 - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c + layer CEL poly2,ecap,phr,p2c + labels poly2,ecap,phr,p2c calma 56 0 #CRE/CRM @@ -936,8 +918,8 @@ style lambda=0.30(cp) #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 - layer CX comment - labels comment + layer CX comment,bb + labels comment,bb calma 63 0 layer XP pad,xp @@ -1034,7 +1016,7 @@ style lambda=0.30(c) squares 0 60 90 calma 25 0 - layer CCC p2c,p2m12c + layer CCC p2c squares 30 60 90 calma 25 0 @@ -1046,7 +1028,7 @@ style lambda=0.30(c) squares 0 60 90 calma 25 0 - layer CV1 m2c/m1,p2m12c + layer CV1 m2c/m1 squares 30 60 90 calma 50 0 @@ -1088,12 +1070,12 @@ style lambda=0.30(c) layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -1184,8 +1166,8 @@ style lambda=0.30(c) labels hr,phr calma 34 0 - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c + layer CEL poly2,ecap,phr,p2c + labels poly2,ecap,phr,p2c calma 56 0 #CRE/CRM @@ -1216,8 +1198,8 @@ style lambda=0.30(c) #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 - layer CX comment - labels comment + layer CX comment,bb + labels comment,bb calma 63 0 layer XP pad,xp @@ -1314,7 +1296,7 @@ style lambda=0.30() squares 0 60 90 calma 55 0 - layer CCE p2c,p2m12c + layer CCE p2c squares 30 60 90 calma 55 0 @@ -1326,7 +1308,7 @@ style lambda=0.30() squares 0 60 90 calma 25 0 - layer CV1 m2c/m1,p2m12c + layer CV1 m2c/m1 squares 30 60 90 calma 50 0 @@ -1368,12 +1350,12 @@ style lambda=0.30() layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -1464,8 +1446,8 @@ style lambda=0.30() labels hr,phr calma 34 0 - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c + layer CEL poly2,ecap,phr,p2c + labels poly2,ecap,phr,p2c calma 56 0 #CRE/CRM @@ -1496,8 +1478,8 @@ style lambda=0.30() #CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 #CRE/CRM calma 70 0 - layer CX comment - labels comment + layer CX comment,bb + labels comment,bb calma 63 0 layer XP pad,xp @@ -1514,7 +1496,7 @@ style lambda=0.30(p) # This is a custom section to add bounding boxes in OpenRAM layer bb BB labels BB - calma 63 0 + calma BB 63 0 layer nwell CWN and-not CWNR @@ -1721,7 +1703,6 @@ layer nwell CWN layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -1735,7 +1716,6 @@ layer nwell CWN layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -1749,7 +1729,6 @@ layer nwell CWN layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -1763,7 +1742,6 @@ layer nwell CWN layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -1777,7 +1755,6 @@ layer nwell CWN layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -1791,7 +1768,6 @@ layer nwell CWN layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA and-not CPS @@ -1805,7 +1781,6 @@ layer nwell CWN layer psc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -1819,128 +1794,6 @@ layer nwell CWN layer psc CAA and CSP and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 and-not CWNR and-not CTA @@ -1971,7 +1824,6 @@ layer nwell CWN calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -1983,7 +1835,6 @@ layer nwell CWN calma CCP 47 * layer pc CCC - and-not CV1 and CPG and-not CPC and-not CEL @@ -1994,82 +1845,6 @@ layer nwell CWN shrink 15 calma CCC 25 * - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - layer gc CCP and-not CPG and-not CPC @@ -2134,11 +1909,6 @@ layer nwell CWN calma CV2 61 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA and-not XP grow 30 and CM2 @@ -2147,32 +1917,6 @@ layer nwell CWN shrink 15 calma CV1 50 * - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - layer m1 CM1 and-not CRM and-not CRF @@ -2219,14 +1963,6 @@ layer nwell CWN labels CMSP calma CMSP 82 * - - - - - - - - layer fp 100 calma 100 100 * @@ -2249,8 +1985,6 @@ layer nwell CWN calma 110 110 * layer m3c CV2 - - and-not CV1 and-not XP grow 30 and CM3 @@ -2259,7 +1993,6 @@ layer nwell CWN shrink 15 calma CV2 61 * - layer m3 CM3 and-not CRM and-not CRT @@ -2329,6 +2062,20 @@ layer nwell CWN and-not CRE calma CRG2 68 * + layer elc CCE + grow 30 + and CM1 + and CEL + labels CM1 + calma CCE 55 * + + layer elc CCC + grow 30 + and CM1 + and CEL + labels CM1 + calma CCC 25 * + layer comment CX labels CX calma CX 63 * @@ -2348,6 +2095,11 @@ layer nwell CWN style lambda=0.30(s) scalefactor 30 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -2554,7 +2306,6 @@ style lambda=0.30(s) layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -2568,7 +2319,6 @@ style lambda=0.30(s) layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -2582,7 +2332,6 @@ style lambda=0.30(s) layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -2596,7 +2345,6 @@ style lambda=0.30(s) layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -2610,7 +2358,6 @@ style lambda=0.30(s) layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -2624,7 +2371,6 @@ style lambda=0.30(s) layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA and-not CPS @@ -2638,7 +2384,6 @@ style lambda=0.30(s) layer psc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -2652,128 +2397,6 @@ style lambda=0.30(s) layer psc CAA and CSP and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 and-not CWNR and-not CTA @@ -2804,7 +2427,6 @@ style lambda=0.30(s) calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -2816,7 +2438,6 @@ style lambda=0.30(s) calma CCP 47 * layer pc CCC - and-not CV1 and CPG and-not CPC and-not CEL @@ -2827,82 +2448,6 @@ style lambda=0.30(s) shrink 15 calma CCC 25 * - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - layer gc CCP and-not CPG and-not CPC @@ -2967,11 +2512,6 @@ style lambda=0.30(s) calma CV2 61 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA and-not XP grow 30 and CM2 @@ -2980,32 +2520,6 @@ style lambda=0.30(s) shrink 15 calma CV1 50 * - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - layer m1 CM1 and-not CRM and-not CRF @@ -3052,14 +2566,6 @@ style lambda=0.30(s) labels CMSP calma CMSP 82 * - - - - - - - - layer fp 100 calma 100 100 * @@ -3082,8 +2588,6 @@ style lambda=0.30(s) calma 110 110 * layer m3c CV2 - - and-not CV1 and-not XP grow 30 and CM3 @@ -3092,7 +2596,6 @@ style lambda=0.30(s) shrink 15 calma CV2 61 * - layer m3 CM3 and-not CRM and-not CRT @@ -3162,6 +2665,20 @@ style lambda=0.30(s) and-not CRE calma CRG2 68 * + layer elc CCE + grow 30 + and CM1 + and CEL + labels CM1 + calma CCE 55 * + + layer elc CCC + grow 30 + and CM1 + and CEL + labels CM1 + calma CCC 25 * + layer comment CX labels CX calma CX 63 * @@ -3181,6 +2698,11 @@ style lambda=0.30(s) style lambda=0.30(ps) scalefactor 30 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -3388,7 +2910,6 @@ style lambda=0.30(ps) layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -3402,7 +2923,6 @@ style lambda=0.30(ps) layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -3416,7 +2936,6 @@ style lambda=0.30(ps) layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -3430,7 +2949,6 @@ style lambda=0.30(ps) layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -3444,7 +2962,6 @@ style lambda=0.30(ps) layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -3458,7 +2975,6 @@ style lambda=0.30(ps) layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA and-not CPS @@ -3472,7 +2988,6 @@ style lambda=0.30(ps) layer psc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -3486,128 +3001,6 @@ style lambda=0.30(ps) layer psc CAA and CSP and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 and-not CWNR and-not CTA @@ -3638,7 +3031,6 @@ style lambda=0.30(ps) calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -3650,7 +3042,6 @@ style lambda=0.30(ps) calma CCP 47 * layer pc CCC - and-not CV1 and CPG and-not CPC and-not CEL @@ -3661,82 +3052,6 @@ style lambda=0.30(ps) shrink 15 calma CCC 25 * - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - layer gc CCP and-not CPG and-not CPC @@ -3801,11 +3116,6 @@ style lambda=0.30(ps) calma CV2 61 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA and-not XP grow 30 and CM2 @@ -3814,32 +3124,6 @@ style lambda=0.30(ps) shrink 15 calma CV1 50 * - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - layer m1 CM1 and-not CRM and-not CRF @@ -3886,14 +3170,6 @@ style lambda=0.30(ps) labels CMSP calma CMSP 82 * - - - - - - - - layer fp 100 calma 100 100 * @@ -3916,8 +3192,6 @@ style lambda=0.30(ps) calma 110 110 * layer m3c CV2 - - and-not CV1 and-not XP grow 30 and CM3 @@ -3926,7 +3200,6 @@ style lambda=0.30(ps) shrink 15 calma CV2 61 * - layer m3 CM3 and-not CRM and-not CRT @@ -3996,6 +3269,20 @@ style lambda=0.30(ps) and-not CRE calma CRG2 68 * + layer elc CCE + grow 30 + and CM1 + and CEL + labels CM1 + calma CCE 55 * + + layer elc CCC + grow 30 + and CM1 + and CEL + labels CM1 + calma CCC 25 * + layer comment CX labels CX calma CX 63 * @@ -4015,6 +3302,11 @@ style lambda=0.30(ps) style lambda=0.30() scalefactor 30 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -4219,7 +3511,6 @@ style lambda=0.30() layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -4233,7 +3524,6 @@ style lambda=0.30() layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -4247,7 +3537,6 @@ style lambda=0.30() layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA @@ -4261,7 +3550,6 @@ style lambda=0.30() layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA @@ -4275,7 +3563,6 @@ style lambda=0.30() layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -4289,7 +3576,6 @@ style lambda=0.30() layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA and-not CPS @@ -4303,7 +3589,6 @@ style lambda=0.30() layer psc CAA and CSP and CCA - and-not CV1 and-not CTA and-not CPS @@ -4317,128 +3602,6 @@ style lambda=0.30() layer psc CAA and CSP and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 and-not CWNR and-not CTA @@ -4469,7 +3632,6 @@ style lambda=0.30() calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -4481,7 +3643,6 @@ style lambda=0.30() calma CCP 47 * layer pc CCC - and-not CV1 and CPG and-not CPC and-not CEL @@ -4492,82 +3653,6 @@ style lambda=0.30() shrink 15 calma CCC 25 * - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - layer gc CCP and-not CPG and-not CPC @@ -4632,11 +3717,6 @@ style lambda=0.30() calma CV2 61 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA and-not XP grow 30 and CM2 @@ -4645,32 +3725,6 @@ style lambda=0.30() shrink 15 calma CV1 50 * - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - layer m1 CM1 and-not CRM and-not CRF @@ -4717,14 +3771,6 @@ style lambda=0.30() labels CMSP calma CMSP 82 * - - - - - - - - layer fp 100 calma 100 100 * @@ -4747,8 +3793,6 @@ style lambda=0.30() calma 110 110 * layer m3c CV2 - - and-not CV1 and-not XP grow 30 and CM3 @@ -4757,7 +3801,6 @@ style lambda=0.30() shrink 15 calma CV2 61 * - layer m3 CM3 and-not CRM and-not CRT @@ -4827,6 +3870,20 @@ style lambda=0.30() and-not CRE calma CRG2 68 * + layer elc CCE + grow 30 + and CM1 + and CEL + labels CM1 + calma CCE 55 * + + layer elc CCC + grow 30 + and CM1 + and CEL + labels CM1 + calma CCC 25 * + layer comment CX labels CX calma CX 63 * @@ -4846,6 +3903,11 @@ style lambda=0.30() style lambda=0.30(c) scalefactor 30 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -5301,6 +4363,11 @@ style lambda=0.30(c) style lambda=0.30(cs) scalefactor 30 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -5758,6 +4825,11 @@ style lambda=0.30(cs) style lambda=0.30(cps) scalefactor 30 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -6216,6 +5288,11 @@ style lambda=0.30(cps) style lambda=0.30(cp) scalefactor 30 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -6740,27 +5817,22 @@ drc width pc/m1 4 \ "Poly contact width < 4 (Mosis #5.1)" - width gc 2 \ "GC contact width < 2 (Mosis #6.1)" width ndc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - width nsc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - width pdc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - width psc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - - width m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 \ + width m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 3 \ "Metal1 width < 3 (Mosis #7.1)" width gv1 2 \ @@ -6769,22 +5841,13 @@ drc width m2c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" - - - - - - - width p2m12c 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - - width p2m12c 4 \ - "stacked p2m12c width < 4 (Mosis #8.1)" - width m2,fm2,rm2,m2c/m2,m3c/m2 3 \ "Metal2 width < 3 (Mosis #9.1)" - width poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c 5 \ + width ecap 8 \ + "Ecap width < 8 (Mosis #11.1)" + + width poly2,ecap,phr 5 \ "Poly2 width < 5 (Mosis #11.1)" width gc2 2 \ @@ -6793,16 +5856,12 @@ drc width p2c 4 \ "Poly2 contact width < 4 (Mosis #13.1)" - width p2m12c 4 \ - "Poly2 contact width < 4 (Mosis #13.1)" - width gv2 2 \ "GV2 via width < 2 (Mosis #14.1)" width m3c/m2 4 \ "Metal3 contact width < 4 (Mosis #14.1)" - width m3,fm3,rm3,m3c/m3,pad 5 \ "Metal3 width < 5 (Mosis #15.1)" @@ -6890,7 +5949,7 @@ drc edge4way nfet,pfet,fet space/active,ndiff,rnd,ndc/a,pdiff,rpd,pdc/a 3 ndiff,rnd,ndc/a,pdiff,rpd,pdc/a,nfet,pfet,fet 0 0 \ "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active - edge4way poly,fp,rp,pc/a ~(poly,fp,rp,pc/a,nfet,pfet,fet,prp)/active 1 space space 1 \ + edge4way poly,fp,rp,pc/a ~(poly,fp,rp,pc/a,nfet,pfet,fet,prp)/active 1 space/a space/a 1 \ "Poly spacing to Diffusion < 1 (Mosis #3.5)" edge4way nfet ~(nfet)/active 3 ~(pselect)/select ~(nfet)/active 3 \ @@ -6977,12 +6036,9 @@ drc spacing gc gc 3 touching_ok \ "Generic contact spacing < 3 (Mosis #5.3)" - edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ + edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c)/metal1 0 0 \ "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 - edge4way ~(gc2)/contact gc2 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ - "Generic contact2 cannot touch Metal1 contacts (Mosis #0)" metal1 - spacing gv1 m2c/m2 2 touching_illegal \ "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" @@ -7001,12 +6057,6 @@ drc spacing psc/m1 ndc/m1 1 touching_illegal \ "psc spacing to ndc < 1 (Mosis #6.3)" - - - - - - spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 1 touching_illegal \ "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" @@ -7020,35 +6070,44 @@ drc "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" spacing pc/a ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ - "pc/a,pm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a < 2 (Mosis #6.7)" + "pc/a spacing to ndc/a,pdc/a,psc/a,nsc/a < 2 (Mosis #6.7)" - spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 touching_ok \ + spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 3 touching_ok \ "Metal1 spacing < 3 (Mosis #7.2)" - spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 fm1,fapm 3 touching_illegal \ + spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 fm1,fapm 3 touching_illegal \ "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" spacing fm1 fm1 4 touching_ok \ "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" - edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 space 1 \ "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 - edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 1 ~(gc)/contact 0 0 \ "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact spacing gv1 gv1 3 touching_ok \ "GV1 via spacing < 3 (Mosis #8.2)" - edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 ~(gv1)/via1 1 \ + edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 ~(gv1)/via1 1 \ "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 - edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 space 1 \ "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 - edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 1 ~(gv1)/via1 0 0 \ "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 + spacing gc gv1 2 touching_illegal \ + "GC contact spacing to GV1 via < 2 (Mosis #8.4)" + + spacing gc m2c/m2 2 touching_illegal \ + " spacing to Metal2 contacts < 2 (Mosis #14.2)" + + spacing gc m2c/m2 2 touching_illegal \ + "GC contact spacing to Metal2 contacts < 2 (Mosis #8.4)" + spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 3 touching_ok \ "Metal2 spacing < 3 (Mosis #9.2)" @@ -7079,7 +6138,7 @@ drc edge4way ~(ecap)/cap ecap 1 poly,fp,rp,pc/a 0 0 \ "Ecap must touch Poly (Mosis #11.3x)" active - edge4way poly2,phr,p2c,p2m12c space 5 ~(poly,fp,rp,pc/a)/active space 5 \ + edge4way poly2,phr space 5 ~(poly,fp,rp,pc/a)/active space 5 \ "Poly2 spacing to Poly < 5 (Mosis #11.3c)" active spacing ecap pc/a 2 touching_illegal \ @@ -7088,13 +6147,13 @@ drc spacing ecap gc 3 touching_illegal \ "Ecap spacing to Generic contact < 3 (Mosis #11.5)" - spacing poly2,ecap,phr,p2c,p2m12c poly2,ecap,phr,p2c,p2m12c 3 touching_ok \ + spacing poly2,ecap,phr poly2,ecap,phr 3 touching_ok \ "Poly2 spacing < 3 (Mosis #11.2)" - spacing poly2,ecap,phr,p2c,p2m12c pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ + spacing poly2,ecap,phr pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ "Poly2 spacing to Poly contact,Diffusion contact < 2 (Mosis #11.5)" - spacing poly2,ecap,phr,p2c,p2m12c gc,gc 3 touching_illegal \ + spacing poly2,ecap,phr gc,gc 3 touching_illegal \ "Poly2 spacing to GC contact < 3 (Mosis #11.5)" spacing gc2 gc2 3 touching_ok \ @@ -7103,17 +6162,17 @@ drc edge4way ~(ecap)/cap ecap 3 ~(gc2)/contact ecap 3 \ "Ecap overlap of Generic contact2 < 3 (Mosis #13.3)" contact - edge4way ~(ecap)/cap ecap 2 ~(p2c,p2m12c)/cap ecap 2 \ - "Ecap overlap of Poly2 contact < 2 (Mosis #13.3)" cap + edge4way ~(ecap)/cap ecap 2 ~(p2c)/metal1 ecap 2 \ + "Ecap overlap of Poly2 contact < 2 (Mosis #13.3)" metal1 - edge4way gc2 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + edge4way gc2 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 space 1 \ "Metal1 must overlap Generic contact2 by 1 (Mosis #13.4)" metal1 - edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc2)/contact 0 0 \ + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 1 ~(gc2)/contact 0 0 \ "Metal1(edge) cannot touch Generic contact2 (Mosis #13.4)" contact - edge4way ~(poly2,ecap,phr,p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 ~(p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 \ - "Poly2 overlap of Poly2 contact < 1 (Mosis #13.4)" cap + edge4way ~(poly2,ecap,phr)/cap poly2,ecap,phr 1 ~(p2c)/metal1 poly2,ecap,phr 1 \ + "Poly2 overlap of Poly2 contact < 1 (Mosis #13.4)" metal1 spacing gv2 gv2 3 touching_ok \ "GV2 via spacing < 3 (Mosis #14.2)" @@ -7127,6 +6186,12 @@ drc edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 + spacing gv1 gv2 2 touching_illegal \ + "GV1 via spacing to GV2 via < 2 (Mosis #14.4)" + + spacing gv1 m3c/m2 1 touching_illegal \ + "GV1 via spacing to Metal3 contact < 1 (Mosis #14.4)" + spacing m3,rm3,m3c/m3,pad m3,rm3,m3c/m3,pad 3 touching_ok \ "Metal3 spacing < 3 (Mosis #15.2)" @@ -7148,7 +6213,7 @@ drc spacing hr,phr hr,phr 4 touching_ok \ "High-Resist spacing < 4 (Mosis #27.2)" - spacing hr,phr,phr p2c,p2m12c 2 touching_illegal \ + spacing hr,phr,phr p2c 2 touching_illegal \ "High-Resist spacing to Poly2 contact < 2 (Mosis #27.3)" spacing hr,phr,phr gc 2 touching_illegal \ @@ -7157,10 +6222,10 @@ drc edge4way hr,phr space 2 ~(ndiff,rnd,ndc/a,pdiff,rpd,pdc/a)/active 0 2 \ "High-Resist space to Diffusion < 2 (Mosis #27.4)" active - spacing hr,phr,phr poly2,ecap,phr,p2c,p2m12c 2 touching_ok \ + spacing hr,phr,phr poly2,ecap,phr 2 touching_ok \ "High-Resist spacing to other Poly2 < 2 (Mosis #27.5)" - edge4way hr,phr space 2 ~(poly2,ecap,phr,p2c,p2m12c)/contact hr,phr 2 \ + edge4way hr,phr space 2 ~(poly2,ecap,phr)/contact hr,phr 2 \ "High-Resist space to Poly2 < 2 (Mosis #27.5x)" contact spacing nwell phr 4 touching_illegal \ @@ -7271,7 +6336,7 @@ drc edge4way gc2 ~(gc2)/contact 1 ~(gc2)/contact (~(gc2),gc2)/contact 1 \ "Contact not rectangular (Magic rule)" - edge4way p2c,p2m12c ~(p2c,p2m12c)/cap 1 ~(p2c,p2m12c)/cap (~(p2c,p2m12c),p2c,p2m12c)/cap 1 \ + edge4way p2c ~(p2c)/metal1 1 ~(p2c)/metal1 (~(p2c),p2c)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ @@ -7291,12 +6356,12 @@ drc exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,gc,pc/a,gc - exact_overlap gc2,p2c,p2m12c + exact_overlap gc2,p2c edge4way pad ~(pad)/m3 1 ~(pad)/m3 (~(pad),pad)/m3 1 \ "Contact not rectangular (Magic rule)" - exact_overlap ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1 + exact_overlap ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c exact_overlap m2c/m2 @@ -7356,17 +6421,17 @@ lef ignore PC ignore CA -routing m1 M1 m1 met1 -routing m2 M2 m2 met2 -routing m3 M3 m3 met3 +routing m1 metal1 M1 m1 met1 +routing m2 metal2 M2 m2 met2 +routing m3 metal3 M3 m3 met3 -contact m2c via via1 V1 v1 +contact m2c via1 via V1 v1 contact m3c via2 V2 v2 end extract - style AMI0.5um(amic5)from:T24H + style AMI0.5um(amic5)from:T11Z cscale 1 lambda 30 step 100 @@ -7387,162 +6452,164 @@ extract planeorder via2 13 planeorder fill 14 - resist (ndiff,rnd,ndc,nsd,nsc)/active 82200 - resist (pdiff,rpd,pdc,psd,psc)/active 105200 - resist (nwell)/well 808000 - resist (rnw)/active 808000 - resist (pwell)/well 1 - resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 22000 - resist (poly2,ecap,p2c,p2m12c,p2c,p2m12c)/cap 40300 - resist (phr)/cap 40300 - resist (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c,m2c)/metal1 90 - resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 90 - resist (m3,fm3,rm3,m3c,pad)/metal3 50 + substrate *psd,space/w,pwell well - contact ndc 4 62700 - contact pdc 4 160000 - contact pc 4 15600 - contact p2c 4 26100 - contact m2c 4 910 - contact m3c 4 830 + resist (ndiff,rnd,ndc,nsd,nsc)/active 82400 + resist (pdiff,rpd,pdc,psd,psc)/active 102700 + resist (nwell)/well 816000 + resist (rnw)/active 816000 0.5 + resist (pwell)/well 1 + resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 22300 + resist (poly2,ecap,p2c)/cap 41300 + resist (phr)/cap 41300 0.5 + resist (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c,m2c)/metal1 90 + resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 90 + resist (m3,fm3,rm3,m3c,pad)/metal3 60 + + contact ndc 4 58700 + contact pdc 4 141000 + contact pc 4 15800 + contact p2c 4 26800 + contact m2c 4 760 + contact m3c 4 730 #poly2 - overlap (poly,fp,rp,pc,pc)/active (poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c)/cap 84.960 + overlap (poly,fp,rp,pc,pc)/active (poly2,ecap,phr,p2c)/cap 82.260 #nwell,cwell,pwell - areacap (nwell)/well 3.600 + areacap (nwell)/well 3.510 #rnw - areacap (rnw)/active 3.600 + areacap (rnw)/active 3.510 #ndiff -# MODEL HANDLES THIS: areacap (ndiff,ndc)/active 38.430 -# MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 38.430 -# MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 94.800 -# MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 94.800 +# MODEL HANDLES THIS: areacap (ndiff,ndc)/active 38.070 +# MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 38.070 +# MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 95.700 +# MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 95.700 - areacap (rnd)/active 38.430 - overlap (rnd)/active ~space/w 38.430 - perimc (rnd)/active ~(rnd)/active 94.800 - sideoverlap (rnd)/active ~(rnd)/active ~space/w 94.800 + areacap (rnd)/active 38.070 + overlap (rnd)/active ~space/w 38.070 + perimc (rnd)/active ~(rnd)/active 95.700 + sideoverlap (rnd)/active ~(rnd)/active ~space/w 95.700 #pdiff -# MODEL HANDLES THIS: areacap (pdiff,pdc)/active 65.880 -# MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 65.880 -# MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 75.300 -# MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 75.300 +# MODEL HANDLES THIS: areacap (pdiff,pdc)/active 65.610 +# MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 65.610 +# MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 73.800 +# MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 73.800 - areacap (rpd)/active 65.880 - overlap (rpd)/active ~space/w 65.880 - perimc (rpd)/active ~(rpd)/active 75.300 - sideoverlap (rpd)/active ~(rpd)/active ~space/w 75.300 + areacap (rpd)/active 65.610 + overlap (rpd)/active ~space/w 65.610 + perimc (rpd)/active ~(rpd)/active 73.800 + sideoverlap (rpd)/active ~(rpd)/active ~space/w 73.800 #rnw #poly -# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,rnd,ndc)/active 221.670 -# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,rnd,ndc)/active 58.500 -# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,rpd,pdc)/active 213.480 -# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,rpd,pdc)/active 82.800 +# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,rnd,ndc)/active 225.450 +# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,rnd,ndc)/active 65.700 +# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,rpd,pdc)/active 219.060 +# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,rpd,pdc)/active 69 - areacap (poly,fp,rp,pc)/active 7.740 - overlap (poly,fp,rp,pc)/active ~space/w 7.740 + areacap (poly,fp,rp,pc)/active 7.920 + overlap (poly,fp,rp,pc)/active ~space/w 7.920 #poly2 #rnw #metal1 - areacap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 2.700 + areacap (m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 2.790 #metal1-sub blocked by ~space/a,~space/c - overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.700 ~space/a,~space/c - perimc (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 20.700 - sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 20.700 ~space/a,~space/c + overlap (m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 ~space/w 2.790 ~space/a,~space/c + perimc (m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 22.200 + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 ~space/w 22.200 ~space/a,~space/c #rnw - overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 2.700 ~space/c - sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 20.700 ~space/c + overlap (m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 rnw/active 2.790 ~space/c + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,p2c,m2c)/metal1 rnw/active 22.200 ~space/c #metal1-diff blocked by ~space/c - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 3.150 ~space/c - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 20.700 ~space/c - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 3.150 ~space/c - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 20.700 ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (ndiff,rnd,ndc)/active 3.150 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (ndiff,rnd,ndc)/active 22.200 ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (pdiff,rpd,pdc)/active 3.150 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (pdiff,rpd,pdc)/active 22.200 ~space/c #metal1-poly blocked by ~space/c - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 4.590 ~space/c - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 15.900 ~space/c - sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 15.900 ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 4.680 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 18 ~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 18 ~space/c #metal1-poly2 not blocked - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly2,ecap,phr,p2c,p2m12c)/cap 3.960 + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (poly2,ecap,phr)/cap 4.320 #metal2 - areacap (m2,fm2,rm2,m3c)/metal2 1.350 + areacap (m2,fm2,rm2,m3c)/metal2 1.440 #metal2-sub blocked by - overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 1.350 ~space/a,~space/m1,~space/c - perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 15.900 - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 15.900 ~space/a,~space/m1,~space/c - overlap (m2,fm2,rm2,m3c)/metal2 rnw/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw/active 15.900 ~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 1.440 ~space/a,~space/m1,~space/c + perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 17.400 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 17.400 ~space/a,~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 rnw/active 1.440 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw/active 17.400 ~space/m1,~space/c #metal2-*diff blocked by ~space/m1,~space/c - overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,rnd,ndc)/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,rnd,ndc)/active 15.900 ~space/m1,~space/c - overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 15.900 ~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,rnd,ndc)/active 1.440 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,rnd,ndc)/active 17.400 ~space/m1,~space/c + overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 1.440 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 17.400 ~space/m1,~space/c #metal2-poly blocked by ~space/m1,~space/c overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 10.800 ~space/m1,~space/c - sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 10.800 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 11.400 ~space/m1,~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 11.400 ~space/m1,~space/c #metal2-poly2 blocked by ~space/m1 #M2->M1 - overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 2.520 - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 14.700 - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 14.700 + overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 2.700 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 15 + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 15 #metal3 areacap (m3,fm3,rm3,pad)/metal3 0.900 #metal3-sub blocked by ~space/a,~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 ~space/w 0.900 ~space/a,~space/m1,~space/m2,~space/c - perimc (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 10.500 - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 ~space/w 10.500 ~space/a,~space/m1,~space/m2,~space/c + perimc (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 11.400 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 ~space/w 11.400 ~space/a,~space/m1,~space/m2,~space/c #rnw overlap (m3,fm3,rm3,pad)/metal3 rnw/active 0.900 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 rnw/active 10.500 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 rnw/active 11.400 ~space/m1,~space/m2,~space/c #metal3-*diff blocked by ~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 (ndiff,rnd,ndc)/active 0.990 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (ndiff,rnd,ndc)/active 10.500 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (ndiff,rnd,ndc)/active 11.400 ~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 (pdiff,rpd,pdc)/active 0.990 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (pdiff,rpd,pdc)/active 10.500 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (pdiff,rpd,pdc)/active 11.400 ~space/m1,~space/m2,~space/c #metal3-poly blocked by ~space/m1,~space/m2,~space/c overlap (m3,fm3,rm3,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 0.810 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 8.100 ~space/m1,~space/m2,~space/c - sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,pad)/metal3 8.100 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 8.400 ~space/m1,~space/m2,~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,pad)/metal3 8.400 ~space/m1,~space/m2,~space/c #metal3-poly2 blocked by ~space/m1,~space/m2 #M3->M1 - overlap (m3,fm3,rm3,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 1.080 ~space/m2 + overlap (m3,fm3,rm3,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 1.080 ~space/m2 #metal3-metal1 blocked by ~space/m2 - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 9.900 ~space/m2 - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m3,fm3,rm3,m3c,pad)/metal3 9.900 ~space/m2 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 9.600 ~space/m2 + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,p2c,m2c)/metal1 (m3,fm3,rm3,m3c,pad)/metal3 9.600 ~space/m2 #M3->M2 - overlap (m3,fm3,rm3,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 3.060 - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 16.800 - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,pad)/metal3 16.800 + overlap (m3,fm3,rm3,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 2.880 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 15.600 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,pad)/metal3 15.600 #metal4 @@ -7554,44 +6621,28 @@ extract #metali -#fets +#devices -# fet pfet pdiff,pdc 2 pfet Vdd! nwell 83 213 -# fet pfet pdiff,pdc 1 pfet Vdd! nwell 83 213 + device mosfet pfet pfet pdiff,pdc nwell ERROR 69 219 + device mosfet nfet nfet ndiff,ndc pwell,space/w ERROR 66 225 - device mosfet pfet pfet pdiff,pdc nwell $VDD 83 213 + fetresis pfet linear 21001 + fetresis pfet saturation 21001 + fetresis nfet linear 6020 + fetresis nfet saturation 6020 -# fet nfet ndiff,ndc 2 nfet Gnd! pwell 59 222 -# fet nfet ndiff,ndc 1 nfet Gnd! pwell 59 222 + device resistor nwellResistor rnwell *nsd + device resistor polyResistor rpoly *poly + device resistor poly2Resistor rpoly2 *poly2 + device resistor ndiffResistor rndiff *ndiff + device resistor pdiffResistor rpdiff *pdiff - device mosfet nfet nfet ndiff,ndc pwell $GND 59 222 + device resistor metal1Resistor rmetal1 *metal1 + device resistor metal2Resistor rmetal2 *metal2 + device resistor metal3Resistor rmetal3 *metal3 - fetresis pfet linear 20996 - fetresis pfet saturation 20996 - fetresis nfet linear 6144 - fetresis nfet saturation 6144 + device resistor presResistor phr *poly2 -# fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 -# fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 -# fet rpoly2 poly2,p2c 2 poly2Resistor Gnd! nwell,pwell 0 0 -# fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 -# fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 - - device resistor None rnwell nsd,nsc - device resistor None rpoly poly,pc - device resistor None rpoly2 poly2,p2c - device resistor None rndiff ndiff,ndc - device resistor None rpdiff pdiff,pdc - -# fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 -# fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 -# fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 -# fet phr poly2,p2c 2 phrResistor Gnd! nwell,pwell 0 0 - - device resistor None rmetal1 *metal1 - device resistor None rmetal2 *metal2 - device resistor None rmetal3 *metal3 - device resistor None phr poly2,p2c end @@ -7606,7 +6657,7 @@ end router layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,rp,ndiff,rnd,nsd,pdiff,rpd,psd,m1,fm1,rm1 1 - layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 + layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 3 contacts m2contact 4 gridspacing 8 @@ -7706,12 +6757,12 @@ style colorversatec 4949 A0A0 5252 2828 \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 - poly2,ecap,phr,p2c,p2m12c yellow \ + poly2,ecap,phr yellow \ FFFF FFFF FFFF FFFF \ FFFF FFFF FFFF FFFF \ FFFF FFFF FFFF FFFF \ FFFF FFFF FFFF FFFF - m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 cyan \ + m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 cyan \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ @@ -7834,7 +6885,7 @@ style versatec 8080 4000 2020 1010 \ 0808 0004 0202 0101 \ 8080 0040 2020 1010 - m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 \ + m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,p2c,m2c/m1 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 \ 8080 0000 0000 0000 \ diff --git a/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech b/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech index deaae865..7207f681 100644 --- a/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech +++ b/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech @@ -1764,6 +1764,11 @@ cifinput style lambda=0.20(p) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -2450,10 +2455,6 @@ style lambda=0.20(p) and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * @@ -2470,6 +2471,11 @@ style lambda=0.20(p) style lambda=0.20(s) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -3158,10 +3164,6 @@ style lambda=0.20(s) and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * @@ -3178,6 +3180,11 @@ style lambda=0.20(s) style lambda=0.20(ps) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -3810,10 +3817,6 @@ style lambda=0.20(ps) and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * @@ -3830,6 +3833,11 @@ style lambda=0.20(ps) style lambda=0.20() scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -4516,10 +4524,6 @@ style lambda=0.20() and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * @@ -4536,6 +4540,11 @@ style lambda=0.20() style lambda=0.20(c) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -4989,10 +4998,6 @@ style lambda=0.20(c) and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * @@ -5009,6 +5014,11 @@ style lambda=0.20(c) style lambda=0.20(cs) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -5464,10 +5474,6 @@ style lambda=0.20(cs) and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * @@ -5484,6 +5490,11 @@ style lambda=0.20(cs) style lambda=0.20(cps) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -5940,10 +5951,6 @@ style lambda=0.20(cps) and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * @@ -5960,6 +5967,11 @@ style lambda=0.20(cps) style lambda=0.20(cp) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma BB 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -6414,10 +6426,6 @@ style lambda=0.20(cp) and-not CBA calma CAA 43 * - layer comment CX - labels CX - calma CX 63 * - calma CTA 60 * calma CRW 65 * diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 882e16d5..a5756ce3 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -86,8 +86,8 @@ drc["has_nwell"] = True drc["grid"]=0.5*_lambda_ #DRC/LVS test set_up -drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" -drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" +drc["drc_rules"]=None #drclvs_home+"/calibreDRC_scn3me_subm.rul" +drc["lvs_rules"]=None #drclvs_home+"/calibreLVS_scn3me_subm.rul" drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" # minwidth_tx with contact (no dog bone transistors) From 42c16ed739f83d050902992ceb7b8d73bc013454 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 26 May 2019 22:30:54 -0700 Subject: [PATCH 08/11] Add boundary layer --- .../scn3me_subm/gds_lib/cell_1rw_1r.gds | Bin 6394 -> 6458 bytes technology/scn3me_subm/gds_lib/cell_1w_1r.gds | Bin 6390 -> 6454 bytes .../gds_lib/replica_cell_1rw_1r.gds | Bin 6346 -> 6410 bytes .../gds_lib/replica_cell_1w_1r.gds | Bin 6342 -> 6406 bytes 4 files changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/scn3me_subm/gds_lib/cell_1rw_1r.gds b/technology/scn3me_subm/gds_lib/cell_1rw_1r.gds index a4fea073f7794ef11cbd2daa04f721b08f919b4f..f9a19873f4bff1427a2f5ceea7c33f32d9b6df44 100644 GIT binary patch delta 53 zcmexmxXWmQJhL2w`a~sL5VbKWNSuR%fq{*eiNSv29tFOT1O_mG(3@9@2QUHvN4^Tr delta 26 fcmdmG^viI9JTn)A{zN5P5VbKWNPP1baW_T)YsLq# diff --git a/technology/scn3me_subm/gds_lib/cell_1w_1r.gds b/technology/scn3me_subm/gds_lib/cell_1w_1r.gds index 382018a72c5508ba11ee26a0f7b90ab724a76510..41cff8af7f7b4c2e2212a810a2b1d26337ea0000 100644 GIT binary patch delta 60 zcmexnxXoySJhL2w`a~sb5VbKOK%9evfq{*eiNSv24h6xG1O_mG(F~I>ipy_4A+E;= E0FgxuRsaA1 delta 30 jcmdmH^v!UBJTn)A{zN5f5VbKOKzy=`7TeWH>ph}xJXCC`7TeWH>xh}xJTA Date: Mon, 27 May 2019 16:19:29 -0700 Subject: [PATCH 09/11] Pbitcell updates. Fix module offset error. Add boundary for debugging. Line wrap code. --- compiler/base/design.py | 2 + compiler/bitcells/pbitcell.py | 106 ++++++++++++++++++++-------------- 2 files changed, 66 insertions(+), 42 deletions(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index 516eef80..b6651dd4 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -30,6 +30,8 @@ class design(hierarchy_design): self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space) if contact.m3m4: self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space) + else: + self.m3_pitch = self.m2_pitch def setup_drc_constants(self): """ These are some DRC constants used in many places in the compiler.""" diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index e045b763..c9eb3f58 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -79,9 +79,7 @@ class pbitcell(design.design): # in netlist_only mode, calling offset_all_coordinates or translate_all will not be possible # this function is not needed to calculate the dimensions of pbitcell in netlist_only mode though if not OPTS.netlist_only: - self.offset_all_coordinates() - gnd_overlap = vector(0, 0.5*contact.well.width) - self.translate_all(gnd_overlap) + self.translate_all(vector(self.leftmost_xpos, self.botmost_ypos)) def add_pins(self): @@ -141,7 +139,8 @@ class pbitcell(design.design): def add_modules(self): """ Determine size of transistors and add ptx modules """ - # if there are any read/write ports, then the inverter nmos is sized based the number of read/write ports + # if there are any read/write ports, + # then the inverter nmos is sized based the number of read/write ports if(self.num_rw_ports > 0): inverter_nmos_width = self.num_rw_ports*parameter["6T_inv_nmos_size"] inverter_pmos_width = parameter["6T_inv_pmos_size"] @@ -149,7 +148,8 @@ class pbitcell(design.design): write_nmos_width = parameter["6T_access_size"] read_nmos_width = 2*parameter["6T_inv_pmos_size"] - # if there are no read/write ports, then the inverter nmos is statically sized for the dual port case + # if there are no read/write ports, + # then the inverter nmos is statically sized for the dual port case else: inverter_nmos_width = 2*parameter["6T_inv_pmos_size"] inverter_pmos_width = parameter["6T_inv_pmos_size"] @@ -183,14 +183,21 @@ class pbitcell(design.design): def calculate_spacing(self): """ Calculate transistor spacings """ + # calculate metal contact extensions over transistor active - readwrite_nmos_contact_extension = 0.5*(self.readwrite_nmos.active_contact.height - self.readwrite_nmos.active_height) - write_nmos_contact_extension = 0.5*(self.write_nmos.active_contact.height - self.write_nmos.active_height) - read_nmos_contact_extension = 0.5*(self.read_nmos.active_contact.height - self.read_nmos.active_height) - max_contact_extension = max(readwrite_nmos_contact_extension, write_nmos_contact_extension, read_nmos_contact_extension) + readwrite_nmos_contact_extension = 0.5*(self.readwrite_nmos.active_contact.height \ + - self.readwrite_nmos.active_height) + write_nmos_contact_extension = 0.5*(self.write_nmos.active_contact.height \ + - self.write_nmos.active_height) + read_nmos_contact_extension = 0.5*(self.read_nmos.active_contact.height \ + - self.read_nmos.active_height) + max_contact_extension = max(readwrite_nmos_contact_extension, + write_nmos_contact_extension, + read_nmos_contact_extension) # y-offset for the access transistor's gate contact - self.gate_contact_yoffset = max_contact_extension + self.m2_space + 0.5*max(contact.poly.height, contact.m1m2.height) + self.gate_contact_yoffset = max_contact_extension + self.m2_space \ + + 0.5*max(contact.poly.height, contact.m1m2.height) # y-position of access transistors self.port_ypos = self.m1_space + 0.5*contact.m1m2.height + self.gate_contact_yoffset @@ -199,8 +206,10 @@ class pbitcell(design.design): self.inverter_nmos_ypos = self.port_ypos # spacing between ports (same for read/write and write ports) - self.bitline_offset = -0.5*self.readwrite_nmos.active_width + 0.5*contact.m1m2.height + self.m2_space + self.m2_width - m2_constraint = self.bitline_offset + self.m2_space + 0.5*contact.m1m2.height - 0.5*self.readwrite_nmos.active_width + self.bitline_offset = -0.5*self.readwrite_nmos.active_width + 0.5*contact.m1m2.height \ + + self.m2_space + self.m2_width + m2_constraint = self.bitline_offset + self.m2_space + 0.5*contact.m1m2.height \ + - 0.5*self.readwrite_nmos.active_width self.write_port_spacing = max(self.active_space, self.m1_space, m2_constraint) self.read_port_spacing = self.bitline_offset + self.m2_space @@ -211,7 +220,7 @@ class pbitcell(design.design): inverter_pmos_contact_extension = 0.5*(self.inverter_pmos.active_contact.height - self.inverter_pmos.active_height) inverter_nmos_contact_extension = 0.5*(self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height) self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_polycontact + 2*contact.poly.width \ + + self.poly_to_polycontact + 2*contact.poly.height \ + self.m1_space + inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ @@ -222,11 +231,11 @@ class pbitcell(design.design): + 1.5*contact.poly.width # spacing between wordlines (and gnd) - self.rowline_spacing = self.m1_space + contact.m1m2.width - self.rowline_offset = -0.5*self.m1_width + self.m1_offset = -0.5*self.m1_width # spacing for vdd - implant_constraint = max(inverter_pmos_contact_extension, 0) + 2*self.implant_enclose_active + 0.5*(contact.well.width - self.m1_width) + implant_constraint = max(inverter_pmos_contact_extension, 0) + 2*self.implant_enclose_active \ + + 0.5*(contact.well.width - self.m1_width) metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space self.vdd_offset = max(implant_constraint, metal1_constraint) + 0.5*self.m1_width @@ -236,8 +245,10 @@ class pbitcell(design.design): def calculate_postions(self): """ Calculate positions that describe the edges and dimensions of the cell """ - self.botmost_ypos = -0.5*self.m1_width - self.total_ports*self.rowline_spacing - self.topmost_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset + self.botmost_ypos = self.m1_offset - self.total_ports*self.m1_pitch + self.topmost_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \ + + self.inverter_gap + self.inverter_pmos.active_height \ + + self.vdd_offset self.leftmost_xpos = -0.5*self.inverter_to_inverter_spacing - self.inverter_nmos.active_width \ - self.num_rw_ports*(self.readwrite_nmos.active_width + self.write_port_spacing) \ @@ -247,9 +258,14 @@ class pbitcell(design.design): self.width = -2*self.leftmost_xpos self.height = self.topmost_ypos - self.botmost_ypos - self.center_ypos = 0.5*(self.topmost_ypos + self.botmost_ypos) - + + # Add this boundary for visual debug + self.add_rect(layer="boundary", + offset=vector(self.leftmost_xpos,self.botmost_ypos), + height=self.height, + width=self.width) + def create_storage(self): """ Creates the crossed coupled inverters that act as storage for the bitcell. @@ -307,13 +323,15 @@ class pbitcell(design.design): width=contact.active.second_layer_width) # add contacts to connect gate poly to drain/source metal1 (to connect Q to Q_bar) - contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x + 0.5*contact.poly.height, self.cross_couple_upper_ypos) + contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x + 0.5*contact.poly.height, + self.cross_couple_upper_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=contact_offset_left, directions=("H","H")) - contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x - 0.5*contact.poly.height, self.cross_couple_lower_ypos) + contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x - 0.5*contact.poly.height, + self.cross_couple_lower_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=contact_offset_right, directions=("H","H")) @@ -328,21 +346,21 @@ class pbitcell(design.design): def route_rails(self): """ Adds gnd and vdd rails and connects them to the inverters """ # Add rails for vdd and gnd - gnd_ypos = self.rowline_offset - self.total_ports*self.rowline_spacing + gnd_ypos = self.m1_offset - self.total_ports*self.m1_pitch self.gnd_position = vector(0, gnd_ypos) self.add_rect_center(layer="metal1", offset=self.gnd_position, - width=self.width, - height=self.m1_width) + width=self.width) self.add_power_pin("gnd", vector(0,gnd_ypos)) - vdd_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset + vdd_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \ + + self.inverter_gap + self.inverter_pmos.active_height \ + + self.vdd_offset self.vdd_position = vector(0, vdd_ypos) self.add_rect_center(layer="metal1", offset=self.vdd_position, - width=self.width, - height=self.m1_width) + width=self.width) self.add_power_pin("vdd", vector(0,vdd_ypos)) def create_readwrite_ports(self): @@ -393,13 +411,12 @@ class pbitcell(design.design): self.readwrite_nmos_right[k].place(offset=[right_readwrite_transistor_xpos, self.port_ypos]) # add pin for RWWL - rwwl_ypos = self.rowline_offset - k*self.rowline_spacing + rwwl_ypos = self.m1_offset - k*self.m1_pitch self.rwwl_positions[k] = vector(0, rwwl_ypos) self.add_layout_pin_rect_center(text=self.rw_wl_names[k], layer="metal1", offset=self.rwwl_positions[k], - width=self.width, - height=self.m1_width) + width=self.width) # add pins for RWBL and RWBR rwbl_xpos = left_readwrite_transistor_xpos - self.bitline_offset + 0.5*self.m2_width @@ -409,7 +426,8 @@ class pbitcell(design.design): offset=self.rwbl_positions[k], height=self.height) - rwbr_xpos = right_readwrite_transistor_xpos + self.readwrite_nmos.active_width + self.bitline_offset - 0.5*self.m2_width + rwbr_xpos = right_readwrite_transistor_xpos + self.readwrite_nmos.active_width \ + + self.bitline_offset - 0.5*self.m2_width self.rwbr_positions[k] = vector(rwbr_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.rw_br_names[k], layer="metal2", @@ -468,13 +486,13 @@ class pbitcell(design.design): self.write_nmos_right[k].place(offset=[right_write_transistor_xpos, self.port_ypos]) # add pin for WWL - wwl_ypos = rwwl_ypos = self.rowline_offset - self.num_rw_ports*self.rowline_spacing - k*self.rowline_spacing + wwl_ypos = rwwl_ypos = self.m1_offset - self.num_rw_ports*self.m1_pitch \ + - k*self.m1_pitch self.wwl_positions[k] = vector(0, wwl_ypos) self.add_layout_pin_rect_center(text=self.w_wl_names[k], layer="metal1", offset=self.wwl_positions[k], - width=self.width, - height=self.m1_width) + width=self.width) # add pins for WBL and WBR wbl_xpos = left_write_transistor_xpos - self.bitline_offset + 0.5*self.m2_width @@ -484,7 +502,8 @@ class pbitcell(design.design): offset=self.wbl_positions[k], height=self.height) - wbr_xpos = right_write_transistor_xpos + self.write_nmos.active_width + self.bitline_offset - 0.5*self.m2_width + wbr_xpos = right_write_transistor_xpos + self.write_nmos.active_width + self.bitline_offset \ + - 0.5*self.m2_width self.wbr_positions[k] = vector(wbr_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.w_br_names[k], layer="metal2", @@ -565,13 +584,13 @@ class pbitcell(design.design): self.read_nmos_right[k].place(offset=[right_read_transistor_xpos+overlap_offset, self.port_ypos]) # add pin for RWL - rwl_ypos = rwwl_ypos = self.rowline_offset - self.num_rw_ports*self.rowline_spacing - self.num_w_ports*self.rowline_spacing - k*self.rowline_spacing + rwl_ypos = rwwl_ypos = self.m1_offset - self.num_rw_ports*self.m1_pitch \ + - self.num_w_ports*self.m1_pitch - k*self.m1_pitch self.rwl_positions[k] = vector(0, rwl_ypos) self.add_layout_pin_rect_center(text=self.r_wl_names[k], layer="metal1", offset=self.rwl_positions[k], - width=self.width, - height=self.m1_width) + width=self.width) # add pins for RBL and RBR rbl_xpos = left_read_transistor_xpos - self.bitline_offset + 0.5*self.m2_width @@ -581,7 +600,8 @@ class pbitcell(design.design): offset=self.rbl_positions[k], height=self.height) - rbr_xpos = right_read_transistor_xpos + self.read_port_width + self.bitline_offset - 0.5*self.m2_width + rbr_xpos = right_read_transistor_xpos + self.read_port_width + self.bitline_offset \ + - 0.5*self.m2_width self.rbr_positions[k] = vector(rbr_xpos, self.center_ypos) self.add_layout_pin_rect_center(text=self.r_br_names[k], layer="metal2", @@ -739,12 +759,14 @@ class pbitcell(design.design): def route_read_access(self): """ Routes read access transistors to the storage component of the bitcell """ # add poly to metal1 contacts for gates of the inverters - left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - self.poly_to_polycontact - 0.5*contact.poly.width, self.cross_couple_upper_ypos) + left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - self.poly_to_polycontact - 0.5*contact.poly.width, + self.cross_couple_upper_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=left_storage_contact, directions=("H","H")) - right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + self.poly_to_polycontact + 0.5*contact.poly.width, self.cross_couple_upper_ypos) + right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + self.poly_to_polycontact + 0.5*contact.poly.width, + self.cross_couple_upper_ypos) self.add_via_center(layers=("poly", "contact", "metal1"), offset=right_storage_contact, directions=("H","H")) From c2cc9013007f60d63e3be32af796a96ce365ab18 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 27 May 2019 16:32:38 -0700 Subject: [PATCH 10/11] Add boundary to every module and pgate for visual debug. --- compiler/base/hierarchy_layout.py | 7 +++++++ compiler/bitcells/pbitcell.py | 6 +----- compiler/modules/bank.py | 1 + compiler/modules/bank_select.py | 1 + compiler/modules/bitcell_array.py | 2 ++ compiler/modules/control_logic.py | 3 ++- compiler/modules/delay_chain.py | 3 ++- compiler/modules/dff_array.py | 1 + compiler/modules/dff_buf.py | 1 + compiler/modules/dff_buf_array.py | 1 + compiler/modules/dff_inv.py | 1 + compiler/modules/dff_inv_array.py | 1 + compiler/modules/hierarchical_decoder.py | 1 + compiler/modules/hierarchical_predecode2x4.py | 1 + compiler/modules/hierarchical_predecode3x8.py | 1 + compiler/modules/precharge_array.py | 1 + compiler/modules/replica_bitline.py | 1 + compiler/modules/sense_amp_array.py | 1 + compiler/modules/single_level_column_mux_array.py | 1 + compiler/modules/tri_gate_array.py | 1 + compiler/modules/wordline_driver.py | 1 + compiler/modules/write_driver_array.py | 1 + compiler/pgates/pgate.py | 7 ++++--- 23 files changed, 35 insertions(+), 10 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e8c1b0b9..2972ecf8 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -879,6 +879,13 @@ class layout(): Wrapper to create a horizontal channel route """ self.create_channel_route(netlist, offset, layer_stack, pitch, vertical=False) + + def add_boundary(self): + """ Add boundary for debugging dimensions """ + self.add_rect(layer="boundary", + offset=vector(0,0), + height=self.height, + width=self.width) def add_enclosure(self, insts, layer="nwell"): """ Add a layer that surrounds the given instances. Useful diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index c9eb3f58..3f0a6073 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -36,6 +36,7 @@ class pbitcell(design.design): self.create_netlist() # We must always create the bitcell layout because some transistor sizes in the other netlists depend on it self.create_layout() + self.add_boundary() def create_netlist(self): self.add_pins() @@ -260,11 +261,6 @@ class pbitcell(design.design): self.height = self.topmost_ypos - self.botmost_ypos self.center_ypos = 0.5*(self.topmost_ypos + self.botmost_ypos) - # Add this boundary for visual debug - self.add_rect(layer="boundary", - offset=vector(self.leftmost_xpos,self.botmost_ypos), - height=self.height, - width=self.width) def create_storage(self): """ diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index a854c40b..e7ec2967 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -47,6 +47,7 @@ class bank(design.design): if not OPTS.netlist_only: debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.") self.create_layout() + self.add_boundary() def create_netlist(self): diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index ac866456..41588e70 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -42,6 +42,7 @@ class bank_select(design.design): self.place_instances() self.route_instances() + self.add_boundary() self.DRC_LVS() diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index f2ab77ac..0bc4011c 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -68,6 +68,8 @@ class bitcell_array(design.design): self.add_layout_pins() + self.add_boundary() + self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 0bf309a6..3c6e31b4 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -67,6 +67,7 @@ class control_logic(design.design): self.place_instances() self.route_all() #self.add_lvs_correspondence_points() + self.add_boundary() self.DRC_LVS() @@ -969,4 +970,4 @@ class control_logic(design.design): total_cin += self.wl_en_driver.get_cin() if self.port_type == 'rw': total_cin +=self.and2.get_cin() - return total_cin \ No newline at end of file + return total_cin diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index 188efffa..99b5875b 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -52,8 +52,9 @@ class delay_chain(design.design): self.place_inverters() self.route_inverters() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() - + def add_pins(self): """ Add the pins of the delay chain""" self.add_pin("in") diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 8b03fe19..53e6b0ba 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -44,6 +44,7 @@ class dff_array(design.design): self.place_dff_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 42e86bc0..d113cd14 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -55,6 +55,7 @@ class dff_buf(design.design): self.place_instances() self.route_wires() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index dfd38760..8b107f04 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -49,6 +49,7 @@ class dff_buf_array(design.design): self.height = self.rows * self.dff.height self.place_dff_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 2f831570..7eecfc68 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -53,6 +53,7 @@ class dff_inv(design.design): self.add_wires() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 3ae50a08..c8743722 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -49,6 +49,7 @@ class dff_inv_array(design.design): self.place_dff_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 1eac268d..b316e631 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -54,6 +54,7 @@ class hierarchical_decoder(design.design): self.route_predecode_rails() self.route_vdd_gnd() self.offset_all_coordinates() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index 938196d3..1efdae20 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -47,6 +47,7 @@ class hierarchical_predecode2x4(hierarchical_predecode): self.place_output_inverters() self.place_nand_array() self.route() + self.add_boundary() self.DRC_LVS() def get_nand_input_line_combination(self): diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index 77d9ce01..85069202 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -52,6 +52,7 @@ class hierarchical_predecode3x8(hierarchical_predecode): self.place_output_inverters() self.place_nand_array() self.route() + self.add_boundary() self.DRC_LVS() def get_nand_input_line_combination(self): diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index f88938c8..fa19d3d5 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -51,6 +51,7 @@ class precharge_array(design.design): self.place_insts() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index acd1f5d0..1371bb68 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -49,6 +49,7 @@ class replica_bitline(design.design): self.width = self.replica_column_inst.rx() - self.delay_chain_inst.lx() + self.m2_pitch self.height = max(self.replica_column_inst.uy(), self.delay_chain_inst.uy()) + self.m3_pitch + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 4dfa03ad..81b2218d 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -50,6 +50,7 @@ class sense_amp_array(design.design): self.place_sense_amp_array() self.add_layout_pins() self.route_rails() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 435f0cbe..e7a72856 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -52,6 +52,7 @@ class single_level_column_mux_array(design.design): self.add_layout_pins() self.add_enclosure(self.mux_inst, "pwell") + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index e3eb42cb..54760572 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -41,6 +41,7 @@ class tri_gate_array(design.design): self.place_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index dbef0417..f81cdd1a 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -44,6 +44,7 @@ class wordline_driver(design.design): self.route_layout() self.route_vdd_gnd() self.offset_all_coordinates() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 27da84b0..c2ceb386 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -50,6 +50,7 @@ class write_driver_array(design.design): self.place_write_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 57b73a21..40c04cb6 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -31,17 +31,18 @@ class pgate(design.design): self.create_netlist() if not OPTS.netlist_only: self.create_layout() + self.add_boundary() self.DRC_LVS() - def create_netlist(): + def create_netlist(self): """ Pure virtual function """ debug.error("Must over-ride create_netlist.",-1) - def create_layout(): + def create_layout(self): """ Pure virtual function """ debug.error("Must over-ride create_layout.",-1) - + def connect_pin_to_rail(self,inst,pin,supply): """ Connects a ptx pin to a supply rail. """ source_pin = inst.get_pin(pin) From 72f4a223c3c390250b8bc3f52f08fbee22765c95 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 27 May 2019 16:38:47 -0700 Subject: [PATCH 11/11] Move power pins before no route option --- compiler/sram_base.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 192bc669..be422135 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -129,14 +129,15 @@ class sram_base(design, verilog, lef): def route_supplies(self): """ Route the supply grid and connect the pins to them. """ + # Copy the pins to the top level + # This will either be used to route or left unconnected. + for inst in self.insts: + self.copy_power_pins(inst,"vdd") + self.copy_power_pins(inst,"gnd") # Do not route the power supply if not OPTS.route_supplies: return - for inst in self.insts: - self.copy_power_pins(inst,"vdd") - self.copy_power_pins(inst,"gnd") - from supply_router import supply_router as router layer_stack =("metal3","via3","metal4") rtr=router(layer_stack, self) @@ -579,4 +580,4 @@ class sram_base(design, verilog, lef): total_cin += self.data_dff.get_clk_cin() if self.col_addr_size > 0: total_cin += self.col_addr_dff.get_clk_cin() - return total_cin \ No newline at end of file + return total_cin