diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index e474be92..186e5ece 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -12,7 +12,7 @@ class precharge(pgate.pgate):
     This module implements the precharge bitline cell used in the design.
     """
 
-    def __init__(self, name, size=1):
+    def __init__(self, name, size=1, BL="bl", BR="br"):
         pgate.pgate.__init__(self, name)
         debug.info(2, "create single precharge cell: {0}".format(name))
 
@@ -24,13 +24,15 @@ class precharge(pgate.pgate):
         self.beta = parameter["beta"]
         self.ptx_width = self.beta*parameter["min_tx_size"]
         self.width = self.bitcell.width
+        self.BL = BL
+        self.BR = BR
 
         self.add_pins()
         self.create_layout()
         self.DRC_LVS()
 
     def add_pins(self):
-        self.add_pin_list(["bl", "br", "en", "vdd"])
+        self.add_pin_list([self.BL, self.BR, "en", "vdd"])
 
     def create_layout(self):
         self.create_ptx()
@@ -82,12 +84,12 @@ class precharge(pgate.pgate):
         """Adds both the upper_pmos and lower_pmos to the module"""
         # adds the lower pmos to layout
         #base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0)
-        self.lower_pmos_position = vector(self.bitcell.get_pin("bl").lx(),
+        self.lower_pmos_position = vector(self.bitcell.get_pin(self.BL).lx(),
                                           self.pmos.active_offset.y)
         self.lower_pmos_inst=self.add_inst(name="lower_pmos",
                                            mod=self.pmos,
                                            offset=self.lower_pmos_position)
-        self.connect_inst(["bl", "en", "br", "vdd"])
+        self.connect_inst([self.BL, "en", self.BR, "vdd"])
 
         # adds the upper pmos(s) to layout
         ydiff = self.pmos.height + 2*self.m1_space + contact.poly.width
@@ -95,13 +97,13 @@ class precharge(pgate.pgate):
         self.upper_pmos1_inst=self.add_inst(name="upper_pmos1",
                                             mod=self.pmos,
                                             offset=self.upper_pmos1_pos)
-        self.connect_inst(["bl", "en", "vdd", "vdd"])
+        self.connect_inst([self.BL, "en", "vdd", "vdd"])
 
         upper_pmos2_pos = self.upper_pmos1_pos + self.overlap_offset
         self.upper_pmos2_inst=self.add_inst(name="upper_pmos2",
                                             mod=self.pmos,
                                             offset=upper_pmos2_pos)
-        self.connect_inst(["br", "en", "vdd", "vdd"])
+        self.connect_inst([self.BR, "en", "vdd", "vdd"])
 
     def connect_poly(self):
         """Connects the upper and lower pmos together"""
@@ -159,16 +161,16 @@ class precharge(pgate.pgate):
     def add_bitlines(self):
         """Adds both bit-line and bit-line-bar to the module"""
         # adds the BL on metal 2
-        offset = vector(self.bitcell.get_pin("bl").cx(),0) - vector(0.5 * self.m2_width,0)
-        self.add_layout_pin(text="bl",
+        offset = vector(self.bitcell.get_pin(self.BL).cx(),0) - vector(0.5 * self.m2_width,0)
+        self.add_layout_pin(text=self.BL,
                             layer="metal2",
                             offset=offset,
                             width=drc['minwidth_metal2'],
                             height=self.height)
 
         # adds the BR on metal 2
-        offset = vector(self.bitcell.get_pin("br").cx(),0) - vector(0.5 * self.m2_width,0)
-        self.add_layout_pin(text="br",
+        offset = vector(self.bitcell.get_pin(self.BR).cx(),0) - vector(0.5 * self.m2_width,0)
+        self.add_layout_pin(text=self.BR,
                             layer="metal2",
                             offset=offset,
                             width=drc['minwidth_metal2'],
@@ -176,10 +178,10 @@ class precharge(pgate.pgate):
 
     def connect_to_bitlines(self):
         self.add_bitline_contacts()
-        self.connect_pmos(self.lower_pmos_inst.get_pin("S"),self.get_pin("bl"))
-        self.connect_pmos(self.lower_pmos_inst.get_pin("D"),self.get_pin("br"))        
-        self.connect_pmos(self.upper_pmos1_inst.get_pin("S"),self.get_pin("bl"))        
-        self.connect_pmos(self.upper_pmos2_inst.get_pin("D"),self.get_pin("br"))        
+        self.connect_pmos(self.lower_pmos_inst.get_pin("S"),self.get_pin(self.BL))
+        self.connect_pmos(self.lower_pmos_inst.get_pin("D"),self.get_pin(self.BR))        
+        self.connect_pmos(self.upper_pmos1_inst.get_pin("S"),self.get_pin(self.BL))        
+        self.connect_pmos(self.upper_pmos2_inst.get_pin("D"),self.get_pin(self.BR))
         
 
     def add_bitline_contacts(self):
diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py
old mode 100755
new mode 100644
index 55460289..4e473a25
--- a/compiler/tests/04_precharge_test.py
+++ b/compiler/tests/04_precharge_test.py
@@ -21,11 +21,25 @@ class precharge_test(openram_test):
         import precharge
         import tech
 
-        debug.info(2, "Checking precharge")
+        debug.info(2, "Checking precharge for handmade bitcell")
         tx = precharge.precharge(name="precharge_driver", size=1)
         self.local_check(tx)
+        
+        debug.info(2, "Checking precharge for pbitcell")
+        OPTS.bitcell = "pbitcell"
+        OPTS.rw_ports = 2
+        OPTS.r_ports = 2
+        OPTS.w_ports = 2
+        tx = precharge.precharge(name="precharge_driver", size=1, BL="rwbl0", BR="rwbl_bar0")
+        self.local_check(tx)
+        
+        tx = precharge.precharge(name="precharge_driver", size=1, BL="wbl0", BR="wbl_bar0")
+        self.local_check(tx)
+        
+        tx = precharge.precharge(name="precharge_driver", size=1, BL="rbl0", BR="rbl_bar0")
+        self.local_check(tx)
 
-        globals.end_openram()
+        #globals.end_openram()
         
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":