From 55dd4d0c47217c313da4efda838ed0e3e500f40c Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 14 Sep 2020 14:35:52 -0700 Subject: [PATCH] Global bitcell array working --- compiler/modules/bank.py | 14 ++-- compiler/modules/global_bitcell_array.py | 15 ++-- compiler/tests/19_single_bank_1rw_1r_test.py | 3 +- .../tests/19_single_bank_global_bitline.py | 74 +++++++++++++++++++ 4 files changed, 91 insertions(+), 15 deletions(-) create mode 100755 compiler/tests/19_single_bank_global_bitline.py diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index d091896e..57890a45 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -374,18 +374,18 @@ class bank(design.design): self.num_rbl = len(self.all_ports) try: - local_bitline_size = OPTS.local_bitline_size + local_array_size = OPTS.local_array_size except AttributeError: - local_bitline_size = 0 + local_array_size = 0 - if local_bitline_size > 0: + if local_array_size > 0: # Find the even multiple that satisfies the fanout with equal sized local arrays total_cols = self.num_cols + self.num_spare_cols - num_lb = floor(total_cols / local_bitline_size) - final_size = total_cols - num_lb * local_bitline_size - cols = [local_bitline_size] * (num_lb - 1) + num_lb = floor(total_cols / local_array_size) + final_size = total_cols - num_lb * local_array_size + cols = [local_array_size] * (num_lb - 1) # Add the odd bits to the last local array - cols.append(local_bitline_size + final_size) + cols.append(local_array_size + final_size) self.bitcell_array = factory.create(module_type="global_bitcell_array", cols=cols, rows=self.num_rows) diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index ad3421e5..c26e62f1 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -60,7 +60,7 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): cols=self.column_sizes[0], rbl=self.rbl, left_rbl=[0], - right_rbl=[1]) + right_rbl=[1] if len(self.all_ports) > 1 else []) self.add_mod(la) self.local_mods.append(la) return @@ -122,10 +122,10 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): # Make a flat list too self.all_rbl_bitline_names = [x for sl in zip(*self.rbl_bitline_names) for x in sl] - self.add_pin_list(self.rbl_bitline_names[0], "INPUT") + self.add_pin_list(self.rbl_bitline_names[0], "INOUT") self.add_pin_list(self.all_bitline_names, "INOUT") if len(self.all_ports) > 1: - self.add_pin_list(self.rbl_bitline_names[1], "INPUT") + self.add_pin_list(self.rbl_bitline_names[1], "INOUT") def add_wordline_pins(self): @@ -145,11 +145,12 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] - - self.add_pin_list(self.rbl_wordline_names[0], "INPUT") + + for port in range(self.rbl[0]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") self.add_pin_list(self.all_wordline_names, "INPUT") - if len(self.all_ports) > 1: - self.add_pin_list(self.rbl_wordline_names[1], "INPUT") + for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") def create_instances(self): """ Create the module instances used in this design """ diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index 22f83f29..b60e7c98 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class single_bank_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/19_single_bank_global_bitline.py b/compiler/tests/19_single_bank_global_bitline.py new file mode 100755 index 00000000..ffaea6e6 --- /dev/null +++ b/compiler/tests/19_single_bank_global_bitline.py @@ -0,0 +1,74 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class single_bank_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + OPTS.local_array_size = 2 + c = sram_config(word_size=4, + num_words=16) + + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner())