From e1fcd90b5916d7f01786823cf9dd660fd19b077a Mon Sep 17 00:00:00 2001 From: samuelkcrow <42583985+samuelkcrow@users.noreply.github.com> Date: Mon, 7 Mar 2022 11:44:47 -0800 Subject: [PATCH 001/102] backing up spice attempts --- 1KB/delay_sram_64_128_scn4m_subm.sp | 14096 +++++++++++++++++++++++++ 1KB/sram_64_128_scn4m_subm.html | 35 + 1KB/sram_64_128_scn4m_subm.lvs.sp | 14050 ++++++++++++++++++++++++ 1KB/sram_64_128_scn4m_subm.sp | 14050 ++++++++++++++++++++++++ 2x16/delay_sram_2_16_scn4m_subm.sp | 1162 ++ 2x16/sram_2_16_scn4m_subm.html | 35 + 2x16/sram_2_16_scn4m_subm.lvs.sp | 1171 ++ 2x16/sram_2_16_scn4m_subm.sp | 1171 ++ 32x32/delay_sram_32_32_scn4m_subm.sp | 3590 +++++++ 32x32/sram_32_32_scn4m_subm.html | 35 + 32x32/sram_32_32_scn4m_subm.lvs.sp | 3599 +++++++ 32x32/sram_32_32_scn4m_subm.sp | 3599 +++++++ 12 files changed, 56593 insertions(+) create mode 100644 1KB/delay_sram_64_128_scn4m_subm.sp create mode 100644 1KB/sram_64_128_scn4m_subm.html create mode 100644 1KB/sram_64_128_scn4m_subm.lvs.sp create mode 100644 1KB/sram_64_128_scn4m_subm.sp create mode 100644 2x16/delay_sram_2_16_scn4m_subm.sp create mode 100644 2x16/sram_2_16_scn4m_subm.html create mode 100644 2x16/sram_2_16_scn4m_subm.lvs.sp create mode 100644 2x16/sram_2_16_scn4m_subm.sp create mode 100644 32x32/delay_sram_32_32_scn4m_subm.sp create mode 100644 32x32/sram_32_32_scn4m_subm.html create mode 100644 32x32/sram_32_32_scn4m_subm.lvs.sp create mode 100644 32x32/sram_32_32_scn4m_subm.sp diff --git a/1KB/delay_sram_64_128_scn4m_subm.sp b/1KB/delay_sram_64_128_scn4m_subm.sp new file mode 100644 index 00000000..29564798 --- /dev/null +++ b/1KB/delay_sram_64_128_scn4m_subm.sp @@ -0,0 +1,14096 @@ +************************************************** +* OpenRAM generated memory. +* Words: 128 +* Data bits: 64 +* Banks: 1 +* Column mux: 2:1 +* Trimmed: False +* LVS: False +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 6 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff +Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff +.ENDS row_addr_dff + +.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd +*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B +* INPUT : din_0 +* OUTPUT: dout_0 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +.ENDS col_addr_dff + +.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 64 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff +Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff +Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff +Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff +Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff +Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff +Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff +Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff +Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff +Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff +Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff +Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff +Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff +Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff +Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff +Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff +Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff +Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff +Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff +Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff +Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff +Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff +Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff +Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff +Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff +Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff +Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff +Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff +Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff +Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff +Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff +Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff +Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff +Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff +Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff +Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff +Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff +Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff +Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff +Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff +Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff +Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff +Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff +Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff +Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff +Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff +Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff +Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff +Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff +Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff +Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff +Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff +Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff +Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff +Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff +Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff +Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff +Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff +Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff +Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff +Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff +Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff +.ENDS data_dff + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_2 + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_3 + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_1 + +.SUBCKT pinvbuf A Zb Z vdd gnd +*.PININFO A:B Zb:B Z:B vdd:B gnd:B +* INOUT : A +* INOUT : Zb +* INOUT : Z +* INOUT : vdd +* INOUT : gnd +Xbuf_inv1 A zb_int vdd gnd pinv_1 +Xbuf_inv2 zb_int z_int vdd gnd pinv_2 +Xbuf_inv3 z_int Zb vdd gnd pinv_3 +Xbuf_inv4 zb_int Z vdd gnd pinv_3 +.ENDS pinvbuf + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw +Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw +Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw +Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw +Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw +Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw +Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw +Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw +Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw +Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw +Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw +Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw +Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw +Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw +Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw +Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw +Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw +Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw +Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw +Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw +Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw +Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw +Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw +Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw +Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw +Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw +Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw +Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw +Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw +Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw +Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw +Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw +Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw +Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw +Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw +Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw +Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw +Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw +Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw +Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw +Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw +Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw +Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw +Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw +Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw +Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw +Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw +Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw +Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c15 bl_0_15 br_0_15 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c15 bl_0_15 br_0_15 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c15 bl_0_15 br_0_15 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c15 bl_0_15 br_0_15 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c15 bl_0_15 br_0_15 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c15 bl_0_15 br_0_15 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c15 bl_0_15 br_0_15 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c15 bl_0_15 br_0_15 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c15 bl_0_15 br_0_15 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c15 bl_0_15 br_0_15 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c15 bl_0_15 br_0_15 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c15 bl_0_15 br_0_15 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c15 bl_0_15 br_0_15 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c44 bl_0_44 br_0_44 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c44 bl_0_44 br_0_44 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c44 bl_0_44 br_0_44 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c44 bl_0_44 br_0_44 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c44 bl_0_44 br_0_44 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c44 bl_0_44 br_0_44 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c44 bl_0_44 br_0_44 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c44 bl_0_44 br_0_44 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c44 bl_0_44 br_0_44 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c44 bl_0_44 br_0_44 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c44 bl_0_44 br_0_44 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c44 bl_0_44 br_0_44 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c44 bl_0_44 br_0_44 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c44 bl_0_44 br_0_44 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c44 bl_0_44 br_0_44 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c44 bl_0_44 br_0_44 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c44 bl_0_44 br_0_44 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c44 bl_0_44 br_0_44 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw 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+Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c52 bl_0_52 br_0_52 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c52 bl_0_52 br_0_52 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c52 bl_0_52 br_0_52 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c52 bl_0_52 br_0_52 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c52 bl_0_52 br_0_52 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c52 bl_0_52 br_0_52 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c52 bl_0_52 br_0_52 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c52 bl_0_52 br_0_52 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c52 bl_0_52 br_0_52 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c52 bl_0_52 br_0_52 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c52 bl_0_52 br_0_52 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c53 bl_0_53 br_0_53 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c53 bl_0_53 br_0_53 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c53 bl_0_53 br_0_53 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c53 bl_0_53 br_0_53 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c53 bl_0_53 br_0_53 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c53 bl_0_53 br_0_53 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c53 bl_0_53 br_0_53 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c53 bl_0_53 br_0_53 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c53 bl_0_53 br_0_53 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c53 bl_0_53 br_0_53 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c53 bl_0_53 br_0_53 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c53 bl_0_53 br_0_53 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c53 bl_0_53 br_0_53 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c53 bl_0_53 br_0_53 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c53 bl_0_53 br_0_53 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c53 bl_0_53 br_0_53 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c53 bl_0_53 br_0_53 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c53 bl_0_53 br_0_53 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c53 bl_0_53 br_0_53 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c53 bl_0_53 br_0_53 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c53 bl_0_53 br_0_53 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c53 bl_0_53 br_0_53 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c53 bl_0_53 br_0_53 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c53 bl_0_53 br_0_53 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c53 bl_0_53 br_0_53 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c53 bl_0_53 br_0_53 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c53 bl_0_53 br_0_53 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c53 bl_0_53 br_0_53 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c53 bl_0_53 br_0_53 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c53 bl_0_53 br_0_53 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c53 bl_0_53 br_0_53 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c53 bl_0_53 br_0_53 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c53 bl_0_53 br_0_53 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c53 bl_0_53 br_0_53 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c53 bl_0_53 br_0_53 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c53 bl_0_53 br_0_53 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c53 bl_0_53 br_0_53 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c53 bl_0_53 br_0_53 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c53 bl_0_53 br_0_53 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c53 bl_0_53 br_0_53 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c53 bl_0_53 br_0_53 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c53 bl_0_53 br_0_53 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c53 bl_0_53 br_0_53 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c59 bl_0_59 br_0_59 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c59 bl_0_59 br_0_59 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c59 bl_0_59 br_0_59 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c60 bl_0_60 br_0_60 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c60 bl_0_60 br_0_60 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c60 bl_0_60 br_0_60 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c60 bl_0_60 br_0_60 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c60 bl_0_60 br_0_60 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c60 bl_0_60 br_0_60 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c60 bl_0_60 br_0_60 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c60 bl_0_60 br_0_60 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c60 bl_0_60 br_0_60 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c60 bl_0_60 br_0_60 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c60 bl_0_60 br_0_60 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c60 bl_0_60 br_0_60 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c60 bl_0_60 br_0_60 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c60 bl_0_60 br_0_60 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c60 bl_0_60 br_0_60 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw 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wl_0_18 vdd gnd cell_1rw +Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c74 bl_0_74 br_0_74 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c74 bl_0_74 br_0_74 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c74 bl_0_74 br_0_74 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c74 bl_0_74 br_0_74 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c74 bl_0_74 br_0_74 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c74 bl_0_74 br_0_74 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c74 bl_0_74 br_0_74 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c74 bl_0_74 br_0_74 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c74 bl_0_74 br_0_74 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c74 bl_0_74 br_0_74 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c74 bl_0_74 br_0_74 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c74 bl_0_74 br_0_74 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c74 bl_0_74 br_0_74 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c74 bl_0_74 br_0_74 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c74 bl_0_74 br_0_74 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c75 bl_0_75 br_0_75 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c75 bl_0_75 br_0_75 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c75 bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c75 bl_0_75 br_0_75 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c75 bl_0_75 br_0_75 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c75 bl_0_75 br_0_75 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c75 bl_0_75 br_0_75 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c75 bl_0_75 br_0_75 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c75 bl_0_75 br_0_75 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c76 bl_0_76 br_0_76 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c76 bl_0_76 br_0_76 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c76 bl_0_76 br_0_76 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c76 bl_0_76 br_0_76 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c76 bl_0_76 br_0_76 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c76 bl_0_76 br_0_76 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c76 bl_0_76 br_0_76 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c76 bl_0_76 br_0_76 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c76 bl_0_76 br_0_76 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c76 bl_0_76 br_0_76 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c76 bl_0_76 br_0_76 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c76 bl_0_76 br_0_76 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c81 bl_0_81 br_0_81 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c81 bl_0_81 br_0_81 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c81 bl_0_81 br_0_81 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c81 bl_0_81 br_0_81 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c81 bl_0_81 br_0_81 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c81 bl_0_81 br_0_81 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c81 bl_0_81 br_0_81 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c82 bl_0_82 br_0_82 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c82 bl_0_82 br_0_82 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c82 bl_0_82 br_0_82 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c82 bl_0_82 br_0_82 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c82 bl_0_82 br_0_82 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c82 bl_0_82 br_0_82 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c82 bl_0_82 br_0_82 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c82 bl_0_82 br_0_82 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c82 bl_0_82 br_0_82 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c82 bl_0_82 br_0_82 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c82 bl_0_82 br_0_82 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw 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wl_0_16 vdd gnd cell_1rw +Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c87 bl_0_87 br_0_87 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c87 bl_0_87 br_0_87 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c87 bl_0_87 br_0_87 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c87 bl_0_87 br_0_87 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c87 bl_0_87 br_0_87 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c87 bl_0_87 br_0_87 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c87 bl_0_87 br_0_87 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c87 bl_0_87 br_0_87 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c88 bl_0_88 br_0_88 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c88 bl_0_88 br_0_88 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c88 bl_0_88 br_0_88 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c88 bl_0_88 br_0_88 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c88 bl_0_88 br_0_88 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c88 bl_0_88 br_0_88 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c88 bl_0_88 br_0_88 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c88 bl_0_88 br_0_88 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c88 bl_0_88 br_0_88 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c88 bl_0_88 br_0_88 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw 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wl_0_15 vdd gnd cell_1rw +Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c96 bl_0_96 br_0_96 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c96 bl_0_96 br_0_96 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c96 bl_0_96 br_0_96 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c96 bl_0_96 br_0_96 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c96 bl_0_96 br_0_96 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c96 bl_0_96 br_0_96 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c96 bl_0_96 br_0_96 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c96 bl_0_96 br_0_96 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c96 bl_0_96 br_0_96 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c96 bl_0_96 br_0_96 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c96 bl_0_96 br_0_96 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c96 bl_0_96 br_0_96 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c96 bl_0_96 br_0_96 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c96 bl_0_96 br_0_96 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c96 bl_0_96 br_0_96 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c96 bl_0_96 br_0_96 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c96 bl_0_96 br_0_96 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c96 bl_0_96 br_0_96 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c96 bl_0_96 br_0_96 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c97 bl_0_97 br_0_97 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c97 bl_0_97 br_0_97 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c97 bl_0_97 br_0_97 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c97 bl_0_97 br_0_97 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c97 bl_0_97 br_0_97 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c97 bl_0_97 br_0_97 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c97 bl_0_97 br_0_97 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c97 bl_0_97 br_0_97 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c97 bl_0_97 br_0_97 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c97 bl_0_97 br_0_97 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c97 bl_0_97 br_0_97 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c97 bl_0_97 br_0_97 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c97 bl_0_97 br_0_97 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c97 bl_0_97 br_0_97 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c97 bl_0_97 br_0_97 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c97 bl_0_97 br_0_97 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c97 bl_0_97 br_0_97 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw 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bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw 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bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw 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bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c110 bl_0_110 br_0_110 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c110 bl_0_110 br_0_110 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c110 bl_0_110 br_0_110 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c110 bl_0_110 br_0_110 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c110 bl_0_110 br_0_110 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c110 bl_0_110 br_0_110 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c110 bl_0_110 br_0_110 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c110 bl_0_110 br_0_110 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c110 bl_0_110 br_0_110 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c110 bl_0_110 br_0_110 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c110 bl_0_110 br_0_110 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c110 bl_0_110 br_0_110 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c110 bl_0_110 br_0_110 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c110 bl_0_110 br_0_110 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c110 bl_0_110 br_0_110 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c110 bl_0_110 br_0_110 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c110 bl_0_110 br_0_110 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c110 bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c111 bl_0_111 br_0_111 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c111 bl_0_111 br_0_111 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c111 bl_0_111 br_0_111 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c111 bl_0_111 br_0_111 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c111 bl_0_111 br_0_111 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c111 bl_0_111 br_0_111 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c111 bl_0_111 br_0_111 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c111 bl_0_111 br_0_111 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c111 bl_0_111 br_0_111 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c111 bl_0_111 br_0_111 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c111 bl_0_111 br_0_111 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c111 bl_0_111 br_0_111 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c111 bl_0_111 br_0_111 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c111 bl_0_111 br_0_111 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c111 bl_0_111 br_0_111 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c111 bl_0_111 br_0_111 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c111 bl_0_111 br_0_111 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c111 bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c112 bl_0_112 br_0_112 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c112 bl_0_112 br_0_112 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c112 bl_0_112 br_0_112 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c112 bl_0_112 br_0_112 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c112 bl_0_112 br_0_112 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c112 bl_0_112 br_0_112 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c112 bl_0_112 br_0_112 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c112 bl_0_112 br_0_112 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c112 bl_0_112 br_0_112 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c112 bl_0_112 br_0_112 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c112 bl_0_112 br_0_112 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c112 bl_0_112 br_0_112 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c112 bl_0_112 br_0_112 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c112 bl_0_112 br_0_112 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c112 bl_0_112 br_0_112 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c112 bl_0_112 br_0_112 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c112 bl_0_112 br_0_112 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c112 bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c114 bl_0_114 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gnd cell_1rw +Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw 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bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c119 bl_0_119 br_0_119 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c119 bl_0_119 br_0_119 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c119 bl_0_119 br_0_119 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c119 bl_0_119 br_0_119 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c119 bl_0_119 br_0_119 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c119 bl_0_119 br_0_119 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c119 bl_0_119 br_0_119 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c119 bl_0_119 br_0_119 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c119 bl_0_119 br_0_119 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c119 bl_0_119 br_0_119 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c119 bl_0_119 br_0_119 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c119 bl_0_119 br_0_119 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c119 bl_0_119 br_0_119 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c119 bl_0_119 br_0_119 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c119 bl_0_119 br_0_119 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c119 bl_0_119 br_0_119 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c119 bl_0_119 br_0_119 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c119 bl_0_119 br_0_119 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c119 bl_0_119 br_0_119 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c119 bl_0_119 br_0_119 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c119 bl_0_119 br_0_119 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c119 bl_0_119 br_0_119 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c119 bl_0_119 br_0_119 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c119 bl_0_119 br_0_119 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c119 bl_0_119 br_0_119 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c119 bl_0_119 br_0_119 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c119 bl_0_119 br_0_119 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c119 bl_0_119 br_0_119 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c119 bl_0_119 br_0_119 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c119 bl_0_119 br_0_119 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c119 bl_0_119 br_0_119 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c119 bl_0_119 br_0_119 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c119 bl_0_119 br_0_119 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c119 bl_0_119 br_0_119 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c119 bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c120 bl_0_120 br_0_120 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c120 bl_0_120 br_0_120 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c120 bl_0_120 br_0_120 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c120 bl_0_120 br_0_120 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c120 bl_0_120 br_0_120 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c120 bl_0_120 br_0_120 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c120 bl_0_120 br_0_120 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c120 bl_0_120 br_0_120 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c120 bl_0_120 br_0_120 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c120 bl_0_120 br_0_120 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c120 bl_0_120 br_0_120 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c120 bl_0_120 br_0_120 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c120 bl_0_120 br_0_120 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c120 bl_0_120 br_0_120 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c120 bl_0_120 br_0_120 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c120 bl_0_120 br_0_120 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c120 bl_0_120 br_0_120 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c120 bl_0_120 br_0_120 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c120 bl_0_120 br_0_120 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c120 bl_0_120 br_0_120 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c120 bl_0_120 br_0_120 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c120 bl_0_120 br_0_120 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c120 bl_0_120 br_0_120 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c120 bl_0_120 br_0_120 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c120 bl_0_120 br_0_120 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c120 bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c121 bl_0_121 br_0_121 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c121 bl_0_121 br_0_121 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c121 bl_0_121 br_0_121 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c121 bl_0_121 br_0_121 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c121 bl_0_121 br_0_121 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c121 bl_0_121 br_0_121 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c121 bl_0_121 br_0_121 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c121 bl_0_121 br_0_121 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c121 bl_0_121 br_0_121 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c121 bl_0_121 br_0_121 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c121 bl_0_121 br_0_121 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c121 bl_0_121 br_0_121 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c121 bl_0_121 br_0_121 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c121 bl_0_121 br_0_121 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c121 bl_0_121 br_0_121 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c121 bl_0_121 br_0_121 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c121 bl_0_121 br_0_121 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c121 bl_0_121 br_0_121 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c121 bl_0_121 br_0_121 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c121 bl_0_121 br_0_121 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c121 bl_0_121 br_0_121 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c121 bl_0_121 br_0_121 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c121 bl_0_121 br_0_121 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c121 bl_0_121 br_0_121 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c121 bl_0_121 br_0_121 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c121 bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c122 bl_0_122 br_0_122 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c122 bl_0_122 br_0_122 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c122 bl_0_122 br_0_122 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c122 bl_0_122 br_0_122 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c122 bl_0_122 br_0_122 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c122 bl_0_122 br_0_122 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c122 bl_0_122 br_0_122 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c122 bl_0_122 br_0_122 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c122 bl_0_122 br_0_122 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c122 bl_0_122 br_0_122 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c122 bl_0_122 br_0_122 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c122 bl_0_122 br_0_122 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c122 bl_0_122 br_0_122 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c122 bl_0_122 br_0_122 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c122 bl_0_122 br_0_122 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c122 bl_0_122 br_0_122 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c122 bl_0_122 br_0_122 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c122 bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c123 bl_0_123 br_0_123 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c123 bl_0_123 br_0_123 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c123 bl_0_123 br_0_123 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c123 bl_0_123 br_0_123 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c123 bl_0_123 br_0_123 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c123 bl_0_123 br_0_123 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c123 bl_0_123 br_0_123 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c123 bl_0_123 br_0_123 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c123 bl_0_123 br_0_123 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c123 bl_0_123 br_0_123 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c123 bl_0_123 br_0_123 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c123 bl_0_123 br_0_123 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c123 bl_0_123 br_0_123 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c123 bl_0_123 br_0_123 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c123 bl_0_123 br_0_123 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c123 bl_0_123 br_0_123 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c123 bl_0_123 br_0_123 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c123 bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c126 bl_0_126 br_0_126 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c126 bl_0_126 br_0_126 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c126 bl_0_126 br_0_126 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c126 bl_0_126 br_0_126 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c126 bl_0_126 br_0_126 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c126 bl_0_126 br_0_126 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c126 bl_0_126 br_0_126 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c126 bl_0_126 br_0_126 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c126 bl_0_126 br_0_126 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c126 bl_0_126 br_0_126 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c126 bl_0_126 br_0_126 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c126 bl_0_126 br_0_126 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c126 bl_0_126 br_0_126 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c126 bl_0_126 br_0_126 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c126 bl_0_126 br_0_126 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c126 bl_0_126 br_0_126 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c126 bl_0_126 br_0_126 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c126 bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c127 bl_0_127 br_0_127 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c127 bl_0_127 br_0_127 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c127 bl_0_127 br_0_127 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c127 bl_0_127 br_0_127 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c127 bl_0_127 br_0_127 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c127 bl_0_127 br_0_127 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c127 bl_0_127 br_0_127 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c127 bl_0_127 br_0_127 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c127 bl_0_127 br_0_127 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c127 bl_0_127 br_0_127 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c127 bl_0_127 br_0_127 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c127 bl_0_127 br_0_127 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c127 bl_0_127 br_0_127 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c127 bl_0_127 br_0_127 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c127 bl_0_127 br_0_127 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c127 bl_0_127 br_0_127 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c127 bl_0_127 br_0_127 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c127 bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw +.ENDS bitcell_array + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* OUTPUT: data_2 +* INPUT : bl_2 +* INPUT : br_2 +* OUTPUT: data_3 +* INPUT : bl_3 +* INPUT : br_3 +* OUTPUT: data_4 +* INPUT : bl_4 +* INPUT : br_4 +* OUTPUT: data_5 +* INPUT : bl_5 +* INPUT : br_5 +* OUTPUT: data_6 +* INPUT : bl_6 +* INPUT : br_6 +* OUTPUT: data_7 +* INPUT : bl_7 +* INPUT : br_7 +* OUTPUT: data_8 +* INPUT : bl_8 +* INPUT : br_8 +* OUTPUT: data_9 +* INPUT : bl_9 +* INPUT : br_9 +* OUTPUT: data_10 +* INPUT : bl_10 +* INPUT : br_10 +* OUTPUT: data_11 +* INPUT : bl_11 +* INPUT : br_11 +* OUTPUT: data_12 +* INPUT : bl_12 +* INPUT : br_12 +* OUTPUT: data_13 +* INPUT : bl_13 +* INPUT : br_13 +* OUTPUT: data_14 +* INPUT : bl_14 +* INPUT : br_14 +* OUTPUT: data_15 +* INPUT : bl_15 +* INPUT : br_15 +* OUTPUT: data_16 +* INPUT : bl_16 +* INPUT : br_16 +* OUTPUT: data_17 +* INPUT : bl_17 +* INPUT : br_17 +* OUTPUT: data_18 +* INPUT : bl_18 +* INPUT : br_18 +* OUTPUT: data_19 +* INPUT : bl_19 +* INPUT : br_19 +* OUTPUT: data_20 +* INPUT : bl_20 +* INPUT : br_20 +* OUTPUT: data_21 +* INPUT : bl_21 +* INPUT : br_21 +* OUTPUT: data_22 +* INPUT : bl_22 +* INPUT : br_22 +* OUTPUT: data_23 +* INPUT : bl_23 +* INPUT : br_23 +* OUTPUT: data_24 +* INPUT : bl_24 +* INPUT : br_24 +* OUTPUT: data_25 +* INPUT : bl_25 +* INPUT : br_25 +* OUTPUT: data_26 +* INPUT : bl_26 +* INPUT : br_26 +* OUTPUT: data_27 +* INPUT : bl_27 +* INPUT : br_27 +* OUTPUT: data_28 +* INPUT : bl_28 +* INPUT : br_28 +* OUTPUT: data_29 +* INPUT : bl_29 +* INPUT : br_29 +* OUTPUT: data_30 +* INPUT : bl_30 +* INPUT : br_30 +* OUTPUT: data_31 +* INPUT : bl_31 +* INPUT : br_31 +* OUTPUT: data_32 +* INPUT : bl_32 +* INPUT : br_32 +* OUTPUT: data_33 +* INPUT : bl_33 +* INPUT : br_33 +* OUTPUT: data_34 +* INPUT : bl_34 +* INPUT : br_34 +* OUTPUT: data_35 +* INPUT : bl_35 +* INPUT : br_35 +* OUTPUT: data_36 +* INPUT : bl_36 +* INPUT : br_36 +* OUTPUT: data_37 +* INPUT : bl_37 +* INPUT : br_37 +* OUTPUT: data_38 +* INPUT : bl_38 +* INPUT : br_38 +* OUTPUT: data_39 +* INPUT : bl_39 +* INPUT : br_39 +* OUTPUT: data_40 +* INPUT : bl_40 +* INPUT : br_40 +* OUTPUT: data_41 +* INPUT : bl_41 +* INPUT : br_41 +* OUTPUT: data_42 +* INPUT : bl_42 +* INPUT : br_42 +* OUTPUT: data_43 +* INPUT : bl_43 +* INPUT : br_43 +* OUTPUT: data_44 +* INPUT : bl_44 +* INPUT : br_44 +* OUTPUT: data_45 +* INPUT : bl_45 +* INPUT : br_45 +* OUTPUT: data_46 +* INPUT : bl_46 +* INPUT : br_46 +* OUTPUT: data_47 +* INPUT : bl_47 +* INPUT : br_47 +* OUTPUT: data_48 +* INPUT : bl_48 +* INPUT : br_48 +* OUTPUT: data_49 +* INPUT : bl_49 +* INPUT : br_49 +* OUTPUT: data_50 +* INPUT : bl_50 +* INPUT : br_50 +* OUTPUT: data_51 +* INPUT : bl_51 +* INPUT : br_51 +* OUTPUT: data_52 +* INPUT : bl_52 +* INPUT : br_52 +* OUTPUT: data_53 +* INPUT : bl_53 +* INPUT : br_53 +* OUTPUT: data_54 +* INPUT : bl_54 +* INPUT : br_54 +* OUTPUT: data_55 +* INPUT : bl_55 +* INPUT : br_55 +* OUTPUT: data_56 +* INPUT : bl_56 +* INPUT : br_56 +* OUTPUT: data_57 +* INPUT : bl_57 +* INPUT : br_57 +* OUTPUT: data_58 +* INPUT : bl_58 +* INPUT : br_58 +* OUTPUT: data_59 +* INPUT : bl_59 +* INPUT : br_59 +* OUTPUT: data_60 +* INPUT : bl_60 +* INPUT : br_60 +* OUTPUT: data_61 +* INPUT : bl_61 +* INPUT : br_61 +* OUTPUT: data_62 +* INPUT : bl_62 +* INPUT : br_62 +* OUTPUT: data_63 +* INPUT : bl_63 +* INPUT : br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 2 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp +Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp +Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp +Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp +Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp +Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp +Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp +Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp +Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp +Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp +Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp +Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp +Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp +Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp +Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp +Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp +Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp +Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp +Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp +Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp +Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp +Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp +Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp +Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp +Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp +Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp +Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp +Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp +Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp +Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp +Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp +Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp +Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp +Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp +Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp +Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp +Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp +Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp +Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp +Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp +Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp +Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp +Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp +Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp +Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp +Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp +Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp +Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp +Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp +Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp +Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp +Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp +Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp +Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp +Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp +Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp +Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp +Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp +Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp +Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp +Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp +Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp +.ENDS sense_amp_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* OUTPUT: bl_64 +* OUTPUT: br_64 +* OUTPUT: bl_65 +* OUTPUT: br_65 +* OUTPUT: bl_66 +* OUTPUT: br_66 +* OUTPUT: bl_67 +* OUTPUT: br_67 +* OUTPUT: bl_68 +* OUTPUT: br_68 +* OUTPUT: bl_69 +* OUTPUT: br_69 +* OUTPUT: bl_70 +* OUTPUT: br_70 +* OUTPUT: bl_71 +* OUTPUT: br_71 +* OUTPUT: bl_72 +* OUTPUT: br_72 +* OUTPUT: bl_73 +* OUTPUT: br_73 +* OUTPUT: bl_74 +* OUTPUT: br_74 +* OUTPUT: bl_75 +* OUTPUT: br_75 +* OUTPUT: bl_76 +* OUTPUT: br_76 +* OUTPUT: bl_77 +* OUTPUT: br_77 +* OUTPUT: bl_78 +* OUTPUT: br_78 +* OUTPUT: bl_79 +* OUTPUT: br_79 +* OUTPUT: bl_80 +* OUTPUT: br_80 +* OUTPUT: bl_81 +* OUTPUT: br_81 +* OUTPUT: bl_82 +* OUTPUT: br_82 +* OUTPUT: bl_83 +* OUTPUT: br_83 +* OUTPUT: bl_84 +* OUTPUT: br_84 +* OUTPUT: bl_85 +* OUTPUT: br_85 +* OUTPUT: bl_86 +* OUTPUT: br_86 +* OUTPUT: bl_87 +* OUTPUT: br_87 +* OUTPUT: bl_88 +* OUTPUT: br_88 +* OUTPUT: bl_89 +* OUTPUT: br_89 +* OUTPUT: bl_90 +* OUTPUT: br_90 +* OUTPUT: bl_91 +* OUTPUT: br_91 +* OUTPUT: bl_92 +* OUTPUT: br_92 +* OUTPUT: bl_93 +* OUTPUT: br_93 +* OUTPUT: bl_94 +* OUTPUT: br_94 +* OUTPUT: bl_95 +* OUTPUT: br_95 +* OUTPUT: bl_96 +* OUTPUT: br_96 +* OUTPUT: bl_97 +* OUTPUT: br_97 +* OUTPUT: bl_98 +* OUTPUT: br_98 +* OUTPUT: bl_99 +* OUTPUT: br_99 +* OUTPUT: bl_100 +* OUTPUT: br_100 +* OUTPUT: bl_101 +* OUTPUT: br_101 +* OUTPUT: bl_102 +* OUTPUT: br_102 +* OUTPUT: bl_103 +* OUTPUT: br_103 +* OUTPUT: bl_104 +* OUTPUT: br_104 +* OUTPUT: bl_105 +* OUTPUT: br_105 +* OUTPUT: bl_106 +* OUTPUT: br_106 +* OUTPUT: bl_107 +* OUTPUT: br_107 +* OUTPUT: bl_108 +* OUTPUT: br_108 +* OUTPUT: bl_109 +* OUTPUT: br_109 +* OUTPUT: bl_110 +* OUTPUT: br_110 +* OUTPUT: bl_111 +* OUTPUT: br_111 +* OUTPUT: bl_112 +* OUTPUT: br_112 +* OUTPUT: bl_113 +* OUTPUT: br_113 +* OUTPUT: bl_114 +* OUTPUT: br_114 +* OUTPUT: bl_115 +* OUTPUT: br_115 +* OUTPUT: bl_116 +* OUTPUT: br_116 +* OUTPUT: bl_117 +* OUTPUT: br_117 +* OUTPUT: bl_118 +* OUTPUT: br_118 +* OUTPUT: bl_119 +* OUTPUT: br_119 +* OUTPUT: bl_120 +* OUTPUT: br_120 +* OUTPUT: bl_121 +* OUTPUT: br_121 +* OUTPUT: bl_122 +* OUTPUT: br_122 +* OUTPUT: bl_123 +* OUTPUT: br_123 +* OUTPUT: bl_124 +* OUTPUT: br_124 +* OUTPUT: bl_125 +* OUTPUT: br_125 +* OUTPUT: bl_126 +* OUTPUT: br_126 +* OUTPUT: bl_127 +* OUTPUT: br_127 +* OUTPUT: bl_128 +* OUTPUT: br_128 +* INPUT : en_bar +* POWER : vdd +* cols: 129 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 +Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 +Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 +Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 +Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 +Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 +Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 +Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 +Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 +Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 +Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 +Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 +Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 +Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 +Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 +Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 +Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 +Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 +Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 +Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 +Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 +Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 +Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 +Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 +Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 +Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 +Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 +Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 +Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 +Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 +Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 +Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 +Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 +Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 +Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 +Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 +Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 +Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 +Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 +Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 +Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 +Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 +Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 +Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 +Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 +Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 +Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 +Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 +Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 +Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 +Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 +Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 +Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 +Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 +Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 +Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 +Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 +Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 +Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 +Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 +Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 +Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 +Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 +Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 +Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 +Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 +Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 +Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 +Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 +Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 +Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 +Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 +Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 +Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 +Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 +Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 +Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 +Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 +Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 +Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 +Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 +Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 +Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 +Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 +Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 +Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 +Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 +Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 +Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 +Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 +Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 +Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 +Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 +Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 +Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 +Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 +Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 +Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 +Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 +Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 +Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 +Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 +Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 +Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 +Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 +Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 +Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 +Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 +Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 +Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 +Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 +Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 +Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 +Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 +Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 +Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 +Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 +Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 +Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 +Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 +Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 +Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 +Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 +Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 +Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 +Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd +*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* INPUT : data_2 +* INPUT : data_3 +* INPUT : data_4 +* INPUT : data_5 +* INPUT : data_6 +* INPUT : data_7 +* INPUT : data_8 +* INPUT : data_9 +* INPUT : data_10 +* INPUT : data_11 +* INPUT : data_12 +* INPUT : data_13 +* INPUT : data_14 +* INPUT : data_15 +* INPUT : data_16 +* INPUT : data_17 +* INPUT : data_18 +* INPUT : data_19 +* INPUT : data_20 +* INPUT : data_21 +* INPUT : data_22 +* INPUT : data_23 +* INPUT : data_24 +* INPUT : data_25 +* INPUT : data_26 +* INPUT : data_27 +* INPUT : data_28 +* INPUT : data_29 +* INPUT : data_30 +* INPUT : data_31 +* INPUT : data_32 +* INPUT : data_33 +* INPUT : data_34 +* INPUT : data_35 +* INPUT : data_36 +* INPUT : data_37 +* INPUT : data_38 +* INPUT : data_39 +* INPUT : data_40 +* INPUT : data_41 +* INPUT : data_42 +* INPUT : data_43 +* INPUT : data_44 +* INPUT : data_45 +* INPUT : data_46 +* INPUT : data_47 +* INPUT : data_48 +* INPUT : data_49 +* INPUT : data_50 +* INPUT : data_51 +* INPUT : data_52 +* INPUT : data_53 +* INPUT : data_54 +* INPUT : data_55 +* INPUT : data_56 +* INPUT : data_57 +* INPUT : data_58 +* INPUT : data_59 +* INPUT : data_60 +* INPUT : data_61 +* INPUT : data_62 +* INPUT : data_63 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 64 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver +Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver +Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver +Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver +Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver +Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver +Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver +Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver +Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver +Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver +Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver +Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver +Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver +Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver +Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver +Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver +Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver +Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver +Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver +Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver +Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver +Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver +Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver +Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver +Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver +Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver +Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver +Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver +Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver +Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver +Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver +Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver +Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver +Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver +Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver +Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver +Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver +Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver +Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver +Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver +Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver +Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver +Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver +Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver +Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver +Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver +Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver +Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver +Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver +Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver +Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver +Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver +Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver +Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver +Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver +Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver +Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver +Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver +Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver +Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver +Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver +Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver +Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver +.ENDS write_driver_array + +* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +.SUBCKT column_mux bl br bl_out br_out sel gnd +*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B +* INOUT : bl +* INOUT : br +* INOUT : bl_out +* INOUT : br_out +* INOUT : sel +* INOUT : gnd +Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +.ENDS column_mux + +.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd +*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* INOUT : sel_0 +* INOUT : sel_1 +* INOUT : bl_out_0 +* INOUT : br_out_0 +* INOUT : bl_out_1 +* INOUT : br_out_1 +* INOUT : bl_out_2 +* INOUT : br_out_2 +* INOUT : bl_out_3 +* INOUT : br_out_3 +* INOUT : bl_out_4 +* INOUT : br_out_4 +* INOUT : bl_out_5 +* INOUT : br_out_5 +* INOUT : bl_out_6 +* INOUT : br_out_6 +* INOUT : bl_out_7 +* INOUT : br_out_7 +* INOUT : bl_out_8 +* INOUT : br_out_8 +* INOUT : bl_out_9 +* INOUT : br_out_9 +* INOUT : bl_out_10 +* INOUT : br_out_10 +* INOUT : bl_out_11 +* INOUT : br_out_11 +* INOUT : bl_out_12 +* INOUT : br_out_12 +* INOUT : bl_out_13 +* INOUT : br_out_13 +* INOUT : bl_out_14 +* INOUT : br_out_14 +* INOUT : bl_out_15 +* INOUT : br_out_15 +* INOUT : bl_out_16 +* INOUT : br_out_16 +* INOUT : bl_out_17 +* INOUT : br_out_17 +* INOUT : bl_out_18 +* INOUT : br_out_18 +* INOUT : bl_out_19 +* INOUT : br_out_19 +* INOUT : bl_out_20 +* INOUT : br_out_20 +* INOUT : bl_out_21 +* INOUT : br_out_21 +* INOUT : bl_out_22 +* INOUT : br_out_22 +* INOUT : bl_out_23 +* INOUT : br_out_23 +* INOUT : bl_out_24 +* INOUT : br_out_24 +* INOUT : bl_out_25 +* INOUT : br_out_25 +* INOUT : bl_out_26 +* INOUT : br_out_26 +* INOUT : bl_out_27 +* INOUT : br_out_27 +* INOUT : bl_out_28 +* INOUT : br_out_28 +* INOUT : bl_out_29 +* INOUT : br_out_29 +* INOUT : bl_out_30 +* INOUT : br_out_30 +* INOUT : bl_out_31 +* INOUT : br_out_31 +* INOUT : bl_out_32 +* INOUT : br_out_32 +* INOUT : bl_out_33 +* INOUT : br_out_33 +* INOUT : bl_out_34 +* INOUT : br_out_34 +* INOUT : bl_out_35 +* INOUT : br_out_35 +* INOUT : bl_out_36 +* INOUT : br_out_36 +* INOUT : bl_out_37 +* INOUT : br_out_37 +* INOUT : bl_out_38 +* INOUT : br_out_38 +* INOUT : bl_out_39 +* INOUT : br_out_39 +* INOUT : bl_out_40 +* INOUT : br_out_40 +* INOUT : bl_out_41 +* INOUT : br_out_41 +* INOUT : bl_out_42 +* INOUT : br_out_42 +* INOUT : bl_out_43 +* INOUT : br_out_43 +* INOUT : bl_out_44 +* INOUT : br_out_44 +* INOUT : bl_out_45 +* INOUT : br_out_45 +* INOUT : bl_out_46 +* INOUT : br_out_46 +* INOUT : bl_out_47 +* INOUT : br_out_47 +* INOUT : bl_out_48 +* INOUT : br_out_48 +* INOUT : bl_out_49 +* INOUT : br_out_49 +* INOUT : bl_out_50 +* INOUT : br_out_50 +* INOUT : bl_out_51 +* INOUT : br_out_51 +* INOUT : bl_out_52 +* INOUT : br_out_52 +* INOUT : bl_out_53 +* INOUT : br_out_53 +* INOUT : bl_out_54 +* INOUT : br_out_54 +* INOUT : bl_out_55 +* INOUT : br_out_55 +* INOUT : bl_out_56 +* INOUT : br_out_56 +* INOUT : bl_out_57 +* INOUT : br_out_57 +* INOUT : bl_out_58 +* INOUT : br_out_58 +* INOUT : bl_out_59 +* INOUT : br_out_59 +* INOUT : bl_out_60 +* INOUT : br_out_60 +* INOUT : bl_out_61 +* INOUT : br_out_61 +* INOUT : bl_out_62 +* INOUT : br_out_62 +* INOUT : bl_out_63 +* INOUT : br_out_63 +* INOUT : gnd +* cols: 128 word_size: 64 bl: bl br: br +XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux +XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux +XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux +XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux +XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux +XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux +XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux +XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux +XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux +XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux +XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux +XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux +XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux +XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux +XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux +XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux +XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux +XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux +XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux +XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux +XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux +XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux +XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux +XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux +XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux +XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux +XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux +XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux +XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux +XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux +XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux +XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux +XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux +XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux +XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux +XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux +XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux +XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux +XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux +XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux +XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux +XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux +XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux +XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux +XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux +XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux +XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux +XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux +XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux +XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux +XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux +XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux +XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux +XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux +XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux +XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux +XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux +XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux +XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux +XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux +XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux +XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux +XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux +XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux +XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux +XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux +XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux +XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux +XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux +XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux +XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux +XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux +XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux +XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux +XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux +XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux +XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux +XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux +XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux +XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux +XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux +XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux +XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux +XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux +XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux +XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux +XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux +XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux +XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux +XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux +XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux +XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux +XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux +XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux +XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux +XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux +XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux +XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux +XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux +XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux +XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux +XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux +XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux +XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux +XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux +XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux +XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux +XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux +XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux +XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux +XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux +XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux +XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux +XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux +XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux +XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux +XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux +XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux +XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux +XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux +XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux +XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux +XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux +XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux +XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux +XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux +XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux +XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux +.ENDS column_mux_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* INPUT : sel_0 +* INPUT : sel_1 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array +Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2 + +* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p +.ENDS pinv_0 + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 32 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv_0 +.ENDS and2_dec_0 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv_0 +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* INPUT : in_16 +* INPUT : in_17 +* INPUT : in_18 +* INPUT : in_19 +* INPUT : in_20 +* INPUT : in_21 +* INPUT : in_22 +* INPUT : in_23 +* INPUT : in_24 +* INPUT : in_25 +* INPUT : in_26 +* INPUT : in_27 +* INPUT : in_28 +* INPUT : in_29 +* INPUT : in_30 +* INPUT : in_31 +* INPUT : in_32 +* INPUT : in_33 +* INPUT : in_34 +* INPUT : in_35 +* INPUT : in_36 +* INPUT : in_37 +* INPUT : in_38 +* INPUT : in_39 +* INPUT : in_40 +* INPUT : in_41 +* INPUT : in_42 +* INPUT : in_43 +* INPUT : in_44 +* INPUT : in_45 +* INPUT : in_46 +* INPUT : in_47 +* INPUT : in_48 +* INPUT : in_49 +* INPUT : in_50 +* INPUT : in_51 +* INPUT : in_52 +* INPUT : in_53 +* INPUT : in_54 +* INPUT : in_55 +* INPUT : in_56 +* INPUT : in_57 +* INPUT : in_58 +* INPUT : in_59 +* INPUT : in_60 +* INPUT : in_61 +* INPUT : in_62 +* INPUT : in_63 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver +Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver +Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver +Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver +Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver +Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver +Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver +Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver +Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver +Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver +Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver +Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver +Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver +Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver +Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver +Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver +Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver +Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver +Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver +Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver +Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver +Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver +Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver +Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver +Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver +Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver +Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver +Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver +Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver +Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver +Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver +Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver +Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver +Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver +Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver +Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver +Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver +Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver +Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver +Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver +Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver +Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver +Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver +Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver +Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver +Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver +Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver +Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver +.ENDS wordline_driver_array + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3 + +.SUBCKT and3_dec A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand3_dec_nand A B C zb_int vdd gnd pnand3 +Xpand3_dec_inv zb_int Z vdd gnd pinv +.ENDS and3_dec + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* OUTPUT: decode_16 +* OUTPUT: decode_17 +* OUTPUT: decode_18 +* OUTPUT: decode_19 +* OUTPUT: decode_20 +* OUTPUT: decode_21 +* OUTPUT: decode_22 +* OUTPUT: decode_23 +* OUTPUT: decode_24 +* OUTPUT: decode_25 +* OUTPUT: decode_26 +* OUTPUT: decode_27 +* OUTPUT: decode_28 +* OUTPUT: decode_29 +* OUTPUT: decode_30 +* OUTPUT: decode_31 +* OUTPUT: decode_32 +* OUTPUT: decode_33 +* OUTPUT: decode_34 +* OUTPUT: decode_35 +* OUTPUT: decode_36 +* OUTPUT: decode_37 +* OUTPUT: decode_38 +* OUTPUT: decode_39 +* OUTPUT: decode_40 +* OUTPUT: decode_41 +* OUTPUT: decode_42 +* OUTPUT: decode_43 +* OUTPUT: decode_44 +* OUTPUT: decode_45 +* OUTPUT: decode_46 +* OUTPUT: decode_47 +* OUTPUT: decode_48 +* OUTPUT: decode_49 +* OUTPUT: decode_50 +* OUTPUT: decode_51 +* OUTPUT: decode_52 +* OUTPUT: decode_53 +* OUTPUT: decode_54 +* OUTPUT: decode_55 +* OUTPUT: decode_56 +* OUTPUT: decode_57 +* OUTPUT: decode_58 +* OUTPUT: decode_59 +* OUTPUT: decode_60 +* OUTPUT: decode_61 +* OUTPUT: decode_62 +* OUTPUT: decode_63 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 +Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 +XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec +XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec +XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec +XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec +XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec +XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec +XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec +XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec +XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec +XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec +XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec +XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec +XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec +XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec +XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec +XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec +XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec +XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec +XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec +XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec +XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec +XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec +XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec +XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec +XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec +XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec +XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec +XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec +XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec +XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec +XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec +XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec +XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec +XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec +XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec +XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec +XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec +XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec +XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec +XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec +XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec +XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec +XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec +XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec +XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec +XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec +XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec +XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec +XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec +XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec +XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec +XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec +XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec +XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec +XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec +XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec +XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec +XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec +XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec +XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec +XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec +XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec +XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec +XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec +.ENDS hierarchical_decoder + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: dout0_2 +* OUTPUT: dout0_3 +* OUTPUT: dout0_4 +* OUTPUT: dout0_5 +* OUTPUT: dout0_6 +* OUTPUT: dout0_7 +* OUTPUT: dout0_8 +* OUTPUT: dout0_9 +* OUTPUT: dout0_10 +* OUTPUT: dout0_11 +* OUTPUT: dout0_12 +* OUTPUT: dout0_13 +* OUTPUT: dout0_14 +* OUTPUT: dout0_15 +* OUTPUT: dout0_16 +* OUTPUT: dout0_17 +* OUTPUT: dout0_18 +* OUTPUT: dout0_19 +* OUTPUT: dout0_20 +* OUTPUT: dout0_21 +* OUTPUT: dout0_22 +* OUTPUT: dout0_23 +* OUTPUT: dout0_24 +* OUTPUT: dout0_25 +* OUTPUT: dout0_26 +* OUTPUT: dout0_27 +* OUTPUT: dout0_28 +* OUTPUT: dout0_29 +* OUTPUT: dout0_30 +* OUTPUT: dout0_31 +* OUTPUT: dout0_32 +* OUTPUT: dout0_33 +* OUTPUT: dout0_34 +* OUTPUT: dout0_35 +* OUTPUT: dout0_36 +* OUTPUT: dout0_37 +* OUTPUT: dout0_38 +* OUTPUT: dout0_39 +* OUTPUT: dout0_40 +* OUTPUT: dout0_41 +* OUTPUT: dout0_42 +* OUTPUT: dout0_43 +* OUTPUT: dout0_44 +* OUTPUT: dout0_45 +* OUTPUT: dout0_46 +* OUTPUT: dout0_47 +* OUTPUT: dout0_48 +* OUTPUT: dout0_49 +* OUTPUT: dout0_50 +* OUTPUT: dout0_51 +* OUTPUT: dout0_52 +* OUTPUT: dout0_53 +* OUTPUT: dout0_54 +* OUTPUT: dout0_55 +* OUTPUT: dout0_56 +* OUTPUT: dout0_57 +* OUTPUT: dout0_58 +* OUTPUT: dout0_59 +* OUTPUT: dout0_60 +* OUTPUT: dout0_61 +* OUTPUT: dout0_62 +* OUTPUT: dout0_63 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : din0_2 +* INPUT : din0_3 +* INPUT : din0_4 +* INPUT : din0_5 +* INPUT : din0_6 +* INPUT : din0_7 +* INPUT : din0_8 +* INPUT : din0_9 +* INPUT : din0_10 +* INPUT : din0_11 +* INPUT : din0_12 +* INPUT : din0_13 +* INPUT : din0_14 +* INPUT : din0_15 +* INPUT : din0_16 +* INPUT : din0_17 +* INPUT : din0_18 +* INPUT : din0_19 +* INPUT : din0_20 +* INPUT : din0_21 +* INPUT : din0_22 +* INPUT : din0_23 +* INPUT : din0_24 +* INPUT : din0_25 +* INPUT : din0_26 +* INPUT : din0_27 +* INPUT : din0_28 +* INPUT : din0_29 +* INPUT : din0_30 +* INPUT : din0_31 +* INPUT : din0_32 +* INPUT : din0_33 +* INPUT : din0_34 +* INPUT : din0_35 +* INPUT : din0_36 +* INPUT : din0_37 +* INPUT : din0_38 +* INPUT : din0_39 +* INPUT : din0_40 +* INPUT : din0_41 +* INPUT : din0_42 +* INPUT : din0_43 +* INPUT : din0_44 +* INPUT : din0_45 +* INPUT : din0_46 +* INPUT : din0_47 +* INPUT : din0_48 +* INPUT : din0_49 +* INPUT : din0_50 +* INPUT : din0_51 +* INPUT : din0_52 +* INPUT : din0_53 +* INPUT : din0_54 +* INPUT : din0_55 +* INPUT : din0_56 +* INPUT : din0_57 +* INPUT : din0_58 +* INPUT : din0_59 +* INPUT : din0_60 +* INPUT : din0_61 +* INPUT : din0_62 +* INPUT : din0_63 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : addr0_4 +* INPUT : addr0_5 +* INPUT : addr0_6 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address +Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf +.ENDS bank + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_2 +Xdff_buf_inv2 Qb Q vdd gnd pinv_3 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_0 + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +.SUBCKT pinv_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p +.ENDS pinv_4 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_4 +.ENDS pdriver + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p +Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p +.ENDS pinv_11 + +* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p +.ENDS pinv_9 + +* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p +Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +.ENDS pinv_10 + +* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p + +* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p + +.SUBCKT pinv_12 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p +Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p +.ENDS pinv_12 + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_7 + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_8 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 1, 2, 5, 14, 42, 125] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 +Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 +Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 +Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 +.ENDS pdriver_0 + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3_0 + +* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p + +* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +.SUBCKT pinv_16 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p +Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +.ENDS pinv_16 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [64] +Xbuf_inv1 A Z vdd gnd pinv_16 +.ENDS pdriver_3 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +.SUBCKT pinv_17 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_17 + +* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p + +* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p + +.SUBCKT pinv_18 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p +Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p +.ENDS pinv_18 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 2, 5, 14, 43] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 +Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 +.ENDS pdriver_4 + +* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p + +* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p + +.SUBCKT pinv_15 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p +Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p +.ENDS pinv_15 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [72] +Xbuf_inv1 A Z vdd gnd pinv_15 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT pinv_19 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_19 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_19 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 +Xdinv1 dout_1 dout_2 vdd gnd pinv_19 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 +Xdinv2 dout_2 dout_3 vdd gnd pinv_19 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 +Xdinv3 dout_3 dout_4 vdd gnd pinv_19 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 +Xdinv4 dout_4 dout_5 vdd gnd pinv_19 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 +Xdinv5 dout_5 dout_6 vdd gnd pinv_19 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 +Xdinv6 dout_6 dout_7 vdd gnd pinv_19 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 +Xdinv7 dout_7 dout_8 vdd gnd pinv_19 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 +Xdinv8 dout_8 out vdd gnd pinv_19 +Xdload_8_0 out n_8_0 vdd gnd pinv_19 +Xdload_8_1 out n_8_1 vdd gnd pinv_19 +Xdload_8_2 out n_8_2 vdd gnd pinv_19 +Xdload_8_3 out n_8_3 vdd gnd pinv_19 +.ENDS delay_chain + +* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p + +.SUBCKT pinv_14 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p +Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p +.ENDS pinv_14 + +* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p + +.SUBCKT pinv_13 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p +.ENDS pinv_13 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [7, 21] +Xbuf_inv1 A Zb1_int vdd gnd pinv_13 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 +.ENDS pdriver_1 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_1 + +* Used for tiling delay chain to desired length +.SUBCKT delay_chain_segment in out vdd gnd +Xdinv0 in dout_1 vdd gnd pinv_11 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 +Xdinv1 dout_1 out vdd gnd pinv_11 +Xdload_1_0 out n_1_0 vdd gnd pinv_11 +Xdload_1_1 out n_1_1 vdd gnd pinv_11 +Xdload_1_2 out n_1_2 vdd gnd pinv_11 +Xdload_1_3 out n_1_3 vdd gnd pinv_11 +.ENDS delay_chain_segment + +.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd +Xdelay1 in out1 vdd gnd delay_chain_segment +Xdelay2 out1 out2 vdd gnd delay_chain_segment +Xdelay3 out2 out3 vdd gnd delay_chain_segment +Xdelay4 out3 out4 vdd gnd delay_chain_segment +Xdelay5 out4 out5 vdd gnd delay_chain_segment +Xdelay6 out5 out6 vdd gnd delay_chain_segment +Xdelay7 out6 out7 vdd gnd delay_chain_segment +Xdelay8 out7 out8 vdd gnd delay_chain_segment +Xdelay9 out8 out9 vdd gnd delay_chain_segment +Xdelay10 out9 out10 vdd gnd delay_chain_segment +Xdelay11 out10 out11 vdd gnd delay_chain_segment +Xdelay12 out11 out12 vdd gnd delay_chain_segment +Xdelay13 out12 out13 vdd gnd delay_chain_segment +Xdelay14 out13 out14 vdd gnd delay_chain_segment +Xdelay15 out14 out15 vdd gnd delay_chain_segment +Xdelay16 out15 out16 vdd gnd delay_chain_segment +.ENDS multi_delay_chain + +.SUBCKT glitch_generator in glitch1_bar glitch2_bar glitch3_bar vdd gnd +*.PININFO in:I glitch1_bar:O glitch2_bar:O glitch3_bar:O vdd:B gnd:B +Xmulti_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain +Xinv_g1 out6 g1_end vdd gnd pinv_11 +Xinv_g2 out7 g2_end vdd gnd pinv_11 +Xinv_g3 out14 g3_end vdd gnd pinv_11 +Xnand2_g1 out1 g1_end glitch1_bar vdd gnd pnand2 +Xnand2_g2 in g2_end glitch2_bar vdd gnd pnand2 +Xnand2_g3 out6 g3_end glitch3_bar vdd gnd pnand2 +.ENDS glitch_generator + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl (NO LONGER USED) +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +* is cs_buf needed on larger memories? +Xbuf_cs cs cs_buf vdd gnd pdriver_0 +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xglitch_generator gated_clk_buf glitch1_bar glitch2_bar glitch3_bar vdd gnd glitch_generator +Xinv_g3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 +Xinv_pre_s glitch3_buf pre_s vdd gnd pinv_11 +Xand_s_en we_bar gated_clk_bar pre_s s_en vdd gnd pand3 +Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 +Xand_wl_en cs_buf glitch2_bar wl_en vdd gnd pand2 +Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd +*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : din0[2] +* INPUT : din0[3] +* INPUT : din0[4] +* INPUT : din0[5] +* INPUT : din0[6] +* INPUT : din0[7] +* INPUT : din0[8] +* INPUT : din0[9] +* INPUT : din0[10] +* INPUT : din0[11] +* INPUT : din0[12] +* INPUT : din0[13] +* INPUT : din0[14] +* INPUT : din0[15] +* INPUT : din0[16] +* INPUT : din0[17] +* INPUT : din0[18] +* INPUT : din0[19] +* INPUT : din0[20] +* INPUT : din0[21] +* INPUT : din0[22] +* INPUT : din0[23] +* INPUT : din0[24] +* INPUT : din0[25] +* INPUT : din0[26] +* INPUT : din0[27] +* INPUT : din0[28] +* INPUT : din0[29] +* INPUT : din0[30] +* INPUT : din0[31] +* INPUT : din0[32] +* INPUT : din0[33] +* INPUT : din0[34] +* INPUT : din0[35] +* INPUT : din0[36] +* INPUT : din0[37] +* INPUT : din0[38] +* INPUT : din0[39] +* INPUT : din0[40] +* INPUT : din0[41] +* INPUT : din0[42] +* INPUT : din0[43] +* INPUT : din0[44] +* INPUT : din0[45] +* INPUT : din0[46] +* INPUT : din0[47] +* INPUT : din0[48] +* INPUT : din0[49] +* INPUT : din0[50] +* INPUT : din0[51] +* INPUT : din0[52] +* INPUT : din0[53] +* INPUT : din0[54] +* INPUT : din0[55] +* INPUT : din0[56] +* INPUT : din0[57] +* INPUT : din0[58] +* INPUT : din0[59] +* INPUT : din0[60] +* INPUT : din0[61] +* INPUT : din0[62] +* INPUT : din0[63] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : addr0[4] +* INPUT : addr0[5] +* INPUT : addr0[6] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* OUTPUT: dout0[2] +* OUTPUT: dout0[3] +* OUTPUT: dout0[4] +* OUTPUT: dout0[5] +* OUTPUT: dout0[6] +* OUTPUT: dout0[7] +* OUTPUT: dout0[8] +* OUTPUT: dout0[9] +* OUTPUT: dout0[10] +* OUTPUT: dout0[11] +* OUTPUT: dout0[12] +* OUTPUT: dout0[13] +* OUTPUT: dout0[14] +* OUTPUT: dout0[15] +* OUTPUT: dout0[16] +* OUTPUT: dout0[17] +* OUTPUT: dout0[18] +* OUTPUT: dout0[19] +* OUTPUT: dout0[20] +* OUTPUT: dout0[21] +* OUTPUT: dout0[22] +* OUTPUT: dout0[23] +* OUTPUT: dout0[24] +* OUTPUT: dout0[25] +* OUTPUT: dout0[26] +* OUTPUT: dout0[27] +* OUTPUT: dout0[28] +* OUTPUT: dout0[29] +* OUTPUT: dout0[30] +* OUTPUT: dout0[31] +* OUTPUT: dout0[32] +* OUTPUT: dout0[33] +* OUTPUT: dout0[34] +* OUTPUT: dout0[35] +* OUTPUT: dout0[36] +* OUTPUT: dout0[37] +* OUTPUT: dout0[38] +* OUTPUT: dout0[39] +* OUTPUT: dout0[40] +* OUTPUT: dout0[41] +* OUTPUT: dout0[42] +* OUTPUT: dout0[43] +* OUTPUT: dout0[44] +* OUTPUT: dout0[45] +* OUTPUT: dout0[46] +* OUTPUT: dout0[47] +* OUTPUT: dout0[48] +* OUTPUT: dout0[49] +* OUTPUT: dout0[50] +* OUTPUT: dout0[51] +* OUTPUT: dout0[52] +* OUTPUT: dout0[53] +* OUTPUT: dout0[54] +* OUTPUT: dout0[55] +* OUTPUT: dout0[56] +* OUTPUT: dout0[57] +* OUTPUT: dout0[58] +* OUTPUT: dout0[59] +* OUTPUT: dout0[60] +* OUTPUT: dout0[61] +* OUTPUT: dout0[62] +* OUTPUT: dout0[63] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff +Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff +Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff +.ENDS sram_64_128_scn4m_subm diff --git a/1KB/sram_64_128_scn4m_subm.html b/1KB/sram_64_128_scn4m_subm.html new file mode 100644 index 00000000..0d27ecf0 --- /dev/null +++ b/1KB/sram_64_128_scn4m_subm.html @@ -0,0 +1,35 @@ + + +VLSIDAOpenRAM

sram_64_128_scn4m_subm.html

Compiled at: 2022-01-27

DRC errors: skipped

LVS errors: skipped

Git commit id: 06d391b3e365127628434b98044035232615f4b0

Ports and Configuration

TypeValue
WORD_SIZE64
NUM_WORDS128
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0
+

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)122MHz
+

Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[63:0] setup rising0.0090.009ns
din0[63:0] setup falling0.0090.009ns
din0[63:0] hold rising0.0010.001ns
din0[63:0] hold falling0.0010.001ns
dout0[63:0] cell rise2.1252.215ns
dout0[63:0] cell fall2.1252.215ns
dout0[63:0] rise transition0.0060.015ns
dout0[63:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[6:0] setup rising0.0090.009ns
addr0[6:0] setup falling0.0090.009ns
addr0[6:0] hold rising0.0010.001ns
addr0[6:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns
+

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising13.524mW
!csb0 & clk0 & !web0Read Falling13.524mW
!csb0 & !clk0 & web0Write Rising13.524mW
!csb0 & !clk0 & web0Write Falling13.524mW
csb0leakage0.008633mW
+

Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib
+

Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_64_128_scn4m_subm.html
.libSynthesis modelssram_64_128_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_64_128_scn4m_subm.log
.pyOpenRAM configuration filesram_64_128_scn4m_subm.py
.spSPICE netlistssram_64_128_scn4m_subm.sp
.vVerilog simulation modelssram_64_128_scn4m_subm.v
diff --git a/1KB/sram_64_128_scn4m_subm.lvs.sp b/1KB/sram_64_128_scn4m_subm.lvs.sp new file mode 100644 index 00000000..8eab54dd --- /dev/null +++ b/1KB/sram_64_128_scn4m_subm.lvs.sp @@ -0,0 +1,14050 @@ +************************************************** +* OpenRAM generated memory. +* Words: 128 +* Data bits: 64 +* Banks: 1 +* Column mux: 2:1 +* Trimmed: False +* LVS: True +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 6 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff +Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff +.ENDS row_addr_dff + +.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd +*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B +* INPUT : din_0 +* OUTPUT: dout_0 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +.ENDS col_addr_dff + +.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 64 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff +Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff +Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff +Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff +Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff +Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff +Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff +Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff +Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff +Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff +Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff +Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff +Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff +Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff +Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff +Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff +Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff +Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff +Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff +Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff +Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff +Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff +Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff +Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff +Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff +Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff +Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff +Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff +Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff +Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff +Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff +Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff +Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff +Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff +Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff +Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff +Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff +Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff +Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff +Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff +Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff +Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff +Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff +Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff +Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff +Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff +Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff +Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff +Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff +Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff +Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff +Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff +Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff +Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff +Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff +Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff +Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff +Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff +Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff +Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff +Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff +Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff +.ENDS data_dff + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pinv_2 + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u +.ENDS pinv_3 + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_1 + +.SUBCKT pinvbuf A Zb Z vdd gnd +*.PININFO A:B Zb:B Z:B vdd:B gnd:B +* INOUT : A +* INOUT : Zb +* INOUT : Z +* INOUT : vdd +* INOUT : gnd +Xbuf_inv1 A zb_int vdd gnd pinv_1 +Xbuf_inv2 zb_int z_int vdd gnd pinv_2 +Xbuf_inv3 z_int Zb vdd gnd pinv_3 +Xbuf_inv4 zb_int Z vdd gnd pinv_3 +.ENDS pinvbuf + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw +Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw +Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw +Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw +Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw +Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw +Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw +Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw +Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw +Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw +Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw +Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw +Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw +Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw +Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw +Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw +Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw +Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw +Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw +Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw +Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw +Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw +Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw +Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw +Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw +Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw +Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw +Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw +Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw +Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw +Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw +Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw +Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw +Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw +Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw +Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw +Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw +Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw +Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw +Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw +Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw +Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw +Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw +Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw +Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw +Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw +Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw +Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw +Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c15 bl_0_15 br_0_15 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c15 bl_0_15 br_0_15 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c15 bl_0_15 br_0_15 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c15 bl_0_15 br_0_15 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c15 bl_0_15 br_0_15 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c15 bl_0_15 br_0_15 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c15 bl_0_15 br_0_15 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c15 bl_0_15 br_0_15 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c15 bl_0_15 br_0_15 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c15 bl_0_15 br_0_15 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c15 bl_0_15 br_0_15 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c15 bl_0_15 br_0_15 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c15 bl_0_15 br_0_15 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c44 bl_0_44 br_0_44 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c44 bl_0_44 br_0_44 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c44 bl_0_44 br_0_44 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c44 bl_0_44 br_0_44 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c44 bl_0_44 br_0_44 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c44 bl_0_44 br_0_44 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c44 bl_0_44 br_0_44 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c44 bl_0_44 br_0_44 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c44 bl_0_44 br_0_44 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c44 bl_0_44 br_0_44 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c44 bl_0_44 br_0_44 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c44 bl_0_44 br_0_44 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c44 bl_0_44 br_0_44 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c44 bl_0_44 br_0_44 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c44 bl_0_44 br_0_44 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c44 bl_0_44 br_0_44 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c44 bl_0_44 br_0_44 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c44 bl_0_44 br_0_44 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c49 bl_0_49 br_0_49 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c49 bl_0_49 br_0_49 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c49 bl_0_49 br_0_49 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c49 bl_0_49 br_0_49 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c49 bl_0_49 br_0_49 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c49 bl_0_49 br_0_49 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c49 bl_0_49 br_0_49 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c49 bl_0_49 br_0_49 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c49 bl_0_49 br_0_49 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c49 bl_0_49 br_0_49 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c49 bl_0_49 br_0_49 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c49 bl_0_49 br_0_49 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c49 bl_0_49 br_0_49 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c49 bl_0_49 br_0_49 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c49 bl_0_49 br_0_49 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c49 bl_0_49 br_0_49 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c49 bl_0_49 br_0_49 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c49 bl_0_49 br_0_49 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw 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br_0_53 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c53 bl_0_53 br_0_53 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c53 bl_0_53 br_0_53 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c53 bl_0_53 br_0_53 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c53 bl_0_53 br_0_53 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c53 bl_0_53 br_0_53 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c53 bl_0_53 br_0_53 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c53 bl_0_53 br_0_53 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c53 bl_0_53 br_0_53 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c53 bl_0_53 br_0_53 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c53 bl_0_53 br_0_53 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c53 bl_0_53 br_0_53 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c53 bl_0_53 br_0_53 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c53 bl_0_53 br_0_53 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c53 bl_0_53 br_0_53 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c53 bl_0_53 br_0_53 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c53 bl_0_53 br_0_53 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c53 bl_0_53 br_0_53 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c53 bl_0_53 br_0_53 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c53 bl_0_53 br_0_53 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c53 bl_0_53 br_0_53 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c53 bl_0_53 br_0_53 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c53 bl_0_53 br_0_53 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c53 bl_0_53 br_0_53 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c53 bl_0_53 br_0_53 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c53 bl_0_53 br_0_53 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c53 bl_0_53 br_0_53 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c53 bl_0_53 br_0_53 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c53 bl_0_53 br_0_53 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c53 bl_0_53 br_0_53 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c53 bl_0_53 br_0_53 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c53 bl_0_53 br_0_53 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c53 bl_0_53 br_0_53 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c53 bl_0_53 br_0_53 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c53 bl_0_53 br_0_53 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c53 bl_0_53 br_0_53 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c53 bl_0_53 br_0_53 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw 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wl_0_15 vdd gnd cell_1rw +Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c73 bl_0_73 br_0_73 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c73 bl_0_73 br_0_73 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c73 bl_0_73 br_0_73 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c73 bl_0_73 br_0_73 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c73 bl_0_73 br_0_73 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c73 bl_0_73 br_0_73 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c73 bl_0_73 br_0_73 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c73 bl_0_73 br_0_73 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c73 bl_0_73 br_0_73 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c73 bl_0_73 br_0_73 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c73 bl_0_73 br_0_73 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c73 bl_0_73 br_0_73 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c73 bl_0_73 br_0_73 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c73 bl_0_73 br_0_73 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c73 bl_0_73 br_0_73 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c73 bl_0_73 br_0_73 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c73 bl_0_73 br_0_73 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c73 bl_0_73 br_0_73 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c74 bl_0_74 br_0_74 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c74 bl_0_74 br_0_74 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c74 bl_0_74 br_0_74 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c74 bl_0_74 br_0_74 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c74 bl_0_74 br_0_74 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c74 bl_0_74 br_0_74 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c74 bl_0_74 br_0_74 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c74 bl_0_74 br_0_74 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c74 bl_0_74 br_0_74 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c74 bl_0_74 br_0_74 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c74 bl_0_74 br_0_74 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c74 bl_0_74 br_0_74 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c74 bl_0_74 br_0_74 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c74 bl_0_74 br_0_74 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c74 bl_0_74 br_0_74 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c74 bl_0_74 br_0_74 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c74 bl_0_74 br_0_74 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c74 bl_0_74 br_0_74 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw 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bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw 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wl_0_12 vdd gnd cell_1rw +Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw 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wl_0_11 vdd gnd cell_1rw +Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c83 bl_0_83 br_0_83 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c83 bl_0_83 br_0_83 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c84 bl_0_84 br_0_84 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c84 bl_0_84 br_0_84 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c84 bl_0_84 br_0_84 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c84 bl_0_84 br_0_84 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c84 bl_0_84 br_0_84 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c84 bl_0_84 br_0_84 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c84 bl_0_84 br_0_84 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c84 bl_0_84 br_0_84 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c84 bl_0_84 br_0_84 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c84 bl_0_84 br_0_84 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c84 bl_0_84 br_0_84 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c84 bl_0_84 br_0_84 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c84 bl_0_84 br_0_84 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c84 bl_0_84 br_0_84 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c84 bl_0_84 br_0_84 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c84 bl_0_84 br_0_84 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw 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wl_0_10 vdd gnd cell_1rw +Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c89 bl_0_89 br_0_89 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c89 bl_0_89 br_0_89 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c89 bl_0_89 br_0_89 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c90 bl_0_90 br_0_90 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c90 bl_0_90 br_0_90 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c90 bl_0_90 br_0_90 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c90 bl_0_90 br_0_90 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c90 bl_0_90 br_0_90 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c90 bl_0_90 br_0_90 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c90 bl_0_90 br_0_90 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c90 bl_0_90 br_0_90 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c90 bl_0_90 br_0_90 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c90 bl_0_90 br_0_90 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c90 bl_0_90 br_0_90 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c90 bl_0_90 br_0_90 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c90 bl_0_90 br_0_90 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c90 bl_0_90 br_0_90 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c90 bl_0_90 br_0_90 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw 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wl_0_17 vdd gnd cell_1rw +Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c98 bl_0_98 br_0_98 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c98 bl_0_98 br_0_98 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c98 bl_0_98 br_0_98 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c98 bl_0_98 br_0_98 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c98 bl_0_98 br_0_98 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c98 bl_0_98 br_0_98 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c98 bl_0_98 br_0_98 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c98 bl_0_98 br_0_98 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c98 bl_0_98 br_0_98 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c98 bl_0_98 br_0_98 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c98 bl_0_98 br_0_98 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c98 bl_0_98 br_0_98 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c98 bl_0_98 br_0_98 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c98 bl_0_98 br_0_98 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c99 bl_0_99 br_0_99 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c99 bl_0_99 br_0_99 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c99 bl_0_99 br_0_99 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c99 bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c100 bl_0_100 br_0_100 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c100 bl_0_100 br_0_100 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c100 bl_0_100 br_0_100 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c100 bl_0_100 br_0_100 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c100 bl_0_100 br_0_100 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c100 bl_0_100 br_0_100 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c100 bl_0_100 br_0_100 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c100 bl_0_100 br_0_100 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c100 bl_0_100 br_0_100 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c100 bl_0_100 br_0_100 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c100 bl_0_100 br_0_100 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c100 bl_0_100 br_0_100 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c100 bl_0_100 br_0_100 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c100 bl_0_100 br_0_100 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c100 bl_0_100 br_0_100 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c100 bl_0_100 br_0_100 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c100 bl_0_100 br_0_100 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c108 bl_0_108 br_0_108 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c108 bl_0_108 br_0_108 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c108 bl_0_108 br_0_108 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c108 bl_0_108 br_0_108 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c108 bl_0_108 br_0_108 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c108 bl_0_108 br_0_108 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c108 bl_0_108 br_0_108 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c108 bl_0_108 br_0_108 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c108 bl_0_108 br_0_108 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c108 bl_0_108 br_0_108 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c108 bl_0_108 br_0_108 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c108 bl_0_108 br_0_108 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c108 bl_0_108 br_0_108 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c108 bl_0_108 br_0_108 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c108 bl_0_108 br_0_108 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c108 bl_0_108 br_0_108 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c108 bl_0_108 br_0_108 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c108 bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c110 bl_0_110 br_0_110 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c110 bl_0_110 br_0_110 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c110 bl_0_110 br_0_110 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c110 bl_0_110 br_0_110 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c110 bl_0_110 br_0_110 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c110 bl_0_110 br_0_110 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c110 bl_0_110 br_0_110 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c110 bl_0_110 br_0_110 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c110 bl_0_110 br_0_110 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c110 bl_0_110 br_0_110 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c110 bl_0_110 br_0_110 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c110 bl_0_110 br_0_110 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c110 bl_0_110 br_0_110 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c110 bl_0_110 br_0_110 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c110 bl_0_110 br_0_110 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c110 bl_0_110 br_0_110 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c110 bl_0_110 br_0_110 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c110 bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c111 bl_0_111 br_0_111 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c111 bl_0_111 br_0_111 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c111 bl_0_111 br_0_111 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c111 bl_0_111 br_0_111 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c111 bl_0_111 br_0_111 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c111 bl_0_111 br_0_111 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c111 bl_0_111 br_0_111 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c111 bl_0_111 br_0_111 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c111 bl_0_111 br_0_111 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c111 bl_0_111 br_0_111 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c111 bl_0_111 br_0_111 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c111 bl_0_111 br_0_111 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c111 bl_0_111 br_0_111 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c111 bl_0_111 br_0_111 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c111 bl_0_111 br_0_111 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c111 bl_0_111 br_0_111 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c111 bl_0_111 br_0_111 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c111 bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c112 bl_0_112 br_0_112 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c112 bl_0_112 br_0_112 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c112 bl_0_112 br_0_112 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c112 bl_0_112 br_0_112 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c112 bl_0_112 br_0_112 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c112 bl_0_112 br_0_112 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c112 bl_0_112 br_0_112 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c112 bl_0_112 br_0_112 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c112 bl_0_112 br_0_112 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c112 bl_0_112 br_0_112 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c112 bl_0_112 br_0_112 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c112 bl_0_112 br_0_112 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c112 bl_0_112 br_0_112 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c112 bl_0_112 br_0_112 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c112 bl_0_112 br_0_112 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c112 bl_0_112 br_0_112 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c112 bl_0_112 br_0_112 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c112 bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c114 bl_0_114 br_0_114 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c114 bl_0_114 br_0_114 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c114 bl_0_114 br_0_114 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c114 bl_0_114 br_0_114 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c114 bl_0_114 br_0_114 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c114 bl_0_114 br_0_114 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c114 bl_0_114 br_0_114 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c114 bl_0_114 br_0_114 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c114 bl_0_114 br_0_114 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c114 bl_0_114 br_0_114 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c114 bl_0_114 br_0_114 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c114 bl_0_114 br_0_114 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c114 bl_0_114 br_0_114 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c114 bl_0_114 br_0_114 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c114 bl_0_114 br_0_114 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c115 bl_0_115 br_0_115 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c115 bl_0_115 br_0_115 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c116 bl_0_116 br_0_116 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c116 bl_0_116 br_0_116 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c116 bl_0_116 br_0_116 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c116 bl_0_116 br_0_116 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c116 bl_0_116 br_0_116 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c116 bl_0_116 br_0_116 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c116 bl_0_116 br_0_116 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c116 bl_0_116 br_0_116 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c116 bl_0_116 br_0_116 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c116 bl_0_116 br_0_116 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c116 bl_0_116 br_0_116 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c116 bl_0_116 br_0_116 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c116 bl_0_116 br_0_116 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c116 bl_0_116 br_0_116 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c116 bl_0_116 br_0_116 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c116 bl_0_116 br_0_116 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c116 bl_0_116 br_0_116 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c116 bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c119 bl_0_119 br_0_119 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c119 bl_0_119 br_0_119 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c119 bl_0_119 br_0_119 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c119 bl_0_119 br_0_119 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c119 bl_0_119 br_0_119 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c119 bl_0_119 br_0_119 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c119 bl_0_119 br_0_119 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c119 bl_0_119 br_0_119 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c119 bl_0_119 br_0_119 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c119 bl_0_119 br_0_119 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c119 bl_0_119 br_0_119 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c119 bl_0_119 br_0_119 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c119 bl_0_119 br_0_119 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c119 bl_0_119 br_0_119 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c119 bl_0_119 br_0_119 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c119 bl_0_119 br_0_119 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c119 bl_0_119 br_0_119 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c119 bl_0_119 br_0_119 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c119 bl_0_119 br_0_119 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c119 bl_0_119 br_0_119 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c119 bl_0_119 br_0_119 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c119 bl_0_119 br_0_119 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c119 bl_0_119 br_0_119 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c119 bl_0_119 br_0_119 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c119 bl_0_119 br_0_119 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c119 bl_0_119 br_0_119 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c119 bl_0_119 br_0_119 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c119 bl_0_119 br_0_119 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c119 bl_0_119 br_0_119 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c119 bl_0_119 br_0_119 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c119 bl_0_119 br_0_119 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c119 bl_0_119 br_0_119 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c119 bl_0_119 br_0_119 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c119 bl_0_119 br_0_119 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c119 bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c120 bl_0_120 br_0_120 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c120 bl_0_120 br_0_120 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c120 bl_0_120 br_0_120 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c120 bl_0_120 br_0_120 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c120 bl_0_120 br_0_120 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c120 bl_0_120 br_0_120 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c120 bl_0_120 br_0_120 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c120 bl_0_120 br_0_120 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c120 bl_0_120 br_0_120 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c120 bl_0_120 br_0_120 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c120 bl_0_120 br_0_120 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c120 bl_0_120 br_0_120 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c120 bl_0_120 br_0_120 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c120 bl_0_120 br_0_120 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c120 bl_0_120 br_0_120 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c120 bl_0_120 br_0_120 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c120 bl_0_120 br_0_120 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c120 bl_0_120 br_0_120 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c120 bl_0_120 br_0_120 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c120 bl_0_120 br_0_120 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c120 bl_0_120 br_0_120 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c120 bl_0_120 br_0_120 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c120 bl_0_120 br_0_120 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c120 bl_0_120 br_0_120 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c120 bl_0_120 br_0_120 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c120 bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c121 bl_0_121 br_0_121 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c121 bl_0_121 br_0_121 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c121 bl_0_121 br_0_121 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c121 bl_0_121 br_0_121 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c121 bl_0_121 br_0_121 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c121 bl_0_121 br_0_121 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c121 bl_0_121 br_0_121 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c121 bl_0_121 br_0_121 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c121 bl_0_121 br_0_121 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c121 bl_0_121 br_0_121 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c121 bl_0_121 br_0_121 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c121 bl_0_121 br_0_121 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c121 bl_0_121 br_0_121 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c121 bl_0_121 br_0_121 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c121 bl_0_121 br_0_121 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c121 bl_0_121 br_0_121 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c121 bl_0_121 br_0_121 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c121 bl_0_121 br_0_121 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c121 bl_0_121 br_0_121 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c121 bl_0_121 br_0_121 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c121 bl_0_121 br_0_121 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c121 bl_0_121 br_0_121 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c121 bl_0_121 br_0_121 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c121 bl_0_121 br_0_121 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c121 bl_0_121 br_0_121 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c121 bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c122 bl_0_122 br_0_122 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c122 bl_0_122 br_0_122 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c122 bl_0_122 br_0_122 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c122 bl_0_122 br_0_122 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c122 bl_0_122 br_0_122 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c122 bl_0_122 br_0_122 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c122 bl_0_122 br_0_122 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c122 bl_0_122 br_0_122 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c122 bl_0_122 br_0_122 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c122 bl_0_122 br_0_122 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c122 bl_0_122 br_0_122 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c122 bl_0_122 br_0_122 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c122 bl_0_122 br_0_122 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c122 bl_0_122 br_0_122 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c122 bl_0_122 br_0_122 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c122 bl_0_122 br_0_122 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c122 bl_0_122 br_0_122 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c122 bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c123 bl_0_123 br_0_123 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c123 bl_0_123 br_0_123 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c123 bl_0_123 br_0_123 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c123 bl_0_123 br_0_123 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c123 bl_0_123 br_0_123 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c123 bl_0_123 br_0_123 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c123 bl_0_123 br_0_123 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c123 bl_0_123 br_0_123 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c123 bl_0_123 br_0_123 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c123 bl_0_123 br_0_123 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c123 bl_0_123 br_0_123 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c123 bl_0_123 br_0_123 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c123 bl_0_123 br_0_123 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c123 bl_0_123 br_0_123 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c123 bl_0_123 br_0_123 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c123 bl_0_123 br_0_123 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c123 bl_0_123 br_0_123 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c123 bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw 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bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw 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bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw +.ENDS bitcell_array + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* OUTPUT: data_2 +* INPUT : bl_2 +* INPUT : br_2 +* OUTPUT: data_3 +* INPUT : bl_3 +* INPUT : br_3 +* OUTPUT: data_4 +* INPUT : bl_4 +* INPUT : br_4 +* OUTPUT: data_5 +* INPUT : bl_5 +* INPUT : br_5 +* OUTPUT: data_6 +* INPUT : bl_6 +* INPUT : br_6 +* OUTPUT: data_7 +* INPUT : bl_7 +* INPUT : br_7 +* OUTPUT: data_8 +* INPUT : bl_8 +* INPUT : br_8 +* OUTPUT: data_9 +* INPUT : bl_9 +* INPUT : br_9 +* OUTPUT: data_10 +* INPUT : bl_10 +* INPUT : br_10 +* OUTPUT: data_11 +* INPUT : bl_11 +* INPUT : br_11 +* OUTPUT: data_12 +* INPUT : bl_12 +* INPUT : br_12 +* OUTPUT: data_13 +* INPUT : bl_13 +* INPUT : br_13 +* OUTPUT: data_14 +* INPUT : bl_14 +* INPUT : br_14 +* OUTPUT: data_15 +* INPUT : bl_15 +* INPUT : br_15 +* OUTPUT: data_16 +* INPUT : bl_16 +* INPUT : br_16 +* OUTPUT: data_17 +* INPUT : bl_17 +* INPUT : br_17 +* OUTPUT: data_18 +* INPUT : bl_18 +* INPUT : br_18 +* OUTPUT: data_19 +* INPUT : bl_19 +* INPUT : br_19 +* OUTPUT: data_20 +* INPUT : bl_20 +* INPUT : br_20 +* OUTPUT: data_21 +* INPUT : bl_21 +* INPUT : br_21 +* OUTPUT: data_22 +* INPUT : bl_22 +* INPUT : br_22 +* OUTPUT: data_23 +* INPUT : bl_23 +* INPUT : br_23 +* OUTPUT: data_24 +* INPUT : bl_24 +* INPUT : br_24 +* OUTPUT: data_25 +* INPUT : bl_25 +* INPUT : br_25 +* OUTPUT: data_26 +* INPUT : bl_26 +* INPUT : br_26 +* OUTPUT: data_27 +* INPUT : bl_27 +* INPUT : br_27 +* OUTPUT: data_28 +* INPUT : bl_28 +* INPUT : br_28 +* OUTPUT: data_29 +* INPUT : bl_29 +* INPUT : br_29 +* OUTPUT: data_30 +* INPUT : bl_30 +* INPUT : br_30 +* OUTPUT: data_31 +* INPUT : bl_31 +* INPUT : br_31 +* OUTPUT: data_32 +* INPUT : bl_32 +* INPUT : br_32 +* OUTPUT: data_33 +* INPUT : bl_33 +* INPUT : br_33 +* OUTPUT: data_34 +* INPUT : bl_34 +* INPUT : br_34 +* OUTPUT: data_35 +* INPUT : bl_35 +* INPUT : br_35 +* OUTPUT: data_36 +* INPUT : bl_36 +* INPUT : br_36 +* OUTPUT: data_37 +* INPUT : bl_37 +* INPUT : br_37 +* OUTPUT: data_38 +* INPUT : bl_38 +* INPUT : br_38 +* OUTPUT: data_39 +* INPUT : bl_39 +* INPUT : br_39 +* OUTPUT: data_40 +* INPUT : bl_40 +* INPUT : br_40 +* OUTPUT: data_41 +* INPUT : bl_41 +* INPUT : br_41 +* OUTPUT: data_42 +* INPUT : bl_42 +* INPUT : br_42 +* OUTPUT: data_43 +* INPUT : bl_43 +* INPUT : br_43 +* OUTPUT: data_44 +* INPUT : bl_44 +* INPUT : br_44 +* OUTPUT: data_45 +* INPUT : bl_45 +* INPUT : br_45 +* OUTPUT: data_46 +* INPUT : bl_46 +* INPUT : br_46 +* OUTPUT: data_47 +* INPUT : bl_47 +* INPUT : br_47 +* OUTPUT: data_48 +* INPUT : bl_48 +* INPUT : br_48 +* OUTPUT: data_49 +* INPUT : bl_49 +* INPUT : br_49 +* OUTPUT: data_50 +* INPUT : bl_50 +* INPUT : br_50 +* OUTPUT: data_51 +* INPUT : bl_51 +* INPUT : br_51 +* OUTPUT: data_52 +* INPUT : bl_52 +* INPUT : br_52 +* OUTPUT: data_53 +* INPUT : bl_53 +* INPUT : br_53 +* OUTPUT: data_54 +* INPUT : bl_54 +* INPUT : br_54 +* OUTPUT: data_55 +* INPUT : bl_55 +* INPUT : br_55 +* OUTPUT: data_56 +* INPUT : bl_56 +* INPUT : br_56 +* OUTPUT: data_57 +* INPUT : bl_57 +* INPUT : br_57 +* OUTPUT: data_58 +* INPUT : bl_58 +* INPUT : br_58 +* OUTPUT: data_59 +* INPUT : bl_59 +* INPUT : br_59 +* OUTPUT: data_60 +* INPUT : bl_60 +* INPUT : br_60 +* OUTPUT: data_61 +* INPUT : bl_61 +* INPUT : br_61 +* OUTPUT: data_62 +* INPUT : bl_62 +* INPUT : br_62 +* OUTPUT: data_63 +* INPUT : bl_63 +* INPUT : br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 2 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp +Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp +Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp +Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp +Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp +Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp +Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp +Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp +Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp +Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp +Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp +Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp +Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp +Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp +Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp +Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp +Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp +Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp +Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp +Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp +Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp +Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp +Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp +Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp +Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp +Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp +Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp +Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp +Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp +Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp +Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp +Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp +Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp +Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp +Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp +Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp +Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp +Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp +Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp +Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp +Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp +Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp +Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp +Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp +Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp +Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp +Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp +Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp +Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp +Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp +Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp +Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp +Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp +Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp +Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp +Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp +Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp +Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp +Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp +Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp +Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp +Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp +.ENDS sense_amp_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* OUTPUT: bl_64 +* OUTPUT: br_64 +* OUTPUT: bl_65 +* OUTPUT: br_65 +* OUTPUT: bl_66 +* OUTPUT: br_66 +* OUTPUT: bl_67 +* OUTPUT: br_67 +* OUTPUT: bl_68 +* OUTPUT: br_68 +* OUTPUT: bl_69 +* OUTPUT: br_69 +* OUTPUT: bl_70 +* OUTPUT: br_70 +* OUTPUT: bl_71 +* OUTPUT: br_71 +* OUTPUT: bl_72 +* OUTPUT: br_72 +* OUTPUT: bl_73 +* OUTPUT: br_73 +* OUTPUT: bl_74 +* OUTPUT: br_74 +* OUTPUT: bl_75 +* OUTPUT: br_75 +* OUTPUT: bl_76 +* OUTPUT: br_76 +* OUTPUT: bl_77 +* OUTPUT: br_77 +* OUTPUT: bl_78 +* OUTPUT: br_78 +* OUTPUT: bl_79 +* OUTPUT: br_79 +* OUTPUT: bl_80 +* OUTPUT: br_80 +* OUTPUT: bl_81 +* OUTPUT: br_81 +* OUTPUT: bl_82 +* OUTPUT: br_82 +* OUTPUT: bl_83 +* OUTPUT: br_83 +* OUTPUT: bl_84 +* OUTPUT: br_84 +* OUTPUT: bl_85 +* OUTPUT: br_85 +* OUTPUT: bl_86 +* OUTPUT: br_86 +* OUTPUT: bl_87 +* OUTPUT: br_87 +* OUTPUT: bl_88 +* OUTPUT: br_88 +* OUTPUT: bl_89 +* OUTPUT: br_89 +* OUTPUT: bl_90 +* OUTPUT: br_90 +* OUTPUT: bl_91 +* OUTPUT: br_91 +* OUTPUT: bl_92 +* OUTPUT: br_92 +* OUTPUT: bl_93 +* OUTPUT: br_93 +* OUTPUT: bl_94 +* OUTPUT: br_94 +* OUTPUT: bl_95 +* OUTPUT: br_95 +* OUTPUT: bl_96 +* OUTPUT: br_96 +* OUTPUT: bl_97 +* OUTPUT: br_97 +* OUTPUT: bl_98 +* OUTPUT: br_98 +* OUTPUT: bl_99 +* OUTPUT: br_99 +* OUTPUT: bl_100 +* OUTPUT: br_100 +* OUTPUT: bl_101 +* OUTPUT: br_101 +* OUTPUT: bl_102 +* OUTPUT: br_102 +* OUTPUT: bl_103 +* OUTPUT: br_103 +* OUTPUT: bl_104 +* OUTPUT: br_104 +* OUTPUT: bl_105 +* OUTPUT: br_105 +* OUTPUT: bl_106 +* OUTPUT: br_106 +* OUTPUT: bl_107 +* OUTPUT: br_107 +* OUTPUT: bl_108 +* OUTPUT: br_108 +* OUTPUT: bl_109 +* OUTPUT: br_109 +* OUTPUT: bl_110 +* OUTPUT: br_110 +* OUTPUT: bl_111 +* OUTPUT: br_111 +* OUTPUT: bl_112 +* OUTPUT: br_112 +* OUTPUT: bl_113 +* OUTPUT: br_113 +* OUTPUT: bl_114 +* OUTPUT: br_114 +* OUTPUT: bl_115 +* OUTPUT: br_115 +* OUTPUT: bl_116 +* OUTPUT: br_116 +* OUTPUT: bl_117 +* OUTPUT: br_117 +* OUTPUT: bl_118 +* OUTPUT: br_118 +* OUTPUT: bl_119 +* OUTPUT: br_119 +* OUTPUT: bl_120 +* OUTPUT: br_120 +* OUTPUT: bl_121 +* OUTPUT: br_121 +* OUTPUT: bl_122 +* OUTPUT: br_122 +* OUTPUT: bl_123 +* OUTPUT: br_123 +* OUTPUT: bl_124 +* OUTPUT: br_124 +* OUTPUT: bl_125 +* OUTPUT: br_125 +* OUTPUT: bl_126 +* OUTPUT: br_126 +* OUTPUT: bl_127 +* OUTPUT: br_127 +* OUTPUT: bl_128 +* OUTPUT: br_128 +* INPUT : en_bar +* POWER : vdd +* cols: 129 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 +Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 +Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 +Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 +Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 +Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 +Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 +Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 +Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 +Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 +Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 +Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 +Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 +Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 +Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 +Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 +Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 +Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 +Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 +Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 +Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 +Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 +Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 +Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 +Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 +Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 +Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 +Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 +Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 +Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 +Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 +Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 +Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 +Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 +Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 +Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 +Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 +Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 +Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 +Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 +Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 +Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 +Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 +Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 +Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 +Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 +Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 +Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 +Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 +Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 +Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 +Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 +Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 +Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 +Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 +Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 +Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 +Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 +Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 +Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 +Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 +Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 +Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 +Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 +Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 +Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 +Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 +Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 +Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 +Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 +Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 +Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 +Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 +Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 +Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 +Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 +Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 +Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 +Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 +Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 +Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 +Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 +Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 +Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 +Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 +Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 +Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 +Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 +Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 +Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 +Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 +Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 +Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 +Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 +Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 +Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 +Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 +Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 +Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 +Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 +Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 +Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 +Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 +Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 +Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 +Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 +Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 +Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 +Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 +Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 +Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 +Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 +Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 +Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 +Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 +Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 +Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 +Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 +Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 +Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 +Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 +Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 +Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 +Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 +Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 +Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd +*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* INPUT : data_2 +* INPUT : data_3 +* INPUT : data_4 +* INPUT : data_5 +* INPUT : data_6 +* INPUT : data_7 +* INPUT : data_8 +* INPUT : data_9 +* INPUT : data_10 +* INPUT : data_11 +* INPUT : data_12 +* INPUT : data_13 +* INPUT : data_14 +* INPUT : data_15 +* INPUT : data_16 +* INPUT : data_17 +* INPUT : data_18 +* INPUT : data_19 +* INPUT : data_20 +* INPUT : data_21 +* INPUT : data_22 +* INPUT : data_23 +* INPUT : data_24 +* INPUT : data_25 +* INPUT : data_26 +* INPUT : data_27 +* INPUT : data_28 +* INPUT : data_29 +* INPUT : data_30 +* INPUT : data_31 +* INPUT : data_32 +* INPUT : data_33 +* INPUT : data_34 +* INPUT : data_35 +* INPUT : data_36 +* INPUT : data_37 +* INPUT : data_38 +* INPUT : data_39 +* INPUT : data_40 +* INPUT : data_41 +* INPUT : data_42 +* INPUT : data_43 +* INPUT : data_44 +* INPUT : data_45 +* INPUT : data_46 +* INPUT : data_47 +* INPUT : data_48 +* INPUT : data_49 +* INPUT : data_50 +* INPUT : data_51 +* INPUT : data_52 +* INPUT : data_53 +* INPUT : data_54 +* INPUT : data_55 +* INPUT : data_56 +* INPUT : data_57 +* INPUT : data_58 +* INPUT : data_59 +* INPUT : data_60 +* INPUT : data_61 +* INPUT : data_62 +* INPUT : data_63 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 64 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver +Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver +Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver +Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver +Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver +Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver +Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver +Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver +Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver +Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver +Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver +Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver +Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver +Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver +Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver +Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver +Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver +Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver +Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver +Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver +Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver +Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver +Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver +Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver +Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver +Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver +Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver +Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver +Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver +Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver +Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver +Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver +Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver +Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver +Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver +Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver +Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver +Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver +Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver +Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver +Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver +Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver +Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver +Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver +Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver +Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver +Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver +Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver +Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver +Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver +Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver +Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver +Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver +Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver +Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver +Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver +Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver +Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver +Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver +Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver +Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver +Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver +Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver +.ENDS write_driver_array + +* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +.SUBCKT column_mux bl br bl_out br_out sel gnd +*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B +* INOUT : bl +* INOUT : br +* INOUT : bl_out +* INOUT : br_out +* INOUT : sel +* INOUT : gnd +Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u +Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u +.ENDS column_mux + +.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd +*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* INOUT : sel_0 +* INOUT : sel_1 +* INOUT : bl_out_0 +* INOUT : br_out_0 +* INOUT : bl_out_1 +* INOUT : br_out_1 +* INOUT : bl_out_2 +* INOUT : br_out_2 +* INOUT : bl_out_3 +* INOUT : br_out_3 +* INOUT : bl_out_4 +* INOUT : br_out_4 +* INOUT : bl_out_5 +* INOUT : br_out_5 +* INOUT : bl_out_6 +* INOUT : br_out_6 +* INOUT : bl_out_7 +* INOUT : br_out_7 +* INOUT : bl_out_8 +* INOUT : br_out_8 +* INOUT : bl_out_9 +* INOUT : br_out_9 +* INOUT : bl_out_10 +* INOUT : br_out_10 +* INOUT : bl_out_11 +* INOUT : br_out_11 +* INOUT : bl_out_12 +* INOUT : br_out_12 +* INOUT : bl_out_13 +* INOUT : br_out_13 +* INOUT : bl_out_14 +* INOUT : br_out_14 +* INOUT : bl_out_15 +* INOUT : br_out_15 +* INOUT : bl_out_16 +* INOUT : br_out_16 +* INOUT : bl_out_17 +* INOUT : br_out_17 +* INOUT : bl_out_18 +* INOUT : br_out_18 +* INOUT : bl_out_19 +* INOUT : br_out_19 +* INOUT : bl_out_20 +* INOUT : br_out_20 +* INOUT : bl_out_21 +* INOUT : br_out_21 +* INOUT : bl_out_22 +* INOUT : br_out_22 +* INOUT : bl_out_23 +* INOUT : br_out_23 +* INOUT : bl_out_24 +* INOUT : br_out_24 +* INOUT : bl_out_25 +* INOUT : br_out_25 +* INOUT : bl_out_26 +* INOUT : br_out_26 +* INOUT : bl_out_27 +* INOUT : br_out_27 +* INOUT : bl_out_28 +* INOUT : br_out_28 +* INOUT : bl_out_29 +* INOUT : br_out_29 +* INOUT : bl_out_30 +* INOUT : br_out_30 +* INOUT : bl_out_31 +* INOUT : br_out_31 +* INOUT : bl_out_32 +* INOUT : br_out_32 +* INOUT : bl_out_33 +* INOUT : br_out_33 +* INOUT : bl_out_34 +* INOUT : br_out_34 +* INOUT : bl_out_35 +* INOUT : br_out_35 +* INOUT : bl_out_36 +* INOUT : br_out_36 +* INOUT : bl_out_37 +* INOUT : br_out_37 +* INOUT : bl_out_38 +* INOUT : br_out_38 +* INOUT : bl_out_39 +* INOUT : br_out_39 +* INOUT : bl_out_40 +* INOUT : br_out_40 +* INOUT : bl_out_41 +* INOUT : br_out_41 +* INOUT : bl_out_42 +* INOUT : br_out_42 +* INOUT : bl_out_43 +* INOUT : br_out_43 +* INOUT : bl_out_44 +* INOUT : br_out_44 +* INOUT : bl_out_45 +* INOUT : br_out_45 +* INOUT : bl_out_46 +* INOUT : br_out_46 +* INOUT : bl_out_47 +* INOUT : br_out_47 +* INOUT : bl_out_48 +* INOUT : br_out_48 +* INOUT : bl_out_49 +* INOUT : br_out_49 +* INOUT : bl_out_50 +* INOUT : br_out_50 +* INOUT : bl_out_51 +* INOUT : br_out_51 +* INOUT : bl_out_52 +* INOUT : br_out_52 +* INOUT : bl_out_53 +* INOUT : br_out_53 +* INOUT : bl_out_54 +* INOUT : br_out_54 +* INOUT : bl_out_55 +* INOUT : br_out_55 +* INOUT : bl_out_56 +* INOUT : br_out_56 +* INOUT : bl_out_57 +* INOUT : br_out_57 +* INOUT : bl_out_58 +* INOUT : br_out_58 +* INOUT : bl_out_59 +* INOUT : br_out_59 +* INOUT : bl_out_60 +* INOUT : br_out_60 +* INOUT : bl_out_61 +* INOUT : br_out_61 +* INOUT : bl_out_62 +* INOUT : br_out_62 +* INOUT : bl_out_63 +* INOUT : br_out_63 +* INOUT : gnd +* cols: 128 word_size: 64 bl: bl br: br +XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux +XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux +XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux +XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux +XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux +XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux +XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux +XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux +XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux +XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux +XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux +XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux +XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux +XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux +XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux +XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux +XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux +XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux +XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux +XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux +XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux +XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux +XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux +XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux +XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux +XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux +XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux +XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux +XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux +XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux +XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux +XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux +XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux +XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux +XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux +XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux +XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux +XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux +XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux +XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux +XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux +XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux +XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux +XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux +XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux +XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux +XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux +XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux +XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux +XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux +XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux +XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux +XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux +XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux +XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux +XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux +XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux +XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux +XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux +XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux +XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux +XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux +XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux +XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux +XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux +XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux +XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux +XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux +XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux +XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux +XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux +XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux +XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux +XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux +XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux +XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux +XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux +XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux +XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux +XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux +XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux +XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux +XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux +XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux +XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux +XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux +XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux +XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux +XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux +XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux +XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux +XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux +XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux +XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux +XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux +XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux +XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux +XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux +XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux +XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux +XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux +XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux +XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux +XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux +XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux +XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux +XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux +XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux +XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux +XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux +XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux +XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux +XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux +XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux +XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux +XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux +XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux +XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux +XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux +XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux +XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux +XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux +XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux +XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux +XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux +XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux +XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux +XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux +.ENDS column_mux_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* INPUT : sel_0 +* INPUT : sel_1 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array +Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2 + +* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u +.ENDS pinv_0 + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 32 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv_0 +.ENDS and2_dec_0 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv_0 +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* INPUT : in_16 +* INPUT : in_17 +* INPUT : in_18 +* INPUT : in_19 +* INPUT : in_20 +* INPUT : in_21 +* INPUT : in_22 +* INPUT : in_23 +* INPUT : in_24 +* INPUT : in_25 +* INPUT : in_26 +* INPUT : in_27 +* INPUT : in_28 +* INPUT : in_29 +* INPUT : in_30 +* INPUT : in_31 +* INPUT : in_32 +* INPUT : in_33 +* INPUT : in_34 +* INPUT : in_35 +* INPUT : in_36 +* INPUT : in_37 +* INPUT : in_38 +* INPUT : in_39 +* INPUT : in_40 +* INPUT : in_41 +* INPUT : in_42 +* INPUT : in_43 +* INPUT : in_44 +* INPUT : in_45 +* INPUT : in_46 +* INPUT : in_47 +* INPUT : in_48 +* INPUT : in_49 +* INPUT : in_50 +* INPUT : in_51 +* INPUT : in_52 +* INPUT : in_53 +* INPUT : in_54 +* INPUT : in_55 +* INPUT : in_56 +* INPUT : in_57 +* INPUT : in_58 +* INPUT : in_59 +* INPUT : in_60 +* INPUT : in_61 +* INPUT : in_62 +* INPUT : in_63 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver +Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver +Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver +Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver +Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver +Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver +Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver +Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver +Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver +Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver +Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver +Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver +Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver +Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver +Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver +Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver +Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver +Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver +Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver +Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver +Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver +Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver +Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver +Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver +Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver +Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver +Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver +Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver +Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver +Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver +Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver +Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver +Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver +Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver +Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver +Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver +Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver +Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver +Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver +Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver +Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver +Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver +Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver +Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver +Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver +Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver +Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver +Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver +.ENDS wordline_driver_array + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand3 + +.SUBCKT and3_dec A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand3_dec_nand A B C zb_int vdd gnd pnand3 +Xpand3_dec_inv zb_int Z vdd gnd pinv +.ENDS and3_dec + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* OUTPUT: decode_16 +* OUTPUT: decode_17 +* OUTPUT: decode_18 +* OUTPUT: decode_19 +* OUTPUT: decode_20 +* OUTPUT: decode_21 +* OUTPUT: decode_22 +* OUTPUT: decode_23 +* OUTPUT: decode_24 +* OUTPUT: decode_25 +* OUTPUT: decode_26 +* OUTPUT: decode_27 +* OUTPUT: decode_28 +* OUTPUT: decode_29 +* OUTPUT: decode_30 +* OUTPUT: decode_31 +* OUTPUT: decode_32 +* OUTPUT: decode_33 +* OUTPUT: decode_34 +* OUTPUT: decode_35 +* OUTPUT: decode_36 +* OUTPUT: decode_37 +* OUTPUT: decode_38 +* OUTPUT: decode_39 +* OUTPUT: decode_40 +* OUTPUT: decode_41 +* OUTPUT: decode_42 +* OUTPUT: decode_43 +* OUTPUT: decode_44 +* OUTPUT: decode_45 +* OUTPUT: decode_46 +* OUTPUT: decode_47 +* OUTPUT: decode_48 +* OUTPUT: decode_49 +* OUTPUT: decode_50 +* OUTPUT: decode_51 +* OUTPUT: decode_52 +* OUTPUT: decode_53 +* OUTPUT: decode_54 +* OUTPUT: decode_55 +* OUTPUT: decode_56 +* OUTPUT: decode_57 +* OUTPUT: decode_58 +* OUTPUT: decode_59 +* OUTPUT: decode_60 +* OUTPUT: decode_61 +* OUTPUT: decode_62 +* OUTPUT: decode_63 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 +Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 +XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec +XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec +XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec +XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec +XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec +XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec +XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec +XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec +XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec +XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec +XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec +XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec +XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec +XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec +XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec +XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec +XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec +XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec +XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec +XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec +XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec +XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec +XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec +XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec +XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec +XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec +XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec +XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec +XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec +XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec +XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec +XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec +XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec +XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec +XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec +XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec +XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec +XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec +XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec +XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec +XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec +XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec +XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec +XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec +XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec +XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec +XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec +XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec +XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec +XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec +XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec +XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec +XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec +XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec +XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec +XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec +XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec +XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec +XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec +XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec +XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec +XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec +XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec +XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec +.ENDS hierarchical_decoder + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: dout0_2 +* OUTPUT: dout0_3 +* OUTPUT: dout0_4 +* OUTPUT: dout0_5 +* OUTPUT: dout0_6 +* OUTPUT: dout0_7 +* OUTPUT: dout0_8 +* OUTPUT: dout0_9 +* OUTPUT: dout0_10 +* OUTPUT: dout0_11 +* OUTPUT: dout0_12 +* OUTPUT: dout0_13 +* OUTPUT: dout0_14 +* OUTPUT: dout0_15 +* OUTPUT: dout0_16 +* OUTPUT: dout0_17 +* OUTPUT: dout0_18 +* OUTPUT: dout0_19 +* OUTPUT: dout0_20 +* OUTPUT: dout0_21 +* OUTPUT: dout0_22 +* OUTPUT: dout0_23 +* OUTPUT: dout0_24 +* OUTPUT: dout0_25 +* OUTPUT: dout0_26 +* OUTPUT: dout0_27 +* OUTPUT: dout0_28 +* OUTPUT: dout0_29 +* OUTPUT: dout0_30 +* OUTPUT: dout0_31 +* OUTPUT: dout0_32 +* OUTPUT: dout0_33 +* OUTPUT: dout0_34 +* OUTPUT: dout0_35 +* OUTPUT: dout0_36 +* OUTPUT: dout0_37 +* OUTPUT: dout0_38 +* OUTPUT: dout0_39 +* OUTPUT: dout0_40 +* OUTPUT: dout0_41 +* OUTPUT: dout0_42 +* OUTPUT: dout0_43 +* OUTPUT: dout0_44 +* OUTPUT: dout0_45 +* OUTPUT: dout0_46 +* OUTPUT: dout0_47 +* OUTPUT: dout0_48 +* OUTPUT: dout0_49 +* OUTPUT: dout0_50 +* OUTPUT: dout0_51 +* OUTPUT: dout0_52 +* OUTPUT: dout0_53 +* OUTPUT: dout0_54 +* OUTPUT: dout0_55 +* OUTPUT: dout0_56 +* OUTPUT: dout0_57 +* OUTPUT: dout0_58 +* OUTPUT: dout0_59 +* OUTPUT: dout0_60 +* OUTPUT: dout0_61 +* OUTPUT: dout0_62 +* OUTPUT: dout0_63 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : din0_2 +* INPUT : din0_3 +* INPUT : din0_4 +* INPUT : din0_5 +* INPUT : din0_6 +* INPUT : din0_7 +* INPUT : din0_8 +* INPUT : din0_9 +* INPUT : din0_10 +* INPUT : din0_11 +* INPUT : din0_12 +* INPUT : din0_13 +* INPUT : din0_14 +* INPUT : din0_15 +* INPUT : din0_16 +* INPUT : din0_17 +* INPUT : din0_18 +* INPUT : din0_19 +* INPUT : din0_20 +* INPUT : din0_21 +* INPUT : din0_22 +* INPUT : din0_23 +* INPUT : din0_24 +* INPUT : din0_25 +* INPUT : din0_26 +* INPUT : din0_27 +* INPUT : din0_28 +* INPUT : din0_29 +* INPUT : din0_30 +* INPUT : din0_31 +* INPUT : din0_32 +* INPUT : din0_33 +* INPUT : din0_34 +* INPUT : din0_35 +* INPUT : din0_36 +* INPUT : din0_37 +* INPUT : din0_38 +* INPUT : din0_39 +* INPUT : din0_40 +* INPUT : din0_41 +* INPUT : din0_42 +* INPUT : din0_43 +* INPUT : din0_44 +* INPUT : din0_45 +* INPUT : din0_46 +* INPUT : din0_47 +* INPUT : din0_48 +* INPUT : din0_49 +* INPUT : din0_50 +* INPUT : din0_51 +* INPUT : din0_52 +* INPUT : din0_53 +* INPUT : din0_54 +* INPUT : din0_55 +* INPUT : din0_56 +* INPUT : din0_57 +* INPUT : din0_58 +* INPUT : din0_59 +* INPUT : din0_60 +* INPUT : din0_61 +* INPUT : din0_62 +* INPUT : din0_63 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : addr0_4 +* INPUT : addr0_5 +* INPUT : addr0_6 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address +Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf +.ENDS bank + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_2 +Xdff_buf_inv2 Qb Q vdd gnd pinv_3 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2_0 + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +.SUBCKT pinv_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u +.ENDS pinv_4 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_4 +.ENDS pdriver + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u +.ENDS pinv_11 + +* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u +.ENDS pinv_9 + +* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u +.ENDS pinv_10 + +* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p + +* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p + +.SUBCKT pinv_12 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u +.ENDS pinv_12 + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_7 + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pinv_8 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 1, 2, 5, 14, 42, 125] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 +Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 +Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 +Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 +.ENDS pdriver_0 + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand3_0 + +* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p + +* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +.SUBCKT pinv_16 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u +.ENDS pinv_16 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [64] +Xbuf_inv1 A Z vdd gnd pinv_16 +.ENDS pdriver_3 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +.SUBCKT pinv_17 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_17 + +* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p + +* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p + +.SUBCKT pinv_18 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u +.ENDS pinv_18 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 2, 5, 14, 43] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 +Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 +.ENDS pdriver_4 + +* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p + +* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p + +.SUBCKT pinv_15 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u +.ENDS pinv_15 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [72] +Xbuf_inv1 A Z vdd gnd pinv_15 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT pinv_19 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_19 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_19 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 +Xdinv1 dout_1 dout_2 vdd gnd pinv_19 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 +Xdinv2 dout_2 dout_3 vdd gnd pinv_19 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 +Xdinv3 dout_3 dout_4 vdd gnd pinv_19 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 +Xdinv4 dout_4 dout_5 vdd gnd pinv_19 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 +Xdinv5 dout_5 dout_6 vdd gnd pinv_19 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 +Xdinv6 dout_6 dout_7 vdd gnd pinv_19 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 +Xdinv7 dout_7 dout_8 vdd gnd pinv_19 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 +Xdinv8 dout_8 out vdd gnd pinv_19 +Xdload_8_0 out n_8_0 vdd gnd pinv_19 +Xdload_8_1 out n_8_1 vdd gnd pinv_19 +Xdload_8_2 out n_8_2 vdd gnd pinv_19 +Xdload_8_3 out n_8_3 vdd gnd pinv_19 +.ENDS delay_chain + +* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p + +.SUBCKT pinv_14 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u +.ENDS pinv_14 + +* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p + +.SUBCKT pinv_13 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u +.ENDS pinv_13 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [7, 21] +Xbuf_inv1 A Zb1_int vdd gnd pinv_13 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 +.ENDS pdriver_1 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2_1 + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 64 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 +Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_17 +Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 +Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 +Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain +Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 +Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd +*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : din0[2] +* INPUT : din0[3] +* INPUT : din0[4] +* INPUT : din0[5] +* INPUT : din0[6] +* INPUT : din0[7] +* INPUT : din0[8] +* INPUT : din0[9] +* INPUT : din0[10] +* INPUT : din0[11] +* INPUT : din0[12] +* INPUT : din0[13] +* INPUT : din0[14] +* INPUT : din0[15] +* INPUT : din0[16] +* INPUT : din0[17] +* INPUT : din0[18] +* INPUT : din0[19] +* INPUT : din0[20] +* INPUT : din0[21] +* INPUT : din0[22] +* INPUT : din0[23] +* INPUT : din0[24] +* INPUT : din0[25] +* INPUT : din0[26] +* INPUT : din0[27] +* INPUT : din0[28] +* INPUT : din0[29] +* INPUT : din0[30] +* INPUT : din0[31] +* INPUT : din0[32] +* INPUT : din0[33] +* INPUT : din0[34] +* INPUT : din0[35] +* INPUT : din0[36] +* INPUT : din0[37] +* INPUT : din0[38] +* INPUT : din0[39] +* INPUT : din0[40] +* INPUT : din0[41] +* INPUT : din0[42] +* INPUT : din0[43] +* INPUT : din0[44] +* INPUT : din0[45] +* INPUT : din0[46] +* INPUT : din0[47] +* INPUT : din0[48] +* INPUT : din0[49] +* INPUT : din0[50] +* INPUT : din0[51] +* INPUT : din0[52] +* INPUT : din0[53] +* INPUT : din0[54] +* INPUT : din0[55] +* INPUT : din0[56] +* INPUT : din0[57] +* INPUT : din0[58] +* INPUT : din0[59] +* INPUT : din0[60] +* INPUT : din0[61] +* INPUT : din0[62] +* INPUT : din0[63] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : addr0[4] +* INPUT : addr0[5] +* INPUT : addr0[6] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* OUTPUT: dout0[2] +* OUTPUT: dout0[3] +* OUTPUT: dout0[4] +* OUTPUT: dout0[5] +* OUTPUT: dout0[6] +* OUTPUT: dout0[7] +* OUTPUT: dout0[8] +* OUTPUT: dout0[9] +* OUTPUT: dout0[10] +* OUTPUT: dout0[11] +* OUTPUT: dout0[12] +* OUTPUT: dout0[13] +* OUTPUT: dout0[14] +* OUTPUT: dout0[15] +* OUTPUT: dout0[16] +* OUTPUT: dout0[17] +* OUTPUT: dout0[18] +* OUTPUT: dout0[19] +* OUTPUT: dout0[20] +* OUTPUT: dout0[21] +* OUTPUT: dout0[22] +* OUTPUT: dout0[23] +* OUTPUT: dout0[24] +* OUTPUT: dout0[25] +* OUTPUT: dout0[26] +* OUTPUT: dout0[27] +* OUTPUT: dout0[28] +* OUTPUT: dout0[29] +* OUTPUT: dout0[30] +* OUTPUT: dout0[31] +* OUTPUT: dout0[32] +* OUTPUT: dout0[33] +* OUTPUT: dout0[34] +* OUTPUT: dout0[35] +* OUTPUT: dout0[36] +* OUTPUT: dout0[37] +* OUTPUT: dout0[38] +* OUTPUT: dout0[39] +* OUTPUT: dout0[40] +* OUTPUT: dout0[41] +* OUTPUT: dout0[42] +* OUTPUT: dout0[43] +* OUTPUT: dout0[44] +* OUTPUT: dout0[45] +* OUTPUT: dout0[46] +* OUTPUT: dout0[47] +* OUTPUT: dout0[48] +* OUTPUT: dout0[49] +* OUTPUT: dout0[50] +* OUTPUT: dout0[51] +* OUTPUT: dout0[52] +* OUTPUT: dout0[53] +* OUTPUT: dout0[54] +* OUTPUT: dout0[55] +* OUTPUT: dout0[56] +* OUTPUT: dout0[57] +* OUTPUT: dout0[58] +* OUTPUT: dout0[59] +* OUTPUT: dout0[60] +* OUTPUT: dout0[61] +* OUTPUT: dout0[62] +* OUTPUT: dout0[63] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff +Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff +Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff +.ENDS sram_64_128_scn4m_subm diff --git a/1KB/sram_64_128_scn4m_subm.sp b/1KB/sram_64_128_scn4m_subm.sp new file mode 100644 index 00000000..abee3faf --- /dev/null +++ b/1KB/sram_64_128_scn4m_subm.sp @@ -0,0 +1,14050 @@ +************************************************** +* OpenRAM generated memory. +* Words: 128 +* Data bits: 64 +* Banks: 1 +* Column mux: 2:1 +* Trimmed: False +* LVS: False +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 6 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff +Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff +.ENDS row_addr_dff + +.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd +*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B +* INPUT : din_0 +* OUTPUT: dout_0 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +.ENDS col_addr_dff + +.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 64 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff +Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff +Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff +Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff +Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff +Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff +Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff +Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff +Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff +Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff +Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff +Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff +Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff +Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff +Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff +Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff +Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff +Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff +Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff +Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff +Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff +Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff +Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff +Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff +Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff +Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff +Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff +Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff +Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff +Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff +Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff +Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff +Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff +Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff +Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff +Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff +Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff +Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff +Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff +Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff +Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff +Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff +Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff +Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff +Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff +Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff +Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff +Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff +Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff +Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff +Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff +Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff +Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff +Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff +Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff +Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff +Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff +Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff +Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff +Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff +Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff +Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff +.ENDS data_dff + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_2 + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_3 + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_1 + +.SUBCKT pinvbuf A Zb Z vdd gnd +*.PININFO A:B Zb:B Z:B vdd:B gnd:B +* INOUT : A +* INOUT : Zb +* INOUT : Z +* INOUT : vdd +* INOUT : gnd +Xbuf_inv1 A zb_int vdd gnd pinv_1 +Xbuf_inv2 zb_int z_int vdd gnd pinv_2 +Xbuf_inv3 z_int Zb vdd gnd pinv_3 +Xbuf_inv4 zb_int Z vdd gnd pinv_3 +.ENDS pinvbuf + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw +Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw +Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw +Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw +Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw +Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw +Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw +Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw +Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw +Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw +Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw +Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw +Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw +Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw +Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw +Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw +Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw +Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw +Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw +Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw +Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw +Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw +Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw +Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw +Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw +Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw +Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw +Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw +Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw +Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw +Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw +Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw +Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw +Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw +Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw +Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw +Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw +Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw +Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw +Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw +Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw +Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw +Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw +Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw +Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw +Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw +Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw +Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw +Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c15 bl_0_15 br_0_15 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c15 bl_0_15 br_0_15 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c15 bl_0_15 br_0_15 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c15 bl_0_15 br_0_15 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c15 bl_0_15 br_0_15 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c15 bl_0_15 br_0_15 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c15 bl_0_15 br_0_15 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c15 bl_0_15 br_0_15 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c15 bl_0_15 br_0_15 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c15 bl_0_15 br_0_15 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c15 bl_0_15 br_0_15 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c15 bl_0_15 br_0_15 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c15 bl_0_15 br_0_15 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c44 bl_0_44 br_0_44 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c44 bl_0_44 br_0_44 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c44 bl_0_44 br_0_44 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c44 bl_0_44 br_0_44 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c44 bl_0_44 br_0_44 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c44 bl_0_44 br_0_44 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c44 bl_0_44 br_0_44 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c44 bl_0_44 br_0_44 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c44 bl_0_44 br_0_44 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c44 bl_0_44 br_0_44 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c44 bl_0_44 br_0_44 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c44 bl_0_44 br_0_44 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c44 bl_0_44 br_0_44 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c44 bl_0_44 br_0_44 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c44 bl_0_44 br_0_44 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c44 bl_0_44 br_0_44 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c44 bl_0_44 br_0_44 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c44 bl_0_44 br_0_44 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c49 bl_0_49 br_0_49 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c49 bl_0_49 br_0_49 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c49 bl_0_49 br_0_49 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c49 bl_0_49 br_0_49 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c49 bl_0_49 br_0_49 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c49 bl_0_49 br_0_49 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c49 bl_0_49 br_0_49 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c49 bl_0_49 br_0_49 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c49 bl_0_49 br_0_49 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c49 bl_0_49 br_0_49 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c49 bl_0_49 br_0_49 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c49 bl_0_49 br_0_49 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c49 bl_0_49 br_0_49 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c49 bl_0_49 br_0_49 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c49 bl_0_49 br_0_49 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c49 bl_0_49 br_0_49 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c49 bl_0_49 br_0_49 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c49 bl_0_49 br_0_49 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c52 bl_0_52 br_0_52 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c52 bl_0_52 br_0_52 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c52 bl_0_52 br_0_52 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c52 bl_0_52 br_0_52 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c52 bl_0_52 br_0_52 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c52 bl_0_52 br_0_52 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c52 bl_0_52 br_0_52 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c52 bl_0_52 br_0_52 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c52 bl_0_52 br_0_52 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c52 bl_0_52 br_0_52 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c52 bl_0_52 br_0_52 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c53 bl_0_53 br_0_53 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c53 bl_0_53 br_0_53 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c53 bl_0_53 br_0_53 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c53 bl_0_53 br_0_53 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c53 bl_0_53 br_0_53 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c53 bl_0_53 br_0_53 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c53 bl_0_53 br_0_53 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw 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+Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c59 bl_0_59 br_0_59 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c59 bl_0_59 br_0_59 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c59 bl_0_59 br_0_59 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c60 bl_0_60 br_0_60 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c60 bl_0_60 br_0_60 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c60 bl_0_60 br_0_60 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c60 bl_0_60 br_0_60 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c60 bl_0_60 br_0_60 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c60 bl_0_60 br_0_60 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c60 bl_0_60 br_0_60 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c60 bl_0_60 br_0_60 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c60 bl_0_60 br_0_60 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c60 bl_0_60 br_0_60 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c60 bl_0_60 br_0_60 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c60 bl_0_60 br_0_60 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c60 bl_0_60 br_0_60 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c60 bl_0_60 br_0_60 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c60 bl_0_60 br_0_60 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c73 bl_0_73 br_0_73 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c73 bl_0_73 br_0_73 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c73 bl_0_73 br_0_73 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c73 bl_0_73 br_0_73 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c73 bl_0_73 br_0_73 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c73 bl_0_73 br_0_73 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c73 bl_0_73 br_0_73 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c73 bl_0_73 br_0_73 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c73 bl_0_73 br_0_73 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c73 bl_0_73 br_0_73 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c73 bl_0_73 br_0_73 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c73 bl_0_73 br_0_73 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c73 bl_0_73 br_0_73 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c73 bl_0_73 br_0_73 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c73 bl_0_73 br_0_73 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c73 bl_0_73 br_0_73 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c73 bl_0_73 br_0_73 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c73 bl_0_73 br_0_73 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c74 bl_0_74 br_0_74 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c74 bl_0_74 br_0_74 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c74 bl_0_74 br_0_74 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c74 bl_0_74 br_0_74 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c74 bl_0_74 br_0_74 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c74 bl_0_74 br_0_74 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c74 bl_0_74 br_0_74 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c74 bl_0_74 br_0_74 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c74 bl_0_74 br_0_74 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c74 bl_0_74 br_0_74 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c74 bl_0_74 br_0_74 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c74 bl_0_74 br_0_74 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c74 bl_0_74 br_0_74 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c74 bl_0_74 br_0_74 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c74 bl_0_74 br_0_74 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c74 bl_0_74 br_0_74 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c74 bl_0_74 br_0_74 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c74 bl_0_74 br_0_74 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c74 bl_0_74 br_0_74 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c74 bl_0_74 br_0_74 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c74 bl_0_74 br_0_74 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c74 bl_0_74 br_0_74 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c74 bl_0_74 br_0_74 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c74 bl_0_74 br_0_74 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c74 bl_0_74 br_0_74 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c74 bl_0_74 br_0_74 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c74 bl_0_74 br_0_74 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c74 bl_0_74 br_0_74 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c74 bl_0_74 br_0_74 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c74 bl_0_74 br_0_74 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c74 bl_0_74 br_0_74 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c74 bl_0_74 br_0_74 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c74 bl_0_74 br_0_74 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c75 bl_0_75 br_0_75 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c75 bl_0_75 br_0_75 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c75 bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c75 bl_0_75 br_0_75 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c75 bl_0_75 br_0_75 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c75 bl_0_75 br_0_75 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c75 bl_0_75 br_0_75 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c75 bl_0_75 br_0_75 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c75 bl_0_75 br_0_75 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c76 bl_0_76 br_0_76 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c76 bl_0_76 br_0_76 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c76 bl_0_76 br_0_76 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c76 bl_0_76 br_0_76 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c76 bl_0_76 br_0_76 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c76 bl_0_76 br_0_76 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c76 bl_0_76 br_0_76 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c76 bl_0_76 br_0_76 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c76 bl_0_76 br_0_76 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c76 bl_0_76 br_0_76 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c76 bl_0_76 br_0_76 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c76 bl_0_76 br_0_76 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c81 bl_0_81 br_0_81 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c81 bl_0_81 br_0_81 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c81 bl_0_81 br_0_81 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c81 bl_0_81 br_0_81 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c81 bl_0_81 br_0_81 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c81 bl_0_81 br_0_81 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c81 bl_0_81 br_0_81 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c82 bl_0_82 br_0_82 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c82 bl_0_82 br_0_82 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c82 bl_0_82 br_0_82 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c82 bl_0_82 br_0_82 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c82 bl_0_82 br_0_82 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c82 bl_0_82 br_0_82 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c82 bl_0_82 br_0_82 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c82 bl_0_82 br_0_82 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c82 bl_0_82 br_0_82 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c82 bl_0_82 br_0_82 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c82 bl_0_82 br_0_82 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c83 bl_0_83 br_0_83 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c83 bl_0_83 br_0_83 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c84 bl_0_84 br_0_84 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c84 bl_0_84 br_0_84 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c84 bl_0_84 br_0_84 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c84 bl_0_84 br_0_84 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c84 bl_0_84 br_0_84 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c84 bl_0_84 br_0_84 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c84 bl_0_84 br_0_84 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c84 bl_0_84 br_0_84 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c84 bl_0_84 br_0_84 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c84 bl_0_84 br_0_84 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c84 bl_0_84 br_0_84 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c84 bl_0_84 br_0_84 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c84 bl_0_84 br_0_84 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c84 bl_0_84 br_0_84 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c84 bl_0_84 br_0_84 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c84 bl_0_84 br_0_84 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c87 bl_0_87 br_0_87 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c87 bl_0_87 br_0_87 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c87 bl_0_87 br_0_87 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c87 bl_0_87 br_0_87 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c87 bl_0_87 br_0_87 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c87 bl_0_87 br_0_87 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c87 bl_0_87 br_0_87 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c87 bl_0_87 br_0_87 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c88 bl_0_88 br_0_88 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c88 bl_0_88 br_0_88 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c88 bl_0_88 br_0_88 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c88 bl_0_88 br_0_88 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c88 bl_0_88 br_0_88 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c88 bl_0_88 br_0_88 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c88 bl_0_88 br_0_88 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c88 bl_0_88 br_0_88 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c88 bl_0_88 br_0_88 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c88 bl_0_88 br_0_88 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c89 bl_0_89 br_0_89 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c89 bl_0_89 br_0_89 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c89 bl_0_89 br_0_89 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c90 bl_0_90 br_0_90 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c90 bl_0_90 br_0_90 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c90 bl_0_90 br_0_90 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c90 bl_0_90 br_0_90 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c90 bl_0_90 br_0_90 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c90 bl_0_90 br_0_90 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c90 bl_0_90 br_0_90 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c90 bl_0_90 br_0_90 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c90 bl_0_90 br_0_90 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c90 bl_0_90 br_0_90 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c90 bl_0_90 br_0_90 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c90 bl_0_90 br_0_90 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c90 bl_0_90 br_0_90 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c90 bl_0_90 br_0_90 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c90 bl_0_90 br_0_90 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c96 bl_0_96 br_0_96 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c96 bl_0_96 br_0_96 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c96 bl_0_96 br_0_96 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c96 bl_0_96 br_0_96 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c96 bl_0_96 br_0_96 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c96 bl_0_96 br_0_96 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c96 bl_0_96 br_0_96 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c96 bl_0_96 br_0_96 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c96 bl_0_96 br_0_96 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c96 bl_0_96 br_0_96 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c96 bl_0_96 br_0_96 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c96 bl_0_96 br_0_96 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c96 bl_0_96 br_0_96 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c96 bl_0_96 br_0_96 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c96 bl_0_96 br_0_96 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c96 bl_0_96 br_0_96 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c96 bl_0_96 br_0_96 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c96 bl_0_96 br_0_96 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c96 bl_0_96 br_0_96 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c97 bl_0_97 br_0_97 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c97 bl_0_97 br_0_97 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c97 bl_0_97 br_0_97 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c97 bl_0_97 br_0_97 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c97 bl_0_97 br_0_97 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c97 bl_0_97 br_0_97 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c97 bl_0_97 br_0_97 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c97 bl_0_97 br_0_97 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c97 bl_0_97 br_0_97 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c97 bl_0_97 br_0_97 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c97 bl_0_97 br_0_97 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c97 bl_0_97 br_0_97 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c97 bl_0_97 br_0_97 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c97 bl_0_97 br_0_97 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c97 bl_0_97 br_0_97 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c97 bl_0_97 br_0_97 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c97 bl_0_97 br_0_97 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c98 bl_0_98 br_0_98 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c98 bl_0_98 br_0_98 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c98 bl_0_98 br_0_98 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c98 bl_0_98 br_0_98 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c98 bl_0_98 br_0_98 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c98 bl_0_98 br_0_98 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c98 bl_0_98 br_0_98 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c98 bl_0_98 br_0_98 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c98 bl_0_98 br_0_98 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c98 bl_0_98 br_0_98 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c98 bl_0_98 br_0_98 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c98 bl_0_98 br_0_98 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c98 bl_0_98 br_0_98 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c98 bl_0_98 br_0_98 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c99 bl_0_99 br_0_99 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c99 bl_0_99 br_0_99 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c99 bl_0_99 br_0_99 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c99 bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c100 bl_0_100 br_0_100 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c100 bl_0_100 br_0_100 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c100 bl_0_100 br_0_100 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c100 bl_0_100 br_0_100 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c100 bl_0_100 br_0_100 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c100 bl_0_100 br_0_100 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c100 bl_0_100 br_0_100 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c100 bl_0_100 br_0_100 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c100 bl_0_100 br_0_100 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c100 bl_0_100 br_0_100 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c100 bl_0_100 br_0_100 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c100 bl_0_100 br_0_100 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c100 bl_0_100 br_0_100 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c100 bl_0_100 br_0_100 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c100 bl_0_100 br_0_100 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c100 bl_0_100 br_0_100 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c100 bl_0_100 br_0_100 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c108 bl_0_108 br_0_108 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c108 bl_0_108 br_0_108 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c108 bl_0_108 br_0_108 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c108 bl_0_108 br_0_108 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c108 bl_0_108 br_0_108 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c108 bl_0_108 br_0_108 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c108 bl_0_108 br_0_108 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c108 bl_0_108 br_0_108 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c108 bl_0_108 br_0_108 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c108 bl_0_108 br_0_108 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c108 bl_0_108 br_0_108 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c108 bl_0_108 br_0_108 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c108 bl_0_108 br_0_108 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c108 bl_0_108 br_0_108 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c108 bl_0_108 br_0_108 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c108 bl_0_108 br_0_108 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c108 bl_0_108 br_0_108 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c108 bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c110 bl_0_110 br_0_110 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c110 bl_0_110 br_0_110 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c110 bl_0_110 br_0_110 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c110 bl_0_110 br_0_110 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c110 bl_0_110 br_0_110 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c110 bl_0_110 br_0_110 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c110 bl_0_110 br_0_110 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c110 bl_0_110 br_0_110 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c110 bl_0_110 br_0_110 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c110 bl_0_110 br_0_110 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c110 bl_0_110 br_0_110 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c110 bl_0_110 br_0_110 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c110 bl_0_110 br_0_110 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c110 bl_0_110 br_0_110 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c110 bl_0_110 br_0_110 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c110 bl_0_110 br_0_110 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c110 bl_0_110 br_0_110 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c110 bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c111 bl_0_111 br_0_111 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c111 bl_0_111 br_0_111 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c111 bl_0_111 br_0_111 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c111 bl_0_111 br_0_111 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c111 bl_0_111 br_0_111 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c111 bl_0_111 br_0_111 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c111 bl_0_111 br_0_111 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c111 bl_0_111 br_0_111 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c111 bl_0_111 br_0_111 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c111 bl_0_111 br_0_111 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c111 bl_0_111 br_0_111 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c111 bl_0_111 br_0_111 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c111 bl_0_111 br_0_111 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c111 bl_0_111 br_0_111 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c111 bl_0_111 br_0_111 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c111 bl_0_111 br_0_111 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c111 bl_0_111 br_0_111 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c111 bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c112 bl_0_112 br_0_112 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c112 bl_0_112 br_0_112 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c112 bl_0_112 br_0_112 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c112 bl_0_112 br_0_112 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c112 bl_0_112 br_0_112 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c112 bl_0_112 br_0_112 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c112 bl_0_112 br_0_112 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c112 bl_0_112 br_0_112 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c112 bl_0_112 br_0_112 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c112 bl_0_112 br_0_112 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c112 bl_0_112 br_0_112 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c112 bl_0_112 br_0_112 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c112 bl_0_112 br_0_112 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c112 bl_0_112 br_0_112 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c112 bl_0_112 br_0_112 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c112 bl_0_112 br_0_112 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c112 bl_0_112 br_0_112 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c112 bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c114 bl_0_114 br_0_114 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c114 bl_0_114 br_0_114 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c114 bl_0_114 br_0_114 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c114 bl_0_114 br_0_114 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c114 bl_0_114 br_0_114 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c114 bl_0_114 br_0_114 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c114 bl_0_114 br_0_114 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c114 bl_0_114 br_0_114 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c114 bl_0_114 br_0_114 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c114 bl_0_114 br_0_114 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c114 bl_0_114 br_0_114 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c114 bl_0_114 br_0_114 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c114 bl_0_114 br_0_114 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c114 bl_0_114 br_0_114 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c114 bl_0_114 br_0_114 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c115 bl_0_115 br_0_115 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c115 bl_0_115 br_0_115 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c116 bl_0_116 br_0_116 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c116 bl_0_116 br_0_116 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c116 bl_0_116 br_0_116 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c116 bl_0_116 br_0_116 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c116 bl_0_116 br_0_116 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c116 bl_0_116 br_0_116 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c116 bl_0_116 br_0_116 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c116 bl_0_116 br_0_116 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c116 bl_0_116 br_0_116 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c116 bl_0_116 br_0_116 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c116 bl_0_116 br_0_116 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c116 bl_0_116 br_0_116 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c116 bl_0_116 br_0_116 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c116 bl_0_116 br_0_116 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c116 bl_0_116 br_0_116 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c116 bl_0_116 br_0_116 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c116 bl_0_116 br_0_116 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c116 bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd 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bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c120 bl_0_120 br_0_120 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c120 bl_0_120 br_0_120 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c120 bl_0_120 br_0_120 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c120 bl_0_120 br_0_120 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c120 bl_0_120 br_0_120 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c120 bl_0_120 br_0_120 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c120 bl_0_120 br_0_120 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c120 bl_0_120 br_0_120 wl_0_13 vdd gnd cell_1rw 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bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c121 bl_0_121 br_0_121 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c121 bl_0_121 br_0_121 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c121 bl_0_121 br_0_121 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c121 bl_0_121 br_0_121 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c121 bl_0_121 br_0_121 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c121 bl_0_121 br_0_121 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c121 bl_0_121 br_0_121 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c121 bl_0_121 br_0_121 wl_0_18 vdd gnd cell_1rw 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bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c122 bl_0_122 br_0_122 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c122 bl_0_122 br_0_122 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c122 bl_0_122 br_0_122 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c122 bl_0_122 br_0_122 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c122 bl_0_122 br_0_122 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c122 bl_0_122 br_0_122 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c122 bl_0_122 br_0_122 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c122 bl_0_122 br_0_122 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c122 bl_0_122 br_0_122 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c122 bl_0_122 br_0_122 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c122 bl_0_122 br_0_122 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c122 bl_0_122 br_0_122 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c122 bl_0_122 br_0_122 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c122 bl_0_122 br_0_122 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c122 bl_0_122 br_0_122 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c122 bl_0_122 br_0_122 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c122 bl_0_122 br_0_122 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c122 bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c123 bl_0_123 br_0_123 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c123 bl_0_123 br_0_123 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c123 bl_0_123 br_0_123 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c123 bl_0_123 br_0_123 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c123 bl_0_123 br_0_123 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c123 bl_0_123 br_0_123 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c123 bl_0_123 br_0_123 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c123 bl_0_123 br_0_123 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c123 bl_0_123 br_0_123 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c123 bl_0_123 br_0_123 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c123 bl_0_123 br_0_123 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c123 bl_0_123 br_0_123 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c123 bl_0_123 br_0_123 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c123 bl_0_123 br_0_123 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c123 bl_0_123 br_0_123 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c123 bl_0_123 br_0_123 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c123 bl_0_123 br_0_123 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c123 bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c126 bl_0_126 br_0_126 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c126 bl_0_126 br_0_126 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c126 bl_0_126 br_0_126 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c126 bl_0_126 br_0_126 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c126 bl_0_126 br_0_126 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c126 bl_0_126 br_0_126 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c126 bl_0_126 br_0_126 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c126 bl_0_126 br_0_126 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c126 bl_0_126 br_0_126 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c126 bl_0_126 br_0_126 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c126 bl_0_126 br_0_126 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c126 bl_0_126 br_0_126 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c126 bl_0_126 br_0_126 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c126 bl_0_126 br_0_126 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c126 bl_0_126 br_0_126 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c126 bl_0_126 br_0_126 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c126 bl_0_126 br_0_126 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c126 bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c127 bl_0_127 br_0_127 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c127 bl_0_127 br_0_127 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c127 bl_0_127 br_0_127 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c127 bl_0_127 br_0_127 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c127 bl_0_127 br_0_127 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c127 bl_0_127 br_0_127 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c127 bl_0_127 br_0_127 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c127 bl_0_127 br_0_127 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c127 bl_0_127 br_0_127 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c127 bl_0_127 br_0_127 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c127 bl_0_127 br_0_127 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c127 bl_0_127 br_0_127 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c127 bl_0_127 br_0_127 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c127 bl_0_127 br_0_127 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c127 bl_0_127 br_0_127 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c127 bl_0_127 br_0_127 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c127 bl_0_127 br_0_127 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c127 bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw +.ENDS bitcell_array + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* OUTPUT: data_2 +* INPUT : bl_2 +* INPUT : br_2 +* OUTPUT: data_3 +* INPUT : bl_3 +* INPUT : br_3 +* OUTPUT: data_4 +* INPUT : bl_4 +* INPUT : br_4 +* OUTPUT: data_5 +* INPUT : bl_5 +* INPUT : br_5 +* OUTPUT: data_6 +* INPUT : bl_6 +* INPUT : br_6 +* OUTPUT: data_7 +* INPUT : bl_7 +* INPUT : br_7 +* OUTPUT: data_8 +* INPUT : bl_8 +* INPUT : br_8 +* OUTPUT: data_9 +* INPUT : bl_9 +* INPUT : br_9 +* OUTPUT: data_10 +* INPUT : bl_10 +* INPUT : br_10 +* OUTPUT: data_11 +* INPUT : bl_11 +* INPUT : br_11 +* OUTPUT: data_12 +* INPUT : bl_12 +* INPUT : br_12 +* OUTPUT: data_13 +* INPUT : bl_13 +* INPUT : br_13 +* OUTPUT: data_14 +* INPUT : bl_14 +* INPUT : br_14 +* OUTPUT: data_15 +* INPUT : bl_15 +* INPUT : br_15 +* OUTPUT: data_16 +* INPUT : bl_16 +* INPUT : br_16 +* OUTPUT: data_17 +* INPUT : bl_17 +* INPUT : br_17 +* OUTPUT: data_18 +* INPUT : bl_18 +* INPUT : br_18 +* OUTPUT: data_19 +* INPUT : bl_19 +* INPUT : br_19 +* OUTPUT: data_20 +* INPUT : bl_20 +* INPUT : br_20 +* OUTPUT: data_21 +* INPUT : bl_21 +* INPUT : br_21 +* OUTPUT: data_22 +* INPUT : bl_22 +* INPUT : br_22 +* OUTPUT: data_23 +* INPUT : bl_23 +* INPUT : br_23 +* OUTPUT: data_24 +* INPUT : bl_24 +* INPUT : br_24 +* OUTPUT: data_25 +* INPUT : bl_25 +* INPUT : br_25 +* OUTPUT: data_26 +* INPUT : bl_26 +* INPUT : br_26 +* OUTPUT: data_27 +* INPUT : bl_27 +* INPUT : br_27 +* OUTPUT: data_28 +* INPUT : bl_28 +* INPUT : br_28 +* OUTPUT: data_29 +* INPUT : bl_29 +* INPUT : br_29 +* OUTPUT: data_30 +* INPUT : bl_30 +* INPUT : br_30 +* OUTPUT: data_31 +* INPUT : bl_31 +* INPUT : br_31 +* OUTPUT: data_32 +* INPUT : bl_32 +* INPUT : br_32 +* OUTPUT: data_33 +* INPUT : bl_33 +* INPUT : br_33 +* OUTPUT: data_34 +* INPUT : bl_34 +* INPUT : br_34 +* OUTPUT: data_35 +* INPUT : bl_35 +* INPUT : br_35 +* OUTPUT: data_36 +* INPUT : bl_36 +* INPUT : br_36 +* OUTPUT: data_37 +* INPUT : bl_37 +* INPUT : br_37 +* OUTPUT: data_38 +* INPUT : bl_38 +* INPUT : br_38 +* OUTPUT: data_39 +* INPUT : bl_39 +* INPUT : br_39 +* OUTPUT: data_40 +* INPUT : bl_40 +* INPUT : br_40 +* OUTPUT: data_41 +* INPUT : bl_41 +* INPUT : br_41 +* OUTPUT: data_42 +* INPUT : bl_42 +* INPUT : br_42 +* OUTPUT: data_43 +* INPUT : bl_43 +* INPUT : br_43 +* OUTPUT: data_44 +* INPUT : bl_44 +* INPUT : br_44 +* OUTPUT: data_45 +* INPUT : bl_45 +* INPUT : br_45 +* OUTPUT: data_46 +* INPUT : bl_46 +* INPUT : br_46 +* OUTPUT: data_47 +* INPUT : bl_47 +* INPUT : br_47 +* OUTPUT: data_48 +* INPUT : bl_48 +* INPUT : br_48 +* OUTPUT: data_49 +* INPUT : bl_49 +* INPUT : br_49 +* OUTPUT: data_50 +* INPUT : bl_50 +* INPUT : br_50 +* OUTPUT: data_51 +* INPUT : bl_51 +* INPUT : br_51 +* OUTPUT: data_52 +* INPUT : bl_52 +* INPUT : br_52 +* OUTPUT: data_53 +* INPUT : bl_53 +* INPUT : br_53 +* OUTPUT: data_54 +* INPUT : bl_54 +* INPUT : br_54 +* OUTPUT: data_55 +* INPUT : bl_55 +* INPUT : br_55 +* OUTPUT: data_56 +* INPUT : bl_56 +* INPUT : br_56 +* OUTPUT: data_57 +* INPUT : bl_57 +* INPUT : br_57 +* OUTPUT: data_58 +* INPUT : bl_58 +* INPUT : br_58 +* OUTPUT: data_59 +* INPUT : bl_59 +* INPUT : br_59 +* OUTPUT: data_60 +* INPUT : bl_60 +* INPUT : br_60 +* OUTPUT: data_61 +* INPUT : bl_61 +* INPUT : br_61 +* OUTPUT: data_62 +* INPUT : bl_62 +* INPUT : br_62 +* OUTPUT: data_63 +* INPUT : bl_63 +* INPUT : br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 2 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp +Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp +Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp +Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp +Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp +Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp +Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp +Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp +Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp +Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp +Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp +Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp +Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp +Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp +Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp +Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp +Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp +Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp +Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp +Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp +Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp +Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp +Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp +Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp +Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp +Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp +Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp +Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp +Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp +Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp +Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp +Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp +Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp +Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp +Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp +Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp +Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp +Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp +Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp +Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp +Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp +Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp +Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp +Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp +Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp +Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp +Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp +Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp +Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp +Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp +Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp +Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp +Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp +Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp +Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp +Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp +Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp +Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp +Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp +Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp +Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp +Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp +.ENDS sense_amp_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* OUTPUT: bl_64 +* OUTPUT: br_64 +* OUTPUT: bl_65 +* OUTPUT: br_65 +* OUTPUT: bl_66 +* OUTPUT: br_66 +* OUTPUT: bl_67 +* OUTPUT: br_67 +* OUTPUT: bl_68 +* OUTPUT: br_68 +* OUTPUT: bl_69 +* OUTPUT: br_69 +* OUTPUT: bl_70 +* OUTPUT: br_70 +* OUTPUT: bl_71 +* OUTPUT: br_71 +* OUTPUT: bl_72 +* OUTPUT: br_72 +* OUTPUT: bl_73 +* OUTPUT: br_73 +* OUTPUT: bl_74 +* OUTPUT: br_74 +* OUTPUT: bl_75 +* OUTPUT: br_75 +* OUTPUT: bl_76 +* OUTPUT: br_76 +* OUTPUT: bl_77 +* OUTPUT: br_77 +* OUTPUT: bl_78 +* OUTPUT: br_78 +* OUTPUT: bl_79 +* OUTPUT: br_79 +* OUTPUT: bl_80 +* OUTPUT: br_80 +* OUTPUT: bl_81 +* OUTPUT: br_81 +* OUTPUT: bl_82 +* OUTPUT: br_82 +* OUTPUT: bl_83 +* OUTPUT: br_83 +* OUTPUT: bl_84 +* OUTPUT: br_84 +* OUTPUT: bl_85 +* OUTPUT: br_85 +* OUTPUT: bl_86 +* OUTPUT: br_86 +* OUTPUT: bl_87 +* OUTPUT: br_87 +* OUTPUT: bl_88 +* OUTPUT: br_88 +* OUTPUT: bl_89 +* OUTPUT: br_89 +* OUTPUT: bl_90 +* OUTPUT: br_90 +* OUTPUT: bl_91 +* OUTPUT: br_91 +* OUTPUT: bl_92 +* OUTPUT: br_92 +* OUTPUT: bl_93 +* OUTPUT: br_93 +* OUTPUT: bl_94 +* OUTPUT: br_94 +* OUTPUT: bl_95 +* OUTPUT: br_95 +* OUTPUT: bl_96 +* OUTPUT: br_96 +* OUTPUT: bl_97 +* OUTPUT: br_97 +* OUTPUT: bl_98 +* OUTPUT: br_98 +* OUTPUT: bl_99 +* OUTPUT: br_99 +* OUTPUT: bl_100 +* OUTPUT: br_100 +* OUTPUT: bl_101 +* OUTPUT: br_101 +* OUTPUT: bl_102 +* OUTPUT: br_102 +* OUTPUT: bl_103 +* OUTPUT: br_103 +* OUTPUT: bl_104 +* OUTPUT: br_104 +* OUTPUT: bl_105 +* OUTPUT: br_105 +* OUTPUT: bl_106 +* OUTPUT: br_106 +* OUTPUT: bl_107 +* OUTPUT: br_107 +* OUTPUT: bl_108 +* OUTPUT: br_108 +* OUTPUT: bl_109 +* OUTPUT: br_109 +* OUTPUT: bl_110 +* OUTPUT: br_110 +* OUTPUT: bl_111 +* OUTPUT: br_111 +* OUTPUT: bl_112 +* OUTPUT: br_112 +* OUTPUT: bl_113 +* OUTPUT: br_113 +* OUTPUT: bl_114 +* OUTPUT: br_114 +* OUTPUT: bl_115 +* OUTPUT: br_115 +* OUTPUT: bl_116 +* OUTPUT: br_116 +* OUTPUT: bl_117 +* OUTPUT: br_117 +* OUTPUT: bl_118 +* OUTPUT: br_118 +* OUTPUT: bl_119 +* OUTPUT: br_119 +* OUTPUT: bl_120 +* OUTPUT: br_120 +* OUTPUT: bl_121 +* OUTPUT: br_121 +* OUTPUT: bl_122 +* OUTPUT: br_122 +* OUTPUT: bl_123 +* OUTPUT: br_123 +* OUTPUT: bl_124 +* OUTPUT: br_124 +* OUTPUT: bl_125 +* OUTPUT: br_125 +* OUTPUT: bl_126 +* OUTPUT: br_126 +* OUTPUT: bl_127 +* OUTPUT: br_127 +* OUTPUT: bl_128 +* OUTPUT: br_128 +* INPUT : en_bar +* POWER : vdd +* cols: 129 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 +Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 +Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 +Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 +Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 +Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 +Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 +Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 +Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 +Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 +Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 +Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 +Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 +Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 +Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 +Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 +Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 +Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 +Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 +Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 +Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 +Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 +Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 +Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 +Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 +Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 +Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 +Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 +Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 +Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 +Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 +Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 +Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 +Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 +Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 +Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 +Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 +Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 +Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 +Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 +Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 +Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 +Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 +Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 +Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 +Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 +Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 +Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 +Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 +Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 +Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 +Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 +Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 +Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 +Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 +Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 +Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 +Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 +Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 +Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 +Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 +Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 +Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 +Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 +Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 +Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 +Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 +Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 +Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 +Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 +Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 +Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 +Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 +Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 +Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 +Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 +Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 +Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 +Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 +Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 +Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 +Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 +Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 +Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 +Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 +Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 +Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 +Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 +Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 +Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 +Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 +Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 +Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 +Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 +Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 +Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 +Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 +Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 +Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 +Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 +Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 +Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 +Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 +Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 +Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 +Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 +Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 +Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 +Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 +Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 +Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 +Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 +Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 +Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 +Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 +Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 +Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 +Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 +Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 +Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 +Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 +Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 +Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 +Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 +Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 +Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd +*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* INPUT : data_2 +* INPUT : data_3 +* INPUT : data_4 +* INPUT : data_5 +* INPUT : data_6 +* INPUT : data_7 +* INPUT : data_8 +* INPUT : data_9 +* INPUT : data_10 +* INPUT : data_11 +* INPUT : data_12 +* INPUT : data_13 +* INPUT : data_14 +* INPUT : data_15 +* INPUT : data_16 +* INPUT : data_17 +* INPUT : data_18 +* INPUT : data_19 +* INPUT : data_20 +* INPUT : data_21 +* INPUT : data_22 +* INPUT : data_23 +* INPUT : data_24 +* INPUT : data_25 +* INPUT : data_26 +* INPUT : data_27 +* INPUT : data_28 +* INPUT : data_29 +* INPUT : data_30 +* INPUT : data_31 +* INPUT : data_32 +* INPUT : data_33 +* INPUT : data_34 +* INPUT : data_35 +* INPUT : data_36 +* INPUT : data_37 +* INPUT : data_38 +* INPUT : data_39 +* INPUT : data_40 +* INPUT : data_41 +* INPUT : data_42 +* INPUT : data_43 +* INPUT : data_44 +* INPUT : data_45 +* INPUT : data_46 +* INPUT : data_47 +* INPUT : data_48 +* INPUT : data_49 +* INPUT : data_50 +* INPUT : data_51 +* INPUT : data_52 +* INPUT : data_53 +* INPUT : data_54 +* INPUT : data_55 +* INPUT : data_56 +* INPUT : data_57 +* INPUT : data_58 +* INPUT : data_59 +* INPUT : data_60 +* INPUT : data_61 +* INPUT : data_62 +* INPUT : data_63 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 64 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver +Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver +Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver +Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver +Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver +Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver +Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver +Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver +Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver +Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver +Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver +Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver +Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver +Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver +Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver +Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver +Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver +Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver +Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver +Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver +Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver +Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver +Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver +Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver +Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver +Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver +Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver +Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver +Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver +Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver +Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver +Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver +Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver +Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver +Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver +Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver +Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver +Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver +Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver +Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver +Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver +Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver +Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver +Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver +Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver +Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver +Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver +Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver +Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver +Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver +Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver +Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver +Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver +Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver +Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver +Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver +Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver +Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver +Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver +Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver +Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver +Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver +Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver +.ENDS write_driver_array + +* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +.SUBCKT column_mux bl br bl_out br_out sel gnd +*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B +* INOUT : bl +* INOUT : br +* INOUT : bl_out +* INOUT : br_out +* INOUT : sel +* INOUT : gnd +Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +.ENDS column_mux + +.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd +*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* INOUT : sel_0 +* INOUT : sel_1 +* INOUT : bl_out_0 +* INOUT : br_out_0 +* INOUT : bl_out_1 +* INOUT : br_out_1 +* INOUT : bl_out_2 +* INOUT : br_out_2 +* INOUT : bl_out_3 +* INOUT : br_out_3 +* INOUT : bl_out_4 +* INOUT : br_out_4 +* INOUT : bl_out_5 +* INOUT : br_out_5 +* INOUT : bl_out_6 +* INOUT : br_out_6 +* INOUT : bl_out_7 +* INOUT : br_out_7 +* INOUT : bl_out_8 +* INOUT : br_out_8 +* INOUT : bl_out_9 +* INOUT : br_out_9 +* INOUT : bl_out_10 +* INOUT : br_out_10 +* INOUT : bl_out_11 +* INOUT : br_out_11 +* INOUT : bl_out_12 +* INOUT : br_out_12 +* INOUT : bl_out_13 +* INOUT : br_out_13 +* INOUT : bl_out_14 +* INOUT : br_out_14 +* INOUT : bl_out_15 +* INOUT : br_out_15 +* INOUT : bl_out_16 +* INOUT : br_out_16 +* INOUT : bl_out_17 +* INOUT : br_out_17 +* INOUT : bl_out_18 +* INOUT : br_out_18 +* INOUT : bl_out_19 +* INOUT : br_out_19 +* INOUT : bl_out_20 +* INOUT : br_out_20 +* INOUT : bl_out_21 +* INOUT : br_out_21 +* INOUT : bl_out_22 +* INOUT : br_out_22 +* INOUT : bl_out_23 +* INOUT : br_out_23 +* INOUT : bl_out_24 +* INOUT : br_out_24 +* INOUT : bl_out_25 +* INOUT : br_out_25 +* INOUT : bl_out_26 +* INOUT : br_out_26 +* INOUT : bl_out_27 +* INOUT : br_out_27 +* INOUT : bl_out_28 +* INOUT : br_out_28 +* INOUT : bl_out_29 +* INOUT : br_out_29 +* INOUT : bl_out_30 +* INOUT : br_out_30 +* INOUT : bl_out_31 +* INOUT : br_out_31 +* INOUT : bl_out_32 +* INOUT : br_out_32 +* INOUT : bl_out_33 +* INOUT : br_out_33 +* INOUT : bl_out_34 +* INOUT : br_out_34 +* INOUT : bl_out_35 +* INOUT : br_out_35 +* INOUT : bl_out_36 +* INOUT : br_out_36 +* INOUT : bl_out_37 +* INOUT : br_out_37 +* INOUT : bl_out_38 +* INOUT : br_out_38 +* INOUT : bl_out_39 +* INOUT : br_out_39 +* INOUT : bl_out_40 +* INOUT : br_out_40 +* INOUT : bl_out_41 +* INOUT : br_out_41 +* INOUT : bl_out_42 +* INOUT : br_out_42 +* INOUT : bl_out_43 +* INOUT : br_out_43 +* INOUT : bl_out_44 +* INOUT : br_out_44 +* INOUT : bl_out_45 +* INOUT : br_out_45 +* INOUT : bl_out_46 +* INOUT : br_out_46 +* INOUT : bl_out_47 +* INOUT : br_out_47 +* INOUT : bl_out_48 +* INOUT : br_out_48 +* INOUT : bl_out_49 +* INOUT : br_out_49 +* INOUT : bl_out_50 +* INOUT : br_out_50 +* INOUT : bl_out_51 +* INOUT : br_out_51 +* INOUT : bl_out_52 +* INOUT : br_out_52 +* INOUT : bl_out_53 +* INOUT : br_out_53 +* INOUT : bl_out_54 +* INOUT : br_out_54 +* INOUT : bl_out_55 +* INOUT : br_out_55 +* INOUT : bl_out_56 +* INOUT : br_out_56 +* INOUT : bl_out_57 +* INOUT : br_out_57 +* INOUT : bl_out_58 +* INOUT : br_out_58 +* INOUT : bl_out_59 +* INOUT : br_out_59 +* INOUT : bl_out_60 +* INOUT : br_out_60 +* INOUT : bl_out_61 +* INOUT : br_out_61 +* INOUT : bl_out_62 +* INOUT : br_out_62 +* INOUT : bl_out_63 +* INOUT : br_out_63 +* INOUT : gnd +* cols: 128 word_size: 64 bl: bl br: br +XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux +XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux +XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux +XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux +XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux +XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux +XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux +XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux +XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux +XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux +XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux +XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux +XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux +XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux +XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux +XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux +XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux +XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux +XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux +XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux +XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux +XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux +XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux +XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux +XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux +XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux +XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux +XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux +XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux +XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux +XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux +XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux +XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux +XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux +XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux +XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux +XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux +XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux +XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux +XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux +XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux +XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux +XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux +XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux +XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux +XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux +XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux +XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux +XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux +XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux +XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux +XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux +XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux +XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux +XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux +XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux +XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux +XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux +XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux +XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux +XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux +XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux +XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux +XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux +XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux +XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux +XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux +XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux +XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux +XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux +XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux +XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux +XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux +XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux +XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux +XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux +XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux +XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux +XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux +XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux +XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux +XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux +XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux +XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux +XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux +XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux +XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux +XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux +XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux +XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux +XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux +XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux +XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux +XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux +XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux +XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux +XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux +XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux +XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux +XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux +XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux +XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux +XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux +XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux +XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux +XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux +XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux +XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux +XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux +XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux +XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux +XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux +XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux +XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux +XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux +XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux +XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux +XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux +XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux +XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux +XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux +XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux +XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux +XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux +XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux +XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux +XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux +XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux +.ENDS column_mux_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* INPUT : sel_0 +* INPUT : sel_1 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array +Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2 + +* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p +.ENDS pinv_0 + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 32 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv_0 +.ENDS and2_dec_0 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv_0 +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* INPUT : in_16 +* INPUT : in_17 +* INPUT : in_18 +* INPUT : in_19 +* INPUT : in_20 +* INPUT : in_21 +* INPUT : in_22 +* INPUT : in_23 +* INPUT : in_24 +* INPUT : in_25 +* INPUT : in_26 +* INPUT : in_27 +* INPUT : in_28 +* INPUT : in_29 +* INPUT : in_30 +* INPUT : in_31 +* INPUT : in_32 +* INPUT : in_33 +* INPUT : in_34 +* INPUT : in_35 +* INPUT : in_36 +* INPUT : in_37 +* INPUT : in_38 +* INPUT : in_39 +* INPUT : in_40 +* INPUT : in_41 +* INPUT : in_42 +* INPUT : in_43 +* INPUT : in_44 +* INPUT : in_45 +* INPUT : in_46 +* INPUT : in_47 +* INPUT : in_48 +* INPUT : in_49 +* INPUT : in_50 +* INPUT : in_51 +* INPUT : in_52 +* INPUT : in_53 +* INPUT : in_54 +* INPUT : in_55 +* INPUT : in_56 +* INPUT : in_57 +* INPUT : in_58 +* INPUT : in_59 +* INPUT : in_60 +* INPUT : in_61 +* INPUT : in_62 +* INPUT : in_63 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver +Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver +Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver +Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver +Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver +Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver +Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver +Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver +Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver +Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver +Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver +Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver +Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver +Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver +Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver +Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver +Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver +Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver +Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver +Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver +Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver +Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver +Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver +Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver +Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver +Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver +Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver +Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver +Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver +Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver +Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver +Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver +Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver +Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver +Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver +Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver +Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver +Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver +Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver +Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver +Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver +Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver +Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver +Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver +Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver +Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver +Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver +Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver +.ENDS wordline_driver_array + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3 + +.SUBCKT and3_dec A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand3_dec_nand A B C zb_int vdd gnd pnand3 +Xpand3_dec_inv zb_int Z vdd gnd pinv +.ENDS and3_dec + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* OUTPUT: decode_16 +* OUTPUT: decode_17 +* OUTPUT: decode_18 +* OUTPUT: decode_19 +* OUTPUT: decode_20 +* OUTPUT: decode_21 +* OUTPUT: decode_22 +* OUTPUT: decode_23 +* OUTPUT: decode_24 +* OUTPUT: decode_25 +* OUTPUT: decode_26 +* OUTPUT: decode_27 +* OUTPUT: decode_28 +* OUTPUT: decode_29 +* OUTPUT: decode_30 +* OUTPUT: decode_31 +* OUTPUT: decode_32 +* OUTPUT: decode_33 +* OUTPUT: decode_34 +* OUTPUT: decode_35 +* OUTPUT: decode_36 +* OUTPUT: decode_37 +* OUTPUT: decode_38 +* OUTPUT: decode_39 +* OUTPUT: decode_40 +* OUTPUT: decode_41 +* OUTPUT: decode_42 +* OUTPUT: decode_43 +* OUTPUT: decode_44 +* OUTPUT: decode_45 +* OUTPUT: decode_46 +* OUTPUT: decode_47 +* OUTPUT: decode_48 +* OUTPUT: decode_49 +* OUTPUT: decode_50 +* OUTPUT: decode_51 +* OUTPUT: decode_52 +* OUTPUT: decode_53 +* OUTPUT: decode_54 +* OUTPUT: decode_55 +* OUTPUT: decode_56 +* OUTPUT: decode_57 +* OUTPUT: decode_58 +* OUTPUT: decode_59 +* OUTPUT: decode_60 +* OUTPUT: decode_61 +* OUTPUT: decode_62 +* OUTPUT: decode_63 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 +Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 +XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec +XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec +XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec +XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec +XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec +XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec +XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec +XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec +XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec +XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec +XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec +XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec +XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec +XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec +XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec +XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec +XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec +XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec +XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec +XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec +XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec +XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec +XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec +XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec +XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec +XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec +XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec +XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec +XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec +XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec +XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec +XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec +XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec +XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec +XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec +XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec +XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec +XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec +XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec +XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec +XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec +XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec +XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec +XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec +XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec +XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec +XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec +XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec +XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec +XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec +XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec +XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec +XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec +XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec +XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec +XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec +XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec +XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec +XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec +XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec +XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec +XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec +XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec +XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec +.ENDS hierarchical_decoder + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: dout0_2 +* OUTPUT: dout0_3 +* OUTPUT: dout0_4 +* OUTPUT: dout0_5 +* OUTPUT: dout0_6 +* OUTPUT: dout0_7 +* OUTPUT: dout0_8 +* OUTPUT: dout0_9 +* OUTPUT: dout0_10 +* OUTPUT: dout0_11 +* OUTPUT: dout0_12 +* OUTPUT: dout0_13 +* OUTPUT: dout0_14 +* OUTPUT: dout0_15 +* OUTPUT: dout0_16 +* OUTPUT: dout0_17 +* OUTPUT: dout0_18 +* OUTPUT: dout0_19 +* OUTPUT: dout0_20 +* OUTPUT: dout0_21 +* OUTPUT: dout0_22 +* OUTPUT: dout0_23 +* OUTPUT: dout0_24 +* OUTPUT: dout0_25 +* OUTPUT: dout0_26 +* OUTPUT: dout0_27 +* OUTPUT: dout0_28 +* OUTPUT: dout0_29 +* OUTPUT: dout0_30 +* OUTPUT: dout0_31 +* OUTPUT: dout0_32 +* OUTPUT: dout0_33 +* OUTPUT: dout0_34 +* OUTPUT: dout0_35 +* OUTPUT: dout0_36 +* OUTPUT: dout0_37 +* OUTPUT: dout0_38 +* OUTPUT: dout0_39 +* OUTPUT: dout0_40 +* OUTPUT: dout0_41 +* OUTPUT: dout0_42 +* OUTPUT: dout0_43 +* OUTPUT: dout0_44 +* OUTPUT: dout0_45 +* OUTPUT: dout0_46 +* OUTPUT: dout0_47 +* OUTPUT: dout0_48 +* OUTPUT: dout0_49 +* OUTPUT: dout0_50 +* OUTPUT: dout0_51 +* OUTPUT: dout0_52 +* OUTPUT: dout0_53 +* OUTPUT: dout0_54 +* OUTPUT: dout0_55 +* OUTPUT: dout0_56 +* OUTPUT: dout0_57 +* OUTPUT: dout0_58 +* OUTPUT: dout0_59 +* OUTPUT: dout0_60 +* OUTPUT: dout0_61 +* OUTPUT: dout0_62 +* OUTPUT: dout0_63 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : din0_2 +* INPUT : din0_3 +* INPUT : din0_4 +* INPUT : din0_5 +* INPUT : din0_6 +* INPUT : din0_7 +* INPUT : din0_8 +* INPUT : din0_9 +* INPUT : din0_10 +* INPUT : din0_11 +* INPUT : din0_12 +* INPUT : din0_13 +* INPUT : din0_14 +* INPUT : din0_15 +* INPUT : din0_16 +* INPUT : din0_17 +* INPUT : din0_18 +* INPUT : din0_19 +* INPUT : din0_20 +* INPUT : din0_21 +* INPUT : din0_22 +* INPUT : din0_23 +* INPUT : din0_24 +* INPUT : din0_25 +* INPUT : din0_26 +* INPUT : din0_27 +* INPUT : din0_28 +* INPUT : din0_29 +* INPUT : din0_30 +* INPUT : din0_31 +* INPUT : din0_32 +* INPUT : din0_33 +* INPUT : din0_34 +* INPUT : din0_35 +* INPUT : din0_36 +* INPUT : din0_37 +* INPUT : din0_38 +* INPUT : din0_39 +* INPUT : din0_40 +* INPUT : din0_41 +* INPUT : din0_42 +* INPUT : din0_43 +* INPUT : din0_44 +* INPUT : din0_45 +* INPUT : din0_46 +* INPUT : din0_47 +* INPUT : din0_48 +* INPUT : din0_49 +* INPUT : din0_50 +* INPUT : din0_51 +* INPUT : din0_52 +* INPUT : din0_53 +* INPUT : din0_54 +* INPUT : din0_55 +* INPUT : din0_56 +* INPUT : din0_57 +* INPUT : din0_58 +* INPUT : din0_59 +* INPUT : din0_60 +* INPUT : din0_61 +* INPUT : din0_62 +* INPUT : din0_63 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : addr0_4 +* INPUT : addr0_5 +* INPUT : addr0_6 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address +Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf +.ENDS bank + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_2 +Xdff_buf_inv2 Qb Q vdd gnd pinv_3 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_0 + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +.SUBCKT pinv_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p +.ENDS pinv_4 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_4 +.ENDS pdriver + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p +Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p +.ENDS pinv_11 + +* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p +.ENDS pinv_9 + +* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p +Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +.ENDS pinv_10 + +* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p + +* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p + +.SUBCKT pinv_12 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p +Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p +.ENDS pinv_12 + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_7 + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_8 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 1, 2, 5, 14, 42, 125] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 +Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 +Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 +Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 +.ENDS pdriver_0 + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3_0 + +* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p + +* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +.SUBCKT pinv_16 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p +Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +.ENDS pinv_16 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [64] +Xbuf_inv1 A Z vdd gnd pinv_16 +.ENDS pdriver_3 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +.SUBCKT pinv_17 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_17 + +* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p + +* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p + +.SUBCKT pinv_18 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p +Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p +.ENDS pinv_18 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 2, 5, 14, 43] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 +Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 +.ENDS pdriver_4 + +* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p + +* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p + +.SUBCKT pinv_15 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p +Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p +.ENDS pinv_15 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [72] +Xbuf_inv1 A Z vdd gnd pinv_15 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT pinv_19 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_19 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_19 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 +Xdinv1 dout_1 dout_2 vdd gnd pinv_19 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 +Xdinv2 dout_2 dout_3 vdd gnd pinv_19 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 +Xdinv3 dout_3 dout_4 vdd gnd pinv_19 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 +Xdinv4 dout_4 dout_5 vdd gnd pinv_19 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 +Xdinv5 dout_5 dout_6 vdd gnd pinv_19 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 +Xdinv6 dout_6 dout_7 vdd gnd pinv_19 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 +Xdinv7 dout_7 dout_8 vdd gnd pinv_19 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 +Xdinv8 dout_8 out vdd gnd pinv_19 +Xdload_8_0 out n_8_0 vdd gnd pinv_19 +Xdload_8_1 out n_8_1 vdd gnd pinv_19 +Xdload_8_2 out n_8_2 vdd gnd pinv_19 +Xdload_8_3 out n_8_3 vdd gnd pinv_19 +.ENDS delay_chain + +* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p + +.SUBCKT pinv_14 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p +Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p +.ENDS pinv_14 + +* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p + +.SUBCKT pinv_13 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p +.ENDS pinv_13 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [7, 21] +Xbuf_inv1 A Zb1_int vdd gnd pinv_13 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 +.ENDS pdriver_1 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_1 + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 64 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 +Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_17 +Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 +Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 +Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain +Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 +Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd +*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : din0[2] +* INPUT : din0[3] +* INPUT : din0[4] +* INPUT : din0[5] +* INPUT : din0[6] +* INPUT : din0[7] +* INPUT : din0[8] +* INPUT : din0[9] +* INPUT : din0[10] +* INPUT : din0[11] +* INPUT : din0[12] +* INPUT : din0[13] +* INPUT : din0[14] +* INPUT : din0[15] +* INPUT : din0[16] +* INPUT : din0[17] +* INPUT : din0[18] +* INPUT : din0[19] +* INPUT : din0[20] +* INPUT : din0[21] +* INPUT : din0[22] +* INPUT : din0[23] +* INPUT : din0[24] +* INPUT : din0[25] +* INPUT : din0[26] +* INPUT : din0[27] +* INPUT : din0[28] +* INPUT : din0[29] +* INPUT : din0[30] +* INPUT : din0[31] +* INPUT : din0[32] +* INPUT : din0[33] +* INPUT : din0[34] +* INPUT : din0[35] +* INPUT : din0[36] +* INPUT : din0[37] +* INPUT : din0[38] +* INPUT : din0[39] +* INPUT : din0[40] +* INPUT : din0[41] +* INPUT : din0[42] +* INPUT : din0[43] +* INPUT : din0[44] +* INPUT : din0[45] +* INPUT : din0[46] +* INPUT : din0[47] +* INPUT : din0[48] +* INPUT : din0[49] +* INPUT : din0[50] +* INPUT : din0[51] +* INPUT : din0[52] +* INPUT : din0[53] +* INPUT : din0[54] +* INPUT : din0[55] +* INPUT : din0[56] +* INPUT : din0[57] +* INPUT : din0[58] +* INPUT : din0[59] +* INPUT : din0[60] +* INPUT : din0[61] +* INPUT : din0[62] +* INPUT : din0[63] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : addr0[4] +* INPUT : addr0[5] +* INPUT : addr0[6] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* OUTPUT: dout0[2] +* OUTPUT: dout0[3] +* OUTPUT: dout0[4] +* OUTPUT: dout0[5] +* OUTPUT: dout0[6] +* OUTPUT: dout0[7] +* OUTPUT: dout0[8] +* OUTPUT: dout0[9] +* OUTPUT: dout0[10] +* OUTPUT: dout0[11] +* OUTPUT: dout0[12] +* OUTPUT: dout0[13] +* OUTPUT: dout0[14] +* OUTPUT: dout0[15] +* OUTPUT: dout0[16] +* OUTPUT: dout0[17] +* OUTPUT: dout0[18] +* OUTPUT: dout0[19] +* OUTPUT: dout0[20] +* OUTPUT: dout0[21] +* OUTPUT: dout0[22] +* OUTPUT: dout0[23] +* OUTPUT: dout0[24] +* OUTPUT: dout0[25] +* OUTPUT: dout0[26] +* OUTPUT: dout0[27] +* OUTPUT: dout0[28] +* OUTPUT: dout0[29] +* OUTPUT: dout0[30] +* OUTPUT: dout0[31] +* OUTPUT: dout0[32] +* OUTPUT: dout0[33] +* OUTPUT: dout0[34] +* OUTPUT: dout0[35] +* OUTPUT: dout0[36] +* OUTPUT: dout0[37] +* OUTPUT: dout0[38] +* OUTPUT: dout0[39] +* OUTPUT: dout0[40] +* OUTPUT: dout0[41] +* OUTPUT: dout0[42] +* OUTPUT: dout0[43] +* OUTPUT: dout0[44] +* OUTPUT: dout0[45] +* OUTPUT: dout0[46] +* OUTPUT: dout0[47] +* OUTPUT: dout0[48] +* OUTPUT: dout0[49] +* OUTPUT: dout0[50] +* OUTPUT: dout0[51] +* OUTPUT: dout0[52] +* OUTPUT: dout0[53] +* OUTPUT: dout0[54] +* OUTPUT: dout0[55] +* OUTPUT: dout0[56] +* OUTPUT: dout0[57] +* OUTPUT: dout0[58] +* OUTPUT: dout0[59] +* OUTPUT: dout0[60] +* OUTPUT: dout0[61] +* OUTPUT: dout0[62] +* OUTPUT: dout0[63] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff +Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff +Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff +.ENDS sram_64_128_scn4m_subm diff --git a/2x16/delay_sram_2_16_scn4m_subm.sp b/2x16/delay_sram_2_16_scn4m_subm.sp new file mode 100644 index 00000000..33a1cce7 --- /dev/null +++ b/2x16/delay_sram_2_16_scn4m_subm.sp @@ -0,0 +1,1162 @@ +************************************************** +* OpenRAM generated memory with exclusively delay based logic +* Words: 16 +* Data bits: 2 +* Banks: 1 +* Column mux: 1:1 +* Trimmed: False +* LVS: False +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I dout_0:O dout_1:O dout_2:O dout_3:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 4 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +.ENDS row_addr_dff + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* POWER : vdd +* GROUND: gnd +* rows: 16 cols: 2 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +.ENDS bitcell_array + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* INPUT : en_bar +* POWER : vdd +* cols: 3 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 1 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +.ENDS sense_amp_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd +*.PININFO data_0:I data_1:I bl_0:O br_0:O bl_1:O br_1:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver +.ENDS write_driver_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 dout_0 dout_1 din_0 din_1 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B dout_0:O dout_1:O din_0:I din_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 bl_0 br_0 bl_1 br_1 w_en vdd gnd write_driver_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2 + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 +XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec +XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec +XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec +XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec +XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec +XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec +XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec +XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec +XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec +XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec +XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec +XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec +XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec +XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec +XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec +XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec +.ENDS hierarchical_decoder + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec_0 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 16 cols: 2 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +.ENDS wordline_driver_array + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 rbl_bl_0_0 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O rbl_bl_0_0:O din0_0:I din0_1:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 dout0_0 dout0_1 din0_0 din0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 rbl_wl0 vdd gnd port_address +.ENDS bank + +* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p + +* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p +.ENDS pinv_7 + +.SUBCKT pinv_5 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_5 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 5] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_7 +.ENDS pdriver_1 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_1 + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p +.ENDS pinv_2 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_2 +.ENDS pdriver + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_0 + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_11 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_6 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_6 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [2] +Xbuf_inv1 A Z vdd gnd pinv_6 +.ENDS pdriver_3 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3_0 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +* spice ptx M{0} {1} p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p + +* spice ptx M{0} {1} n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p +Mpinv_nmos Z A gnd gnd n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p +.ENDS pinv_8 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 2, 5, 15] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Z vdd gnd pinv_8 +.ENDS pdriver_0 + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_1 + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_0 + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_0 +Xdff_buf_inv2 Qb Q vdd gnd pinv_1 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_10 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_5 +.ENDS pdriver_4 + +* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p + +* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p +Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +.ENDS pinv_9 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [10] +Xbuf_inv1 A Z vdd gnd pinv_9 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +* Used for tiling delay chain to desired length +.SUBCKT delay_chain_segment in out vdd gnd +Xdinv0 in dout_1 vdd gnd pinv_11 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 +Xdinv1 dout_1 out vdd gnd pinv_11 +Xdload_1_0 out n_1_0 vdd gnd pinv_11 +Xdload_1_1 out n_1_1 vdd gnd pinv_11 +Xdload_1_2 out n_1_2 vdd gnd pinv_11 +Xdload_1_3 out n_1_3 vdd gnd pinv_11 +.ENDS delay_chain_segment + +.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd +Xdelay1 in out1 vdd gnd delay_chain_segment +Xdelay2 out1 out2 vdd gnd delay_chain_segment +Xdelay3 out2 out3 vdd gnd delay_chain_segment +Xdelay4 out3 out4 vdd gnd delay_chain_segment +Xdelay5 out4 out5 vdd gnd delay_chain_segment +Xdelay6 out5 out6 vdd gnd delay_chain_segment +Xdelay7 out6 out7 vdd gnd delay_chain_segment +Xdelay8 out7 out8 vdd gnd delay_chain_segment +Xdelay9 out8 out9 vdd gnd delay_chain_segment +Xdelay10 out9 out10 vdd gnd delay_chain_segment +Xdelay11 out10 out11 vdd gnd delay_chain_segment +Xdelay12 out11 out12 vdd gnd delay_chain_segment +Xdelay13 out12 out13 vdd gnd delay_chain_segment +Xdelay14 out13 out14 vdd gnd delay_chain_segment +Xdelay15 out14 out15 vdd gnd delay_chain_segment +Xdelay16 out15 out16 vdd gnd delay_chain_segment +.ENDS multi_delay_chain + +.SUBCKT glitch_generator in glitch1_bar glitch2_bar glitch3_bar vdd gnd +*.PININFO in:I glitch1_bar:O glitch2_bar:O glitch3_bar:O vdd:B gnd:B +Xmulti_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain +Xinv_g1 out6 g1_end vdd gnd pinv_11 +Xinv_g2 out7 g2_end vdd gnd pinv_11 +Xinv_g3 out16 g3_end vdd gnd pinv_11 +Xnand2_g1 out2 g1_end glitch1_bar vdd gnd pnand2 +Xnand2_g2 in g2_end glitch2_bar vdd gnd pnand2 +Xnand2_g3 out6 g3_end glitch3_bar vdd gnd pnand2 +.ENDS glitch_generator + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl (NO LONGER USED) +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +* is cs_buf needed on larger memories? +Xbuf_cs cs cs_buf vdd gnd pdriver_0 +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xglitch_generator gated_clk_buf glitch1_bar glitch2_bar glitch3_bar vdd gnd glitch_generator +Xinv_g3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 +Xand_s_en we_bar gated_clk_bar glitch3_bar s_en vdd gnd pand3 +Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 +Xand_wl_en cs_buf glitch2_bar wl_en vdd gnd pand2 +Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 2 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +.ENDS data_dff + +.SUBCKT sram_2_16_scn4m_subm din0[0] din0[1] addr0[0] addr0[1] addr0[2] addr0[3] csb0 web0 clk0 dout0[0] dout0[1] vdd gnd +*.PININFO din0[0]:I din0[1]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] rbl_bl0 bank_din0_0 bank_din0_1 a0_0 a0_1 a0_2 a0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] a0_0 a0_1 a0_2 a0_3 clk_buf0 vdd gnd row_addr_dff +Xdata_dff0 din0[0] din0[1] bank_din0_0 bank_din0_1 clk_buf0 vdd gnd data_dff +.ENDS sram_2_16_scn4m_subm diff --git a/2x16/sram_2_16_scn4m_subm.html b/2x16/sram_2_16_scn4m_subm.html new file mode 100644 index 00000000..7a189353 --- /dev/null +++ b/2x16/sram_2_16_scn4m_subm.html @@ -0,0 +1,35 @@ + + +VLSIDAOpenRAM

sram_2_16_scn4m_subm.html

Compiled at: 2022-01-19

DRC errors: skipped

LVS errors: skipped

Git commit id: 06d391b3e365127628434b98044035232615f4b0

Ports and Configuration

TypeValue
WORD_SIZE2
NUM_WORDS16
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0
+

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)200MHz
+

Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[1:0] setup rising0.0090.009ns
din0[1:0] setup falling0.0090.009ns
din0[1:0] hold rising0.0010.001ns
din0[1:0] hold falling0.0010.001ns
dout0[1:0] cell rise1.2571.347ns
dout0[1:0] cell fall1.2571.347ns
dout0[1:0] rise transition0.0060.015ns
dout0[1:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[3:0] setup rising0.0090.009ns
addr0[3:0] setup falling0.0090.009ns
addr0[3:0] hold rising0.0010.001ns
addr0[3:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns
+

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising3.4010mW
!csb0 & clk0 & !web0Read Falling3.4010mW
!csb0 & !clk0 & web0Write Rising3.4010mW
!csb0 & !clk0 & web0Write Falling3.4010mW
csb0leakage0.000194mW
+

Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib
+

Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_2_16_scn4m_subm.html
.libSynthesis modelssram_2_16_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_2_16_scn4m_subm.log
.pyOpenRAM configuration filesram_2_16_scn4m_subm.py
.spSPICE netlistssram_2_16_scn4m_subm.sp
.vVerilog simulation modelssram_2_16_scn4m_subm.v
diff --git a/2x16/sram_2_16_scn4m_subm.lvs.sp b/2x16/sram_2_16_scn4m_subm.lvs.sp new file mode 100644 index 00000000..61329998 --- /dev/null +++ b/2x16/sram_2_16_scn4m_subm.lvs.sp @@ -0,0 +1,1171 @@ +************************************************** +* OpenRAM generated memory. +* Words: 16 +* Data bits: 2 +* Banks: 1 +* Column mux: 1:1 +* Trimmed: False +* LVS: True +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I dout_0:O dout_1:O dout_2:O dout_3:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 4 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +.ENDS row_addr_dff + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* POWER : vdd +* GROUND: gnd +* rows: 16 cols: 2 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +.ENDS bitcell_array + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* INPUT : en_bar +* POWER : vdd +* cols: 3 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 1 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +.ENDS sense_amp_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd +*.PININFO data_0:I data_1:I bl_0:O br_0:O bl_1:O br_1:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver +.ENDS write_driver_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 dout_0 dout_1 din_0 din_1 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B dout_0:O dout_1:O din_0:I din_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 bl_0 br_0 bl_1 br_1 w_en vdd gnd write_driver_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2 + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 +XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec +XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec +XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec +XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec +XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec +XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec +XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec +XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec +XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec +XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec +XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec +XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec +XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec +XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec +XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec +XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec +.ENDS hierarchical_decoder + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec_0 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 16 cols: 2 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +.ENDS wordline_driver_array + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 rbl_bl_0_0 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O rbl_bl_0_0:O din0_0:I din0_1:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 dout0_0 dout0_1 din0_0 din0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 rbl_wl0 vdd gnd port_address +.ENDS bank + +* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p + +* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u +.ENDS pinv_7 + +.SUBCKT pinv_5 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_5 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 5] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_7 +.ENDS pdriver_1 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2_1 + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u +.ENDS pinv_2 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_2 +.ENDS pdriver + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2_0 + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_11 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_11 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 +Xdinv1 dout_1 dout_2 vdd gnd pinv_11 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_11 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_11 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_11 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_11 +Xdinv2 dout_2 dout_3 vdd gnd pinv_11 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_11 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_11 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_11 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_11 +Xdinv3 dout_3 dout_4 vdd gnd pinv_11 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_11 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_11 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_11 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_11 +Xdinv4 dout_4 dout_5 vdd gnd pinv_11 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_11 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_11 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_11 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_11 +Xdinv5 dout_5 dout_6 vdd gnd pinv_11 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_11 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_11 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_11 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_11 +Xdinv6 dout_6 dout_7 vdd gnd pinv_11 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_11 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_11 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_11 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_11 +Xdinv7 dout_7 dout_8 vdd gnd pinv_11 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_11 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_11 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_11 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_11 +Xdinv8 dout_8 out vdd gnd pinv_11 +Xdload_8_0 out n_8_0 vdd gnd pinv_11 +Xdload_8_1 out n_8_1 vdd gnd pinv_11 +Xdload_8_2 out n_8_2 vdd gnd pinv_11 +Xdload_8_3 out n_8_3 vdd gnd pinv_11 +.ENDS delay_chain + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_6 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pinv_6 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [2] +Xbuf_inv1 A Z vdd gnd pinv_6 +.ENDS pdriver_3 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand3_0 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +* spice ptx M{0} {1} p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p + +* spice ptx M{0} {1} n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=24.0u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=12.0u l=0.4u +.ENDS pinv_8 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 2, 5, 15] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Z vdd gnd pinv_8 +.ENDS pdriver_0 + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u +.ENDS pinv_1 + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pinv_0 + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_0 +Xdff_buf_inv2 Qb Q vdd gnd pinv_1 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_10 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_5 +.ENDS pdriver_4 + +* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p + +* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u +.ENDS pinv_9 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [10] +Xbuf_inv1 A Z vdd gnd pinv_9 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 +Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_10 +Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 +Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 +Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain +Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 +Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 2 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +.ENDS data_dff + +.SUBCKT sram_2_16_scn4m_subm din0[0] din0[1] addr0[0] addr0[1] addr0[2] addr0[3] csb0 web0 clk0 dout0[0] dout0[1] vdd gnd +*.PININFO din0[0]:I din0[1]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] rbl_bl0 bank_din0_0 bank_din0_1 a0_0 a0_1 a0_2 a0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] a0_0 a0_1 a0_2 a0_3 clk_buf0 vdd gnd row_addr_dff +Xdata_dff0 din0[0] din0[1] bank_din0_0 bank_din0_1 clk_buf0 vdd gnd data_dff +.ENDS sram_2_16_scn4m_subm diff --git a/2x16/sram_2_16_scn4m_subm.sp b/2x16/sram_2_16_scn4m_subm.sp new file mode 100644 index 00000000..fd519df6 --- /dev/null +++ b/2x16/sram_2_16_scn4m_subm.sp @@ -0,0 +1,1171 @@ +************************************************** +* OpenRAM generated memory. +* Words: 16 +* Data bits: 2 +* Banks: 1 +* Column mux: 1:1 +* Trimmed: False +* LVS: False +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I dout_0:O dout_1:O dout_2:O dout_3:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 4 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +.ENDS row_addr_dff + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* POWER : vdd +* GROUND: gnd +* rows: 16 cols: 2 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +.ENDS bitcell_array + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* INPUT : en_bar +* POWER : vdd +* cols: 3 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 1 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +.ENDS sense_amp_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd +*.PININFO data_0:I data_1:I bl_0:O br_0:O bl_1:O br_1:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver +.ENDS write_driver_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 dout_0 dout_1 din_0 din_1 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B dout_0:O dout_1:O din_0:I din_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 bl_0 br_0 bl_1 br_1 w_en vdd gnd write_driver_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2 + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 +XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec +XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec +XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec +XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec +XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec +XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec +XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec +XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec +XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec +XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec +XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec +XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec +XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec +XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec +XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec +XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec +.ENDS hierarchical_decoder + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec_0 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 16 cols: 2 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +.ENDS wordline_driver_array + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 rbl_bl_0_0 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O rbl_bl_0_0:O din0_0:I din0_1:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 dout0_0 dout0_1 din0_0 din0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 rbl_wl0 vdd gnd port_address +.ENDS bank + +* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p + +* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p +.ENDS pinv_7 + +.SUBCKT pinv_5 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_5 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 5] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_7 +.ENDS pdriver_1 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_1 + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p +.ENDS pinv_2 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_2 +.ENDS pdriver + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_0 + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_11 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_11 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 +Xdinv1 dout_1 dout_2 vdd gnd pinv_11 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_11 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_11 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_11 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_11 +Xdinv2 dout_2 dout_3 vdd gnd pinv_11 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_11 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_11 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_11 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_11 +Xdinv3 dout_3 dout_4 vdd gnd pinv_11 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_11 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_11 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_11 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_11 +Xdinv4 dout_4 dout_5 vdd gnd pinv_11 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_11 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_11 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_11 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_11 +Xdinv5 dout_5 dout_6 vdd gnd pinv_11 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_11 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_11 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_11 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_11 +Xdinv6 dout_6 dout_7 vdd gnd pinv_11 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_11 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_11 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_11 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_11 +Xdinv7 dout_7 dout_8 vdd gnd pinv_11 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_11 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_11 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_11 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_11 +Xdinv8 dout_8 out vdd gnd pinv_11 +Xdload_8_0 out n_8_0 vdd gnd pinv_11 +Xdload_8_1 out n_8_1 vdd gnd pinv_11 +Xdload_8_2 out n_8_2 vdd gnd pinv_11 +Xdload_8_3 out n_8_3 vdd gnd pinv_11 +.ENDS delay_chain + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_6 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_6 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [2] +Xbuf_inv1 A Z vdd gnd pinv_6 +.ENDS pdriver_3 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3_0 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +* spice ptx M{0} {1} p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p + +* spice ptx M{0} {1} n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p +Mpinv_nmos Z A gnd gnd n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p +.ENDS pinv_8 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 2, 5, 15] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Z vdd gnd pinv_8 +.ENDS pdriver_0 + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_1 + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_0 + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_0 +Xdff_buf_inv2 Qb Q vdd gnd pinv_1 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_10 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1] +Xbuf_inv1 A Zb1_int vdd gnd pinv_5 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_5 +.ENDS pdriver_4 + +* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p + +* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p +Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +.ENDS pinv_9 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [10] +Xbuf_inv1 A Z vdd gnd pinv_9 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 +Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_10 +Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 +Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 +Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain +Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 +Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 2 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +.ENDS data_dff + +.SUBCKT sram_2_16_scn4m_subm din0[0] din0[1] addr0[0] addr0[1] addr0[2] addr0[3] csb0 web0 clk0 dout0[0] dout0[1] vdd gnd +*.PININFO din0[0]:I din0[1]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] rbl_bl0 bank_din0_0 bank_din0_1 a0_0 a0_1 a0_2 a0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] a0_0 a0_1 a0_2 a0_3 clk_buf0 vdd gnd row_addr_dff +Xdata_dff0 din0[0] din0[1] bank_din0_0 bank_din0_1 clk_buf0 vdd gnd data_dff +.ENDS sram_2_16_scn4m_subm diff --git a/32x32/delay_sram_32_32_scn4m_subm.sp b/32x32/delay_sram_32_32_scn4m_subm.sp new file mode 100644 index 00000000..bc30863f --- /dev/null +++ b/32x32/delay_sram_32_32_scn4m_subm.sp @@ -0,0 +1,3590 @@ +************************************************** +* OpenRAM generated memory: delay version +* Words: 32 +* Data bits: 32 +* Banks: 1 +* Column mux: 1:1 +* Trimmed: False +* LVS: False +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 dout_0 dout_1 dout_2 dout_3 dout_4 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 5 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff +.ENDS row_addr_dff + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* POWER : vdd +* GROUND: gnd +* rows: 32 cols: 32 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw +.ENDS bitcell_array + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw +Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw +Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw +Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw +Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw +Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw +Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw +Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw +Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw +Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw +Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw +Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw +Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw +Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw +Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw +Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw +Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 en vdd gnd +*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* INPUT : data_2 +* INPUT : data_3 +* INPUT : data_4 +* INPUT : data_5 +* INPUT : data_6 +* INPUT : data_7 +* INPUT : data_8 +* INPUT : data_9 +* INPUT : data_10 +* INPUT : data_11 +* INPUT : data_12 +* INPUT : data_13 +* INPUT : data_14 +* INPUT : data_15 +* INPUT : data_16 +* INPUT : data_17 +* INPUT : data_18 +* INPUT : data_19 +* INPUT : data_20 +* INPUT : data_21 +* INPUT : data_22 +* INPUT : data_23 +* INPUT : data_24 +* INPUT : data_25 +* INPUT : data_26 +* INPUT : data_27 +* INPUT : data_28 +* INPUT : data_29 +* INPUT : data_30 +* INPUT : data_31 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 32 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver +Xwrite_driver2 data_2 bl_2 br_2 en vdd gnd write_driver +Xwrite_driver3 data_3 bl_3 br_3 en vdd gnd write_driver +Xwrite_driver4 data_4 bl_4 br_4 en vdd gnd write_driver +Xwrite_driver5 data_5 bl_5 br_5 en vdd gnd write_driver +Xwrite_driver6 data_6 bl_6 br_6 en vdd gnd write_driver +Xwrite_driver7 data_7 bl_7 br_7 en vdd gnd write_driver +Xwrite_driver8 data_8 bl_8 br_8 en vdd gnd write_driver +Xwrite_driver9 data_9 bl_9 br_9 en vdd gnd write_driver +Xwrite_driver10 data_10 bl_10 br_10 en vdd gnd write_driver +Xwrite_driver11 data_11 bl_11 br_11 en vdd gnd write_driver +Xwrite_driver12 data_12 bl_12 br_12 en vdd gnd write_driver +Xwrite_driver13 data_13 bl_13 br_13 en vdd gnd write_driver +Xwrite_driver14 data_14 bl_14 br_14 en vdd gnd write_driver +Xwrite_driver15 data_15 bl_15 br_15 en vdd gnd write_driver +Xwrite_driver16 data_16 bl_16 br_16 en vdd gnd write_driver +Xwrite_driver17 data_17 bl_17 br_17 en vdd gnd write_driver +Xwrite_driver18 data_18 bl_18 br_18 en vdd gnd write_driver +Xwrite_driver19 data_19 bl_19 br_19 en vdd gnd write_driver +Xwrite_driver20 data_20 bl_20 br_20 en vdd gnd write_driver +Xwrite_driver21 data_21 bl_21 br_21 en vdd gnd write_driver +Xwrite_driver22 data_22 bl_22 br_22 en vdd gnd write_driver +Xwrite_driver23 data_23 bl_23 br_23 en vdd gnd write_driver +Xwrite_driver24 data_24 bl_24 br_24 en vdd gnd write_driver +Xwrite_driver25 data_25 bl_25 br_25 en vdd gnd write_driver +Xwrite_driver26 data_26 bl_26 br_26 en vdd gnd write_driver +Xwrite_driver27 data_27 bl_27 br_27 en vdd gnd write_driver +Xwrite_driver28 data_28 bl_28 br_28 en vdd gnd write_driver +Xwrite_driver29 data_29 bl_29 br_29 en vdd gnd write_driver +Xwrite_driver30 data_30 bl_30 br_30 en vdd gnd write_driver +Xwrite_driver31 data_31 bl_31 br_31 en vdd gnd write_driver +.ENDS write_driver_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* INPUT : en_bar +* POWER : vdd +* cols: 33 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 +Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 +Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 +Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 +Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 +Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 +Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 +Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 +Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 +Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 +Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 +Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 +Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 +Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 +Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 +Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 +Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 +Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 +Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 +Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 +Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 +Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 +Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 +Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 +Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 +Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 +Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 +Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 +Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 +Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* OUTPUT: data_2 +* INPUT : bl_2 +* INPUT : br_2 +* OUTPUT: data_3 +* INPUT : bl_3 +* INPUT : br_3 +* OUTPUT: data_4 +* INPUT : bl_4 +* INPUT : br_4 +* OUTPUT: data_5 +* INPUT : bl_5 +* INPUT : br_5 +* OUTPUT: data_6 +* INPUT : bl_6 +* INPUT : br_6 +* OUTPUT: data_7 +* INPUT : bl_7 +* INPUT : br_7 +* OUTPUT: data_8 +* INPUT : bl_8 +* INPUT : br_8 +* OUTPUT: data_9 +* INPUT : bl_9 +* INPUT : br_9 +* OUTPUT: data_10 +* INPUT : bl_10 +* INPUT : br_10 +* OUTPUT: data_11 +* INPUT : bl_11 +* INPUT : br_11 +* OUTPUT: data_12 +* INPUT : bl_12 +* INPUT : br_12 +* OUTPUT: data_13 +* INPUT : bl_13 +* INPUT : br_13 +* OUTPUT: data_14 +* INPUT : bl_14 +* INPUT : br_14 +* OUTPUT: data_15 +* INPUT : bl_15 +* INPUT : br_15 +* OUTPUT: data_16 +* INPUT : bl_16 +* INPUT : br_16 +* OUTPUT: data_17 +* INPUT : bl_17 +* INPUT : br_17 +* OUTPUT: data_18 +* INPUT : bl_18 +* INPUT : br_18 +* OUTPUT: data_19 +* INPUT : bl_19 +* INPUT : br_19 +* OUTPUT: data_20 +* INPUT : bl_20 +* INPUT : br_20 +* OUTPUT: data_21 +* INPUT : bl_21 +* INPUT : br_21 +* OUTPUT: data_22 +* INPUT : bl_22 +* INPUT : br_22 +* OUTPUT: data_23 +* INPUT : bl_23 +* INPUT : br_23 +* OUTPUT: data_24 +* INPUT : bl_24 +* INPUT : br_24 +* OUTPUT: data_25 +* INPUT : bl_25 +* INPUT : br_25 +* OUTPUT: data_26 +* INPUT : bl_26 +* INPUT : br_26 +* OUTPUT: data_27 +* INPUT : bl_27 +* INPUT : br_27 +* OUTPUT: data_28 +* INPUT : bl_28 +* INPUT : br_28 +* OUTPUT: data_29 +* INPUT : bl_29 +* INPUT : br_29 +* OUTPUT: data_30 +* INPUT : bl_30 +* INPUT : br_30 +* OUTPUT: data_31 +* INPUT : bl_31 +* INPUT : br_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 1 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp +Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp +Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp +Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp +Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp +Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp +Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp +Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp +Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp +Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp +Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp +Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp +Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp +Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp +Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp +Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp +Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp +Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp +Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp +Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp +Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp +Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp +Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp +Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp +Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp +Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp +Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp +Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp +Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp +Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp +.ENDS sense_amp_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 dout_2 bl_2 br_2 dout_3 bl_3 br_3 dout_4 bl_4 br_4 dout_5 bl_5 br_5 dout_6 bl_6 br_6 dout_7 bl_7 br_7 dout_8 bl_8 br_8 dout_9 bl_9 br_9 dout_10 bl_10 br_10 dout_11 bl_11 br_11 dout_12 bl_12 br_12 dout_13 bl_13 br_13 dout_14 bl_14 br_14 dout_15 bl_15 br_15 dout_16 bl_16 br_16 dout_17 bl_17 br_17 dout_18 bl_18 br_18 dout_19 bl_19 br_19 dout_20 bl_20 br_20 dout_21 bl_21 br_21 dout_22 bl_22 br_22 dout_23 bl_23 br_23 dout_24 bl_24 br_24 dout_25 bl_25 br_25 dout_26 bl_26 br_26 dout_27 bl_27 br_27 dout_28 bl_28 br_28 dout_29 bl_29 br_29 dout_30 bl_30 br_30 dout_31 bl_31 br_31 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 w_en vdd gnd write_driver_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p +Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +.ENDS pinv_0 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv_0 +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* INPUT : in_16 +* INPUT : in_17 +* INPUT : in_18 +* INPUT : in_19 +* INPUT : in_20 +* INPUT : in_21 +* INPUT : in_22 +* INPUT : in_23 +* INPUT : in_24 +* INPUT : in_25 +* INPUT : in_26 +* INPUT : in_27 +* INPUT : in_28 +* INPUT : in_29 +* INPUT : in_30 +* INPUT : in_31 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 32 cols: 32 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver +Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver +Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver +Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver +Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver +Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver +Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver +Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver +Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver +Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver +Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver +Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver +Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver +Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver +Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver +Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver +.ENDS wordline_driver_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3 + +.SUBCKT and3_dec A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand3_dec_nand A B C zb_int vdd gnd pnand3 +Xpand3_dec_inv zb_int Z vdd gnd pinv +.ENDS and3_dec + +.SUBCKT hierarchical_predecode3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd +*.PININFO in_0:I in_1:I in_2:I out_0:O out_1:O out_2:O out_3:O out_4:O out_5:O out_6:O out_7:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* OUTPUT: out_4 +* OUTPUT: out_5 +* OUTPUT: out_6 +* OUTPUT: out_7 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +Xpre_inv_2 in_2 inbar_2 vdd gnd pinv +XXpre3x8_and_0 inbar_0 inbar_1 inbar_2 out_0 vdd gnd and3_dec +XXpre3x8_and_1 in_0 inbar_1 inbar_2 out_1 vdd gnd and3_dec +XXpre3x8_and_2 inbar_0 in_1 inbar_2 out_2 vdd gnd and3_dec +XXpre3x8_and_3 in_0 in_1 inbar_2 out_3 vdd gnd and3_dec +XXpre3x8_and_4 inbar_0 inbar_1 in_2 out_4 vdd gnd and3_dec +XXpre3x8_and_5 in_0 inbar_1 in_2 out_5 vdd gnd and3_dec +XXpre3x8_and_6 inbar_0 in_1 in_2 out_6 vdd gnd and3_dec +XXpre3x8_and_7 in_0 in_1 in_2 out_7 vdd gnd and3_dec +.ENDS hierarchical_predecode3x8 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* OUTPUT: decode_16 +* OUTPUT: decode_17 +* OUTPUT: decode_18 +* OUTPUT: decode_19 +* OUTPUT: decode_20 +* OUTPUT: decode_21 +* OUTPUT: decode_22 +* OUTPUT: decode_23 +* OUTPUT: decode_24 +* OUTPUT: decode_25 +* OUTPUT: decode_26 +* OUTPUT: decode_27 +* OUTPUT: decode_28 +* OUTPUT: decode_29 +* OUTPUT: decode_30 +* OUTPUT: decode_31 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre3x8_0 addr_2 addr_3 addr_4 out_4 out_5 out_6 out_7 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode3x8 +XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec +XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec +XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec +XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec +XDEC_AND_16 out_0 out_8 decode_16 vdd gnd and2_dec +XDEC_AND_20 out_0 out_9 decode_20 vdd gnd and2_dec +XDEC_AND_24 out_0 out_10 decode_24 vdd gnd and2_dec +XDEC_AND_28 out_0 out_11 decode_28 vdd gnd and2_dec +XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec +XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec +XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec +XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec +XDEC_AND_17 out_1 out_8 decode_17 vdd gnd and2_dec +XDEC_AND_21 out_1 out_9 decode_21 vdd gnd and2_dec +XDEC_AND_25 out_1 out_10 decode_25 vdd gnd and2_dec +XDEC_AND_29 out_1 out_11 decode_29 vdd gnd and2_dec +XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec +XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec +XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec +XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec +XDEC_AND_18 out_2 out_8 decode_18 vdd gnd and2_dec +XDEC_AND_22 out_2 out_9 decode_22 vdd gnd and2_dec +XDEC_AND_26 out_2 out_10 decode_26 vdd gnd and2_dec +XDEC_AND_30 out_2 out_11 decode_30 vdd gnd and2_dec +XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec +XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec +XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec +XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec +XDEC_AND_19 out_3 out_8 decode_19 vdd gnd and2_dec +XDEC_AND_23 out_3 out_9 decode_23 vdd gnd and2_dec +XDEC_AND_27 out_3 out_10 decode_27 vdd gnd and2_dec +XDEC_AND_31 out_3 out_11 decode_31 vdd gnd and2_dec +.ENDS hierarchical_decoder + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 8 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv_0 +.ENDS and2_dec_0 + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: dout0_2 +* OUTPUT: dout0_3 +* OUTPUT: dout0_4 +* OUTPUT: dout0_5 +* OUTPUT: dout0_6 +* OUTPUT: dout0_7 +* OUTPUT: dout0_8 +* OUTPUT: dout0_9 +* OUTPUT: dout0_10 +* OUTPUT: dout0_11 +* OUTPUT: dout0_12 +* OUTPUT: dout0_13 +* OUTPUT: dout0_14 +* OUTPUT: dout0_15 +* OUTPUT: dout0_16 +* OUTPUT: dout0_17 +* OUTPUT: dout0_18 +* OUTPUT: dout0_19 +* OUTPUT: dout0_20 +* OUTPUT: dout0_21 +* OUTPUT: dout0_22 +* OUTPUT: dout0_23 +* OUTPUT: dout0_24 +* OUTPUT: dout0_25 +* OUTPUT: dout0_26 +* OUTPUT: dout0_27 +* OUTPUT: dout0_28 +* OUTPUT: dout0_29 +* OUTPUT: dout0_30 +* OUTPUT: dout0_31 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : din0_2 +* INPUT : din0_3 +* INPUT : din0_4 +* INPUT : din0_5 +* INPUT : din0_6 +* INPUT : din0_7 +* INPUT : din0_8 +* INPUT : din0_9 +* INPUT : din0_10 +* INPUT : din0_11 +* INPUT : din0_12 +* INPUT : din0_13 +* INPUT : din0_14 +* INPUT : din0_15 +* INPUT : din0_16 +* INPUT : din0_17 +* INPUT : din0_18 +* INPUT : din0_19 +* INPUT : din0_20 +* INPUT : din0_21 +* INPUT : din0_22 +* INPUT : din0_23 +* INPUT : din0_24 +* INPUT : din0_25 +* INPUT : din0_26 +* INPUT : din0_27 +* INPUT : din0_28 +* INPUT : din0_29 +* INPUT : din0_30 +* INPUT : din0_31 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : addr0_4 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 rbl_wl0 vdd gnd port_address +.ENDS bank + +.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 32 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff +Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff +Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff +Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff +Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff +Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff +Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff +Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff +Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff +Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff +Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff +Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff +Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff +Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff +Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff +Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff +Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff +Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff +Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff +Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff +Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff +Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff +Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff +Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff +Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff +Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff +Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff +Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff +Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff +Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff +.ENDS data_dff + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3_0 + +* spice ptx M{0} {1} p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p + +* spice ptx M{0} {1} n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p + +.SUBCKT pinv_13 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p +Mpinv_nmos Z A gnd gnd n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p +.ENDS pinv_13 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [40] +Xbuf_inv1 A Z vdd gnd pinv_13 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_1 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_1 + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_2 + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_1 +Xdff_buf_inv2 Qb Q vdd gnd pinv_2 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p + +.SUBCKT pinv_14 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p +.ENDS pinv_14 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [32] +Xbuf_inv1 A Z vdd gnd pinv_14 +.ENDS pdriver_3 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +.SUBCKT pinv_18 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_18 + +* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p + +* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_12 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p +Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +.ENDS pinv_12 + +* spice ptx M{0} {1} p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p + +* spice ptx M{0} {1} n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p +Mpinv_nmos Z A gnd gnd n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p +.ENDS pinv_11 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [3, 10] +Xbuf_inv1 A Zb1_int vdd gnd pinv_11 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_12 +.ENDS pdriver_1 + +* spice ptx M{0} {1} p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p + +* spice ptx M{0} {1} n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p +Mpinv_nmos Z A gnd gnd n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p +.ENDS pinv_10 + +* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p + +* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p +.ENDS pinv_8 + +* spice ptx M{0} {1} n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p + +* spice ptx M{0} {1} p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p +Mpinv_nmos Z A gnd gnd n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p +.ENDS pinv_9 + +.SUBCKT pinv_6 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_6 + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_7 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 2, 7, 22, 67] +Xbuf_inv1 A Zb1_int vdd gnd pinv_6 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 +Xbuf_inv6 Zb5_int Z vdd gnd pinv_10 +.ENDS pdriver_0 + +.SUBCKT pinv_15 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_15 + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +.SUBCKT pinv_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p +.ENDS pinv_3 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_3 +.ENDS pdriver + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_0 + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +.SUBCKT pinv_16 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_16 + +* spice ptx M{0} {1} n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p + +* spice ptx M{0} {1} p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p + +.SUBCKT pinv_17 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p +Mpinv_nmos Z A gnd gnd n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p +.ENDS pinv_17 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 4, 11] +Xbuf_inv1 A Zb1_int vdd gnd pinv_6 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_16 +Xbuf_inv4 Zb3_int Z vdd gnd pinv_17 +.ENDS pdriver_4 + +* Used for tiling delay chain to desired length +.SUBCKT delay_chain_segment in out vdd gnd +Xdinv0 in dout_1 vdd gnd pinv_11 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 +Xdinv1 dout_1 out vdd gnd pinv_11 +Xdload_1_0 out n_1_0 vdd gnd pinv_11 +Xdload_1_1 out n_1_1 vdd gnd pinv_11 +Xdload_1_2 out n_1_2 vdd gnd pinv_11 +Xdload_1_3 out n_1_3 vdd gnd pinv_11 +.ENDS delay_chain_segment + +.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd +Xdelay1 in out1 vdd gnd delay_chain_segment +Xdelay2 out1 out2 vdd gnd delay_chain_segment +Xdelay3 out2 out3 vdd gnd delay_chain_segment +Xdelay4 out3 out4 vdd gnd delay_chain_segment +Xdelay5 out4 out5 vdd gnd delay_chain_segment +Xdelay6 out5 out6 vdd gnd delay_chain_segment +Xdelay7 out6 out7 vdd gnd delay_chain_segment +Xdelay8 out7 out8 vdd gnd delay_chain_segment +Xdelay9 out8 out9 vdd gnd delay_chain_segment +Xdelay10 out9 out10 vdd gnd delay_chain_segment +Xdelay11 out10 out11 vdd gnd delay_chain_segment +Xdelay12 out11 out12 vdd gnd delay_chain_segment +Xdelay13 out12 out13 vdd gnd delay_chain_segment +Xdelay14 out13 out14 vdd gnd delay_chain_segment +Xdelay15 out14 out15 vdd gnd delay_chain_segment +Xdelay16 out15 out16 vdd gnd delay_chain_segment +.ENDS multi_delay_chain + +.SUBCKT glitch_generator in glitch1_bar glitch2_bar glitch3_bar vdd gnd +*.PININFO in:I glitch1_bar:O glitch2_bar:O glitch3_bar:O vdd:B gnd:B +Xmulti_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain +Xinv_g1 out6 g1_end vdd gnd pinv_11 +Xinv_g2 out7 g2_end vdd gnd pinv_11 +Xinv_g3 out16 g3_end vdd gnd pinv_11 +Xnand2_g1 out2 g1_end glitch1_bar vdd gnd pnand2 +Xnand2_g2 in g2_end glitch2_bar vdd gnd pnand2 +Xnand2_g3 out6 g3_end glitch3_bar vdd gnd pnand2 +.ENDS glitch_generator + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl (NO LONGER USED) +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +* is cs_buf needed on larger memories? +Xbuf_cs cs cs_buf vdd gnd pdriver_0 +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xglitch_generator gated_clk_buf glitch1_bar glitch2_bar glitch3_bar vdd gnd glitch_generator +Xinv_g3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 +Xand_s_en we_bar gated_clk_bar glitch3_bar s_en vdd gnd pand3 +Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 +Xand_wl_en cs_buf glitch2_bar wl_en vdd gnd pand2 +Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT sram_32_32_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] vdd gnd +*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : din0[2] +* INPUT : din0[3] +* INPUT : din0[4] +* INPUT : din0[5] +* INPUT : din0[6] +* INPUT : din0[7] +* INPUT : din0[8] +* INPUT : din0[9] +* INPUT : din0[10] +* INPUT : din0[11] +* INPUT : din0[12] +* INPUT : din0[13] +* INPUT : din0[14] +* INPUT : din0[15] +* INPUT : din0[16] +* INPUT : din0[17] +* INPUT : din0[18] +* INPUT : din0[19] +* INPUT : din0[20] +* INPUT : din0[21] +* INPUT : din0[22] +* INPUT : din0[23] +* INPUT : din0[24] +* INPUT : din0[25] +* INPUT : din0[26] +* INPUT : din0[27] +* INPUT : din0[28] +* INPUT : din0[29] +* INPUT : din0[30] +* INPUT : din0[31] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : addr0[4] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* OUTPUT: dout0[2] +* OUTPUT: dout0[3] +* OUTPUT: dout0[4] +* OUTPUT: dout0[5] +* OUTPUT: dout0[6] +* OUTPUT: dout0[7] +* OUTPUT: dout0[8] +* OUTPUT: dout0[9] +* OUTPUT: dout0[10] +* OUTPUT: dout0[11] +* OUTPUT: dout0[12] +* OUTPUT: dout0[13] +* OUTPUT: dout0[14] +* OUTPUT: dout0[15] +* OUTPUT: dout0[16] +* OUTPUT: dout0[17] +* OUTPUT: dout0[18] +* OUTPUT: dout0[19] +* OUTPUT: dout0[20] +* OUTPUT: dout0[21] +* OUTPUT: dout0[22] +* OUTPUT: dout0[23] +* OUTPUT: dout0[24] +* OUTPUT: dout0[25] +* OUTPUT: dout0[26] +* OUTPUT: dout0[27] +* OUTPUT: dout0[28] +* OUTPUT: dout0[29] +* OUTPUT: dout0[30] +* OUTPUT: dout0[31] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 a0_0 a0_1 a0_2 a0_3 a0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] a0_0 a0_1 a0_2 a0_3 a0_4 clk_buf0 vdd gnd row_addr_dff +Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 clk_buf0 vdd gnd data_dff +.ENDS sram_32_32_scn4m_subm diff --git a/32x32/sram_32_32_scn4m_subm.html b/32x32/sram_32_32_scn4m_subm.html new file mode 100644 index 00000000..f3040ca0 --- /dev/null +++ b/32x32/sram_32_32_scn4m_subm.html @@ -0,0 +1,35 @@ + + +VLSIDAOpenRAM

sram_32_32_scn4m_subm.html

Compiled at: 2022-01-19

DRC errors: skipped

LVS errors: skipped

Git commit id: 06d391b3e365127628434b98044035232615f4b0

Ports and Configuration

TypeValue
WORD_SIZE32
NUM_WORDS32
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0
+

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)169MHz
+

Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[31:0] setup rising0.0090.009ns
din0[31:0] setup falling0.0090.009ns
din0[31:0] hold rising0.0010.001ns
din0[31:0] hold falling0.0010.001ns
dout0[31:0] cell rise1.51.591ns
dout0[31:0] cell fall1.51.591ns
dout0[31:0] rise transition0.0060.015ns
dout0[31:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[4:0] setup rising0.0090.009ns
addr0[4:0] setup falling0.0090.009ns
addr0[4:0] hold rising0.0010.001ns
addr0[4:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns
+

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising6.1899mW
!csb0 & clk0 & !web0Read Falling6.1899mW
!csb0 & !clk0 & web0Write Rising6.1899mW
!csb0 & !clk0 & web0Write Falling6.1899mW
csb0leakage0.001294mW
+

Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib
+

Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_32_32_scn4m_subm.html
.libSynthesis modelssram_32_32_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_32_32_scn4m_subm.log
.pyOpenRAM configuration filesram_32_32_scn4m_subm.py
.spSPICE netlistssram_32_32_scn4m_subm.sp
.vVerilog simulation modelssram_32_32_scn4m_subm.v
diff --git a/32x32/sram_32_32_scn4m_subm.lvs.sp b/32x32/sram_32_32_scn4m_subm.lvs.sp new file mode 100644 index 00000000..de7b0f17 --- /dev/null +++ b/32x32/sram_32_32_scn4m_subm.lvs.sp @@ -0,0 +1,3599 @@ +************************************************** +* OpenRAM generated memory. +* Words: 32 +* Data bits: 32 +* Banks: 1 +* Column mux: 1:1 +* Trimmed: False +* LVS: True +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 dout_0 dout_1 dout_2 dout_3 dout_4 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 5 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff +.ENDS row_addr_dff + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* POWER : vdd +* GROUND: gnd +* rows: 32 cols: 32 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw +.ENDS bitcell_array + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw +Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw +Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw +Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw +Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw +Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw +Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw +Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw +Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw +Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw +Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw +Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw +Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw +Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw +Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw +Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw +Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 en vdd gnd +*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* INPUT : data_2 +* INPUT : data_3 +* INPUT : data_4 +* INPUT : data_5 +* INPUT : data_6 +* INPUT : data_7 +* INPUT : data_8 +* INPUT : data_9 +* INPUT : data_10 +* INPUT : data_11 +* INPUT : data_12 +* INPUT : data_13 +* INPUT : data_14 +* INPUT : data_15 +* INPUT : data_16 +* INPUT : data_17 +* INPUT : data_18 +* INPUT : data_19 +* INPUT : data_20 +* INPUT : data_21 +* INPUT : data_22 +* INPUT : data_23 +* INPUT : data_24 +* INPUT : data_25 +* INPUT : data_26 +* INPUT : data_27 +* INPUT : data_28 +* INPUT : data_29 +* INPUT : data_30 +* INPUT : data_31 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 32 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver +Xwrite_driver2 data_2 bl_2 br_2 en vdd gnd write_driver +Xwrite_driver3 data_3 bl_3 br_3 en vdd gnd write_driver +Xwrite_driver4 data_4 bl_4 br_4 en vdd gnd write_driver +Xwrite_driver5 data_5 bl_5 br_5 en vdd gnd write_driver +Xwrite_driver6 data_6 bl_6 br_6 en vdd gnd write_driver +Xwrite_driver7 data_7 bl_7 br_7 en vdd gnd write_driver +Xwrite_driver8 data_8 bl_8 br_8 en vdd gnd write_driver +Xwrite_driver9 data_9 bl_9 br_9 en vdd gnd write_driver +Xwrite_driver10 data_10 bl_10 br_10 en vdd gnd write_driver +Xwrite_driver11 data_11 bl_11 br_11 en vdd gnd write_driver +Xwrite_driver12 data_12 bl_12 br_12 en vdd gnd write_driver +Xwrite_driver13 data_13 bl_13 br_13 en vdd gnd write_driver +Xwrite_driver14 data_14 bl_14 br_14 en vdd gnd write_driver +Xwrite_driver15 data_15 bl_15 br_15 en vdd gnd write_driver +Xwrite_driver16 data_16 bl_16 br_16 en vdd gnd write_driver +Xwrite_driver17 data_17 bl_17 br_17 en vdd gnd write_driver +Xwrite_driver18 data_18 bl_18 br_18 en vdd gnd write_driver +Xwrite_driver19 data_19 bl_19 br_19 en vdd gnd write_driver +Xwrite_driver20 data_20 bl_20 br_20 en vdd gnd write_driver +Xwrite_driver21 data_21 bl_21 br_21 en vdd gnd write_driver +Xwrite_driver22 data_22 bl_22 br_22 en vdd gnd write_driver +Xwrite_driver23 data_23 bl_23 br_23 en vdd gnd write_driver +Xwrite_driver24 data_24 bl_24 br_24 en vdd gnd write_driver +Xwrite_driver25 data_25 bl_25 br_25 en vdd gnd write_driver +Xwrite_driver26 data_26 bl_26 br_26 en vdd gnd write_driver +Xwrite_driver27 data_27 bl_27 br_27 en vdd gnd write_driver +Xwrite_driver28 data_28 bl_28 br_28 en vdd gnd write_driver +Xwrite_driver29 data_29 bl_29 br_29 en vdd gnd write_driver +Xwrite_driver30 data_30 bl_30 br_30 en vdd gnd write_driver +Xwrite_driver31 data_31 bl_31 br_31 en vdd gnd write_driver +.ENDS write_driver_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* INPUT : en_bar +* POWER : vdd +* cols: 33 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 +Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 +Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 +Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 +Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 +Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 +Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 +Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 +Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 +Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 +Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 +Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 +Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 +Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 +Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 +Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 +Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 +Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 +Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 +Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 +Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 +Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 +Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 +Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 +Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 +Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 +Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 +Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 +Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 +Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* OUTPUT: data_2 +* INPUT : bl_2 +* INPUT : br_2 +* OUTPUT: data_3 +* INPUT : bl_3 +* INPUT : br_3 +* OUTPUT: data_4 +* INPUT : bl_4 +* INPUT : br_4 +* OUTPUT: data_5 +* INPUT : bl_5 +* INPUT : br_5 +* OUTPUT: data_6 +* INPUT : bl_6 +* INPUT : br_6 +* OUTPUT: data_7 +* INPUT : bl_7 +* INPUT : br_7 +* OUTPUT: data_8 +* INPUT : bl_8 +* INPUT : br_8 +* OUTPUT: data_9 +* INPUT : bl_9 +* INPUT : br_9 +* OUTPUT: data_10 +* INPUT : bl_10 +* INPUT : br_10 +* OUTPUT: data_11 +* INPUT : bl_11 +* INPUT : br_11 +* OUTPUT: data_12 +* INPUT : bl_12 +* INPUT : br_12 +* OUTPUT: data_13 +* INPUT : bl_13 +* INPUT : br_13 +* OUTPUT: data_14 +* INPUT : bl_14 +* INPUT : br_14 +* OUTPUT: data_15 +* INPUT : bl_15 +* INPUT : br_15 +* OUTPUT: data_16 +* INPUT : bl_16 +* INPUT : br_16 +* OUTPUT: data_17 +* INPUT : bl_17 +* INPUT : br_17 +* OUTPUT: data_18 +* INPUT : bl_18 +* INPUT : br_18 +* OUTPUT: data_19 +* INPUT : bl_19 +* INPUT : br_19 +* OUTPUT: data_20 +* INPUT : bl_20 +* INPUT : br_20 +* OUTPUT: data_21 +* INPUT : bl_21 +* INPUT : br_21 +* OUTPUT: data_22 +* INPUT : bl_22 +* INPUT : br_22 +* OUTPUT: data_23 +* INPUT : bl_23 +* INPUT : br_23 +* OUTPUT: data_24 +* INPUT : bl_24 +* INPUT : br_24 +* OUTPUT: data_25 +* INPUT : bl_25 +* INPUT : br_25 +* OUTPUT: data_26 +* INPUT : bl_26 +* INPUT : br_26 +* OUTPUT: data_27 +* INPUT : bl_27 +* INPUT : br_27 +* OUTPUT: data_28 +* INPUT : bl_28 +* INPUT : br_28 +* OUTPUT: data_29 +* INPUT : bl_29 +* INPUT : br_29 +* OUTPUT: data_30 +* INPUT : bl_30 +* INPUT : br_30 +* OUTPUT: data_31 +* INPUT : bl_31 +* INPUT : br_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 1 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp +Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp +Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp +Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp +Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp +Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp +Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp +Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp +Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp +Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp +Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp +Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp +Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp +Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp +Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp +Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp +Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp +Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp +Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp +Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp +Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp +Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp +Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp +Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp +Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp +Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp +Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp +Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp +Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp +Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp +.ENDS sense_amp_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 dout_2 bl_2 br_2 dout_3 bl_3 br_3 dout_4 bl_4 br_4 dout_5 bl_5 br_5 dout_6 bl_6 br_6 dout_7 bl_7 br_7 dout_8 bl_8 br_8 dout_9 bl_9 br_9 dout_10 bl_10 br_10 dout_11 bl_11 br_11 dout_12 bl_12 br_12 dout_13 bl_13 br_13 dout_14 bl_14 br_14 dout_15 bl_15 br_15 dout_16 bl_16 br_16 dout_17 bl_17 br_17 dout_18 bl_18 br_18 dout_19 bl_19 br_19 dout_20 bl_20 br_20 dout_21 bl_21 br_21 dout_22 bl_22 br_22 dout_23 bl_23 br_23 dout_24 bl_24 br_24 dout_25 bl_25 br_25 dout_26 bl_26 br_26 dout_27 bl_27 br_27 dout_28 bl_28 br_28 dout_29 bl_29 br_29 dout_30 bl_30 br_30 dout_31 bl_31 br_31 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 w_en vdd gnd write_driver_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u +.ENDS pinv_0 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv_0 +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* INPUT : in_16 +* INPUT : in_17 +* INPUT : in_18 +* INPUT : in_19 +* INPUT : in_20 +* INPUT : in_21 +* INPUT : in_22 +* INPUT : in_23 +* INPUT : in_24 +* INPUT : in_25 +* INPUT : in_26 +* INPUT : in_27 +* INPUT : in_28 +* INPUT : in_29 +* INPUT : in_30 +* INPUT : in_31 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 32 cols: 32 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver +Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver +Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver +Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver +Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver +Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver +Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver +Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver +Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver +Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver +Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver +Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver +Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver +Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver +Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver +Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver +.ENDS wordline_driver_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand3 + +.SUBCKT and3_dec A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand3_dec_nand A B C zb_int vdd gnd pnand3 +Xpand3_dec_inv zb_int Z vdd gnd pinv +.ENDS and3_dec + +.SUBCKT hierarchical_predecode3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd +*.PININFO in_0:I in_1:I in_2:I out_0:O out_1:O out_2:O out_3:O out_4:O out_5:O out_6:O out_7:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* OUTPUT: out_4 +* OUTPUT: out_5 +* OUTPUT: out_6 +* OUTPUT: out_7 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +Xpre_inv_2 in_2 inbar_2 vdd gnd pinv +XXpre3x8_and_0 inbar_0 inbar_1 inbar_2 out_0 vdd gnd and3_dec +XXpre3x8_and_1 in_0 inbar_1 inbar_2 out_1 vdd gnd and3_dec +XXpre3x8_and_2 inbar_0 in_1 inbar_2 out_2 vdd gnd and3_dec +XXpre3x8_and_3 in_0 in_1 inbar_2 out_3 vdd gnd and3_dec +XXpre3x8_and_4 inbar_0 inbar_1 in_2 out_4 vdd gnd and3_dec +XXpre3x8_and_5 in_0 inbar_1 in_2 out_5 vdd gnd and3_dec +XXpre3x8_and_6 inbar_0 in_1 in_2 out_6 vdd gnd and3_dec +XXpre3x8_and_7 in_0 in_1 in_2 out_7 vdd gnd and3_dec +.ENDS hierarchical_predecode3x8 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* OUTPUT: decode_16 +* OUTPUT: decode_17 +* OUTPUT: decode_18 +* OUTPUT: decode_19 +* OUTPUT: decode_20 +* OUTPUT: decode_21 +* OUTPUT: decode_22 +* OUTPUT: decode_23 +* OUTPUT: decode_24 +* OUTPUT: decode_25 +* OUTPUT: decode_26 +* OUTPUT: decode_27 +* OUTPUT: decode_28 +* OUTPUT: decode_29 +* OUTPUT: decode_30 +* OUTPUT: decode_31 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre3x8_0 addr_2 addr_3 addr_4 out_4 out_5 out_6 out_7 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode3x8 +XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec +XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec +XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec +XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec +XDEC_AND_16 out_0 out_8 decode_16 vdd gnd and2_dec +XDEC_AND_20 out_0 out_9 decode_20 vdd gnd and2_dec +XDEC_AND_24 out_0 out_10 decode_24 vdd gnd and2_dec +XDEC_AND_28 out_0 out_11 decode_28 vdd gnd and2_dec +XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec +XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec +XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec +XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec +XDEC_AND_17 out_1 out_8 decode_17 vdd gnd and2_dec +XDEC_AND_21 out_1 out_9 decode_21 vdd gnd and2_dec +XDEC_AND_25 out_1 out_10 decode_25 vdd gnd and2_dec +XDEC_AND_29 out_1 out_11 decode_29 vdd gnd and2_dec +XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec +XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec +XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec +XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec +XDEC_AND_18 out_2 out_8 decode_18 vdd gnd and2_dec +XDEC_AND_22 out_2 out_9 decode_22 vdd gnd and2_dec +XDEC_AND_26 out_2 out_10 decode_26 vdd gnd and2_dec +XDEC_AND_30 out_2 out_11 decode_30 vdd gnd and2_dec +XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec +XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec +XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec +XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec +XDEC_AND_19 out_3 out_8 decode_19 vdd gnd and2_dec +XDEC_AND_23 out_3 out_9 decode_23 vdd gnd and2_dec +XDEC_AND_27 out_3 out_10 decode_27 vdd gnd and2_dec +XDEC_AND_31 out_3 out_11 decode_31 vdd gnd and2_dec +.ENDS hierarchical_decoder + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 8 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv_0 +.ENDS and2_dec_0 + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: dout0_2 +* OUTPUT: dout0_3 +* OUTPUT: dout0_4 +* OUTPUT: dout0_5 +* OUTPUT: dout0_6 +* OUTPUT: dout0_7 +* OUTPUT: dout0_8 +* OUTPUT: dout0_9 +* OUTPUT: dout0_10 +* OUTPUT: dout0_11 +* OUTPUT: dout0_12 +* OUTPUT: dout0_13 +* OUTPUT: dout0_14 +* OUTPUT: dout0_15 +* OUTPUT: dout0_16 +* OUTPUT: dout0_17 +* OUTPUT: dout0_18 +* OUTPUT: dout0_19 +* OUTPUT: dout0_20 +* OUTPUT: dout0_21 +* OUTPUT: dout0_22 +* OUTPUT: dout0_23 +* OUTPUT: dout0_24 +* OUTPUT: dout0_25 +* OUTPUT: dout0_26 +* OUTPUT: dout0_27 +* OUTPUT: dout0_28 +* OUTPUT: dout0_29 +* OUTPUT: dout0_30 +* OUTPUT: dout0_31 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : din0_2 +* INPUT : din0_3 +* INPUT : din0_4 +* INPUT : din0_5 +* INPUT : din0_6 +* INPUT : din0_7 +* INPUT : din0_8 +* INPUT : din0_9 +* INPUT : din0_10 +* INPUT : din0_11 +* INPUT : din0_12 +* INPUT : din0_13 +* INPUT : din0_14 +* INPUT : din0_15 +* INPUT : din0_16 +* INPUT : din0_17 +* INPUT : din0_18 +* INPUT : din0_19 +* INPUT : din0_20 +* INPUT : din0_21 +* INPUT : din0_22 +* INPUT : din0_23 +* INPUT : din0_24 +* INPUT : din0_25 +* INPUT : din0_26 +* INPUT : din0_27 +* INPUT : din0_28 +* INPUT : din0_29 +* INPUT : din0_30 +* INPUT : din0_31 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : addr0_4 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 rbl_wl0 vdd gnd port_address +.ENDS bank + +.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 32 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff +Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff +Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff +Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff +Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff +Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff +Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff +Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff +Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff +Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff +Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff +Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff +Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff +Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff +Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff +Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff +Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff +Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff +Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff +Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff +Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff +Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff +Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff +Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff +Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff +Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff +Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff +Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff +Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff +Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff +.ENDS data_dff + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand3_0 + +* spice ptx M{0} {1} p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p + +* spice ptx M{0} {1} n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p + +.SUBCKT pinv_13 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=64.0u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=32.0u l=0.4u +.ENDS pinv_13 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [40] +Xbuf_inv1 A Z vdd gnd pinv_13 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2_1 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pinv_1 + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u +.ENDS pinv_2 + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_1 +Xdff_buf_inv2 Qb Q vdd gnd pinv_2 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p + +.SUBCKT pinv_14 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u +.ENDS pinv_14 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [32] +Xbuf_inv1 A Z vdd gnd pinv_14 +.ENDS pdriver_3 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +.SUBCKT pinv_18 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_18 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_18 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_18 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_18 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_18 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_18 +Xdinv1 dout_1 dout_2 vdd gnd pinv_18 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_18 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_18 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_18 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_18 +Xdinv2 dout_2 dout_3 vdd gnd pinv_18 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_18 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_18 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_18 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_18 +Xdinv3 dout_3 dout_4 vdd gnd pinv_18 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_18 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_18 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_18 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_18 +Xdinv4 dout_4 dout_5 vdd gnd pinv_18 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_18 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_18 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_18 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_18 +Xdinv5 dout_5 dout_6 vdd gnd pinv_18 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_18 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_18 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_18 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_18 +Xdinv6 dout_6 dout_7 vdd gnd pinv_18 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_18 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_18 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_18 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_18 +Xdinv7 dout_7 dout_8 vdd gnd pinv_18 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_18 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_18 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_18 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_18 +Xdinv8 dout_8 out vdd gnd pinv_18 +Xdload_8_0 out n_8_0 vdd gnd pinv_18 +Xdload_8_1 out n_8_1 vdd gnd pinv_18 +Xdload_8_2 out n_8_2 vdd gnd pinv_18 +Xdload_8_3 out n_8_3 vdd gnd pinv_18 +.ENDS delay_chain + +* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p + +* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_12 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u +.ENDS pinv_12 + +* spice ptx M{0} {1} p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p + +* spice ptx M{0} {1} n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=4.800000000000001u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=2.4000000000000004u l=0.4u +.ENDS pinv_11 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [3, 10] +Xbuf_inv1 A Zb1_int vdd gnd pinv_11 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_12 +.ENDS pdriver_1 + +* spice ptx M{0} {1} p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p + +* spice ptx M{0} {1} n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=107.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=53.6u l=0.4u +.ENDS pinv_10 + +* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p + +* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u +.ENDS pinv_8 + +* spice ptx M{0} {1} n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p + +* spice ptx M{0} {1} p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=35.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=17.6u l=0.4u +.ENDS pinv_9 + +.SUBCKT pinv_6 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_6 + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pinv_7 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 2, 7, 22, 67] +Xbuf_inv1 A Zb1_int vdd gnd pinv_6 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 +Xbuf_inv6 Zb5_int Z vdd gnd pinv_10 +.ENDS pdriver_0 + +.SUBCKT pinv_15 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u +.ENDS pinv_15 + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +.SUBCKT pinv_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u +.ENDS pinv_3 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_3 +.ENDS pdriver + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u +.ENDS pnand2_0 + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +.SUBCKT pinv_16 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u +.ENDS pinv_16 + +* spice ptx M{0} {1} n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p + +* spice ptx M{0} {1} p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p + +.SUBCKT pinv_17 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=17.6u l=0.4u +Mpinv_nmos Z A gnd gnd n m=1 w=8.8u l=0.4u +.ENDS pinv_17 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 4, 11] +Xbuf_inv1 A Zb1_int vdd gnd pinv_6 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_16 +Xbuf_inv4 Zb3_int Z vdd gnd pinv_17 +.ENDS pdriver_4 + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 32 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_15 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 +Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_15 +Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 +Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 +Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain +Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 +Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT sram_32_32_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] vdd gnd +*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : din0[2] +* INPUT : din0[3] +* INPUT : din0[4] +* INPUT : din0[5] +* INPUT : din0[6] +* INPUT : din0[7] +* INPUT : din0[8] +* INPUT : din0[9] +* INPUT : din0[10] +* INPUT : din0[11] +* INPUT : din0[12] +* INPUT : din0[13] +* INPUT : din0[14] +* INPUT : din0[15] +* INPUT : din0[16] +* INPUT : din0[17] +* INPUT : din0[18] +* INPUT : din0[19] +* INPUT : din0[20] +* INPUT : din0[21] +* INPUT : din0[22] +* INPUT : din0[23] +* INPUT : din0[24] +* INPUT : din0[25] +* INPUT : din0[26] +* INPUT : din0[27] +* INPUT : din0[28] +* INPUT : din0[29] +* INPUT : din0[30] +* INPUT : din0[31] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : addr0[4] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* OUTPUT: dout0[2] +* OUTPUT: dout0[3] +* OUTPUT: dout0[4] +* OUTPUT: dout0[5] +* OUTPUT: dout0[6] +* OUTPUT: dout0[7] +* OUTPUT: dout0[8] +* OUTPUT: dout0[9] +* OUTPUT: dout0[10] +* OUTPUT: dout0[11] +* OUTPUT: dout0[12] +* OUTPUT: dout0[13] +* OUTPUT: dout0[14] +* OUTPUT: dout0[15] +* OUTPUT: dout0[16] +* OUTPUT: dout0[17] +* OUTPUT: dout0[18] +* OUTPUT: dout0[19] +* OUTPUT: dout0[20] +* OUTPUT: dout0[21] +* OUTPUT: dout0[22] +* OUTPUT: dout0[23] +* OUTPUT: dout0[24] +* OUTPUT: dout0[25] +* OUTPUT: dout0[26] +* OUTPUT: dout0[27] +* OUTPUT: dout0[28] +* OUTPUT: dout0[29] +* OUTPUT: dout0[30] +* OUTPUT: dout0[31] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 a0_0 a0_1 a0_2 a0_3 a0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] a0_0 a0_1 a0_2 a0_3 a0_4 clk_buf0 vdd gnd row_addr_dff +Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 clk_buf0 vdd gnd data_dff +.ENDS sram_32_32_scn4m_subm diff --git a/32x32/sram_32_32_scn4m_subm.sp b/32x32/sram_32_32_scn4m_subm.sp new file mode 100644 index 00000000..06c6d8fb --- /dev/null +++ b/32x32/sram_32_32_scn4m_subm.sp @@ -0,0 +1,3599 @@ +************************************************** +* OpenRAM generated memory. +* Words: 32 +* Data bits: 32 +* Banks: 1 +* Column mux: 1:1 +* Trimmed: False +* LVS: False +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 dout_0 dout_1 dout_2 dout_3 dout_4 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 5 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff +.ENDS row_addr_dff + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* POWER : vdd +* GROUND: gnd +* rows: 32 cols: 32 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw +.ENDS bitcell_array + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw +Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw +Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw +Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw +Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw +Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw +Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw +Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw +Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw +Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw +Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw +Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw +Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw +Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw +Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw +Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw +Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 en vdd gnd +*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* INPUT : data_2 +* INPUT : data_3 +* INPUT : data_4 +* INPUT : data_5 +* INPUT : data_6 +* INPUT : data_7 +* INPUT : data_8 +* INPUT : data_9 +* INPUT : data_10 +* INPUT : data_11 +* INPUT : data_12 +* INPUT : data_13 +* INPUT : data_14 +* INPUT : data_15 +* INPUT : data_16 +* INPUT : data_17 +* INPUT : data_18 +* INPUT : data_19 +* INPUT : data_20 +* INPUT : data_21 +* INPUT : data_22 +* INPUT : data_23 +* INPUT : data_24 +* INPUT : data_25 +* INPUT : data_26 +* INPUT : data_27 +* INPUT : data_28 +* INPUT : data_29 +* INPUT : data_30 +* INPUT : data_31 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 32 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver +Xwrite_driver2 data_2 bl_2 br_2 en vdd gnd write_driver +Xwrite_driver3 data_3 bl_3 br_3 en vdd gnd write_driver +Xwrite_driver4 data_4 bl_4 br_4 en vdd gnd write_driver +Xwrite_driver5 data_5 bl_5 br_5 en vdd gnd write_driver +Xwrite_driver6 data_6 bl_6 br_6 en vdd gnd write_driver +Xwrite_driver7 data_7 bl_7 br_7 en vdd gnd write_driver +Xwrite_driver8 data_8 bl_8 br_8 en vdd gnd write_driver +Xwrite_driver9 data_9 bl_9 br_9 en vdd gnd write_driver +Xwrite_driver10 data_10 bl_10 br_10 en vdd gnd write_driver +Xwrite_driver11 data_11 bl_11 br_11 en vdd gnd write_driver +Xwrite_driver12 data_12 bl_12 br_12 en vdd gnd write_driver +Xwrite_driver13 data_13 bl_13 br_13 en vdd gnd write_driver +Xwrite_driver14 data_14 bl_14 br_14 en vdd gnd write_driver +Xwrite_driver15 data_15 bl_15 br_15 en vdd gnd write_driver +Xwrite_driver16 data_16 bl_16 br_16 en vdd gnd write_driver +Xwrite_driver17 data_17 bl_17 br_17 en vdd gnd write_driver +Xwrite_driver18 data_18 bl_18 br_18 en vdd gnd write_driver +Xwrite_driver19 data_19 bl_19 br_19 en vdd gnd write_driver +Xwrite_driver20 data_20 bl_20 br_20 en vdd gnd write_driver +Xwrite_driver21 data_21 bl_21 br_21 en vdd gnd write_driver +Xwrite_driver22 data_22 bl_22 br_22 en vdd gnd write_driver +Xwrite_driver23 data_23 bl_23 br_23 en vdd gnd write_driver +Xwrite_driver24 data_24 bl_24 br_24 en vdd gnd write_driver +Xwrite_driver25 data_25 bl_25 br_25 en vdd gnd write_driver +Xwrite_driver26 data_26 bl_26 br_26 en vdd gnd write_driver +Xwrite_driver27 data_27 bl_27 br_27 en vdd gnd write_driver +Xwrite_driver28 data_28 bl_28 br_28 en vdd gnd write_driver +Xwrite_driver29 data_29 bl_29 br_29 en vdd gnd write_driver +Xwrite_driver30 data_30 bl_30 br_30 en vdd gnd write_driver +Xwrite_driver31 data_31 bl_31 br_31 en vdd gnd write_driver +.ENDS write_driver_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* INPUT : en_bar +* POWER : vdd +* cols: 33 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 +Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 +Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 +Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 +Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 +Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 +Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 +Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 +Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 +Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 +Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 +Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 +Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 +Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 +Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 +Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 +Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 +Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 +Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 +Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 +Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 +Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 +Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 +Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 +Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 +Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 +Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 +Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 +Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 +Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* OUTPUT: data_2 +* INPUT : bl_2 +* INPUT : br_2 +* OUTPUT: data_3 +* INPUT : bl_3 +* INPUT : br_3 +* OUTPUT: data_4 +* INPUT : bl_4 +* INPUT : br_4 +* OUTPUT: data_5 +* INPUT : bl_5 +* INPUT : br_5 +* OUTPUT: data_6 +* INPUT : bl_6 +* INPUT : br_6 +* OUTPUT: data_7 +* INPUT : bl_7 +* INPUT : br_7 +* OUTPUT: data_8 +* INPUT : bl_8 +* INPUT : br_8 +* OUTPUT: data_9 +* INPUT : bl_9 +* INPUT : br_9 +* OUTPUT: data_10 +* INPUT : bl_10 +* INPUT : br_10 +* OUTPUT: data_11 +* INPUT : bl_11 +* INPUT : br_11 +* OUTPUT: data_12 +* INPUT : bl_12 +* INPUT : br_12 +* OUTPUT: data_13 +* INPUT : bl_13 +* INPUT : br_13 +* OUTPUT: data_14 +* INPUT : bl_14 +* INPUT : br_14 +* OUTPUT: data_15 +* INPUT : bl_15 +* INPUT : br_15 +* OUTPUT: data_16 +* INPUT : bl_16 +* INPUT : br_16 +* OUTPUT: data_17 +* INPUT : bl_17 +* INPUT : br_17 +* OUTPUT: data_18 +* INPUT : bl_18 +* INPUT : br_18 +* OUTPUT: data_19 +* INPUT : bl_19 +* INPUT : br_19 +* OUTPUT: data_20 +* INPUT : bl_20 +* INPUT : br_20 +* OUTPUT: data_21 +* INPUT : bl_21 +* INPUT : br_21 +* OUTPUT: data_22 +* INPUT : bl_22 +* INPUT : br_22 +* OUTPUT: data_23 +* INPUT : bl_23 +* INPUT : br_23 +* OUTPUT: data_24 +* INPUT : bl_24 +* INPUT : br_24 +* OUTPUT: data_25 +* INPUT : bl_25 +* INPUT : br_25 +* OUTPUT: data_26 +* INPUT : bl_26 +* INPUT : br_26 +* OUTPUT: data_27 +* INPUT : bl_27 +* INPUT : br_27 +* OUTPUT: data_28 +* INPUT : bl_28 +* INPUT : br_28 +* OUTPUT: data_29 +* INPUT : bl_29 +* INPUT : br_29 +* OUTPUT: data_30 +* INPUT : bl_30 +* INPUT : br_30 +* OUTPUT: data_31 +* INPUT : bl_31 +* INPUT : br_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 1 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp +Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp +Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp +Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp +Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp +Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp +Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp +Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp +Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp +Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp +Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp +Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp +Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp +Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp +Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp +Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp +Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp +Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp +Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp +Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp +Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp +Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp +Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp +Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp +Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp +Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp +Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp +Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp +Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp +Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp +.ENDS sense_amp_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 dout_2 bl_2 br_2 dout_3 bl_3 br_3 dout_4 bl_4 br_4 dout_5 bl_5 br_5 dout_6 bl_6 br_6 dout_7 bl_7 br_7 dout_8 bl_8 br_8 dout_9 bl_9 br_9 dout_10 bl_10 br_10 dout_11 bl_11 br_11 dout_12 bl_12 br_12 dout_13 bl_13 br_13 dout_14 bl_14 br_14 dout_15 bl_15 br_15 dout_16 bl_16 br_16 dout_17 bl_17 br_17 dout_18 bl_18 br_18 dout_19 bl_19 br_19 dout_20 bl_20 br_20 dout_21 bl_21 br_21 dout_22 bl_22 br_22 dout_23 bl_23 br_23 dout_24 bl_24 br_24 dout_25 bl_25 br_25 dout_26 bl_26 br_26 dout_27 bl_27 br_27 dout_28 bl_28 br_28 dout_29 bl_29 br_29 dout_30 bl_30 br_30 dout_31 bl_31 br_31 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 w_en vdd gnd write_driver_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p +Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +.ENDS pinv_0 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv_0 +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* INPUT : in_16 +* INPUT : in_17 +* INPUT : in_18 +* INPUT : in_19 +* INPUT : in_20 +* INPUT : in_21 +* INPUT : in_22 +* INPUT : in_23 +* INPUT : in_24 +* INPUT : in_25 +* INPUT : in_26 +* INPUT : in_27 +* INPUT : in_28 +* INPUT : in_29 +* INPUT : in_30 +* INPUT : in_31 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 32 cols: 32 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver +Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver +Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver +Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver +Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver +Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver +Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver +Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver +Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver +Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver +Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver +Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver +Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver +Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver +Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver +Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver +.ENDS wordline_driver_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3 + +.SUBCKT and3_dec A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand3_dec_nand A B C zb_int vdd gnd pnand3 +Xpand3_dec_inv zb_int Z vdd gnd pinv +.ENDS and3_dec + +.SUBCKT hierarchical_predecode3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd +*.PININFO in_0:I in_1:I in_2:I out_0:O out_1:O out_2:O out_3:O out_4:O out_5:O out_6:O out_7:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* OUTPUT: out_4 +* OUTPUT: out_5 +* OUTPUT: out_6 +* OUTPUT: out_7 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +Xpre_inv_2 in_2 inbar_2 vdd gnd pinv +XXpre3x8_and_0 inbar_0 inbar_1 inbar_2 out_0 vdd gnd and3_dec +XXpre3x8_and_1 in_0 inbar_1 inbar_2 out_1 vdd gnd and3_dec +XXpre3x8_and_2 inbar_0 in_1 inbar_2 out_2 vdd gnd and3_dec +XXpre3x8_and_3 in_0 in_1 inbar_2 out_3 vdd gnd and3_dec +XXpre3x8_and_4 inbar_0 inbar_1 in_2 out_4 vdd gnd and3_dec +XXpre3x8_and_5 in_0 inbar_1 in_2 out_5 vdd gnd and3_dec +XXpre3x8_and_6 inbar_0 in_1 in_2 out_6 vdd gnd and3_dec +XXpre3x8_and_7 in_0 in_1 in_2 out_7 vdd gnd and3_dec +.ENDS hierarchical_predecode3x8 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* OUTPUT: decode_16 +* OUTPUT: decode_17 +* OUTPUT: decode_18 +* OUTPUT: decode_19 +* OUTPUT: decode_20 +* OUTPUT: decode_21 +* OUTPUT: decode_22 +* OUTPUT: decode_23 +* OUTPUT: decode_24 +* OUTPUT: decode_25 +* OUTPUT: decode_26 +* OUTPUT: decode_27 +* OUTPUT: decode_28 +* OUTPUT: decode_29 +* OUTPUT: decode_30 +* OUTPUT: decode_31 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre3x8_0 addr_2 addr_3 addr_4 out_4 out_5 out_6 out_7 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode3x8 +XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec +XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec +XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec +XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec +XDEC_AND_16 out_0 out_8 decode_16 vdd gnd and2_dec +XDEC_AND_20 out_0 out_9 decode_20 vdd gnd and2_dec +XDEC_AND_24 out_0 out_10 decode_24 vdd gnd and2_dec +XDEC_AND_28 out_0 out_11 decode_28 vdd gnd and2_dec +XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec +XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec +XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec +XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec +XDEC_AND_17 out_1 out_8 decode_17 vdd gnd and2_dec +XDEC_AND_21 out_1 out_9 decode_21 vdd gnd and2_dec +XDEC_AND_25 out_1 out_10 decode_25 vdd gnd and2_dec +XDEC_AND_29 out_1 out_11 decode_29 vdd gnd and2_dec +XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec +XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec +XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec +XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec +XDEC_AND_18 out_2 out_8 decode_18 vdd gnd and2_dec +XDEC_AND_22 out_2 out_9 decode_22 vdd gnd and2_dec +XDEC_AND_26 out_2 out_10 decode_26 vdd gnd and2_dec +XDEC_AND_30 out_2 out_11 decode_30 vdd gnd and2_dec +XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec +XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec +XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec +XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec +XDEC_AND_19 out_3 out_8 decode_19 vdd gnd and2_dec +XDEC_AND_23 out_3 out_9 decode_23 vdd gnd and2_dec +XDEC_AND_27 out_3 out_10 decode_27 vdd gnd and2_dec +XDEC_AND_31 out_3 out_11 decode_31 vdd gnd and2_dec +.ENDS hierarchical_decoder + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 8 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv_0 +.ENDS and2_dec_0 + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: dout0_2 +* OUTPUT: dout0_3 +* OUTPUT: dout0_4 +* OUTPUT: dout0_5 +* OUTPUT: dout0_6 +* OUTPUT: dout0_7 +* OUTPUT: dout0_8 +* OUTPUT: dout0_9 +* OUTPUT: dout0_10 +* OUTPUT: dout0_11 +* OUTPUT: dout0_12 +* OUTPUT: dout0_13 +* OUTPUT: dout0_14 +* OUTPUT: dout0_15 +* OUTPUT: dout0_16 +* OUTPUT: dout0_17 +* OUTPUT: dout0_18 +* OUTPUT: dout0_19 +* OUTPUT: dout0_20 +* OUTPUT: dout0_21 +* OUTPUT: dout0_22 +* OUTPUT: dout0_23 +* OUTPUT: dout0_24 +* OUTPUT: dout0_25 +* OUTPUT: dout0_26 +* OUTPUT: dout0_27 +* OUTPUT: dout0_28 +* OUTPUT: dout0_29 +* OUTPUT: dout0_30 +* OUTPUT: dout0_31 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : din0_2 +* INPUT : din0_3 +* INPUT : din0_4 +* INPUT : din0_5 +* INPUT : din0_6 +* INPUT : din0_7 +* INPUT : din0_8 +* INPUT : din0_9 +* INPUT : din0_10 +* INPUT : din0_11 +* INPUT : din0_12 +* INPUT : din0_13 +* INPUT : din0_14 +* INPUT : din0_15 +* INPUT : din0_16 +* INPUT : din0_17 +* INPUT : din0_18 +* INPUT : din0_19 +* INPUT : din0_20 +* INPUT : din0_21 +* INPUT : din0_22 +* INPUT : din0_23 +* INPUT : din0_24 +* INPUT : din0_25 +* INPUT : din0_26 +* INPUT : din0_27 +* INPUT : din0_28 +* INPUT : din0_29 +* INPUT : din0_30 +* INPUT : din0_31 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : addr0_4 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 rbl_wl0 vdd gnd port_address +.ENDS bank + +.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 32 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff +Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff +Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff +Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff +Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff +Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff +Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff +Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff +Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff +Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff +Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff +Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff +Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff +Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff +Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff +Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff +Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff +Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff +Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff +Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff +Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff +Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff +Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff +Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff +Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff +Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff +Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff +Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff +Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff +Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff +.ENDS data_dff + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3_0 + +* spice ptx M{0} {1} p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p + +* spice ptx M{0} {1} n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p + +.SUBCKT pinv_13 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p +Mpinv_nmos Z A gnd gnd n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p +.ENDS pinv_13 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [40] +Xbuf_inv1 A Z vdd gnd pinv_13 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_1 + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_1 + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_2 + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_1 +Xdff_buf_inv2 Qb Q vdd gnd pinv_2 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p + +.SUBCKT pinv_14 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p +.ENDS pinv_14 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [32] +Xbuf_inv1 A Z vdd gnd pinv_14 +.ENDS pdriver_3 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +.SUBCKT pinv_18 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_18 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_18 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_18 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_18 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_18 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_18 +Xdinv1 dout_1 dout_2 vdd gnd pinv_18 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_18 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_18 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_18 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_18 +Xdinv2 dout_2 dout_3 vdd gnd pinv_18 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_18 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_18 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_18 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_18 +Xdinv3 dout_3 dout_4 vdd gnd pinv_18 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_18 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_18 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_18 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_18 +Xdinv4 dout_4 dout_5 vdd gnd pinv_18 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_18 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_18 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_18 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_18 +Xdinv5 dout_5 dout_6 vdd gnd pinv_18 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_18 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_18 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_18 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_18 +Xdinv6 dout_6 dout_7 vdd gnd pinv_18 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_18 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_18 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_18 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_18 +Xdinv7 dout_7 dout_8 vdd gnd pinv_18 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_18 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_18 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_18 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_18 +Xdinv8 dout_8 out vdd gnd pinv_18 +Xdload_8_0 out n_8_0 vdd gnd pinv_18 +Xdload_8_1 out n_8_1 vdd gnd pinv_18 +Xdload_8_2 out n_8_2 vdd gnd pinv_18 +Xdload_8_3 out n_8_3 vdd gnd pinv_18 +.ENDS delay_chain + +* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p + +* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +.SUBCKT pinv_12 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p +Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +.ENDS pinv_12 + +* spice ptx M{0} {1} p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p + +* spice ptx M{0} {1} n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p +Mpinv_nmos Z A gnd gnd n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p +.ENDS pinv_11 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [3, 10] +Xbuf_inv1 A Zb1_int vdd gnd pinv_11 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_12 +.ENDS pdriver_1 + +* spice ptx M{0} {1} p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p + +* spice ptx M{0} {1} n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p +Mpinv_nmos Z A gnd gnd n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p +.ENDS pinv_10 + +* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p + +* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p +.ENDS pinv_8 + +* spice ptx M{0} {1} n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p + +* spice ptx M{0} {1} p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p +Mpinv_nmos Z A gnd gnd n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p +.ENDS pinv_9 + +.SUBCKT pinv_6 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_6 + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_7 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 2, 7, 22, 67] +Xbuf_inv1 A Zb1_int vdd gnd pinv_6 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 +Xbuf_inv6 Zb5_int Z vdd gnd pinv_10 +.ENDS pdriver_0 + +.SUBCKT pinv_15 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_15 + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +.SUBCKT pinv_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p +.ENDS pinv_3 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_3 +.ENDS pdriver + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_0 + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +.SUBCKT pinv_16 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_16 + +* spice ptx M{0} {1} n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p + +* spice ptx M{0} {1} p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p + +.SUBCKT pinv_17 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p +Mpinv_nmos Z A gnd gnd n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p +.ENDS pinv_17 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 4, 11] +Xbuf_inv1 A Zb1_int vdd gnd pinv_6 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_16 +Xbuf_inv4 Zb3_int Z vdd gnd pinv_17 +.ENDS pdriver_4 + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 32 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_15 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 +Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_15 +Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 +Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 +Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain +Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 +Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT sram_32_32_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] vdd gnd +*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : din0[2] +* INPUT : din0[3] +* INPUT : din0[4] +* INPUT : din0[5] +* INPUT : din0[6] +* INPUT : din0[7] +* INPUT : din0[8] +* INPUT : din0[9] +* INPUT : din0[10] +* INPUT : din0[11] +* INPUT : din0[12] +* INPUT : din0[13] +* INPUT : din0[14] +* INPUT : din0[15] +* INPUT : din0[16] +* INPUT : din0[17] +* INPUT : din0[18] +* INPUT : din0[19] +* INPUT : din0[20] +* INPUT : din0[21] +* INPUT : din0[22] +* INPUT : din0[23] +* INPUT : din0[24] +* INPUT : din0[25] +* INPUT : din0[26] +* INPUT : din0[27] +* INPUT : din0[28] +* INPUT : din0[29] +* INPUT : din0[30] +* INPUT : din0[31] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : addr0[4] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* OUTPUT: dout0[2] +* OUTPUT: dout0[3] +* OUTPUT: dout0[4] +* OUTPUT: dout0[5] +* OUTPUT: dout0[6] +* OUTPUT: dout0[7] +* OUTPUT: dout0[8] +* OUTPUT: dout0[9] +* OUTPUT: dout0[10] +* OUTPUT: dout0[11] +* OUTPUT: dout0[12] +* OUTPUT: dout0[13] +* OUTPUT: dout0[14] +* OUTPUT: dout0[15] +* OUTPUT: dout0[16] +* OUTPUT: dout0[17] +* OUTPUT: dout0[18] +* OUTPUT: dout0[19] +* OUTPUT: dout0[20] +* OUTPUT: dout0[21] +* OUTPUT: dout0[22] +* OUTPUT: dout0[23] +* OUTPUT: dout0[24] +* OUTPUT: dout0[25] +* OUTPUT: dout0[26] +* OUTPUT: dout0[27] +* OUTPUT: dout0[28] +* OUTPUT: dout0[29] +* OUTPUT: dout0[30] +* OUTPUT: dout0[31] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 a0_0 a0_1 a0_2 a0_3 a0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] a0_0 a0_1 a0_2 a0_3 a0_4 clk_buf0 vdd gnd row_addr_dff +Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 clk_buf0 vdd gnd data_dff +.ENDS sram_32_32_scn4m_subm From b05a721fb54a0d975b58c5fa7b4f431e53d268d9 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 25 Apr 2022 22:15:55 -0700 Subject: [PATCH 002/102] spice for delay chain with all inverter outputs as pins --- compiler/modules/delay_chain_all_pins.py | 220 +++++++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 compiler/modules/delay_chain_all_pins.py diff --git a/compiler/modules/delay_chain_all_pins.py b/compiler/modules/delay_chain_all_pins.py new file mode 100644 index 00000000..0eb0dea5 --- /dev/null +++ b/compiler/modules/delay_chain_all_pins.py @@ -0,0 +1,220 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +import design +from vector import vector +from globals import OPTS +from sram_factory import factory + + +class delay_chain(design.design): + """ + Generate a delay chain with the given number of stages, fanout, and output pins. + Fanout list contains the electrical effort (fanout) of each stage. + Usually, this will be constant, but it could have varied fanout. + Pinout list contains the inverter stages which have an output pin attached. + Supplying an empty pinout list will result in an output on the last stage. + """ + + def __init__(self, name, fanout_list, pinout_list): + """init function""" + super().__init__(name) + debug.info(1, "creating delay chain {0}".format(str(fanout_list))) + self.add_comment("fanouts: {0}".format(str(fanout_list))) + + # Two fanouts are needed so that we can route the vdd/gnd connections + for f in fanout_list: + debug.check(f>=2, "Must have >=2 fanouts for each stage.") + + # number of inverters including any fanout loads. + self.fanout_list = fanout_list + self.rows = len(self.fanout_list) + + # defaults to signle output at end of delay chain + if len(self.pinout_list) == 0: + self.pinout_list = [self.rows] # TODO: check for off-by-one here + else: + self.pinout_list = pinout_list + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + self.add_modules() + self.add_pins() + self.create_inverters() + + def create_layout(self): + # Each stage is a a row + self.height = self.rows * self.inv.height + # The width is determined by the largest fanout plus the driver + self.width = (max(self.fanout_list) + 1) * self.inv.width + + self.place_inverters() + self.route_inverters() + self.route_supplies() + self.add_layout_pins() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + """ Add the pins of the delay chain""" + self.add_pin("in", "INPUT") + for pin_stage in self.pinout_list: + self.add_pin("out{}".format(pin_stage), "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def add_modules(self): + + self.dff = factory.create(module_type="dff_buf") + dff_height = self.dff.height + + self.inv = factory.create(module_type="pinv", + height=dff_height) + + def create_inverters(self): + """ Create the inverters and connect them based on the stage list """ + self.driver_inst_list = [] + self.load_inst_map = {} + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): + # Add the inverter + cur_driver=self.add_inst(name="dinv{}".format(stage_num), + mod=self.inv) + # keep track of the inverter instances so we can use them to get the pins + self.driver_inst_list.append(cur_driver) + + # Hook up the driver + stageout_name = "out{}".format(stage_num + 1) # TODO: check for off-by-one here + if stage_num == 0: + stagein_name = "in" + else: + stagein_name = "out{}".format(stage_num) + self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"]) + + # Now add the dummy loads to the right + self.load_inst_map[cur_driver]=[] + for i in range(fanout_size): + cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num, i), + mod=self.inv) + # Fanout stage is always driven by driver and output is disconnected + disconnect_name = "n_{0}_{1}".format(stage_num, i) + self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"]) + + # Keep track of all the loads to connect their inputs as a load + self.load_inst_map[cur_driver].append(cur_load) + + def place_inverters(self): + """ Place the inverters and connect them based on the stage list """ + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): + if stage_num % 2: + inv_mirror = "MX" + inv_offset = vector(0, (stage_num + 1) * self.inv.height) + else: + inv_mirror = "R0" + inv_offset = vector(0, stage_num * self.inv.height) + + # Add the inverter + cur_driver=self.driver_inst_list[stage_num] + cur_driver.place(offset=inv_offset, + mirror=inv_mirror) + + # Now add the dummy loads to the right + load_list = self.load_inst_map[cur_driver] + for i in range(fanout_size): + inv_offset += vector(self.inv.width, 0) + load_list[i].place(offset=inv_offset, + mirror=inv_mirror) + + def add_route(self, pin1, pin2): + """ This guarantees that we route from the top to bottom row correctly. """ + pin1_pos = pin1.center() + pin2_pos = pin2.center() + if pin1_pos.y == pin2_pos.y: + self.add_path("m2", [pin1_pos, pin2_pos]) + else: + mid_point = vector(pin2_pos.x, 0.5 * (pin1_pos.y + pin2_pos.y)) + # Written this way to guarantee it goes right first if we are switching rows + self.add_path("m2", [pin1_pos, vector(pin1_pos.x, mid_point.y), mid_point, vector(mid_point.x, pin2_pos.y), pin2_pos]) + + def route_inverters(self): + """ Add metal routing for each of the fanout stages """ + + for i in range(len(self.driver_inst_list)): + inv = self.driver_inst_list[i] + for load in self.load_inst_map[inv]: + # Drop a via on each A pin + a_pin = load.get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m3", + offset=a_pin.center()) + + # Route an M3 horizontal wire to the furthest + z_pin = inv.get_pin("Z") + a_pin = inv.get_pin("A") + a_max = self.load_inst_map[inv][-1].get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) + self.add_via_stack_center(from_layer=z_pin.layer, + to_layer="m3", + offset=z_pin.center()) + self.add_path("m3", [z_pin.center(), a_max.center()]) + + # Route Z to the A of the next stage + if i + 1 < len(self.driver_inst_list): + z_pin = inv.get_pin("Z") + next_inv = self.driver_inst_list[i + 1] + next_a_pin = next_inv.get_pin("A") + y_mid = (z_pin.cy() + next_a_pin.cy()) / 2 + mid1_point = vector(z_pin.cx(), y_mid) + mid2_point = vector(next_a_pin.cx(), y_mid) + self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) + + def route_supplies(self): + # Add power and ground to all the cells except: + # the fanout driver, the right-most load + # The routing to connect the loads is over the first and last cells + # We have an even number of drivers and must only do every other + # supply rail + + for inst in self.driver_inst_list: + load_list = self.load_inst_map[inst] + for pin_name in ["vdd", "gnd"]: + pin = load_list[0].get_pin(pin_name) + self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0)) + + pin = load_list[-2].get_pin(pin_name) + self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0)) + + def add_layout_pins(self): + + # input is A pin of first inverter + # It gets routed to the left a bit to prevent pin access errors + # due to the output pin when going up to M3 + a_pin = self.driver_inst_list[0].get_pin("A") + mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=mid_loc) + self.add_path(a_pin.layer, [a_pin.center(), mid_loc]) + + self.add_layout_pin_rect_center(text="in", + layer="m2", + offset=mid_loc) + + # output is A pin of last load/fanout inverter + last_driver_inst = self.driver_inst_list[-1] + a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m1", + offset=a_pin.center()) + self.add_layout_pin_rect_center(text="out", + layer="m1", + offset=a_pin.center()) From 66502fc5dcc94408c3b7dccd1aa73f591334bef9 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 27 Apr 2022 03:01:08 -0700 Subject: [PATCH 003/102] new control logic module with no more rbl logic, added glitches so far --- ..._128_scn4m_subm-collapse-glitch-control.sp | 14097 ++++++++++++++++ compiler/modules/control_logic_delay.py | 811 + compiler/modules/multi_delay_chain.py | 220 + 3 files changed, 15128 insertions(+) create mode 100644 1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp create mode 100644 compiler/modules/control_logic_delay.py create mode 100644 compiler/modules/multi_delay_chain.py diff --git a/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp b/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp new file mode 100644 index 00000000..678019c2 --- /dev/null +++ b/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp @@ -0,0 +1,14097 @@ +************************************************** +* OpenRAM generated memory. +* Words: 128 +* Data bits: 64 +* Banks: 1 +* Column mux: 2:1 +* Trimmed: False +* LVS: False +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 6 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff +Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff +Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff +Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff +Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff +.ENDS row_addr_dff + +.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd +*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B +* INPUT : din_0 +* OUTPUT: dout_0 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 1 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +.ENDS col_addr_dff + +.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd +*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* rows: 1 cols: 64 +Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff +Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff +Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff +Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff +Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff +Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff +Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff +Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff +Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff +Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff +Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff +Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff +Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff +Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff +Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff +Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff +Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff +Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff +Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff +Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff +Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff +Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff +Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff +Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff +Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff +Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff +Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff +Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff +Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff +Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff +Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff +Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff +Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff +Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff +Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff +Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff +Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff +Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff +Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff +Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff +Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff +Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff +Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff +Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff +Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff +Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff +Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff +Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff +Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff +Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff +Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff +Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff +Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff +Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff +Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff +Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff +Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff +Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff +Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff +Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff +Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff +Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff +Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff +Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff +.ENDS data_dff + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_2 + +* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p + +.SUBCKT pinv_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +.ENDS pinv_3 + +* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pinv_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_1 + +.SUBCKT pinvbuf A Zb Z vdd gnd +*.PININFO A:B Zb:B Z:B vdd:B gnd:B +* INOUT : A +* INOUT : Zb +* INOUT : Z +* INOUT : vdd +* INOUT : gnd +Xbuf_inv1 A zb_int vdd gnd pinv_1 +Xbuf_inv2 zb_int z_int vdd gnd pinv_2 +Xbuf_inv3 z_int Zb vdd gnd pinv_3 +Xbuf_inv4 zb_int Z vdd gnd pinv_3 +.ENDS pinvbuf + +*********************** "dummy_cell_1rw" ****************************** +.SUBCKT dummy_cell_1rw bl br wl vdd gnd + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_2 + +.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array + +.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_0 + +.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw +Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw +Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw +Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS dummy_array_3 + +*********************** "cell_1rw" ****************************** +.SUBCKT replica_cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q vdd vdd vdd p w=0.6u l=0.8u +M1002 Q vdd gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q vdd vdd p w=0.6u l=0.8u +M1003 gnd Q vdd gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 vdd wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd +*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B +* OUTPUT: bl_0_0 +* OUTPUT: br_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* INPUT : wl_0_64 +* INPUT : wl_0_65 +* INPUT : wl_0_66 +* POWER : vdd +* GROUND: gnd +Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw +Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw +Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw +Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw +Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw +Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw +Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw +Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw +Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw +Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw +Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw +Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw +Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw +Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw +Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw +Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw +Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw +Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw +Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw +Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw +Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw +Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw +Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw +Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw +Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw +Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw +Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw +Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw +Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw +Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw +Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw +Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw +Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw +Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw +Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw +Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw +Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw +Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw +Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw +Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw +Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw +Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw +Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw +Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw +Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw +Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw +Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw +Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw +Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw +Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw +Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw +Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw +Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw +Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw +Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw +Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw +Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw +Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw +Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw +Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw +Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw +Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw +Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw +Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw +Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw +Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw +.ENDS replica_column + +.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* POWER : vdd +* GROUND: gnd +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw +.ENDS dummy_array_1 + +*********************** "cell_1rw" ****************************** +.SUBCKT cell_1rw bl br wl vdd gnd +* SPICE3 file created from cell_1rw.ext - technology: scmos + +* Inverter 1 +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u + +.ENDS + +.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw 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br_0_16 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw 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wl_0_18 vdd gnd cell_1rw +Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c49 bl_0_49 br_0_49 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c49 bl_0_49 br_0_49 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c49 bl_0_49 br_0_49 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c49 bl_0_49 br_0_49 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c49 bl_0_49 br_0_49 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c49 bl_0_49 br_0_49 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c49 bl_0_49 br_0_49 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c49 bl_0_49 br_0_49 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c49 bl_0_49 br_0_49 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c49 bl_0_49 br_0_49 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c49 bl_0_49 br_0_49 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c49 bl_0_49 br_0_49 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c49 bl_0_49 br_0_49 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c49 bl_0_49 br_0_49 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c49 bl_0_49 br_0_49 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c49 bl_0_49 br_0_49 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c49 bl_0_49 br_0_49 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c49 bl_0_49 br_0_49 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c52 bl_0_52 br_0_52 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c52 bl_0_52 br_0_52 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c52 bl_0_52 br_0_52 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c52 bl_0_52 br_0_52 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c52 bl_0_52 br_0_52 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c52 bl_0_52 br_0_52 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c52 bl_0_52 br_0_52 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c52 bl_0_52 br_0_52 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c52 bl_0_52 br_0_52 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c52 bl_0_52 br_0_52 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c52 bl_0_52 br_0_52 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c53 bl_0_53 br_0_53 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c53 bl_0_53 br_0_53 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c53 bl_0_53 br_0_53 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c53 bl_0_53 br_0_53 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c53 bl_0_53 br_0_53 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c53 bl_0_53 br_0_53 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c53 bl_0_53 br_0_53 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c53 bl_0_53 br_0_53 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c53 bl_0_53 br_0_53 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c53 bl_0_53 br_0_53 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c53 bl_0_53 br_0_53 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c53 bl_0_53 br_0_53 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c53 bl_0_53 br_0_53 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c53 bl_0_53 br_0_53 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c53 bl_0_53 br_0_53 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c53 bl_0_53 br_0_53 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c53 bl_0_53 br_0_53 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c53 bl_0_53 br_0_53 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c53 bl_0_53 br_0_53 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c53 bl_0_53 br_0_53 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c53 bl_0_53 br_0_53 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c53 bl_0_53 br_0_53 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c53 bl_0_53 br_0_53 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c53 bl_0_53 br_0_53 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c53 bl_0_53 br_0_53 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c53 bl_0_53 br_0_53 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c53 bl_0_53 br_0_53 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c53 bl_0_53 br_0_53 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c53 bl_0_53 br_0_53 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c53 bl_0_53 br_0_53 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c53 bl_0_53 br_0_53 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c53 bl_0_53 br_0_53 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c53 bl_0_53 br_0_53 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c53 bl_0_53 br_0_53 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c53 bl_0_53 br_0_53 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c53 bl_0_53 br_0_53 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c53 bl_0_53 br_0_53 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c53 bl_0_53 br_0_53 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c53 bl_0_53 br_0_53 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c53 bl_0_53 br_0_53 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c53 bl_0_53 br_0_53 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c53 bl_0_53 br_0_53 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c53 bl_0_53 br_0_53 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c59 bl_0_59 br_0_59 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c59 bl_0_59 br_0_59 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c59 bl_0_59 br_0_59 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c60 bl_0_60 br_0_60 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c60 bl_0_60 br_0_60 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c60 bl_0_60 br_0_60 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c60 bl_0_60 br_0_60 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c60 bl_0_60 br_0_60 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c60 bl_0_60 br_0_60 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c60 bl_0_60 br_0_60 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c60 bl_0_60 br_0_60 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c60 bl_0_60 br_0_60 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c60 bl_0_60 br_0_60 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c60 bl_0_60 br_0_60 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c60 bl_0_60 br_0_60 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c60 bl_0_60 br_0_60 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c60 bl_0_60 br_0_60 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c60 bl_0_60 br_0_60 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c73 bl_0_73 br_0_73 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c73 bl_0_73 br_0_73 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c73 bl_0_73 br_0_73 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c73 bl_0_73 br_0_73 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c73 bl_0_73 br_0_73 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c73 bl_0_73 br_0_73 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c73 bl_0_73 br_0_73 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c73 bl_0_73 br_0_73 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c73 bl_0_73 br_0_73 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c73 bl_0_73 br_0_73 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c73 bl_0_73 br_0_73 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c73 bl_0_73 br_0_73 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c73 bl_0_73 br_0_73 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c73 bl_0_73 br_0_73 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c73 bl_0_73 br_0_73 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c73 bl_0_73 br_0_73 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c73 bl_0_73 br_0_73 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c73 bl_0_73 br_0_73 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c74 bl_0_74 br_0_74 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c74 bl_0_74 br_0_74 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c74 bl_0_74 br_0_74 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c74 bl_0_74 br_0_74 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c74 bl_0_74 br_0_74 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c74 bl_0_74 br_0_74 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c74 bl_0_74 br_0_74 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c74 bl_0_74 br_0_74 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c74 bl_0_74 br_0_74 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c74 bl_0_74 br_0_74 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c74 bl_0_74 br_0_74 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c74 bl_0_74 br_0_74 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c74 bl_0_74 br_0_74 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c74 bl_0_74 br_0_74 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c74 bl_0_74 br_0_74 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c74 bl_0_74 br_0_74 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c74 bl_0_74 br_0_74 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c74 bl_0_74 br_0_74 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c74 bl_0_74 br_0_74 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c74 bl_0_74 br_0_74 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c74 bl_0_74 br_0_74 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c74 bl_0_74 br_0_74 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c74 bl_0_74 br_0_74 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c74 bl_0_74 br_0_74 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c74 bl_0_74 br_0_74 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c74 bl_0_74 br_0_74 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c74 bl_0_74 br_0_74 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c74 bl_0_74 br_0_74 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c74 bl_0_74 br_0_74 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c74 bl_0_74 br_0_74 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c74 bl_0_74 br_0_74 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c74 bl_0_74 br_0_74 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c74 bl_0_74 br_0_74 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c75 bl_0_75 br_0_75 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c75 bl_0_75 br_0_75 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c75 bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw 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wl_0_12 vdd gnd cell_1rw +Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c81 bl_0_81 br_0_81 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c81 bl_0_81 br_0_81 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c81 bl_0_81 br_0_81 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c81 bl_0_81 br_0_81 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c81 bl_0_81 br_0_81 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c81 bl_0_81 br_0_81 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c81 bl_0_81 br_0_81 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c82 bl_0_82 br_0_82 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c82 bl_0_82 br_0_82 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c82 bl_0_82 br_0_82 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c82 bl_0_82 br_0_82 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c82 bl_0_82 br_0_82 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c82 bl_0_82 br_0_82 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c82 bl_0_82 br_0_82 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c82 bl_0_82 br_0_82 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c82 bl_0_82 br_0_82 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c82 bl_0_82 br_0_82 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c82 bl_0_82 br_0_82 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c83 bl_0_83 br_0_83 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c83 bl_0_83 br_0_83 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c84 bl_0_84 br_0_84 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c84 bl_0_84 br_0_84 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c84 bl_0_84 br_0_84 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c84 bl_0_84 br_0_84 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c84 bl_0_84 br_0_84 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c84 bl_0_84 br_0_84 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c84 bl_0_84 br_0_84 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c84 bl_0_84 br_0_84 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c84 bl_0_84 br_0_84 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c84 bl_0_84 br_0_84 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c84 bl_0_84 br_0_84 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c84 bl_0_84 br_0_84 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c84 bl_0_84 br_0_84 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c84 bl_0_84 br_0_84 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c84 bl_0_84 br_0_84 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c84 bl_0_84 br_0_84 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c87 bl_0_87 br_0_87 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c87 bl_0_87 br_0_87 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c87 bl_0_87 br_0_87 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c87 bl_0_87 br_0_87 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c87 bl_0_87 br_0_87 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c87 bl_0_87 br_0_87 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c87 bl_0_87 br_0_87 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c87 bl_0_87 br_0_87 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c88 bl_0_88 br_0_88 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c88 bl_0_88 br_0_88 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c88 bl_0_88 br_0_88 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c88 bl_0_88 br_0_88 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c88 bl_0_88 br_0_88 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c88 bl_0_88 br_0_88 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c88 bl_0_88 br_0_88 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c88 bl_0_88 br_0_88 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c88 bl_0_88 br_0_88 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c88 bl_0_88 br_0_88 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c89 bl_0_89 br_0_89 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c89 bl_0_89 br_0_89 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c89 bl_0_89 br_0_89 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c90 bl_0_90 br_0_90 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c90 bl_0_90 br_0_90 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c90 bl_0_90 br_0_90 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c90 bl_0_90 br_0_90 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c90 bl_0_90 br_0_90 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c90 bl_0_90 br_0_90 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c90 bl_0_90 br_0_90 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c90 bl_0_90 br_0_90 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c90 bl_0_90 br_0_90 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c90 bl_0_90 br_0_90 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c90 bl_0_90 br_0_90 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c90 bl_0_90 br_0_90 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c90 bl_0_90 br_0_90 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c90 bl_0_90 br_0_90 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c90 bl_0_90 br_0_90 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c96 bl_0_96 br_0_96 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c96 bl_0_96 br_0_96 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c96 bl_0_96 br_0_96 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c96 bl_0_96 br_0_96 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c96 bl_0_96 br_0_96 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c96 bl_0_96 br_0_96 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c96 bl_0_96 br_0_96 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c96 bl_0_96 br_0_96 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c96 bl_0_96 br_0_96 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c96 bl_0_96 br_0_96 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c96 bl_0_96 br_0_96 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c96 bl_0_96 br_0_96 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c96 bl_0_96 br_0_96 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c96 bl_0_96 br_0_96 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c96 bl_0_96 br_0_96 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c96 bl_0_96 br_0_96 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c96 bl_0_96 br_0_96 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c96 bl_0_96 br_0_96 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c96 bl_0_96 br_0_96 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c97 bl_0_97 br_0_97 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c97 bl_0_97 br_0_97 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c97 bl_0_97 br_0_97 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c97 bl_0_97 br_0_97 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c97 bl_0_97 br_0_97 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c97 bl_0_97 br_0_97 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c97 bl_0_97 br_0_97 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c97 bl_0_97 br_0_97 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c97 bl_0_97 br_0_97 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c97 bl_0_97 br_0_97 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c97 bl_0_97 br_0_97 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c97 bl_0_97 br_0_97 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c97 bl_0_97 br_0_97 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c97 bl_0_97 br_0_97 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c97 bl_0_97 br_0_97 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c97 bl_0_97 br_0_97 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c97 bl_0_97 br_0_97 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c98 bl_0_98 br_0_98 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c98 bl_0_98 br_0_98 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c98 bl_0_98 br_0_98 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c98 bl_0_98 br_0_98 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c98 bl_0_98 br_0_98 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c98 bl_0_98 br_0_98 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c98 bl_0_98 br_0_98 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c98 bl_0_98 br_0_98 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c98 bl_0_98 br_0_98 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c98 bl_0_98 br_0_98 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c98 bl_0_98 br_0_98 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c98 bl_0_98 br_0_98 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c98 bl_0_98 br_0_98 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c98 bl_0_98 br_0_98 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c99 bl_0_99 br_0_99 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c99 bl_0_99 br_0_99 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c99 bl_0_99 br_0_99 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c99 bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c100 bl_0_100 br_0_100 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c100 bl_0_100 br_0_100 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c100 bl_0_100 br_0_100 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c100 bl_0_100 br_0_100 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c100 bl_0_100 br_0_100 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c100 bl_0_100 br_0_100 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c100 bl_0_100 br_0_100 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c100 bl_0_100 br_0_100 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c100 bl_0_100 br_0_100 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c100 bl_0_100 br_0_100 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c100 bl_0_100 br_0_100 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c100 bl_0_100 br_0_100 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c100 bl_0_100 br_0_100 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c100 bl_0_100 br_0_100 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c100 bl_0_100 br_0_100 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c100 bl_0_100 br_0_100 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c100 bl_0_100 br_0_100 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c108 bl_0_108 br_0_108 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c108 bl_0_108 br_0_108 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c108 bl_0_108 br_0_108 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c108 bl_0_108 br_0_108 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c108 bl_0_108 br_0_108 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c108 bl_0_108 br_0_108 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c108 bl_0_108 br_0_108 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c108 bl_0_108 br_0_108 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c108 bl_0_108 br_0_108 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c108 bl_0_108 br_0_108 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c108 bl_0_108 br_0_108 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c108 bl_0_108 br_0_108 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c108 bl_0_108 br_0_108 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c108 bl_0_108 br_0_108 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c108 bl_0_108 br_0_108 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c108 bl_0_108 br_0_108 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c108 bl_0_108 br_0_108 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c108 bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw 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bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw 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bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw 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bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c114 bl_0_114 br_0_114 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c114 bl_0_114 br_0_114 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c114 bl_0_114 br_0_114 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c114 bl_0_114 br_0_114 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c114 bl_0_114 br_0_114 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c114 bl_0_114 br_0_114 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c114 bl_0_114 br_0_114 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c114 bl_0_114 br_0_114 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c114 bl_0_114 br_0_114 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c114 bl_0_114 br_0_114 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c114 bl_0_114 br_0_114 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c114 bl_0_114 br_0_114 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c114 bl_0_114 br_0_114 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c114 bl_0_114 br_0_114 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c114 bl_0_114 br_0_114 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c115 bl_0_115 br_0_115 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c115 bl_0_115 br_0_115 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c116 bl_0_116 br_0_116 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c116 bl_0_116 br_0_116 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c116 bl_0_116 br_0_116 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c116 bl_0_116 br_0_116 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c116 bl_0_116 br_0_116 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c116 bl_0_116 br_0_116 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c116 bl_0_116 br_0_116 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c116 bl_0_116 br_0_116 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c116 bl_0_116 br_0_116 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c116 bl_0_116 br_0_116 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c116 bl_0_116 br_0_116 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c116 bl_0_116 br_0_116 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c116 bl_0_116 br_0_116 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c116 bl_0_116 br_0_116 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c116 bl_0_116 br_0_116 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c116 bl_0_116 br_0_116 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c116 bl_0_116 br_0_116 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c116 bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c119 bl_0_119 br_0_119 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c119 bl_0_119 br_0_119 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c119 bl_0_119 br_0_119 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c119 bl_0_119 br_0_119 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c119 bl_0_119 br_0_119 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c119 bl_0_119 br_0_119 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c119 bl_0_119 br_0_119 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c119 bl_0_119 br_0_119 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c119 bl_0_119 br_0_119 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c119 bl_0_119 br_0_119 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c119 bl_0_119 br_0_119 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c119 bl_0_119 br_0_119 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c119 bl_0_119 br_0_119 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c119 bl_0_119 br_0_119 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c119 bl_0_119 br_0_119 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c119 bl_0_119 br_0_119 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c119 bl_0_119 br_0_119 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c119 bl_0_119 br_0_119 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c119 bl_0_119 br_0_119 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c119 bl_0_119 br_0_119 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c119 bl_0_119 br_0_119 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c119 bl_0_119 br_0_119 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c119 bl_0_119 br_0_119 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c119 bl_0_119 br_0_119 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c119 bl_0_119 br_0_119 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c119 bl_0_119 br_0_119 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c119 bl_0_119 br_0_119 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c119 bl_0_119 br_0_119 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c119 bl_0_119 br_0_119 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c119 bl_0_119 br_0_119 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c119 bl_0_119 br_0_119 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c119 bl_0_119 br_0_119 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c119 bl_0_119 br_0_119 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c119 bl_0_119 br_0_119 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c119 bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw 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bl_0_120 br_0_120 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c120 bl_0_120 br_0_120 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c120 bl_0_120 br_0_120 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c120 bl_0_120 br_0_120 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c120 bl_0_120 br_0_120 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c120 bl_0_120 br_0_120 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c120 bl_0_120 br_0_120 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c120 bl_0_120 br_0_120 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c120 bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw 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bl_0_121 br_0_121 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c121 bl_0_121 br_0_121 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c121 bl_0_121 br_0_121 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c121 bl_0_121 br_0_121 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c121 bl_0_121 br_0_121 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c121 bl_0_121 br_0_121 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c121 bl_0_121 br_0_121 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c121 bl_0_121 br_0_121 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c121 bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw 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bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw 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bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c126 bl_0_126 br_0_126 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c126 bl_0_126 br_0_126 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c126 bl_0_126 br_0_126 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c126 bl_0_126 br_0_126 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c126 bl_0_126 br_0_126 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c126 bl_0_126 br_0_126 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c126 bl_0_126 br_0_126 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c126 bl_0_126 br_0_126 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c126 bl_0_126 br_0_126 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c126 bl_0_126 br_0_126 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c126 bl_0_126 br_0_126 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c126 bl_0_126 br_0_126 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c126 bl_0_126 br_0_126 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c126 bl_0_126 br_0_126 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c126 bl_0_126 br_0_126 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c126 bl_0_126 br_0_126 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c126 bl_0_126 br_0_126 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c126 bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw +Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw +Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw +Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw +Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw +Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw +Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw +Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw +Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw +Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw +Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw +Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw +Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw +Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw +Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw +Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw +Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw +Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw +Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw +Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw +Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw +Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw +Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw +Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw +Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw +Xbit_r24_c127 bl_0_127 br_0_127 wl_0_24 vdd gnd cell_1rw +Xbit_r25_c127 bl_0_127 br_0_127 wl_0_25 vdd gnd cell_1rw +Xbit_r26_c127 bl_0_127 br_0_127 wl_0_26 vdd gnd cell_1rw +Xbit_r27_c127 bl_0_127 br_0_127 wl_0_27 vdd gnd cell_1rw +Xbit_r28_c127 bl_0_127 br_0_127 wl_0_28 vdd gnd cell_1rw +Xbit_r29_c127 bl_0_127 br_0_127 wl_0_29 vdd gnd cell_1rw +Xbit_r30_c127 bl_0_127 br_0_127 wl_0_30 vdd gnd cell_1rw +Xbit_r31_c127 bl_0_127 br_0_127 wl_0_31 vdd gnd cell_1rw +Xbit_r32_c127 bl_0_127 br_0_127 wl_0_32 vdd gnd cell_1rw +Xbit_r33_c127 bl_0_127 br_0_127 wl_0_33 vdd gnd cell_1rw +Xbit_r34_c127 bl_0_127 br_0_127 wl_0_34 vdd gnd cell_1rw +Xbit_r35_c127 bl_0_127 br_0_127 wl_0_35 vdd gnd cell_1rw +Xbit_r36_c127 bl_0_127 br_0_127 wl_0_36 vdd gnd cell_1rw +Xbit_r37_c127 bl_0_127 br_0_127 wl_0_37 vdd gnd cell_1rw +Xbit_r38_c127 bl_0_127 br_0_127 wl_0_38 vdd gnd cell_1rw +Xbit_r39_c127 bl_0_127 br_0_127 wl_0_39 vdd gnd cell_1rw +Xbit_r40_c127 bl_0_127 br_0_127 wl_0_40 vdd gnd cell_1rw +Xbit_r41_c127 bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw +Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw +Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw +Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw +Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw +Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw +Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw +Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw +Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw +Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw +Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw +Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw +Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw +Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw +Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw +Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw +Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw +Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw +Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw +Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw +Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw +Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw +Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw +.ENDS bitcell_array + +.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd +*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B +* INOUT : rbl_bl_0_0 +* INOUT : rbl_br_0_0 +* INOUT : bl_0_0 +* INOUT : br_0_0 +* INOUT : bl_0_1 +* INOUT : br_0_1 +* INOUT : bl_0_2 +* INOUT : br_0_2 +* INOUT : bl_0_3 +* INOUT : br_0_3 +* INOUT : bl_0_4 +* INOUT : br_0_4 +* INOUT : bl_0_5 +* INOUT : br_0_5 +* INOUT : bl_0_6 +* INOUT : br_0_6 +* INOUT : bl_0_7 +* INOUT : br_0_7 +* INOUT : bl_0_8 +* INOUT : br_0_8 +* INOUT : bl_0_9 +* INOUT : br_0_9 +* INOUT : bl_0_10 +* INOUT : br_0_10 +* INOUT : bl_0_11 +* INOUT : br_0_11 +* INOUT : bl_0_12 +* INOUT : br_0_12 +* INOUT : bl_0_13 +* INOUT : br_0_13 +* INOUT : bl_0_14 +* INOUT : br_0_14 +* INOUT : bl_0_15 +* INOUT : br_0_15 +* INOUT : bl_0_16 +* INOUT : br_0_16 +* INOUT : bl_0_17 +* INOUT : br_0_17 +* INOUT : bl_0_18 +* INOUT : br_0_18 +* INOUT : bl_0_19 +* INOUT : br_0_19 +* INOUT : bl_0_20 +* INOUT : br_0_20 +* INOUT : bl_0_21 +* INOUT : br_0_21 +* INOUT : bl_0_22 +* INOUT : br_0_22 +* INOUT : bl_0_23 +* INOUT : br_0_23 +* INOUT : bl_0_24 +* INOUT : br_0_24 +* INOUT : bl_0_25 +* INOUT : br_0_25 +* INOUT : bl_0_26 +* INOUT : br_0_26 +* INOUT : bl_0_27 +* INOUT : br_0_27 +* INOUT : bl_0_28 +* INOUT : br_0_28 +* INOUT : bl_0_29 +* INOUT : br_0_29 +* INOUT : bl_0_30 +* INOUT : br_0_30 +* INOUT : bl_0_31 +* INOUT : br_0_31 +* INOUT : bl_0_32 +* INOUT : br_0_32 +* INOUT : bl_0_33 +* INOUT : br_0_33 +* INOUT : bl_0_34 +* INOUT : br_0_34 +* INOUT : bl_0_35 +* INOUT : br_0_35 +* INOUT : bl_0_36 +* INOUT : br_0_36 +* INOUT : bl_0_37 +* INOUT : br_0_37 +* INOUT : bl_0_38 +* INOUT : br_0_38 +* INOUT : bl_0_39 +* INOUT : br_0_39 +* INOUT : bl_0_40 +* INOUT : br_0_40 +* INOUT : bl_0_41 +* INOUT : br_0_41 +* INOUT : bl_0_42 +* INOUT : br_0_42 +* INOUT : bl_0_43 +* INOUT : br_0_43 +* INOUT : bl_0_44 +* INOUT : br_0_44 +* INOUT : bl_0_45 +* INOUT : br_0_45 +* INOUT : bl_0_46 +* INOUT : br_0_46 +* INOUT : bl_0_47 +* INOUT : br_0_47 +* INOUT : bl_0_48 +* INOUT : br_0_48 +* INOUT : bl_0_49 +* INOUT : br_0_49 +* INOUT : bl_0_50 +* INOUT : br_0_50 +* INOUT : bl_0_51 +* INOUT : br_0_51 +* INOUT : bl_0_52 +* INOUT : br_0_52 +* INOUT : bl_0_53 +* INOUT : br_0_53 +* INOUT : bl_0_54 +* INOUT : br_0_54 +* INOUT : bl_0_55 +* INOUT : br_0_55 +* INOUT : bl_0_56 +* INOUT : br_0_56 +* INOUT : bl_0_57 +* INOUT : br_0_57 +* INOUT : bl_0_58 +* INOUT : br_0_58 +* INOUT : bl_0_59 +* INOUT : br_0_59 +* INOUT : bl_0_60 +* INOUT : br_0_60 +* INOUT : bl_0_61 +* INOUT : br_0_61 +* INOUT : bl_0_62 +* INOUT : br_0_62 +* INOUT : bl_0_63 +* INOUT : br_0_63 +* INOUT : bl_0_64 +* INOUT : br_0_64 +* INOUT : bl_0_65 +* INOUT : br_0_65 +* INOUT : bl_0_66 +* INOUT : br_0_66 +* INOUT : bl_0_67 +* INOUT : br_0_67 +* INOUT : bl_0_68 +* INOUT : br_0_68 +* INOUT : bl_0_69 +* INOUT : br_0_69 +* INOUT : bl_0_70 +* INOUT : br_0_70 +* INOUT : bl_0_71 +* INOUT : br_0_71 +* INOUT : bl_0_72 +* INOUT : br_0_72 +* INOUT : bl_0_73 +* INOUT : br_0_73 +* INOUT : bl_0_74 +* INOUT : br_0_74 +* INOUT : bl_0_75 +* INOUT : br_0_75 +* INOUT : bl_0_76 +* INOUT : br_0_76 +* INOUT : bl_0_77 +* INOUT : br_0_77 +* INOUT : bl_0_78 +* INOUT : br_0_78 +* INOUT : bl_0_79 +* INOUT : br_0_79 +* INOUT : bl_0_80 +* INOUT : br_0_80 +* INOUT : bl_0_81 +* INOUT : br_0_81 +* INOUT : bl_0_82 +* INOUT : br_0_82 +* INOUT : bl_0_83 +* INOUT : br_0_83 +* INOUT : bl_0_84 +* INOUT : br_0_84 +* INOUT : bl_0_85 +* INOUT : br_0_85 +* INOUT : bl_0_86 +* INOUT : br_0_86 +* INOUT : bl_0_87 +* INOUT : br_0_87 +* INOUT : bl_0_88 +* INOUT : br_0_88 +* INOUT : bl_0_89 +* INOUT : br_0_89 +* INOUT : bl_0_90 +* INOUT : br_0_90 +* INOUT : bl_0_91 +* INOUT : br_0_91 +* INOUT : bl_0_92 +* INOUT : br_0_92 +* INOUT : bl_0_93 +* INOUT : br_0_93 +* INOUT : bl_0_94 +* INOUT : br_0_94 +* INOUT : bl_0_95 +* INOUT : br_0_95 +* INOUT : bl_0_96 +* INOUT : br_0_96 +* INOUT : bl_0_97 +* INOUT : br_0_97 +* INOUT : bl_0_98 +* INOUT : br_0_98 +* INOUT : bl_0_99 +* INOUT : br_0_99 +* INOUT : bl_0_100 +* INOUT : br_0_100 +* INOUT : bl_0_101 +* INOUT : br_0_101 +* INOUT : bl_0_102 +* INOUT : br_0_102 +* INOUT : bl_0_103 +* INOUT : br_0_103 +* INOUT : bl_0_104 +* INOUT : br_0_104 +* INOUT : bl_0_105 +* INOUT : br_0_105 +* INOUT : bl_0_106 +* INOUT : br_0_106 +* INOUT : bl_0_107 +* INOUT : br_0_107 +* INOUT : bl_0_108 +* INOUT : br_0_108 +* INOUT : bl_0_109 +* INOUT : br_0_109 +* INOUT : bl_0_110 +* INOUT : br_0_110 +* INOUT : bl_0_111 +* INOUT : br_0_111 +* INOUT : bl_0_112 +* INOUT : br_0_112 +* INOUT : bl_0_113 +* INOUT : br_0_113 +* INOUT : bl_0_114 +* INOUT : br_0_114 +* INOUT : bl_0_115 +* INOUT : br_0_115 +* INOUT : bl_0_116 +* INOUT : br_0_116 +* INOUT : bl_0_117 +* INOUT : br_0_117 +* INOUT : bl_0_118 +* INOUT : br_0_118 +* INOUT : bl_0_119 +* INOUT : br_0_119 +* INOUT : bl_0_120 +* INOUT : br_0_120 +* INOUT : bl_0_121 +* INOUT : br_0_121 +* INOUT : bl_0_122 +* INOUT : br_0_122 +* INOUT : bl_0_123 +* INOUT : br_0_123 +* INOUT : bl_0_124 +* INOUT : br_0_124 +* INOUT : bl_0_125 +* INOUT : br_0_125 +* INOUT : bl_0_126 +* INOUT : br_0_126 +* INOUT : bl_0_127 +* INOUT : br_0_127 +* INPUT : rbl_wl_0_0 +* INPUT : wl_0_0 +* INPUT : wl_0_1 +* INPUT : wl_0_2 +* INPUT : wl_0_3 +* INPUT : wl_0_4 +* INPUT : wl_0_5 +* INPUT : wl_0_6 +* INPUT : wl_0_7 +* INPUT : wl_0_8 +* INPUT : wl_0_9 +* INPUT : wl_0_10 +* INPUT : wl_0_11 +* INPUT : wl_0_12 +* INPUT : wl_0_13 +* INPUT : wl_0_14 +* INPUT : wl_0_15 +* INPUT : wl_0_16 +* INPUT : wl_0_17 +* INPUT : wl_0_18 +* INPUT : wl_0_19 +* INPUT : wl_0_20 +* INPUT : wl_0_21 +* INPUT : wl_0_22 +* INPUT : wl_0_23 +* INPUT : wl_0_24 +* INPUT : wl_0_25 +* INPUT : wl_0_26 +* INPUT : wl_0_27 +* INPUT : wl_0_28 +* INPUT : wl_0_29 +* INPUT : wl_0_30 +* INPUT : wl_0_31 +* INPUT : wl_0_32 +* INPUT : wl_0_33 +* INPUT : wl_0_34 +* INPUT : wl_0_35 +* INPUT : wl_0_36 +* INPUT : wl_0_37 +* INPUT : wl_0_38 +* INPUT : wl_0_39 +* INPUT : wl_0_40 +* INPUT : wl_0_41 +* INPUT : wl_0_42 +* INPUT : wl_0_43 +* INPUT : wl_0_44 +* INPUT : wl_0_45 +* INPUT : wl_0_46 +* INPUT : wl_0_47 +* INPUT : wl_0_48 +* INPUT : wl_0_49 +* INPUT : wl_0_50 +* INPUT : wl_0_51 +* INPUT : wl_0_52 +* INPUT : wl_0_53 +* INPUT : wl_0_54 +* INPUT : wl_0_55 +* INPUT : wl_0_56 +* INPUT : wl_0_57 +* INPUT : wl_0_58 +* INPUT : wl_0_59 +* INPUT : wl_0_60 +* INPUT : wl_0_61 +* INPUT : wl_0_62 +* INPUT : wl_0_63 +* POWER : vdd +* GROUND: gnd +* rbl: None left_rbl: None right_rbl: None +Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array +Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column +Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 vdd gnd dummy_array +Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_1 +Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_0 +Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 +Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 +.ENDS replica_bitcell_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd +*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B +* OUTPUT: data_0 +* INPUT : bl_0 +* INPUT : br_0 +* OUTPUT: data_1 +* INPUT : bl_1 +* INPUT : br_1 +* OUTPUT: data_2 +* INPUT : bl_2 +* INPUT : br_2 +* OUTPUT: data_3 +* INPUT : bl_3 +* INPUT : br_3 +* OUTPUT: data_4 +* INPUT : bl_4 +* INPUT : br_4 +* OUTPUT: data_5 +* INPUT : bl_5 +* INPUT : br_5 +* OUTPUT: data_6 +* INPUT : bl_6 +* INPUT : br_6 +* OUTPUT: data_7 +* INPUT : bl_7 +* INPUT : br_7 +* OUTPUT: data_8 +* INPUT : bl_8 +* INPUT : br_8 +* OUTPUT: data_9 +* INPUT : bl_9 +* INPUT : br_9 +* OUTPUT: data_10 +* INPUT : bl_10 +* INPUT : br_10 +* OUTPUT: data_11 +* INPUT : bl_11 +* INPUT : br_11 +* OUTPUT: data_12 +* INPUT : bl_12 +* INPUT : br_12 +* OUTPUT: data_13 +* INPUT : bl_13 +* INPUT : br_13 +* OUTPUT: data_14 +* INPUT : bl_14 +* INPUT : br_14 +* OUTPUT: data_15 +* INPUT : bl_15 +* INPUT : br_15 +* OUTPUT: data_16 +* INPUT : bl_16 +* INPUT : br_16 +* OUTPUT: data_17 +* INPUT : bl_17 +* INPUT : br_17 +* OUTPUT: data_18 +* INPUT : bl_18 +* INPUT : br_18 +* OUTPUT: data_19 +* INPUT : bl_19 +* INPUT : br_19 +* OUTPUT: data_20 +* INPUT : bl_20 +* INPUT : br_20 +* OUTPUT: data_21 +* INPUT : bl_21 +* INPUT : br_21 +* OUTPUT: data_22 +* INPUT : bl_22 +* INPUT : br_22 +* OUTPUT: data_23 +* INPUT : bl_23 +* INPUT : br_23 +* OUTPUT: data_24 +* INPUT : bl_24 +* INPUT : br_24 +* OUTPUT: data_25 +* INPUT : bl_25 +* INPUT : br_25 +* OUTPUT: data_26 +* INPUT : bl_26 +* INPUT : br_26 +* OUTPUT: data_27 +* INPUT : bl_27 +* INPUT : br_27 +* OUTPUT: data_28 +* INPUT : bl_28 +* INPUT : br_28 +* OUTPUT: data_29 +* INPUT : bl_29 +* INPUT : br_29 +* OUTPUT: data_30 +* INPUT : bl_30 +* INPUT : br_30 +* OUTPUT: data_31 +* INPUT : bl_31 +* INPUT : br_31 +* OUTPUT: data_32 +* INPUT : bl_32 +* INPUT : br_32 +* OUTPUT: data_33 +* INPUT : bl_33 +* INPUT : br_33 +* OUTPUT: data_34 +* INPUT : bl_34 +* INPUT : br_34 +* OUTPUT: data_35 +* INPUT : bl_35 +* INPUT : br_35 +* OUTPUT: data_36 +* INPUT : bl_36 +* INPUT : br_36 +* OUTPUT: data_37 +* INPUT : bl_37 +* INPUT : br_37 +* OUTPUT: data_38 +* INPUT : bl_38 +* INPUT : br_38 +* OUTPUT: data_39 +* INPUT : bl_39 +* INPUT : br_39 +* OUTPUT: data_40 +* INPUT : bl_40 +* INPUT : br_40 +* OUTPUT: data_41 +* INPUT : bl_41 +* INPUT : br_41 +* OUTPUT: data_42 +* INPUT : bl_42 +* INPUT : br_42 +* OUTPUT: data_43 +* INPUT : bl_43 +* INPUT : br_43 +* OUTPUT: data_44 +* INPUT : bl_44 +* INPUT : br_44 +* OUTPUT: data_45 +* INPUT : bl_45 +* INPUT : br_45 +* OUTPUT: data_46 +* INPUT : bl_46 +* INPUT : br_46 +* OUTPUT: data_47 +* INPUT : bl_47 +* INPUT : br_47 +* OUTPUT: data_48 +* INPUT : bl_48 +* INPUT : br_48 +* OUTPUT: data_49 +* INPUT : bl_49 +* INPUT : br_49 +* OUTPUT: data_50 +* INPUT : bl_50 +* INPUT : br_50 +* OUTPUT: data_51 +* INPUT : bl_51 +* INPUT : br_51 +* OUTPUT: data_52 +* INPUT : bl_52 +* INPUT : br_52 +* OUTPUT: data_53 +* INPUT : bl_53 +* INPUT : br_53 +* OUTPUT: data_54 +* INPUT : bl_54 +* INPUT : br_54 +* OUTPUT: data_55 +* INPUT : bl_55 +* INPUT : br_55 +* OUTPUT: data_56 +* INPUT : bl_56 +* INPUT : br_56 +* OUTPUT: data_57 +* INPUT : bl_57 +* INPUT : br_57 +* OUTPUT: data_58 +* INPUT : bl_58 +* INPUT : br_58 +* OUTPUT: data_59 +* INPUT : bl_59 +* INPUT : br_59 +* OUTPUT: data_60 +* INPUT : bl_60 +* INPUT : br_60 +* OUTPUT: data_61 +* INPUT : bl_61 +* INPUT : br_61 +* OUTPUT: data_62 +* INPUT : bl_62 +* INPUT : br_62 +* OUTPUT: data_63 +* INPUT : bl_63 +* INPUT : br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* words_per_row: 2 +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp +Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp +Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp +Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp +Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp +Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp +Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp +Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp +Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp +Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp +Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp +Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp +Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp +Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp +Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp +Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp +Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp +Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp +Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp +Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp +Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp +Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp +Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp +Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp +Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp +Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp +Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp +Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp +Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp +Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp +Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp +Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp +Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp +Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp +Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp +Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp +Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp +Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp +Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp +Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp +Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp +Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp +Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp +Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp +Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp +Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp +Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp +Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp +Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp +Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp +Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp +Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp +Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp +Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp +Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp +Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp +Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp +Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp +Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp +Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp +Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp +Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp +.ENDS sense_amp_array + +* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT precharge_0 bl br en_bar vdd +*.PININFO bl:O br:O en_bar:I vdd:B +* OUTPUT: bl +* OUTPUT: br +* INPUT : en_bar +* POWER : vdd +Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS precharge_0 + +.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd +*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* OUTPUT: bl_64 +* OUTPUT: br_64 +* OUTPUT: bl_65 +* OUTPUT: br_65 +* OUTPUT: bl_66 +* OUTPUT: br_66 +* OUTPUT: bl_67 +* OUTPUT: br_67 +* OUTPUT: bl_68 +* OUTPUT: br_68 +* OUTPUT: bl_69 +* OUTPUT: br_69 +* OUTPUT: bl_70 +* OUTPUT: br_70 +* OUTPUT: bl_71 +* OUTPUT: br_71 +* OUTPUT: bl_72 +* OUTPUT: br_72 +* OUTPUT: bl_73 +* OUTPUT: br_73 +* OUTPUT: bl_74 +* OUTPUT: br_74 +* OUTPUT: bl_75 +* OUTPUT: br_75 +* OUTPUT: bl_76 +* OUTPUT: br_76 +* OUTPUT: bl_77 +* OUTPUT: br_77 +* OUTPUT: bl_78 +* OUTPUT: br_78 +* OUTPUT: bl_79 +* OUTPUT: br_79 +* OUTPUT: bl_80 +* OUTPUT: br_80 +* OUTPUT: bl_81 +* OUTPUT: br_81 +* OUTPUT: bl_82 +* OUTPUT: br_82 +* OUTPUT: bl_83 +* OUTPUT: br_83 +* OUTPUT: bl_84 +* OUTPUT: br_84 +* OUTPUT: bl_85 +* OUTPUT: br_85 +* OUTPUT: bl_86 +* OUTPUT: br_86 +* OUTPUT: bl_87 +* OUTPUT: br_87 +* OUTPUT: bl_88 +* OUTPUT: br_88 +* OUTPUT: bl_89 +* OUTPUT: br_89 +* OUTPUT: bl_90 +* OUTPUT: br_90 +* OUTPUT: bl_91 +* OUTPUT: br_91 +* OUTPUT: bl_92 +* OUTPUT: br_92 +* OUTPUT: bl_93 +* OUTPUT: br_93 +* OUTPUT: bl_94 +* OUTPUT: br_94 +* OUTPUT: bl_95 +* OUTPUT: br_95 +* OUTPUT: bl_96 +* OUTPUT: br_96 +* OUTPUT: bl_97 +* OUTPUT: br_97 +* OUTPUT: bl_98 +* OUTPUT: br_98 +* OUTPUT: bl_99 +* OUTPUT: br_99 +* OUTPUT: bl_100 +* OUTPUT: br_100 +* OUTPUT: bl_101 +* OUTPUT: br_101 +* OUTPUT: bl_102 +* OUTPUT: br_102 +* OUTPUT: bl_103 +* OUTPUT: br_103 +* OUTPUT: bl_104 +* OUTPUT: br_104 +* OUTPUT: bl_105 +* OUTPUT: br_105 +* OUTPUT: bl_106 +* OUTPUT: br_106 +* OUTPUT: bl_107 +* OUTPUT: br_107 +* OUTPUT: bl_108 +* OUTPUT: br_108 +* OUTPUT: bl_109 +* OUTPUT: br_109 +* OUTPUT: bl_110 +* OUTPUT: br_110 +* OUTPUT: bl_111 +* OUTPUT: br_111 +* OUTPUT: bl_112 +* OUTPUT: br_112 +* OUTPUT: bl_113 +* OUTPUT: br_113 +* OUTPUT: bl_114 +* OUTPUT: br_114 +* OUTPUT: bl_115 +* OUTPUT: br_115 +* OUTPUT: bl_116 +* OUTPUT: br_116 +* OUTPUT: bl_117 +* OUTPUT: br_117 +* OUTPUT: bl_118 +* OUTPUT: br_118 +* OUTPUT: bl_119 +* OUTPUT: br_119 +* OUTPUT: bl_120 +* OUTPUT: br_120 +* OUTPUT: bl_121 +* OUTPUT: br_121 +* OUTPUT: bl_122 +* OUTPUT: br_122 +* OUTPUT: bl_123 +* OUTPUT: br_123 +* OUTPUT: bl_124 +* OUTPUT: br_124 +* OUTPUT: bl_125 +* OUTPUT: br_125 +* OUTPUT: bl_126 +* OUTPUT: br_126 +* OUTPUT: bl_127 +* OUTPUT: br_127 +* OUTPUT: bl_128 +* OUTPUT: br_128 +* INPUT : en_bar +* POWER : vdd +* cols: 129 size: 1 bl: bl br: br +Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 +Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 +Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 +Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 +Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 +Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 +Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 +Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 +Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 +Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 +Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 +Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 +Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 +Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 +Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 +Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 +Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 +Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 +Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 +Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 +Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 +Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 +Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 +Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 +Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 +Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 +Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 +Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 +Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 +Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 +Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 +Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 +Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 +Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 +Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 +Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 +Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 +Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 +Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 +Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 +Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 +Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 +Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 +Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 +Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 +Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 +Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 +Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 +Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 +Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 +Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 +Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 +Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 +Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 +Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 +Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 +Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 +Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 +Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 +Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 +Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 +Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 +Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 +Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 +Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 +Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 +Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 +Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 +Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 +Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 +Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 +Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 +Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 +Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 +Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 +Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 +Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 +Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 +Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 +Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 +Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 +Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 +Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 +Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 +Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 +Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 +Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 +Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 +Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 +Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 +Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 +Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 +Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 +Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 +Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 +Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 +Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 +Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 +Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 +Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 +Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 +Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 +Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 +Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 +Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 +Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 +Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 +Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 +Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 +Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 +Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 +Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 +Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 +Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 +Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 +Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 +Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 +Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 +Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 +Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 +Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 +Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 +Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 +Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 +Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 +Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 +Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 +Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 +Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 +.ENDS precharge_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u + +**** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ +* pull down with en enable +M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver + +.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd +*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B +* INPUT : data_0 +* INPUT : data_1 +* INPUT : data_2 +* INPUT : data_3 +* INPUT : data_4 +* INPUT : data_5 +* INPUT : data_6 +* INPUT : data_7 +* INPUT : data_8 +* INPUT : data_9 +* INPUT : data_10 +* INPUT : data_11 +* INPUT : data_12 +* INPUT : data_13 +* INPUT : data_14 +* INPUT : data_15 +* INPUT : data_16 +* INPUT : data_17 +* INPUT : data_18 +* INPUT : data_19 +* INPUT : data_20 +* INPUT : data_21 +* INPUT : data_22 +* INPUT : data_23 +* INPUT : data_24 +* INPUT : data_25 +* INPUT : data_26 +* INPUT : data_27 +* INPUT : data_28 +* INPUT : data_29 +* INPUT : data_30 +* INPUT : data_31 +* INPUT : data_32 +* INPUT : data_33 +* INPUT : data_34 +* INPUT : data_35 +* INPUT : data_36 +* INPUT : data_37 +* INPUT : data_38 +* INPUT : data_39 +* INPUT : data_40 +* INPUT : data_41 +* INPUT : data_42 +* INPUT : data_43 +* INPUT : data_44 +* INPUT : data_45 +* INPUT : data_46 +* INPUT : data_47 +* INPUT : data_48 +* INPUT : data_49 +* INPUT : data_50 +* INPUT : data_51 +* INPUT : data_52 +* INPUT : data_53 +* INPUT : data_54 +* INPUT : data_55 +* INPUT : data_56 +* INPUT : data_57 +* INPUT : data_58 +* INPUT : data_59 +* INPUT : data_60 +* INPUT : data_61 +* INPUT : data_62 +* INPUT : data_63 +* OUTPUT: bl_0 +* OUTPUT: br_0 +* OUTPUT: bl_1 +* OUTPUT: br_1 +* OUTPUT: bl_2 +* OUTPUT: br_2 +* OUTPUT: bl_3 +* OUTPUT: br_3 +* OUTPUT: bl_4 +* OUTPUT: br_4 +* OUTPUT: bl_5 +* OUTPUT: br_5 +* OUTPUT: bl_6 +* OUTPUT: br_6 +* OUTPUT: bl_7 +* OUTPUT: br_7 +* OUTPUT: bl_8 +* OUTPUT: br_8 +* OUTPUT: bl_9 +* OUTPUT: br_9 +* OUTPUT: bl_10 +* OUTPUT: br_10 +* OUTPUT: bl_11 +* OUTPUT: br_11 +* OUTPUT: bl_12 +* OUTPUT: br_12 +* OUTPUT: bl_13 +* OUTPUT: br_13 +* OUTPUT: bl_14 +* OUTPUT: br_14 +* OUTPUT: bl_15 +* OUTPUT: br_15 +* OUTPUT: bl_16 +* OUTPUT: br_16 +* OUTPUT: bl_17 +* OUTPUT: br_17 +* OUTPUT: bl_18 +* OUTPUT: br_18 +* OUTPUT: bl_19 +* OUTPUT: br_19 +* OUTPUT: bl_20 +* OUTPUT: br_20 +* OUTPUT: bl_21 +* OUTPUT: br_21 +* OUTPUT: bl_22 +* OUTPUT: br_22 +* OUTPUT: bl_23 +* OUTPUT: br_23 +* OUTPUT: bl_24 +* OUTPUT: br_24 +* OUTPUT: bl_25 +* OUTPUT: br_25 +* OUTPUT: bl_26 +* OUTPUT: br_26 +* OUTPUT: bl_27 +* OUTPUT: br_27 +* OUTPUT: bl_28 +* OUTPUT: br_28 +* OUTPUT: bl_29 +* OUTPUT: br_29 +* OUTPUT: bl_30 +* OUTPUT: br_30 +* OUTPUT: bl_31 +* OUTPUT: br_31 +* OUTPUT: bl_32 +* OUTPUT: br_32 +* OUTPUT: bl_33 +* OUTPUT: br_33 +* OUTPUT: bl_34 +* OUTPUT: br_34 +* OUTPUT: bl_35 +* OUTPUT: br_35 +* OUTPUT: bl_36 +* OUTPUT: br_36 +* OUTPUT: bl_37 +* OUTPUT: br_37 +* OUTPUT: bl_38 +* OUTPUT: br_38 +* OUTPUT: bl_39 +* OUTPUT: br_39 +* OUTPUT: bl_40 +* OUTPUT: br_40 +* OUTPUT: bl_41 +* OUTPUT: br_41 +* OUTPUT: bl_42 +* OUTPUT: br_42 +* OUTPUT: bl_43 +* OUTPUT: br_43 +* OUTPUT: bl_44 +* OUTPUT: br_44 +* OUTPUT: bl_45 +* OUTPUT: br_45 +* OUTPUT: bl_46 +* OUTPUT: br_46 +* OUTPUT: bl_47 +* OUTPUT: br_47 +* OUTPUT: bl_48 +* OUTPUT: br_48 +* OUTPUT: bl_49 +* OUTPUT: br_49 +* OUTPUT: bl_50 +* OUTPUT: br_50 +* OUTPUT: bl_51 +* OUTPUT: br_51 +* OUTPUT: bl_52 +* OUTPUT: br_52 +* OUTPUT: bl_53 +* OUTPUT: br_53 +* OUTPUT: bl_54 +* OUTPUT: br_54 +* OUTPUT: bl_55 +* OUTPUT: br_55 +* OUTPUT: bl_56 +* OUTPUT: br_56 +* OUTPUT: bl_57 +* OUTPUT: br_57 +* OUTPUT: bl_58 +* OUTPUT: br_58 +* OUTPUT: bl_59 +* OUTPUT: br_59 +* OUTPUT: bl_60 +* OUTPUT: br_60 +* OUTPUT: bl_61 +* OUTPUT: br_61 +* OUTPUT: bl_62 +* OUTPUT: br_62 +* OUTPUT: bl_63 +* OUTPUT: br_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* word_size 64 +Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver +Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver +Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver +Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver +Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver +Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver +Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver +Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver +Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver +Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver +Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver +Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver +Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver +Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver +Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver +Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver +Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver +Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver +Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver +Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver +Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver +Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver +Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver +Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver +Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver +Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver +Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver +Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver +Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver +Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver +Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver +Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver +Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver +Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver +Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver +Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver +Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver +Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver +Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver +Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver +Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver +Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver +Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver +Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver +Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver +Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver +Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver +Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver +Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver +Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver +Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver +Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver +Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver +Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver +Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver +Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver +Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver +Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver +Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver +Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver +Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver +Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver +Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver +.ENDS write_driver_array + +* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p + +.SUBCKT column_mux bl br bl_out br_out sel gnd +*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B +* INOUT : bl +* INOUT : br +* INOUT : bl_out +* INOUT : br_out +* INOUT : sel +* INOUT : gnd +Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p +.ENDS column_mux + +.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd +*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* INOUT : sel_0 +* INOUT : sel_1 +* INOUT : bl_out_0 +* INOUT : br_out_0 +* INOUT : bl_out_1 +* INOUT : br_out_1 +* INOUT : bl_out_2 +* INOUT : br_out_2 +* INOUT : bl_out_3 +* INOUT : br_out_3 +* INOUT : bl_out_4 +* INOUT : br_out_4 +* INOUT : bl_out_5 +* INOUT : br_out_5 +* INOUT : bl_out_6 +* INOUT : br_out_6 +* INOUT : bl_out_7 +* INOUT : br_out_7 +* INOUT : bl_out_8 +* INOUT : br_out_8 +* INOUT : bl_out_9 +* INOUT : br_out_9 +* INOUT : bl_out_10 +* INOUT : br_out_10 +* INOUT : bl_out_11 +* INOUT : br_out_11 +* INOUT : bl_out_12 +* INOUT : br_out_12 +* INOUT : bl_out_13 +* INOUT : br_out_13 +* INOUT : bl_out_14 +* INOUT : br_out_14 +* INOUT : bl_out_15 +* INOUT : br_out_15 +* INOUT : bl_out_16 +* INOUT : br_out_16 +* INOUT : bl_out_17 +* INOUT : br_out_17 +* INOUT : bl_out_18 +* INOUT : br_out_18 +* INOUT : bl_out_19 +* INOUT : br_out_19 +* INOUT : bl_out_20 +* INOUT : br_out_20 +* INOUT : bl_out_21 +* INOUT : br_out_21 +* INOUT : bl_out_22 +* INOUT : br_out_22 +* INOUT : bl_out_23 +* INOUT : br_out_23 +* INOUT : bl_out_24 +* INOUT : br_out_24 +* INOUT : bl_out_25 +* INOUT : br_out_25 +* INOUT : bl_out_26 +* INOUT : br_out_26 +* INOUT : bl_out_27 +* INOUT : br_out_27 +* INOUT : bl_out_28 +* INOUT : br_out_28 +* INOUT : bl_out_29 +* INOUT : br_out_29 +* INOUT : bl_out_30 +* INOUT : br_out_30 +* INOUT : bl_out_31 +* INOUT : br_out_31 +* INOUT : bl_out_32 +* INOUT : br_out_32 +* INOUT : bl_out_33 +* INOUT : br_out_33 +* INOUT : bl_out_34 +* INOUT : br_out_34 +* INOUT : bl_out_35 +* INOUT : br_out_35 +* INOUT : bl_out_36 +* INOUT : br_out_36 +* INOUT : bl_out_37 +* INOUT : br_out_37 +* INOUT : bl_out_38 +* INOUT : br_out_38 +* INOUT : bl_out_39 +* INOUT : br_out_39 +* INOUT : bl_out_40 +* INOUT : br_out_40 +* INOUT : bl_out_41 +* INOUT : br_out_41 +* INOUT : bl_out_42 +* INOUT : br_out_42 +* INOUT : bl_out_43 +* INOUT : br_out_43 +* INOUT : bl_out_44 +* INOUT : br_out_44 +* INOUT : bl_out_45 +* INOUT : br_out_45 +* INOUT : bl_out_46 +* INOUT : br_out_46 +* INOUT : bl_out_47 +* INOUT : br_out_47 +* INOUT : bl_out_48 +* INOUT : br_out_48 +* INOUT : bl_out_49 +* INOUT : br_out_49 +* INOUT : bl_out_50 +* INOUT : br_out_50 +* INOUT : bl_out_51 +* INOUT : br_out_51 +* INOUT : bl_out_52 +* INOUT : br_out_52 +* INOUT : bl_out_53 +* INOUT : br_out_53 +* INOUT : bl_out_54 +* INOUT : br_out_54 +* INOUT : bl_out_55 +* INOUT : br_out_55 +* INOUT : bl_out_56 +* INOUT : br_out_56 +* INOUT : bl_out_57 +* INOUT : br_out_57 +* INOUT : bl_out_58 +* INOUT : br_out_58 +* INOUT : bl_out_59 +* INOUT : br_out_59 +* INOUT : bl_out_60 +* INOUT : br_out_60 +* INOUT : bl_out_61 +* INOUT : br_out_61 +* INOUT : bl_out_62 +* INOUT : br_out_62 +* INOUT : bl_out_63 +* INOUT : br_out_63 +* INOUT : gnd +* cols: 128 word_size: 64 bl: bl br: br +XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux +XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux +XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux +XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux +XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux +XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux +XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux +XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux +XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux +XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux +XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux +XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux +XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux +XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux +XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux +XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux +XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux +XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux +XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux +XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux +XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux +XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux +XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux +XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux +XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux +XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux +XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux +XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux +XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux +XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux +XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux +XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux +XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux +XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux +XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux +XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux +XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux +XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux +XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux +XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux +XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux +XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux +XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux +XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux +XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux +XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux +XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux +XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux +XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux +XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux +XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux +XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux +XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux +XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux +XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux +XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux +XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux +XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux +XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux +XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux +XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux +XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux +XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux +XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux +XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux +XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux +XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux +XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux +XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux +XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux +XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux +XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux +XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux +XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux +XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux +XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux +XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux +XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux +XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux +XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux +XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux +XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux +XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux +XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux +XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux +XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux +XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux +XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux +XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux +XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux +XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux +XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux +XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux +XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux +XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux +XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux +XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux +XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux +XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux +XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux +XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux +XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux +XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux +XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux +XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux +XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux +XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux +XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux +XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux +XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux +XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux +XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux +XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux +XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux +XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux +XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux +XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux +XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux +XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux +XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux +XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux +XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux +XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux +XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux +XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux +XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux +XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux +XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux +.ENDS column_mux_array + +.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd +*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B +* INOUT : rbl_bl +* INOUT : rbl_br +* INOUT : bl_0 +* INOUT : br_0 +* INOUT : bl_1 +* INOUT : br_1 +* INOUT : bl_2 +* INOUT : br_2 +* INOUT : bl_3 +* INOUT : br_3 +* INOUT : bl_4 +* INOUT : br_4 +* INOUT : bl_5 +* INOUT : br_5 +* INOUT : bl_6 +* INOUT : br_6 +* INOUT : bl_7 +* INOUT : br_7 +* INOUT : bl_8 +* INOUT : br_8 +* INOUT : bl_9 +* INOUT : br_9 +* INOUT : bl_10 +* INOUT : br_10 +* INOUT : bl_11 +* INOUT : br_11 +* INOUT : bl_12 +* INOUT : br_12 +* INOUT : bl_13 +* INOUT : br_13 +* INOUT : bl_14 +* INOUT : br_14 +* INOUT : bl_15 +* INOUT : br_15 +* INOUT : bl_16 +* INOUT : br_16 +* INOUT : bl_17 +* INOUT : br_17 +* INOUT : bl_18 +* INOUT : br_18 +* INOUT : bl_19 +* INOUT : br_19 +* INOUT : bl_20 +* INOUT : br_20 +* INOUT : bl_21 +* INOUT : br_21 +* INOUT : bl_22 +* INOUT : br_22 +* INOUT : bl_23 +* INOUT : br_23 +* INOUT : bl_24 +* INOUT : br_24 +* INOUT : bl_25 +* INOUT : br_25 +* INOUT : bl_26 +* INOUT : br_26 +* INOUT : bl_27 +* INOUT : br_27 +* INOUT : bl_28 +* INOUT : br_28 +* INOUT : bl_29 +* INOUT : br_29 +* INOUT : bl_30 +* INOUT : br_30 +* INOUT : bl_31 +* INOUT : br_31 +* INOUT : bl_32 +* INOUT : br_32 +* INOUT : bl_33 +* INOUT : br_33 +* INOUT : bl_34 +* INOUT : br_34 +* INOUT : bl_35 +* INOUT : br_35 +* INOUT : bl_36 +* INOUT : br_36 +* INOUT : bl_37 +* INOUT : br_37 +* INOUT : bl_38 +* INOUT : br_38 +* INOUT : bl_39 +* INOUT : br_39 +* INOUT : bl_40 +* INOUT : br_40 +* INOUT : bl_41 +* INOUT : br_41 +* INOUT : bl_42 +* INOUT : br_42 +* INOUT : bl_43 +* INOUT : br_43 +* INOUT : bl_44 +* INOUT : br_44 +* INOUT : bl_45 +* INOUT : br_45 +* INOUT : bl_46 +* INOUT : br_46 +* INOUT : bl_47 +* INOUT : br_47 +* INOUT : bl_48 +* INOUT : br_48 +* INOUT : bl_49 +* INOUT : br_49 +* INOUT : bl_50 +* INOUT : br_50 +* INOUT : bl_51 +* INOUT : br_51 +* INOUT : bl_52 +* INOUT : br_52 +* INOUT : bl_53 +* INOUT : br_53 +* INOUT : bl_54 +* INOUT : br_54 +* INOUT : bl_55 +* INOUT : br_55 +* INOUT : bl_56 +* INOUT : br_56 +* INOUT : bl_57 +* INOUT : br_57 +* INOUT : bl_58 +* INOUT : br_58 +* INOUT : bl_59 +* INOUT : br_59 +* INOUT : bl_60 +* INOUT : br_60 +* INOUT : bl_61 +* INOUT : br_61 +* INOUT : bl_62 +* INOUT : br_62 +* INOUT : bl_63 +* INOUT : br_63 +* INOUT : bl_64 +* INOUT : br_64 +* INOUT : bl_65 +* INOUT : br_65 +* INOUT : bl_66 +* INOUT : br_66 +* INOUT : bl_67 +* INOUT : br_67 +* INOUT : bl_68 +* INOUT : br_68 +* INOUT : bl_69 +* INOUT : br_69 +* INOUT : bl_70 +* INOUT : br_70 +* INOUT : bl_71 +* INOUT : br_71 +* INOUT : bl_72 +* INOUT : br_72 +* INOUT : bl_73 +* INOUT : br_73 +* INOUT : bl_74 +* INOUT : br_74 +* INOUT : bl_75 +* INOUT : br_75 +* INOUT : bl_76 +* INOUT : br_76 +* INOUT : bl_77 +* INOUT : br_77 +* INOUT : bl_78 +* INOUT : br_78 +* INOUT : bl_79 +* INOUT : br_79 +* INOUT : bl_80 +* INOUT : br_80 +* INOUT : bl_81 +* INOUT : br_81 +* INOUT : bl_82 +* INOUT : br_82 +* INOUT : bl_83 +* INOUT : br_83 +* INOUT : bl_84 +* INOUT : br_84 +* INOUT : bl_85 +* INOUT : br_85 +* INOUT : bl_86 +* INOUT : br_86 +* INOUT : bl_87 +* INOUT : br_87 +* INOUT : bl_88 +* INOUT : br_88 +* INOUT : bl_89 +* INOUT : br_89 +* INOUT : bl_90 +* INOUT : br_90 +* INOUT : bl_91 +* INOUT : br_91 +* INOUT : bl_92 +* INOUT : br_92 +* INOUT : bl_93 +* INOUT : br_93 +* INOUT : bl_94 +* INOUT : br_94 +* INOUT : bl_95 +* INOUT : br_95 +* INOUT : bl_96 +* INOUT : br_96 +* INOUT : bl_97 +* INOUT : br_97 +* INOUT : bl_98 +* INOUT : br_98 +* INOUT : bl_99 +* INOUT : br_99 +* INOUT : bl_100 +* INOUT : br_100 +* INOUT : bl_101 +* INOUT : br_101 +* INOUT : bl_102 +* INOUT : br_102 +* INOUT : bl_103 +* INOUT : br_103 +* INOUT : bl_104 +* INOUT : br_104 +* INOUT : bl_105 +* INOUT : br_105 +* INOUT : bl_106 +* INOUT : br_106 +* INOUT : bl_107 +* INOUT : br_107 +* INOUT : bl_108 +* INOUT : br_108 +* INOUT : bl_109 +* INOUT : br_109 +* INOUT : bl_110 +* INOUT : br_110 +* INOUT : bl_111 +* INOUT : br_111 +* INOUT : bl_112 +* INOUT : br_112 +* INOUT : bl_113 +* INOUT : br_113 +* INOUT : bl_114 +* INOUT : br_114 +* INOUT : bl_115 +* INOUT : br_115 +* INOUT : bl_116 +* INOUT : br_116 +* INOUT : bl_117 +* INOUT : br_117 +* INOUT : bl_118 +* INOUT : br_118 +* INOUT : bl_119 +* INOUT : br_119 +* INOUT : bl_120 +* INOUT : br_120 +* INOUT : bl_121 +* INOUT : br_121 +* INOUT : bl_122 +* INOUT : br_122 +* INOUT : bl_123 +* INOUT : br_123 +* INOUT : bl_124 +* INOUT : br_124 +* INOUT : bl_125 +* INOUT : br_125 +* INOUT : bl_126 +* INOUT : br_126 +* INOUT : bl_127 +* INOUT : br_127 +* OUTPUT: dout_0 +* OUTPUT: dout_1 +* OUTPUT: dout_2 +* OUTPUT: dout_3 +* OUTPUT: dout_4 +* OUTPUT: dout_5 +* OUTPUT: dout_6 +* OUTPUT: dout_7 +* OUTPUT: dout_8 +* OUTPUT: dout_9 +* OUTPUT: dout_10 +* OUTPUT: dout_11 +* OUTPUT: dout_12 +* OUTPUT: dout_13 +* OUTPUT: dout_14 +* OUTPUT: dout_15 +* OUTPUT: dout_16 +* OUTPUT: dout_17 +* OUTPUT: dout_18 +* OUTPUT: dout_19 +* OUTPUT: dout_20 +* OUTPUT: dout_21 +* OUTPUT: dout_22 +* OUTPUT: dout_23 +* OUTPUT: dout_24 +* OUTPUT: dout_25 +* OUTPUT: dout_26 +* OUTPUT: dout_27 +* OUTPUT: dout_28 +* OUTPUT: dout_29 +* OUTPUT: dout_30 +* OUTPUT: dout_31 +* OUTPUT: dout_32 +* OUTPUT: dout_33 +* OUTPUT: dout_34 +* OUTPUT: dout_35 +* OUTPUT: dout_36 +* OUTPUT: dout_37 +* OUTPUT: dout_38 +* OUTPUT: dout_39 +* OUTPUT: dout_40 +* OUTPUT: dout_41 +* OUTPUT: dout_42 +* OUTPUT: dout_43 +* OUTPUT: dout_44 +* OUTPUT: dout_45 +* OUTPUT: dout_46 +* OUTPUT: dout_47 +* OUTPUT: dout_48 +* OUTPUT: dout_49 +* OUTPUT: dout_50 +* OUTPUT: dout_51 +* OUTPUT: dout_52 +* OUTPUT: dout_53 +* OUTPUT: dout_54 +* OUTPUT: dout_55 +* OUTPUT: dout_56 +* OUTPUT: dout_57 +* OUTPUT: dout_58 +* OUTPUT: dout_59 +* OUTPUT: dout_60 +* OUTPUT: dout_61 +* OUTPUT: dout_62 +* OUTPUT: dout_63 +* INPUT : din_0 +* INPUT : din_1 +* INPUT : din_2 +* INPUT : din_3 +* INPUT : din_4 +* INPUT : din_5 +* INPUT : din_6 +* INPUT : din_7 +* INPUT : din_8 +* INPUT : din_9 +* INPUT : din_10 +* INPUT : din_11 +* INPUT : din_12 +* INPUT : din_13 +* INPUT : din_14 +* INPUT : din_15 +* INPUT : din_16 +* INPUT : din_17 +* INPUT : din_18 +* INPUT : din_19 +* INPUT : din_20 +* INPUT : din_21 +* INPUT : din_22 +* INPUT : din_23 +* INPUT : din_24 +* INPUT : din_25 +* INPUT : din_26 +* INPUT : din_27 +* INPUT : din_28 +* INPUT : din_29 +* INPUT : din_30 +* INPUT : din_31 +* INPUT : din_32 +* INPUT : din_33 +* INPUT : din_34 +* INPUT : din_35 +* INPUT : din_36 +* INPUT : din_37 +* INPUT : din_38 +* INPUT : din_39 +* INPUT : din_40 +* INPUT : din_41 +* INPUT : din_42 +* INPUT : din_43 +* INPUT : din_44 +* INPUT : din_45 +* INPUT : din_46 +* INPUT : din_47 +* INPUT : din_48 +* INPUT : din_49 +* INPUT : din_50 +* INPUT : din_51 +* INPUT : din_52 +* INPUT : din_53 +* INPUT : din_54 +* INPUT : din_55 +* INPUT : din_56 +* INPUT : din_57 +* INPUT : din_58 +* INPUT : din_59 +* INPUT : din_60 +* INPUT : din_61 +* INPUT : din_62 +* INPUT : din_63 +* INPUT : sel_0 +* INPUT : sel_1 +* INPUT : s_en +* INPUT : p_en_bar +* INPUT : w_en +* POWER : vdd +* GROUND: gnd +Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array +Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array +Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array +Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array +.ENDS port_data + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2 + +* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p + +.SUBCKT pinv_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p +.ENDS pinv_0 + +.SUBCKT and2_dec_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 32 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv_0 +.ENDS and2_dec_0 + +.SUBCKT wordline_driver A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xwld_nand A B zb_int vdd gnd pnand2 +Xwl_driver zb_int Z vdd gnd pinv_0 +.ENDS wordline_driver + +.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd +*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* INPUT : in_2 +* INPUT : in_3 +* INPUT : in_4 +* INPUT : in_5 +* INPUT : in_6 +* INPUT : in_7 +* INPUT : in_8 +* INPUT : in_9 +* INPUT : in_10 +* INPUT : in_11 +* INPUT : in_12 +* INPUT : in_13 +* INPUT : in_14 +* INPUT : in_15 +* INPUT : in_16 +* INPUT : in_17 +* INPUT : in_18 +* INPUT : in_19 +* INPUT : in_20 +* INPUT : in_21 +* INPUT : in_22 +* INPUT : in_23 +* INPUT : in_24 +* INPUT : in_25 +* INPUT : in_26 +* INPUT : in_27 +* INPUT : in_28 +* INPUT : in_29 +* INPUT : in_30 +* INPUT : in_31 +* INPUT : in_32 +* INPUT : in_33 +* INPUT : in_34 +* INPUT : in_35 +* INPUT : in_36 +* INPUT : in_37 +* INPUT : in_38 +* INPUT : in_39 +* INPUT : in_40 +* INPUT : in_41 +* INPUT : in_42 +* INPUT : in_43 +* INPUT : in_44 +* INPUT : in_45 +* INPUT : in_46 +* INPUT : in_47 +* INPUT : in_48 +* INPUT : in_49 +* INPUT : in_50 +* INPUT : in_51 +* INPUT : in_52 +* INPUT : in_53 +* INPUT : in_54 +* INPUT : in_55 +* INPUT : in_56 +* INPUT : in_57 +* INPUT : in_58 +* INPUT : in_59 +* INPUT : in_60 +* INPUT : in_61 +* INPUT : in_62 +* INPUT : in_63 +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* INPUT : en +* POWER : vdd +* GROUND: gnd +* rows: 64 cols: 128 +Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver +Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver +Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver +Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver +Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver +Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver +Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver +Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver +Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver +Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver +Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver +Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver +Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver +Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver +Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver +Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver +Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver +Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver +Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver +Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver +Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver +Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver +Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver +Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver +Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver +Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver +Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver +Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver +Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver +Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver +Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver +Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver +Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver +Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver +Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver +Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver +Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver +Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver +Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver +Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver +Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver +Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver +Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver +Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver +Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver +Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver +Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver +Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver +Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver +Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver +Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver +Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver +Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver +Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver +Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver +Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver +Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver +Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver +Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver +Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver +Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver +Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver +Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver +Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver +.ENDS wordline_driver_array + +.SUBCKT pinv A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv + +* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p + +.SUBCKT pnand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3 + +.SUBCKT and3_dec A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand3_dec_nand A B C zb_int vdd gnd pnand3 +Xpand3_dec_inv zb_int Z vdd gnd pinv +.ENDS and3_dec + +.SUBCKT and2_dec A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* size: 1 +Xpand2_dec_nand A B zb_int vdd gnd pnand2 +Xpand2_dec_inv zb_int Z vdd gnd pinv +.ENDS and2_dec + +.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B +* INPUT : in_0 +* INPUT : in_1 +* OUTPUT: out_0 +* OUTPUT: out_1 +* OUTPUT: out_2 +* OUTPUT: out_3 +* POWER : vdd +* GROUND: gnd +Xpre_inv_0 in_0 inbar_0 vdd gnd pinv +Xpre_inv_1 in_1 inbar_1 vdd gnd pinv +XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec +XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec +XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec +XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec +.ENDS hierarchical_predecode2x4 + +.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* OUTPUT: decode_0 +* OUTPUT: decode_1 +* OUTPUT: decode_2 +* OUTPUT: decode_3 +* OUTPUT: decode_4 +* OUTPUT: decode_5 +* OUTPUT: decode_6 +* OUTPUT: decode_7 +* OUTPUT: decode_8 +* OUTPUT: decode_9 +* OUTPUT: decode_10 +* OUTPUT: decode_11 +* OUTPUT: decode_12 +* OUTPUT: decode_13 +* OUTPUT: decode_14 +* OUTPUT: decode_15 +* OUTPUT: decode_16 +* OUTPUT: decode_17 +* OUTPUT: decode_18 +* OUTPUT: decode_19 +* OUTPUT: decode_20 +* OUTPUT: decode_21 +* OUTPUT: decode_22 +* OUTPUT: decode_23 +* OUTPUT: decode_24 +* OUTPUT: decode_25 +* OUTPUT: decode_26 +* OUTPUT: decode_27 +* OUTPUT: decode_28 +* OUTPUT: decode_29 +* OUTPUT: decode_30 +* OUTPUT: decode_31 +* OUTPUT: decode_32 +* OUTPUT: decode_33 +* OUTPUT: decode_34 +* OUTPUT: decode_35 +* OUTPUT: decode_36 +* OUTPUT: decode_37 +* OUTPUT: decode_38 +* OUTPUT: decode_39 +* OUTPUT: decode_40 +* OUTPUT: decode_41 +* OUTPUT: decode_42 +* OUTPUT: decode_43 +* OUTPUT: decode_44 +* OUTPUT: decode_45 +* OUTPUT: decode_46 +* OUTPUT: decode_47 +* OUTPUT: decode_48 +* OUTPUT: decode_49 +* OUTPUT: decode_50 +* OUTPUT: decode_51 +* OUTPUT: decode_52 +* OUTPUT: decode_53 +* OUTPUT: decode_54 +* OUTPUT: decode_55 +* OUTPUT: decode_56 +* OUTPUT: decode_57 +* OUTPUT: decode_58 +* OUTPUT: decode_59 +* OUTPUT: decode_60 +* OUTPUT: decode_61 +* OUTPUT: decode_62 +* OUTPUT: decode_63 +* POWER : vdd +* GROUND: gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 +Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 +XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec +XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec +XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec +XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec +XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec +XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec +XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec +XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec +XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec +XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec +XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec +XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec +XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec +XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec +XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec +XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec +XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec +XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec +XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec +XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec +XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec +XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec +XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec +XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec +XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec +XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec +XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec +XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec +XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec +XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec +XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec +XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec +XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec +XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec +XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec +XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec +XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec +XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec +XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec +XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec +XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec +XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec +XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec +XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec +XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec +XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec +XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec +XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec +XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec +XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec +XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec +XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec +XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec +XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec +XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec +XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec +XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec +XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec +XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec +XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec +XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec +XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec +XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec +XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec +.ENDS hierarchical_decoder + +.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd +*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B +* INPUT : addr_0 +* INPUT : addr_1 +* INPUT : addr_2 +* INPUT : addr_3 +* INPUT : addr_4 +* INPUT : addr_5 +* INPUT : wl_en +* OUTPUT: wl_0 +* OUTPUT: wl_1 +* OUTPUT: wl_2 +* OUTPUT: wl_3 +* OUTPUT: wl_4 +* OUTPUT: wl_5 +* OUTPUT: wl_6 +* OUTPUT: wl_7 +* OUTPUT: wl_8 +* OUTPUT: wl_9 +* OUTPUT: wl_10 +* OUTPUT: wl_11 +* OUTPUT: wl_12 +* OUTPUT: wl_13 +* OUTPUT: wl_14 +* OUTPUT: wl_15 +* OUTPUT: wl_16 +* OUTPUT: wl_17 +* OUTPUT: wl_18 +* OUTPUT: wl_19 +* OUTPUT: wl_20 +* OUTPUT: wl_21 +* OUTPUT: wl_22 +* OUTPUT: wl_23 +* OUTPUT: wl_24 +* OUTPUT: wl_25 +* OUTPUT: wl_26 +* OUTPUT: wl_27 +* OUTPUT: wl_28 +* OUTPUT: wl_29 +* OUTPUT: wl_30 +* OUTPUT: wl_31 +* OUTPUT: wl_32 +* OUTPUT: wl_33 +* OUTPUT: wl_34 +* OUTPUT: wl_35 +* OUTPUT: wl_36 +* OUTPUT: wl_37 +* OUTPUT: wl_38 +* OUTPUT: wl_39 +* OUTPUT: wl_40 +* OUTPUT: wl_41 +* OUTPUT: wl_42 +* OUTPUT: wl_43 +* OUTPUT: wl_44 +* OUTPUT: wl_45 +* OUTPUT: wl_46 +* OUTPUT: wl_47 +* OUTPUT: wl_48 +* OUTPUT: wl_49 +* OUTPUT: wl_50 +* OUTPUT: wl_51 +* OUTPUT: wl_52 +* OUTPUT: wl_53 +* OUTPUT: wl_54 +* OUTPUT: wl_55 +* OUTPUT: wl_56 +* OUTPUT: wl_57 +* OUTPUT: wl_58 +* OUTPUT: wl_59 +* OUTPUT: wl_60 +* OUTPUT: wl_61 +* OUTPUT: wl_62 +* OUTPUT: wl_63 +* OUTPUT: rbl_wl +* POWER : vdd +* GROUND: gnd +Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder +Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array +Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 +.ENDS port_address + +.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd +*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B +* OUTPUT: dout0_0 +* OUTPUT: dout0_1 +* OUTPUT: dout0_2 +* OUTPUT: dout0_3 +* OUTPUT: dout0_4 +* OUTPUT: dout0_5 +* OUTPUT: dout0_6 +* OUTPUT: dout0_7 +* OUTPUT: dout0_8 +* OUTPUT: dout0_9 +* OUTPUT: dout0_10 +* OUTPUT: dout0_11 +* OUTPUT: dout0_12 +* OUTPUT: dout0_13 +* OUTPUT: dout0_14 +* OUTPUT: dout0_15 +* OUTPUT: dout0_16 +* OUTPUT: dout0_17 +* OUTPUT: dout0_18 +* OUTPUT: dout0_19 +* OUTPUT: dout0_20 +* OUTPUT: dout0_21 +* OUTPUT: dout0_22 +* OUTPUT: dout0_23 +* OUTPUT: dout0_24 +* OUTPUT: dout0_25 +* OUTPUT: dout0_26 +* OUTPUT: dout0_27 +* OUTPUT: dout0_28 +* OUTPUT: dout0_29 +* OUTPUT: dout0_30 +* OUTPUT: dout0_31 +* OUTPUT: dout0_32 +* OUTPUT: dout0_33 +* OUTPUT: dout0_34 +* OUTPUT: dout0_35 +* OUTPUT: dout0_36 +* OUTPUT: dout0_37 +* OUTPUT: dout0_38 +* OUTPUT: dout0_39 +* OUTPUT: dout0_40 +* OUTPUT: dout0_41 +* OUTPUT: dout0_42 +* OUTPUT: dout0_43 +* OUTPUT: dout0_44 +* OUTPUT: dout0_45 +* OUTPUT: dout0_46 +* OUTPUT: dout0_47 +* OUTPUT: dout0_48 +* OUTPUT: dout0_49 +* OUTPUT: dout0_50 +* OUTPUT: dout0_51 +* OUTPUT: dout0_52 +* OUTPUT: dout0_53 +* OUTPUT: dout0_54 +* OUTPUT: dout0_55 +* OUTPUT: dout0_56 +* OUTPUT: dout0_57 +* OUTPUT: dout0_58 +* OUTPUT: dout0_59 +* OUTPUT: dout0_60 +* OUTPUT: dout0_61 +* OUTPUT: dout0_62 +* OUTPUT: dout0_63 +* OUTPUT: rbl_bl_0_0 +* INPUT : din0_0 +* INPUT : din0_1 +* INPUT : din0_2 +* INPUT : din0_3 +* INPUT : din0_4 +* INPUT : din0_5 +* INPUT : din0_6 +* INPUT : din0_7 +* INPUT : din0_8 +* INPUT : din0_9 +* INPUT : din0_10 +* INPUT : din0_11 +* INPUT : din0_12 +* INPUT : din0_13 +* INPUT : din0_14 +* INPUT : din0_15 +* INPUT : din0_16 +* INPUT : din0_17 +* INPUT : din0_18 +* INPUT : din0_19 +* INPUT : din0_20 +* INPUT : din0_21 +* INPUT : din0_22 +* INPUT : din0_23 +* INPUT : din0_24 +* INPUT : din0_25 +* INPUT : din0_26 +* INPUT : din0_27 +* INPUT : din0_28 +* INPUT : din0_29 +* INPUT : din0_30 +* INPUT : din0_31 +* INPUT : din0_32 +* INPUT : din0_33 +* INPUT : din0_34 +* INPUT : din0_35 +* INPUT : din0_36 +* INPUT : din0_37 +* INPUT : din0_38 +* INPUT : din0_39 +* INPUT : din0_40 +* INPUT : din0_41 +* INPUT : din0_42 +* INPUT : din0_43 +* INPUT : din0_44 +* INPUT : din0_45 +* INPUT : din0_46 +* INPUT : din0_47 +* INPUT : din0_48 +* INPUT : din0_49 +* INPUT : din0_50 +* INPUT : din0_51 +* INPUT : din0_52 +* INPUT : din0_53 +* INPUT : din0_54 +* INPUT : din0_55 +* INPUT : din0_56 +* INPUT : din0_57 +* INPUT : din0_58 +* INPUT : din0_59 +* INPUT : din0_60 +* INPUT : din0_61 +* INPUT : din0_62 +* INPUT : din0_63 +* INPUT : addr0_0 +* INPUT : addr0_1 +* INPUT : addr0_2 +* INPUT : addr0_3 +* INPUT : addr0_4 +* INPUT : addr0_5 +* INPUT : addr0_6 +* INPUT : s_en0 +* INPUT : p_en_bar0 +* INPUT : w_en0 +* INPUT : wl_en0 +* POWER : vdd +* GROUND: gnd +Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array +Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data +Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address +Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf +.ENDS bank + +.SUBCKT dff_buf_0 D Q Qb clk vdd gnd +*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B +* INPUT : D +* OUTPUT: Q +* OUTPUT: Qb +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_buf_dff D qint clk vdd gnd dff +Xdff_buf_inv1 qint Qb vdd gnd pinv_2 +Xdff_buf_inv2 Qb Q vdd gnd pinv_3 +.ENDS dff_buf_0 + +.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B +* INPUT : din_0 +* INPUT : din_1 +* OUTPUT: dout_0 +* OUTPUT: dout_bar_0 +* OUTPUT: dout_1 +* OUTPUT: dout_bar_1 +* INPUT : clk +* POWER : vdd +* GROUND: gnd +* inv1: 2 inv2: 4 +Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 +Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 +.ENDS dff_buf_array + +.SUBCKT pnand2_0 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_0 + +* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p + +* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p + +.SUBCKT pinv_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p +Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p +.ENDS pinv_4 + +.SUBCKT pdriver A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [12] +Xbuf_inv1 A Z vdd gnd pinv_4 +.ENDS pdriver + +.SUBCKT pand2 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand2_nand A B zb_int vdd gnd pnand2_0 +Xpand2_inv zb_int Z vdd gnd pdriver +.ENDS pand2 + +* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p + +.SUBCKT pinv_11 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p +Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p +.ENDS pinv_11 + +* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p + +* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p + +.SUBCKT pinv_9 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p +Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p +.ENDS pinv_9 + +* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p + +.SUBCKT pinv_10 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p +Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +.ENDS pinv_10 + +* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p + +* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p + +.SUBCKT pinv_12 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p +Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p +.ENDS pinv_12 + +.SUBCKT pinv_7 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_7 + +.SUBCKT pinv_8 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pinv_8 + +.SUBCKT pdriver_0 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 1, 2, 5, 14, 42, 125] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 +Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 +Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 +Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 +.ENDS pdriver_0 + +.SUBCKT pnand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand3_0 + +* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p + +* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p + +.SUBCKT pinv_16 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p +Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p +.ENDS pinv_16 + +.SUBCKT pdriver_3 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [64] +Xbuf_inv1 A Z vdd gnd pinv_16 +.ENDS pdriver_3 + +.SUBCKT pand3_0 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_3 +.ENDS pand3_0 + +.SUBCKT pinv_17 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_17 + +* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p + +* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p + +.SUBCKT pinv_18 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p +Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p +.ENDS pinv_18 + +.SUBCKT pdriver_4 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [1, 1, 2, 5, 14, 43] +Xbuf_inv1 A Zb1_int vdd gnd pinv_7 +Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 +Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 +Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 +Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 +Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 +.ENDS pdriver_4 + +* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p + +* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p + +.SUBCKT pinv_15 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p +Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p +.ENDS pinv_15 + +.SUBCKT pdriver_2 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [72] +Xbuf_inv1 A Z vdd gnd pinv_15 +.ENDS pdriver_2 + +.SUBCKT pand3 A B C Z vdd gnd +*.PININFO A:I B:I C:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* INPUT : C +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Xpand3_nand A B C zb_int vdd gnd pnand3_0 +Xpand3_inv zb_int Z vdd gnd pdriver_2 +.ENDS pand3 + +.SUBCKT pinv_19 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p +.ENDS pinv_19 + +.SUBCKT delay_chain in out vdd gnd +*.PININFO in:I out:O vdd:B gnd:B +* INPUT : in +* OUTPUT: out +* POWER : vdd +* GROUND: gnd +* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] +Xdinv0 in dout_1 vdd gnd pinv_19 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 +Xdinv1 dout_1 dout_2 vdd gnd pinv_19 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 +Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 +Xdinv2 dout_2 dout_3 vdd gnd pinv_19 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 +Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 +Xdinv3 dout_3 dout_4 vdd gnd pinv_19 +Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 +Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 +Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 +Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 +Xdinv4 dout_4 dout_5 vdd gnd pinv_19 +Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 +Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 +Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 +Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 +Xdinv5 dout_5 dout_6 vdd gnd pinv_19 +Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 +Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 +Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 +Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 +Xdinv6 dout_6 dout_7 vdd gnd pinv_19 +Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 +Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 +Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 +Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 +Xdinv7 dout_7 dout_8 vdd gnd pinv_19 +Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 +Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 +Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 +Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 +Xdinv8 dout_8 out vdd gnd pinv_19 +Xdload_8_0 out n_8_0 vdd gnd pinv_19 +Xdload_8_1 out n_8_1 vdd gnd pinv_19 +Xdload_8_2 out n_8_2 vdd gnd pinv_19 +Xdload_8_3 out n_8_3 vdd gnd pinv_19 +.ENDS delay_chain + +* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p + +* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p + +.SUBCKT pinv_14 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p +Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p +.ENDS pinv_14 + +* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p + +* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p + +.SUBCKT pinv_13 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p +Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p +.ENDS pinv_13 + +.SUBCKT pdriver_1 A Z vdd gnd +*.PININFO A:I Z:O vdd:B gnd:B +* INPUT : A +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +* sizes: [7, 21] +Xbuf_inv1 A Zb1_int vdd gnd pinv_13 +Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 +.ENDS pdriver_1 + +.SUBCKT pnand2_1 A B Z vdd gnd +*.PININFO A:I B:I Z:O vdd:B gnd:B +* INPUT : A +* INPUT : B +* OUTPUT: Z +* POWER : vdd +* GROUND: gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p +.ENDS pnand2_1 + +* Used for tiling delay chain to desired length +.SUBCKT delay_chain_segment in out vdd gnd +Xdinv0 in dout_1 vdd gnd pinv_11 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 +Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 +Xdinv1 dout_1 out vdd gnd pinv_11 +Xdload_1_0 out n_1_0 vdd gnd pinv_11 +Xdload_1_1 out n_1_1 vdd gnd pinv_11 +Xdload_1_2 out n_1_2 vdd gnd pinv_11 +Xdload_1_3 out n_1_3 vdd gnd pinv_11 +.ENDS delay_chain_segment + +.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd +Xdelay1 in out1 vdd gnd delay_chain_segment +Xdelay2 out1 out2 vdd gnd delay_chain_segment +Xdelay3 out2 out3 vdd gnd delay_chain_segment +Xdelay4 out3 out4 vdd gnd delay_chain_segment +Xdelay5 out4 out5 vdd gnd delay_chain_segment +Xdelay6 out5 out6 vdd gnd delay_chain_segment +Xdelay7 out6 out7 vdd gnd delay_chain_segment +Xdelay8 out7 out8 vdd gnd delay_chain_segment +Xdelay9 out8 out9 vdd gnd delay_chain_segment +Xdelay10 out9 out10 vdd gnd delay_chain_segment +Xdelay11 out10 out11 vdd gnd delay_chain_segment +Xdelay12 out11 out12 vdd gnd delay_chain_segment +Xdelay13 out12 out13 vdd gnd delay_chain_segment +Xdelay14 out13 out14 vdd gnd delay_chain_segment +Xdelay15 out14 out15 vdd gnd delay_chain_segment +Xdelay16 out15 out16 vdd gnd delay_chain_segment +.ENDS multi_delay_chain + +.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd +*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B +* INPUT : csb +* INPUT : web +* INPUT : clk +* INPUT : rbl_bl (NO LONGER USED) +* OUTPUT: s_en +* OUTPUT: w_en +* OUTPUT: p_en_bar +* OUTPUT: wl_en +* OUTPUT: clk_buf +* POWER : vdd +* GROUND: gnd +* word_size 2 +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array +Xmulti_delay_chain gated_clk_buf out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain +Xinv_glitch1 out6 g1_end vdd gnd pinv_11 +Xinv_glitch2 out7 g2_end vdd gnd pinv_11 +Xinv_glitch3 out14 g3_end vdd gnd pinv_11 +Xnand2_glitch1 out1 g1_end glitch1_bar vdd gnd pnand2 +Xnand2_glitch2 gated_clk_buf g2_end glitch2_bar vdd gnd pnand2 +Xnand2_glitch3 out6 g3_end glitch3_bar vdd gnd pnand2 +Xinv_glitch3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 +* is cs_buf needed on larger memories? I don't remember why I needed this for small mems. Some timing bs surely +* I have a feeling this was another misguided workaround to proper gate sizing smh my head bruh +Xbuf_cs cs cs_buf vdd gnd pdriver_0 +Xclkbuf clk clk_buf vdd gnd pdriver_0 +Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 +Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 +Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 +* uhhhh do I really need this?? can't I just roll this into one gate with the next? +Xinv_pre_s glitch3_buf pre_s vdd gnd pinv_11 +* I'm an idiot and the following two and3 gates are not supposed to be the same size smh +Xand_s_en we_bar gated_clk_bar pre_s s_en vdd gnd pand3 +Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 +Xand_wl_en_unbuf cs_buf glitch2_bar wl_en_unbuf vdd gnd pand2 +* Xbuf_wl_en is an untested addition, probably too slow but honestly hard to say because the +* fanout was so horrible on wl_en without it that maybe it's actually better now ¯\_(ツ)_/¯ +Xbuf_wl_en wl_en_unbuf wl_en vdd gnd pdriver_1 +Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 +.ENDS control_logic_rw + +.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd +*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B +* INPUT : din0[0] +* INPUT : din0[1] +* INPUT : din0[2] +* INPUT : din0[3] +* INPUT : din0[4] +* INPUT : din0[5] +* INPUT : din0[6] +* INPUT : din0[7] +* INPUT : din0[8] +* INPUT : din0[9] +* INPUT : din0[10] +* INPUT : din0[11] +* INPUT : din0[12] +* INPUT : din0[13] +* INPUT : din0[14] +* INPUT : din0[15] +* INPUT : din0[16] +* INPUT : din0[17] +* INPUT : din0[18] +* INPUT : din0[19] +* INPUT : din0[20] +* INPUT : din0[21] +* INPUT : din0[22] +* INPUT : din0[23] +* INPUT : din0[24] +* INPUT : din0[25] +* INPUT : din0[26] +* INPUT : din0[27] +* INPUT : din0[28] +* INPUT : din0[29] +* INPUT : din0[30] +* INPUT : din0[31] +* INPUT : din0[32] +* INPUT : din0[33] +* INPUT : din0[34] +* INPUT : din0[35] +* INPUT : din0[36] +* INPUT : din0[37] +* INPUT : din0[38] +* INPUT : din0[39] +* INPUT : din0[40] +* INPUT : din0[41] +* INPUT : din0[42] +* INPUT : din0[43] +* INPUT : din0[44] +* INPUT : din0[45] +* INPUT : din0[46] +* INPUT : din0[47] +* INPUT : din0[48] +* INPUT : din0[49] +* INPUT : din0[50] +* INPUT : din0[51] +* INPUT : din0[52] +* INPUT : din0[53] +* INPUT : din0[54] +* INPUT : din0[55] +* INPUT : din0[56] +* INPUT : din0[57] +* INPUT : din0[58] +* INPUT : din0[59] +* INPUT : din0[60] +* INPUT : din0[61] +* INPUT : din0[62] +* INPUT : din0[63] +* INPUT : addr0[0] +* INPUT : addr0[1] +* INPUT : addr0[2] +* INPUT : addr0[3] +* INPUT : addr0[4] +* INPUT : addr0[5] +* INPUT : addr0[6] +* INPUT : csb0 +* INPUT : web0 +* INPUT : clk0 +* OUTPUT: dout0[0] +* OUTPUT: dout0[1] +* OUTPUT: dout0[2] +* OUTPUT: dout0[3] +* OUTPUT: dout0[4] +* OUTPUT: dout0[5] +* OUTPUT: dout0[6] +* OUTPUT: dout0[7] +* OUTPUT: dout0[8] +* OUTPUT: dout0[9] +* OUTPUT: dout0[10] +* OUTPUT: dout0[11] +* OUTPUT: dout0[12] +* OUTPUT: dout0[13] +* OUTPUT: dout0[14] +* OUTPUT: dout0[15] +* OUTPUT: dout0[16] +* OUTPUT: dout0[17] +* OUTPUT: dout0[18] +* OUTPUT: dout0[19] +* OUTPUT: dout0[20] +* OUTPUT: dout0[21] +* OUTPUT: dout0[22] +* OUTPUT: dout0[23] +* OUTPUT: dout0[24] +* OUTPUT: dout0[25] +* OUTPUT: dout0[26] +* OUTPUT: dout0[27] +* OUTPUT: dout0[28] +* OUTPUT: dout0[29] +* OUTPUT: dout0[30] +* OUTPUT: dout0[31] +* OUTPUT: dout0[32] +* OUTPUT: dout0[33] +* OUTPUT: dout0[34] +* OUTPUT: dout0[35] +* OUTPUT: dout0[36] +* OUTPUT: dout0[37] +* OUTPUT: dout0[38] +* OUTPUT: dout0[39] +* OUTPUT: dout0[40] +* OUTPUT: dout0[41] +* OUTPUT: dout0[42] +* OUTPUT: dout0[43] +* OUTPUT: dout0[44] +* OUTPUT: dout0[45] +* OUTPUT: dout0[46] +* OUTPUT: dout0[47] +* OUTPUT: dout0[48] +* OUTPUT: dout0[49] +* OUTPUT: dout0[50] +* OUTPUT: dout0[51] +* OUTPUT: dout0[52] +* OUTPUT: dout0[53] +* OUTPUT: dout0[54] +* OUTPUT: dout0[55] +* OUTPUT: dout0[56] +* OUTPUT: dout0[57] +* OUTPUT: dout0[58] +* OUTPUT: dout0[59] +* OUTPUT: dout0[60] +* OUTPUT: dout0[61] +* OUTPUT: dout0[62] +* OUTPUT: dout0[63] +* POWER : vdd +* GROUND: gnd +Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank +Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw +Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff +Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff +Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff +.ENDS sram_64_128_scn4m_subm diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py new file mode 100644 index 00000000..5bd9ed69 --- /dev/null +++ b/compiler/modules/control_logic_delay.py @@ -0,0 +1,811 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import design +import debug +from sram_factory import factory +import math +from vector import vector +from globals import OPTS +import logical_effort + + +class control_logic(design.design): + """ + Dynamically generated Control logic for the total SRAM circuit. + Variant: delay-based + """ + + def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""): + """ Constructor """ + name = "control_logic_" + port_type + super().__init__(name) + debug.info(1, "Creating {}".format(name)) + self.add_comment("num_rows: {0}".format(num_rows)) + self.add_comment("words_per_row: {0}".format(words_per_row)) + self.add_comment("word_size {0}".format(word_size)) + + self.sram=sram + self.num_rows = num_rows + self.words_per_row = words_per_row + self.word_size = word_size + self.port_type = port_type + + if not spare_columns: + self.num_spare_cols = 0 + else: + self.num_spare_cols = spare_columns + + self.num_cols = word_size * words_per_row + self.num_spare_cols + self.num_words = num_rows * words_per_row + + self.enable_delay_chain_resizing = False + self.inv_parasitic_delay = logical_effort.logical_effort.pinv + + # Determines how much larger the sen delay should be. Accounts for possible error in model. + # FIXME: This should be made a parameter + self.wl_timing_tolerance = 1 + self.wl_stage_efforts = None + self.sen_stage_efforts = None + + if self.port_type == "rw": + self.num_control_signals = 2 + else: + self.num_control_signals = 1 + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + self.setup_signal_busses() + self.add_pins() + self.add_modules() + self.create_instances() + + def create_layout(self): + """ Create layout and route between modules """ + self.place_instances() + self.route_all() + # self.add_lvs_correspondence_points() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + """ Add the pins to the control logic module. """ + self.add_pin_list(self.input_list + ["clk"] + self.rbl_list, "INPUT") + self.add_pin_list(self.output_list, "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def add_modules(self): + """ Add all the required modules """ + + self.dff = factory.create(module_type="dff_buf") + dff_height = self.dff.height + + self.ctrl_dff_array = factory.create(module_type="dff_buf_array", + rows=self.num_control_signals, + columns=1) + + self.and2 = factory.create(module_type="pand2", + size=12, + height=dff_height) + + self.rbl_driver = factory.create(module_type="pbuf", + size=self.num_cols, + height=dff_height) + + # clk_buf drives a flop for every address + addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2) + # plus data flops and control flops + num_flops = addr_flops + self.word_size + self.num_spare_cols + self.num_control_signals + # each flop internally has a FO 5 approximately + # plus about 5 fanouts for the control logic + clock_fanout = 5 * num_flops + 5 + self.clk_buf_driver = factory.create(module_type="pdriver", + fanout=clock_fanout, + height=dff_height) + + # We will use the maximum since this same value is used to size the wl_en + # and the p_en_bar drivers + # max_fanout = max(self.num_rows, self.num_cols) + + # wl_en drives every row in the bank + # MRG 9/3/2021: Ensure that this is two stages to prevent race conditions with the write driver + size_list = [max(int(self.num_rows / 9), 1), max(int(self.num_rows / 3), 1)] + self.wl_en_driver = factory.create(module_type="pdriver", + size_list=size_list, + height=dff_height) + + # wl_en_unbuf is the weak timing signal that feeds wl_en_driver + self.wl_en_and = factory.create(module_type="pand2", + size=1, # FIXME: Minimum size??? Should even have this gate?? + height=dff_height) + + # w_en drives every write driver + self.wen_and = factory.create(module_type="pand3", + size=self.word_size + 8, + height=dff_height) + + # s_en drives every sense amp + self.sen_and3 = factory.create(module_type="pand3", + size=self.word_size + self.num_spare_cols, + height=dff_height) + + # used to generate inverted signals with low fanout + self.inv = factory.create(module_type="pinv", + size=1, + height=dff_height) + + # p_en_bar drives every column in the bitcell array + # but it is sized the same as the wl_en driver with + # prepended 3 inverter stages to guarantee it is slower and odd polarity + self.p_en_bar_driver = factory.create(module_type="pdriver", + fanout=self.num_cols, + height=dff_height) + + self.nand2 = factory.create(module_type="pnand2", + height=dff_height) + + debug.check(OPTS.delay_chain_stages % 2, + "Must use odd number of delay chain stages for inverting delay chain.") + self.delay_chain=factory.create(module_type="delay_chain", + fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ]) + + # not being used + def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): + """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" + from math import ceil + previous_delay_chain_delay = (previous_fanout + 1 + self.inv_parasitic_delay) * previous_stages + debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) + + # This can be anything >=2 + delay_fanout = 3 + # The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each + # inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value + required_delay = self.wl_delay * self.wl_timing_tolerance - (self.sen_delay - previous_delay_chain_delay) + debug.check(required_delay > 0, "Cannot size delay chain to have negative delay") + delay_per_stage = delay_fanout + 1 + self.inv_parasitic_delay + delay_stages = ceil(required_delay / delay_per_stage) + # force an even number of stages. + if delay_stages % 2 == 1: + delay_stages += 1 + # Fanout can be varied as well but is a little more complicated but potentially optimal. + debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay)) + return (delay_stages, delay_fanout) + + # not being used + def get_dynamic_delay_fanout_list(self, previous_stages, previous_fanout): + """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" + + previous_delay_per_stage = previous_fanout + 1 + self.inv_parasitic_delay + previous_delay_chain_delay = previous_delay_per_stage * previous_stages + debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) + + fanout_rise = fanout_fall = 2 # This can be anything >=2 + # The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each + # inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value + required_delay_fall = self.wl_delay_fall * self.wl_timing_tolerance - \ + (self.sen_delay_fall - previous_delay_chain_delay / 2) + required_delay_rise = self.wl_delay_rise * self.wl_timing_tolerance - \ + (self.sen_delay_rise - previous_delay_chain_delay / 2) + debug.info(2, + "Required delays from chain: fall={}, rise={}".format(required_delay_fall, + required_delay_rise)) + + # If the fanout is different between rise/fall by this amount. Stage algorithm is made more pessimistic. + WARNING_FANOUT_DIFF = 5 + stages_close = False + # The stages need to be equal (or at least a even number of stages with matching rise/fall delays) + while True: + stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall, + fanout_fall) + stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise, + fanout_rise) + debug.info(1, + "Fall stages={}, rise stages={}".format(stages_fall, + stages_rise)) + if abs(stages_fall - stages_rise) == 1 and not stages_close: + stages_close = True + safe_fanout_rise = fanout_rise + safe_fanout_fall = fanout_fall + + if stages_fall == stages_rise: + break + elif abs(stages_fall - stages_rise) == 1 and WARNING_FANOUT_DIFF < abs(fanout_fall - fanout_rise): + debug.info(1, "Delay chain fanouts between stages are large. Making chain size larger for safety.") + fanout_rise = safe_fanout_rise + fanout_fall = safe_fanout_fall + break + # There should also be a condition to make sure the fanout does not get too large. + # Otherwise, increase the fanout of delay with the most stages, calculate new stages + elif stages_fall>stages_rise: + fanout_fall+=1 + else: + fanout_rise+=1 + + total_stages = max(stages_fall, stages_rise) * 2 + debug.info(1, "New Delay chain: stages={}, fanout_rise={}, fanout_fall={}".format(total_stages, fanout_rise, fanout_fall)) + + # Creates interleaved fanout list of rise/fall delays. Assumes fall is the first stage. + stage_list = [fanout_fall if i % 2==0 else fanout_rise for i in range(total_stages)] + return stage_list + + # only used by above unused function + def calculate_stages_with_fixed_fanout(self, required_delay, fanout): + from math import ceil + # Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay + # 3 is the minimum delay per stage (with pinv=0). + if required_delay <= 3 + self.inv_parasitic_delay: + return 1 + delay_per_stage = fanout + 1 + self.inv_parasitic_delay + delay_stages = ceil(required_delay / delay_per_stage) + return delay_stages + + def setup_signal_busses(self): + """ Setup bus names, determine the size of the busses etc """ + + # List of input control signals + if self.port_type == "rw": + self.input_list = ["csb", "web"] + self.rbl_list = ["rbl_bl"] + else: + self.input_list = ["csb"] + self.rbl_list = ["rbl_bl"] + + if self.port_type == "rw": + self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"] + else: + self.dff_output_list = ["cs_bar", "cs"] + + # list of output control signals (for making a vertical bus) + if self.port_type == "rw": + self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] + elif self.port_type == "r": + self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"] + else: + self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] + # leave space for the bus plus one extra space + self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch + + # Outputs to the bank + if self.port_type == "rw": + self.output_list = ["s_en", "w_en"] + elif self.port_type == "r": + self.output_list = ["s_en"] + else: + self.output_list = ["w_en"] + self.output_list.append("p_en_bar") + self.output_list.append("wl_en") + self.output_list.append("clk_buf") + + self.supply_list = ["vdd", "gnd"] + + def route_rails(self): + """ Add the input signal inverted tracks """ + height = self.control_logic_center.y - self.m2_pitch + offset = vector(self.ctrl_dff_array.width, 0) + + self.input_bus = self.create_vertical_bus("m2", + offset, + self.internal_bus_list, + height) + + def create_instances(self): + """ Create all the instances """ + self.create_dffs() + self.create_clk_buf_row() + self.create_gated_clk_bar_row() + self.create_gated_clk_buf_row() + self.create_wlen_row() + if (self.port_type == "rw") or (self.port_type == "w"): + self.create_rbl_delay_row() + self.create_wen_row() + if (self.port_type == "rw") or (self.port_type == "r"): + self.create_sen_row() + self.create_delay() + self.create_pen_row() + + def place_instances(self): + """ Place all the instances """ + # Keep track of all right-most instances to determine row boundary + # and add the vdd/gnd pins + self.row_end_inst = [] + + # Add the control flops on the left of the bus + self.place_dffs() + + # All of the control logic is placed to the right of the DFFs and bus + self.control_x_offset = self.ctrl_dff_array.width + self.internal_bus_width + + row = 0 + # Add the logic on the right of the bus + self.place_clk_buf_row(row) + row += 1 + self.place_gated_clk_bar_row(row) + row += 1 + self.place_gated_clk_buf_row(row) + row += 1 + if (self.port_type == "rw") or (self.port_type == "r"): + self.place_sen_row(row) + row += 1 + if (self.port_type == "rw") or (self.port_type == "w"): + self.place_wen_row(row) + row += 1 + self.place_pen_row(row) + row += 1 + if (self.port_type == "rw") or (self.port_type == "w"): + self.place_rbl_delay_row(row) + row += 1 + self.place_wlen_row(row) + row += 1 + + control_center_y = self.wl_en_inst.uy() + self.m3_pitch + + # Delay chain always gets placed at row 4 + self.place_delay(4) + height = self.delay_inst.uy() + + # This offset is used for placement of the control logic in the SRAM level. + self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y) + + # Extra pitch on top and right + self.height = height + 2 * self.m1_pitch + # Max of modules or logic rows + self.width = max([inst.rx() for inst in self.row_end_inst]) + if (self.port_type == "rw") or (self.port_type == "r"): + self.width = max(self.delay_inst.rx(), self.width) + self.width += self.m2_pitch + + def route_all(self): + """ Routing between modules """ + self.route_rails() + self.route_dffs() + self.route_wlen() + if (self.port_type == "rw") or (self.port_type == "w"): + self.route_rbl_delay() + self.route_wen() + if (self.port_type == "rw") or (self.port_type == "r"): + self.route_sen() + self.route_delay() + self.route_pen() + self.route_clk_buf() + self.route_gated_clk_bar() + self.route_gated_clk_buf() + self.route_supply() + + def create_delay(self): + """ Create the replica bitline """ + self.delay_inst=self.add_inst(name="delay_chain", + mod=self.delay_chain) + # rbl_bl_delay is asserted (1) when the bitline has been discharged + self.connect_inst(["rbl_bl", "rbl_bl_delay", "vdd", "gnd"]) + + def place_delay(self, row): + """ Place the replica bitline """ + debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.") + + # It is flipped on X axis + y_off = row * self.and2.height + self.delay_chain.height + + # Add the RBL above the rows + # Add to the right of the control rows and routing channel + offset = vector(0, y_off) + self.delay_inst.place(offset, mirror="MX") + + def route_delay(self): + + out_pos = self.delay_inst.get_pin("out").center() + # Connect to the rail level with the vdd rail + # Use gated clock since it is in every type of control logic # TODO: git blame whoever wrote this, do they mean every type made by others or is this foreshadowing our future addition of delay/async logic. If the former, seems a bit odd to include something basically explanatory. If the latter, seems odd I'm hearing about it now for the first time, because it begs the question if there are other steps that have been taken to lay groundwork for control logic varieties. + vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch + in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos) + mid1 = vector(out_pos.x, in_pos.y) + self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) + self.add_via_center(layers=self.m1_stack, + offset=in_pos) + + # Input from RBL goes to the delay line for futher delay + self.copy_layout_pin(self.delay_inst, "in", "rbl_bl") + + # glitch{1-3} are internal timing signals based on different in/out + # points on the delay chain for adjustable start time and duration + def create_glitches(self): + self.glitch1_inv = self.add_inst(name="inv_glitch1", + mod=self.inv) + self.connect_inst(["out6", "g1_end", "vdd", "gnd"]) + + self.glitch2_inv = self.add_inst(name="inv_glitch2", + mod=self.inv) + self.connect_inst(["out7", "g2_end", "vdd", "gnd"]) + + self.glitch3_inv = self.add_inst(name="inv_glitch3", + mod=self.inv) + self.connect_inst(["out14", "g3_end", "vdd", "gnd"]) + + self.glitch1_nand = self.add_inst(name="nand2_glitch1", + mod=self.nand2) + self.connect_inst(["out1", "g1_end", "glitch1_bar", "vdd", "gnd"]) + + self.glitch2_nand = self.add_inst(name="nand2_glitch2", + mod=self.nand2) + self.connect_inst(["gated_clk_buf", "g2_end", "glitch2_bar", "vdd", "gnd"]) + + self.glitch3_nand = self.add_inst(name="nand2_glitch3", + mod=self.nand2) + self.connect_inst(["out6", "g3_end", "glitch3_bar", "vdd", "gnd"]) + + def create_clk_buf_row(self): + """ Create the multistage and gated clock buffer """ + self.clk_buf_inst = self.add_inst(name="clkbuf", + mod=self.clk_buf_driver) + self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) + + def place_clk_buf_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.clk_buf_inst, x_offset, row) + + self.row_end_inst.append(self.clk_buf_inst) + + def route_clk_buf(self): + clk_pin = self.clk_buf_inst.get_pin("A") + clk_pos = clk_pin.center() + self.add_layout_pin_rect_center(text="clk", + layer="m2", + offset=clk_pos) + self.add_via_stack_center(from_layer=clk_pin.layer, + to_layer="m2", + offset=clk_pos) + + self.route_output_to_bus_jogged(self.clk_buf_inst, + "clk_buf") + self.connect_output(self.clk_buf_inst, "Z", "clk_buf") + + def create_gated_clk_bar_row(self): + self.clk_bar_inst = self.add_inst(name="inv_clk_bar", + mod=self.inv) + self.connect_inst(["clk_buf", "clk_bar", "vdd", "gnd"]) + + self.gated_clk_bar_inst = self.add_inst(name="and2_gated_clk_bar", + mod=self.and2) + self.connect_inst(["clk_bar", "cs", "gated_clk_bar", "vdd", "gnd"]) + + def place_gated_clk_bar_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.clk_bar_inst, x_offset, row) + x_offset = self.place_util(self.gated_clk_bar_inst, x_offset, row) + + self.row_end_inst.append(self.gated_clk_bar_inst) + + def route_gated_clk_bar(self): + clkbuf_map = zip(["A"], ["clk_buf"]) + self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.input_bus) + + out_pin = self.clk_bar_inst.get_pin("Z") + out_pos = out_pin.center() + in_pin = self.gated_clk_bar_inst.get_pin("A") + in_pos = in_pin.center() + self.add_zjog(out_pin.layer, out_pos, in_pos) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=in_pos) + + + # This is the second gate over, so it needs to be on M3 + clkbuf_map = zip(["B"], ["cs"]) + self.connect_vertical_bus(clkbuf_map, + self.gated_clk_bar_inst, + self.input_bus, + self.m2_stack[::-1]) + # The pin is on M1, so we need another via as well + b_pin = self.gated_clk_bar_inst.get_pin("B") + self.add_via_stack_center(from_layer=b_pin.layer, + to_layer="m3", + offset=b_pin.center()) + + # This is the second gate over, so it needs to be on M3 + self.route_output_to_bus_jogged(self.gated_clk_bar_inst, + "gated_clk_bar") + + def create_gated_clk_buf_row(self): + self.gated_clk_buf_inst = self.add_inst(name="and2_gated_clk_buf", + mod=self.and2) + self.connect_inst(["clk_buf", "cs", "gated_clk_buf", "vdd", "gnd"]) + + def place_gated_clk_buf_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.gated_clk_buf_inst, x_offset, row) + + self.row_end_inst.append(self.gated_clk_buf_inst) + + def route_gated_clk_buf(self): + clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"]) + self.connect_vertical_bus(clkbuf_map, + self.gated_clk_buf_inst, + self.input_bus) + + clkbuf_map = zip(["Z"], ["gated_clk_buf"]) + self.connect_vertical_bus(clkbuf_map, + self.gated_clk_buf_inst, + self.input_bus, + self.m2_stack[::-1]) + # The pin is on M1, so we need another via as well + z_pin = self.gated_clk_buf_inst.get_pin("Z") + self.add_via_stack_center(from_layer=z_pin.layer, + to_layer="m2", + offset=z_pin.center()) + + def create_wlen_row(self): + # input pre_p_en, output: wl_en + self.wl_en_inst=self.add_inst(name="buf_wl_en", + mod=self.wl_en_driver) + self.connect_inst(["gated_clk_bar", "wl_en", "vdd", "gnd"]) + + def place_wlen_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.wl_en_inst, x_offset, row) + + self.row_end_inst.append(self.wl_en_inst) + + def route_wlen(self): + wlen_map = zip(["A"], ["gated_clk_bar"]) + self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus) + + self.connect_output(self.wl_en_inst, "Z", "wl_en") + + def create_pen_row(self): + self.p_en_bar_nand_inst=self.add_inst(name="nand_p_en_bar", + mod=self.nand2) + # We use the rbl_bl_delay here to ensure that the p_en is only asserted when the + # bitlines have already been discharged. Otherwise, it is a combination loop. + self.connect_inst(["gated_clk_buf", "rbl_bl_delay", "p_en_bar_unbuf", "vdd", "gnd"]) + + self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar", + mod=self.p_en_bar_driver) + self.connect_inst(["p_en_bar_unbuf", "p_en_bar", "vdd", "gnd"]) + + def place_pen_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.p_en_bar_nand_inst, x_offset, row) + x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row) + + self.row_end_inst.append(self.p_en_bar_driver_inst) + + def route_pen(self): + in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"]) + self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.input_bus) + + out_pin = self.p_en_bar_nand_inst.get_pin("Z") + out_pos = out_pin.center() + in_pin = self.p_en_bar_driver_inst.get_pin("A") + in_pos = in_pin.center() + mid1 = vector(in_pos.x, out_pos.y) + self.add_path(out_pin.layer, [out_pos, mid1, in_pos]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=in_pin.center()) + + self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") + + def create_sen_row(self): + """ Create the sense enable buffer. """ + if self.port_type=="rw": + input_name = "we_bar" + else: + input_name = "cs" + # GATE FOR S_EN + self.s_en_gate_inst = self.add_inst(name="buf_s_en_and", + mod=self.sen_and3) + # s_en is asserted in the second half of the cycle during a read. + # we also must wait until the bitline has been discharged enough for proper sensing + # hence we use rbl_bl_delay as well. + self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) + + def place_sen_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.s_en_gate_inst, x_offset, row) + + self.row_end_inst.append(self.s_en_gate_inst) + + def route_sen(self): + + if self.port_type=="rw": + input_name = "we_bar" + else: + input_name = "cs" + + sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name]) + self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus) + + self.connect_output(self.s_en_gate_inst, "Z", "s_en") + + def create_wen_row(self): + + # input: we (or cs) output: w_en + if self.port_type == "rw": + input_name = "we" + else: + # No we for write-only ports, so use cs + input_name = "cs" + + # GATE THE W_EN + self.w_en_gate_inst = self.add_inst(name="w_en_and", + mod=self.wen_and) + # Only drive the writes in the second half of the clock cycle during a write operation. + self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"]) + + def place_wen_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) + + self.row_end_inst.append(self.w_en_gate_inst) + + def route_wen(self): + if self.port_type == "rw": + input_name = "we" + else: + # No we for write-only ports, so use cs + input_name = "cs" + + wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"]) + self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus) + + self.connect_output(self.w_en_gate_inst, "Z", "w_en") + + def create_dffs(self): + self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", + mod=self.ctrl_dff_array) + inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list + self.connect_inst(inst_pins) + + def place_dffs(self): + self.ctrl_dff_inst.place(vector(0, 0)) + + def route_dffs(self): + if self.port_type == "rw": + dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) + elif self.port_type == "r": + dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) + else: + dff_out_map = zip(["dout_bar_0"], ["cs"]) + self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1]) + + # Connect the clock rail to the other clock rail + # by routing in the supply rail track to avoid channel conflicts + in_pos = self.ctrl_dff_inst.get_pin("clk").uc() + mid_pos = vector(in_pos.x, self.gated_clk_buf_inst.get_pin("vdd").cy() - self.m1_pitch) + rail_pos = vector(self.input_bus["clk_buf"].cx(), mid_pos.y) + self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos]) + self.add_via_center(layers=self.m1_stack, + offset=rail_pos) + + self.copy_layout_pin(self.ctrl_dff_inst, "din_0", "csb") + if (self.port_type == "rw"): + self.copy_layout_pin(self.ctrl_dff_inst, "din_1", "web") + + def get_offset(self, row): + """ Compute the y-offset and mirroring """ + y_off = row * self.and2.height + if row % 2: + y_off += self.and2.height + mirror="MX" + else: + mirror="R0" + + return (y_off, mirror) + + def connect_output(self, inst, pin_name, out_name): + """ Create an output pin on the right side from the pin of a given instance. """ + + out_pin = inst.get_pin(pin_name) + out_pos = out_pin.center() + right_pos = out_pos + vector(self.width - out_pin.cx(), 0) + + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer="m2", + offset=out_pos) + self.add_layout_pin_segment_center(text=out_name, + layer="m2", + start=out_pos, + end=right_pos) + + def route_supply(self): + """ Add vdd and gnd to the instance cells """ + + supply_layer = self.dff.get_pin("vdd").layer + + max_row_x_loc = max([inst.rx() for inst in self.row_end_inst]) + for inst in self.row_end_inst: + pins = inst.get_pins("vdd") + for pin in pins: + if pin.layer == supply_layer: + row_loc = pin.rc() + pin_loc = vector(max_row_x_loc, pin.rc().y) + self.add_power_pin("vdd", pin_loc, start_layer=pin.layer) + self.add_path(supply_layer, [row_loc, pin_loc]) + + pins = inst.get_pins("gnd") + for pin in pins: + if pin.layer == supply_layer: + row_loc = pin.rc() + pin_loc = vector(max_row_x_loc, pin.rc().y) + self.add_power_pin("gnd", pin_loc, start_layer=pin.layer) + self.add_path(supply_layer, [row_loc, pin_loc]) + + self.copy_layout_pin(self.delay_inst, "gnd") + self.copy_layout_pin(self.delay_inst, "vdd") + + self.copy_layout_pin(self.ctrl_dff_inst, "gnd") + self.copy_layout_pin(self.ctrl_dff_inst, "vdd") + + # not used + def add_lvs_correspondence_points(self): + """ This adds some points for easier debugging if LVS goes wrong. + These should probably be turned off by default though, since extraction + will show these as ports in the extracted netlist. + """ + # pin=self.clk_inv1.get_pin("Z") + # self.add_label_pin(text="clk1_bar", + # layer="m1", + # offset=pin.ll(), + # height=pin.height(), + # width=pin.width()) + + # pin=self.clk_inv2.get_pin("Z") + # self.add_label_pin(text="clk2", + # layer="m1", + # offset=pin.ll(), + # height=pin.height(), + # width=pin.width()) + + pin=self.delay_inst.get_pin("out") + self.add_label_pin(text="out", + layer=pin.layer, + offset=pin.ll(), + height=pin.height(), + width=pin.width()) + + def graph_exclude_dffs(self): + """Exclude dffs from graph as they do not represent critical path""" + + self.graph_inst_exclude.add(self.ctrl_dff_inst) + if self.port_type=="rw" or self.port_type=="w": + self.graph_inst_exclude.add(self.w_en_gate_inst) + + def place_util(self, inst, x_offset, row): + """ Utility to place a row and compute the next offset """ + + (y_offset, mirror) = self.get_offset(row) + offset = vector(x_offset, y_offset) + inst.place(offset, mirror) + return x_offset + inst.width + + def route_output_to_bus_jogged(self, inst, name): + # Connect this at the bottom of the buffer + out_pin = inst.get_pin("Z") + out_pos = out_pin.center() + mid1 = vector(out_pos.x, out_pos.y - 0.4 * inst.mod.height) + mid2 = vector(self.input_bus[name].cx(), mid1.y) + bus_pos = self.input_bus[name].center() + self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer="m2", + offset=out_pos) + + def get_left_pins(self, name): + """ + Return the left side supply pins to connect to a vertical stripe. + """ + return(self.cntrl_dff_inst.get_pins(name) + self.delay_inst.get_pins(name)) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py new file mode 100644 index 00000000..0eb0dea5 --- /dev/null +++ b/compiler/modules/multi_delay_chain.py @@ -0,0 +1,220 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +import design +from vector import vector +from globals import OPTS +from sram_factory import factory + + +class delay_chain(design.design): + """ + Generate a delay chain with the given number of stages, fanout, and output pins. + Fanout list contains the electrical effort (fanout) of each stage. + Usually, this will be constant, but it could have varied fanout. + Pinout list contains the inverter stages which have an output pin attached. + Supplying an empty pinout list will result in an output on the last stage. + """ + + def __init__(self, name, fanout_list, pinout_list): + """init function""" + super().__init__(name) + debug.info(1, "creating delay chain {0}".format(str(fanout_list))) + self.add_comment("fanouts: {0}".format(str(fanout_list))) + + # Two fanouts are needed so that we can route the vdd/gnd connections + for f in fanout_list: + debug.check(f>=2, "Must have >=2 fanouts for each stage.") + + # number of inverters including any fanout loads. + self.fanout_list = fanout_list + self.rows = len(self.fanout_list) + + # defaults to signle output at end of delay chain + if len(self.pinout_list) == 0: + self.pinout_list = [self.rows] # TODO: check for off-by-one here + else: + self.pinout_list = pinout_list + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + self.add_modules() + self.add_pins() + self.create_inverters() + + def create_layout(self): + # Each stage is a a row + self.height = self.rows * self.inv.height + # The width is determined by the largest fanout plus the driver + self.width = (max(self.fanout_list) + 1) * self.inv.width + + self.place_inverters() + self.route_inverters() + self.route_supplies() + self.add_layout_pins() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + """ Add the pins of the delay chain""" + self.add_pin("in", "INPUT") + for pin_stage in self.pinout_list: + self.add_pin("out{}".format(pin_stage), "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def add_modules(self): + + self.dff = factory.create(module_type="dff_buf") + dff_height = self.dff.height + + self.inv = factory.create(module_type="pinv", + height=dff_height) + + def create_inverters(self): + """ Create the inverters and connect them based on the stage list """ + self.driver_inst_list = [] + self.load_inst_map = {} + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): + # Add the inverter + cur_driver=self.add_inst(name="dinv{}".format(stage_num), + mod=self.inv) + # keep track of the inverter instances so we can use them to get the pins + self.driver_inst_list.append(cur_driver) + + # Hook up the driver + stageout_name = "out{}".format(stage_num + 1) # TODO: check for off-by-one here + if stage_num == 0: + stagein_name = "in" + else: + stagein_name = "out{}".format(stage_num) + self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"]) + + # Now add the dummy loads to the right + self.load_inst_map[cur_driver]=[] + for i in range(fanout_size): + cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num, i), + mod=self.inv) + # Fanout stage is always driven by driver and output is disconnected + disconnect_name = "n_{0}_{1}".format(stage_num, i) + self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"]) + + # Keep track of all the loads to connect their inputs as a load + self.load_inst_map[cur_driver].append(cur_load) + + def place_inverters(self): + """ Place the inverters and connect them based on the stage list """ + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): + if stage_num % 2: + inv_mirror = "MX" + inv_offset = vector(0, (stage_num + 1) * self.inv.height) + else: + inv_mirror = "R0" + inv_offset = vector(0, stage_num * self.inv.height) + + # Add the inverter + cur_driver=self.driver_inst_list[stage_num] + cur_driver.place(offset=inv_offset, + mirror=inv_mirror) + + # Now add the dummy loads to the right + load_list = self.load_inst_map[cur_driver] + for i in range(fanout_size): + inv_offset += vector(self.inv.width, 0) + load_list[i].place(offset=inv_offset, + mirror=inv_mirror) + + def add_route(self, pin1, pin2): + """ This guarantees that we route from the top to bottom row correctly. """ + pin1_pos = pin1.center() + pin2_pos = pin2.center() + if pin1_pos.y == pin2_pos.y: + self.add_path("m2", [pin1_pos, pin2_pos]) + else: + mid_point = vector(pin2_pos.x, 0.5 * (pin1_pos.y + pin2_pos.y)) + # Written this way to guarantee it goes right first if we are switching rows + self.add_path("m2", [pin1_pos, vector(pin1_pos.x, mid_point.y), mid_point, vector(mid_point.x, pin2_pos.y), pin2_pos]) + + def route_inverters(self): + """ Add metal routing for each of the fanout stages """ + + for i in range(len(self.driver_inst_list)): + inv = self.driver_inst_list[i] + for load in self.load_inst_map[inv]: + # Drop a via on each A pin + a_pin = load.get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m3", + offset=a_pin.center()) + + # Route an M3 horizontal wire to the furthest + z_pin = inv.get_pin("Z") + a_pin = inv.get_pin("A") + a_max = self.load_inst_map[inv][-1].get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=a_pin.center()) + self.add_via_stack_center(from_layer=z_pin.layer, + to_layer="m3", + offset=z_pin.center()) + self.add_path("m3", [z_pin.center(), a_max.center()]) + + # Route Z to the A of the next stage + if i + 1 < len(self.driver_inst_list): + z_pin = inv.get_pin("Z") + next_inv = self.driver_inst_list[i + 1] + next_a_pin = next_inv.get_pin("A") + y_mid = (z_pin.cy() + next_a_pin.cy()) / 2 + mid1_point = vector(z_pin.cx(), y_mid) + mid2_point = vector(next_a_pin.cx(), y_mid) + self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) + + def route_supplies(self): + # Add power and ground to all the cells except: + # the fanout driver, the right-most load + # The routing to connect the loads is over the first and last cells + # We have an even number of drivers and must only do every other + # supply rail + + for inst in self.driver_inst_list: + load_list = self.load_inst_map[inst] + for pin_name in ["vdd", "gnd"]: + pin = load_list[0].get_pin(pin_name) + self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0)) + + pin = load_list[-2].get_pin(pin_name) + self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0)) + + def add_layout_pins(self): + + # input is A pin of first inverter + # It gets routed to the left a bit to prevent pin access errors + # due to the output pin when going up to M3 + a_pin = self.driver_inst_list[0].get_pin("A") + mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy()) + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m2", + offset=mid_loc) + self.add_path(a_pin.layer, [a_pin.center(), mid_loc]) + + self.add_layout_pin_rect_center(text="in", + layer="m2", + offset=mid_loc) + + # output is A pin of last load/fanout inverter + last_driver_inst = self.driver_inst_list[-1] + a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m1", + offset=a_pin.center()) + self.add_layout_pin_rect_center(text="out", + layer="m1", + offset=a_pin.center()) From 62a65f8053fa360aafd01f10004f6bac469218e4 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 27 Apr 2022 12:13:36 -0700 Subject: [PATCH 004/102] all remaining spice for delay control --- ..._128_scn4m_subm-collapse-glitch-control.sp | 8 +- compiler/modules/control_logic_delay.py | 81 ++++++++++--------- compiler/modules/multi_delay_chain.py | 4 +- 3 files changed, 51 insertions(+), 42 deletions(-) diff --git a/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp b/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp index 678019c2..12b07ea5 100644 --- a/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp +++ b/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp @@ -13930,17 +13930,17 @@ Xnand2_glitch3 out6 g3_end glitch3_bar vdd gnd pnand2 Xinv_glitch3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 * is cs_buf needed on larger memories? I don't remember why I needed this for small mems. Some timing bs surely * I have a feeling this was another misguided workaround to proper gate sizing smh my head bruh -Xbuf_cs cs cs_buf vdd gnd pdriver_0 +*Xbuf_cs cs cs_buf vdd gnd pdriver_0 Xclkbuf clk clk_buf vdd gnd pdriver_0 Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 * uhhhh do I really need this?? can't I just roll this into one gate with the next? -Xinv_pre_s glitch3_buf pre_s vdd gnd pinv_11 +Xinv_pre_sen glitch3_buf pre_sen vdd gnd pinv_11 * I'm an idiot and the following two and3 gates are not supposed to be the same size smh -Xand_s_en we_bar gated_clk_bar pre_s s_en vdd gnd pand3 +Xand_s_en we_bar gated_clk_bar pre_sen s_en vdd gnd pand3 Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 -Xand_wl_en_unbuf cs_buf glitch2_bar wl_en_unbuf vdd gnd pand2 +Xand_wl_en_unbuf cs glitch2_bar wl_en_unbuf vdd gnd pand2 * Xbuf_wl_en is an untested addition, probably too slow but honestly hard to say because the * fanout was so horrible on wl_en without it that maybe it's actually better now ¯\_(ツ)_/¯ Xbuf_wl_en wl_en_unbuf wl_en vdd gnd pdriver_1 diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 5bd9ed69..983c25d3 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -14,7 +14,7 @@ from globals import OPTS import logical_effort -class control_logic(design.design): +class control_logic_delay(design.design): """ Dynamically generated Control logic for the total SRAM circuit. Variant: delay-based @@ -96,10 +96,6 @@ class control_logic(design.design): size=12, height=dff_height) - self.rbl_driver = factory.create(module_type="pbuf", - size=self.num_cols, - height=dff_height) - # clk_buf drives a flop for every address addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2) # plus data flops and control flops @@ -154,8 +150,9 @@ class control_logic(design.design): debug.check(OPTS.delay_chain_stages % 2, "Must use odd number of delay chain stages for inverting delay chain.") - self.delay_chain=factory.create(module_type="delay_chain", - fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ]) + self.multi_delay_chain=factory.create(module_type = "multi_delay_chain", + fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ], + pinout_list = [1, 6, 7, 14]) # TODO: generate this list programatically # not being used def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): @@ -302,13 +299,14 @@ class control_logic(design.design): self.create_clk_buf_row() self.create_gated_clk_bar_row() self.create_gated_clk_buf_row() + self.create_delay() + self.create_glitches() + self.create_glitch3_additional_invs() self.create_wlen_row() if (self.port_type == "rw") or (self.port_type == "w"): - self.create_rbl_delay_row() self.create_wen_row() if (self.port_type == "rw") or (self.port_type == "r"): self.create_sen_row() - self.create_delay() self.create_pen_row() def place_instances(self): @@ -380,11 +378,10 @@ class control_logic(design.design): self.route_supply() def create_delay(self): - """ Create the replica bitline """ - self.delay_inst=self.add_inst(name="delay_chain", - mod=self.delay_chain) - # rbl_bl_delay is asserted (1) when the bitline has been discharged - self.connect_inst(["rbl_bl", "rbl_bl_delay", "vdd", "gnd"]) + """ Create the delay chain """ + self.delay_inst=self.add_inst(name="multi_delay_chain", + mod=self.multi_delay_chain) + self.connect_inst(["gated_clk_buf", "out1", "out6", "out7", "out14", "vdd", "gnd"]) def place_delay(self, row): """ Place the replica bitline """ @@ -416,28 +413,28 @@ class control_logic(design.design): # glitch{1-3} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration def create_glitches(self): - self.glitch1_inv = self.add_inst(name="inv_glitch1", - mod=self.inv) + self.glitch1_inv_inst = self.add_inst(name="inv_glitch1", + mod=self.inv) self.connect_inst(["out6", "g1_end", "vdd", "gnd"]) - self.glitch2_inv = self.add_inst(name="inv_glitch2", - mod=self.inv) + self.glitch2_inv_inst = self.add_inst(name="inv_glitch2", + mod=self.inv) self.connect_inst(["out7", "g2_end", "vdd", "gnd"]) - self.glitch3_inv = self.add_inst(name="inv_glitch3", - mod=self.inv) + self.glitch3_inv_inst = self.add_inst(name="inv_glitch3", + mod=self.inv) self.connect_inst(["out14", "g3_end", "vdd", "gnd"]) - self.glitch1_nand = self.add_inst(name="nand2_glitch1", - mod=self.nand2) + self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1", + mod=self.nand2) self.connect_inst(["out1", "g1_end", "glitch1_bar", "vdd", "gnd"]) - self.glitch2_nand = self.add_inst(name="nand2_glitch2", - mod=self.nand2) + self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2", + mod=self.nand2) self.connect_inst(["gated_clk_buf", "g2_end", "glitch2_bar", "vdd", "gnd"]) - self.glitch3_nand = self.add_inst(name="nand2_glitch3", - mod=self.nand2) + self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3", + mod=self.nand2) self.connect_inst(["out6", "g3_end", "glitch3_bar", "vdd", "gnd"]) def create_clk_buf_row(self): @@ -544,10 +541,13 @@ class control_logic(design.design): offset=z_pin.center()) def create_wlen_row(self): - # input pre_p_en, output: wl_en + self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf", + mod=self.wl_en_and) + self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"]) + self.wl_en_inst=self.add_inst(name="buf_wl_en", mod=self.wl_en_driver) - self.connect_inst(["gated_clk_bar", "wl_en", "vdd", "gnd"]) + self.connect_inst(["wl_en_unbuf", "wl_en", "vdd", "gnd"]) def place_wlen_row(self, row): x_offset = self.control_x_offset @@ -563,15 +563,13 @@ class control_logic(design.design): self.connect_output(self.wl_en_inst, "Z", "wl_en") def create_pen_row(self): - self.p_en_bar_nand_inst=self.add_inst(name="nand_p_en_bar", - mod=self.nand2) + # FIXME: comment below # We use the rbl_bl_delay here to ensure that the p_en is only asserted when the # bitlines have already been discharged. Otherwise, it is a combination loop. - self.connect_inst(["gated_clk_buf", "rbl_bl_delay", "p_en_bar_unbuf", "vdd", "gnd"]) self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar", mod=self.p_en_bar_driver) - self.connect_inst(["p_en_bar_unbuf", "p_en_bar", "vdd", "gnd"]) + self.connect_inst(["glitch1_bar", "p_en_bar", "vdd", "gnd"]) def place_pen_row(self, row): x_offset = self.control_x_offset @@ -597,6 +595,16 @@ class control_logic(design.design): self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") + def create_glitch3_additional_invs(self): + """ A pair of inverters to create additional signals from and buffer glitch 3""" + self.glitch3_buf_inv_inst = self.add_inst(name="inv_glitch3_buf", + mod=self.inv) + self.connect_inst(["glitch3_bar", "glitch3_buf", "vdd", "gnd"]) + + self.pre_sen_inv = self.add_inst(name="inv_pre_sen", + mod=self.inv) + self.connect_inst(["gltich3_buf", "pre_sen", "vdd", "gnd"]) + def create_sen_row(self): """ Create the sense enable buffer. """ if self.port_type=="rw": @@ -604,12 +612,13 @@ class control_logic(design.design): else: input_name = "cs" # GATE FOR S_EN - self.s_en_gate_inst = self.add_inst(name="buf_s_en_and", + self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) + # FIXME: comment below # s_en is asserted in the second half of the cycle during a read. # we also must wait until the bitline has been discharged enough for proper sensing # hence we use rbl_bl_delay as well. - self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) + self.connect_inst(["pre_sen", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) def place_sen_row(self, row): x_offset = self.control_x_offset @@ -640,10 +649,10 @@ class control_logic(design.design): input_name = "cs" # GATE THE W_EN - self.w_en_gate_inst = self.add_inst(name="w_en_and", + self.w_en_gate_inst = self.add_inst(name="and_w_en", mod=self.wen_and) # Only drive the writes in the second half of the clock cycle during a write operation. - self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"]) + self.connect_inst([input_name, "glitch2_bar", "glitch3_buf", "w_en", "vdd", "gnd"]) def place_wen_row(self, row): x_offset = self.control_x_offset diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 0eb0dea5..20f824ff 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -12,7 +12,7 @@ from globals import OPTS from sram_factory import factory -class delay_chain(design.design): +class multi_delay_chain(design.design): """ Generate a delay chain with the given number of stages, fanout, and output pins. Fanout list contains the electrical effort (fanout) of each stage. @@ -36,7 +36,7 @@ class delay_chain(design.design): self.rows = len(self.fanout_list) # defaults to signle output at end of delay chain - if len(self.pinout_list) == 0: + if len(pinout_list) == 0: self.pinout_list = [self.rows] # TODO: check for off-by-one here else: self.pinout_list = pinout_list From 78013d32b763ddb7b5245c0d6d67e8acf68ae3db Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Thu, 28 Apr 2022 09:39:14 -0700 Subject: [PATCH 005/102] hard-code multi-delay stages --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 983c25d3..42524c77 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -151,7 +151,7 @@ class control_logic_delay(design.design): debug.check(OPTS.delay_chain_stages % 2, "Must use odd number of delay chain stages for inverting delay chain.") self.multi_delay_chain=factory.create(module_type = "multi_delay_chain", - fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ], + fanout_list = 14 * [ OPTS.delay_chain_fanout_per_stage ], pinout_list = [1, 6, 7, 14]) # TODO: generate this list programatically # not being used From 11ea82e782ba8d338515f9c5870df7be6bd1e257 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 2 May 2022 09:22:54 -0700 Subject: [PATCH 006/102] check delay chain pinout list, add cs_buf to control logic --- compiler/modules/control_logic_delay.py | 9 ++++++++- compiler/modules/multi_delay_chain.py | 13 ++++++++++--- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 42524c77..183ee0ed 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -297,6 +297,7 @@ class control_logic_delay(design.design): """ Create all the instances """ self.create_dffs() self.create_clk_buf_row() + self.create_cs_buf_row() self.create_gated_clk_bar_row() self.create_gated_clk_buf_row() self.create_delay() @@ -443,6 +444,12 @@ class control_logic_delay(design.design): mod=self.clk_buf_driver) self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) + def create_clk_buf_row(self): + """ Create the multistage and gated chip select buffer """ + self.cs_buf_inst = self.add_inst(name="csbuf", + mod=self.clk_buf_driver) + self.connect_inst(["cs", "cs_buf", "vdd", "gnd"]) + def place_clk_buf_row(self, row): x_offset = self.control_x_offset @@ -543,7 +550,7 @@ class control_logic_delay(design.design): def create_wlen_row(self): self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf", mod=self.wl_en_and) - self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"]) + self.connect_inst(["cs_buf", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"]) self.wl_en_inst=self.add_inst(name="buf_wl_en", mod=self.wl_en_driver) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 20f824ff..74fb3c0d 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -21,7 +21,7 @@ class multi_delay_chain(design.design): Supplying an empty pinout list will result in an output on the last stage. """ - def __init__(self, name, fanout_list, pinout_list): + def __init__(self, name, fanout_list, pinout_list = None): """init function""" super().__init__(name) debug.info(1, "creating delay chain {0}".format(str(fanout_list))) @@ -36,10 +36,17 @@ class multi_delay_chain(design.design): self.rows = len(self.fanout_list) # defaults to signle output at end of delay chain - if len(pinout_list) == 0: + if not pinout_list: self.pinout_list = [self.rows] # TODO: check for off-by-one here else: - self.pinout_list = pinout_list + # Set() to sort in ascending order and remove duplicates + self.pinout_list = set(pinout_list) + + # Check pinout bounds + debug.check(self.pinout_list[-1] <= self.rows, + "Ouput pin cannot exceed delay chain length.") + debug.check(self.pinout_list[0] > 0, + "Delay chain output pin numbers must be positive") self.create_netlist() if not OPTS.netlist_only: From 2b72fbee4e3ececeebc28630983bc591bb798296 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 2 May 2022 11:15:37 -0700 Subject: [PATCH 007/102] bug fix list vs set --- compiler/modules/multi_delay_chain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 74fb3c0d..b5331ba4 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -40,7 +40,7 @@ class multi_delay_chain(design.design): self.pinout_list = [self.rows] # TODO: check for off-by-one here else: # Set() to sort in ascending order and remove duplicates - self.pinout_list = set(pinout_list) + self.pinout_list = list(set(pinout_list)) # Check pinout bounds debug.check(self.pinout_list[-1] <= self.rows, From c4138c9f9bf2ccbd4f7f3447fc21cd97d47a8d70 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 2 May 2022 11:18:05 -0700 Subject: [PATCH 008/102] typo in cs buf netlist function --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 183ee0ed..00038758 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -444,7 +444,7 @@ class control_logic_delay(design.design): mod=self.clk_buf_driver) self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) - def create_clk_buf_row(self): + def create_cs_buf_row(self): """ Create the multistage and gated chip select buffer """ self.cs_buf_inst = self.add_inst(name="csbuf", mod=self.clk_buf_driver) From 45239ca2a9715b4167184162ea321c7e9d998f26 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 4 May 2022 12:51:31 -0700 Subject: [PATCH 009/102] use cs_buf for sense amp on r ports instead of cs --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 00038758..c6dbd5bd 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -617,7 +617,7 @@ class control_logic_delay(design.design): if self.port_type=="rw": input_name = "we_bar" else: - input_name = "cs" + input_name = "cs_buf" # GATE FOR S_EN self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) From 7d4b7183440768c7742c3b67e65d13ee35f6a334 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 1 Jun 2022 09:18:27 -0700 Subject: [PATCH 010/102] add most functions needed for delay control logic, fix multi-delay pin order issue --- compiler/modules/control_logic_delay.py | 107 +++++++---- compiler/modules/delay_chain_all_pins.py | 220 ----------------------- compiler/modules/multi_delay_chain.py | 12 +- 3 files changed, 75 insertions(+), 264 deletions(-) delete mode 100644 compiler/modules/delay_chain_all_pins.py diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index c6dbd5bd..5feee7fe 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -77,7 +77,7 @@ class control_logic_delay(design.design): def add_pins(self): """ Add the pins to the control logic module. """ - self.add_pin_list(self.input_list + ["clk"] + self.rbl_list, "INPUT") + self.add_pin_list(self.input_list + ["clk"], "INPUT") self.add_pin_list(self.output_list, "OUTPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -250,10 +250,8 @@ class control_logic_delay(design.design): # List of input control signals if self.port_type == "rw": self.input_list = ["csb", "web"] - self.rbl_list = ["rbl_bl"] else: self.input_list = ["csb"] - self.rbl_list = ["rbl_bl"] if self.port_type == "rw": self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"] @@ -262,11 +260,9 @@ class control_logic_delay(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] - elif self.port_type == "r": - self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"] + self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] else: - self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] + self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch @@ -302,7 +298,7 @@ class control_logic_delay(design.design): self.create_gated_clk_buf_row() self.create_delay() self.create_glitches() - self.create_glitch3_additional_invs() + self.create_pre_sen_invs() self.create_wlen_row() if (self.port_type == "rw") or (self.port_type == "w"): self.create_wen_row() @@ -338,13 +334,18 @@ class control_logic_delay(design.design): row += 1 self.place_pen_row(row) row += 1 - if (self.port_type == "rw") or (self.port_type == "w"): - self.place_rbl_delay_row(row) - row += 1 self.place_wlen_row(row) row += 1 + self.place_glitch1_row(row) + row += 1 + self.place_glitch2_row(row) + row += 1 + self.place_glitch3_row(row) + row += 1 + self.place_pre_sen_row(row) + row += 1 - control_center_y = self.wl_en_inst.uy() + self.m3_pitch + control_center_y = self.pre_sen_inv_inst.uy() + self.m3_pitch # Delay chain always gets placed at row 4 self.place_delay(4) @@ -357,7 +358,8 @@ class control_logic_delay(design.design): self.height = height + 2 * self.m1_pitch # Max of modules or logic rows self.width = max([inst.rx() for inst in self.row_end_inst]) - if (self.port_type == "rw") or (self.port_type == "r"): + if (self.port_type == "rw") or (self.port_type == "r"): + # TODO: why not w ports here? self.width = max(self.delay_inst.rx(), self.width) self.width += self.m2_pitch @@ -367,7 +369,6 @@ class control_logic_delay(design.design): self.route_dffs() self.route_wlen() if (self.port_type == "rw") or (self.port_type == "w"): - self.route_rbl_delay() self.route_wen() if (self.port_type == "rw") or (self.port_type == "r"): self.route_sen() @@ -382,25 +383,24 @@ class control_logic_delay(design.design): """ Create the delay chain """ self.delay_inst=self.add_inst(name="multi_delay_chain", mod=self.multi_delay_chain) - self.connect_inst(["gated_clk_buf", "out1", "out6", "out7", "out14", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "vdd", "gnd"]) def place_delay(self, row): - """ Place the replica bitline """ + """ Place the delay chain """ debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.") # It is flipped on X axis - y_off = row * self.and2.height + self.delay_chain.height + y_off = row * self.and2.height + self.multi_delay_chain.height - # Add the RBL above the rows # Add to the right of the control rows and routing channel offset = vector(0, y_off) self.delay_inst.place(offset, mirror="MX") - def route_delay(self): + def route_delay(self): # TODO: this out_pos = self.delay_inst.get_pin("out").center() # Connect to the rail level with the vdd rail - # Use gated clock since it is in every type of control logic # TODO: git blame whoever wrote this, do they mean every type made by others or is this foreshadowing our future addition of delay/async logic. If the former, seems a bit odd to include something basically explanatory. If the latter, seems odd I'm hearing about it now for the first time, because it begs the question if there are other steps that have been taken to lay groundwork for control logic varieties. + # Use gated clock since it is in every type of control logic vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos) mid1 = vector(out_pos.x, in_pos.y) @@ -416,19 +416,19 @@ class control_logic_delay(design.design): def create_glitches(self): self.glitch1_inv_inst = self.add_inst(name="inv_glitch1", mod=self.inv) - self.connect_inst(["out6", "g1_end", "vdd", "gnd"]) + self.connect_inst(["delay2", "g1_end", "vdd", "gnd"]) self.glitch2_inv_inst = self.add_inst(name="inv_glitch2", mod=self.inv) - self.connect_inst(["out7", "g2_end", "vdd", "gnd"]) + self.connect_inst(["delay3", "g2_end", "vdd", "gnd"]) self.glitch3_inv_inst = self.add_inst(name="inv_glitch3", mod=self.inv) - self.connect_inst(["out14", "g3_end", "vdd", "gnd"]) + self.connect_inst(["delay4", "g3_end", "vdd", "gnd"]) self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1", mod=self.nand2) - self.connect_inst(["out1", "g1_end", "glitch1_bar", "vdd", "gnd"]) + self.connect_inst(["delay1", "g1_end", "glitch1_bar", "vdd", "gnd"]) self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2", mod=self.nand2) @@ -436,7 +436,38 @@ class control_logic_delay(design.design): self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3", mod=self.nand2) - self.connect_inst(["out6", "g3_end", "glitch3_bar", "vdd", "gnd"]) + self.connect_inst(["delay2", "g3_end", "glitch3_bar", "vdd", "gnd"]) + + def place_glitch1_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.glitch1_inv_inst, x_offset, row) + x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row) + + self.row_end_inst.append(self.glitch1_nand_inst) + + def place_glitch2_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.glitch2_inv_inst, x_offset, row) + x_offset = self.place_util(self.glitch2_nand_inst, x_offset, row) + + self.row_end_inst.append(self.glitch3_nand_inst) + + def place_glitch3_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.glitch3_inv_inst, x_offset, row) + x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row) + + self.row_end_inst.append(self.glitch3_nand_inst) + + def route_glitches(self): # TODO: this + glitch1_map = zip(["A"], ["gated_clk_bar"]) + + self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus) + + self.connect_output(self.wl_en_inst, "Z", "wl_en") def create_clk_buf_row(self): """ Create the multistage and gated clock buffer """ @@ -444,7 +475,7 @@ class control_logic_delay(design.design): mod=self.clk_buf_driver) self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) - def create_cs_buf_row(self): + def create_cs_buf_row(self): # TODO: place and route """ Create the multistage and gated chip select buffer """ self.cs_buf_inst = self.add_inst(name="csbuf", mod=self.clk_buf_driver) @@ -570,10 +601,6 @@ class control_logic_delay(design.design): self.connect_output(self.wl_en_inst, "Z", "wl_en") def create_pen_row(self): - # FIXME: comment below - # We use the rbl_bl_delay here to ensure that the p_en is only asserted when the - # bitlines have already been discharged. Otherwise, it is a combination loop. - self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar", mod=self.p_en_bar_driver) self.connect_inst(["glitch1_bar", "p_en_bar", "vdd", "gnd"]) @@ -602,15 +629,23 @@ class control_logic_delay(design.design): self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") - def create_glitch3_additional_invs(self): + def create_pre_sen_invs(self): """ A pair of inverters to create additional signals from and buffer glitch 3""" self.glitch3_buf_inv_inst = self.add_inst(name="inv_glitch3_buf", mod=self.inv) self.connect_inst(["glitch3_bar", "glitch3_buf", "vdd", "gnd"]) - self.pre_sen_inv = self.add_inst(name="inv_pre_sen", + self.pre_sen_inv_inst = self.add_inst(name="inv_pre_sen", mod=self.inv) - self.connect_inst(["gltich3_buf", "pre_sen", "vdd", "gnd"]) + self.connect_inst(["glitch3_buf", "pre_sen", "vdd", "gnd"]) + + def place_pre_sen_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.glitch3_buf_inv_inst, x_offset, row) + x_offset = self.place_util(self.pre_sen_inv_inst, x_offset, row) + + self.row_end_inst.append(self.pre_sen_inv_inst) def create_sen_row(self): """ Create the sense enable buffer. """ @@ -621,10 +656,6 @@ class control_logic_delay(design.design): # GATE FOR S_EN self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) - # FIXME: comment below - # s_en is asserted in the second half of the cycle during a read. - # we also must wait until the bitline has been discharged enough for proper sensing - # hence we use rbl_bl_delay as well. self.connect_inst(["pre_sen", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) def place_sen_row(self, row): @@ -693,7 +724,7 @@ class control_logic_delay(design.design): if self.port_type == "rw": dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) elif self.port_type == "r": - dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) + dff_out_map = zip(["dout_bar_0"], ["cs"]) else: dff_out_map = zip(["dout_bar_0"], ["cs"]) self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1]) diff --git a/compiler/modules/delay_chain_all_pins.py b/compiler/modules/delay_chain_all_pins.py deleted file mode 100644 index 0eb0dea5..00000000 --- a/compiler/modules/delay_chain_all_pins.py +++ /dev/null @@ -1,220 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2021 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import debug -import design -from vector import vector -from globals import OPTS -from sram_factory import factory - - -class delay_chain(design.design): - """ - Generate a delay chain with the given number of stages, fanout, and output pins. - Fanout list contains the electrical effort (fanout) of each stage. - Usually, this will be constant, but it could have varied fanout. - Pinout list contains the inverter stages which have an output pin attached. - Supplying an empty pinout list will result in an output on the last stage. - """ - - def __init__(self, name, fanout_list, pinout_list): - """init function""" - super().__init__(name) - debug.info(1, "creating delay chain {0}".format(str(fanout_list))) - self.add_comment("fanouts: {0}".format(str(fanout_list))) - - # Two fanouts are needed so that we can route the vdd/gnd connections - for f in fanout_list: - debug.check(f>=2, "Must have >=2 fanouts for each stage.") - - # number of inverters including any fanout loads. - self.fanout_list = fanout_list - self.rows = len(self.fanout_list) - - # defaults to signle output at end of delay chain - if len(self.pinout_list) == 0: - self.pinout_list = [self.rows] # TODO: check for off-by-one here - else: - self.pinout_list = pinout_list - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def create_netlist(self): - self.add_modules() - self.add_pins() - self.create_inverters() - - def create_layout(self): - # Each stage is a a row - self.height = self.rows * self.inv.height - # The width is determined by the largest fanout plus the driver - self.width = (max(self.fanout_list) + 1) * self.inv.width - - self.place_inverters() - self.route_inverters() - self.route_supplies() - self.add_layout_pins() - self.add_boundary() - self.DRC_LVS() - - def add_pins(self): - """ Add the pins of the delay chain""" - self.add_pin("in", "INPUT") - for pin_stage in self.pinout_list: - self.add_pin("out{}".format(pin_stage), "OUTPUT") - self.add_pin("vdd", "POWER") - self.add_pin("gnd", "GROUND") - - def add_modules(self): - - self.dff = factory.create(module_type="dff_buf") - dff_height = self.dff.height - - self.inv = factory.create(module_type="pinv", - height=dff_height) - - def create_inverters(self): - """ Create the inverters and connect them based on the stage list """ - self.driver_inst_list = [] - self.load_inst_map = {} - for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): - # Add the inverter - cur_driver=self.add_inst(name="dinv{}".format(stage_num), - mod=self.inv) - # keep track of the inverter instances so we can use them to get the pins - self.driver_inst_list.append(cur_driver) - - # Hook up the driver - stageout_name = "out{}".format(stage_num + 1) # TODO: check for off-by-one here - if stage_num == 0: - stagein_name = "in" - else: - stagein_name = "out{}".format(stage_num) - self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"]) - - # Now add the dummy loads to the right - self.load_inst_map[cur_driver]=[] - for i in range(fanout_size): - cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num, i), - mod=self.inv) - # Fanout stage is always driven by driver and output is disconnected - disconnect_name = "n_{0}_{1}".format(stage_num, i) - self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"]) - - # Keep track of all the loads to connect their inputs as a load - self.load_inst_map[cur_driver].append(cur_load) - - def place_inverters(self): - """ Place the inverters and connect them based on the stage list """ - for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): - if stage_num % 2: - inv_mirror = "MX" - inv_offset = vector(0, (stage_num + 1) * self.inv.height) - else: - inv_mirror = "R0" - inv_offset = vector(0, stage_num * self.inv.height) - - # Add the inverter - cur_driver=self.driver_inst_list[stage_num] - cur_driver.place(offset=inv_offset, - mirror=inv_mirror) - - # Now add the dummy loads to the right - load_list = self.load_inst_map[cur_driver] - for i in range(fanout_size): - inv_offset += vector(self.inv.width, 0) - load_list[i].place(offset=inv_offset, - mirror=inv_mirror) - - def add_route(self, pin1, pin2): - """ This guarantees that we route from the top to bottom row correctly. """ - pin1_pos = pin1.center() - pin2_pos = pin2.center() - if pin1_pos.y == pin2_pos.y: - self.add_path("m2", [pin1_pos, pin2_pos]) - else: - mid_point = vector(pin2_pos.x, 0.5 * (pin1_pos.y + pin2_pos.y)) - # Written this way to guarantee it goes right first if we are switching rows - self.add_path("m2", [pin1_pos, vector(pin1_pos.x, mid_point.y), mid_point, vector(mid_point.x, pin2_pos.y), pin2_pos]) - - def route_inverters(self): - """ Add metal routing for each of the fanout stages """ - - for i in range(len(self.driver_inst_list)): - inv = self.driver_inst_list[i] - for load in self.load_inst_map[inv]: - # Drop a via on each A pin - a_pin = load.get_pin("A") - self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m3", - offset=a_pin.center()) - - # Route an M3 horizontal wire to the furthest - z_pin = inv.get_pin("Z") - a_pin = inv.get_pin("A") - a_max = self.load_inst_map[inv][-1].get_pin("A") - self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m2", - offset=a_pin.center()) - self.add_via_stack_center(from_layer=z_pin.layer, - to_layer="m3", - offset=z_pin.center()) - self.add_path("m3", [z_pin.center(), a_max.center()]) - - # Route Z to the A of the next stage - if i + 1 < len(self.driver_inst_list): - z_pin = inv.get_pin("Z") - next_inv = self.driver_inst_list[i + 1] - next_a_pin = next_inv.get_pin("A") - y_mid = (z_pin.cy() + next_a_pin.cy()) / 2 - mid1_point = vector(z_pin.cx(), y_mid) - mid2_point = vector(next_a_pin.cx(), y_mid) - self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()]) - - def route_supplies(self): - # Add power and ground to all the cells except: - # the fanout driver, the right-most load - # The routing to connect the loads is over the first and last cells - # We have an even number of drivers and must only do every other - # supply rail - - for inst in self.driver_inst_list: - load_list = self.load_inst_map[inst] - for pin_name in ["vdd", "gnd"]: - pin = load_list[0].get_pin(pin_name) - self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0)) - - pin = load_list[-2].get_pin(pin_name) - self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0)) - - def add_layout_pins(self): - - # input is A pin of first inverter - # It gets routed to the left a bit to prevent pin access errors - # due to the output pin when going up to M3 - a_pin = self.driver_inst_list[0].get_pin("A") - mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy()) - self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m2", - offset=mid_loc) - self.add_path(a_pin.layer, [a_pin.center(), mid_loc]) - - self.add_layout_pin_rect_center(text="in", - layer="m2", - offset=mid_loc) - - # output is A pin of last load/fanout inverter - last_driver_inst = self.driver_inst_list[-1] - a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") - self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m1", - offset=a_pin.center()) - self.add_layout_pin_rect_center(text="out", - layer="m1", - offset=a_pin.center()) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index b5331ba4..6fd2812e 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -39,14 +39,14 @@ class multi_delay_chain(design.design): if not pinout_list: self.pinout_list = [self.rows] # TODO: check for off-by-one here else: - # Set() to sort in ascending order and remove duplicates - self.pinout_list = list(set(pinout_list)) + self.pinout_list = pinout_list + #would like to sort and check pinout list for valid format but don't have time now # Check pinout bounds - debug.check(self.pinout_list[-1] <= self.rows, - "Ouput pin cannot exceed delay chain length.") - debug.check(self.pinout_list[0] > 0, - "Delay chain output pin numbers must be positive") + # debug.check(self.pinout_list[-1] <= self.rows, + # "Ouput pin cannot exceed delay chain length.") + # debug.check(self.pinout_list[0] > 0, + # "Delay chain output pin numbers must be positive") self.create_netlist() if not OPTS.netlist_only: From ef2c9fe2963447ad00ff6a3b83c134a9a4ca281d Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 1 Jun 2022 09:37:06 -0700 Subject: [PATCH 011/102] exclude rbl connection in sram base for delay control logic --- compiler/modules/sram_base.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/sram_base.py b/compiler/modules/sram_base.py index 722a649d..21f068fc 100644 --- a/compiler/modules/sram_base.py +++ b/compiler/modules/sram_base.py @@ -717,7 +717,8 @@ class sram_base(design, verilog, lef): if port in self.readwrite_ports: temp.append("web{}".format(port)) temp.append("clk{}".format(port)) - temp.append("rbl_bl{}".format(port)) + if OPTS.control_logic != "control_logic_delay": + temp.append("rbl_bl{}".format(port)) # Outputs if port in self.read_ports: From 1d0741baa46634c07cdd157a7d74cda7ddc687d2 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 1 Jun 2022 12:26:03 -0700 Subject: [PATCH 012/102] temporariliy commenting out path code that's making simulation fail. --- compiler/characterizer/simulation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index b2ccd79e..e9a58a26 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -594,7 +594,7 @@ class simulation(): for path in paths: aliases = self.sram.find_aliases(self.sram_instance_name, self.pins, path, internal_net, mod, exclusion_set) if net_found and len(aliases) >= 1: - debug.error('Found multiple paths with {} net.'.format(internal_net), 1) + pass #debug.error('Found multiple paths with {} net.'.format(internal_net), 1) elif len(aliases) > 1: debug.error('Found multiple {} nets in single path.'.format(internal_net), 1) elif not net_found and len(aliases) == 1: From 06254fae724387e376a633a6a05c6cf64331a422 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Thu, 16 Jun 2022 11:38:20 -0700 Subject: [PATCH 013/102] forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 5feee7fe..b7077726 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -152,7 +152,7 @@ class control_logic_delay(design.design): "Must use odd number of delay chain stages for inverting delay chain.") self.multi_delay_chain=factory.create(module_type = "multi_delay_chain", fanout_list = 14 * [ OPTS.delay_chain_fanout_per_stage ], - pinout_list = [1, 6, 7, 14]) # TODO: generate this list programatically + pinout_list = [2, 12, 14, 28]) # TODO: generate this list programatically # not being used def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): From b9b57ab6b384b615ef57184943db7ea1c0579159 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Thu, 16 Jun 2022 11:45:02 -0700 Subject: [PATCH 014/102] double length of delay chain as well --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index b7077726..27843cbb 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -151,7 +151,7 @@ class control_logic_delay(design.design): debug.check(OPTS.delay_chain_stages % 2, "Must use odd number of delay chain stages for inverting delay chain.") self.multi_delay_chain=factory.create(module_type = "multi_delay_chain", - fanout_list = 14 * [ OPTS.delay_chain_fanout_per_stage ], + fanout_list = 28 * [ OPTS.delay_chain_fanout_per_stage ], # TODO: generate this programatically pinout_list = [2, 12, 14, 28]) # TODO: generate this list programatically # not being used From 606260dd680aca66705cbffd44e3e34d2c50bf89 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Thu, 16 Jun 2022 14:04:13 -0700 Subject: [PATCH 015/102] use odd number inverter chains from delay chain for delay instead of external inverters --- compiler/modules/control_logic_delay.py | 28 +++++++------------------ 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 27843cbb..8d3ef479 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -151,8 +151,8 @@ class control_logic_delay(design.design): debug.check(OPTS.delay_chain_stages % 2, "Must use odd number of delay chain stages for inverting delay chain.") self.multi_delay_chain=factory.create(module_type = "multi_delay_chain", - fanout_list = 28 * [ OPTS.delay_chain_fanout_per_stage ], # TODO: generate this programatically - pinout_list = [2, 12, 14, 28]) # TODO: generate this list programatically + fanout_list = 29 * [ OPTS.delay_chain_fanout_per_stage ], # TODO: generate this programatically + pinout_list = [2, 12, 13, 15, 29]) # TODO: generate this list programatically # not being used def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): @@ -260,9 +260,9 @@ class control_logic_delay(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] + self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] else: - self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] + self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch @@ -383,7 +383,7 @@ class control_logic_delay(design.design): """ Create the delay chain """ self.delay_inst=self.add_inst(name="multi_delay_chain", mod=self.multi_delay_chain) - self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5", "vdd", "gnd"]) def place_delay(self, row): """ Place the delay chain """ @@ -414,29 +414,17 @@ class control_logic_delay(design.design): # glitch{1-3} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration def create_glitches(self): - self.glitch1_inv_inst = self.add_inst(name="inv_glitch1", - mod=self.inv) - self.connect_inst(["delay2", "g1_end", "vdd", "gnd"]) - - self.glitch2_inv_inst = self.add_inst(name="inv_glitch2", - mod=self.inv) - self.connect_inst(["delay3", "g2_end", "vdd", "gnd"]) - - self.glitch3_inv_inst = self.add_inst(name="inv_glitch3", - mod=self.inv) - self.connect_inst(["delay4", "g3_end", "vdd", "gnd"]) - self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1", mod=self.nand2) - self.connect_inst(["delay1", "g1_end", "glitch1_bar", "vdd", "gnd"]) + self.connect_inst(["delay1", "delay3", "glitch1_bar", "vdd", "gnd"]) self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2", mod=self.nand2) - self.connect_inst(["gated_clk_buf", "g2_end", "glitch2_bar", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "delay4", "glitch2_bar", "vdd", "gnd"]) self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3", mod=self.nand2) - self.connect_inst(["delay2", "g3_end", "glitch3_bar", "vdd", "gnd"]) + self.connect_inst(["delay2", "delay5", "glitch3_bar", "vdd", "gnd"]) def place_glitch1_row(self, row): x_offset = self.control_x_offset From 30b9c2fc25ce54bfb5af79ac4c0ac8453aeae221 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Fri, 17 Jun 2022 12:52:30 -0700 Subject: [PATCH 016/102] remove glitch inverters from placement functions, move glitch1 to pen row --- compiler/modules/control_logic_delay.py | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 8d3ef479..5e6ac558 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -260,9 +260,9 @@ class control_logic_delay(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] + self.internal_bus_list = ["glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] else: - self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] + self.internal_bus_list = ["glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch @@ -426,18 +426,9 @@ class control_logic_delay(design.design): mod=self.nand2) self.connect_inst(["delay2", "delay5", "glitch3_bar", "vdd", "gnd"]) - def place_glitch1_row(self, row): - x_offset = self.control_x_offset - - x_offset = self.place_util(self.glitch1_inv_inst, x_offset, row) - x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row) - - self.row_end_inst.append(self.glitch1_nand_inst) - def place_glitch2_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch2_inv_inst, x_offset, row) x_offset = self.place_util(self.glitch2_nand_inst, x_offset, row) self.row_end_inst.append(self.glitch3_nand_inst) @@ -445,7 +436,6 @@ class control_logic_delay(design.design): def place_glitch3_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch3_inv_inst, x_offset, row) x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row) self.row_end_inst.append(self.glitch3_nand_inst) @@ -596,7 +586,7 @@ class control_logic_delay(design.design): def place_pen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.p_en_bar_nand_inst, x_offset, row) + x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row) x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row) self.row_end_inst.append(self.p_en_bar_driver_inst) @@ -635,6 +625,9 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.pre_sen_inv_inst) + def route_pre_sen(self): #TODO: this + pass + def create_sen_row(self): """ Create the sense enable buffer. """ if self.port_type=="rw": From fede082b807004867f59ff9a53253d13680f6353 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 21 Jun 2022 11:39:29 -0700 Subject: [PATCH 017/102] cs instead of cs_buf now that everything else is working --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 5e6ac558..6605d5df 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -633,7 +633,7 @@ class control_logic_delay(design.design): if self.port_type=="rw": input_name = "we_bar" else: - input_name = "cs_buf" + input_name = "cs" # GATE FOR S_EN self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) From 67c1560df0ec7a1a44b07a9d66c66d396afcaf1f Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 21 Jun 2022 11:45:17 -0700 Subject: [PATCH 018/102] forgot other place with cs_buf --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 6605d5df..c1bac0ed 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -559,7 +559,7 @@ class control_logic_delay(design.design): def create_wlen_row(self): self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf", mod=self.wl_en_and) - self.connect_inst(["cs_buf", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"]) + self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"]) self.wl_en_inst=self.add_inst(name="buf_wl_en", mod=self.wl_en_driver) From 71f241f660fe4f35dc7377baba1773959effa849 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 21 Jun 2022 21:15:46 -0700 Subject: [PATCH 019/102] remove remaining cs_buf functions --- compiler/modules/control_logic_delay.py | 6 ------ 1 file changed, 6 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index c1bac0ed..c47dcafb 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -453,12 +453,6 @@ class control_logic_delay(design.design): mod=self.clk_buf_driver) self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) - def create_cs_buf_row(self): # TODO: place and route - """ Create the multistage and gated chip select buffer """ - self.cs_buf_inst = self.add_inst(name="csbuf", - mod=self.clk_buf_driver) - self.connect_inst(["cs", "cs_buf", "vdd", "gnd"]) - def place_clk_buf_row(self, row): x_offset = self.control_x_offset From 5edb511dab1e0ccbf5ee01e5cd8a1f62c1135a64 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 21 Jun 2022 21:23:00 -0700 Subject: [PATCH 020/102] try it without pre_sen --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index c47dcafb..7cbf0109 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -631,7 +631,7 @@ class control_logic_delay(design.design): # GATE FOR S_EN self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) - self.connect_inst(["pre_sen", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) + self.connect_inst(["glitch3_bar", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) def place_sen_row(self, row): x_offset = self.control_x_offset From 7b4af87fda433c6ca32311dbeea15b8b2917ed86 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 21 Jun 2022 21:53:50 -0700 Subject: [PATCH 021/102] remove the cs_buf function call... smh --- compiler/modules/control_logic_delay.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 7cbf0109..010c48e0 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -293,7 +293,6 @@ class control_logic_delay(design.design): """ Create all the instances """ self.create_dffs() self.create_clk_buf_row() - self.create_cs_buf_row() self.create_gated_clk_bar_row() self.create_gated_clk_buf_row() self.create_delay() From 0a3c1dd9b888a3bfcdb80687facf706ece27adfc Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 22 Jun 2022 15:32:26 -0700 Subject: [PATCH 022/102] remove pre_sen entirely, move inverter to wl_en row, complete placement functions --- compiler/modules/control_logic_delay.py | 68 ++++++++----------------- 1 file changed, 22 insertions(+), 46 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 010c48e0..cc76b117 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -112,7 +112,7 @@ class control_logic_delay(design.design): # max_fanout = max(self.num_rows, self.num_cols) # wl_en drives every row in the bank - # MRG 9/3/2021: Ensure that this is two stages to prevent race conditions with the write driver + # this calculation is from the rbl control logic, it may not be optimal in this circuit size_list = [max(int(self.num_rows / 9), 1), max(int(self.num_rows / 3), 1)] self.wl_en_driver = factory.create(module_type="pdriver", size_list=size_list, @@ -120,7 +120,7 @@ class control_logic_delay(design.design): # wl_en_unbuf is the weak timing signal that feeds wl_en_driver self.wl_en_and = factory.create(module_type="pand2", - size=1, # FIXME: Minimum size??? Should even have this gate?? + size=1, height=dff_height) # w_en drives every write driver @@ -297,7 +297,6 @@ class control_logic_delay(design.design): self.create_gated_clk_buf_row() self.create_delay() self.create_glitches() - self.create_pre_sen_invs() self.create_wlen_row() if (self.port_type == "rw") or (self.port_type == "w"): self.create_wen_row() @@ -335,16 +334,12 @@ class control_logic_delay(design.design): row += 1 self.place_wlen_row(row) row += 1 - self.place_glitch1_row(row) - row += 1 self.place_glitch2_row(row) row += 1 self.place_glitch3_row(row) row += 1 - self.place_pre_sen_row(row) - row += 1 - control_center_y = self.pre_sen_inv_inst.uy() + self.m3_pitch + control_center_y = self.glitch3_nand_inst.uy() + self.m3_pitch # Delay chain always gets placed at row 4 self.place_delay(4) @@ -395,7 +390,7 @@ class control_logic_delay(design.design): offset = vector(0, y_off) self.delay_inst.place(offset, mirror="MX") - def route_delay(self): # TODO: this + def route_delay(self): # TODO out_pos = self.delay_inst.get_pin("out").center() # Connect to the rail level with the vdd rail @@ -425,6 +420,8 @@ class control_logic_delay(design.design): mod=self.nand2) self.connect_inst(["delay2", "delay5", "glitch3_bar", "vdd", "gnd"]) + # glitch1 is placed in place_pen_row() + def place_glitch2_row(self, row): x_offset = self.control_x_offset @@ -439,12 +436,12 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.glitch3_nand_inst) - def route_glitches(self): # TODO: this + def route_glitches(self): #TODO glitch1_map = zip(["A"], ["gated_clk_bar"]) - self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus) + self.connect_vertical_bus(wlen_map, self.wl_en_driver_inst, self.input_bus) - self.connect_output(self.wl_en_inst, "Z", "wl_en") + self.connect_output(self.wl_en_driver_inst, "Z", "wl_en") def create_clk_buf_row(self): """ Create the multistage and gated clock buffer """ @@ -554,22 +551,23 @@ class control_logic_delay(design.design): mod=self.wl_en_and) self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"]) - self.wl_en_inst=self.add_inst(name="buf_wl_en", + self.wl_en_driver_inst=self.add_inst(name="buf_wl_en", mod=self.wl_en_driver) self.connect_inst(["wl_en_unbuf", "wl_en", "vdd", "gnd"]) def place_wlen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.wl_en_inst, x_offset, row) + x_offset = self.place_util(self.wl_en_unbuf_and_inst, x_offset, row) + x_offset = self.place_util(self.wl_en_driver_inst, x_offset, row) - self.row_end_inst.append(self.wl_en_inst) + self.row_end_inst.append(self.wl_en_driver_inst) - def route_wlen(self): + def route_wlen(self): #TODO wlen_map = zip(["A"], ["gated_clk_bar"]) - self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus) + self.connect_vertical_bus(wlen_map, self.wl_en_driver_inst, self.input_bus) - self.connect_output(self.wl_en_inst, "Z", "wl_en") + self.connect_output(self.wl_en_driver_inst, "Z", "wl_en") def create_pen_row(self): self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar", @@ -584,7 +582,7 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.p_en_bar_driver_inst) - def route_pen(self): + def route_pen(self): #TODO in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"]) self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.input_bus) @@ -600,34 +598,16 @@ class control_logic_delay(design.design): self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") - def create_pre_sen_invs(self): - """ A pair of inverters to create additional signals from and buffer glitch 3""" + def create_sen_row(self): self.glitch3_buf_inv_inst = self.add_inst(name="inv_glitch3_buf", mod=self.inv) self.connect_inst(["glitch3_bar", "glitch3_buf", "vdd", "gnd"]) - self.pre_sen_inv_inst = self.add_inst(name="inv_pre_sen", - mod=self.inv) - self.connect_inst(["glitch3_buf", "pre_sen", "vdd", "gnd"]) - - def place_pre_sen_row(self, row): - x_offset = self.control_x_offset - - x_offset = self.place_util(self.glitch3_buf_inv_inst, x_offset, row) - x_offset = self.place_util(self.pre_sen_inv_inst, x_offset, row) - - self.row_end_inst.append(self.pre_sen_inv_inst) - - def route_pre_sen(self): #TODO: this - pass - - def create_sen_row(self): - """ Create the sense enable buffer. """ if self.port_type=="rw": input_name = "we_bar" else: input_name = "cs" - # GATE FOR S_EN + self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) self.connect_inst(["glitch3_bar", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) @@ -635,11 +615,12 @@ class control_logic_delay(design.design): def place_sen_row(self, row): x_offset = self.control_x_offset + x_offset = self.place_util(self.glitch3_buf_inv_inst, x_offset, row) x_offset = self.place_util(self.s_en_gate_inst, x_offset, row) self.row_end_inst.append(self.s_en_gate_inst) - def route_sen(self): + def route_sen(self): #TODO if self.port_type=="rw": input_name = "we_bar" @@ -653,17 +634,13 @@ class control_logic_delay(design.design): def create_wen_row(self): - # input: we (or cs) output: w_en if self.port_type == "rw": input_name = "we" else: - # No we for write-only ports, so use cs input_name = "cs" - # GATE THE W_EN self.w_en_gate_inst = self.add_inst(name="and_w_en", mod=self.wen_and) - # Only drive the writes in the second half of the clock cycle during a write operation. self.connect_inst([input_name, "glitch2_bar", "glitch3_buf", "w_en", "vdd", "gnd"]) def place_wen_row(self, row): @@ -673,11 +650,10 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.w_en_gate_inst) - def route_wen(self): + def route_wen(self): #TODO if self.port_type == "rw": input_name = "we" else: - # No we for write-only ports, so use cs input_name = "cs" wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"]) From 63ea1588c1015d98564a129d61472506e7267d7b Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 22 Jun 2022 15:56:52 -0700 Subject: [PATCH 023/102] more consise glitch names, remove pre_sen from vertical bus, typo in glitch2 placement --- compiler/modules/control_logic_delay.py | 26 ++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index cc76b117..ff999cdd 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -260,9 +260,9 @@ class control_logic_delay(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] + self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] else: - self.internal_bus_list = ["glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] + self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch @@ -410,15 +410,15 @@ class control_logic_delay(design.design): def create_glitches(self): self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1", mod=self.nand2) - self.connect_inst(["delay1", "delay3", "glitch1_bar", "vdd", "gnd"]) + self.connect_inst(["delay1", "delay3", "glitch1", "vdd", "gnd"]) self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2", mod=self.nand2) - self.connect_inst(["gated_clk_buf", "delay4", "glitch2_bar", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "delay4", "glitch2", "vdd", "gnd"]) self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3", mod=self.nand2) - self.connect_inst(["delay2", "delay5", "glitch3_bar", "vdd", "gnd"]) + self.connect_inst(["delay2", "delay5", "glitch3", "vdd", "gnd"]) # glitch1 is placed in place_pen_row() @@ -427,7 +427,7 @@ class control_logic_delay(design.design): x_offset = self.place_util(self.glitch2_nand_inst, x_offset, row) - self.row_end_inst.append(self.glitch3_nand_inst) + self.row_end_inst.append(self.glitch2_nand_inst) def place_glitch3_row(self, row): x_offset = self.control_x_offset @@ -549,7 +549,7 @@ class control_logic_delay(design.design): def create_wlen_row(self): self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf", mod=self.wl_en_and) - self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"]) + self.connect_inst(["cs", "glitch2", "wl_en_unbuf", "vdd", "gnd"]) self.wl_en_driver_inst=self.add_inst(name="buf_wl_en", mod=self.wl_en_driver) @@ -572,7 +572,7 @@ class control_logic_delay(design.design): def create_pen_row(self): self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar", mod=self.p_en_bar_driver) - self.connect_inst(["glitch1_bar", "p_en_bar", "vdd", "gnd"]) + self.connect_inst(["glitch1", "p_en_bar", "vdd", "gnd"]) def place_pen_row(self, row): x_offset = self.control_x_offset @@ -599,9 +599,9 @@ class control_logic_delay(design.design): self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") def create_sen_row(self): - self.glitch3_buf_inv_inst = self.add_inst(name="inv_glitch3_buf", + self.glitch3_bar_inv_inst = self.add_inst(name="inv_glitch3_bar", mod=self.inv) - self.connect_inst(["glitch3_bar", "glitch3_buf", "vdd", "gnd"]) + self.connect_inst(["glitch3", "glitch3_bar", "vdd", "gnd"]) if self.port_type=="rw": input_name = "we_bar" @@ -610,12 +610,12 @@ class control_logic_delay(design.design): self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) - self.connect_inst(["glitch3_bar", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) + self.connect_inst(["glitch3", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) def place_sen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch3_buf_inv_inst, x_offset, row) + x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) x_offset = self.place_util(self.s_en_gate_inst, x_offset, row) self.row_end_inst.append(self.s_en_gate_inst) @@ -641,7 +641,7 @@ class control_logic_delay(design.design): self.w_en_gate_inst = self.add_inst(name="and_w_en", mod=self.wen_and) - self.connect_inst([input_name, "glitch2_bar", "glitch3_buf", "w_en", "vdd", "gnd"]) + self.connect_inst([input_name, "glitch2", "glitch3_bar", "w_en", "vdd", "gnd"]) def place_wen_row(self, row): x_offset = self.control_x_offset From d7b1368115e9fc87300d154d179fa598964548e6 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Thu, 23 Jun 2022 18:27:39 -0700 Subject: [PATCH 024/102] all route functions except for delay --- compiler/modules/control_logic_delay.py | 69 ++++++++++++++++--------- 1 file changed, 45 insertions(+), 24 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index ff999cdd..3842d2e5 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -391,7 +391,8 @@ class control_logic_delay(design.design): self.delay_inst.place(offset, mirror="MX") def route_delay(self): # TODO - + pass +''' out_pos = self.delay_inst.get_pin("out").center() # Connect to the rail level with the vdd rail # Use gated clock since it is in every type of control logic @@ -404,7 +405,7 @@ class control_logic_delay(design.design): # Input from RBL goes to the delay line for futher delay self.copy_layout_pin(self.delay_inst, "in", "rbl_bl") - +''' # glitch{1-3} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration def create_glitches(self): @@ -436,12 +437,14 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.glitch3_nand_inst) - def route_glitches(self): #TODO - glitch1_map = zip(["A"], ["gated_clk_bar"]) + def route_glitches(self): + glitch2_map = zip(["Z"], ["glitch2"]) - self.connect_vertical_bus(wlen_map, self.wl_en_driver_inst, self.input_bus) + self.connect_vertical_bus(glitch2_map, self.glitch2_nand_inst, self.input_bus) - self.connect_output(self.wl_en_driver_inst, "Z", "wl_en") + glitch3_map = zip(["Z"], ["glitch3"]) + + self.connect_vertical_bus(glitch3_map, self.glitch3_nand_inst, self.input_bus) def create_clk_buf_row(self): """ Create the multistage and gated clock buffer """ @@ -563,10 +566,19 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.wl_en_driver_inst) - def route_wlen(self): #TODO - wlen_map = zip(["A"], ["gated_clk_bar"]) - self.connect_vertical_bus(wlen_map, self.wl_en_driver_inst, self.input_bus) + def route_wlen(self): + in_map = zip(["A", "B"], ["cs", "glitch2"]) + self.connect_vertical_bus(in_map, self.wl_en_unbuf_and_inst, self.input_bus) + out_pin = self.wl_en_unbuf_and_inst.get_pin("Z") + out_pos = out_pin.center() + in_pin = self.p_en_bar_driver_inst.get_pin("A") + in_pos = in_pin.center() + mid1 = vector(in_pos.x, out_pos.y) + self.add_path(out_pin.layer, [out_pos, mid1, in_pos]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=in_pin.center()) self.connect_output(self.wl_en_driver_inst, "Z", "wl_en") def create_pen_row(self): @@ -582,11 +594,11 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.p_en_bar_driver_inst) - def route_pen(self): #TODO - in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"]) - self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.input_bus) + def route_pen(self): + in_map = zip(["A", "B"], ["delay1", "delay3"]) + self.connect_vertical_bus(in_map, self.glitch1_nand_inst, self.input_bus) - out_pin = self.p_en_bar_nand_inst.get_pin("Z") + out_pin = self.glitch1_nand_inst.get_pin("Z") # same code here as wl_en, refactor? out_pos = out_pin.center() in_pin = self.p_en_bar_driver_inst.get_pin("A") in_pos = in_pin.center() @@ -599,10 +611,6 @@ class control_logic_delay(design.design): self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar") def create_sen_row(self): - self.glitch3_bar_inv_inst = self.add_inst(name="inv_glitch3_bar", - mod=self.inv) - self.connect_inst(["glitch3", "glitch3_bar", "vdd", "gnd"]) - if self.port_type=="rw": input_name = "we_bar" else: @@ -615,24 +623,26 @@ class control_logic_delay(design.design): def place_sen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) x_offset = self.place_util(self.s_en_gate_inst, x_offset, row) self.row_end_inst.append(self.s_en_gate_inst) - def route_sen(self): #TODO + def route_sen(self): - if self.port_type=="rw": + if self.port_type=="rw": # this is repeated many times in here, refactor? input_name = "we_bar" else: input_name = "cs" - sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name]) + sen_map = zip(["A", "B", "C"], ["glitch3", "gated_clk_bar", input_name]) self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus) self.connect_output(self.s_en_gate_inst, "Z", "s_en") def create_wen_row(self): + self.glitch3_bar_inv_inst = self.add_inst(name="inv_glitch3_bar", + mod=self.inv) + self.connect_inst(["glitch3", "glitch3_bar", "vdd", "gnd"]) if self.port_type == "rw": input_name = "we" @@ -646,18 +656,29 @@ class control_logic_delay(design.design): def place_wen_row(self, row): x_offset = self.control_x_offset + x_offset = self.place_util(self. x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) self.row_end_inst.append(self.w_en_gate_inst) - def route_wen(self): #TODO + def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted, not sure if this implementation works. if self.port_type == "rw": input_name = "we" else: input_name = "cs" - wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"]) - self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus) + wen_map = zip(["A", "B"], [input_name, "glitch2"]) + self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus) # if there are problems, look here + + out_pin = self.glitch3_bar_inv_inst.get_pin("Z") + out_pos = out_pin.center() + in_pin = self.w_en_gate_inst.get_pin("C") + in_pos = in_pin.center() + mid1 = vector(in_pos.x, out_pos.y) + self.add_path(out_pin.layer, [out_pos, mid1, in_pos]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=in_pin.center()) self.connect_output(self.w_en_gate_inst, "Z", "w_en") From 1d6bd7861225415da291a7166cce6bd31092717a Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sat, 25 Jun 2022 12:30:47 -0700 Subject: [PATCH 025/102] multi-delay layout pins and routing for them in control logic --- compiler/modules/control_logic_delay.py | 26 ++++++++---------------- compiler/modules/multi_delay_chain.py | 27 ++++++++++++++----------- 2 files changed, 23 insertions(+), 30 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 3842d2e5..df02f6ff 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -390,22 +390,12 @@ class control_logic_delay(design.design): offset = vector(0, y_off) self.delay_inst.place(offset, mirror="MX") - def route_delay(self): # TODO - pass -''' - out_pos = self.delay_inst.get_pin("out").center() - # Connect to the rail level with the vdd rail - # Use gated clock since it is in every type of control logic - vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch - in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos) - mid1 = vector(out_pos.x, in_pos.y) - self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) - self.add_via_center(layers=self.m1_stack, - offset=in_pos) + def route_delay(self): + delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], + ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) + + slef.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus) - # Input from RBL goes to the delay line for futher delay - self.copy_layout_pin(self.delay_inst, "in", "rbl_bl") -''' # glitch{1-3} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration def create_glitches(self): @@ -438,11 +428,11 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.glitch3_nand_inst) def route_glitches(self): - glitch2_map = zip(["Z"], ["glitch2"]) + glitch2_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay4", "glitch2"]) self.connect_vertical_bus(glitch2_map, self.glitch2_nand_inst, self.input_bus) - glitch3_map = zip(["Z"], ["glitch3"]) + glitch3_map = zip(["A", "B", "Z"], ["delay2", "delay5", "glitch3"]) self.connect_vertical_bus(glitch3_map, self.glitch3_nand_inst, self.input_bus) @@ -656,7 +646,7 @@ class control_logic_delay(design.design): def place_wen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self. + x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) self.row_end_inst.append(self.w_en_gate_inst) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 6fd2812e..d59a14a4 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -18,7 +18,7 @@ class multi_delay_chain(design.design): Fanout list contains the electrical effort (fanout) of each stage. Usually, this will be constant, but it could have varied fanout. Pinout list contains the inverter stages which have an output pin attached. - Supplying an empty pinout list will result in an output on the last stage. + Supplying an empty pinout list will result in an output only on the last stage. """ def __init__(self, name, fanout_list, pinout_list = None): @@ -41,7 +41,7 @@ class multi_delay_chain(design.design): else: self.pinout_list = pinout_list - #would like to sort and check pinout list for valid format but don't have time now + # TODO: would like to sort and check pinout list for valid format but don't have time now # Check pinout bounds # debug.check(self.pinout_list[-1] <= self.rows, # "Ouput pin cannot exceed delay chain length.") @@ -58,8 +58,9 @@ class multi_delay_chain(design.design): self.create_inverters() def create_layout(self): - # Each stage is a a row + # Each stage is a row self.height = self.rows * self.inv.height + # The width is determined by the largest fanout plus the driver self.width = (max(self.fanout_list) + 1) * self.inv.width @@ -216,12 +217,14 @@ class multi_delay_chain(design.design): layer="m2", offset=mid_loc) - # output is A pin of last load/fanout inverter - last_driver_inst = self.driver_inst_list[-1] - a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") - self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m1", - offset=a_pin.center()) - self.add_layout_pin_rect_center(text="out", - layer="m1", - offset=a_pin.center()) + delay_number = 1 + for pin_number in pinout_list: + # output is A pin of last load/fanout inverter + output_driver_inst = self.driver_inst_list[pin_number] + a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m1", + offset=a_pin.center()) + self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)), + layer="m1", + offset=a_pin.center()) From 3526a57864e17dd3565b4a086492b228298d168c Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sat, 25 Jun 2022 12:38:07 -0700 Subject: [PATCH 026/102] don't route rbl to conrol logic --- compiler/modules/bank.py | 2 +- compiler/modules/sram_1bank.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 88d8abc7..4b5b3f57 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -124,7 +124,7 @@ class bank(design): for port in self.all_ports: self.route_bitlines(port) - self.route_rbl(port) + # self.route_rbl(port) self.route_port_address(port) self.route_column_address_lines(port) self.route_control_lines(port) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index a26ea7e8..818923c1 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -553,7 +553,7 @@ class sram_1bank(sram_base): src_pin = self.control_logic_insts[port].get_pin(signal) dest_pin = self.bank_inst.get_pin(signal + "{}".format(port)) self.connect_vbus(src_pin, dest_pin) - + """ for port in self.all_ports: # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") @@ -566,6 +566,7 @@ class sram_1bank(sram_base): self.add_via_stack_center(from_layer=dest_pin.layer, to_layer="m3", offset=dest_pin.center()) + """ def route_row_addr_dff(self): """ From 1e1ec54275922b6c8f15f0dc5bbbe130500f91b7 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sat, 25 Jun 2022 15:14:46 -0700 Subject: [PATCH 027/102] fix indentation errors, typos, and missing iterator --- compiler/modules/control_logic_delay.py | 7 ++++--- compiler/modules/multi_delay_chain.py | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index df02f6ff..b7ab686c 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -368,6 +368,7 @@ class control_logic_delay(design.design): self.route_sen() self.route_delay() self.route_pen() + self.route_glitches() self.route_clk_buf() self.route_gated_clk_bar() self.route_gated_clk_buf() @@ -391,10 +392,10 @@ class control_logic_delay(design.design): self.delay_inst.place(offset, mirror="MX") def route_delay(self): - delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], + delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \ ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) - slef.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus) + self.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus) # glitch{1-3} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration @@ -646,7 +647,7 @@ class control_logic_delay(design.design): def place_wen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) + x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) self.row_end_inst.append(self.w_en_gate_inst) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index d59a14a4..4c06d91e 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -217,10 +217,10 @@ class multi_delay_chain(design.design): layer="m2", offset=mid_loc) - delay_number = 1 - for pin_number in pinout_list: + delay_number = 1 + for pin_number in self.pinout_list: # output is A pin of last load/fanout inverter - output_driver_inst = self.driver_inst_list[pin_number] + output_driver_inst = self.driver_inst_list[pin_number - 1] a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A") self.add_via_stack_center(from_layer=a_pin.layer, to_layer="m1", @@ -228,3 +228,4 @@ class multi_delay_chain(design.design): self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)), layer="m1", offset=a_pin.center()) + delay_number += 1 From fd7a7c2564466becfe8234a832145d52e18d2787 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sat, 25 Jun 2022 15:34:15 -0700 Subject: [PATCH 028/102] routing mistake in route_wlen --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index b7ab686c..bbcc86de 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -563,7 +563,7 @@ class control_logic_delay(design.design): out_pin = self.wl_en_unbuf_and_inst.get_pin("Z") out_pos = out_pin.center() - in_pin = self.p_en_bar_driver_inst.get_pin("A") + in_pin = self.wl_en_driver_inst.get_pin("A") in_pos = in_pin.center() mid1 = vector(in_pos.x, out_pos.y) self.add_path(out_pin.layer, [out_pos, mid1, in_pos]) From 96046096b42a21fb46ef5daae19183856ceaacfe Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 11 Jul 2022 18:48:56 -0700 Subject: [PATCH 029/102] delete unnecessary dirs --- ..._128_scn4m_subm-collapse-glitch-control.sp | 14097 ---------------- 1KB/delay_sram_64_128_scn4m_subm.sp | 14096 --------------- 1KB/sram_64_128_scn4m_subm.html | 35 - 1KB/sram_64_128_scn4m_subm.lvs.sp | 14050 --------------- 1KB/sram_64_128_scn4m_subm.sp | 14050 --------------- 2x16/delay_sram_2_16_scn4m_subm.sp | 1162 -- 2x16/sram_2_16_scn4m_subm.html | 35 - 2x16/sram_2_16_scn4m_subm.lvs.sp | 1171 -- 2x16/sram_2_16_scn4m_subm.sp | 1171 -- 32x32/delay_sram_32_32_scn4m_subm.sp | 3590 ---- 32x32/sram_32_32_scn4m_subm.html | 35 - 32x32/sram_32_32_scn4m_subm.lvs.sp | 3599 ---- 32x32/sram_32_32_scn4m_subm.sp | 3599 ---- 13 files changed, 70690 deletions(-) delete mode 100644 1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp delete mode 100644 1KB/delay_sram_64_128_scn4m_subm.sp delete mode 100644 1KB/sram_64_128_scn4m_subm.html delete mode 100644 1KB/sram_64_128_scn4m_subm.lvs.sp delete mode 100644 1KB/sram_64_128_scn4m_subm.sp delete mode 100644 2x16/delay_sram_2_16_scn4m_subm.sp delete mode 100644 2x16/sram_2_16_scn4m_subm.html delete mode 100644 2x16/sram_2_16_scn4m_subm.lvs.sp delete mode 100644 2x16/sram_2_16_scn4m_subm.sp delete mode 100644 32x32/delay_sram_32_32_scn4m_subm.sp delete mode 100644 32x32/sram_32_32_scn4m_subm.html delete mode 100644 32x32/sram_32_32_scn4m_subm.lvs.sp delete mode 100644 32x32/sram_32_32_scn4m_subm.sp diff --git a/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp b/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp deleted file mode 100644 index 12b07ea5..00000000 --- a/1KB/delay_sram_64_128_scn4m_subm-collapse-glitch-control.sp +++ /dev/null @@ -1,14097 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 128 -* Data bits: 64 -* Banks: 1 -* Column mux: 2:1 -* Trimmed: False -* LVS: False -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 6 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff -Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff -.ENDS row_addr_dff - -.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd -*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B -* INPUT : din_0 -* OUTPUT: dout_0 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -.ENDS col_addr_dff - -.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 64 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff -Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff -Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff -Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff -Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff -Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff -Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff -Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff -Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff -Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff -Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff -Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff -Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff -Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff -Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff -Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff -Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff -Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff -Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff -Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff -Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff -Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff -Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff -Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff -Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff -Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff -Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff -Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff -Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff -Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff -Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff -Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff -Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff -Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff -Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff -Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff -Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff -Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff -Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff -Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff -Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff -Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff -Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff -Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff -Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff -Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff -Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff -Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff -Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff -Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff -Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff -Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff -Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff -Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff -Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff -Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff -Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff -Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff -Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff -Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff -Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff -Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff -.ENDS data_dff - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_2 - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_3 - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_1 - -.SUBCKT pinvbuf A Zb Z vdd gnd -*.PININFO A:B Zb:B Z:B vdd:B gnd:B -* INOUT : A -* INOUT : Zb -* INOUT : Z -* INOUT : vdd -* INOUT : gnd -Xbuf_inv1 A zb_int vdd gnd pinv_1 -Xbuf_inv2 zb_int z_int vdd gnd pinv_2 -Xbuf_inv3 z_int Zb vdd gnd pinv_3 -Xbuf_inv4 zb_int Z vdd gnd pinv_3 -.ENDS pinvbuf - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw -Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw -Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw -Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw -Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw -Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw -Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw -Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw -Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw -Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw -Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw -Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw -Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw -Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw -Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw -Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw -Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw -Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw -Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw -Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw -Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw -Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw -Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw -Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw -Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw -Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw -Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw -Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw -Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw -Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw -Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw -Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw -Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw -Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw -Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw -Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw -Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw -Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw -Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw -Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw -Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw -Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw -Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw -Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw -Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw -Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw -Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw -Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw -Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c15 bl_0_15 br_0_15 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c15 bl_0_15 br_0_15 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c15 bl_0_15 br_0_15 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c15 bl_0_15 br_0_15 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c15 bl_0_15 br_0_15 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c15 bl_0_15 br_0_15 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c15 bl_0_15 br_0_15 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c15 bl_0_15 br_0_15 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c15 bl_0_15 br_0_15 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c15 bl_0_15 br_0_15 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c15 bl_0_15 br_0_15 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c15 bl_0_15 br_0_15 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c15 bl_0_15 br_0_15 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c44 bl_0_44 br_0_44 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c44 bl_0_44 br_0_44 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c44 bl_0_44 br_0_44 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c44 bl_0_44 br_0_44 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c44 bl_0_44 br_0_44 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c44 bl_0_44 br_0_44 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c44 bl_0_44 br_0_44 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c44 bl_0_44 br_0_44 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c44 bl_0_44 br_0_44 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c44 bl_0_44 br_0_44 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c44 bl_0_44 br_0_44 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c44 bl_0_44 br_0_44 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c44 bl_0_44 br_0_44 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c44 bl_0_44 br_0_44 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c44 bl_0_44 br_0_44 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c44 bl_0_44 br_0_44 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c44 bl_0_44 br_0_44 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c44 bl_0_44 br_0_44 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c49 bl_0_49 br_0_49 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c49 bl_0_49 br_0_49 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c49 bl_0_49 br_0_49 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c49 bl_0_49 br_0_49 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c49 bl_0_49 br_0_49 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c49 bl_0_49 br_0_49 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c49 bl_0_49 br_0_49 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c49 bl_0_49 br_0_49 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c49 bl_0_49 br_0_49 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c49 bl_0_49 br_0_49 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c49 bl_0_49 br_0_49 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c49 bl_0_49 br_0_49 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c49 bl_0_49 br_0_49 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c49 bl_0_49 br_0_49 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c49 bl_0_49 br_0_49 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c49 bl_0_49 br_0_49 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c49 bl_0_49 br_0_49 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c49 bl_0_49 br_0_49 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c52 bl_0_52 br_0_52 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c52 bl_0_52 br_0_52 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c52 bl_0_52 br_0_52 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c52 bl_0_52 br_0_52 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c52 bl_0_52 br_0_52 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c52 bl_0_52 br_0_52 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c52 bl_0_52 br_0_52 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c52 bl_0_52 br_0_52 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c52 bl_0_52 br_0_52 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c52 bl_0_52 br_0_52 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c52 bl_0_52 br_0_52 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c53 bl_0_53 br_0_53 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c53 bl_0_53 br_0_53 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c53 bl_0_53 br_0_53 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c53 bl_0_53 br_0_53 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c53 bl_0_53 br_0_53 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c53 bl_0_53 br_0_53 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c53 bl_0_53 br_0_53 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c53 bl_0_53 br_0_53 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c53 bl_0_53 br_0_53 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c53 bl_0_53 br_0_53 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c53 bl_0_53 br_0_53 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c53 bl_0_53 br_0_53 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c53 bl_0_53 br_0_53 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c53 bl_0_53 br_0_53 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c53 bl_0_53 br_0_53 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c53 bl_0_53 br_0_53 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c53 bl_0_53 br_0_53 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c53 bl_0_53 br_0_53 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c53 bl_0_53 br_0_53 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c53 bl_0_53 br_0_53 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c53 bl_0_53 br_0_53 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c53 bl_0_53 br_0_53 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c53 bl_0_53 br_0_53 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c53 bl_0_53 br_0_53 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c53 bl_0_53 br_0_53 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c53 bl_0_53 br_0_53 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c53 bl_0_53 br_0_53 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c53 bl_0_53 br_0_53 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c53 bl_0_53 br_0_53 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c53 bl_0_53 br_0_53 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c53 bl_0_53 br_0_53 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c53 bl_0_53 br_0_53 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c53 bl_0_53 br_0_53 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c53 bl_0_53 br_0_53 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c53 bl_0_53 br_0_53 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c53 bl_0_53 br_0_53 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c53 bl_0_53 br_0_53 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c53 bl_0_53 br_0_53 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c53 bl_0_53 br_0_53 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c53 bl_0_53 br_0_53 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c53 bl_0_53 br_0_53 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c53 bl_0_53 br_0_53 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c53 bl_0_53 br_0_53 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c59 bl_0_59 br_0_59 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c59 bl_0_59 br_0_59 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c59 bl_0_59 br_0_59 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c60 bl_0_60 br_0_60 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c60 bl_0_60 br_0_60 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c60 bl_0_60 br_0_60 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c60 bl_0_60 br_0_60 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c60 bl_0_60 br_0_60 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c60 bl_0_60 br_0_60 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c60 bl_0_60 br_0_60 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c60 bl_0_60 br_0_60 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c60 bl_0_60 br_0_60 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c60 bl_0_60 br_0_60 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c60 bl_0_60 br_0_60 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c60 bl_0_60 br_0_60 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c60 bl_0_60 br_0_60 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c60 bl_0_60 br_0_60 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c60 bl_0_60 br_0_60 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c73 bl_0_73 br_0_73 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c73 bl_0_73 br_0_73 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c73 bl_0_73 br_0_73 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c73 bl_0_73 br_0_73 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c73 bl_0_73 br_0_73 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c73 bl_0_73 br_0_73 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c73 bl_0_73 br_0_73 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c73 bl_0_73 br_0_73 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c73 bl_0_73 br_0_73 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c73 bl_0_73 br_0_73 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c73 bl_0_73 br_0_73 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c73 bl_0_73 br_0_73 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c73 bl_0_73 br_0_73 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c73 bl_0_73 br_0_73 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c73 bl_0_73 br_0_73 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c73 bl_0_73 br_0_73 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c73 bl_0_73 br_0_73 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c73 bl_0_73 br_0_73 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c74 bl_0_74 br_0_74 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c74 bl_0_74 br_0_74 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c74 bl_0_74 br_0_74 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c74 bl_0_74 br_0_74 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c74 bl_0_74 br_0_74 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c74 bl_0_74 br_0_74 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c74 bl_0_74 br_0_74 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c74 bl_0_74 br_0_74 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c74 bl_0_74 br_0_74 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c74 bl_0_74 br_0_74 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c74 bl_0_74 br_0_74 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c74 bl_0_74 br_0_74 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c74 bl_0_74 br_0_74 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c74 bl_0_74 br_0_74 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c74 bl_0_74 br_0_74 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c74 bl_0_74 br_0_74 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c74 bl_0_74 br_0_74 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c74 bl_0_74 br_0_74 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c74 bl_0_74 br_0_74 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c74 bl_0_74 br_0_74 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c74 bl_0_74 br_0_74 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c74 bl_0_74 br_0_74 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c74 bl_0_74 br_0_74 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c74 bl_0_74 br_0_74 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c74 bl_0_74 br_0_74 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c74 bl_0_74 br_0_74 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c74 bl_0_74 br_0_74 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c74 bl_0_74 br_0_74 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c74 bl_0_74 br_0_74 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c74 bl_0_74 br_0_74 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c74 bl_0_74 br_0_74 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c74 bl_0_74 br_0_74 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c74 bl_0_74 br_0_74 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c75 bl_0_75 br_0_75 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c75 bl_0_75 br_0_75 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c75 bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c75 bl_0_75 br_0_75 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c75 bl_0_75 br_0_75 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c75 bl_0_75 br_0_75 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c75 bl_0_75 br_0_75 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c75 bl_0_75 br_0_75 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c75 bl_0_75 br_0_75 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c76 bl_0_76 br_0_76 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c76 bl_0_76 br_0_76 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c76 bl_0_76 br_0_76 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c76 bl_0_76 br_0_76 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c76 bl_0_76 br_0_76 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c76 bl_0_76 br_0_76 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c76 bl_0_76 br_0_76 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c76 bl_0_76 br_0_76 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c76 bl_0_76 br_0_76 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c76 bl_0_76 br_0_76 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c76 bl_0_76 br_0_76 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c76 bl_0_76 br_0_76 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c81 bl_0_81 br_0_81 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c81 bl_0_81 br_0_81 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c81 bl_0_81 br_0_81 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c81 bl_0_81 br_0_81 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c81 bl_0_81 br_0_81 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c81 bl_0_81 br_0_81 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c81 bl_0_81 br_0_81 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c82 bl_0_82 br_0_82 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c82 bl_0_82 br_0_82 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c82 bl_0_82 br_0_82 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c82 bl_0_82 br_0_82 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c82 bl_0_82 br_0_82 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c82 bl_0_82 br_0_82 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c82 bl_0_82 br_0_82 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c82 bl_0_82 br_0_82 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c82 bl_0_82 br_0_82 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c82 bl_0_82 br_0_82 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c82 bl_0_82 br_0_82 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c83 bl_0_83 br_0_83 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c83 bl_0_83 br_0_83 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c84 bl_0_84 br_0_84 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c84 bl_0_84 br_0_84 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c84 bl_0_84 br_0_84 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c84 bl_0_84 br_0_84 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c84 bl_0_84 br_0_84 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c84 bl_0_84 br_0_84 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c84 bl_0_84 br_0_84 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c84 bl_0_84 br_0_84 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c84 bl_0_84 br_0_84 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c84 bl_0_84 br_0_84 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c84 bl_0_84 br_0_84 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c84 bl_0_84 br_0_84 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c84 bl_0_84 br_0_84 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c84 bl_0_84 br_0_84 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c84 bl_0_84 br_0_84 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c84 bl_0_84 br_0_84 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c87 bl_0_87 br_0_87 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c87 bl_0_87 br_0_87 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c87 bl_0_87 br_0_87 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c87 bl_0_87 br_0_87 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c87 bl_0_87 br_0_87 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c87 bl_0_87 br_0_87 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c87 bl_0_87 br_0_87 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c87 bl_0_87 br_0_87 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c88 bl_0_88 br_0_88 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c88 bl_0_88 br_0_88 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c88 bl_0_88 br_0_88 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c88 bl_0_88 br_0_88 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c88 bl_0_88 br_0_88 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c88 bl_0_88 br_0_88 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c88 bl_0_88 br_0_88 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c88 bl_0_88 br_0_88 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c88 bl_0_88 br_0_88 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c88 bl_0_88 br_0_88 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c89 bl_0_89 br_0_89 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c89 bl_0_89 br_0_89 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c89 bl_0_89 br_0_89 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c90 bl_0_90 br_0_90 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c90 bl_0_90 br_0_90 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c90 bl_0_90 br_0_90 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c90 bl_0_90 br_0_90 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c90 bl_0_90 br_0_90 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c90 bl_0_90 br_0_90 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c90 bl_0_90 br_0_90 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c90 bl_0_90 br_0_90 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c90 bl_0_90 br_0_90 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c90 bl_0_90 br_0_90 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c90 bl_0_90 br_0_90 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c90 bl_0_90 br_0_90 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c90 bl_0_90 br_0_90 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c90 bl_0_90 br_0_90 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c90 bl_0_90 br_0_90 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c96 bl_0_96 br_0_96 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c96 bl_0_96 br_0_96 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c96 bl_0_96 br_0_96 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c96 bl_0_96 br_0_96 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c96 bl_0_96 br_0_96 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c96 bl_0_96 br_0_96 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c96 bl_0_96 br_0_96 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c96 bl_0_96 br_0_96 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c96 bl_0_96 br_0_96 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c96 bl_0_96 br_0_96 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c96 bl_0_96 br_0_96 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c96 bl_0_96 br_0_96 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c96 bl_0_96 br_0_96 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c96 bl_0_96 br_0_96 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c96 bl_0_96 br_0_96 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c96 bl_0_96 br_0_96 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c96 bl_0_96 br_0_96 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c96 bl_0_96 br_0_96 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c96 bl_0_96 br_0_96 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c97 bl_0_97 br_0_97 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c97 bl_0_97 br_0_97 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c97 bl_0_97 br_0_97 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c97 bl_0_97 br_0_97 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c97 bl_0_97 br_0_97 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c97 bl_0_97 br_0_97 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c97 bl_0_97 br_0_97 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c97 bl_0_97 br_0_97 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c97 bl_0_97 br_0_97 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c97 bl_0_97 br_0_97 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c97 bl_0_97 br_0_97 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c97 bl_0_97 br_0_97 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c97 bl_0_97 br_0_97 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c97 bl_0_97 br_0_97 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c97 bl_0_97 br_0_97 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c97 bl_0_97 br_0_97 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c97 bl_0_97 br_0_97 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c98 bl_0_98 br_0_98 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c98 bl_0_98 br_0_98 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c98 bl_0_98 br_0_98 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c98 bl_0_98 br_0_98 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c98 bl_0_98 br_0_98 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c98 bl_0_98 br_0_98 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c98 bl_0_98 br_0_98 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c98 bl_0_98 br_0_98 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c98 bl_0_98 br_0_98 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c98 bl_0_98 br_0_98 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c98 bl_0_98 br_0_98 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c98 bl_0_98 br_0_98 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c98 bl_0_98 br_0_98 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c98 bl_0_98 br_0_98 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c99 bl_0_99 br_0_99 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c99 bl_0_99 br_0_99 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c99 bl_0_99 br_0_99 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c99 bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c100 bl_0_100 br_0_100 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c100 bl_0_100 br_0_100 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c100 bl_0_100 br_0_100 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c100 bl_0_100 br_0_100 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c100 bl_0_100 br_0_100 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c100 bl_0_100 br_0_100 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c100 bl_0_100 br_0_100 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c100 bl_0_100 br_0_100 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c100 bl_0_100 br_0_100 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c100 bl_0_100 br_0_100 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c100 bl_0_100 br_0_100 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c100 bl_0_100 br_0_100 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c100 bl_0_100 br_0_100 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c100 bl_0_100 br_0_100 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c100 bl_0_100 br_0_100 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c100 bl_0_100 br_0_100 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c100 bl_0_100 br_0_100 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c108 bl_0_108 br_0_108 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c108 bl_0_108 br_0_108 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c108 bl_0_108 br_0_108 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c108 bl_0_108 br_0_108 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c108 bl_0_108 br_0_108 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c108 bl_0_108 br_0_108 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c108 bl_0_108 br_0_108 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c108 bl_0_108 br_0_108 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c108 bl_0_108 br_0_108 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c108 bl_0_108 br_0_108 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c108 bl_0_108 br_0_108 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c108 bl_0_108 br_0_108 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c108 bl_0_108 br_0_108 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c108 bl_0_108 br_0_108 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c108 bl_0_108 br_0_108 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c108 bl_0_108 br_0_108 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c108 bl_0_108 br_0_108 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c108 bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c110 bl_0_110 br_0_110 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c110 bl_0_110 br_0_110 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c110 bl_0_110 br_0_110 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c110 bl_0_110 br_0_110 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c110 bl_0_110 br_0_110 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c110 bl_0_110 br_0_110 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c110 bl_0_110 br_0_110 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c110 bl_0_110 br_0_110 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c110 bl_0_110 br_0_110 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c110 bl_0_110 br_0_110 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c110 bl_0_110 br_0_110 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c110 bl_0_110 br_0_110 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c110 bl_0_110 br_0_110 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c110 bl_0_110 br_0_110 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c110 bl_0_110 br_0_110 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c110 bl_0_110 br_0_110 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c110 bl_0_110 br_0_110 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c110 bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c111 bl_0_111 br_0_111 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c111 bl_0_111 br_0_111 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c111 bl_0_111 br_0_111 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c111 bl_0_111 br_0_111 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c111 bl_0_111 br_0_111 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c111 bl_0_111 br_0_111 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c111 bl_0_111 br_0_111 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c111 bl_0_111 br_0_111 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c111 bl_0_111 br_0_111 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c111 bl_0_111 br_0_111 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c111 bl_0_111 br_0_111 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c111 bl_0_111 br_0_111 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c111 bl_0_111 br_0_111 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c111 bl_0_111 br_0_111 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c111 bl_0_111 br_0_111 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c111 bl_0_111 br_0_111 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c111 bl_0_111 br_0_111 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c111 bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c112 bl_0_112 br_0_112 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c112 bl_0_112 br_0_112 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c112 bl_0_112 br_0_112 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c112 bl_0_112 br_0_112 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c112 bl_0_112 br_0_112 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c112 bl_0_112 br_0_112 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c112 bl_0_112 br_0_112 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c112 bl_0_112 br_0_112 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c112 bl_0_112 br_0_112 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c112 bl_0_112 br_0_112 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c112 bl_0_112 br_0_112 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c112 bl_0_112 br_0_112 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c112 bl_0_112 br_0_112 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c112 bl_0_112 br_0_112 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c112 bl_0_112 br_0_112 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c112 bl_0_112 br_0_112 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c112 bl_0_112 br_0_112 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c112 bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c114 bl_0_114 br_0_114 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c114 bl_0_114 br_0_114 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c114 bl_0_114 br_0_114 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c114 bl_0_114 br_0_114 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c114 bl_0_114 br_0_114 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c114 bl_0_114 br_0_114 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c114 bl_0_114 br_0_114 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c114 bl_0_114 br_0_114 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c114 bl_0_114 br_0_114 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c114 bl_0_114 br_0_114 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c114 bl_0_114 br_0_114 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c114 bl_0_114 br_0_114 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c114 bl_0_114 br_0_114 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c114 bl_0_114 br_0_114 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c114 bl_0_114 br_0_114 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c115 bl_0_115 br_0_115 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c115 bl_0_115 br_0_115 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c116 bl_0_116 br_0_116 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c116 bl_0_116 br_0_116 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c116 bl_0_116 br_0_116 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c116 bl_0_116 br_0_116 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c116 bl_0_116 br_0_116 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c116 bl_0_116 br_0_116 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c116 bl_0_116 br_0_116 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c116 bl_0_116 br_0_116 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c116 bl_0_116 br_0_116 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c116 bl_0_116 br_0_116 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c116 bl_0_116 br_0_116 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c116 bl_0_116 br_0_116 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c116 bl_0_116 br_0_116 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c116 bl_0_116 br_0_116 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c116 bl_0_116 br_0_116 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c116 bl_0_116 br_0_116 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c116 bl_0_116 br_0_116 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c116 bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c119 bl_0_119 br_0_119 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c119 bl_0_119 br_0_119 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c119 bl_0_119 br_0_119 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c119 bl_0_119 br_0_119 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c119 bl_0_119 br_0_119 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c119 bl_0_119 br_0_119 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c119 bl_0_119 br_0_119 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c119 bl_0_119 br_0_119 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c119 bl_0_119 br_0_119 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c119 bl_0_119 br_0_119 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c119 bl_0_119 br_0_119 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c119 bl_0_119 br_0_119 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c119 bl_0_119 br_0_119 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c119 bl_0_119 br_0_119 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c119 bl_0_119 br_0_119 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c119 bl_0_119 br_0_119 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c119 bl_0_119 br_0_119 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c119 bl_0_119 br_0_119 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c119 bl_0_119 br_0_119 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c119 bl_0_119 br_0_119 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c119 bl_0_119 br_0_119 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c119 bl_0_119 br_0_119 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c119 bl_0_119 br_0_119 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c119 bl_0_119 br_0_119 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c119 bl_0_119 br_0_119 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c119 bl_0_119 br_0_119 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c119 bl_0_119 br_0_119 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c119 bl_0_119 br_0_119 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c119 bl_0_119 br_0_119 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c119 bl_0_119 br_0_119 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c119 bl_0_119 br_0_119 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c119 bl_0_119 br_0_119 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c119 bl_0_119 br_0_119 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c119 bl_0_119 br_0_119 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c119 bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c120 bl_0_120 br_0_120 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c120 bl_0_120 br_0_120 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c120 bl_0_120 br_0_120 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c120 bl_0_120 br_0_120 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c120 bl_0_120 br_0_120 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c120 bl_0_120 br_0_120 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c120 bl_0_120 br_0_120 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c120 bl_0_120 br_0_120 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c120 bl_0_120 br_0_120 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c120 bl_0_120 br_0_120 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c120 bl_0_120 br_0_120 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c120 bl_0_120 br_0_120 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c120 bl_0_120 br_0_120 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c120 bl_0_120 br_0_120 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c120 bl_0_120 br_0_120 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c120 bl_0_120 br_0_120 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c120 bl_0_120 br_0_120 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c120 bl_0_120 br_0_120 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c120 bl_0_120 br_0_120 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c120 bl_0_120 br_0_120 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c120 bl_0_120 br_0_120 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c120 bl_0_120 br_0_120 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c120 bl_0_120 br_0_120 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c120 bl_0_120 br_0_120 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c120 bl_0_120 br_0_120 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c120 bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c121 bl_0_121 br_0_121 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c121 bl_0_121 br_0_121 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c121 bl_0_121 br_0_121 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c121 bl_0_121 br_0_121 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c121 bl_0_121 br_0_121 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c121 bl_0_121 br_0_121 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c121 bl_0_121 br_0_121 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c121 bl_0_121 br_0_121 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c121 bl_0_121 br_0_121 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c121 bl_0_121 br_0_121 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c121 bl_0_121 br_0_121 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c121 bl_0_121 br_0_121 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c121 bl_0_121 br_0_121 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c121 bl_0_121 br_0_121 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c121 bl_0_121 br_0_121 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c121 bl_0_121 br_0_121 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c121 bl_0_121 br_0_121 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c121 bl_0_121 br_0_121 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c121 bl_0_121 br_0_121 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c121 bl_0_121 br_0_121 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c121 bl_0_121 br_0_121 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c121 bl_0_121 br_0_121 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c121 bl_0_121 br_0_121 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c121 bl_0_121 br_0_121 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c121 bl_0_121 br_0_121 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c121 bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c122 bl_0_122 br_0_122 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c122 bl_0_122 br_0_122 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c122 bl_0_122 br_0_122 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c122 bl_0_122 br_0_122 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c122 bl_0_122 br_0_122 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c122 bl_0_122 br_0_122 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c122 bl_0_122 br_0_122 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c122 bl_0_122 br_0_122 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c122 bl_0_122 br_0_122 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c122 bl_0_122 br_0_122 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c122 bl_0_122 br_0_122 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c122 bl_0_122 br_0_122 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c122 bl_0_122 br_0_122 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c122 bl_0_122 br_0_122 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c122 bl_0_122 br_0_122 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c122 bl_0_122 br_0_122 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c122 bl_0_122 br_0_122 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c122 bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c123 bl_0_123 br_0_123 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c123 bl_0_123 br_0_123 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c123 bl_0_123 br_0_123 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c123 bl_0_123 br_0_123 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c123 bl_0_123 br_0_123 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c123 bl_0_123 br_0_123 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c123 bl_0_123 br_0_123 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c123 bl_0_123 br_0_123 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c123 bl_0_123 br_0_123 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c123 bl_0_123 br_0_123 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c123 bl_0_123 br_0_123 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c123 bl_0_123 br_0_123 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c123 bl_0_123 br_0_123 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c123 bl_0_123 br_0_123 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c123 bl_0_123 br_0_123 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c123 bl_0_123 br_0_123 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c123 bl_0_123 br_0_123 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c123 bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c126 bl_0_126 br_0_126 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c126 bl_0_126 br_0_126 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c126 bl_0_126 br_0_126 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c126 bl_0_126 br_0_126 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c126 bl_0_126 br_0_126 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c126 bl_0_126 br_0_126 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c126 bl_0_126 br_0_126 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c126 bl_0_126 br_0_126 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c126 bl_0_126 br_0_126 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c126 bl_0_126 br_0_126 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c126 bl_0_126 br_0_126 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c126 bl_0_126 br_0_126 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c126 bl_0_126 br_0_126 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c126 bl_0_126 br_0_126 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c126 bl_0_126 br_0_126 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c126 bl_0_126 br_0_126 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c126 bl_0_126 br_0_126 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c126 bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c127 bl_0_127 br_0_127 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c127 bl_0_127 br_0_127 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c127 bl_0_127 br_0_127 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c127 bl_0_127 br_0_127 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c127 bl_0_127 br_0_127 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c127 bl_0_127 br_0_127 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c127 bl_0_127 br_0_127 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c127 bl_0_127 br_0_127 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c127 bl_0_127 br_0_127 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c127 bl_0_127 br_0_127 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c127 bl_0_127 br_0_127 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c127 bl_0_127 br_0_127 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c127 bl_0_127 br_0_127 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c127 bl_0_127 br_0_127 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c127 bl_0_127 br_0_127 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c127 bl_0_127 br_0_127 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c127 bl_0_127 br_0_127 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c127 bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw -.ENDS bitcell_array - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 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bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* OUTPUT: data_2 -* INPUT : bl_2 -* INPUT : br_2 -* OUTPUT: data_3 -* INPUT : bl_3 -* INPUT : br_3 -* OUTPUT: data_4 -* INPUT : bl_4 -* INPUT : br_4 -* OUTPUT: data_5 -* INPUT : bl_5 -* INPUT : br_5 -* OUTPUT: data_6 -* INPUT : bl_6 -* INPUT : br_6 -* OUTPUT: data_7 -* INPUT : bl_7 -* INPUT : br_7 -* OUTPUT: data_8 -* INPUT : bl_8 -* INPUT : br_8 -* OUTPUT: data_9 -* INPUT : bl_9 -* INPUT : br_9 -* OUTPUT: data_10 -* INPUT : bl_10 -* INPUT : br_10 -* OUTPUT: data_11 -* INPUT : bl_11 -* INPUT : br_11 -* OUTPUT: data_12 -* INPUT : bl_12 -* INPUT : br_12 -* OUTPUT: data_13 -* INPUT : bl_13 -* INPUT : br_13 -* OUTPUT: data_14 -* INPUT : bl_14 -* INPUT : br_14 -* OUTPUT: data_15 -* INPUT : bl_15 -* INPUT : br_15 -* OUTPUT: data_16 -* INPUT : bl_16 -* INPUT : br_16 -* OUTPUT: data_17 -* INPUT : bl_17 -* INPUT : br_17 -* OUTPUT: data_18 -* INPUT : bl_18 -* INPUT : br_18 -* OUTPUT: data_19 -* INPUT : bl_19 -* INPUT : br_19 -* OUTPUT: data_20 -* INPUT : bl_20 -* INPUT : br_20 -* OUTPUT: data_21 -* INPUT : bl_21 -* INPUT : br_21 -* OUTPUT: data_22 -* INPUT : bl_22 -* INPUT : br_22 -* OUTPUT: data_23 -* INPUT : bl_23 -* INPUT : br_23 -* OUTPUT: data_24 -* INPUT : bl_24 -* INPUT : br_24 -* OUTPUT: data_25 -* INPUT : bl_25 -* INPUT : br_25 -* OUTPUT: data_26 -* INPUT : bl_26 -* INPUT : br_26 -* OUTPUT: data_27 -* INPUT : bl_27 -* INPUT : br_27 -* OUTPUT: data_28 -* INPUT : bl_28 -* INPUT : br_28 -* OUTPUT: data_29 -* INPUT : bl_29 -* INPUT : br_29 -* OUTPUT: data_30 -* INPUT : bl_30 -* INPUT : br_30 -* OUTPUT: data_31 -* INPUT : bl_31 -* INPUT : br_31 -* OUTPUT: data_32 -* INPUT : bl_32 -* INPUT : br_32 -* OUTPUT: data_33 -* INPUT : bl_33 -* INPUT : br_33 -* OUTPUT: data_34 -* INPUT : bl_34 -* INPUT : br_34 -* OUTPUT: data_35 -* INPUT : bl_35 -* INPUT : br_35 -* OUTPUT: data_36 -* INPUT : bl_36 -* INPUT : br_36 -* OUTPUT: data_37 -* INPUT : bl_37 -* INPUT : br_37 -* OUTPUT: data_38 -* INPUT : bl_38 -* INPUT : br_38 -* OUTPUT: data_39 -* INPUT : bl_39 -* INPUT : br_39 -* OUTPUT: data_40 -* INPUT : bl_40 -* INPUT : br_40 -* OUTPUT: data_41 -* INPUT : bl_41 -* INPUT : br_41 -* OUTPUT: data_42 -* INPUT : bl_42 -* INPUT : br_42 -* OUTPUT: data_43 -* INPUT : bl_43 -* INPUT : br_43 -* OUTPUT: data_44 -* INPUT : bl_44 -* INPUT : br_44 -* OUTPUT: data_45 -* INPUT : bl_45 -* INPUT : br_45 -* OUTPUT: data_46 -* INPUT : bl_46 -* INPUT : br_46 -* OUTPUT: data_47 -* INPUT : bl_47 -* INPUT : br_47 -* OUTPUT: data_48 -* INPUT : bl_48 -* INPUT : br_48 -* OUTPUT: data_49 -* INPUT : bl_49 -* INPUT : br_49 -* OUTPUT: data_50 -* INPUT : bl_50 -* INPUT : br_50 -* OUTPUT: data_51 -* INPUT : bl_51 -* INPUT : br_51 -* OUTPUT: data_52 -* INPUT : bl_52 -* INPUT : br_52 -* OUTPUT: data_53 -* INPUT : bl_53 -* INPUT : br_53 -* OUTPUT: data_54 -* INPUT : bl_54 -* INPUT : br_54 -* OUTPUT: data_55 -* INPUT : bl_55 -* INPUT : br_55 -* OUTPUT: data_56 -* INPUT : bl_56 -* INPUT : br_56 -* OUTPUT: data_57 -* INPUT : bl_57 -* INPUT : br_57 -* OUTPUT: data_58 -* INPUT : bl_58 -* INPUT : br_58 -* OUTPUT: data_59 -* INPUT : bl_59 -* INPUT : br_59 -* OUTPUT: data_60 -* INPUT : bl_60 -* INPUT : br_60 -* OUTPUT: data_61 -* INPUT : bl_61 -* INPUT : br_61 -* OUTPUT: data_62 -* INPUT : bl_62 -* INPUT : br_62 -* OUTPUT: data_63 -* INPUT : bl_63 -* INPUT : br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 2 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp -Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp -Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp -Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp -Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp -Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp -Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp -Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp -Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp -Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp -Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp -Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp -Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp -Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp -Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp -Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp -Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp -Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp -Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp -Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp -Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp -Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp -Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp -Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp -Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp -Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp -Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp -Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp -Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp -Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp -Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp -Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp -Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp -Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp -Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp -Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp -Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp -Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp -Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp -Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp -Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp -Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp -Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp -Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp -Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp -Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp -Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp -Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp -Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp -Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp -Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp -Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp -Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp -Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp -Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp -Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp -Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp -Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp -Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp -Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp -Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp -Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp -.ENDS sense_amp_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* OUTPUT: bl_64 -* OUTPUT: br_64 -* OUTPUT: bl_65 -* OUTPUT: br_65 -* OUTPUT: bl_66 -* OUTPUT: br_66 -* OUTPUT: bl_67 -* OUTPUT: br_67 -* OUTPUT: bl_68 -* OUTPUT: br_68 -* OUTPUT: bl_69 -* OUTPUT: br_69 -* OUTPUT: bl_70 -* OUTPUT: br_70 -* OUTPUT: bl_71 -* OUTPUT: br_71 -* OUTPUT: bl_72 -* OUTPUT: br_72 -* OUTPUT: bl_73 -* OUTPUT: br_73 -* OUTPUT: bl_74 -* OUTPUT: br_74 -* OUTPUT: bl_75 -* OUTPUT: br_75 -* OUTPUT: bl_76 -* OUTPUT: br_76 -* OUTPUT: bl_77 -* OUTPUT: br_77 -* OUTPUT: bl_78 -* OUTPUT: br_78 -* OUTPUT: bl_79 -* OUTPUT: br_79 -* OUTPUT: bl_80 -* OUTPUT: br_80 -* OUTPUT: bl_81 -* OUTPUT: br_81 -* OUTPUT: bl_82 -* OUTPUT: br_82 -* OUTPUT: bl_83 -* OUTPUT: br_83 -* OUTPUT: bl_84 -* OUTPUT: br_84 -* OUTPUT: bl_85 -* OUTPUT: br_85 -* OUTPUT: bl_86 -* OUTPUT: br_86 -* OUTPUT: bl_87 -* OUTPUT: br_87 -* OUTPUT: bl_88 -* OUTPUT: br_88 -* OUTPUT: bl_89 -* OUTPUT: br_89 -* OUTPUT: bl_90 -* OUTPUT: br_90 -* OUTPUT: bl_91 -* OUTPUT: br_91 -* OUTPUT: bl_92 -* OUTPUT: br_92 -* OUTPUT: bl_93 -* OUTPUT: br_93 -* OUTPUT: bl_94 -* OUTPUT: br_94 -* OUTPUT: bl_95 -* OUTPUT: br_95 -* OUTPUT: bl_96 -* OUTPUT: br_96 -* OUTPUT: bl_97 -* OUTPUT: br_97 -* OUTPUT: bl_98 -* OUTPUT: br_98 -* OUTPUT: bl_99 -* OUTPUT: br_99 -* OUTPUT: bl_100 -* OUTPUT: br_100 -* OUTPUT: bl_101 -* OUTPUT: br_101 -* OUTPUT: bl_102 -* OUTPUT: br_102 -* OUTPUT: bl_103 -* OUTPUT: br_103 -* OUTPUT: bl_104 -* OUTPUT: br_104 -* OUTPUT: bl_105 -* OUTPUT: br_105 -* OUTPUT: bl_106 -* OUTPUT: br_106 -* OUTPUT: bl_107 -* OUTPUT: br_107 -* OUTPUT: bl_108 -* OUTPUT: br_108 -* OUTPUT: bl_109 -* OUTPUT: br_109 -* OUTPUT: bl_110 -* OUTPUT: br_110 -* OUTPUT: bl_111 -* OUTPUT: br_111 -* OUTPUT: bl_112 -* OUTPUT: br_112 -* OUTPUT: bl_113 -* OUTPUT: br_113 -* OUTPUT: bl_114 -* OUTPUT: br_114 -* OUTPUT: bl_115 -* OUTPUT: br_115 -* OUTPUT: bl_116 -* OUTPUT: br_116 -* OUTPUT: bl_117 -* OUTPUT: br_117 -* OUTPUT: bl_118 -* OUTPUT: br_118 -* OUTPUT: bl_119 -* OUTPUT: br_119 -* OUTPUT: bl_120 -* OUTPUT: br_120 -* OUTPUT: bl_121 -* OUTPUT: br_121 -* OUTPUT: bl_122 -* OUTPUT: br_122 -* OUTPUT: bl_123 -* OUTPUT: br_123 -* OUTPUT: bl_124 -* OUTPUT: br_124 -* OUTPUT: bl_125 -* OUTPUT: br_125 -* OUTPUT: bl_126 -* OUTPUT: br_126 -* OUTPUT: bl_127 -* OUTPUT: br_127 -* OUTPUT: bl_128 -* OUTPUT: br_128 -* INPUT : en_bar -* POWER : vdd -* cols: 129 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 -Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 -Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 -Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 -Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 -Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 -Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 -Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 -Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 -Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 -Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 -Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 -Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 -Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 -Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 -Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 -Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 -Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 -Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 -Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 -Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 -Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 -Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 -Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 -Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 -Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 -Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 -Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 -Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 -Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 -Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 -Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 -Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 -Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 -Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 -Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 -Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 -Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 -Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 -Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 -Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 -Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 -Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 -Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 -Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 -Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 -Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 -Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 -Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 -Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 -Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 -Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 -Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 -Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 -Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 -Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 -Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 -Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 -Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 -Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 -Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 -Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 -Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 -Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 -Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 -Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 -Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 -Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 -Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 -Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 -Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 -Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 -Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 -Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 -Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 -Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 -Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 -Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 -Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 -Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 -Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 -Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 -Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 -Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 -Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 -Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 -Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 -Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 -Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 -Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 -Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 -Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 -Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 -Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 -Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 -Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 -Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 -Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 -Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 -Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 -Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 -Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 -Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 -Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 -Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 -Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 -Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 -Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 -Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 -Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 -Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 -Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 -Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 -Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 -Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 -Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 -Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 -Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 -Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 -Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 -Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 -Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 -Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 -Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 -Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 -Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd -*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* INPUT : data_2 -* INPUT : data_3 -* INPUT : data_4 -* INPUT : data_5 -* INPUT : data_6 -* INPUT : data_7 -* INPUT : data_8 -* INPUT : data_9 -* INPUT : data_10 -* INPUT : data_11 -* INPUT : data_12 -* INPUT : data_13 -* INPUT : data_14 -* INPUT : data_15 -* INPUT : data_16 -* INPUT : data_17 -* INPUT : data_18 -* INPUT : data_19 -* INPUT : data_20 -* INPUT : data_21 -* INPUT : data_22 -* INPUT : data_23 -* INPUT : data_24 -* INPUT : data_25 -* INPUT : data_26 -* INPUT : data_27 -* INPUT : data_28 -* INPUT : data_29 -* INPUT : data_30 -* INPUT : data_31 -* INPUT : data_32 -* INPUT : data_33 -* INPUT : data_34 -* INPUT : data_35 -* INPUT : data_36 -* INPUT : data_37 -* INPUT : data_38 -* INPUT : data_39 -* INPUT : data_40 -* INPUT : data_41 -* INPUT : data_42 -* INPUT : data_43 -* INPUT : data_44 -* INPUT : data_45 -* INPUT : data_46 -* INPUT : data_47 -* INPUT : data_48 -* INPUT : data_49 -* INPUT : data_50 -* INPUT : data_51 -* INPUT : data_52 -* INPUT : data_53 -* INPUT : data_54 -* INPUT : data_55 -* INPUT : data_56 -* INPUT : data_57 -* INPUT : data_58 -* INPUT : data_59 -* INPUT : data_60 -* INPUT : data_61 -* INPUT : data_62 -* INPUT : data_63 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 64 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver -Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver -Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver -Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver -Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver -Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver -Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver -Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver -Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver -Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver -Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver -Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver -Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver -Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver -Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver -Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver -Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver -Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver -Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver -Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver -Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver -Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver -Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver -Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver -Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver -Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver -Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver -Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver -Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver -Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver -Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver -Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver -Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver -Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver -Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver -Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver -Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver -Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver -Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver -Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver -Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver -Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver -Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver -Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver -Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver -Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver -Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver -Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver -Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver -Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver -Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver -Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver -Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver -Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver -Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver -Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver -Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver -Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver -Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver -Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver -Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver -Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver -Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver -.ENDS write_driver_array - -* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -.SUBCKT column_mux bl br bl_out br_out sel gnd -*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B -* INOUT : bl -* INOUT : br -* INOUT : bl_out -* INOUT : br_out -* INOUT : sel -* INOUT : gnd -Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -.ENDS column_mux - -.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd -*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* INOUT : sel_0 -* INOUT : sel_1 -* INOUT : bl_out_0 -* INOUT : br_out_0 -* INOUT : bl_out_1 -* INOUT : br_out_1 -* INOUT : bl_out_2 -* INOUT : br_out_2 -* INOUT : bl_out_3 -* INOUT : br_out_3 -* INOUT : bl_out_4 -* INOUT : br_out_4 -* INOUT : bl_out_5 -* INOUT : br_out_5 -* INOUT : bl_out_6 -* INOUT : br_out_6 -* INOUT : bl_out_7 -* INOUT : br_out_7 -* INOUT : bl_out_8 -* INOUT : br_out_8 -* INOUT : bl_out_9 -* INOUT : br_out_9 -* INOUT : bl_out_10 -* INOUT : br_out_10 -* INOUT : bl_out_11 -* INOUT : br_out_11 -* INOUT : bl_out_12 -* INOUT : br_out_12 -* INOUT : bl_out_13 -* INOUT : br_out_13 -* INOUT : bl_out_14 -* INOUT : br_out_14 -* INOUT : bl_out_15 -* INOUT : br_out_15 -* INOUT : bl_out_16 -* INOUT : br_out_16 -* INOUT : bl_out_17 -* INOUT : br_out_17 -* INOUT : bl_out_18 -* INOUT : br_out_18 -* INOUT : bl_out_19 -* INOUT : br_out_19 -* INOUT : bl_out_20 -* INOUT : br_out_20 -* INOUT : bl_out_21 -* INOUT : br_out_21 -* INOUT : bl_out_22 -* INOUT : br_out_22 -* INOUT : bl_out_23 -* INOUT : br_out_23 -* INOUT : bl_out_24 -* INOUT : br_out_24 -* INOUT : bl_out_25 -* INOUT : br_out_25 -* INOUT : bl_out_26 -* INOUT : br_out_26 -* INOUT : bl_out_27 -* INOUT : br_out_27 -* INOUT : bl_out_28 -* INOUT : br_out_28 -* INOUT : bl_out_29 -* INOUT : br_out_29 -* INOUT : bl_out_30 -* INOUT : br_out_30 -* INOUT : bl_out_31 -* INOUT : br_out_31 -* INOUT : bl_out_32 -* INOUT : br_out_32 -* INOUT : bl_out_33 -* INOUT : br_out_33 -* INOUT : bl_out_34 -* INOUT : br_out_34 -* INOUT : bl_out_35 -* INOUT : br_out_35 -* INOUT : bl_out_36 -* INOUT : br_out_36 -* INOUT : bl_out_37 -* INOUT : br_out_37 -* INOUT : bl_out_38 -* INOUT : br_out_38 -* INOUT : bl_out_39 -* INOUT : br_out_39 -* INOUT : bl_out_40 -* INOUT : br_out_40 -* INOUT : bl_out_41 -* INOUT : br_out_41 -* INOUT : bl_out_42 -* INOUT : br_out_42 -* INOUT : bl_out_43 -* INOUT : br_out_43 -* INOUT : bl_out_44 -* INOUT : br_out_44 -* INOUT : bl_out_45 -* INOUT : br_out_45 -* INOUT : bl_out_46 -* INOUT : br_out_46 -* INOUT : bl_out_47 -* INOUT : br_out_47 -* INOUT : bl_out_48 -* INOUT : br_out_48 -* INOUT : bl_out_49 -* INOUT : br_out_49 -* INOUT : bl_out_50 -* INOUT : br_out_50 -* INOUT : bl_out_51 -* INOUT : br_out_51 -* INOUT : bl_out_52 -* INOUT : br_out_52 -* INOUT : bl_out_53 -* INOUT : br_out_53 -* INOUT : bl_out_54 -* INOUT : br_out_54 -* INOUT : bl_out_55 -* INOUT : br_out_55 -* INOUT : bl_out_56 -* INOUT : br_out_56 -* INOUT : bl_out_57 -* INOUT : br_out_57 -* INOUT : bl_out_58 -* INOUT : br_out_58 -* INOUT : bl_out_59 -* INOUT : br_out_59 -* INOUT : bl_out_60 -* INOUT : br_out_60 -* INOUT : bl_out_61 -* INOUT : br_out_61 -* INOUT : bl_out_62 -* INOUT : br_out_62 -* INOUT : bl_out_63 -* INOUT : br_out_63 -* INOUT : gnd -* cols: 128 word_size: 64 bl: bl br: br -XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux -XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux -XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux -XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux -XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux -XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux -XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux -XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux -XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux -XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux -XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux -XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux -XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux -XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux -XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux -XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux -XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux -XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux -XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux -XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux -XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux -XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux -XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux -XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux -XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux -XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux -XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux -XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux -XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux -XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux -XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux -XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux -XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux -XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux -XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux -XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux -XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux -XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux -XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux -XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux -XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux -XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux -XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux -XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux -XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux -XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux -XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux -XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux -XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux -XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux -XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux -XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux -XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux -XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux -XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux -XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux -XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux -XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux -XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux -XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux -XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux -XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux -XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux -XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux -XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux -XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux -XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux -XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux -XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux -XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux -XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux -XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux -XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux -XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux -XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux -XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux -XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux -XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux -XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux -XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux -XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux -XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux -XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux -XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux -XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux -XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux -XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux -XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux -XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux -XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux -XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux -XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux -XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux -XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux -XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux -XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux -XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux -XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux -XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux -XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux -XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux -XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux -XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux -XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux -XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux -XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux -XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux -XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux -XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux -XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux -XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux -XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux -XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux -XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux -XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux -XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux -XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux -XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux -XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux -XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux -XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux -XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux -XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux -XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux -XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux -XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux -XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux -XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux -.ENDS column_mux_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* INPUT : sel_0 -* INPUT : sel_1 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array -Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2 - -* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p -.ENDS pinv_0 - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 32 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv_0 -.ENDS and2_dec_0 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv_0 -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* INPUT : in_16 -* INPUT : in_17 -* INPUT : in_18 -* INPUT : in_19 -* INPUT : in_20 -* INPUT : in_21 -* INPUT : in_22 -* INPUT : in_23 -* INPUT : in_24 -* INPUT : in_25 -* INPUT : in_26 -* INPUT : in_27 -* INPUT : in_28 -* INPUT : in_29 -* INPUT : in_30 -* INPUT : in_31 -* INPUT : in_32 -* INPUT : in_33 -* INPUT : in_34 -* INPUT : in_35 -* INPUT : in_36 -* INPUT : in_37 -* INPUT : in_38 -* INPUT : in_39 -* INPUT : in_40 -* INPUT : in_41 -* INPUT : in_42 -* INPUT : in_43 -* INPUT : in_44 -* INPUT : in_45 -* INPUT : in_46 -* INPUT : in_47 -* INPUT : in_48 -* INPUT : in_49 -* INPUT : in_50 -* INPUT : in_51 -* INPUT : in_52 -* INPUT : in_53 -* INPUT : in_54 -* INPUT : in_55 -* INPUT : in_56 -* INPUT : in_57 -* INPUT : in_58 -* INPUT : in_59 -* INPUT : in_60 -* INPUT : in_61 -* INPUT : in_62 -* INPUT : in_63 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver -Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver -Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver -Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver -Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver -Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver -Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver -Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver -Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver -Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver -Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver -Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver -Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver -Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver -Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver -Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver -Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver -Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver -Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver -Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver -Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver -Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver -Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver -Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver -Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver -Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver -Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver -Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver -Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver -Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver -Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver -Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver -Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver -Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver -Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver -Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver -Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver -Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver -Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver -Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver -Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver -Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver -Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver -Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver -Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver -Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver -Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver -Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver -.ENDS wordline_driver_array - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3 - -.SUBCKT and3_dec A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand3_dec_nand A B C zb_int vdd gnd pnand3 -Xpand3_dec_inv zb_int Z vdd gnd pinv -.ENDS and3_dec - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* OUTPUT: decode_16 -* OUTPUT: decode_17 -* OUTPUT: decode_18 -* OUTPUT: decode_19 -* OUTPUT: decode_20 -* OUTPUT: decode_21 -* OUTPUT: decode_22 -* OUTPUT: decode_23 -* OUTPUT: decode_24 -* OUTPUT: decode_25 -* OUTPUT: decode_26 -* OUTPUT: decode_27 -* OUTPUT: decode_28 -* OUTPUT: decode_29 -* OUTPUT: decode_30 -* OUTPUT: decode_31 -* OUTPUT: decode_32 -* OUTPUT: decode_33 -* OUTPUT: decode_34 -* OUTPUT: decode_35 -* OUTPUT: decode_36 -* OUTPUT: decode_37 -* OUTPUT: decode_38 -* OUTPUT: decode_39 -* OUTPUT: decode_40 -* OUTPUT: decode_41 -* OUTPUT: decode_42 -* OUTPUT: decode_43 -* OUTPUT: decode_44 -* OUTPUT: decode_45 -* OUTPUT: decode_46 -* OUTPUT: decode_47 -* OUTPUT: decode_48 -* OUTPUT: decode_49 -* OUTPUT: decode_50 -* OUTPUT: decode_51 -* OUTPUT: decode_52 -* OUTPUT: decode_53 -* OUTPUT: decode_54 -* OUTPUT: decode_55 -* OUTPUT: decode_56 -* OUTPUT: decode_57 -* OUTPUT: decode_58 -* OUTPUT: decode_59 -* OUTPUT: decode_60 -* OUTPUT: decode_61 -* OUTPUT: decode_62 -* OUTPUT: decode_63 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 -Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 -XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec -XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec -XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec -XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec -XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec -XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec -XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec -XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec -XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec -XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec -XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec -XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec -XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec -XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec -XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec -XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec -XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec -XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec -XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec -XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec -XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec -XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec -XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec -XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec -XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec -XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec -XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec -XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec -XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec -XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec -XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec -XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec -XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec -XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec -XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec -XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec -XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec -XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec -XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec -XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec -XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec -XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec -XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec -XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec -XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec -XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec -XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec -XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec -XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec -XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec -XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec -XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec -XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec -XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec -XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec -XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec -XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec -XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec -XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec -XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec -XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec -XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec -XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec -XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec -.ENDS hierarchical_decoder - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: dout0_2 -* OUTPUT: dout0_3 -* OUTPUT: dout0_4 -* OUTPUT: dout0_5 -* OUTPUT: dout0_6 -* OUTPUT: dout0_7 -* OUTPUT: dout0_8 -* OUTPUT: dout0_9 -* OUTPUT: dout0_10 -* OUTPUT: dout0_11 -* OUTPUT: dout0_12 -* OUTPUT: dout0_13 -* OUTPUT: dout0_14 -* OUTPUT: dout0_15 -* OUTPUT: dout0_16 -* OUTPUT: dout0_17 -* OUTPUT: dout0_18 -* OUTPUT: dout0_19 -* OUTPUT: dout0_20 -* OUTPUT: dout0_21 -* OUTPUT: dout0_22 -* OUTPUT: dout0_23 -* OUTPUT: dout0_24 -* OUTPUT: dout0_25 -* OUTPUT: dout0_26 -* OUTPUT: dout0_27 -* OUTPUT: dout0_28 -* OUTPUT: dout0_29 -* OUTPUT: dout0_30 -* OUTPUT: dout0_31 -* OUTPUT: dout0_32 -* OUTPUT: dout0_33 -* OUTPUT: dout0_34 -* OUTPUT: dout0_35 -* OUTPUT: dout0_36 -* OUTPUT: dout0_37 -* OUTPUT: dout0_38 -* OUTPUT: dout0_39 -* OUTPUT: dout0_40 -* OUTPUT: dout0_41 -* OUTPUT: dout0_42 -* OUTPUT: dout0_43 -* OUTPUT: dout0_44 -* OUTPUT: dout0_45 -* OUTPUT: dout0_46 -* OUTPUT: dout0_47 -* OUTPUT: dout0_48 -* OUTPUT: dout0_49 -* OUTPUT: dout0_50 -* OUTPUT: dout0_51 -* OUTPUT: dout0_52 -* OUTPUT: dout0_53 -* OUTPUT: dout0_54 -* OUTPUT: dout0_55 -* OUTPUT: dout0_56 -* OUTPUT: dout0_57 -* OUTPUT: dout0_58 -* OUTPUT: dout0_59 -* OUTPUT: dout0_60 -* OUTPUT: dout0_61 -* OUTPUT: dout0_62 -* OUTPUT: dout0_63 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : din0_2 -* INPUT : din0_3 -* INPUT : din0_4 -* INPUT : din0_5 -* INPUT : din0_6 -* INPUT : din0_7 -* INPUT : din0_8 -* INPUT : din0_9 -* INPUT : din0_10 -* INPUT : din0_11 -* INPUT : din0_12 -* INPUT : din0_13 -* INPUT : din0_14 -* INPUT : din0_15 -* INPUT : din0_16 -* INPUT : din0_17 -* INPUT : din0_18 -* INPUT : din0_19 -* INPUT : din0_20 -* INPUT : din0_21 -* INPUT : din0_22 -* INPUT : din0_23 -* INPUT : din0_24 -* INPUT : din0_25 -* INPUT : din0_26 -* INPUT : din0_27 -* INPUT : din0_28 -* INPUT : din0_29 -* INPUT : din0_30 -* INPUT : din0_31 -* INPUT : din0_32 -* INPUT : din0_33 -* INPUT : din0_34 -* INPUT : din0_35 -* INPUT : din0_36 -* INPUT : din0_37 -* INPUT : din0_38 -* INPUT : din0_39 -* INPUT : din0_40 -* INPUT : din0_41 -* INPUT : din0_42 -* INPUT : din0_43 -* INPUT : din0_44 -* INPUT : din0_45 -* INPUT : din0_46 -* INPUT : din0_47 -* INPUT : din0_48 -* INPUT : din0_49 -* INPUT : din0_50 -* INPUT : din0_51 -* INPUT : din0_52 -* INPUT : din0_53 -* INPUT : din0_54 -* INPUT : din0_55 -* INPUT : din0_56 -* INPUT : din0_57 -* INPUT : din0_58 -* INPUT : din0_59 -* INPUT : din0_60 -* INPUT : din0_61 -* INPUT : din0_62 -* INPUT : din0_63 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : addr0_4 -* INPUT : addr0_5 -* INPUT : addr0_6 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address -Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf -.ENDS bank - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_2 -Xdff_buf_inv2 Qb Q vdd gnd pinv_3 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_0 - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -.SUBCKT pinv_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p -.ENDS pinv_4 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_4 -.ENDS pdriver - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p -Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p -.ENDS pinv_11 - -* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p -.ENDS pinv_9 - -* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p -Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -.ENDS pinv_10 - -* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p - -* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p - -.SUBCKT pinv_12 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p -Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p -.ENDS pinv_12 - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_7 - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_8 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 1, 2, 5, 14, 42, 125] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 -Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 -Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 -Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 -.ENDS pdriver_0 - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3_0 - -* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p - -* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -.SUBCKT pinv_16 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p -Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -.ENDS pinv_16 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [64] -Xbuf_inv1 A Z vdd gnd pinv_16 -.ENDS pdriver_3 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -.SUBCKT pinv_17 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_17 - -* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p - -* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p - -.SUBCKT pinv_18 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p -Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p -.ENDS pinv_18 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 2, 5, 14, 43] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 -Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 -.ENDS pdriver_4 - -* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p - -* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p - -.SUBCKT pinv_15 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p -Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p -.ENDS pinv_15 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [72] -Xbuf_inv1 A Z vdd gnd pinv_15 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT pinv_19 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_19 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_19 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 -Xdinv1 dout_1 dout_2 vdd gnd pinv_19 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 -Xdinv2 dout_2 dout_3 vdd gnd pinv_19 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 -Xdinv3 dout_3 dout_4 vdd gnd pinv_19 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 -Xdinv4 dout_4 dout_5 vdd gnd pinv_19 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 -Xdinv5 dout_5 dout_6 vdd gnd pinv_19 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 -Xdinv6 dout_6 dout_7 vdd gnd pinv_19 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 -Xdinv7 dout_7 dout_8 vdd gnd pinv_19 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 -Xdinv8 dout_8 out vdd gnd pinv_19 -Xdload_8_0 out n_8_0 vdd gnd pinv_19 -Xdload_8_1 out n_8_1 vdd gnd pinv_19 -Xdload_8_2 out n_8_2 vdd gnd pinv_19 -Xdload_8_3 out n_8_3 vdd gnd pinv_19 -.ENDS delay_chain - -* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p - -.SUBCKT pinv_14 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p -Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p -.ENDS pinv_14 - -* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p - -.SUBCKT pinv_13 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p -.ENDS pinv_13 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [7, 21] -Xbuf_inv1 A Zb1_int vdd gnd pinv_13 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 -.ENDS pdriver_1 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_1 - -* Used for tiling delay chain to desired length -.SUBCKT delay_chain_segment in out vdd gnd -Xdinv0 in dout_1 vdd gnd pinv_11 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 -Xdinv1 dout_1 out vdd gnd pinv_11 -Xdload_1_0 out n_1_0 vdd gnd pinv_11 -Xdload_1_1 out n_1_1 vdd gnd pinv_11 -Xdload_1_2 out n_1_2 vdd gnd pinv_11 -Xdload_1_3 out n_1_3 vdd gnd pinv_11 -.ENDS delay_chain_segment - -.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd -Xdelay1 in out1 vdd gnd delay_chain_segment -Xdelay2 out1 out2 vdd gnd delay_chain_segment -Xdelay3 out2 out3 vdd gnd delay_chain_segment -Xdelay4 out3 out4 vdd gnd delay_chain_segment -Xdelay5 out4 out5 vdd gnd delay_chain_segment -Xdelay6 out5 out6 vdd gnd delay_chain_segment -Xdelay7 out6 out7 vdd gnd delay_chain_segment -Xdelay8 out7 out8 vdd gnd delay_chain_segment -Xdelay9 out8 out9 vdd gnd delay_chain_segment -Xdelay10 out9 out10 vdd gnd delay_chain_segment -Xdelay11 out10 out11 vdd gnd delay_chain_segment -Xdelay12 out11 out12 vdd gnd delay_chain_segment -Xdelay13 out12 out13 vdd gnd delay_chain_segment -Xdelay14 out13 out14 vdd gnd delay_chain_segment -Xdelay15 out14 out15 vdd gnd delay_chain_segment -Xdelay16 out15 out16 vdd gnd delay_chain_segment -.ENDS multi_delay_chain - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl (NO LONGER USED) -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -Xmulti_delay_chain gated_clk_buf out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain -Xinv_glitch1 out6 g1_end vdd gnd pinv_11 -Xinv_glitch2 out7 g2_end vdd gnd pinv_11 -Xinv_glitch3 out14 g3_end vdd gnd pinv_11 -Xnand2_glitch1 out1 g1_end glitch1_bar vdd gnd pnand2 -Xnand2_glitch2 gated_clk_buf g2_end glitch2_bar vdd gnd pnand2 -Xnand2_glitch3 out6 g3_end glitch3_bar vdd gnd pnand2 -Xinv_glitch3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 -* is cs_buf needed on larger memories? I don't remember why I needed this for small mems. Some timing bs surely -* I have a feeling this was another misguided workaround to proper gate sizing smh my head bruh -*Xbuf_cs cs cs_buf vdd gnd pdriver_0 -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -* uhhhh do I really need this?? can't I just roll this into one gate with the next? -Xinv_pre_sen glitch3_buf pre_sen vdd gnd pinv_11 -* I'm an idiot and the following two and3 gates are not supposed to be the same size smh -Xand_s_en we_bar gated_clk_bar pre_sen s_en vdd gnd pand3 -Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 -Xand_wl_en_unbuf cs glitch2_bar wl_en_unbuf vdd gnd pand2 -* Xbuf_wl_en is an untested addition, probably too slow but honestly hard to say because the -* fanout was so horrible on wl_en without it that maybe it's actually better now ¯\_(ツ)_/¯ -Xbuf_wl_en wl_en_unbuf wl_en vdd gnd pdriver_1 -Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd -*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : din0[2] -* INPUT : din0[3] -* INPUT : din0[4] -* INPUT : din0[5] -* INPUT : din0[6] -* INPUT : din0[7] -* INPUT : din0[8] -* INPUT : din0[9] -* INPUT : din0[10] -* INPUT : din0[11] -* INPUT : din0[12] -* INPUT : din0[13] -* INPUT : din0[14] -* INPUT : din0[15] -* INPUT : din0[16] -* INPUT : din0[17] -* INPUT : din0[18] -* INPUT : din0[19] -* INPUT : din0[20] -* INPUT : din0[21] -* INPUT : din0[22] -* INPUT : din0[23] -* INPUT : din0[24] -* INPUT : din0[25] -* INPUT : din0[26] -* INPUT : din0[27] -* INPUT : din0[28] -* INPUT : din0[29] -* INPUT : din0[30] -* INPUT : din0[31] -* INPUT : din0[32] -* INPUT : din0[33] -* INPUT : din0[34] -* INPUT : din0[35] -* INPUT : din0[36] -* INPUT : din0[37] -* INPUT : din0[38] -* INPUT : din0[39] -* INPUT : din0[40] -* INPUT : din0[41] -* INPUT : din0[42] -* INPUT : din0[43] -* INPUT : din0[44] -* INPUT : din0[45] -* INPUT : din0[46] -* INPUT : din0[47] -* INPUT : din0[48] -* INPUT : din0[49] -* INPUT : din0[50] -* INPUT : din0[51] -* INPUT : din0[52] -* INPUT : din0[53] -* INPUT : din0[54] -* INPUT : din0[55] -* INPUT : din0[56] -* INPUT : din0[57] -* INPUT : din0[58] -* INPUT : din0[59] -* INPUT : din0[60] -* INPUT : din0[61] -* INPUT : din0[62] -* INPUT : din0[63] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : addr0[4] -* INPUT : addr0[5] -* INPUT : addr0[6] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* OUTPUT: dout0[2] -* OUTPUT: dout0[3] -* OUTPUT: dout0[4] -* OUTPUT: dout0[5] -* OUTPUT: dout0[6] -* OUTPUT: dout0[7] -* OUTPUT: dout0[8] -* OUTPUT: dout0[9] -* OUTPUT: dout0[10] -* OUTPUT: dout0[11] -* OUTPUT: dout0[12] -* OUTPUT: dout0[13] -* OUTPUT: dout0[14] -* OUTPUT: dout0[15] -* OUTPUT: dout0[16] -* OUTPUT: dout0[17] -* OUTPUT: dout0[18] -* OUTPUT: dout0[19] -* OUTPUT: dout0[20] -* OUTPUT: dout0[21] -* OUTPUT: dout0[22] -* OUTPUT: dout0[23] -* OUTPUT: dout0[24] -* OUTPUT: dout0[25] -* OUTPUT: dout0[26] -* OUTPUT: dout0[27] -* OUTPUT: dout0[28] -* OUTPUT: dout0[29] -* OUTPUT: dout0[30] -* OUTPUT: dout0[31] -* OUTPUT: dout0[32] -* OUTPUT: dout0[33] -* OUTPUT: dout0[34] -* OUTPUT: dout0[35] -* OUTPUT: dout0[36] -* OUTPUT: dout0[37] -* OUTPUT: dout0[38] -* OUTPUT: dout0[39] -* OUTPUT: dout0[40] -* OUTPUT: dout0[41] -* OUTPUT: dout0[42] -* OUTPUT: dout0[43] -* OUTPUT: dout0[44] -* OUTPUT: dout0[45] -* OUTPUT: dout0[46] -* OUTPUT: dout0[47] -* OUTPUT: dout0[48] -* OUTPUT: dout0[49] -* OUTPUT: dout0[50] -* OUTPUT: dout0[51] -* OUTPUT: dout0[52] -* OUTPUT: dout0[53] -* OUTPUT: dout0[54] -* OUTPUT: dout0[55] -* OUTPUT: dout0[56] -* OUTPUT: dout0[57] -* OUTPUT: dout0[58] -* OUTPUT: dout0[59] -* OUTPUT: dout0[60] -* OUTPUT: dout0[61] -* OUTPUT: dout0[62] -* OUTPUT: dout0[63] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff -Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff -Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff -.ENDS sram_64_128_scn4m_subm diff --git a/1KB/delay_sram_64_128_scn4m_subm.sp b/1KB/delay_sram_64_128_scn4m_subm.sp deleted file mode 100644 index 29564798..00000000 --- a/1KB/delay_sram_64_128_scn4m_subm.sp +++ /dev/null @@ -1,14096 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 128 -* Data bits: 64 -* Banks: 1 -* Column mux: 2:1 -* Trimmed: False -* LVS: False -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 6 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff -Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff -.ENDS row_addr_dff - -.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd -*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B -* INPUT : din_0 -* OUTPUT: dout_0 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -.ENDS col_addr_dff - -.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 64 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff -Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff -Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff -Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff -Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff -Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff -Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff -Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff -Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff -Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff -Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff -Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff -Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff -Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff -Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff -Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff -Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff -Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff -Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff -Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff -Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff -Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff -Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff -Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff -Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff -Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff -Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff -Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff -Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff -Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff -Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff -Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff -Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff -Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff -Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff -Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff -Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff -Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff -Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff -Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff -Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff -Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff -Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff -Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff -Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff -Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff -Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff -Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff -Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff -Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff -Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff -Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff -Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff -Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff -Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff -Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff -Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff -Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff -Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff -Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff -Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff -Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff -.ENDS data_dff - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_2 - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_3 - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_1 - -.SUBCKT pinvbuf A Zb Z vdd gnd -*.PININFO A:B Zb:B Z:B vdd:B gnd:B -* INOUT : A -* INOUT : Zb -* INOUT : Z -* INOUT : vdd -* INOUT : gnd -Xbuf_inv1 A zb_int vdd gnd pinv_1 -Xbuf_inv2 zb_int z_int vdd gnd pinv_2 -Xbuf_inv3 z_int Zb vdd gnd pinv_3 -Xbuf_inv4 zb_int Z vdd gnd pinv_3 -.ENDS pinvbuf - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw -Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw -Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw -Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw -Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw -Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw -Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw -Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw -Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw -Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw -Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw -Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw -Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw -Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw -Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw -Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw -Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw -Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw -Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw -Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw -Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw -Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw -Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw -Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw -Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw -Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw -Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw -Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw -Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw -Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw -Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw -Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw -Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw -Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw -Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw -Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw -Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw -Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw -Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw -Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw -Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw -Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw -Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw -Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw -Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw -Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw -Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw -Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw -Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c15 bl_0_15 br_0_15 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c15 bl_0_15 br_0_15 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c15 bl_0_15 br_0_15 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c15 bl_0_15 br_0_15 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c15 bl_0_15 br_0_15 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c15 bl_0_15 br_0_15 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c15 bl_0_15 br_0_15 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c15 bl_0_15 br_0_15 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c15 bl_0_15 br_0_15 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c15 bl_0_15 br_0_15 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c15 bl_0_15 br_0_15 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c15 bl_0_15 br_0_15 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c15 bl_0_15 br_0_15 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c44 bl_0_44 br_0_44 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c44 bl_0_44 br_0_44 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c44 bl_0_44 br_0_44 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c44 bl_0_44 br_0_44 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c44 bl_0_44 br_0_44 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c44 bl_0_44 br_0_44 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c44 bl_0_44 br_0_44 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c44 bl_0_44 br_0_44 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c44 bl_0_44 br_0_44 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c44 bl_0_44 br_0_44 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c44 bl_0_44 br_0_44 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c44 bl_0_44 br_0_44 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c44 bl_0_44 br_0_44 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c44 bl_0_44 br_0_44 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c44 bl_0_44 br_0_44 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c44 bl_0_44 br_0_44 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c44 bl_0_44 br_0_44 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c44 bl_0_44 br_0_44 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c49 bl_0_49 br_0_49 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c49 bl_0_49 br_0_49 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c49 bl_0_49 br_0_49 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c49 bl_0_49 br_0_49 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c49 bl_0_49 br_0_49 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c49 bl_0_49 br_0_49 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c49 bl_0_49 br_0_49 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c49 bl_0_49 br_0_49 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c49 bl_0_49 br_0_49 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c49 bl_0_49 br_0_49 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c49 bl_0_49 br_0_49 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c49 bl_0_49 br_0_49 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c49 bl_0_49 br_0_49 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c49 bl_0_49 br_0_49 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c49 bl_0_49 br_0_49 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c49 bl_0_49 br_0_49 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c49 bl_0_49 br_0_49 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c49 bl_0_49 br_0_49 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c52 bl_0_52 br_0_52 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c52 bl_0_52 br_0_52 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c52 bl_0_52 br_0_52 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c52 bl_0_52 br_0_52 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c52 bl_0_52 br_0_52 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c52 bl_0_52 br_0_52 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c52 bl_0_52 br_0_52 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c52 bl_0_52 br_0_52 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c52 bl_0_52 br_0_52 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c52 bl_0_52 br_0_52 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c52 bl_0_52 br_0_52 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c53 bl_0_53 br_0_53 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c53 bl_0_53 br_0_53 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c53 bl_0_53 br_0_53 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c53 bl_0_53 br_0_53 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c53 bl_0_53 br_0_53 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c53 bl_0_53 br_0_53 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c53 bl_0_53 br_0_53 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c53 bl_0_53 br_0_53 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c53 bl_0_53 br_0_53 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c53 bl_0_53 br_0_53 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c53 bl_0_53 br_0_53 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c53 bl_0_53 br_0_53 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c53 bl_0_53 br_0_53 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c53 bl_0_53 br_0_53 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c53 bl_0_53 br_0_53 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c53 bl_0_53 br_0_53 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c53 bl_0_53 br_0_53 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c53 bl_0_53 br_0_53 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c53 bl_0_53 br_0_53 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c53 bl_0_53 br_0_53 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c53 bl_0_53 br_0_53 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c53 bl_0_53 br_0_53 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c53 bl_0_53 br_0_53 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c53 bl_0_53 br_0_53 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c53 bl_0_53 br_0_53 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c53 bl_0_53 br_0_53 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c53 bl_0_53 br_0_53 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c53 bl_0_53 br_0_53 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c53 bl_0_53 br_0_53 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c53 bl_0_53 br_0_53 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c53 bl_0_53 br_0_53 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c53 bl_0_53 br_0_53 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c53 bl_0_53 br_0_53 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c53 bl_0_53 br_0_53 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c53 bl_0_53 br_0_53 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c53 bl_0_53 br_0_53 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c53 bl_0_53 br_0_53 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c53 bl_0_53 br_0_53 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c53 bl_0_53 br_0_53 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c53 bl_0_53 br_0_53 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c53 bl_0_53 br_0_53 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c53 bl_0_53 br_0_53 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c53 bl_0_53 br_0_53 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c59 bl_0_59 br_0_59 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c59 bl_0_59 br_0_59 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c59 bl_0_59 br_0_59 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c60 bl_0_60 br_0_60 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c60 bl_0_60 br_0_60 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c60 bl_0_60 br_0_60 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c60 bl_0_60 br_0_60 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c60 bl_0_60 br_0_60 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c60 bl_0_60 br_0_60 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c60 bl_0_60 br_0_60 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c60 bl_0_60 br_0_60 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c60 bl_0_60 br_0_60 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c60 bl_0_60 br_0_60 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c60 bl_0_60 br_0_60 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c60 bl_0_60 br_0_60 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c60 bl_0_60 br_0_60 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c60 bl_0_60 br_0_60 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c60 bl_0_60 br_0_60 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c73 bl_0_73 br_0_73 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c73 bl_0_73 br_0_73 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c73 bl_0_73 br_0_73 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c73 bl_0_73 br_0_73 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c73 bl_0_73 br_0_73 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c73 bl_0_73 br_0_73 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c73 bl_0_73 br_0_73 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c73 bl_0_73 br_0_73 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c73 bl_0_73 br_0_73 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c73 bl_0_73 br_0_73 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c73 bl_0_73 br_0_73 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c73 bl_0_73 br_0_73 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c73 bl_0_73 br_0_73 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c73 bl_0_73 br_0_73 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c73 bl_0_73 br_0_73 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c73 bl_0_73 br_0_73 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c73 bl_0_73 br_0_73 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c73 bl_0_73 br_0_73 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c74 bl_0_74 br_0_74 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c74 bl_0_74 br_0_74 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c74 bl_0_74 br_0_74 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c74 bl_0_74 br_0_74 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c74 bl_0_74 br_0_74 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c74 bl_0_74 br_0_74 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c74 bl_0_74 br_0_74 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c74 bl_0_74 br_0_74 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c74 bl_0_74 br_0_74 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c74 bl_0_74 br_0_74 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c74 bl_0_74 br_0_74 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c74 bl_0_74 br_0_74 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c74 bl_0_74 br_0_74 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c74 bl_0_74 br_0_74 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c74 bl_0_74 br_0_74 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c74 bl_0_74 br_0_74 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c74 bl_0_74 br_0_74 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c74 bl_0_74 br_0_74 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c74 bl_0_74 br_0_74 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c74 bl_0_74 br_0_74 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c74 bl_0_74 br_0_74 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c74 bl_0_74 br_0_74 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c74 bl_0_74 br_0_74 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c74 bl_0_74 br_0_74 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c74 bl_0_74 br_0_74 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c74 bl_0_74 br_0_74 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c74 bl_0_74 br_0_74 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c74 bl_0_74 br_0_74 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c74 bl_0_74 br_0_74 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c74 bl_0_74 br_0_74 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c74 bl_0_74 br_0_74 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c74 bl_0_74 br_0_74 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c74 bl_0_74 br_0_74 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c75 bl_0_75 br_0_75 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c75 bl_0_75 br_0_75 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c75 bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c75 bl_0_75 br_0_75 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c75 bl_0_75 br_0_75 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c75 bl_0_75 br_0_75 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c75 bl_0_75 br_0_75 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c75 bl_0_75 br_0_75 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c75 bl_0_75 br_0_75 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c76 bl_0_76 br_0_76 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c76 bl_0_76 br_0_76 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c76 bl_0_76 br_0_76 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c76 bl_0_76 br_0_76 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c76 bl_0_76 br_0_76 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c76 bl_0_76 br_0_76 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c76 bl_0_76 br_0_76 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c76 bl_0_76 br_0_76 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c76 bl_0_76 br_0_76 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c76 bl_0_76 br_0_76 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c76 bl_0_76 br_0_76 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c76 bl_0_76 br_0_76 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c81 bl_0_81 br_0_81 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c81 bl_0_81 br_0_81 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c81 bl_0_81 br_0_81 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c81 bl_0_81 br_0_81 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c81 bl_0_81 br_0_81 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c81 bl_0_81 br_0_81 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c81 bl_0_81 br_0_81 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c82 bl_0_82 br_0_82 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c82 bl_0_82 br_0_82 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c82 bl_0_82 br_0_82 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c82 bl_0_82 br_0_82 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c82 bl_0_82 br_0_82 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c82 bl_0_82 br_0_82 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c82 bl_0_82 br_0_82 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c82 bl_0_82 br_0_82 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c82 bl_0_82 br_0_82 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c82 bl_0_82 br_0_82 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c82 bl_0_82 br_0_82 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c83 bl_0_83 br_0_83 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c83 bl_0_83 br_0_83 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c84 bl_0_84 br_0_84 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c84 bl_0_84 br_0_84 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c84 bl_0_84 br_0_84 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c84 bl_0_84 br_0_84 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c84 bl_0_84 br_0_84 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c84 bl_0_84 br_0_84 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c84 bl_0_84 br_0_84 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c84 bl_0_84 br_0_84 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c84 bl_0_84 br_0_84 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c84 bl_0_84 br_0_84 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c84 bl_0_84 br_0_84 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c84 bl_0_84 br_0_84 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c84 bl_0_84 br_0_84 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c84 bl_0_84 br_0_84 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c84 bl_0_84 br_0_84 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c84 bl_0_84 br_0_84 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c87 bl_0_87 br_0_87 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c87 bl_0_87 br_0_87 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c87 bl_0_87 br_0_87 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c87 bl_0_87 br_0_87 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c87 bl_0_87 br_0_87 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c87 bl_0_87 br_0_87 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c87 bl_0_87 br_0_87 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c87 bl_0_87 br_0_87 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c88 bl_0_88 br_0_88 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c88 bl_0_88 br_0_88 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c88 bl_0_88 br_0_88 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c88 bl_0_88 br_0_88 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c88 bl_0_88 br_0_88 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c88 bl_0_88 br_0_88 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c88 bl_0_88 br_0_88 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c88 bl_0_88 br_0_88 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c88 bl_0_88 br_0_88 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c88 bl_0_88 br_0_88 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c89 bl_0_89 br_0_89 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c89 bl_0_89 br_0_89 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c89 bl_0_89 br_0_89 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c90 bl_0_90 br_0_90 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c90 bl_0_90 br_0_90 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c90 bl_0_90 br_0_90 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c90 bl_0_90 br_0_90 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c90 bl_0_90 br_0_90 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c90 bl_0_90 br_0_90 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c90 bl_0_90 br_0_90 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c90 bl_0_90 br_0_90 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c90 bl_0_90 br_0_90 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c90 bl_0_90 br_0_90 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c90 bl_0_90 br_0_90 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c90 bl_0_90 br_0_90 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c90 bl_0_90 br_0_90 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c90 bl_0_90 br_0_90 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c90 bl_0_90 br_0_90 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c96 bl_0_96 br_0_96 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c96 bl_0_96 br_0_96 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c96 bl_0_96 br_0_96 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c96 bl_0_96 br_0_96 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c96 bl_0_96 br_0_96 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c96 bl_0_96 br_0_96 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c96 bl_0_96 br_0_96 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c96 bl_0_96 br_0_96 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c96 bl_0_96 br_0_96 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c96 bl_0_96 br_0_96 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c96 bl_0_96 br_0_96 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c96 bl_0_96 br_0_96 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c96 bl_0_96 br_0_96 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c96 bl_0_96 br_0_96 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c96 bl_0_96 br_0_96 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c96 bl_0_96 br_0_96 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c96 bl_0_96 br_0_96 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c96 bl_0_96 br_0_96 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c96 bl_0_96 br_0_96 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c97 bl_0_97 br_0_97 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c97 bl_0_97 br_0_97 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c97 bl_0_97 br_0_97 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c97 bl_0_97 br_0_97 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c97 bl_0_97 br_0_97 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c97 bl_0_97 br_0_97 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c97 bl_0_97 br_0_97 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c97 bl_0_97 br_0_97 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c97 bl_0_97 br_0_97 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c97 bl_0_97 br_0_97 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c97 bl_0_97 br_0_97 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c97 bl_0_97 br_0_97 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c97 bl_0_97 br_0_97 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c97 bl_0_97 br_0_97 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c97 bl_0_97 br_0_97 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c97 bl_0_97 br_0_97 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c97 bl_0_97 br_0_97 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c98 bl_0_98 br_0_98 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c98 bl_0_98 br_0_98 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c98 bl_0_98 br_0_98 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c98 bl_0_98 br_0_98 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c98 bl_0_98 br_0_98 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c98 bl_0_98 br_0_98 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c98 bl_0_98 br_0_98 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c98 bl_0_98 br_0_98 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c98 bl_0_98 br_0_98 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c98 bl_0_98 br_0_98 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c98 bl_0_98 br_0_98 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c98 bl_0_98 br_0_98 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c98 bl_0_98 br_0_98 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c98 bl_0_98 br_0_98 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c99 bl_0_99 br_0_99 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c99 bl_0_99 br_0_99 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c99 bl_0_99 br_0_99 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c99 bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c100 bl_0_100 br_0_100 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c100 bl_0_100 br_0_100 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c100 bl_0_100 br_0_100 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c100 bl_0_100 br_0_100 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c100 bl_0_100 br_0_100 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c100 bl_0_100 br_0_100 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c100 bl_0_100 br_0_100 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c100 bl_0_100 br_0_100 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c100 bl_0_100 br_0_100 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c100 bl_0_100 br_0_100 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c100 bl_0_100 br_0_100 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c100 bl_0_100 br_0_100 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c100 bl_0_100 br_0_100 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c100 bl_0_100 br_0_100 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c100 bl_0_100 br_0_100 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c100 bl_0_100 br_0_100 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c100 bl_0_100 br_0_100 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c108 bl_0_108 br_0_108 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c108 bl_0_108 br_0_108 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c108 bl_0_108 br_0_108 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c108 bl_0_108 br_0_108 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c108 bl_0_108 br_0_108 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c108 bl_0_108 br_0_108 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c108 bl_0_108 br_0_108 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c108 bl_0_108 br_0_108 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c108 bl_0_108 br_0_108 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c108 bl_0_108 br_0_108 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c108 bl_0_108 br_0_108 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c108 bl_0_108 br_0_108 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c108 bl_0_108 br_0_108 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c108 bl_0_108 br_0_108 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c108 bl_0_108 br_0_108 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c108 bl_0_108 br_0_108 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c108 bl_0_108 br_0_108 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c108 bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c110 bl_0_110 br_0_110 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c110 bl_0_110 br_0_110 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c110 bl_0_110 br_0_110 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c110 bl_0_110 br_0_110 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c110 bl_0_110 br_0_110 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c110 bl_0_110 br_0_110 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c110 bl_0_110 br_0_110 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c110 bl_0_110 br_0_110 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c110 bl_0_110 br_0_110 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c110 bl_0_110 br_0_110 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c110 bl_0_110 br_0_110 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c110 bl_0_110 br_0_110 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c110 bl_0_110 br_0_110 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c110 bl_0_110 br_0_110 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c110 bl_0_110 br_0_110 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c110 bl_0_110 br_0_110 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c110 bl_0_110 br_0_110 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c110 bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c111 bl_0_111 br_0_111 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c111 bl_0_111 br_0_111 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c111 bl_0_111 br_0_111 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c111 bl_0_111 br_0_111 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c111 bl_0_111 br_0_111 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c111 bl_0_111 br_0_111 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c111 bl_0_111 br_0_111 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c111 bl_0_111 br_0_111 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c111 bl_0_111 br_0_111 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c111 bl_0_111 br_0_111 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c111 bl_0_111 br_0_111 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c111 bl_0_111 br_0_111 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c111 bl_0_111 br_0_111 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c111 bl_0_111 br_0_111 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c111 bl_0_111 br_0_111 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c111 bl_0_111 br_0_111 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c111 bl_0_111 br_0_111 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c111 bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c112 bl_0_112 br_0_112 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c112 bl_0_112 br_0_112 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c112 bl_0_112 br_0_112 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c112 bl_0_112 br_0_112 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c112 bl_0_112 br_0_112 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c112 bl_0_112 br_0_112 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c112 bl_0_112 br_0_112 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c112 bl_0_112 br_0_112 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c112 bl_0_112 br_0_112 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c112 bl_0_112 br_0_112 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c112 bl_0_112 br_0_112 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c112 bl_0_112 br_0_112 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c112 bl_0_112 br_0_112 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c112 bl_0_112 br_0_112 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c112 bl_0_112 br_0_112 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c112 bl_0_112 br_0_112 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c112 bl_0_112 br_0_112 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c112 bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c114 bl_0_114 br_0_114 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c114 bl_0_114 br_0_114 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c114 bl_0_114 br_0_114 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c114 bl_0_114 br_0_114 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c114 bl_0_114 br_0_114 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c114 bl_0_114 br_0_114 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c114 bl_0_114 br_0_114 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c114 bl_0_114 br_0_114 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c114 bl_0_114 br_0_114 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c114 bl_0_114 br_0_114 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c114 bl_0_114 br_0_114 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c114 bl_0_114 br_0_114 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c114 bl_0_114 br_0_114 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c114 bl_0_114 br_0_114 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c114 bl_0_114 br_0_114 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c115 bl_0_115 br_0_115 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c115 bl_0_115 br_0_115 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c116 bl_0_116 br_0_116 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c116 bl_0_116 br_0_116 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c116 bl_0_116 br_0_116 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c116 bl_0_116 br_0_116 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c116 bl_0_116 br_0_116 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c116 bl_0_116 br_0_116 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c116 bl_0_116 br_0_116 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c116 bl_0_116 br_0_116 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c116 bl_0_116 br_0_116 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c116 bl_0_116 br_0_116 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c116 bl_0_116 br_0_116 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c116 bl_0_116 br_0_116 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c116 bl_0_116 br_0_116 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c116 bl_0_116 br_0_116 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c116 bl_0_116 br_0_116 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c116 bl_0_116 br_0_116 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c116 bl_0_116 br_0_116 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c116 bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c119 bl_0_119 br_0_119 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c119 bl_0_119 br_0_119 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c119 bl_0_119 br_0_119 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c119 bl_0_119 br_0_119 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c119 bl_0_119 br_0_119 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c119 bl_0_119 br_0_119 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c119 bl_0_119 br_0_119 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c119 bl_0_119 br_0_119 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c119 bl_0_119 br_0_119 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c119 bl_0_119 br_0_119 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c119 bl_0_119 br_0_119 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c119 bl_0_119 br_0_119 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c119 bl_0_119 br_0_119 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c119 bl_0_119 br_0_119 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c119 bl_0_119 br_0_119 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c119 bl_0_119 br_0_119 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c119 bl_0_119 br_0_119 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c119 bl_0_119 br_0_119 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c119 bl_0_119 br_0_119 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c119 bl_0_119 br_0_119 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c119 bl_0_119 br_0_119 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c119 bl_0_119 br_0_119 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c119 bl_0_119 br_0_119 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c119 bl_0_119 br_0_119 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c119 bl_0_119 br_0_119 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c119 bl_0_119 br_0_119 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c119 bl_0_119 br_0_119 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c119 bl_0_119 br_0_119 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c119 bl_0_119 br_0_119 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c119 bl_0_119 br_0_119 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c119 bl_0_119 br_0_119 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c119 bl_0_119 br_0_119 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c119 bl_0_119 br_0_119 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c119 bl_0_119 br_0_119 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c119 bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c120 bl_0_120 br_0_120 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c120 bl_0_120 br_0_120 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c120 bl_0_120 br_0_120 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c120 bl_0_120 br_0_120 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c120 bl_0_120 br_0_120 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c120 bl_0_120 br_0_120 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c120 bl_0_120 br_0_120 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c120 bl_0_120 br_0_120 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c120 bl_0_120 br_0_120 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c120 bl_0_120 br_0_120 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c120 bl_0_120 br_0_120 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c120 bl_0_120 br_0_120 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c120 bl_0_120 br_0_120 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c120 bl_0_120 br_0_120 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c120 bl_0_120 br_0_120 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c120 bl_0_120 br_0_120 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c120 bl_0_120 br_0_120 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c120 bl_0_120 br_0_120 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c120 bl_0_120 br_0_120 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c120 bl_0_120 br_0_120 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c120 bl_0_120 br_0_120 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c120 bl_0_120 br_0_120 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c120 bl_0_120 br_0_120 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c120 bl_0_120 br_0_120 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c120 bl_0_120 br_0_120 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c120 bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c121 bl_0_121 br_0_121 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c121 bl_0_121 br_0_121 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c121 bl_0_121 br_0_121 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c121 bl_0_121 br_0_121 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c121 bl_0_121 br_0_121 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c121 bl_0_121 br_0_121 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c121 bl_0_121 br_0_121 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c121 bl_0_121 br_0_121 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c121 bl_0_121 br_0_121 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c121 bl_0_121 br_0_121 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c121 bl_0_121 br_0_121 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c121 bl_0_121 br_0_121 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c121 bl_0_121 br_0_121 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c121 bl_0_121 br_0_121 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c121 bl_0_121 br_0_121 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c121 bl_0_121 br_0_121 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c121 bl_0_121 br_0_121 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c121 bl_0_121 br_0_121 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c121 bl_0_121 br_0_121 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c121 bl_0_121 br_0_121 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c121 bl_0_121 br_0_121 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c121 bl_0_121 br_0_121 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c121 bl_0_121 br_0_121 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c121 bl_0_121 br_0_121 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c121 bl_0_121 br_0_121 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c121 bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c122 bl_0_122 br_0_122 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c122 bl_0_122 br_0_122 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c122 bl_0_122 br_0_122 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c122 bl_0_122 br_0_122 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c122 bl_0_122 br_0_122 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c122 bl_0_122 br_0_122 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c122 bl_0_122 br_0_122 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c122 bl_0_122 br_0_122 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c122 bl_0_122 br_0_122 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c122 bl_0_122 br_0_122 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c122 bl_0_122 br_0_122 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c122 bl_0_122 br_0_122 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c122 bl_0_122 br_0_122 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c122 bl_0_122 br_0_122 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c122 bl_0_122 br_0_122 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c122 bl_0_122 br_0_122 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c122 bl_0_122 br_0_122 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c122 bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c123 bl_0_123 br_0_123 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c123 bl_0_123 br_0_123 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c123 bl_0_123 br_0_123 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c123 bl_0_123 br_0_123 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c123 bl_0_123 br_0_123 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c123 bl_0_123 br_0_123 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c123 bl_0_123 br_0_123 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c123 bl_0_123 br_0_123 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c123 bl_0_123 br_0_123 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c123 bl_0_123 br_0_123 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c123 bl_0_123 br_0_123 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c123 bl_0_123 br_0_123 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c123 bl_0_123 br_0_123 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c123 bl_0_123 br_0_123 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c123 bl_0_123 br_0_123 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c123 bl_0_123 br_0_123 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c123 bl_0_123 br_0_123 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c123 bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c126 bl_0_126 br_0_126 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c126 bl_0_126 br_0_126 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c126 bl_0_126 br_0_126 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c126 bl_0_126 br_0_126 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c126 bl_0_126 br_0_126 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c126 bl_0_126 br_0_126 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c126 bl_0_126 br_0_126 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c126 bl_0_126 br_0_126 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c126 bl_0_126 br_0_126 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c126 bl_0_126 br_0_126 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c126 bl_0_126 br_0_126 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c126 bl_0_126 br_0_126 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c126 bl_0_126 br_0_126 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c126 bl_0_126 br_0_126 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c126 bl_0_126 br_0_126 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c126 bl_0_126 br_0_126 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c126 bl_0_126 br_0_126 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c126 bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c127 bl_0_127 br_0_127 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c127 bl_0_127 br_0_127 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c127 bl_0_127 br_0_127 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c127 bl_0_127 br_0_127 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c127 bl_0_127 br_0_127 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c127 bl_0_127 br_0_127 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c127 bl_0_127 br_0_127 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c127 bl_0_127 br_0_127 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c127 bl_0_127 br_0_127 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c127 bl_0_127 br_0_127 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c127 bl_0_127 br_0_127 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c127 bl_0_127 br_0_127 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c127 bl_0_127 br_0_127 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c127 bl_0_127 br_0_127 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c127 bl_0_127 br_0_127 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c127 bl_0_127 br_0_127 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c127 bl_0_127 br_0_127 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c127 bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw -.ENDS bitcell_array - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 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wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* OUTPUT: data_2 -* INPUT : bl_2 -* INPUT : br_2 -* OUTPUT: data_3 -* INPUT : bl_3 -* INPUT : br_3 -* OUTPUT: data_4 -* INPUT : bl_4 -* INPUT : br_4 -* OUTPUT: data_5 -* INPUT : bl_5 -* INPUT : br_5 -* OUTPUT: data_6 -* INPUT : bl_6 -* INPUT : br_6 -* OUTPUT: data_7 -* INPUT : bl_7 -* INPUT : br_7 -* OUTPUT: data_8 -* INPUT : bl_8 -* INPUT : br_8 -* OUTPUT: data_9 -* INPUT : bl_9 -* INPUT : br_9 -* OUTPUT: data_10 -* INPUT : bl_10 -* INPUT : br_10 -* OUTPUT: data_11 -* INPUT : bl_11 -* INPUT : br_11 -* OUTPUT: data_12 -* INPUT : bl_12 -* INPUT : br_12 -* OUTPUT: data_13 -* INPUT : bl_13 -* INPUT : br_13 -* OUTPUT: data_14 -* INPUT : bl_14 -* INPUT : br_14 -* OUTPUT: data_15 -* INPUT : bl_15 -* INPUT : br_15 -* OUTPUT: data_16 -* INPUT : bl_16 -* INPUT : br_16 -* OUTPUT: data_17 -* INPUT : bl_17 -* INPUT : br_17 -* OUTPUT: data_18 -* INPUT : bl_18 -* INPUT : br_18 -* OUTPUT: data_19 -* INPUT : bl_19 -* INPUT : br_19 -* OUTPUT: data_20 -* INPUT : bl_20 -* INPUT : br_20 -* OUTPUT: data_21 -* INPUT : bl_21 -* INPUT : br_21 -* OUTPUT: data_22 -* INPUT : bl_22 -* INPUT : br_22 -* OUTPUT: data_23 -* INPUT : bl_23 -* INPUT : br_23 -* OUTPUT: data_24 -* INPUT : bl_24 -* INPUT : br_24 -* OUTPUT: data_25 -* INPUT : bl_25 -* INPUT : br_25 -* OUTPUT: data_26 -* INPUT : bl_26 -* INPUT : br_26 -* OUTPUT: data_27 -* INPUT : bl_27 -* INPUT : br_27 -* OUTPUT: data_28 -* INPUT : bl_28 -* INPUT : br_28 -* OUTPUT: data_29 -* INPUT : bl_29 -* INPUT : br_29 -* OUTPUT: data_30 -* INPUT : bl_30 -* INPUT : br_30 -* OUTPUT: data_31 -* INPUT : bl_31 -* INPUT : br_31 -* OUTPUT: data_32 -* INPUT : bl_32 -* INPUT : br_32 -* OUTPUT: data_33 -* INPUT : bl_33 -* INPUT : br_33 -* OUTPUT: data_34 -* INPUT : bl_34 -* INPUT : br_34 -* OUTPUT: data_35 -* INPUT : bl_35 -* INPUT : br_35 -* OUTPUT: data_36 -* INPUT : bl_36 -* INPUT : br_36 -* OUTPUT: data_37 -* INPUT : bl_37 -* INPUT : br_37 -* OUTPUT: data_38 -* INPUT : bl_38 -* INPUT : br_38 -* OUTPUT: data_39 -* INPUT : bl_39 -* INPUT : br_39 -* OUTPUT: data_40 -* INPUT : bl_40 -* INPUT : br_40 -* OUTPUT: data_41 -* INPUT : bl_41 -* INPUT : br_41 -* OUTPUT: data_42 -* INPUT : bl_42 -* INPUT : br_42 -* OUTPUT: data_43 -* INPUT : bl_43 -* INPUT : br_43 -* OUTPUT: data_44 -* INPUT : bl_44 -* INPUT : br_44 -* OUTPUT: data_45 -* INPUT : bl_45 -* INPUT : br_45 -* OUTPUT: data_46 -* INPUT : bl_46 -* INPUT : br_46 -* OUTPUT: data_47 -* INPUT : bl_47 -* INPUT : br_47 -* OUTPUT: data_48 -* INPUT : bl_48 -* INPUT : br_48 -* OUTPUT: data_49 -* INPUT : bl_49 -* INPUT : br_49 -* OUTPUT: data_50 -* INPUT : bl_50 -* INPUT : br_50 -* OUTPUT: data_51 -* INPUT : bl_51 -* INPUT : br_51 -* OUTPUT: data_52 -* INPUT : bl_52 -* INPUT : br_52 -* OUTPUT: data_53 -* INPUT : bl_53 -* INPUT : br_53 -* OUTPUT: data_54 -* INPUT : bl_54 -* INPUT : br_54 -* OUTPUT: data_55 -* INPUT : bl_55 -* INPUT : br_55 -* OUTPUT: data_56 -* INPUT : bl_56 -* INPUT : br_56 -* OUTPUT: data_57 -* INPUT : bl_57 -* INPUT : br_57 -* OUTPUT: data_58 -* INPUT : bl_58 -* INPUT : br_58 -* OUTPUT: data_59 -* INPUT : bl_59 -* INPUT : br_59 -* OUTPUT: data_60 -* INPUT : bl_60 -* INPUT : br_60 -* OUTPUT: data_61 -* INPUT : bl_61 -* INPUT : br_61 -* OUTPUT: data_62 -* INPUT : bl_62 -* INPUT : br_62 -* OUTPUT: data_63 -* INPUT : bl_63 -* INPUT : br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 2 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp -Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp -Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp -Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp -Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp -Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp -Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp -Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp -Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp -Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp -Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp -Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp -Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp -Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp -Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp -Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp -Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp -Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp -Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp -Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp -Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp -Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp -Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp -Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp -Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp -Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp -Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp -Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp -Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp -Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp -Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp -Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp -Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp -Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp -Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp -Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp -Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp -Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp -Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp -Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp -Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp -Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp -Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp -Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp -Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp -Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp -Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp -Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp -Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp -Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp -Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp -Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp -Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp -Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp -Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp -Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp -Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp -Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp -Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp -Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp -Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp -Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp -.ENDS sense_amp_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* OUTPUT: bl_64 -* OUTPUT: br_64 -* OUTPUT: bl_65 -* OUTPUT: br_65 -* OUTPUT: bl_66 -* OUTPUT: br_66 -* OUTPUT: bl_67 -* OUTPUT: br_67 -* OUTPUT: bl_68 -* OUTPUT: br_68 -* OUTPUT: bl_69 -* OUTPUT: br_69 -* OUTPUT: bl_70 -* OUTPUT: br_70 -* OUTPUT: bl_71 -* OUTPUT: br_71 -* OUTPUT: bl_72 -* OUTPUT: br_72 -* OUTPUT: bl_73 -* OUTPUT: br_73 -* OUTPUT: bl_74 -* OUTPUT: br_74 -* OUTPUT: bl_75 -* OUTPUT: br_75 -* OUTPUT: bl_76 -* OUTPUT: br_76 -* OUTPUT: bl_77 -* OUTPUT: br_77 -* OUTPUT: bl_78 -* OUTPUT: br_78 -* OUTPUT: bl_79 -* OUTPUT: br_79 -* OUTPUT: bl_80 -* OUTPUT: br_80 -* OUTPUT: bl_81 -* OUTPUT: br_81 -* OUTPUT: bl_82 -* OUTPUT: br_82 -* OUTPUT: bl_83 -* OUTPUT: br_83 -* OUTPUT: bl_84 -* OUTPUT: br_84 -* OUTPUT: bl_85 -* OUTPUT: br_85 -* OUTPUT: bl_86 -* OUTPUT: br_86 -* OUTPUT: bl_87 -* OUTPUT: br_87 -* OUTPUT: bl_88 -* OUTPUT: br_88 -* OUTPUT: bl_89 -* OUTPUT: br_89 -* OUTPUT: bl_90 -* OUTPUT: br_90 -* OUTPUT: bl_91 -* OUTPUT: br_91 -* OUTPUT: bl_92 -* OUTPUT: br_92 -* OUTPUT: bl_93 -* OUTPUT: br_93 -* OUTPUT: bl_94 -* OUTPUT: br_94 -* OUTPUT: bl_95 -* OUTPUT: br_95 -* OUTPUT: bl_96 -* OUTPUT: br_96 -* OUTPUT: bl_97 -* OUTPUT: br_97 -* OUTPUT: bl_98 -* OUTPUT: br_98 -* OUTPUT: bl_99 -* OUTPUT: br_99 -* OUTPUT: bl_100 -* OUTPUT: br_100 -* OUTPUT: bl_101 -* OUTPUT: br_101 -* OUTPUT: bl_102 -* OUTPUT: br_102 -* OUTPUT: bl_103 -* OUTPUT: br_103 -* OUTPUT: bl_104 -* OUTPUT: br_104 -* OUTPUT: bl_105 -* OUTPUT: br_105 -* OUTPUT: bl_106 -* OUTPUT: br_106 -* OUTPUT: bl_107 -* OUTPUT: br_107 -* OUTPUT: bl_108 -* OUTPUT: br_108 -* OUTPUT: bl_109 -* OUTPUT: br_109 -* OUTPUT: bl_110 -* OUTPUT: br_110 -* OUTPUT: bl_111 -* OUTPUT: br_111 -* OUTPUT: bl_112 -* OUTPUT: br_112 -* OUTPUT: bl_113 -* OUTPUT: br_113 -* OUTPUT: bl_114 -* OUTPUT: br_114 -* OUTPUT: bl_115 -* OUTPUT: br_115 -* OUTPUT: bl_116 -* OUTPUT: br_116 -* OUTPUT: bl_117 -* OUTPUT: br_117 -* OUTPUT: bl_118 -* OUTPUT: br_118 -* OUTPUT: bl_119 -* OUTPUT: br_119 -* OUTPUT: bl_120 -* OUTPUT: br_120 -* OUTPUT: bl_121 -* OUTPUT: br_121 -* OUTPUT: bl_122 -* OUTPUT: br_122 -* OUTPUT: bl_123 -* OUTPUT: br_123 -* OUTPUT: bl_124 -* OUTPUT: br_124 -* OUTPUT: bl_125 -* OUTPUT: br_125 -* OUTPUT: bl_126 -* OUTPUT: br_126 -* OUTPUT: bl_127 -* OUTPUT: br_127 -* OUTPUT: bl_128 -* OUTPUT: br_128 -* INPUT : en_bar -* POWER : vdd -* cols: 129 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 -Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 -Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 -Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 -Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 -Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 -Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 -Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 -Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 -Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 -Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 -Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 -Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 -Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 -Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 -Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 -Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 -Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 -Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 -Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 -Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 -Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 -Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 -Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 -Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 -Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 -Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 -Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 -Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 -Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 -Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 -Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 -Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 -Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 -Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 -Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 -Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 -Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 -Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 -Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 -Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 -Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 -Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 -Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 -Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 -Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 -Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 -Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 -Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 -Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 -Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 -Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 -Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 -Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 -Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 -Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 -Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 -Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 -Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 -Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 -Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 -Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 -Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 -Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 -Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 -Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 -Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 -Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 -Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 -Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 -Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 -Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 -Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 -Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 -Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 -Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 -Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 -Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 -Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 -Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 -Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 -Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 -Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 -Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 -Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 -Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 -Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 -Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 -Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 -Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 -Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 -Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 -Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 -Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 -Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 -Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 -Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 -Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 -Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 -Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 -Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 -Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 -Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 -Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 -Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 -Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 -Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 -Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 -Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 -Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 -Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 -Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 -Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 -Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 -Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 -Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 -Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 -Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 -Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 -Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 -Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 -Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 -Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 -Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 -Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 -Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd -*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* INPUT : data_2 -* INPUT : data_3 -* INPUT : data_4 -* INPUT : data_5 -* INPUT : data_6 -* INPUT : data_7 -* INPUT : data_8 -* INPUT : data_9 -* INPUT : data_10 -* INPUT : data_11 -* INPUT : data_12 -* INPUT : data_13 -* INPUT : data_14 -* INPUT : data_15 -* INPUT : data_16 -* INPUT : data_17 -* INPUT : data_18 -* INPUT : data_19 -* INPUT : data_20 -* INPUT : data_21 -* INPUT : data_22 -* INPUT : data_23 -* INPUT : data_24 -* INPUT : data_25 -* INPUT : data_26 -* INPUT : data_27 -* INPUT : data_28 -* INPUT : data_29 -* INPUT : data_30 -* INPUT : data_31 -* INPUT : data_32 -* INPUT : data_33 -* INPUT : data_34 -* INPUT : data_35 -* INPUT : data_36 -* INPUT : data_37 -* INPUT : data_38 -* INPUT : data_39 -* INPUT : data_40 -* INPUT : data_41 -* INPUT : data_42 -* INPUT : data_43 -* INPUT : data_44 -* INPUT : data_45 -* INPUT : data_46 -* INPUT : data_47 -* INPUT : data_48 -* INPUT : data_49 -* INPUT : data_50 -* INPUT : data_51 -* INPUT : data_52 -* INPUT : data_53 -* INPUT : data_54 -* INPUT : data_55 -* INPUT : data_56 -* INPUT : data_57 -* INPUT : data_58 -* INPUT : data_59 -* INPUT : data_60 -* INPUT : data_61 -* INPUT : data_62 -* INPUT : data_63 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 64 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver -Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver -Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver -Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver -Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver -Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver -Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver -Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver -Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver -Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver -Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver -Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver -Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver -Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver -Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver -Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver -Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver -Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver -Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver -Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver -Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver -Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver -Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver -Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver -Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver -Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver -Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver -Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver -Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver -Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver -Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver -Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver -Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver -Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver -Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver -Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver -Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver -Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver -Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver -Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver -Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver -Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver -Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver -Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver -Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver -Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver -Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver -Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver -Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver -Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver -Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver -Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver -Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver -Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver -Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver -Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver -Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver -Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver -Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver -Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver -Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver -Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver -Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver -.ENDS write_driver_array - -* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -.SUBCKT column_mux bl br bl_out br_out sel gnd -*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B -* INOUT : bl -* INOUT : br -* INOUT : bl_out -* INOUT : br_out -* INOUT : sel -* INOUT : gnd -Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -.ENDS column_mux - -.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd -*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* INOUT : sel_0 -* INOUT : sel_1 -* INOUT : bl_out_0 -* INOUT : br_out_0 -* INOUT : bl_out_1 -* INOUT : br_out_1 -* INOUT : bl_out_2 -* INOUT : br_out_2 -* INOUT : bl_out_3 -* INOUT : br_out_3 -* INOUT : bl_out_4 -* INOUT : br_out_4 -* INOUT : bl_out_5 -* INOUT : br_out_5 -* INOUT : bl_out_6 -* INOUT : br_out_6 -* INOUT : bl_out_7 -* INOUT : br_out_7 -* INOUT : bl_out_8 -* INOUT : br_out_8 -* INOUT : bl_out_9 -* INOUT : br_out_9 -* INOUT : bl_out_10 -* INOUT : br_out_10 -* INOUT : bl_out_11 -* INOUT : br_out_11 -* INOUT : bl_out_12 -* INOUT : br_out_12 -* INOUT : bl_out_13 -* INOUT : br_out_13 -* INOUT : bl_out_14 -* INOUT : br_out_14 -* INOUT : bl_out_15 -* INOUT : br_out_15 -* INOUT : bl_out_16 -* INOUT : br_out_16 -* INOUT : bl_out_17 -* INOUT : br_out_17 -* INOUT : bl_out_18 -* INOUT : br_out_18 -* INOUT : bl_out_19 -* INOUT : br_out_19 -* INOUT : bl_out_20 -* INOUT : br_out_20 -* INOUT : bl_out_21 -* INOUT : br_out_21 -* INOUT : bl_out_22 -* INOUT : br_out_22 -* INOUT : bl_out_23 -* INOUT : br_out_23 -* INOUT : bl_out_24 -* INOUT : br_out_24 -* INOUT : bl_out_25 -* INOUT : br_out_25 -* INOUT : bl_out_26 -* INOUT : br_out_26 -* INOUT : bl_out_27 -* INOUT : br_out_27 -* INOUT : bl_out_28 -* INOUT : br_out_28 -* INOUT : bl_out_29 -* INOUT : br_out_29 -* INOUT : bl_out_30 -* INOUT : br_out_30 -* INOUT : bl_out_31 -* INOUT : br_out_31 -* INOUT : bl_out_32 -* INOUT : br_out_32 -* INOUT : bl_out_33 -* INOUT : br_out_33 -* INOUT : bl_out_34 -* INOUT : br_out_34 -* INOUT : bl_out_35 -* INOUT : br_out_35 -* INOUT : bl_out_36 -* INOUT : br_out_36 -* INOUT : bl_out_37 -* INOUT : br_out_37 -* INOUT : bl_out_38 -* INOUT : br_out_38 -* INOUT : bl_out_39 -* INOUT : br_out_39 -* INOUT : bl_out_40 -* INOUT : br_out_40 -* INOUT : bl_out_41 -* INOUT : br_out_41 -* INOUT : bl_out_42 -* INOUT : br_out_42 -* INOUT : bl_out_43 -* INOUT : br_out_43 -* INOUT : bl_out_44 -* INOUT : br_out_44 -* INOUT : bl_out_45 -* INOUT : br_out_45 -* INOUT : bl_out_46 -* INOUT : br_out_46 -* INOUT : bl_out_47 -* INOUT : br_out_47 -* INOUT : bl_out_48 -* INOUT : br_out_48 -* INOUT : bl_out_49 -* INOUT : br_out_49 -* INOUT : bl_out_50 -* INOUT : br_out_50 -* INOUT : bl_out_51 -* INOUT : br_out_51 -* INOUT : bl_out_52 -* INOUT : br_out_52 -* INOUT : bl_out_53 -* INOUT : br_out_53 -* INOUT : bl_out_54 -* INOUT : br_out_54 -* INOUT : bl_out_55 -* INOUT : br_out_55 -* INOUT : bl_out_56 -* INOUT : br_out_56 -* INOUT : bl_out_57 -* INOUT : br_out_57 -* INOUT : bl_out_58 -* INOUT : br_out_58 -* INOUT : bl_out_59 -* INOUT : br_out_59 -* INOUT : bl_out_60 -* INOUT : br_out_60 -* INOUT : bl_out_61 -* INOUT : br_out_61 -* INOUT : bl_out_62 -* INOUT : br_out_62 -* INOUT : bl_out_63 -* INOUT : br_out_63 -* INOUT : gnd -* cols: 128 word_size: 64 bl: bl br: br -XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux -XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux -XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux -XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux -XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux -XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux -XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux -XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux -XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux -XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux -XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux -XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux -XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux -XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux -XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux -XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux -XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux -XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux -XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux -XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux -XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux -XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux -XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux -XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux -XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux -XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux -XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux -XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux -XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux -XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux -XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux -XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux -XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux -XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux -XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux -XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux -XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux -XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux -XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux -XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux -XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux -XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux -XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux -XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux -XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux -XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux -XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux -XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux -XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux -XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux -XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux -XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux -XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux -XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux -XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux -XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux -XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux -XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux -XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux -XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux -XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux -XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux -XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux -XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux -XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux -XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux -XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux -XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux -XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux -XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux -XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux -XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux -XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux -XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux -XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux -XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux -XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux -XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux -XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux -XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux -XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux -XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux -XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux -XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux -XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux -XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux -XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux -XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux -XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux -XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux -XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux -XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux -XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux -XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux -XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux -XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux -XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux -XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux -XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux -XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux -XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux -XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux -XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux -XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux -XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux -XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux -XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux -XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux -XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux -XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux -XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux -XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux -XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux -XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux -XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux -XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux -XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux -XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux -XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux -XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux -XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux -XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux -XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux -XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux -XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux -XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux -XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux -XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux -.ENDS column_mux_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* INPUT : sel_0 -* INPUT : sel_1 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array -Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2 - -* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p -.ENDS pinv_0 - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 32 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv_0 -.ENDS and2_dec_0 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv_0 -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* INPUT : in_16 -* INPUT : in_17 -* INPUT : in_18 -* INPUT : in_19 -* INPUT : in_20 -* INPUT : in_21 -* INPUT : in_22 -* INPUT : in_23 -* INPUT : in_24 -* INPUT : in_25 -* INPUT : in_26 -* INPUT : in_27 -* INPUT : in_28 -* INPUT : in_29 -* INPUT : in_30 -* INPUT : in_31 -* INPUT : in_32 -* INPUT : in_33 -* INPUT : in_34 -* INPUT : in_35 -* INPUT : in_36 -* INPUT : in_37 -* INPUT : in_38 -* INPUT : in_39 -* INPUT : in_40 -* INPUT : in_41 -* INPUT : in_42 -* INPUT : in_43 -* INPUT : in_44 -* INPUT : in_45 -* INPUT : in_46 -* INPUT : in_47 -* INPUT : in_48 -* INPUT : in_49 -* INPUT : in_50 -* INPUT : in_51 -* INPUT : in_52 -* INPUT : in_53 -* INPUT : in_54 -* INPUT : in_55 -* INPUT : in_56 -* INPUT : in_57 -* INPUT : in_58 -* INPUT : in_59 -* INPUT : in_60 -* INPUT : in_61 -* INPUT : in_62 -* INPUT : in_63 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver -Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver -Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver -Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver -Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver -Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver -Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver -Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver -Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver -Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver -Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver -Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver -Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver -Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver -Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver -Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver -Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver -Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver -Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver -Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver -Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver -Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver -Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver -Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver -Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver -Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver -Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver -Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver -Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver -Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver -Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver -Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver -Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver -Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver -Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver -Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver -Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver -Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver -Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver -Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver -Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver -Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver -Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver -Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver -Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver -Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver -Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver -Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver -.ENDS wordline_driver_array - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3 - -.SUBCKT and3_dec A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand3_dec_nand A B C zb_int vdd gnd pnand3 -Xpand3_dec_inv zb_int Z vdd gnd pinv -.ENDS and3_dec - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* OUTPUT: decode_16 -* OUTPUT: decode_17 -* OUTPUT: decode_18 -* OUTPUT: decode_19 -* OUTPUT: decode_20 -* OUTPUT: decode_21 -* OUTPUT: decode_22 -* OUTPUT: decode_23 -* OUTPUT: decode_24 -* OUTPUT: decode_25 -* OUTPUT: decode_26 -* OUTPUT: decode_27 -* OUTPUT: decode_28 -* OUTPUT: decode_29 -* OUTPUT: decode_30 -* OUTPUT: decode_31 -* OUTPUT: decode_32 -* OUTPUT: decode_33 -* OUTPUT: decode_34 -* OUTPUT: decode_35 -* OUTPUT: decode_36 -* OUTPUT: decode_37 -* OUTPUT: decode_38 -* OUTPUT: decode_39 -* OUTPUT: decode_40 -* OUTPUT: decode_41 -* OUTPUT: decode_42 -* OUTPUT: decode_43 -* OUTPUT: decode_44 -* OUTPUT: decode_45 -* OUTPUT: decode_46 -* OUTPUT: decode_47 -* OUTPUT: decode_48 -* OUTPUT: decode_49 -* OUTPUT: decode_50 -* OUTPUT: decode_51 -* OUTPUT: decode_52 -* OUTPUT: decode_53 -* OUTPUT: decode_54 -* OUTPUT: decode_55 -* OUTPUT: decode_56 -* OUTPUT: decode_57 -* OUTPUT: decode_58 -* OUTPUT: decode_59 -* OUTPUT: decode_60 -* OUTPUT: decode_61 -* OUTPUT: decode_62 -* OUTPUT: decode_63 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 -Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 -XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec -XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec -XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec -XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec -XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec -XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec -XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec -XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec -XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec -XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec -XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec -XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec -XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec -XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec -XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec -XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec -XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec -XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec -XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec -XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec -XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec -XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec -XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec -XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec -XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec -XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec -XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec -XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec -XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec -XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec -XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec -XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec -XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec -XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec -XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec -XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec -XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec -XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec -XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec -XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec -XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec -XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec -XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec -XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec -XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec -XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec -XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec -XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec -XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec -XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec -XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec -XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec -XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec -XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec -XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec -XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec -XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec -XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec -XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec -XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec -XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec -XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec -XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec -XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec -.ENDS hierarchical_decoder - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: dout0_2 -* OUTPUT: dout0_3 -* OUTPUT: dout0_4 -* OUTPUT: dout0_5 -* OUTPUT: dout0_6 -* OUTPUT: dout0_7 -* OUTPUT: dout0_8 -* OUTPUT: dout0_9 -* OUTPUT: dout0_10 -* OUTPUT: dout0_11 -* OUTPUT: dout0_12 -* OUTPUT: dout0_13 -* OUTPUT: dout0_14 -* OUTPUT: dout0_15 -* OUTPUT: dout0_16 -* OUTPUT: dout0_17 -* OUTPUT: dout0_18 -* OUTPUT: dout0_19 -* OUTPUT: dout0_20 -* OUTPUT: dout0_21 -* OUTPUT: dout0_22 -* OUTPUT: dout0_23 -* OUTPUT: dout0_24 -* OUTPUT: dout0_25 -* OUTPUT: dout0_26 -* OUTPUT: dout0_27 -* OUTPUT: dout0_28 -* OUTPUT: dout0_29 -* OUTPUT: dout0_30 -* OUTPUT: dout0_31 -* OUTPUT: dout0_32 -* OUTPUT: dout0_33 -* OUTPUT: dout0_34 -* OUTPUT: dout0_35 -* OUTPUT: dout0_36 -* OUTPUT: dout0_37 -* OUTPUT: dout0_38 -* OUTPUT: dout0_39 -* OUTPUT: dout0_40 -* OUTPUT: dout0_41 -* OUTPUT: dout0_42 -* OUTPUT: dout0_43 -* OUTPUT: dout0_44 -* OUTPUT: dout0_45 -* OUTPUT: dout0_46 -* OUTPUT: dout0_47 -* OUTPUT: dout0_48 -* OUTPUT: dout0_49 -* OUTPUT: dout0_50 -* OUTPUT: dout0_51 -* OUTPUT: dout0_52 -* OUTPUT: dout0_53 -* OUTPUT: dout0_54 -* OUTPUT: dout0_55 -* OUTPUT: dout0_56 -* OUTPUT: dout0_57 -* OUTPUT: dout0_58 -* OUTPUT: dout0_59 -* OUTPUT: dout0_60 -* OUTPUT: dout0_61 -* OUTPUT: dout0_62 -* OUTPUT: dout0_63 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : din0_2 -* INPUT : din0_3 -* INPUT : din0_4 -* INPUT : din0_5 -* INPUT : din0_6 -* INPUT : din0_7 -* INPUT : din0_8 -* INPUT : din0_9 -* INPUT : din0_10 -* INPUT : din0_11 -* INPUT : din0_12 -* INPUT : din0_13 -* INPUT : din0_14 -* INPUT : din0_15 -* INPUT : din0_16 -* INPUT : din0_17 -* INPUT : din0_18 -* INPUT : din0_19 -* INPUT : din0_20 -* INPUT : din0_21 -* INPUT : din0_22 -* INPUT : din0_23 -* INPUT : din0_24 -* INPUT : din0_25 -* INPUT : din0_26 -* INPUT : din0_27 -* INPUT : din0_28 -* INPUT : din0_29 -* INPUT : din0_30 -* INPUT : din0_31 -* INPUT : din0_32 -* INPUT : din0_33 -* INPUT : din0_34 -* INPUT : din0_35 -* INPUT : din0_36 -* INPUT : din0_37 -* INPUT : din0_38 -* INPUT : din0_39 -* INPUT : din0_40 -* INPUT : din0_41 -* INPUT : din0_42 -* INPUT : din0_43 -* INPUT : din0_44 -* INPUT : din0_45 -* INPUT : din0_46 -* INPUT : din0_47 -* INPUT : din0_48 -* INPUT : din0_49 -* INPUT : din0_50 -* INPUT : din0_51 -* INPUT : din0_52 -* INPUT : din0_53 -* INPUT : din0_54 -* INPUT : din0_55 -* INPUT : din0_56 -* INPUT : din0_57 -* INPUT : din0_58 -* INPUT : din0_59 -* INPUT : din0_60 -* INPUT : din0_61 -* INPUT : din0_62 -* INPUT : din0_63 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : addr0_4 -* INPUT : addr0_5 -* INPUT : addr0_6 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address -Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf -.ENDS bank - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_2 -Xdff_buf_inv2 Qb Q vdd gnd pinv_3 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_0 - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -.SUBCKT pinv_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p -.ENDS pinv_4 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_4 -.ENDS pdriver - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p -Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p -.ENDS pinv_11 - -* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p -.ENDS pinv_9 - -* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p -Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -.ENDS pinv_10 - -* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p - -* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p - -.SUBCKT pinv_12 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p -Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p -.ENDS pinv_12 - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_7 - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_8 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 1, 2, 5, 14, 42, 125] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 -Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 -Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 -Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 -.ENDS pdriver_0 - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3_0 - -* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p - -* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -.SUBCKT pinv_16 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p -Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -.ENDS pinv_16 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [64] -Xbuf_inv1 A Z vdd gnd pinv_16 -.ENDS pdriver_3 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -.SUBCKT pinv_17 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_17 - -* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p - -* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p - -.SUBCKT pinv_18 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p -Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p -.ENDS pinv_18 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 2, 5, 14, 43] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 -Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 -.ENDS pdriver_4 - -* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p - -* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p - -.SUBCKT pinv_15 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p -Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p -.ENDS pinv_15 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [72] -Xbuf_inv1 A Z vdd gnd pinv_15 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT pinv_19 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_19 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_19 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 -Xdinv1 dout_1 dout_2 vdd gnd pinv_19 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 -Xdinv2 dout_2 dout_3 vdd gnd pinv_19 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 -Xdinv3 dout_3 dout_4 vdd gnd pinv_19 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 -Xdinv4 dout_4 dout_5 vdd gnd pinv_19 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 -Xdinv5 dout_5 dout_6 vdd gnd pinv_19 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 -Xdinv6 dout_6 dout_7 vdd gnd pinv_19 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 -Xdinv7 dout_7 dout_8 vdd gnd pinv_19 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 -Xdinv8 dout_8 out vdd gnd pinv_19 -Xdload_8_0 out n_8_0 vdd gnd pinv_19 -Xdload_8_1 out n_8_1 vdd gnd pinv_19 -Xdload_8_2 out n_8_2 vdd gnd pinv_19 -Xdload_8_3 out n_8_3 vdd gnd pinv_19 -.ENDS delay_chain - -* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p - -.SUBCKT pinv_14 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p -Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p -.ENDS pinv_14 - -* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p - -.SUBCKT pinv_13 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p -.ENDS pinv_13 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [7, 21] -Xbuf_inv1 A Zb1_int vdd gnd pinv_13 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 -.ENDS pdriver_1 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_1 - -* Used for tiling delay chain to desired length -.SUBCKT delay_chain_segment in out vdd gnd -Xdinv0 in dout_1 vdd gnd pinv_11 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 -Xdinv1 dout_1 out vdd gnd pinv_11 -Xdload_1_0 out n_1_0 vdd gnd pinv_11 -Xdload_1_1 out n_1_1 vdd gnd pinv_11 -Xdload_1_2 out n_1_2 vdd gnd pinv_11 -Xdload_1_3 out n_1_3 vdd gnd pinv_11 -.ENDS delay_chain_segment - -.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd -Xdelay1 in out1 vdd gnd delay_chain_segment -Xdelay2 out1 out2 vdd gnd delay_chain_segment -Xdelay3 out2 out3 vdd gnd delay_chain_segment -Xdelay4 out3 out4 vdd gnd delay_chain_segment -Xdelay5 out4 out5 vdd gnd delay_chain_segment -Xdelay6 out5 out6 vdd gnd delay_chain_segment -Xdelay7 out6 out7 vdd gnd delay_chain_segment -Xdelay8 out7 out8 vdd gnd delay_chain_segment -Xdelay9 out8 out9 vdd gnd delay_chain_segment -Xdelay10 out9 out10 vdd gnd delay_chain_segment -Xdelay11 out10 out11 vdd gnd delay_chain_segment -Xdelay12 out11 out12 vdd gnd delay_chain_segment -Xdelay13 out12 out13 vdd gnd delay_chain_segment -Xdelay14 out13 out14 vdd gnd delay_chain_segment -Xdelay15 out14 out15 vdd gnd delay_chain_segment -Xdelay16 out15 out16 vdd gnd delay_chain_segment -.ENDS multi_delay_chain - -.SUBCKT glitch_generator in glitch1_bar glitch2_bar glitch3_bar vdd gnd -*.PININFO in:I glitch1_bar:O glitch2_bar:O glitch3_bar:O vdd:B gnd:B -Xmulti_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain -Xinv_g1 out6 g1_end vdd gnd pinv_11 -Xinv_g2 out7 g2_end vdd gnd pinv_11 -Xinv_g3 out14 g3_end vdd gnd pinv_11 -Xnand2_g1 out1 g1_end glitch1_bar vdd gnd pnand2 -Xnand2_g2 in g2_end glitch2_bar vdd gnd pnand2 -Xnand2_g3 out6 g3_end glitch3_bar vdd gnd pnand2 -.ENDS glitch_generator - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl (NO LONGER USED) -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -* is cs_buf needed on larger memories? -Xbuf_cs cs cs_buf vdd gnd pdriver_0 -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xglitch_generator gated_clk_buf glitch1_bar glitch2_bar glitch3_bar vdd gnd glitch_generator -Xinv_g3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 -Xinv_pre_s glitch3_buf pre_s vdd gnd pinv_11 -Xand_s_en we_bar gated_clk_bar pre_s s_en vdd gnd pand3 -Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 -Xand_wl_en cs_buf glitch2_bar wl_en vdd gnd pand2 -Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd -*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : din0[2] -* INPUT : din0[3] -* INPUT : din0[4] -* INPUT : din0[5] -* INPUT : din0[6] -* INPUT : din0[7] -* INPUT : din0[8] -* INPUT : din0[9] -* INPUT : din0[10] -* INPUT : din0[11] -* INPUT : din0[12] -* INPUT : din0[13] -* INPUT : din0[14] -* INPUT : din0[15] -* INPUT : din0[16] -* INPUT : din0[17] -* INPUT : din0[18] -* INPUT : din0[19] -* INPUT : din0[20] -* INPUT : din0[21] -* INPUT : din0[22] -* INPUT : din0[23] -* INPUT : din0[24] -* INPUT : din0[25] -* INPUT : din0[26] -* INPUT : din0[27] -* INPUT : din0[28] -* INPUT : din0[29] -* INPUT : din0[30] -* INPUT : din0[31] -* INPUT : din0[32] -* INPUT : din0[33] -* INPUT : din0[34] -* INPUT : din0[35] -* INPUT : din0[36] -* INPUT : din0[37] -* INPUT : din0[38] -* INPUT : din0[39] -* INPUT : din0[40] -* INPUT : din0[41] -* INPUT : din0[42] -* INPUT : din0[43] -* INPUT : din0[44] -* INPUT : din0[45] -* INPUT : din0[46] -* INPUT : din0[47] -* INPUT : din0[48] -* INPUT : din0[49] -* INPUT : din0[50] -* INPUT : din0[51] -* INPUT : din0[52] -* INPUT : din0[53] -* INPUT : din0[54] -* INPUT : din0[55] -* INPUT : din0[56] -* INPUT : din0[57] -* INPUT : din0[58] -* INPUT : din0[59] -* INPUT : din0[60] -* INPUT : din0[61] -* INPUT : din0[62] -* INPUT : din0[63] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : addr0[4] -* INPUT : addr0[5] -* INPUT : addr0[6] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* OUTPUT: dout0[2] -* OUTPUT: dout0[3] -* OUTPUT: dout0[4] -* OUTPUT: dout0[5] -* OUTPUT: dout0[6] -* OUTPUT: dout0[7] -* OUTPUT: dout0[8] -* OUTPUT: dout0[9] -* OUTPUT: dout0[10] -* OUTPUT: dout0[11] -* OUTPUT: dout0[12] -* OUTPUT: dout0[13] -* OUTPUT: dout0[14] -* OUTPUT: dout0[15] -* OUTPUT: dout0[16] -* OUTPUT: dout0[17] -* OUTPUT: dout0[18] -* OUTPUT: dout0[19] -* OUTPUT: dout0[20] -* OUTPUT: dout0[21] -* OUTPUT: dout0[22] -* OUTPUT: dout0[23] -* OUTPUT: dout0[24] -* OUTPUT: dout0[25] -* OUTPUT: dout0[26] -* OUTPUT: dout0[27] -* OUTPUT: dout0[28] -* OUTPUT: dout0[29] -* OUTPUT: dout0[30] -* OUTPUT: dout0[31] -* OUTPUT: dout0[32] -* OUTPUT: dout0[33] -* OUTPUT: dout0[34] -* OUTPUT: dout0[35] -* OUTPUT: dout0[36] -* OUTPUT: dout0[37] -* OUTPUT: dout0[38] -* OUTPUT: dout0[39] -* OUTPUT: dout0[40] -* OUTPUT: dout0[41] -* OUTPUT: dout0[42] -* OUTPUT: dout0[43] -* OUTPUT: dout0[44] -* OUTPUT: dout0[45] -* OUTPUT: dout0[46] -* OUTPUT: dout0[47] -* OUTPUT: dout0[48] -* OUTPUT: dout0[49] -* OUTPUT: dout0[50] -* OUTPUT: dout0[51] -* OUTPUT: dout0[52] -* OUTPUT: dout0[53] -* OUTPUT: dout0[54] -* OUTPUT: dout0[55] -* OUTPUT: dout0[56] -* OUTPUT: dout0[57] -* OUTPUT: dout0[58] -* OUTPUT: dout0[59] -* OUTPUT: dout0[60] -* OUTPUT: dout0[61] -* OUTPUT: dout0[62] -* OUTPUT: dout0[63] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff -Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff -Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff -.ENDS sram_64_128_scn4m_subm diff --git a/1KB/sram_64_128_scn4m_subm.html b/1KB/sram_64_128_scn4m_subm.html deleted file mode 100644 index 0d27ecf0..00000000 --- a/1KB/sram_64_128_scn4m_subm.html +++ /dev/null @@ -1,35 +0,0 @@ - - -VLSIDAOpenRAM

sram_64_128_scn4m_subm.html

Compiled at: 2022-01-27

DRC errors: skipped

LVS errors: skipped

Git commit id: 06d391b3e365127628434b98044035232615f4b0

Ports and Configuration

TypeValue
WORD_SIZE64
NUM_WORDS128
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0
-

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)122MHz
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Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[63:0] setup rising0.0090.009ns
din0[63:0] setup falling0.0090.009ns
din0[63:0] hold rising0.0010.001ns
din0[63:0] hold falling0.0010.001ns
dout0[63:0] cell rise2.1252.215ns
dout0[63:0] cell fall2.1252.215ns
dout0[63:0] rise transition0.0060.015ns
dout0[63:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[6:0] setup rising0.0090.009ns
addr0[6:0] setup falling0.0090.009ns
addr0[6:0] hold rising0.0010.001ns
addr0[6:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns
-

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising13.524mW
!csb0 & clk0 & !web0Read Falling13.524mW
!csb0 & !clk0 & web0Write Rising13.524mW
!csb0 & !clk0 & web0Write Falling13.524mW
csb0leakage0.008633mW
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Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib
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Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_64_128_scn4m_subm.html
.libSynthesis modelssram_64_128_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_64_128_scn4m_subm.log
.pyOpenRAM configuration filesram_64_128_scn4m_subm.py
.spSPICE netlistssram_64_128_scn4m_subm.sp
.vVerilog simulation modelssram_64_128_scn4m_subm.v
diff --git a/1KB/sram_64_128_scn4m_subm.lvs.sp b/1KB/sram_64_128_scn4m_subm.lvs.sp deleted file mode 100644 index 8eab54dd..00000000 --- a/1KB/sram_64_128_scn4m_subm.lvs.sp +++ /dev/null @@ -1,14050 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 128 -* Data bits: 64 -* Banks: 1 -* Column mux: 2:1 -* Trimmed: False -* LVS: True -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 6 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff -Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff -.ENDS row_addr_dff - -.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd -*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B -* INPUT : din_0 -* OUTPUT: dout_0 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -.ENDS col_addr_dff - -.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 64 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff -Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff -Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff -Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff -Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff -Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff -Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff -Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff -Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff -Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff -Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff -Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff -Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff -Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff -Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff -Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff -Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff -Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff -Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff -Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff -Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff -Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff -Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff -Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff -Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff -Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff -Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff -Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff -Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff -Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff -Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff -Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff -Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff -Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff -Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff -Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff -Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff -Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff -Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff -Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff -Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff -Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff -Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff -Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff -Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff -Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff -Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff -Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff -Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff -Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff -Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff -Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff -Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff -Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff -Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff -Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff -Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff -Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff -Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff -Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff -Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff -Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff -.ENDS data_dff - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pinv_2 - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u -.ENDS pinv_3 - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_1 - -.SUBCKT pinvbuf A Zb Z vdd gnd -*.PININFO A:B Zb:B Z:B vdd:B gnd:B -* INOUT : A -* INOUT : Zb -* INOUT : Z -* INOUT : vdd -* INOUT : gnd -Xbuf_inv1 A zb_int vdd gnd pinv_1 -Xbuf_inv2 zb_int z_int vdd gnd pinv_2 -Xbuf_inv3 z_int Zb vdd gnd pinv_3 -Xbuf_inv4 zb_int Z vdd gnd pinv_3 -.ENDS pinvbuf - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw -Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw -Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw -Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw -Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw -Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw -Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw -Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw -Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw -Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw -Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw -Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw -Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw -Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw -Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw -Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw -Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw -Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw -Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw -Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw -Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw -Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw -Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw -Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw -Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw -Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw -Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw -Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw -Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw -Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw -Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw -Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw -Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw -Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw -Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw -Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw -Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw -Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw -Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw -Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw -Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw -Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw -Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw -Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw -Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw -Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw -Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw -Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw -Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c15 bl_0_15 br_0_15 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c15 bl_0_15 br_0_15 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c15 bl_0_15 br_0_15 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c15 bl_0_15 br_0_15 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c15 bl_0_15 br_0_15 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c15 bl_0_15 br_0_15 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c15 bl_0_15 br_0_15 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c15 bl_0_15 br_0_15 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c15 bl_0_15 br_0_15 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c15 bl_0_15 br_0_15 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c15 bl_0_15 br_0_15 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c15 bl_0_15 br_0_15 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c15 bl_0_15 br_0_15 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c44 bl_0_44 br_0_44 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c44 bl_0_44 br_0_44 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c44 bl_0_44 br_0_44 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c44 bl_0_44 br_0_44 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c44 bl_0_44 br_0_44 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c44 bl_0_44 br_0_44 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c44 bl_0_44 br_0_44 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c44 bl_0_44 br_0_44 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c44 bl_0_44 br_0_44 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c44 bl_0_44 br_0_44 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c44 bl_0_44 br_0_44 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c44 bl_0_44 br_0_44 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c44 bl_0_44 br_0_44 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c44 bl_0_44 br_0_44 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c44 bl_0_44 br_0_44 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c44 bl_0_44 br_0_44 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c44 bl_0_44 br_0_44 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c44 bl_0_44 br_0_44 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c49 bl_0_49 br_0_49 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c49 bl_0_49 br_0_49 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c49 bl_0_49 br_0_49 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c49 bl_0_49 br_0_49 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c49 bl_0_49 br_0_49 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c49 bl_0_49 br_0_49 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c49 bl_0_49 br_0_49 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c49 bl_0_49 br_0_49 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c49 bl_0_49 br_0_49 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c49 bl_0_49 br_0_49 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c49 bl_0_49 br_0_49 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c49 bl_0_49 br_0_49 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c49 bl_0_49 br_0_49 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c49 bl_0_49 br_0_49 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c49 bl_0_49 br_0_49 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c49 bl_0_49 br_0_49 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c49 bl_0_49 br_0_49 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c49 bl_0_49 br_0_49 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c52 bl_0_52 br_0_52 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c52 bl_0_52 br_0_52 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c52 bl_0_52 br_0_52 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c52 bl_0_52 br_0_52 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c52 bl_0_52 br_0_52 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c52 bl_0_52 br_0_52 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c52 bl_0_52 br_0_52 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c52 bl_0_52 br_0_52 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c52 bl_0_52 br_0_52 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c52 bl_0_52 br_0_52 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c52 bl_0_52 br_0_52 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c53 bl_0_53 br_0_53 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c53 bl_0_53 br_0_53 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c53 bl_0_53 br_0_53 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c53 bl_0_53 br_0_53 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c53 bl_0_53 br_0_53 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c53 bl_0_53 br_0_53 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c53 bl_0_53 br_0_53 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c53 bl_0_53 br_0_53 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c53 bl_0_53 br_0_53 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c53 bl_0_53 br_0_53 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c53 bl_0_53 br_0_53 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c53 bl_0_53 br_0_53 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c53 bl_0_53 br_0_53 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c53 bl_0_53 br_0_53 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c53 bl_0_53 br_0_53 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c53 bl_0_53 br_0_53 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c53 bl_0_53 br_0_53 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c53 bl_0_53 br_0_53 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c53 bl_0_53 br_0_53 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c53 bl_0_53 br_0_53 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c53 bl_0_53 br_0_53 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c53 bl_0_53 br_0_53 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c53 bl_0_53 br_0_53 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c53 bl_0_53 br_0_53 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c53 bl_0_53 br_0_53 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c53 bl_0_53 br_0_53 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c53 bl_0_53 br_0_53 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c53 bl_0_53 br_0_53 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c53 bl_0_53 br_0_53 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c53 bl_0_53 br_0_53 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c53 bl_0_53 br_0_53 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c53 bl_0_53 br_0_53 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c53 bl_0_53 br_0_53 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c53 bl_0_53 br_0_53 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c53 bl_0_53 br_0_53 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c53 bl_0_53 br_0_53 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c53 bl_0_53 br_0_53 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c53 bl_0_53 br_0_53 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c53 bl_0_53 br_0_53 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c53 bl_0_53 br_0_53 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c53 bl_0_53 br_0_53 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c53 bl_0_53 br_0_53 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c53 bl_0_53 br_0_53 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c59 bl_0_59 br_0_59 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c59 bl_0_59 br_0_59 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c59 bl_0_59 br_0_59 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c60 bl_0_60 br_0_60 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c60 bl_0_60 br_0_60 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c60 bl_0_60 br_0_60 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c60 bl_0_60 br_0_60 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c60 bl_0_60 br_0_60 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c60 bl_0_60 br_0_60 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c60 bl_0_60 br_0_60 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c60 bl_0_60 br_0_60 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c60 bl_0_60 br_0_60 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c60 bl_0_60 br_0_60 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c60 bl_0_60 br_0_60 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c60 bl_0_60 br_0_60 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c60 bl_0_60 br_0_60 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c60 bl_0_60 br_0_60 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c60 bl_0_60 br_0_60 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c73 bl_0_73 br_0_73 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c73 bl_0_73 br_0_73 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c73 bl_0_73 br_0_73 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c73 bl_0_73 br_0_73 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c73 bl_0_73 br_0_73 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c73 bl_0_73 br_0_73 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c73 bl_0_73 br_0_73 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c73 bl_0_73 br_0_73 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c73 bl_0_73 br_0_73 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c73 bl_0_73 br_0_73 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c73 bl_0_73 br_0_73 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c73 bl_0_73 br_0_73 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c73 bl_0_73 br_0_73 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c73 bl_0_73 br_0_73 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c73 bl_0_73 br_0_73 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c73 bl_0_73 br_0_73 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c73 bl_0_73 br_0_73 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c73 bl_0_73 br_0_73 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c74 bl_0_74 br_0_74 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c74 bl_0_74 br_0_74 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c74 bl_0_74 br_0_74 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c74 bl_0_74 br_0_74 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c74 bl_0_74 br_0_74 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c74 bl_0_74 br_0_74 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c74 bl_0_74 br_0_74 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c74 bl_0_74 br_0_74 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c74 bl_0_74 br_0_74 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c74 bl_0_74 br_0_74 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c74 bl_0_74 br_0_74 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c74 bl_0_74 br_0_74 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c74 bl_0_74 br_0_74 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c74 bl_0_74 br_0_74 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c74 bl_0_74 br_0_74 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c74 bl_0_74 br_0_74 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c74 bl_0_74 br_0_74 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c74 bl_0_74 br_0_74 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c74 bl_0_74 br_0_74 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c74 bl_0_74 br_0_74 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c74 bl_0_74 br_0_74 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c74 bl_0_74 br_0_74 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c74 bl_0_74 br_0_74 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c74 bl_0_74 br_0_74 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c74 bl_0_74 br_0_74 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c74 bl_0_74 br_0_74 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c74 bl_0_74 br_0_74 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c74 bl_0_74 br_0_74 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c74 bl_0_74 br_0_74 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c74 bl_0_74 br_0_74 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c74 bl_0_74 br_0_74 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c74 bl_0_74 br_0_74 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c74 bl_0_74 br_0_74 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c75 bl_0_75 br_0_75 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c75 bl_0_75 br_0_75 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c75 bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c75 bl_0_75 br_0_75 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c75 bl_0_75 br_0_75 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c75 bl_0_75 br_0_75 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c75 bl_0_75 br_0_75 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c75 bl_0_75 br_0_75 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c75 bl_0_75 br_0_75 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c76 bl_0_76 br_0_76 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c76 bl_0_76 br_0_76 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c76 bl_0_76 br_0_76 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c76 bl_0_76 br_0_76 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c76 bl_0_76 br_0_76 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c76 bl_0_76 br_0_76 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c76 bl_0_76 br_0_76 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c76 bl_0_76 br_0_76 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c76 bl_0_76 br_0_76 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c76 bl_0_76 br_0_76 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c76 bl_0_76 br_0_76 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c76 bl_0_76 br_0_76 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c81 bl_0_81 br_0_81 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c81 bl_0_81 br_0_81 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c81 bl_0_81 br_0_81 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c81 bl_0_81 br_0_81 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c81 bl_0_81 br_0_81 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c81 bl_0_81 br_0_81 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c81 bl_0_81 br_0_81 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c82 bl_0_82 br_0_82 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c82 bl_0_82 br_0_82 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c82 bl_0_82 br_0_82 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c82 bl_0_82 br_0_82 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c82 bl_0_82 br_0_82 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c82 bl_0_82 br_0_82 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c82 bl_0_82 br_0_82 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c82 bl_0_82 br_0_82 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c82 bl_0_82 br_0_82 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c82 bl_0_82 br_0_82 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c82 bl_0_82 br_0_82 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c83 bl_0_83 br_0_83 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c83 bl_0_83 br_0_83 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c84 bl_0_84 br_0_84 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c84 bl_0_84 br_0_84 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c84 bl_0_84 br_0_84 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c84 bl_0_84 br_0_84 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c84 bl_0_84 br_0_84 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c84 bl_0_84 br_0_84 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c84 bl_0_84 br_0_84 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c84 bl_0_84 br_0_84 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c84 bl_0_84 br_0_84 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c84 bl_0_84 br_0_84 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c84 bl_0_84 br_0_84 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c84 bl_0_84 br_0_84 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c84 bl_0_84 br_0_84 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c84 bl_0_84 br_0_84 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c84 bl_0_84 br_0_84 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c84 bl_0_84 br_0_84 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c87 bl_0_87 br_0_87 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c87 bl_0_87 br_0_87 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c87 bl_0_87 br_0_87 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c87 bl_0_87 br_0_87 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c87 bl_0_87 br_0_87 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c87 bl_0_87 br_0_87 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c87 bl_0_87 br_0_87 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c87 bl_0_87 br_0_87 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c88 bl_0_88 br_0_88 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c88 bl_0_88 br_0_88 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c88 bl_0_88 br_0_88 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c88 bl_0_88 br_0_88 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c88 bl_0_88 br_0_88 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c88 bl_0_88 br_0_88 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c88 bl_0_88 br_0_88 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c88 bl_0_88 br_0_88 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c88 bl_0_88 br_0_88 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c88 bl_0_88 br_0_88 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c89 bl_0_89 br_0_89 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c89 bl_0_89 br_0_89 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c89 bl_0_89 br_0_89 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c90 bl_0_90 br_0_90 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c90 bl_0_90 br_0_90 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c90 bl_0_90 br_0_90 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c90 bl_0_90 br_0_90 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c90 bl_0_90 br_0_90 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c90 bl_0_90 br_0_90 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c90 bl_0_90 br_0_90 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c90 bl_0_90 br_0_90 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c90 bl_0_90 br_0_90 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c90 bl_0_90 br_0_90 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c90 bl_0_90 br_0_90 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c90 bl_0_90 br_0_90 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c90 bl_0_90 br_0_90 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c90 bl_0_90 br_0_90 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c90 bl_0_90 br_0_90 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c96 bl_0_96 br_0_96 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c96 bl_0_96 br_0_96 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c96 bl_0_96 br_0_96 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c96 bl_0_96 br_0_96 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c96 bl_0_96 br_0_96 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c96 bl_0_96 br_0_96 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c96 bl_0_96 br_0_96 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c96 bl_0_96 br_0_96 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c96 bl_0_96 br_0_96 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c96 bl_0_96 br_0_96 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c96 bl_0_96 br_0_96 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c96 bl_0_96 br_0_96 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c96 bl_0_96 br_0_96 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c96 bl_0_96 br_0_96 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c96 bl_0_96 br_0_96 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c96 bl_0_96 br_0_96 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c96 bl_0_96 br_0_96 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c96 bl_0_96 br_0_96 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c96 bl_0_96 br_0_96 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c97 bl_0_97 br_0_97 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c97 bl_0_97 br_0_97 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c97 bl_0_97 br_0_97 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c97 bl_0_97 br_0_97 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c97 bl_0_97 br_0_97 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c97 bl_0_97 br_0_97 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c97 bl_0_97 br_0_97 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c97 bl_0_97 br_0_97 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c97 bl_0_97 br_0_97 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c97 bl_0_97 br_0_97 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c97 bl_0_97 br_0_97 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c97 bl_0_97 br_0_97 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c97 bl_0_97 br_0_97 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c97 bl_0_97 br_0_97 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c97 bl_0_97 br_0_97 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c97 bl_0_97 br_0_97 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c97 bl_0_97 br_0_97 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c98 bl_0_98 br_0_98 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c98 bl_0_98 br_0_98 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c98 bl_0_98 br_0_98 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c98 bl_0_98 br_0_98 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c98 bl_0_98 br_0_98 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c98 bl_0_98 br_0_98 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c98 bl_0_98 br_0_98 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c98 bl_0_98 br_0_98 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c98 bl_0_98 br_0_98 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c98 bl_0_98 br_0_98 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c98 bl_0_98 br_0_98 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c98 bl_0_98 br_0_98 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c98 bl_0_98 br_0_98 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c98 bl_0_98 br_0_98 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c99 bl_0_99 br_0_99 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c99 bl_0_99 br_0_99 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c99 bl_0_99 br_0_99 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c99 bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c100 bl_0_100 br_0_100 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c100 bl_0_100 br_0_100 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c100 bl_0_100 br_0_100 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c100 bl_0_100 br_0_100 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c100 bl_0_100 br_0_100 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c100 bl_0_100 br_0_100 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c100 bl_0_100 br_0_100 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c100 bl_0_100 br_0_100 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c100 bl_0_100 br_0_100 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c100 bl_0_100 br_0_100 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c100 bl_0_100 br_0_100 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c100 bl_0_100 br_0_100 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c100 bl_0_100 br_0_100 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c100 bl_0_100 br_0_100 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c100 bl_0_100 br_0_100 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c100 bl_0_100 br_0_100 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c100 bl_0_100 br_0_100 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c108 bl_0_108 br_0_108 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c108 bl_0_108 br_0_108 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c108 bl_0_108 br_0_108 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c108 bl_0_108 br_0_108 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c108 bl_0_108 br_0_108 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c108 bl_0_108 br_0_108 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c108 bl_0_108 br_0_108 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c108 bl_0_108 br_0_108 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c108 bl_0_108 br_0_108 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c108 bl_0_108 br_0_108 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c108 bl_0_108 br_0_108 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c108 bl_0_108 br_0_108 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c108 bl_0_108 br_0_108 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c108 bl_0_108 br_0_108 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c108 bl_0_108 br_0_108 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c108 bl_0_108 br_0_108 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c108 bl_0_108 br_0_108 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c108 bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c110 bl_0_110 br_0_110 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c110 bl_0_110 br_0_110 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c110 bl_0_110 br_0_110 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c110 bl_0_110 br_0_110 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c110 bl_0_110 br_0_110 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c110 bl_0_110 br_0_110 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c110 bl_0_110 br_0_110 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c110 bl_0_110 br_0_110 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c110 bl_0_110 br_0_110 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c110 bl_0_110 br_0_110 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c110 bl_0_110 br_0_110 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c110 bl_0_110 br_0_110 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c110 bl_0_110 br_0_110 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c110 bl_0_110 br_0_110 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c110 bl_0_110 br_0_110 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c110 bl_0_110 br_0_110 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c110 bl_0_110 br_0_110 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c110 bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c111 bl_0_111 br_0_111 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c111 bl_0_111 br_0_111 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c111 bl_0_111 br_0_111 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c111 bl_0_111 br_0_111 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c111 bl_0_111 br_0_111 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c111 bl_0_111 br_0_111 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c111 bl_0_111 br_0_111 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c111 bl_0_111 br_0_111 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c111 bl_0_111 br_0_111 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c111 bl_0_111 br_0_111 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c111 bl_0_111 br_0_111 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c111 bl_0_111 br_0_111 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c111 bl_0_111 br_0_111 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c111 bl_0_111 br_0_111 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c111 bl_0_111 br_0_111 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c111 bl_0_111 br_0_111 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c111 bl_0_111 br_0_111 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c111 bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c112 bl_0_112 br_0_112 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c112 bl_0_112 br_0_112 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c112 bl_0_112 br_0_112 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c112 bl_0_112 br_0_112 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c112 bl_0_112 br_0_112 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c112 bl_0_112 br_0_112 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c112 bl_0_112 br_0_112 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c112 bl_0_112 br_0_112 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c112 bl_0_112 br_0_112 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c112 bl_0_112 br_0_112 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c112 bl_0_112 br_0_112 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c112 bl_0_112 br_0_112 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c112 bl_0_112 br_0_112 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c112 bl_0_112 br_0_112 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c112 bl_0_112 br_0_112 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c112 bl_0_112 br_0_112 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c112 bl_0_112 br_0_112 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c112 bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c114 bl_0_114 br_0_114 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c114 bl_0_114 br_0_114 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c114 bl_0_114 br_0_114 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c114 bl_0_114 br_0_114 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c114 bl_0_114 br_0_114 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c114 bl_0_114 br_0_114 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c114 bl_0_114 br_0_114 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c114 bl_0_114 br_0_114 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c114 bl_0_114 br_0_114 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c114 bl_0_114 br_0_114 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c114 bl_0_114 br_0_114 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c114 bl_0_114 br_0_114 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c114 bl_0_114 br_0_114 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c114 bl_0_114 br_0_114 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c114 bl_0_114 br_0_114 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c115 bl_0_115 br_0_115 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c115 bl_0_115 br_0_115 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c116 bl_0_116 br_0_116 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c116 bl_0_116 br_0_116 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c116 bl_0_116 br_0_116 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c116 bl_0_116 br_0_116 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c116 bl_0_116 br_0_116 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c116 bl_0_116 br_0_116 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c116 bl_0_116 br_0_116 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c116 bl_0_116 br_0_116 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c116 bl_0_116 br_0_116 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c116 bl_0_116 br_0_116 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c116 bl_0_116 br_0_116 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c116 bl_0_116 br_0_116 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c116 bl_0_116 br_0_116 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c116 bl_0_116 br_0_116 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c116 bl_0_116 br_0_116 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c116 bl_0_116 br_0_116 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c116 bl_0_116 br_0_116 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c116 bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c119 bl_0_119 br_0_119 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c119 bl_0_119 br_0_119 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c119 bl_0_119 br_0_119 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c119 bl_0_119 br_0_119 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c119 bl_0_119 br_0_119 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c119 bl_0_119 br_0_119 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c119 bl_0_119 br_0_119 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c119 bl_0_119 br_0_119 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c119 bl_0_119 br_0_119 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c119 bl_0_119 br_0_119 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c119 bl_0_119 br_0_119 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c119 bl_0_119 br_0_119 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c119 bl_0_119 br_0_119 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c119 bl_0_119 br_0_119 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c119 bl_0_119 br_0_119 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c119 bl_0_119 br_0_119 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c119 bl_0_119 br_0_119 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c119 bl_0_119 br_0_119 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c119 bl_0_119 br_0_119 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c119 bl_0_119 br_0_119 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c119 bl_0_119 br_0_119 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c119 bl_0_119 br_0_119 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c119 bl_0_119 br_0_119 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c119 bl_0_119 br_0_119 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c119 bl_0_119 br_0_119 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c119 bl_0_119 br_0_119 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c119 bl_0_119 br_0_119 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c119 bl_0_119 br_0_119 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c119 bl_0_119 br_0_119 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c119 bl_0_119 br_0_119 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c119 bl_0_119 br_0_119 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c119 bl_0_119 br_0_119 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c119 bl_0_119 br_0_119 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c119 bl_0_119 br_0_119 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c119 bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c120 bl_0_120 br_0_120 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c120 bl_0_120 br_0_120 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c120 bl_0_120 br_0_120 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c120 bl_0_120 br_0_120 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c120 bl_0_120 br_0_120 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c120 bl_0_120 br_0_120 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c120 bl_0_120 br_0_120 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c120 bl_0_120 br_0_120 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c120 bl_0_120 br_0_120 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c120 bl_0_120 br_0_120 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c120 bl_0_120 br_0_120 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c120 bl_0_120 br_0_120 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c120 bl_0_120 br_0_120 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c120 bl_0_120 br_0_120 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c120 bl_0_120 br_0_120 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c120 bl_0_120 br_0_120 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c120 bl_0_120 br_0_120 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c120 bl_0_120 br_0_120 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c120 bl_0_120 br_0_120 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c120 bl_0_120 br_0_120 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c120 bl_0_120 br_0_120 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c120 bl_0_120 br_0_120 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c120 bl_0_120 br_0_120 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c120 bl_0_120 br_0_120 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c120 bl_0_120 br_0_120 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c120 bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c121 bl_0_121 br_0_121 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c121 bl_0_121 br_0_121 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c121 bl_0_121 br_0_121 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c121 bl_0_121 br_0_121 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c121 bl_0_121 br_0_121 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c121 bl_0_121 br_0_121 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c121 bl_0_121 br_0_121 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c121 bl_0_121 br_0_121 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c121 bl_0_121 br_0_121 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c121 bl_0_121 br_0_121 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c121 bl_0_121 br_0_121 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c121 bl_0_121 br_0_121 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c121 bl_0_121 br_0_121 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c121 bl_0_121 br_0_121 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c121 bl_0_121 br_0_121 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c121 bl_0_121 br_0_121 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c121 bl_0_121 br_0_121 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c121 bl_0_121 br_0_121 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c121 bl_0_121 br_0_121 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c121 bl_0_121 br_0_121 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c121 bl_0_121 br_0_121 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c121 bl_0_121 br_0_121 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c121 bl_0_121 br_0_121 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c121 bl_0_121 br_0_121 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c121 bl_0_121 br_0_121 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c121 bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c122 bl_0_122 br_0_122 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c122 bl_0_122 br_0_122 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c122 bl_0_122 br_0_122 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c122 bl_0_122 br_0_122 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c122 bl_0_122 br_0_122 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c122 bl_0_122 br_0_122 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c122 bl_0_122 br_0_122 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c122 bl_0_122 br_0_122 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c122 bl_0_122 br_0_122 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c122 bl_0_122 br_0_122 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c122 bl_0_122 br_0_122 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c122 bl_0_122 br_0_122 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c122 bl_0_122 br_0_122 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c122 bl_0_122 br_0_122 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c122 bl_0_122 br_0_122 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c122 bl_0_122 br_0_122 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c122 bl_0_122 br_0_122 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c122 bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c123 bl_0_123 br_0_123 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c123 bl_0_123 br_0_123 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c123 bl_0_123 br_0_123 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c123 bl_0_123 br_0_123 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c123 bl_0_123 br_0_123 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c123 bl_0_123 br_0_123 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c123 bl_0_123 br_0_123 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c123 bl_0_123 br_0_123 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c123 bl_0_123 br_0_123 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c123 bl_0_123 br_0_123 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c123 bl_0_123 br_0_123 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c123 bl_0_123 br_0_123 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c123 bl_0_123 br_0_123 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c123 bl_0_123 br_0_123 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c123 bl_0_123 br_0_123 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c123 bl_0_123 br_0_123 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c123 bl_0_123 br_0_123 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c123 bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c126 bl_0_126 br_0_126 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c126 bl_0_126 br_0_126 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c126 bl_0_126 br_0_126 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c126 bl_0_126 br_0_126 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c126 bl_0_126 br_0_126 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c126 bl_0_126 br_0_126 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c126 bl_0_126 br_0_126 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c126 bl_0_126 br_0_126 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c126 bl_0_126 br_0_126 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c126 bl_0_126 br_0_126 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c126 bl_0_126 br_0_126 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c126 bl_0_126 br_0_126 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c126 bl_0_126 br_0_126 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c126 bl_0_126 br_0_126 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c126 bl_0_126 br_0_126 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c126 bl_0_126 br_0_126 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c126 bl_0_126 br_0_126 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c126 bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c127 bl_0_127 br_0_127 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c127 bl_0_127 br_0_127 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c127 bl_0_127 br_0_127 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c127 bl_0_127 br_0_127 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c127 bl_0_127 br_0_127 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c127 bl_0_127 br_0_127 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c127 bl_0_127 br_0_127 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c127 bl_0_127 br_0_127 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c127 bl_0_127 br_0_127 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c127 bl_0_127 br_0_127 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c127 bl_0_127 br_0_127 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c127 bl_0_127 br_0_127 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c127 bl_0_127 br_0_127 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c127 bl_0_127 br_0_127 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c127 bl_0_127 br_0_127 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c127 bl_0_127 br_0_127 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c127 bl_0_127 br_0_127 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c127 bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw -.ENDS bitcell_array - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 vdd gnd dummy_array -Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_1 -Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* OUTPUT: data_2 -* INPUT : bl_2 -* INPUT : br_2 -* OUTPUT: data_3 -* INPUT : bl_3 -* INPUT : br_3 -* OUTPUT: data_4 -* INPUT : bl_4 -* INPUT : br_4 -* OUTPUT: data_5 -* INPUT : bl_5 -* INPUT : br_5 -* OUTPUT: data_6 -* INPUT : bl_6 -* INPUT : br_6 -* OUTPUT: data_7 -* INPUT : bl_7 -* INPUT : br_7 -* OUTPUT: data_8 -* INPUT : bl_8 -* INPUT : br_8 -* OUTPUT: data_9 -* INPUT : bl_9 -* INPUT : br_9 -* OUTPUT: data_10 -* INPUT : bl_10 -* INPUT : br_10 -* OUTPUT: data_11 -* INPUT : bl_11 -* INPUT : br_11 -* OUTPUT: data_12 -* INPUT : bl_12 -* INPUT : br_12 -* OUTPUT: data_13 -* INPUT : bl_13 -* INPUT : br_13 -* OUTPUT: data_14 -* INPUT : bl_14 -* INPUT : br_14 -* OUTPUT: data_15 -* INPUT : bl_15 -* INPUT : br_15 -* OUTPUT: data_16 -* INPUT : bl_16 -* INPUT : br_16 -* OUTPUT: data_17 -* INPUT : bl_17 -* INPUT : br_17 -* OUTPUT: data_18 -* INPUT : bl_18 -* INPUT : br_18 -* OUTPUT: data_19 -* INPUT : bl_19 -* INPUT : br_19 -* OUTPUT: data_20 -* INPUT : bl_20 -* INPUT : br_20 -* OUTPUT: data_21 -* INPUT : bl_21 -* INPUT : br_21 -* OUTPUT: data_22 -* INPUT : bl_22 -* INPUT : br_22 -* OUTPUT: data_23 -* INPUT : bl_23 -* INPUT : br_23 -* OUTPUT: data_24 -* INPUT : bl_24 -* INPUT : br_24 -* OUTPUT: data_25 -* INPUT : bl_25 -* INPUT : br_25 -* OUTPUT: data_26 -* INPUT : bl_26 -* INPUT : br_26 -* OUTPUT: data_27 -* INPUT : bl_27 -* INPUT : br_27 -* OUTPUT: data_28 -* INPUT : bl_28 -* INPUT : br_28 -* OUTPUT: data_29 -* INPUT : bl_29 -* INPUT : br_29 -* OUTPUT: data_30 -* INPUT : bl_30 -* INPUT : br_30 -* OUTPUT: data_31 -* INPUT : bl_31 -* INPUT : br_31 -* OUTPUT: data_32 -* INPUT : bl_32 -* INPUT : br_32 -* OUTPUT: data_33 -* INPUT : bl_33 -* INPUT : br_33 -* OUTPUT: data_34 -* INPUT : bl_34 -* INPUT : br_34 -* OUTPUT: data_35 -* INPUT : bl_35 -* INPUT : br_35 -* OUTPUT: data_36 -* INPUT : bl_36 -* INPUT : br_36 -* OUTPUT: data_37 -* INPUT : bl_37 -* INPUT : br_37 -* OUTPUT: data_38 -* INPUT : bl_38 -* INPUT : br_38 -* OUTPUT: data_39 -* INPUT : bl_39 -* INPUT : br_39 -* OUTPUT: data_40 -* INPUT : bl_40 -* INPUT : br_40 -* OUTPUT: data_41 -* INPUT : bl_41 -* INPUT : br_41 -* OUTPUT: data_42 -* INPUT : bl_42 -* INPUT : br_42 -* OUTPUT: data_43 -* INPUT : bl_43 -* INPUT : br_43 -* OUTPUT: data_44 -* INPUT : bl_44 -* INPUT : br_44 -* OUTPUT: data_45 -* INPUT : bl_45 -* INPUT : br_45 -* OUTPUT: data_46 -* INPUT : bl_46 -* INPUT : br_46 -* OUTPUT: data_47 -* INPUT : bl_47 -* INPUT : br_47 -* OUTPUT: data_48 -* INPUT : bl_48 -* INPUT : br_48 -* OUTPUT: data_49 -* INPUT : bl_49 -* INPUT : br_49 -* OUTPUT: data_50 -* INPUT : bl_50 -* INPUT : br_50 -* OUTPUT: data_51 -* INPUT : bl_51 -* INPUT : br_51 -* OUTPUT: data_52 -* INPUT : bl_52 -* INPUT : br_52 -* OUTPUT: data_53 -* INPUT : bl_53 -* INPUT : br_53 -* OUTPUT: data_54 -* INPUT : bl_54 -* INPUT : br_54 -* OUTPUT: data_55 -* INPUT : bl_55 -* INPUT : br_55 -* OUTPUT: data_56 -* INPUT : bl_56 -* INPUT : br_56 -* OUTPUT: data_57 -* INPUT : bl_57 -* INPUT : br_57 -* OUTPUT: data_58 -* INPUT : bl_58 -* INPUT : br_58 -* OUTPUT: data_59 -* INPUT : bl_59 -* INPUT : br_59 -* OUTPUT: data_60 -* INPUT : bl_60 -* INPUT : br_60 -* OUTPUT: data_61 -* INPUT : bl_61 -* INPUT : br_61 -* OUTPUT: data_62 -* INPUT : bl_62 -* INPUT : br_62 -* OUTPUT: data_63 -* INPUT : bl_63 -* INPUT : br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 2 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp -Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp -Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp -Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp -Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp -Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp -Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp -Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp -Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp -Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp -Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp -Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp -Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp -Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp -Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp -Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp -Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp -Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp -Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp -Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp -Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp -Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp -Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp -Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp -Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp -Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp -Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp -Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp -Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp -Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp -Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp -Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp -Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp -Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp -Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp -Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp -Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp -Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp -Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp -Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp -Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp -Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp -Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp -Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp -Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp -Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp -Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp -Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp -Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp -Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp -Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp -Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp -Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp -Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp -Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp -Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp -Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp -Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp -Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp -Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp -Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp -Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp -.ENDS sense_amp_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* OUTPUT: bl_64 -* OUTPUT: br_64 -* OUTPUT: bl_65 -* OUTPUT: br_65 -* OUTPUT: bl_66 -* OUTPUT: br_66 -* OUTPUT: bl_67 -* OUTPUT: br_67 -* OUTPUT: bl_68 -* OUTPUT: br_68 -* OUTPUT: bl_69 -* OUTPUT: br_69 -* OUTPUT: bl_70 -* OUTPUT: br_70 -* OUTPUT: bl_71 -* OUTPUT: br_71 -* OUTPUT: bl_72 -* OUTPUT: br_72 -* OUTPUT: bl_73 -* OUTPUT: br_73 -* OUTPUT: bl_74 -* OUTPUT: br_74 -* OUTPUT: bl_75 -* OUTPUT: br_75 -* OUTPUT: bl_76 -* OUTPUT: br_76 -* OUTPUT: bl_77 -* OUTPUT: br_77 -* OUTPUT: bl_78 -* OUTPUT: br_78 -* OUTPUT: bl_79 -* OUTPUT: br_79 -* OUTPUT: bl_80 -* OUTPUT: br_80 -* OUTPUT: bl_81 -* OUTPUT: br_81 -* OUTPUT: bl_82 -* OUTPUT: br_82 -* OUTPUT: bl_83 -* OUTPUT: br_83 -* OUTPUT: bl_84 -* OUTPUT: br_84 -* OUTPUT: bl_85 -* OUTPUT: br_85 -* OUTPUT: bl_86 -* OUTPUT: br_86 -* OUTPUT: bl_87 -* OUTPUT: br_87 -* OUTPUT: bl_88 -* OUTPUT: br_88 -* OUTPUT: bl_89 -* OUTPUT: br_89 -* OUTPUT: bl_90 -* OUTPUT: br_90 -* OUTPUT: bl_91 -* OUTPUT: br_91 -* OUTPUT: bl_92 -* OUTPUT: br_92 -* OUTPUT: bl_93 -* OUTPUT: br_93 -* OUTPUT: bl_94 -* OUTPUT: br_94 -* OUTPUT: bl_95 -* OUTPUT: br_95 -* OUTPUT: bl_96 -* OUTPUT: br_96 -* OUTPUT: bl_97 -* OUTPUT: br_97 -* OUTPUT: bl_98 -* OUTPUT: br_98 -* OUTPUT: bl_99 -* OUTPUT: br_99 -* OUTPUT: bl_100 -* OUTPUT: br_100 -* OUTPUT: bl_101 -* OUTPUT: br_101 -* OUTPUT: bl_102 -* OUTPUT: br_102 -* OUTPUT: bl_103 -* OUTPUT: br_103 -* OUTPUT: bl_104 -* OUTPUT: br_104 -* OUTPUT: bl_105 -* OUTPUT: br_105 -* OUTPUT: bl_106 -* OUTPUT: br_106 -* OUTPUT: bl_107 -* OUTPUT: br_107 -* OUTPUT: bl_108 -* OUTPUT: br_108 -* OUTPUT: bl_109 -* OUTPUT: br_109 -* OUTPUT: bl_110 -* OUTPUT: br_110 -* OUTPUT: bl_111 -* OUTPUT: br_111 -* OUTPUT: bl_112 -* OUTPUT: br_112 -* OUTPUT: bl_113 -* OUTPUT: br_113 -* OUTPUT: bl_114 -* OUTPUT: br_114 -* OUTPUT: bl_115 -* OUTPUT: br_115 -* OUTPUT: bl_116 -* OUTPUT: br_116 -* OUTPUT: bl_117 -* OUTPUT: br_117 -* OUTPUT: bl_118 -* OUTPUT: br_118 -* OUTPUT: bl_119 -* OUTPUT: br_119 -* OUTPUT: bl_120 -* OUTPUT: br_120 -* OUTPUT: bl_121 -* OUTPUT: br_121 -* OUTPUT: bl_122 -* OUTPUT: br_122 -* OUTPUT: bl_123 -* OUTPUT: br_123 -* OUTPUT: bl_124 -* OUTPUT: br_124 -* OUTPUT: bl_125 -* OUTPUT: br_125 -* OUTPUT: bl_126 -* OUTPUT: br_126 -* OUTPUT: bl_127 -* OUTPUT: br_127 -* OUTPUT: bl_128 -* OUTPUT: br_128 -* INPUT : en_bar -* POWER : vdd -* cols: 129 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 -Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 -Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 -Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 -Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 -Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 -Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 -Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 -Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 -Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 -Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 -Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 -Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 -Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 -Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 -Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 -Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 -Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 -Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 -Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 -Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 -Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 -Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 -Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 -Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 -Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 -Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 -Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 -Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 -Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 -Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 -Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 -Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 -Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 -Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 -Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 -Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 -Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 -Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 -Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 -Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 -Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 -Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 -Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 -Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 -Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 -Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 -Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 -Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 -Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 -Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 -Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 -Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 -Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 -Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 -Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 -Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 -Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 -Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 -Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 -Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 -Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 -Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 -Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 -Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 -Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 -Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 -Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 -Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 -Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 -Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 -Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 -Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 -Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 -Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 -Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 -Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 -Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 -Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 -Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 -Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 -Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 -Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 -Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 -Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 -Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 -Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 -Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 -Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 -Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 -Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 -Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 -Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 -Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 -Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 -Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 -Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 -Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 -Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 -Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 -Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 -Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 -Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 -Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 -Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 -Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 -Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 -Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 -Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 -Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 -Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 -Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 -Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 -Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 -Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 -Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 -Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 -Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 -Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 -Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 -Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 -Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 -Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 -Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 -Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 -Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd -*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* INPUT : data_2 -* INPUT : data_3 -* INPUT : data_4 -* INPUT : data_5 -* INPUT : data_6 -* INPUT : data_7 -* INPUT : data_8 -* INPUT : data_9 -* INPUT : data_10 -* INPUT : data_11 -* INPUT : data_12 -* INPUT : data_13 -* INPUT : data_14 -* INPUT : data_15 -* INPUT : data_16 -* INPUT : data_17 -* INPUT : data_18 -* INPUT : data_19 -* INPUT : data_20 -* INPUT : data_21 -* INPUT : data_22 -* INPUT : data_23 -* INPUT : data_24 -* INPUT : data_25 -* INPUT : data_26 -* INPUT : data_27 -* INPUT : data_28 -* INPUT : data_29 -* INPUT : data_30 -* INPUT : data_31 -* INPUT : data_32 -* INPUT : data_33 -* INPUT : data_34 -* INPUT : data_35 -* INPUT : data_36 -* INPUT : data_37 -* INPUT : data_38 -* INPUT : data_39 -* INPUT : data_40 -* INPUT : data_41 -* INPUT : data_42 -* INPUT : data_43 -* INPUT : data_44 -* INPUT : data_45 -* INPUT : data_46 -* INPUT : data_47 -* INPUT : data_48 -* INPUT : data_49 -* INPUT : data_50 -* INPUT : data_51 -* INPUT : data_52 -* INPUT : data_53 -* INPUT : data_54 -* INPUT : data_55 -* INPUT : data_56 -* INPUT : data_57 -* INPUT : data_58 -* INPUT : data_59 -* INPUT : data_60 -* INPUT : data_61 -* INPUT : data_62 -* INPUT : data_63 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 64 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver -Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver -Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver -Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver -Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver -Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver -Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver -Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver -Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver -Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver -Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver -Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver -Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver -Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver -Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver -Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver -Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver -Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver -Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver -Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver -Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver -Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver -Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver -Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver -Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver -Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver -Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver -Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver -Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver -Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver -Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver -Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver -Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver -Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver -Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver -Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver -Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver -Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver -Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver -Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver -Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver -Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver -Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver -Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver -Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver -Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver -Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver -Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver -Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver -Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver -Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver -Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver -Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver -Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver -Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver -Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver -Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver -Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver -Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver -Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver -Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver -Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver -Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver -.ENDS write_driver_array - -* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -.SUBCKT column_mux bl br bl_out br_out sel gnd -*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B -* INOUT : bl -* INOUT : br -* INOUT : bl_out -* INOUT : br_out -* INOUT : sel -* INOUT : gnd -Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u -Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u -.ENDS column_mux - -.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd -*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* INOUT : sel_0 -* INOUT : sel_1 -* INOUT : bl_out_0 -* INOUT : br_out_0 -* INOUT : bl_out_1 -* INOUT : br_out_1 -* INOUT : bl_out_2 -* INOUT : br_out_2 -* INOUT : bl_out_3 -* INOUT : br_out_3 -* INOUT : bl_out_4 -* INOUT : br_out_4 -* INOUT : bl_out_5 -* INOUT : br_out_5 -* INOUT : bl_out_6 -* INOUT : br_out_6 -* INOUT : bl_out_7 -* INOUT : br_out_7 -* INOUT : bl_out_8 -* INOUT : br_out_8 -* INOUT : bl_out_9 -* INOUT : br_out_9 -* INOUT : bl_out_10 -* INOUT : br_out_10 -* INOUT : bl_out_11 -* INOUT : br_out_11 -* INOUT : bl_out_12 -* INOUT : br_out_12 -* INOUT : bl_out_13 -* INOUT : br_out_13 -* INOUT : bl_out_14 -* INOUT : br_out_14 -* INOUT : bl_out_15 -* INOUT : br_out_15 -* INOUT : bl_out_16 -* INOUT : br_out_16 -* INOUT : bl_out_17 -* INOUT : br_out_17 -* INOUT : bl_out_18 -* INOUT : br_out_18 -* INOUT : bl_out_19 -* INOUT : br_out_19 -* INOUT : bl_out_20 -* INOUT : br_out_20 -* INOUT : bl_out_21 -* INOUT : br_out_21 -* INOUT : bl_out_22 -* INOUT : br_out_22 -* INOUT : bl_out_23 -* INOUT : br_out_23 -* INOUT : bl_out_24 -* INOUT : br_out_24 -* INOUT : bl_out_25 -* INOUT : br_out_25 -* INOUT : bl_out_26 -* INOUT : br_out_26 -* INOUT : bl_out_27 -* INOUT : br_out_27 -* INOUT : bl_out_28 -* INOUT : br_out_28 -* INOUT : bl_out_29 -* INOUT : br_out_29 -* INOUT : bl_out_30 -* INOUT : br_out_30 -* INOUT : bl_out_31 -* INOUT : br_out_31 -* INOUT : bl_out_32 -* INOUT : br_out_32 -* INOUT : bl_out_33 -* INOUT : br_out_33 -* INOUT : bl_out_34 -* INOUT : br_out_34 -* INOUT : bl_out_35 -* INOUT : br_out_35 -* INOUT : bl_out_36 -* INOUT : br_out_36 -* INOUT : bl_out_37 -* INOUT : br_out_37 -* INOUT : bl_out_38 -* INOUT : br_out_38 -* INOUT : bl_out_39 -* INOUT : br_out_39 -* INOUT : bl_out_40 -* INOUT : br_out_40 -* INOUT : bl_out_41 -* INOUT : br_out_41 -* INOUT : bl_out_42 -* INOUT : br_out_42 -* INOUT : bl_out_43 -* INOUT : br_out_43 -* INOUT : bl_out_44 -* INOUT : br_out_44 -* INOUT : bl_out_45 -* INOUT : br_out_45 -* INOUT : bl_out_46 -* INOUT : br_out_46 -* INOUT : bl_out_47 -* INOUT : br_out_47 -* INOUT : bl_out_48 -* INOUT : br_out_48 -* INOUT : bl_out_49 -* INOUT : br_out_49 -* INOUT : bl_out_50 -* INOUT : br_out_50 -* INOUT : bl_out_51 -* INOUT : br_out_51 -* INOUT : bl_out_52 -* INOUT : br_out_52 -* INOUT : bl_out_53 -* INOUT : br_out_53 -* INOUT : bl_out_54 -* INOUT : br_out_54 -* INOUT : bl_out_55 -* INOUT : br_out_55 -* INOUT : bl_out_56 -* INOUT : br_out_56 -* INOUT : bl_out_57 -* INOUT : br_out_57 -* INOUT : bl_out_58 -* INOUT : br_out_58 -* INOUT : bl_out_59 -* INOUT : br_out_59 -* INOUT : bl_out_60 -* INOUT : br_out_60 -* INOUT : bl_out_61 -* INOUT : br_out_61 -* INOUT : bl_out_62 -* INOUT : br_out_62 -* INOUT : bl_out_63 -* INOUT : br_out_63 -* INOUT : gnd -* cols: 128 word_size: 64 bl: bl br: br -XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux -XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux -XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux -XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux -XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux -XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux -XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux -XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux -XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux -XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux -XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux -XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux -XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux -XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux -XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux -XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux -XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux -XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux -XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux -XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux -XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux -XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux -XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux -XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux -XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux -XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux -XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux -XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux -XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux -XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux -XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux -XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux -XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux -XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux -XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux -XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux -XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux -XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux -XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux -XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux -XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux -XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux -XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux -XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux -XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux -XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux -XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux -XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux -XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux -XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux -XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux -XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux -XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux -XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux -XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux -XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux -XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux -XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux -XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux -XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux -XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux -XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux -XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux -XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux -XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux -XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux -XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux -XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux -XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux -XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux -XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux -XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux -XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux -XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux -XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux -XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux -XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux -XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux -XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux -XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux -XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux -XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux -XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux -XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux -XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux -XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux -XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux -XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux -XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux -XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux -XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux -XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux -XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux -XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux -XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux -XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux -XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux -XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux -XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux -XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux -XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux -XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux -XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux -XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux -XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux -XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux -XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux -XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux -XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux -XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux -XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux -XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux -XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux -XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux -XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux -XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux -XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux -XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux -XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux -XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux -XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux -XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux -XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux -XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux -XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux -XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux -XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux -XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux -.ENDS column_mux_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* INPUT : sel_0 -* INPUT : sel_1 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array -Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2 - -* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u -.ENDS pinv_0 - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 32 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv_0 -.ENDS and2_dec_0 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv_0 -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* INPUT : in_16 -* INPUT : in_17 -* INPUT : in_18 -* INPUT : in_19 -* INPUT : in_20 -* INPUT : in_21 -* INPUT : in_22 -* INPUT : in_23 -* INPUT : in_24 -* INPUT : in_25 -* INPUT : in_26 -* INPUT : in_27 -* INPUT : in_28 -* INPUT : in_29 -* INPUT : in_30 -* INPUT : in_31 -* INPUT : in_32 -* INPUT : in_33 -* INPUT : in_34 -* INPUT : in_35 -* INPUT : in_36 -* INPUT : in_37 -* INPUT : in_38 -* INPUT : in_39 -* INPUT : in_40 -* INPUT : in_41 -* INPUT : in_42 -* INPUT : in_43 -* INPUT : in_44 -* INPUT : in_45 -* INPUT : in_46 -* INPUT : in_47 -* INPUT : in_48 -* INPUT : in_49 -* INPUT : in_50 -* INPUT : in_51 -* INPUT : in_52 -* INPUT : in_53 -* INPUT : in_54 -* INPUT : in_55 -* INPUT : in_56 -* INPUT : in_57 -* INPUT : in_58 -* INPUT : in_59 -* INPUT : in_60 -* INPUT : in_61 -* INPUT : in_62 -* INPUT : in_63 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver -Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver -Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver -Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver -Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver -Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver -Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver -Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver -Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver -Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver -Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver -Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver -Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver -Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver -Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver -Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver -Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver -Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver -Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver -Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver -Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver -Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver -Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver -Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver -Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver -Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver -Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver -Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver -Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver -Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver -Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver -Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver -Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver -Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver -Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver -Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver -Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver -Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver -Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver -Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver -Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver -Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver -Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver -Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver -Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver -Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver -Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver -Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver -.ENDS wordline_driver_array - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand3 - -.SUBCKT and3_dec A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand3_dec_nand A B C zb_int vdd gnd pnand3 -Xpand3_dec_inv zb_int Z vdd gnd pinv -.ENDS and3_dec - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* OUTPUT: decode_16 -* OUTPUT: decode_17 -* OUTPUT: decode_18 -* OUTPUT: decode_19 -* OUTPUT: decode_20 -* OUTPUT: decode_21 -* OUTPUT: decode_22 -* OUTPUT: decode_23 -* OUTPUT: decode_24 -* OUTPUT: decode_25 -* OUTPUT: decode_26 -* OUTPUT: decode_27 -* OUTPUT: decode_28 -* OUTPUT: decode_29 -* OUTPUT: decode_30 -* OUTPUT: decode_31 -* OUTPUT: decode_32 -* OUTPUT: decode_33 -* OUTPUT: decode_34 -* OUTPUT: decode_35 -* OUTPUT: decode_36 -* OUTPUT: decode_37 -* OUTPUT: decode_38 -* OUTPUT: decode_39 -* OUTPUT: decode_40 -* OUTPUT: decode_41 -* OUTPUT: decode_42 -* OUTPUT: decode_43 -* OUTPUT: decode_44 -* OUTPUT: decode_45 -* OUTPUT: decode_46 -* OUTPUT: decode_47 -* OUTPUT: decode_48 -* OUTPUT: decode_49 -* OUTPUT: decode_50 -* OUTPUT: decode_51 -* OUTPUT: decode_52 -* OUTPUT: decode_53 -* OUTPUT: decode_54 -* OUTPUT: decode_55 -* OUTPUT: decode_56 -* OUTPUT: decode_57 -* OUTPUT: decode_58 -* OUTPUT: decode_59 -* OUTPUT: decode_60 -* OUTPUT: decode_61 -* OUTPUT: decode_62 -* OUTPUT: decode_63 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 -Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 -XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec -XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec -XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec -XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec -XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec -XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec -XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec -XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec -XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec -XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec -XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec -XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec -XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec -XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec -XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec -XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec -XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec -XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec -XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec -XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec -XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec -XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec -XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec -XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec -XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec -XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec -XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec -XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec -XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec -XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec -XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec -XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec -XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec -XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec -XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec -XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec -XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec -XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec -XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec -XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec -XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec -XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec -XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec -XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec -XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec -XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec -XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec -XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec -XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec -XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec -XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec -XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec -XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec -XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec -XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec -XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec -XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec -XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec -XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec -XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec -XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec -XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec -XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec -XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec -.ENDS hierarchical_decoder - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: dout0_2 -* OUTPUT: dout0_3 -* OUTPUT: dout0_4 -* OUTPUT: dout0_5 -* OUTPUT: dout0_6 -* OUTPUT: dout0_7 -* OUTPUT: dout0_8 -* OUTPUT: dout0_9 -* OUTPUT: dout0_10 -* OUTPUT: dout0_11 -* OUTPUT: dout0_12 -* OUTPUT: dout0_13 -* OUTPUT: dout0_14 -* OUTPUT: dout0_15 -* OUTPUT: dout0_16 -* OUTPUT: dout0_17 -* OUTPUT: dout0_18 -* OUTPUT: dout0_19 -* OUTPUT: dout0_20 -* OUTPUT: dout0_21 -* OUTPUT: dout0_22 -* OUTPUT: dout0_23 -* OUTPUT: dout0_24 -* OUTPUT: dout0_25 -* OUTPUT: dout0_26 -* OUTPUT: dout0_27 -* OUTPUT: dout0_28 -* OUTPUT: dout0_29 -* OUTPUT: dout0_30 -* OUTPUT: dout0_31 -* OUTPUT: dout0_32 -* OUTPUT: dout0_33 -* OUTPUT: dout0_34 -* OUTPUT: dout0_35 -* OUTPUT: dout0_36 -* OUTPUT: dout0_37 -* OUTPUT: dout0_38 -* OUTPUT: dout0_39 -* OUTPUT: dout0_40 -* OUTPUT: dout0_41 -* OUTPUT: dout0_42 -* OUTPUT: dout0_43 -* OUTPUT: dout0_44 -* OUTPUT: dout0_45 -* OUTPUT: dout0_46 -* OUTPUT: dout0_47 -* OUTPUT: dout0_48 -* OUTPUT: dout0_49 -* OUTPUT: dout0_50 -* OUTPUT: dout0_51 -* OUTPUT: dout0_52 -* OUTPUT: dout0_53 -* OUTPUT: dout0_54 -* OUTPUT: dout0_55 -* OUTPUT: dout0_56 -* OUTPUT: dout0_57 -* OUTPUT: dout0_58 -* OUTPUT: dout0_59 -* OUTPUT: dout0_60 -* OUTPUT: dout0_61 -* OUTPUT: dout0_62 -* OUTPUT: dout0_63 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : din0_2 -* INPUT : din0_3 -* INPUT : din0_4 -* INPUT : din0_5 -* INPUT : din0_6 -* INPUT : din0_7 -* INPUT : din0_8 -* INPUT : din0_9 -* INPUT : din0_10 -* INPUT : din0_11 -* INPUT : din0_12 -* INPUT : din0_13 -* INPUT : din0_14 -* INPUT : din0_15 -* INPUT : din0_16 -* INPUT : din0_17 -* INPUT : din0_18 -* INPUT : din0_19 -* INPUT : din0_20 -* INPUT : din0_21 -* INPUT : din0_22 -* INPUT : din0_23 -* INPUT : din0_24 -* INPUT : din0_25 -* INPUT : din0_26 -* INPUT : din0_27 -* INPUT : din0_28 -* INPUT : din0_29 -* INPUT : din0_30 -* INPUT : din0_31 -* INPUT : din0_32 -* INPUT : din0_33 -* INPUT : din0_34 -* INPUT : din0_35 -* INPUT : din0_36 -* INPUT : din0_37 -* INPUT : din0_38 -* INPUT : din0_39 -* INPUT : din0_40 -* INPUT : din0_41 -* INPUT : din0_42 -* INPUT : din0_43 -* INPUT : din0_44 -* INPUT : din0_45 -* INPUT : din0_46 -* INPUT : din0_47 -* INPUT : din0_48 -* INPUT : din0_49 -* INPUT : din0_50 -* INPUT : din0_51 -* INPUT : din0_52 -* INPUT : din0_53 -* INPUT : din0_54 -* INPUT : din0_55 -* INPUT : din0_56 -* INPUT : din0_57 -* INPUT : din0_58 -* INPUT : din0_59 -* INPUT : din0_60 -* INPUT : din0_61 -* INPUT : din0_62 -* INPUT : din0_63 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : addr0_4 -* INPUT : addr0_5 -* INPUT : addr0_6 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address -Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf -.ENDS bank - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_2 -Xdff_buf_inv2 Qb Q vdd gnd pinv_3 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2_0 - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -.SUBCKT pinv_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u -.ENDS pinv_4 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_4 -.ENDS pdriver - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u -.ENDS pinv_11 - -* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u -.ENDS pinv_9 - -* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u -.ENDS pinv_10 - -* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p - -* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p - -.SUBCKT pinv_12 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u -.ENDS pinv_12 - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_7 - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pinv_8 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 1, 2, 5, 14, 42, 125] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 -Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 -Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 -Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 -.ENDS pdriver_0 - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand3_0 - -* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p - -* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -.SUBCKT pinv_16 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u -.ENDS pinv_16 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [64] -Xbuf_inv1 A Z vdd gnd pinv_16 -.ENDS pdriver_3 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -.SUBCKT pinv_17 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_17 - -* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p - -* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p - -.SUBCKT pinv_18 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u -.ENDS pinv_18 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 2, 5, 14, 43] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 -Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 -.ENDS pdriver_4 - -* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p - -* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p - -.SUBCKT pinv_15 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u -.ENDS pinv_15 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [72] -Xbuf_inv1 A Z vdd gnd pinv_15 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT pinv_19 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_19 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_19 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 -Xdinv1 dout_1 dout_2 vdd gnd pinv_19 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 -Xdinv2 dout_2 dout_3 vdd gnd pinv_19 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 -Xdinv3 dout_3 dout_4 vdd gnd pinv_19 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 -Xdinv4 dout_4 dout_5 vdd gnd pinv_19 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 -Xdinv5 dout_5 dout_6 vdd gnd pinv_19 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 -Xdinv6 dout_6 dout_7 vdd gnd pinv_19 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 -Xdinv7 dout_7 dout_8 vdd gnd pinv_19 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 -Xdinv8 dout_8 out vdd gnd pinv_19 -Xdload_8_0 out n_8_0 vdd gnd pinv_19 -Xdload_8_1 out n_8_1 vdd gnd pinv_19 -Xdload_8_2 out n_8_2 vdd gnd pinv_19 -Xdload_8_3 out n_8_3 vdd gnd pinv_19 -.ENDS delay_chain - -* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p - -.SUBCKT pinv_14 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u -.ENDS pinv_14 - -* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p - -.SUBCKT pinv_13 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u -.ENDS pinv_13 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [7, 21] -Xbuf_inv1 A Zb1_int vdd gnd pinv_13 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 -.ENDS pdriver_1 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2_1 - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 64 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 -Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_17 -Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 -Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 -Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain -Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 -Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd -*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : din0[2] -* INPUT : din0[3] -* INPUT : din0[4] -* INPUT : din0[5] -* INPUT : din0[6] -* INPUT : din0[7] -* INPUT : din0[8] -* INPUT : din0[9] -* INPUT : din0[10] -* INPUT : din0[11] -* INPUT : din0[12] -* INPUT : din0[13] -* INPUT : din0[14] -* INPUT : din0[15] -* INPUT : din0[16] -* INPUT : din0[17] -* INPUT : din0[18] -* INPUT : din0[19] -* INPUT : din0[20] -* INPUT : din0[21] -* INPUT : din0[22] -* INPUT : din0[23] -* INPUT : din0[24] -* INPUT : din0[25] -* INPUT : din0[26] -* INPUT : din0[27] -* INPUT : din0[28] -* INPUT : din0[29] -* INPUT : din0[30] -* INPUT : din0[31] -* INPUT : din0[32] -* INPUT : din0[33] -* INPUT : din0[34] -* INPUT : din0[35] -* INPUT : din0[36] -* INPUT : din0[37] -* INPUT : din0[38] -* INPUT : din0[39] -* INPUT : din0[40] -* INPUT : din0[41] -* INPUT : din0[42] -* INPUT : din0[43] -* INPUT : din0[44] -* INPUT : din0[45] -* INPUT : din0[46] -* INPUT : din0[47] -* INPUT : din0[48] -* INPUT : din0[49] -* INPUT : din0[50] -* INPUT : din0[51] -* INPUT : din0[52] -* INPUT : din0[53] -* INPUT : din0[54] -* INPUT : din0[55] -* INPUT : din0[56] -* INPUT : din0[57] -* INPUT : din0[58] -* INPUT : din0[59] -* INPUT : din0[60] -* INPUT : din0[61] -* INPUT : din0[62] -* INPUT : din0[63] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : addr0[4] -* INPUT : addr0[5] -* INPUT : addr0[6] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* OUTPUT: dout0[2] -* OUTPUT: dout0[3] -* OUTPUT: dout0[4] -* OUTPUT: dout0[5] -* OUTPUT: dout0[6] -* OUTPUT: dout0[7] -* OUTPUT: dout0[8] -* OUTPUT: dout0[9] -* OUTPUT: dout0[10] -* OUTPUT: dout0[11] -* OUTPUT: dout0[12] -* OUTPUT: dout0[13] -* OUTPUT: dout0[14] -* OUTPUT: dout0[15] -* OUTPUT: dout0[16] -* OUTPUT: dout0[17] -* OUTPUT: dout0[18] -* OUTPUT: dout0[19] -* OUTPUT: dout0[20] -* OUTPUT: dout0[21] -* OUTPUT: dout0[22] -* OUTPUT: dout0[23] -* OUTPUT: dout0[24] -* OUTPUT: dout0[25] -* OUTPUT: dout0[26] -* OUTPUT: dout0[27] -* OUTPUT: dout0[28] -* OUTPUT: dout0[29] -* OUTPUT: dout0[30] -* OUTPUT: dout0[31] -* OUTPUT: dout0[32] -* OUTPUT: dout0[33] -* OUTPUT: dout0[34] -* OUTPUT: dout0[35] -* OUTPUT: dout0[36] -* OUTPUT: dout0[37] -* OUTPUT: dout0[38] -* OUTPUT: dout0[39] -* OUTPUT: dout0[40] -* OUTPUT: dout0[41] -* OUTPUT: dout0[42] -* OUTPUT: dout0[43] -* OUTPUT: dout0[44] -* OUTPUT: dout0[45] -* OUTPUT: dout0[46] -* OUTPUT: dout0[47] -* OUTPUT: dout0[48] -* OUTPUT: dout0[49] -* OUTPUT: dout0[50] -* OUTPUT: dout0[51] -* OUTPUT: dout0[52] -* OUTPUT: dout0[53] -* OUTPUT: dout0[54] -* OUTPUT: dout0[55] -* OUTPUT: dout0[56] -* OUTPUT: dout0[57] -* OUTPUT: dout0[58] -* OUTPUT: dout0[59] -* OUTPUT: dout0[60] -* OUTPUT: dout0[61] -* OUTPUT: dout0[62] -* OUTPUT: dout0[63] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff -Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff -Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff -.ENDS sram_64_128_scn4m_subm diff --git a/1KB/sram_64_128_scn4m_subm.sp b/1KB/sram_64_128_scn4m_subm.sp deleted file mode 100644 index abee3faf..00000000 --- a/1KB/sram_64_128_scn4m_subm.sp +++ /dev/null @@ -1,14050 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 128 -* Data bits: 64 -* Banks: 1 -* Column mux: 2:1 -* Trimmed: False -* LVS: False -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 din_5 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 6 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff -Xdff_r5_c0 din_5 dout_5 clk vdd gnd dff -.ENDS row_addr_dff - -.SUBCKT col_addr_dff din_0 dout_0 clk vdd gnd -*.PININFO din_0:I dout_0:O clk:I vdd:B gnd:B -* INPUT : din_0 -* OUTPUT: dout_0 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -.ENDS col_addr_dff - -.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 64 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff -Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff -Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff -Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff -Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff -Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff -Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff -Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff -Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff -Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff -Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff -Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff -Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff -Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff -Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff -Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff -Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff -Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff -Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff -Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff -Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff -Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff -Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff -Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff -Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff -Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff -Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff -Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff -Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff -Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff -Xdff_r0_c32 din_32 dout_32 clk vdd gnd dff -Xdff_r0_c33 din_33 dout_33 clk vdd gnd dff -Xdff_r0_c34 din_34 dout_34 clk vdd gnd dff -Xdff_r0_c35 din_35 dout_35 clk vdd gnd dff -Xdff_r0_c36 din_36 dout_36 clk vdd gnd dff -Xdff_r0_c37 din_37 dout_37 clk vdd gnd dff -Xdff_r0_c38 din_38 dout_38 clk vdd gnd dff -Xdff_r0_c39 din_39 dout_39 clk vdd gnd dff -Xdff_r0_c40 din_40 dout_40 clk vdd gnd dff -Xdff_r0_c41 din_41 dout_41 clk vdd gnd dff -Xdff_r0_c42 din_42 dout_42 clk vdd gnd dff -Xdff_r0_c43 din_43 dout_43 clk vdd gnd dff -Xdff_r0_c44 din_44 dout_44 clk vdd gnd dff -Xdff_r0_c45 din_45 dout_45 clk vdd gnd dff -Xdff_r0_c46 din_46 dout_46 clk vdd gnd dff -Xdff_r0_c47 din_47 dout_47 clk vdd gnd dff -Xdff_r0_c48 din_48 dout_48 clk vdd gnd dff -Xdff_r0_c49 din_49 dout_49 clk vdd gnd dff -Xdff_r0_c50 din_50 dout_50 clk vdd gnd dff -Xdff_r0_c51 din_51 dout_51 clk vdd gnd dff -Xdff_r0_c52 din_52 dout_52 clk vdd gnd dff -Xdff_r0_c53 din_53 dout_53 clk vdd gnd dff -Xdff_r0_c54 din_54 dout_54 clk vdd gnd dff -Xdff_r0_c55 din_55 dout_55 clk vdd gnd dff -Xdff_r0_c56 din_56 dout_56 clk vdd gnd dff -Xdff_r0_c57 din_57 dout_57 clk vdd gnd dff -Xdff_r0_c58 din_58 dout_58 clk vdd gnd dff -Xdff_r0_c59 din_59 dout_59 clk vdd gnd dff -Xdff_r0_c60 din_60 dout_60 clk vdd gnd dff -Xdff_r0_c61 din_61 dout_61 clk vdd gnd dff -Xdff_r0_c62 din_62 dout_62 clk vdd gnd dff -Xdff_r0_c63 din_63 dout_63 clk vdd gnd dff -.ENDS data_dff - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_2 - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_3 - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_1 - -.SUBCKT pinvbuf A Zb Z vdd gnd -*.PININFO A:B Zb:B Z:B vdd:B gnd:B -* INOUT : A -* INOUT : Zb -* INOUT : Z -* INOUT : vdd -* INOUT : gnd -Xbuf_inv1 A zb_int vdd gnd pinv_1 -Xbuf_inv2 zb_int z_int vdd gnd pinv_2 -Xbuf_inv3 z_int Zb vdd gnd pinv_3 -Xbuf_inv4 zb_int Z vdd gnd pinv_3 -.ENDS pinvbuf - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd dummy_cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd dummy_cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd dummy_cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd dummy_cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd dummy_cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd dummy_cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd dummy_cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd dummy_cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd dummy_cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd dummy_cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd dummy_cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd dummy_cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd dummy_cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd dummy_cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd dummy_cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd dummy_cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd dummy_cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd dummy_cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd dummy_cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd dummy_cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd dummy_cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd dummy_cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd dummy_cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd dummy_cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd dummy_cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd dummy_cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd dummy_cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd dummy_cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd dummy_cell_1rw -Xbit_r64_c0 bl_0_0 br_0_0 wl_0_64 vdd gnd dummy_cell_1rw -Xbit_r65_c0 bl_0_0 br_0_0 wl_0_65 vdd gnd dummy_cell_1rw -Xbit_r66_c0 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 wl_0_64 wl_0_65 wl_0_66 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I wl_0_64:I wl_0_65:I wl_0_66:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* INPUT : wl_0_64 -* INPUT : wl_0_65 -* INPUT : wl_0_66 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw -Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw -Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw -Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw -Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw -Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw -Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw -Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw -Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw -Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw -Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw -Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw -Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw -Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw -Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw -Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw -Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd replica_cell_1rw -Xrbc_35 bl_0_0 br_0_0 wl_0_35 vdd gnd replica_cell_1rw -Xrbc_36 bl_0_0 br_0_0 wl_0_36 vdd gnd replica_cell_1rw -Xrbc_37 bl_0_0 br_0_0 wl_0_37 vdd gnd replica_cell_1rw -Xrbc_38 bl_0_0 br_0_0 wl_0_38 vdd gnd replica_cell_1rw -Xrbc_39 bl_0_0 br_0_0 wl_0_39 vdd gnd replica_cell_1rw -Xrbc_40 bl_0_0 br_0_0 wl_0_40 vdd gnd replica_cell_1rw -Xrbc_41 bl_0_0 br_0_0 wl_0_41 vdd gnd replica_cell_1rw -Xrbc_42 bl_0_0 br_0_0 wl_0_42 vdd gnd replica_cell_1rw -Xrbc_43 bl_0_0 br_0_0 wl_0_43 vdd gnd replica_cell_1rw -Xrbc_44 bl_0_0 br_0_0 wl_0_44 vdd gnd replica_cell_1rw -Xrbc_45 bl_0_0 br_0_0 wl_0_45 vdd gnd replica_cell_1rw -Xrbc_46 bl_0_0 br_0_0 wl_0_46 vdd gnd replica_cell_1rw -Xrbc_47 bl_0_0 br_0_0 wl_0_47 vdd gnd replica_cell_1rw -Xrbc_48 bl_0_0 br_0_0 wl_0_48 vdd gnd replica_cell_1rw -Xrbc_49 bl_0_0 br_0_0 wl_0_49 vdd gnd replica_cell_1rw -Xrbc_50 bl_0_0 br_0_0 wl_0_50 vdd gnd replica_cell_1rw -Xrbc_51 bl_0_0 br_0_0 wl_0_51 vdd gnd replica_cell_1rw -Xrbc_52 bl_0_0 br_0_0 wl_0_52 vdd gnd replica_cell_1rw -Xrbc_53 bl_0_0 br_0_0 wl_0_53 vdd gnd replica_cell_1rw -Xrbc_54 bl_0_0 br_0_0 wl_0_54 vdd gnd replica_cell_1rw -Xrbc_55 bl_0_0 br_0_0 wl_0_55 vdd gnd replica_cell_1rw -Xrbc_56 bl_0_0 br_0_0 wl_0_56 vdd gnd replica_cell_1rw -Xrbc_57 bl_0_0 br_0_0 wl_0_57 vdd gnd replica_cell_1rw -Xrbc_58 bl_0_0 br_0_0 wl_0_58 vdd gnd replica_cell_1rw -Xrbc_59 bl_0_0 br_0_0 wl_0_59 vdd gnd replica_cell_1rw -Xrbc_60 bl_0_0 br_0_0 wl_0_60 vdd gnd replica_cell_1rw -Xrbc_61 bl_0_0 br_0_0 wl_0_61 vdd gnd replica_cell_1rw -Xrbc_62 bl_0_0 br_0_0 wl_0_62 vdd gnd replica_cell_1rw -Xrbc_63 bl_0_0 br_0_0 wl_0_63 vdd gnd replica_cell_1rw -Xrbc_64 bl_0_0 br_0_0 wl_0_64 vdd gnd replica_cell_1rw -Xrbc_65 bl_0_0 br_0_0 wl_0_65 vdd gnd replica_cell_1rw -Xrbc_66 bl_0_0 br_0_0 wl_0_66 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c0 bl_0_0 br_0_0 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c0 bl_0_0 br_0_0 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c0 bl_0_0 br_0_0 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c0 bl_0_0 br_0_0 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c0 bl_0_0 br_0_0 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c0 bl_0_0 br_0_0 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c0 bl_0_0 br_0_0 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c0 bl_0_0 br_0_0 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c0 bl_0_0 br_0_0 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c0 bl_0_0 br_0_0 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c0 bl_0_0 br_0_0 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c0 bl_0_0 br_0_0 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c0 bl_0_0 br_0_0 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c0 bl_0_0 br_0_0 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c0 bl_0_0 br_0_0 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c0 bl_0_0 br_0_0 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c0 bl_0_0 br_0_0 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c0 bl_0_0 br_0_0 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c0 bl_0_0 br_0_0 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c0 bl_0_0 br_0_0 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c0 bl_0_0 br_0_0 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c0 bl_0_0 br_0_0 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c0 bl_0_0 br_0_0 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c0 bl_0_0 br_0_0 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c0 bl_0_0 br_0_0 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c0 bl_0_0 br_0_0 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c0 bl_0_0 br_0_0 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c0 bl_0_0 br_0_0 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c0 bl_0_0 br_0_0 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c1 bl_0_1 br_0_1 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c1 bl_0_1 br_0_1 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c1 bl_0_1 br_0_1 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c1 bl_0_1 br_0_1 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c1 bl_0_1 br_0_1 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c1 bl_0_1 br_0_1 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c1 bl_0_1 br_0_1 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c1 bl_0_1 br_0_1 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c1 bl_0_1 br_0_1 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c1 bl_0_1 br_0_1 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c1 bl_0_1 br_0_1 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c1 bl_0_1 br_0_1 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c1 bl_0_1 br_0_1 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c1 bl_0_1 br_0_1 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c1 bl_0_1 br_0_1 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c1 bl_0_1 br_0_1 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c1 bl_0_1 br_0_1 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c1 bl_0_1 br_0_1 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c1 bl_0_1 br_0_1 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c1 bl_0_1 br_0_1 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c1 bl_0_1 br_0_1 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c1 bl_0_1 br_0_1 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c1 bl_0_1 br_0_1 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c1 bl_0_1 br_0_1 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c1 bl_0_1 br_0_1 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c1 bl_0_1 br_0_1 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c1 bl_0_1 br_0_1 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c1 bl_0_1 br_0_1 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c1 bl_0_1 br_0_1 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c1 bl_0_1 br_0_1 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c1 bl_0_1 br_0_1 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c1 bl_0_1 br_0_1 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c2 bl_0_2 br_0_2 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c2 bl_0_2 br_0_2 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c2 bl_0_2 br_0_2 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c2 bl_0_2 br_0_2 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c2 bl_0_2 br_0_2 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c2 bl_0_2 br_0_2 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c2 bl_0_2 br_0_2 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c2 bl_0_2 br_0_2 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c2 bl_0_2 br_0_2 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c2 bl_0_2 br_0_2 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c2 bl_0_2 br_0_2 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c2 bl_0_2 br_0_2 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c2 bl_0_2 br_0_2 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c2 bl_0_2 br_0_2 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c2 bl_0_2 br_0_2 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c2 bl_0_2 br_0_2 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c2 bl_0_2 br_0_2 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c2 bl_0_2 br_0_2 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c2 bl_0_2 br_0_2 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c2 bl_0_2 br_0_2 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c2 bl_0_2 br_0_2 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c2 bl_0_2 br_0_2 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c2 bl_0_2 br_0_2 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c2 bl_0_2 br_0_2 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c2 bl_0_2 br_0_2 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c2 bl_0_2 br_0_2 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c2 bl_0_2 br_0_2 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c2 bl_0_2 br_0_2 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c2 bl_0_2 br_0_2 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c2 bl_0_2 br_0_2 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c2 bl_0_2 br_0_2 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c2 bl_0_2 br_0_2 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c3 bl_0_3 br_0_3 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c3 bl_0_3 br_0_3 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c3 bl_0_3 br_0_3 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c3 bl_0_3 br_0_3 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c3 bl_0_3 br_0_3 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c3 bl_0_3 br_0_3 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c3 bl_0_3 br_0_3 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c3 bl_0_3 br_0_3 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c3 bl_0_3 br_0_3 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c3 bl_0_3 br_0_3 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c3 bl_0_3 br_0_3 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c3 bl_0_3 br_0_3 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c3 bl_0_3 br_0_3 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c3 bl_0_3 br_0_3 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c3 bl_0_3 br_0_3 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c3 bl_0_3 br_0_3 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c3 bl_0_3 br_0_3 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c3 bl_0_3 br_0_3 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c3 bl_0_3 br_0_3 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c3 bl_0_3 br_0_3 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c3 bl_0_3 br_0_3 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c3 bl_0_3 br_0_3 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c3 bl_0_3 br_0_3 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c3 bl_0_3 br_0_3 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c3 bl_0_3 br_0_3 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c3 bl_0_3 br_0_3 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c3 bl_0_3 br_0_3 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c3 bl_0_3 br_0_3 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c3 bl_0_3 br_0_3 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c3 bl_0_3 br_0_3 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c3 bl_0_3 br_0_3 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c3 bl_0_3 br_0_3 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c4 bl_0_4 br_0_4 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c4 bl_0_4 br_0_4 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c4 bl_0_4 br_0_4 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c4 bl_0_4 br_0_4 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c4 bl_0_4 br_0_4 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c4 bl_0_4 br_0_4 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c4 bl_0_4 br_0_4 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c4 bl_0_4 br_0_4 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c4 bl_0_4 br_0_4 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c4 bl_0_4 br_0_4 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c4 bl_0_4 br_0_4 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c4 bl_0_4 br_0_4 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c4 bl_0_4 br_0_4 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c4 bl_0_4 br_0_4 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c4 bl_0_4 br_0_4 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c4 bl_0_4 br_0_4 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c4 bl_0_4 br_0_4 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c4 bl_0_4 br_0_4 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c4 bl_0_4 br_0_4 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c4 bl_0_4 br_0_4 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c4 bl_0_4 br_0_4 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c4 bl_0_4 br_0_4 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c4 bl_0_4 br_0_4 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c4 bl_0_4 br_0_4 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c4 bl_0_4 br_0_4 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c4 bl_0_4 br_0_4 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c4 bl_0_4 br_0_4 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c4 bl_0_4 br_0_4 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c4 bl_0_4 br_0_4 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c4 bl_0_4 br_0_4 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c4 bl_0_4 br_0_4 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c4 bl_0_4 br_0_4 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c5 bl_0_5 br_0_5 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c5 bl_0_5 br_0_5 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c5 bl_0_5 br_0_5 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c5 bl_0_5 br_0_5 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c5 bl_0_5 br_0_5 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c5 bl_0_5 br_0_5 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c5 bl_0_5 br_0_5 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c5 bl_0_5 br_0_5 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c5 bl_0_5 br_0_5 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c5 bl_0_5 br_0_5 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c5 bl_0_5 br_0_5 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c5 bl_0_5 br_0_5 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c5 bl_0_5 br_0_5 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c5 bl_0_5 br_0_5 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c5 bl_0_5 br_0_5 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c5 bl_0_5 br_0_5 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c5 bl_0_5 br_0_5 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c5 bl_0_5 br_0_5 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c5 bl_0_5 br_0_5 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c5 bl_0_5 br_0_5 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c5 bl_0_5 br_0_5 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c5 bl_0_5 br_0_5 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c5 bl_0_5 br_0_5 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c5 bl_0_5 br_0_5 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c5 bl_0_5 br_0_5 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c5 bl_0_5 br_0_5 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c5 bl_0_5 br_0_5 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c5 bl_0_5 br_0_5 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c5 bl_0_5 br_0_5 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c5 bl_0_5 br_0_5 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c5 bl_0_5 br_0_5 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c5 bl_0_5 br_0_5 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c6 bl_0_6 br_0_6 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c6 bl_0_6 br_0_6 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c6 bl_0_6 br_0_6 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c6 bl_0_6 br_0_6 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c6 bl_0_6 br_0_6 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c6 bl_0_6 br_0_6 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c6 bl_0_6 br_0_6 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c6 bl_0_6 br_0_6 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c6 bl_0_6 br_0_6 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c6 bl_0_6 br_0_6 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c6 bl_0_6 br_0_6 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c6 bl_0_6 br_0_6 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c6 bl_0_6 br_0_6 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c6 bl_0_6 br_0_6 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c6 bl_0_6 br_0_6 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c6 bl_0_6 br_0_6 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c6 bl_0_6 br_0_6 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c6 bl_0_6 br_0_6 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c6 bl_0_6 br_0_6 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c6 bl_0_6 br_0_6 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c6 bl_0_6 br_0_6 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c6 bl_0_6 br_0_6 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c6 bl_0_6 br_0_6 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c6 bl_0_6 br_0_6 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c6 bl_0_6 br_0_6 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c6 bl_0_6 br_0_6 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c6 bl_0_6 br_0_6 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c6 bl_0_6 br_0_6 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c6 bl_0_6 br_0_6 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c6 bl_0_6 br_0_6 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c6 bl_0_6 br_0_6 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c6 bl_0_6 br_0_6 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c7 bl_0_7 br_0_7 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c7 bl_0_7 br_0_7 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c7 bl_0_7 br_0_7 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c7 bl_0_7 br_0_7 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c7 bl_0_7 br_0_7 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c7 bl_0_7 br_0_7 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c7 bl_0_7 br_0_7 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c7 bl_0_7 br_0_7 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c7 bl_0_7 br_0_7 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c7 bl_0_7 br_0_7 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c7 bl_0_7 br_0_7 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c7 bl_0_7 br_0_7 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c7 bl_0_7 br_0_7 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c7 bl_0_7 br_0_7 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c7 bl_0_7 br_0_7 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c7 bl_0_7 br_0_7 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c7 bl_0_7 br_0_7 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c7 bl_0_7 br_0_7 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c7 bl_0_7 br_0_7 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c7 bl_0_7 br_0_7 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c7 bl_0_7 br_0_7 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c7 bl_0_7 br_0_7 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c7 bl_0_7 br_0_7 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c7 bl_0_7 br_0_7 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c7 bl_0_7 br_0_7 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c7 bl_0_7 br_0_7 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c7 bl_0_7 br_0_7 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c7 bl_0_7 br_0_7 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c7 bl_0_7 br_0_7 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c7 bl_0_7 br_0_7 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c7 bl_0_7 br_0_7 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c7 bl_0_7 br_0_7 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c8 bl_0_8 br_0_8 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c8 bl_0_8 br_0_8 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c8 bl_0_8 br_0_8 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c8 bl_0_8 br_0_8 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c8 bl_0_8 br_0_8 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c8 bl_0_8 br_0_8 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c8 bl_0_8 br_0_8 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c8 bl_0_8 br_0_8 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c8 bl_0_8 br_0_8 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c8 bl_0_8 br_0_8 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c8 bl_0_8 br_0_8 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c8 bl_0_8 br_0_8 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c8 bl_0_8 br_0_8 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c8 bl_0_8 br_0_8 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c8 bl_0_8 br_0_8 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c8 bl_0_8 br_0_8 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c8 bl_0_8 br_0_8 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c8 bl_0_8 br_0_8 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c8 bl_0_8 br_0_8 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c8 bl_0_8 br_0_8 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c8 bl_0_8 br_0_8 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c8 bl_0_8 br_0_8 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c8 bl_0_8 br_0_8 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c8 bl_0_8 br_0_8 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c8 bl_0_8 br_0_8 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c8 bl_0_8 br_0_8 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c8 bl_0_8 br_0_8 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c8 bl_0_8 br_0_8 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c8 bl_0_8 br_0_8 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c8 bl_0_8 br_0_8 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c8 bl_0_8 br_0_8 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c8 bl_0_8 br_0_8 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c9 bl_0_9 br_0_9 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c9 bl_0_9 br_0_9 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c9 bl_0_9 br_0_9 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c9 bl_0_9 br_0_9 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c9 bl_0_9 br_0_9 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c9 bl_0_9 br_0_9 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c9 bl_0_9 br_0_9 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c9 bl_0_9 br_0_9 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c9 bl_0_9 br_0_9 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c9 bl_0_9 br_0_9 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c9 bl_0_9 br_0_9 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c9 bl_0_9 br_0_9 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c9 bl_0_9 br_0_9 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c9 bl_0_9 br_0_9 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c9 bl_0_9 br_0_9 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c9 bl_0_9 br_0_9 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c9 bl_0_9 br_0_9 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c9 bl_0_9 br_0_9 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c9 bl_0_9 br_0_9 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c9 bl_0_9 br_0_9 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c9 bl_0_9 br_0_9 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c9 bl_0_9 br_0_9 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c9 bl_0_9 br_0_9 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c9 bl_0_9 br_0_9 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c9 bl_0_9 br_0_9 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c9 bl_0_9 br_0_9 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c9 bl_0_9 br_0_9 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c9 bl_0_9 br_0_9 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c9 bl_0_9 br_0_9 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c9 bl_0_9 br_0_9 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c9 bl_0_9 br_0_9 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c9 bl_0_9 br_0_9 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c10 bl_0_10 br_0_10 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c10 bl_0_10 br_0_10 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c10 bl_0_10 br_0_10 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c10 bl_0_10 br_0_10 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c10 bl_0_10 br_0_10 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c10 bl_0_10 br_0_10 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c10 bl_0_10 br_0_10 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c10 bl_0_10 br_0_10 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c10 bl_0_10 br_0_10 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c10 bl_0_10 br_0_10 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c10 bl_0_10 br_0_10 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c10 bl_0_10 br_0_10 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c10 bl_0_10 br_0_10 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c10 bl_0_10 br_0_10 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c10 bl_0_10 br_0_10 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c10 bl_0_10 br_0_10 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c10 bl_0_10 br_0_10 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c10 bl_0_10 br_0_10 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c10 bl_0_10 br_0_10 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c10 bl_0_10 br_0_10 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c10 bl_0_10 br_0_10 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c10 bl_0_10 br_0_10 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c10 bl_0_10 br_0_10 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c10 bl_0_10 br_0_10 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c10 bl_0_10 br_0_10 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c10 bl_0_10 br_0_10 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c10 bl_0_10 br_0_10 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c10 bl_0_10 br_0_10 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c10 bl_0_10 br_0_10 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c10 bl_0_10 br_0_10 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c10 bl_0_10 br_0_10 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c10 bl_0_10 br_0_10 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c11 bl_0_11 br_0_11 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c11 bl_0_11 br_0_11 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c11 bl_0_11 br_0_11 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c11 bl_0_11 br_0_11 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c11 bl_0_11 br_0_11 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c11 bl_0_11 br_0_11 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c11 bl_0_11 br_0_11 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c11 bl_0_11 br_0_11 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c11 bl_0_11 br_0_11 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c11 bl_0_11 br_0_11 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c11 bl_0_11 br_0_11 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c11 bl_0_11 br_0_11 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c11 bl_0_11 br_0_11 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c11 bl_0_11 br_0_11 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c11 bl_0_11 br_0_11 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c11 bl_0_11 br_0_11 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c11 bl_0_11 br_0_11 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c11 bl_0_11 br_0_11 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c11 bl_0_11 br_0_11 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c11 bl_0_11 br_0_11 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c11 bl_0_11 br_0_11 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c11 bl_0_11 br_0_11 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c11 bl_0_11 br_0_11 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c11 bl_0_11 br_0_11 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c11 bl_0_11 br_0_11 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c11 bl_0_11 br_0_11 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c11 bl_0_11 br_0_11 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c11 bl_0_11 br_0_11 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c11 bl_0_11 br_0_11 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c11 bl_0_11 br_0_11 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c11 bl_0_11 br_0_11 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c11 bl_0_11 br_0_11 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c12 bl_0_12 br_0_12 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c12 bl_0_12 br_0_12 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c12 bl_0_12 br_0_12 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c12 bl_0_12 br_0_12 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c12 bl_0_12 br_0_12 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c12 bl_0_12 br_0_12 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c12 bl_0_12 br_0_12 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c12 bl_0_12 br_0_12 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c12 bl_0_12 br_0_12 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c12 bl_0_12 br_0_12 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c12 bl_0_12 br_0_12 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c12 bl_0_12 br_0_12 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c12 bl_0_12 br_0_12 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c12 bl_0_12 br_0_12 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c12 bl_0_12 br_0_12 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c12 bl_0_12 br_0_12 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c12 bl_0_12 br_0_12 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c12 bl_0_12 br_0_12 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c12 bl_0_12 br_0_12 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c12 bl_0_12 br_0_12 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c12 bl_0_12 br_0_12 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c12 bl_0_12 br_0_12 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c12 bl_0_12 br_0_12 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c12 bl_0_12 br_0_12 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c12 bl_0_12 br_0_12 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c12 bl_0_12 br_0_12 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c12 bl_0_12 br_0_12 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c12 bl_0_12 br_0_12 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c12 bl_0_12 br_0_12 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c12 bl_0_12 br_0_12 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c12 bl_0_12 br_0_12 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c12 bl_0_12 br_0_12 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c13 bl_0_13 br_0_13 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c13 bl_0_13 br_0_13 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c13 bl_0_13 br_0_13 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c13 bl_0_13 br_0_13 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c13 bl_0_13 br_0_13 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c13 bl_0_13 br_0_13 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c13 bl_0_13 br_0_13 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c13 bl_0_13 br_0_13 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c13 bl_0_13 br_0_13 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c13 bl_0_13 br_0_13 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c13 bl_0_13 br_0_13 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c13 bl_0_13 br_0_13 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c13 bl_0_13 br_0_13 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c13 bl_0_13 br_0_13 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c13 bl_0_13 br_0_13 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c13 bl_0_13 br_0_13 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c13 bl_0_13 br_0_13 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c13 bl_0_13 br_0_13 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c13 bl_0_13 br_0_13 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c13 bl_0_13 br_0_13 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c13 bl_0_13 br_0_13 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c13 bl_0_13 br_0_13 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c13 bl_0_13 br_0_13 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c13 bl_0_13 br_0_13 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c13 bl_0_13 br_0_13 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c13 bl_0_13 br_0_13 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c13 bl_0_13 br_0_13 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c13 bl_0_13 br_0_13 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c13 bl_0_13 br_0_13 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c13 bl_0_13 br_0_13 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c13 bl_0_13 br_0_13 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c13 bl_0_13 br_0_13 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c14 bl_0_14 br_0_14 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c14 bl_0_14 br_0_14 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c14 bl_0_14 br_0_14 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c14 bl_0_14 br_0_14 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c14 bl_0_14 br_0_14 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c14 bl_0_14 br_0_14 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c14 bl_0_14 br_0_14 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c14 bl_0_14 br_0_14 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c14 bl_0_14 br_0_14 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c14 bl_0_14 br_0_14 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c14 bl_0_14 br_0_14 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c14 bl_0_14 br_0_14 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c14 bl_0_14 br_0_14 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c14 bl_0_14 br_0_14 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c14 bl_0_14 br_0_14 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c14 bl_0_14 br_0_14 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c14 bl_0_14 br_0_14 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c14 bl_0_14 br_0_14 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c14 bl_0_14 br_0_14 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c14 bl_0_14 br_0_14 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c14 bl_0_14 br_0_14 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c14 bl_0_14 br_0_14 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c14 bl_0_14 br_0_14 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c14 bl_0_14 br_0_14 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c14 bl_0_14 br_0_14 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c14 bl_0_14 br_0_14 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c14 bl_0_14 br_0_14 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c14 bl_0_14 br_0_14 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c14 bl_0_14 br_0_14 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c14 bl_0_14 br_0_14 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c14 bl_0_14 br_0_14 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c14 bl_0_14 br_0_14 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c15 bl_0_15 br_0_15 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c15 bl_0_15 br_0_15 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c15 bl_0_15 br_0_15 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c15 bl_0_15 br_0_15 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c15 bl_0_15 br_0_15 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c15 bl_0_15 br_0_15 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c15 bl_0_15 br_0_15 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c15 bl_0_15 br_0_15 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c15 bl_0_15 br_0_15 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c15 bl_0_15 br_0_15 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c15 bl_0_15 br_0_15 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c15 bl_0_15 br_0_15 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c15 bl_0_15 br_0_15 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c15 bl_0_15 br_0_15 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c15 bl_0_15 br_0_15 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c15 bl_0_15 br_0_15 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c15 bl_0_15 br_0_15 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c15 bl_0_15 br_0_15 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c15 bl_0_15 br_0_15 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c15 bl_0_15 br_0_15 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c15 bl_0_15 br_0_15 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c15 bl_0_15 br_0_15 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c15 bl_0_15 br_0_15 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c15 bl_0_15 br_0_15 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c15 bl_0_15 br_0_15 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c15 bl_0_15 br_0_15 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c15 bl_0_15 br_0_15 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c15 bl_0_15 br_0_15 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c15 bl_0_15 br_0_15 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c15 bl_0_15 br_0_15 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c15 bl_0_15 br_0_15 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c15 bl_0_15 br_0_15 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c16 bl_0_16 br_0_16 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c16 bl_0_16 br_0_16 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c16 bl_0_16 br_0_16 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c16 bl_0_16 br_0_16 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c16 bl_0_16 br_0_16 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c16 bl_0_16 br_0_16 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c16 bl_0_16 br_0_16 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c16 bl_0_16 br_0_16 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c16 bl_0_16 br_0_16 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c16 bl_0_16 br_0_16 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c16 bl_0_16 br_0_16 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c16 bl_0_16 br_0_16 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c16 bl_0_16 br_0_16 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c16 bl_0_16 br_0_16 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c16 bl_0_16 br_0_16 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c16 bl_0_16 br_0_16 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c16 bl_0_16 br_0_16 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c16 bl_0_16 br_0_16 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c16 bl_0_16 br_0_16 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c16 bl_0_16 br_0_16 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c16 bl_0_16 br_0_16 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c16 bl_0_16 br_0_16 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c16 bl_0_16 br_0_16 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c16 bl_0_16 br_0_16 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c16 bl_0_16 br_0_16 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c16 bl_0_16 br_0_16 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c16 bl_0_16 br_0_16 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c16 bl_0_16 br_0_16 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c16 bl_0_16 br_0_16 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c16 bl_0_16 br_0_16 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c16 bl_0_16 br_0_16 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c16 bl_0_16 br_0_16 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c17 bl_0_17 br_0_17 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c17 bl_0_17 br_0_17 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c17 bl_0_17 br_0_17 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c17 bl_0_17 br_0_17 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c17 bl_0_17 br_0_17 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c17 bl_0_17 br_0_17 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c17 bl_0_17 br_0_17 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c17 bl_0_17 br_0_17 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c17 bl_0_17 br_0_17 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c17 bl_0_17 br_0_17 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c17 bl_0_17 br_0_17 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c17 bl_0_17 br_0_17 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c17 bl_0_17 br_0_17 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c17 bl_0_17 br_0_17 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c17 bl_0_17 br_0_17 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c17 bl_0_17 br_0_17 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c17 bl_0_17 br_0_17 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c17 bl_0_17 br_0_17 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c17 bl_0_17 br_0_17 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c17 bl_0_17 br_0_17 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c17 bl_0_17 br_0_17 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c17 bl_0_17 br_0_17 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c17 bl_0_17 br_0_17 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c17 bl_0_17 br_0_17 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c17 bl_0_17 br_0_17 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c17 bl_0_17 br_0_17 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c17 bl_0_17 br_0_17 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c17 bl_0_17 br_0_17 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c17 bl_0_17 br_0_17 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c17 bl_0_17 br_0_17 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c17 bl_0_17 br_0_17 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c17 bl_0_17 br_0_17 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c18 bl_0_18 br_0_18 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c18 bl_0_18 br_0_18 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c18 bl_0_18 br_0_18 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c18 bl_0_18 br_0_18 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c18 bl_0_18 br_0_18 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c18 bl_0_18 br_0_18 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c18 bl_0_18 br_0_18 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c18 bl_0_18 br_0_18 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c18 bl_0_18 br_0_18 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c18 bl_0_18 br_0_18 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c18 bl_0_18 br_0_18 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c18 bl_0_18 br_0_18 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c18 bl_0_18 br_0_18 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c18 bl_0_18 br_0_18 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c18 bl_0_18 br_0_18 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c18 bl_0_18 br_0_18 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c18 bl_0_18 br_0_18 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c18 bl_0_18 br_0_18 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c18 bl_0_18 br_0_18 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c18 bl_0_18 br_0_18 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c18 bl_0_18 br_0_18 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c18 bl_0_18 br_0_18 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c18 bl_0_18 br_0_18 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c18 bl_0_18 br_0_18 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c18 bl_0_18 br_0_18 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c18 bl_0_18 br_0_18 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c18 bl_0_18 br_0_18 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c18 bl_0_18 br_0_18 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c18 bl_0_18 br_0_18 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c18 bl_0_18 br_0_18 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c18 bl_0_18 br_0_18 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c18 bl_0_18 br_0_18 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c19 bl_0_19 br_0_19 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c19 bl_0_19 br_0_19 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c19 bl_0_19 br_0_19 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c19 bl_0_19 br_0_19 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c19 bl_0_19 br_0_19 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c19 bl_0_19 br_0_19 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c19 bl_0_19 br_0_19 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c19 bl_0_19 br_0_19 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c19 bl_0_19 br_0_19 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c19 bl_0_19 br_0_19 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c19 bl_0_19 br_0_19 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c19 bl_0_19 br_0_19 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c19 bl_0_19 br_0_19 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c19 bl_0_19 br_0_19 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c19 bl_0_19 br_0_19 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c19 bl_0_19 br_0_19 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c19 bl_0_19 br_0_19 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c19 bl_0_19 br_0_19 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c19 bl_0_19 br_0_19 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c19 bl_0_19 br_0_19 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c19 bl_0_19 br_0_19 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c19 bl_0_19 br_0_19 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c19 bl_0_19 br_0_19 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c19 bl_0_19 br_0_19 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c19 bl_0_19 br_0_19 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c19 bl_0_19 br_0_19 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c19 bl_0_19 br_0_19 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c19 bl_0_19 br_0_19 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c19 bl_0_19 br_0_19 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c19 bl_0_19 br_0_19 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c19 bl_0_19 br_0_19 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c19 bl_0_19 br_0_19 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c20 bl_0_20 br_0_20 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c20 bl_0_20 br_0_20 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c20 bl_0_20 br_0_20 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c20 bl_0_20 br_0_20 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c20 bl_0_20 br_0_20 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c20 bl_0_20 br_0_20 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c20 bl_0_20 br_0_20 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c20 bl_0_20 br_0_20 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c20 bl_0_20 br_0_20 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c20 bl_0_20 br_0_20 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c20 bl_0_20 br_0_20 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c20 bl_0_20 br_0_20 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c20 bl_0_20 br_0_20 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c20 bl_0_20 br_0_20 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c20 bl_0_20 br_0_20 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c20 bl_0_20 br_0_20 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c20 bl_0_20 br_0_20 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c20 bl_0_20 br_0_20 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c20 bl_0_20 br_0_20 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c20 bl_0_20 br_0_20 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c20 bl_0_20 br_0_20 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c20 bl_0_20 br_0_20 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c20 bl_0_20 br_0_20 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c20 bl_0_20 br_0_20 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c20 bl_0_20 br_0_20 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c20 bl_0_20 br_0_20 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c20 bl_0_20 br_0_20 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c20 bl_0_20 br_0_20 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c20 bl_0_20 br_0_20 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c20 bl_0_20 br_0_20 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c20 bl_0_20 br_0_20 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c20 bl_0_20 br_0_20 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c21 bl_0_21 br_0_21 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c21 bl_0_21 br_0_21 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c21 bl_0_21 br_0_21 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c21 bl_0_21 br_0_21 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c21 bl_0_21 br_0_21 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c21 bl_0_21 br_0_21 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c21 bl_0_21 br_0_21 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c21 bl_0_21 br_0_21 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c21 bl_0_21 br_0_21 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c21 bl_0_21 br_0_21 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c21 bl_0_21 br_0_21 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c21 bl_0_21 br_0_21 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c21 bl_0_21 br_0_21 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c21 bl_0_21 br_0_21 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c21 bl_0_21 br_0_21 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c21 bl_0_21 br_0_21 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c21 bl_0_21 br_0_21 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c21 bl_0_21 br_0_21 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c21 bl_0_21 br_0_21 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c21 bl_0_21 br_0_21 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c21 bl_0_21 br_0_21 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c21 bl_0_21 br_0_21 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c21 bl_0_21 br_0_21 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c21 bl_0_21 br_0_21 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c21 bl_0_21 br_0_21 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c21 bl_0_21 br_0_21 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c21 bl_0_21 br_0_21 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c21 bl_0_21 br_0_21 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c21 bl_0_21 br_0_21 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c21 bl_0_21 br_0_21 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c21 bl_0_21 br_0_21 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c21 bl_0_21 br_0_21 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c22 bl_0_22 br_0_22 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c22 bl_0_22 br_0_22 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c22 bl_0_22 br_0_22 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c22 bl_0_22 br_0_22 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c22 bl_0_22 br_0_22 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c22 bl_0_22 br_0_22 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c22 bl_0_22 br_0_22 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c22 bl_0_22 br_0_22 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c22 bl_0_22 br_0_22 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c22 bl_0_22 br_0_22 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c22 bl_0_22 br_0_22 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c22 bl_0_22 br_0_22 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c22 bl_0_22 br_0_22 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c22 bl_0_22 br_0_22 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c22 bl_0_22 br_0_22 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c22 bl_0_22 br_0_22 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c22 bl_0_22 br_0_22 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c22 bl_0_22 br_0_22 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c22 bl_0_22 br_0_22 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c22 bl_0_22 br_0_22 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c22 bl_0_22 br_0_22 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c22 bl_0_22 br_0_22 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c22 bl_0_22 br_0_22 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c22 bl_0_22 br_0_22 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c22 bl_0_22 br_0_22 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c22 bl_0_22 br_0_22 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c22 bl_0_22 br_0_22 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c22 bl_0_22 br_0_22 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c22 bl_0_22 br_0_22 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c22 bl_0_22 br_0_22 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c22 bl_0_22 br_0_22 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c22 bl_0_22 br_0_22 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c23 bl_0_23 br_0_23 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c23 bl_0_23 br_0_23 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c23 bl_0_23 br_0_23 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c23 bl_0_23 br_0_23 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c23 bl_0_23 br_0_23 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c23 bl_0_23 br_0_23 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c23 bl_0_23 br_0_23 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c23 bl_0_23 br_0_23 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c23 bl_0_23 br_0_23 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c23 bl_0_23 br_0_23 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c23 bl_0_23 br_0_23 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c23 bl_0_23 br_0_23 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c23 bl_0_23 br_0_23 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c23 bl_0_23 br_0_23 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c23 bl_0_23 br_0_23 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c23 bl_0_23 br_0_23 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c23 bl_0_23 br_0_23 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c23 bl_0_23 br_0_23 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c23 bl_0_23 br_0_23 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c23 bl_0_23 br_0_23 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c23 bl_0_23 br_0_23 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c23 bl_0_23 br_0_23 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c23 bl_0_23 br_0_23 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c23 bl_0_23 br_0_23 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c23 bl_0_23 br_0_23 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c23 bl_0_23 br_0_23 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c23 bl_0_23 br_0_23 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c23 bl_0_23 br_0_23 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c23 bl_0_23 br_0_23 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c23 bl_0_23 br_0_23 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c23 bl_0_23 br_0_23 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c23 bl_0_23 br_0_23 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c24 bl_0_24 br_0_24 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c24 bl_0_24 br_0_24 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c24 bl_0_24 br_0_24 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c24 bl_0_24 br_0_24 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c24 bl_0_24 br_0_24 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c24 bl_0_24 br_0_24 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c24 bl_0_24 br_0_24 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c24 bl_0_24 br_0_24 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c24 bl_0_24 br_0_24 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c24 bl_0_24 br_0_24 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c24 bl_0_24 br_0_24 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c24 bl_0_24 br_0_24 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c24 bl_0_24 br_0_24 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c24 bl_0_24 br_0_24 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c24 bl_0_24 br_0_24 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c24 bl_0_24 br_0_24 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c24 bl_0_24 br_0_24 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c24 bl_0_24 br_0_24 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c24 bl_0_24 br_0_24 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c24 bl_0_24 br_0_24 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c24 bl_0_24 br_0_24 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c24 bl_0_24 br_0_24 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c24 bl_0_24 br_0_24 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c24 bl_0_24 br_0_24 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c24 bl_0_24 br_0_24 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c24 bl_0_24 br_0_24 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c24 bl_0_24 br_0_24 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c24 bl_0_24 br_0_24 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c24 bl_0_24 br_0_24 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c24 bl_0_24 br_0_24 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c24 bl_0_24 br_0_24 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c24 bl_0_24 br_0_24 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c25 bl_0_25 br_0_25 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c25 bl_0_25 br_0_25 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c25 bl_0_25 br_0_25 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c25 bl_0_25 br_0_25 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c25 bl_0_25 br_0_25 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c25 bl_0_25 br_0_25 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c25 bl_0_25 br_0_25 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c25 bl_0_25 br_0_25 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c25 bl_0_25 br_0_25 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c25 bl_0_25 br_0_25 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c25 bl_0_25 br_0_25 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c25 bl_0_25 br_0_25 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c25 bl_0_25 br_0_25 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c25 bl_0_25 br_0_25 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c25 bl_0_25 br_0_25 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c25 bl_0_25 br_0_25 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c25 bl_0_25 br_0_25 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c25 bl_0_25 br_0_25 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c25 bl_0_25 br_0_25 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c25 bl_0_25 br_0_25 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c25 bl_0_25 br_0_25 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c25 bl_0_25 br_0_25 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c25 bl_0_25 br_0_25 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c25 bl_0_25 br_0_25 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c25 bl_0_25 br_0_25 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c25 bl_0_25 br_0_25 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c25 bl_0_25 br_0_25 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c25 bl_0_25 br_0_25 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c25 bl_0_25 br_0_25 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c25 bl_0_25 br_0_25 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c25 bl_0_25 br_0_25 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c25 bl_0_25 br_0_25 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c26 bl_0_26 br_0_26 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c26 bl_0_26 br_0_26 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c26 bl_0_26 br_0_26 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c26 bl_0_26 br_0_26 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c26 bl_0_26 br_0_26 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c26 bl_0_26 br_0_26 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c26 bl_0_26 br_0_26 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c26 bl_0_26 br_0_26 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c26 bl_0_26 br_0_26 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c26 bl_0_26 br_0_26 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c26 bl_0_26 br_0_26 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c26 bl_0_26 br_0_26 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c26 bl_0_26 br_0_26 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c26 bl_0_26 br_0_26 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c26 bl_0_26 br_0_26 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c26 bl_0_26 br_0_26 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c26 bl_0_26 br_0_26 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c26 bl_0_26 br_0_26 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c26 bl_0_26 br_0_26 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c26 bl_0_26 br_0_26 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c26 bl_0_26 br_0_26 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c26 bl_0_26 br_0_26 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c26 bl_0_26 br_0_26 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c26 bl_0_26 br_0_26 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c26 bl_0_26 br_0_26 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c26 bl_0_26 br_0_26 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c26 bl_0_26 br_0_26 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c26 bl_0_26 br_0_26 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c26 bl_0_26 br_0_26 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c26 bl_0_26 br_0_26 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c26 bl_0_26 br_0_26 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c26 bl_0_26 br_0_26 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c27 bl_0_27 br_0_27 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c27 bl_0_27 br_0_27 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c27 bl_0_27 br_0_27 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c27 bl_0_27 br_0_27 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c27 bl_0_27 br_0_27 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c27 bl_0_27 br_0_27 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c27 bl_0_27 br_0_27 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c27 bl_0_27 br_0_27 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c27 bl_0_27 br_0_27 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c27 bl_0_27 br_0_27 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c27 bl_0_27 br_0_27 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c27 bl_0_27 br_0_27 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c27 bl_0_27 br_0_27 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c27 bl_0_27 br_0_27 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c27 bl_0_27 br_0_27 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c27 bl_0_27 br_0_27 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c27 bl_0_27 br_0_27 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c27 bl_0_27 br_0_27 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c27 bl_0_27 br_0_27 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c27 bl_0_27 br_0_27 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c27 bl_0_27 br_0_27 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c27 bl_0_27 br_0_27 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c27 bl_0_27 br_0_27 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c27 bl_0_27 br_0_27 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c27 bl_0_27 br_0_27 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c27 bl_0_27 br_0_27 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c27 bl_0_27 br_0_27 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c27 bl_0_27 br_0_27 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c27 bl_0_27 br_0_27 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c27 bl_0_27 br_0_27 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c27 bl_0_27 br_0_27 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c27 bl_0_27 br_0_27 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c28 bl_0_28 br_0_28 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c28 bl_0_28 br_0_28 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c28 bl_0_28 br_0_28 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c28 bl_0_28 br_0_28 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c28 bl_0_28 br_0_28 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c28 bl_0_28 br_0_28 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c28 bl_0_28 br_0_28 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c28 bl_0_28 br_0_28 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c28 bl_0_28 br_0_28 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c28 bl_0_28 br_0_28 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c28 bl_0_28 br_0_28 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c28 bl_0_28 br_0_28 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c28 bl_0_28 br_0_28 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c28 bl_0_28 br_0_28 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c28 bl_0_28 br_0_28 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c28 bl_0_28 br_0_28 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c28 bl_0_28 br_0_28 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c28 bl_0_28 br_0_28 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c28 bl_0_28 br_0_28 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c28 bl_0_28 br_0_28 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c28 bl_0_28 br_0_28 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c28 bl_0_28 br_0_28 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c28 bl_0_28 br_0_28 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c28 bl_0_28 br_0_28 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c28 bl_0_28 br_0_28 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c28 bl_0_28 br_0_28 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c28 bl_0_28 br_0_28 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c28 bl_0_28 br_0_28 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c28 bl_0_28 br_0_28 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c28 bl_0_28 br_0_28 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c28 bl_0_28 br_0_28 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c28 bl_0_28 br_0_28 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c29 bl_0_29 br_0_29 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c29 bl_0_29 br_0_29 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c29 bl_0_29 br_0_29 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c29 bl_0_29 br_0_29 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c29 bl_0_29 br_0_29 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c29 bl_0_29 br_0_29 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c29 bl_0_29 br_0_29 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c29 bl_0_29 br_0_29 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c29 bl_0_29 br_0_29 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c29 bl_0_29 br_0_29 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c29 bl_0_29 br_0_29 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c29 bl_0_29 br_0_29 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c29 bl_0_29 br_0_29 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c29 bl_0_29 br_0_29 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c29 bl_0_29 br_0_29 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c29 bl_0_29 br_0_29 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c29 bl_0_29 br_0_29 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c29 bl_0_29 br_0_29 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c29 bl_0_29 br_0_29 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c29 bl_0_29 br_0_29 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c29 bl_0_29 br_0_29 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c29 bl_0_29 br_0_29 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c29 bl_0_29 br_0_29 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c29 bl_0_29 br_0_29 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c29 bl_0_29 br_0_29 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c29 bl_0_29 br_0_29 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c29 bl_0_29 br_0_29 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c29 bl_0_29 br_0_29 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c29 bl_0_29 br_0_29 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c29 bl_0_29 br_0_29 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c29 bl_0_29 br_0_29 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c29 bl_0_29 br_0_29 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c30 bl_0_30 br_0_30 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c30 bl_0_30 br_0_30 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c30 bl_0_30 br_0_30 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c30 bl_0_30 br_0_30 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c30 bl_0_30 br_0_30 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c30 bl_0_30 br_0_30 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c30 bl_0_30 br_0_30 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c30 bl_0_30 br_0_30 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c30 bl_0_30 br_0_30 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c30 bl_0_30 br_0_30 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c30 bl_0_30 br_0_30 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c30 bl_0_30 br_0_30 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c30 bl_0_30 br_0_30 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c30 bl_0_30 br_0_30 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c30 bl_0_30 br_0_30 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c30 bl_0_30 br_0_30 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c30 bl_0_30 br_0_30 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c30 bl_0_30 br_0_30 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c30 bl_0_30 br_0_30 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c30 bl_0_30 br_0_30 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c30 bl_0_30 br_0_30 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c30 bl_0_30 br_0_30 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c30 bl_0_30 br_0_30 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c30 bl_0_30 br_0_30 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c30 bl_0_30 br_0_30 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c30 bl_0_30 br_0_30 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c30 bl_0_30 br_0_30 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c30 bl_0_30 br_0_30 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c30 bl_0_30 br_0_30 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c30 bl_0_30 br_0_30 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c30 bl_0_30 br_0_30 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c30 bl_0_30 br_0_30 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c31 bl_0_31 br_0_31 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c31 bl_0_31 br_0_31 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c31 bl_0_31 br_0_31 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c31 bl_0_31 br_0_31 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c31 bl_0_31 br_0_31 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c31 bl_0_31 br_0_31 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c31 bl_0_31 br_0_31 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c31 bl_0_31 br_0_31 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c31 bl_0_31 br_0_31 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c31 bl_0_31 br_0_31 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c31 bl_0_31 br_0_31 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c31 bl_0_31 br_0_31 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c31 bl_0_31 br_0_31 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c31 bl_0_31 br_0_31 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c31 bl_0_31 br_0_31 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c31 bl_0_31 br_0_31 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c31 bl_0_31 br_0_31 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c31 bl_0_31 br_0_31 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c31 bl_0_31 br_0_31 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c31 bl_0_31 br_0_31 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c31 bl_0_31 br_0_31 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c31 bl_0_31 br_0_31 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c31 bl_0_31 br_0_31 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c31 bl_0_31 br_0_31 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c31 bl_0_31 br_0_31 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c31 bl_0_31 br_0_31 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c31 bl_0_31 br_0_31 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c31 bl_0_31 br_0_31 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c31 bl_0_31 br_0_31 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c31 bl_0_31 br_0_31 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c31 bl_0_31 br_0_31 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c31 bl_0_31 br_0_31 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c32 bl_0_32 br_0_32 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c32 bl_0_32 br_0_32 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c32 bl_0_32 br_0_32 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c32 bl_0_32 br_0_32 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c32 bl_0_32 br_0_32 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c32 bl_0_32 br_0_32 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c32 bl_0_32 br_0_32 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c32 bl_0_32 br_0_32 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c32 bl_0_32 br_0_32 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c32 bl_0_32 br_0_32 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c32 bl_0_32 br_0_32 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c32 bl_0_32 br_0_32 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c32 bl_0_32 br_0_32 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c32 bl_0_32 br_0_32 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c32 bl_0_32 br_0_32 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c32 bl_0_32 br_0_32 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c32 bl_0_32 br_0_32 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c32 bl_0_32 br_0_32 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c32 bl_0_32 br_0_32 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c32 bl_0_32 br_0_32 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c32 bl_0_32 br_0_32 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c32 bl_0_32 br_0_32 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c32 bl_0_32 br_0_32 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c32 bl_0_32 br_0_32 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c32 bl_0_32 br_0_32 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c32 bl_0_32 br_0_32 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c32 bl_0_32 br_0_32 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c32 bl_0_32 br_0_32 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c32 bl_0_32 br_0_32 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c32 bl_0_32 br_0_32 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c32 bl_0_32 br_0_32 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c32 bl_0_32 br_0_32 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c32 bl_0_32 br_0_32 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c32 bl_0_32 br_0_32 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c32 bl_0_32 br_0_32 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c32 bl_0_32 br_0_32 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c32 bl_0_32 br_0_32 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c32 bl_0_32 br_0_32 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c32 bl_0_32 br_0_32 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c32 bl_0_32 br_0_32 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c32 bl_0_32 br_0_32 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c32 bl_0_32 br_0_32 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c32 bl_0_32 br_0_32 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c32 bl_0_32 br_0_32 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c32 bl_0_32 br_0_32 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c32 bl_0_32 br_0_32 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c32 bl_0_32 br_0_32 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c32 bl_0_32 br_0_32 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c32 bl_0_32 br_0_32 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c32 bl_0_32 br_0_32 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c32 bl_0_32 br_0_32 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c32 bl_0_32 br_0_32 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c32 bl_0_32 br_0_32 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c32 bl_0_32 br_0_32 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c32 bl_0_32 br_0_32 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c32 bl_0_32 br_0_32 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c32 bl_0_32 br_0_32 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c32 bl_0_32 br_0_32 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c32 bl_0_32 br_0_32 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c32 bl_0_32 br_0_32 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c32 bl_0_32 br_0_32 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c32 bl_0_32 br_0_32 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c32 bl_0_32 br_0_32 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c32 bl_0_32 br_0_32 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c33 bl_0_33 br_0_33 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c33 bl_0_33 br_0_33 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c33 bl_0_33 br_0_33 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c33 bl_0_33 br_0_33 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c33 bl_0_33 br_0_33 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c33 bl_0_33 br_0_33 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c33 bl_0_33 br_0_33 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c33 bl_0_33 br_0_33 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c33 bl_0_33 br_0_33 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c33 bl_0_33 br_0_33 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c33 bl_0_33 br_0_33 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c33 bl_0_33 br_0_33 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c33 bl_0_33 br_0_33 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c33 bl_0_33 br_0_33 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c33 bl_0_33 br_0_33 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c33 bl_0_33 br_0_33 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c33 bl_0_33 br_0_33 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c33 bl_0_33 br_0_33 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c33 bl_0_33 br_0_33 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c33 bl_0_33 br_0_33 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c33 bl_0_33 br_0_33 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c33 bl_0_33 br_0_33 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c33 bl_0_33 br_0_33 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c33 bl_0_33 br_0_33 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c33 bl_0_33 br_0_33 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c33 bl_0_33 br_0_33 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c33 bl_0_33 br_0_33 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c33 bl_0_33 br_0_33 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c33 bl_0_33 br_0_33 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c33 bl_0_33 br_0_33 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c33 bl_0_33 br_0_33 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c33 bl_0_33 br_0_33 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c33 bl_0_33 br_0_33 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c33 bl_0_33 br_0_33 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c33 bl_0_33 br_0_33 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c33 bl_0_33 br_0_33 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c33 bl_0_33 br_0_33 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c33 bl_0_33 br_0_33 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c33 bl_0_33 br_0_33 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c33 bl_0_33 br_0_33 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c33 bl_0_33 br_0_33 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c33 bl_0_33 br_0_33 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c33 bl_0_33 br_0_33 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c33 bl_0_33 br_0_33 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c33 bl_0_33 br_0_33 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c33 bl_0_33 br_0_33 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c33 bl_0_33 br_0_33 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c33 bl_0_33 br_0_33 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c33 bl_0_33 br_0_33 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c33 bl_0_33 br_0_33 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c33 bl_0_33 br_0_33 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c33 bl_0_33 br_0_33 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c33 bl_0_33 br_0_33 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c33 bl_0_33 br_0_33 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c33 bl_0_33 br_0_33 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c33 bl_0_33 br_0_33 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c33 bl_0_33 br_0_33 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c33 bl_0_33 br_0_33 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c33 bl_0_33 br_0_33 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c33 bl_0_33 br_0_33 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c33 bl_0_33 br_0_33 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c33 bl_0_33 br_0_33 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c33 bl_0_33 br_0_33 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c33 bl_0_33 br_0_33 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c34 bl_0_34 br_0_34 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c34 bl_0_34 br_0_34 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c34 bl_0_34 br_0_34 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c34 bl_0_34 br_0_34 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c34 bl_0_34 br_0_34 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c34 bl_0_34 br_0_34 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c34 bl_0_34 br_0_34 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c34 bl_0_34 br_0_34 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c34 bl_0_34 br_0_34 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c34 bl_0_34 br_0_34 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c34 bl_0_34 br_0_34 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c34 bl_0_34 br_0_34 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c34 bl_0_34 br_0_34 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c34 bl_0_34 br_0_34 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c34 bl_0_34 br_0_34 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c34 bl_0_34 br_0_34 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c34 bl_0_34 br_0_34 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c34 bl_0_34 br_0_34 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c34 bl_0_34 br_0_34 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c34 bl_0_34 br_0_34 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c34 bl_0_34 br_0_34 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c34 bl_0_34 br_0_34 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c34 bl_0_34 br_0_34 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c34 bl_0_34 br_0_34 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c34 bl_0_34 br_0_34 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c34 bl_0_34 br_0_34 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c34 bl_0_34 br_0_34 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c34 bl_0_34 br_0_34 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c34 bl_0_34 br_0_34 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c34 bl_0_34 br_0_34 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c34 bl_0_34 br_0_34 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c34 bl_0_34 br_0_34 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c34 bl_0_34 br_0_34 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c34 bl_0_34 br_0_34 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c34 bl_0_34 br_0_34 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c34 bl_0_34 br_0_34 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c34 bl_0_34 br_0_34 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c34 bl_0_34 br_0_34 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c34 bl_0_34 br_0_34 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c34 bl_0_34 br_0_34 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c34 bl_0_34 br_0_34 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c34 bl_0_34 br_0_34 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c34 bl_0_34 br_0_34 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c34 bl_0_34 br_0_34 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c34 bl_0_34 br_0_34 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c34 bl_0_34 br_0_34 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c34 bl_0_34 br_0_34 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c34 bl_0_34 br_0_34 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c34 bl_0_34 br_0_34 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c34 bl_0_34 br_0_34 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c34 bl_0_34 br_0_34 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c34 bl_0_34 br_0_34 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c34 bl_0_34 br_0_34 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c34 bl_0_34 br_0_34 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c34 bl_0_34 br_0_34 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c34 bl_0_34 br_0_34 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c34 bl_0_34 br_0_34 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c34 bl_0_34 br_0_34 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c34 bl_0_34 br_0_34 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c34 bl_0_34 br_0_34 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c34 bl_0_34 br_0_34 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c34 bl_0_34 br_0_34 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c34 bl_0_34 br_0_34 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c34 bl_0_34 br_0_34 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c35 bl_0_35 br_0_35 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c35 bl_0_35 br_0_35 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c35 bl_0_35 br_0_35 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c35 bl_0_35 br_0_35 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c35 bl_0_35 br_0_35 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c35 bl_0_35 br_0_35 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c35 bl_0_35 br_0_35 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c35 bl_0_35 br_0_35 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c35 bl_0_35 br_0_35 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c35 bl_0_35 br_0_35 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c35 bl_0_35 br_0_35 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c35 bl_0_35 br_0_35 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c35 bl_0_35 br_0_35 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c35 bl_0_35 br_0_35 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c35 bl_0_35 br_0_35 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c35 bl_0_35 br_0_35 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c35 bl_0_35 br_0_35 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c35 bl_0_35 br_0_35 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c35 bl_0_35 br_0_35 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c35 bl_0_35 br_0_35 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c35 bl_0_35 br_0_35 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c35 bl_0_35 br_0_35 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c35 bl_0_35 br_0_35 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c35 bl_0_35 br_0_35 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c35 bl_0_35 br_0_35 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c35 bl_0_35 br_0_35 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c35 bl_0_35 br_0_35 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c35 bl_0_35 br_0_35 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c35 bl_0_35 br_0_35 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c35 bl_0_35 br_0_35 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c35 bl_0_35 br_0_35 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c35 bl_0_35 br_0_35 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c35 bl_0_35 br_0_35 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c35 bl_0_35 br_0_35 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c35 bl_0_35 br_0_35 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c35 bl_0_35 br_0_35 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c35 bl_0_35 br_0_35 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c35 bl_0_35 br_0_35 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c35 bl_0_35 br_0_35 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c35 bl_0_35 br_0_35 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c35 bl_0_35 br_0_35 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c35 bl_0_35 br_0_35 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c35 bl_0_35 br_0_35 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c35 bl_0_35 br_0_35 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c35 bl_0_35 br_0_35 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c35 bl_0_35 br_0_35 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c35 bl_0_35 br_0_35 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c35 bl_0_35 br_0_35 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c35 bl_0_35 br_0_35 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c35 bl_0_35 br_0_35 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c35 bl_0_35 br_0_35 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c35 bl_0_35 br_0_35 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c35 bl_0_35 br_0_35 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c35 bl_0_35 br_0_35 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c35 bl_0_35 br_0_35 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c35 bl_0_35 br_0_35 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c35 bl_0_35 br_0_35 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c35 bl_0_35 br_0_35 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c35 bl_0_35 br_0_35 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c35 bl_0_35 br_0_35 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c35 bl_0_35 br_0_35 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c35 bl_0_35 br_0_35 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c35 bl_0_35 br_0_35 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c35 bl_0_35 br_0_35 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c36 bl_0_36 br_0_36 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c36 bl_0_36 br_0_36 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c36 bl_0_36 br_0_36 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c36 bl_0_36 br_0_36 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c36 bl_0_36 br_0_36 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c36 bl_0_36 br_0_36 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c36 bl_0_36 br_0_36 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c36 bl_0_36 br_0_36 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c36 bl_0_36 br_0_36 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c36 bl_0_36 br_0_36 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c36 bl_0_36 br_0_36 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c36 bl_0_36 br_0_36 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c36 bl_0_36 br_0_36 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c36 bl_0_36 br_0_36 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c36 bl_0_36 br_0_36 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c36 bl_0_36 br_0_36 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c36 bl_0_36 br_0_36 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c36 bl_0_36 br_0_36 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c36 bl_0_36 br_0_36 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c36 bl_0_36 br_0_36 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c36 bl_0_36 br_0_36 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c36 bl_0_36 br_0_36 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c36 bl_0_36 br_0_36 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c36 bl_0_36 br_0_36 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c36 bl_0_36 br_0_36 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c36 bl_0_36 br_0_36 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c36 bl_0_36 br_0_36 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c36 bl_0_36 br_0_36 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c36 bl_0_36 br_0_36 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c36 bl_0_36 br_0_36 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c36 bl_0_36 br_0_36 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c36 bl_0_36 br_0_36 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c36 bl_0_36 br_0_36 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c36 bl_0_36 br_0_36 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c36 bl_0_36 br_0_36 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c36 bl_0_36 br_0_36 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c36 bl_0_36 br_0_36 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c36 bl_0_36 br_0_36 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c36 bl_0_36 br_0_36 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c36 bl_0_36 br_0_36 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c36 bl_0_36 br_0_36 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c36 bl_0_36 br_0_36 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c36 bl_0_36 br_0_36 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c36 bl_0_36 br_0_36 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c36 bl_0_36 br_0_36 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c36 bl_0_36 br_0_36 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c36 bl_0_36 br_0_36 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c36 bl_0_36 br_0_36 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c36 bl_0_36 br_0_36 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c36 bl_0_36 br_0_36 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c36 bl_0_36 br_0_36 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c36 bl_0_36 br_0_36 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c36 bl_0_36 br_0_36 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c36 bl_0_36 br_0_36 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c36 bl_0_36 br_0_36 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c36 bl_0_36 br_0_36 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c36 bl_0_36 br_0_36 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c36 bl_0_36 br_0_36 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c36 bl_0_36 br_0_36 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c36 bl_0_36 br_0_36 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c36 bl_0_36 br_0_36 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c36 bl_0_36 br_0_36 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c36 bl_0_36 br_0_36 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c36 bl_0_36 br_0_36 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c37 bl_0_37 br_0_37 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c37 bl_0_37 br_0_37 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c37 bl_0_37 br_0_37 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c37 bl_0_37 br_0_37 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c37 bl_0_37 br_0_37 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c37 bl_0_37 br_0_37 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c37 bl_0_37 br_0_37 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c37 bl_0_37 br_0_37 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c37 bl_0_37 br_0_37 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c37 bl_0_37 br_0_37 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c37 bl_0_37 br_0_37 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c37 bl_0_37 br_0_37 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c37 bl_0_37 br_0_37 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c37 bl_0_37 br_0_37 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c37 bl_0_37 br_0_37 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c37 bl_0_37 br_0_37 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c37 bl_0_37 br_0_37 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c37 bl_0_37 br_0_37 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c37 bl_0_37 br_0_37 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c37 bl_0_37 br_0_37 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c37 bl_0_37 br_0_37 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c37 bl_0_37 br_0_37 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c37 bl_0_37 br_0_37 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c37 bl_0_37 br_0_37 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c37 bl_0_37 br_0_37 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c37 bl_0_37 br_0_37 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c37 bl_0_37 br_0_37 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c37 bl_0_37 br_0_37 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c37 bl_0_37 br_0_37 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c37 bl_0_37 br_0_37 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c37 bl_0_37 br_0_37 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c37 bl_0_37 br_0_37 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c37 bl_0_37 br_0_37 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c37 bl_0_37 br_0_37 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c37 bl_0_37 br_0_37 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c37 bl_0_37 br_0_37 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c37 bl_0_37 br_0_37 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c37 bl_0_37 br_0_37 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c37 bl_0_37 br_0_37 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c37 bl_0_37 br_0_37 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c37 bl_0_37 br_0_37 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c37 bl_0_37 br_0_37 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c37 bl_0_37 br_0_37 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c37 bl_0_37 br_0_37 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c37 bl_0_37 br_0_37 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c37 bl_0_37 br_0_37 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c37 bl_0_37 br_0_37 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c37 bl_0_37 br_0_37 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c37 bl_0_37 br_0_37 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c37 bl_0_37 br_0_37 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c37 bl_0_37 br_0_37 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c37 bl_0_37 br_0_37 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c37 bl_0_37 br_0_37 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c37 bl_0_37 br_0_37 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c37 bl_0_37 br_0_37 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c37 bl_0_37 br_0_37 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c37 bl_0_37 br_0_37 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c37 bl_0_37 br_0_37 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c37 bl_0_37 br_0_37 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c37 bl_0_37 br_0_37 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c37 bl_0_37 br_0_37 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c37 bl_0_37 br_0_37 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c37 bl_0_37 br_0_37 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c37 bl_0_37 br_0_37 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c38 bl_0_38 br_0_38 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c38 bl_0_38 br_0_38 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c38 bl_0_38 br_0_38 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c38 bl_0_38 br_0_38 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c38 bl_0_38 br_0_38 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c38 bl_0_38 br_0_38 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c38 bl_0_38 br_0_38 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c38 bl_0_38 br_0_38 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c38 bl_0_38 br_0_38 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c38 bl_0_38 br_0_38 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c38 bl_0_38 br_0_38 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c38 bl_0_38 br_0_38 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c38 bl_0_38 br_0_38 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c38 bl_0_38 br_0_38 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c38 bl_0_38 br_0_38 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c38 bl_0_38 br_0_38 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c38 bl_0_38 br_0_38 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c38 bl_0_38 br_0_38 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c38 bl_0_38 br_0_38 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c38 bl_0_38 br_0_38 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c38 bl_0_38 br_0_38 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c38 bl_0_38 br_0_38 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c38 bl_0_38 br_0_38 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c38 bl_0_38 br_0_38 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c38 bl_0_38 br_0_38 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c38 bl_0_38 br_0_38 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c38 bl_0_38 br_0_38 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c38 bl_0_38 br_0_38 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c38 bl_0_38 br_0_38 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c38 bl_0_38 br_0_38 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c38 bl_0_38 br_0_38 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c38 bl_0_38 br_0_38 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c38 bl_0_38 br_0_38 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c38 bl_0_38 br_0_38 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c38 bl_0_38 br_0_38 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c38 bl_0_38 br_0_38 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c38 bl_0_38 br_0_38 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c38 bl_0_38 br_0_38 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c38 bl_0_38 br_0_38 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c38 bl_0_38 br_0_38 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c38 bl_0_38 br_0_38 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c38 bl_0_38 br_0_38 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c38 bl_0_38 br_0_38 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c38 bl_0_38 br_0_38 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c38 bl_0_38 br_0_38 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c38 bl_0_38 br_0_38 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c38 bl_0_38 br_0_38 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c38 bl_0_38 br_0_38 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c38 bl_0_38 br_0_38 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c38 bl_0_38 br_0_38 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c38 bl_0_38 br_0_38 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c38 bl_0_38 br_0_38 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c38 bl_0_38 br_0_38 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c38 bl_0_38 br_0_38 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c38 bl_0_38 br_0_38 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c38 bl_0_38 br_0_38 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c38 bl_0_38 br_0_38 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c38 bl_0_38 br_0_38 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c38 bl_0_38 br_0_38 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c38 bl_0_38 br_0_38 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c38 bl_0_38 br_0_38 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c38 bl_0_38 br_0_38 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c38 bl_0_38 br_0_38 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c38 bl_0_38 br_0_38 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c39 bl_0_39 br_0_39 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c39 bl_0_39 br_0_39 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c39 bl_0_39 br_0_39 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c39 bl_0_39 br_0_39 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c39 bl_0_39 br_0_39 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c39 bl_0_39 br_0_39 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c39 bl_0_39 br_0_39 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c39 bl_0_39 br_0_39 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c39 bl_0_39 br_0_39 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c39 bl_0_39 br_0_39 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c39 bl_0_39 br_0_39 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c39 bl_0_39 br_0_39 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c39 bl_0_39 br_0_39 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c39 bl_0_39 br_0_39 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c39 bl_0_39 br_0_39 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c39 bl_0_39 br_0_39 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c39 bl_0_39 br_0_39 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c39 bl_0_39 br_0_39 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c39 bl_0_39 br_0_39 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c39 bl_0_39 br_0_39 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c39 bl_0_39 br_0_39 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c39 bl_0_39 br_0_39 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c39 bl_0_39 br_0_39 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c39 bl_0_39 br_0_39 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c39 bl_0_39 br_0_39 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c39 bl_0_39 br_0_39 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c39 bl_0_39 br_0_39 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c39 bl_0_39 br_0_39 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c39 bl_0_39 br_0_39 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c39 bl_0_39 br_0_39 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c39 bl_0_39 br_0_39 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c39 bl_0_39 br_0_39 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c39 bl_0_39 br_0_39 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c39 bl_0_39 br_0_39 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c39 bl_0_39 br_0_39 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c39 bl_0_39 br_0_39 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c39 bl_0_39 br_0_39 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c39 bl_0_39 br_0_39 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c39 bl_0_39 br_0_39 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c39 bl_0_39 br_0_39 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c39 bl_0_39 br_0_39 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c39 bl_0_39 br_0_39 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c39 bl_0_39 br_0_39 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c39 bl_0_39 br_0_39 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c39 bl_0_39 br_0_39 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c39 bl_0_39 br_0_39 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c39 bl_0_39 br_0_39 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c39 bl_0_39 br_0_39 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c39 bl_0_39 br_0_39 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c39 bl_0_39 br_0_39 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c39 bl_0_39 br_0_39 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c39 bl_0_39 br_0_39 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c39 bl_0_39 br_0_39 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c39 bl_0_39 br_0_39 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c39 bl_0_39 br_0_39 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c39 bl_0_39 br_0_39 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c39 bl_0_39 br_0_39 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c39 bl_0_39 br_0_39 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c39 bl_0_39 br_0_39 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c39 bl_0_39 br_0_39 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c39 bl_0_39 br_0_39 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c39 bl_0_39 br_0_39 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c39 bl_0_39 br_0_39 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c39 bl_0_39 br_0_39 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c40 bl_0_40 br_0_40 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c40 bl_0_40 br_0_40 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c40 bl_0_40 br_0_40 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c40 bl_0_40 br_0_40 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c40 bl_0_40 br_0_40 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c40 bl_0_40 br_0_40 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c40 bl_0_40 br_0_40 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c40 bl_0_40 br_0_40 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c40 bl_0_40 br_0_40 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c40 bl_0_40 br_0_40 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c40 bl_0_40 br_0_40 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c40 bl_0_40 br_0_40 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c40 bl_0_40 br_0_40 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c40 bl_0_40 br_0_40 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c40 bl_0_40 br_0_40 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c40 bl_0_40 br_0_40 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c40 bl_0_40 br_0_40 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c40 bl_0_40 br_0_40 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c40 bl_0_40 br_0_40 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c40 bl_0_40 br_0_40 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c40 bl_0_40 br_0_40 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c40 bl_0_40 br_0_40 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c40 bl_0_40 br_0_40 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c40 bl_0_40 br_0_40 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c40 bl_0_40 br_0_40 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c40 bl_0_40 br_0_40 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c40 bl_0_40 br_0_40 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c40 bl_0_40 br_0_40 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c40 bl_0_40 br_0_40 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c40 bl_0_40 br_0_40 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c40 bl_0_40 br_0_40 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c40 bl_0_40 br_0_40 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c40 bl_0_40 br_0_40 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c40 bl_0_40 br_0_40 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c40 bl_0_40 br_0_40 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c40 bl_0_40 br_0_40 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c40 bl_0_40 br_0_40 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c40 bl_0_40 br_0_40 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c40 bl_0_40 br_0_40 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c40 bl_0_40 br_0_40 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c40 bl_0_40 br_0_40 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c40 bl_0_40 br_0_40 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c40 bl_0_40 br_0_40 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c40 bl_0_40 br_0_40 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c40 bl_0_40 br_0_40 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c40 bl_0_40 br_0_40 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c40 bl_0_40 br_0_40 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c40 bl_0_40 br_0_40 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c40 bl_0_40 br_0_40 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c40 bl_0_40 br_0_40 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c40 bl_0_40 br_0_40 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c40 bl_0_40 br_0_40 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c40 bl_0_40 br_0_40 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c40 bl_0_40 br_0_40 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c40 bl_0_40 br_0_40 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c40 bl_0_40 br_0_40 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c40 bl_0_40 br_0_40 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c40 bl_0_40 br_0_40 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c40 bl_0_40 br_0_40 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c40 bl_0_40 br_0_40 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c40 bl_0_40 br_0_40 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c40 bl_0_40 br_0_40 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c40 bl_0_40 br_0_40 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c40 bl_0_40 br_0_40 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c41 bl_0_41 br_0_41 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c41 bl_0_41 br_0_41 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c41 bl_0_41 br_0_41 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c41 bl_0_41 br_0_41 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c41 bl_0_41 br_0_41 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c41 bl_0_41 br_0_41 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c41 bl_0_41 br_0_41 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c41 bl_0_41 br_0_41 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c41 bl_0_41 br_0_41 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c41 bl_0_41 br_0_41 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c41 bl_0_41 br_0_41 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c41 bl_0_41 br_0_41 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c41 bl_0_41 br_0_41 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c41 bl_0_41 br_0_41 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c41 bl_0_41 br_0_41 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c41 bl_0_41 br_0_41 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c41 bl_0_41 br_0_41 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c41 bl_0_41 br_0_41 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c41 bl_0_41 br_0_41 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c41 bl_0_41 br_0_41 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c41 bl_0_41 br_0_41 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c41 bl_0_41 br_0_41 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c41 bl_0_41 br_0_41 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c41 bl_0_41 br_0_41 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c41 bl_0_41 br_0_41 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c41 bl_0_41 br_0_41 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c41 bl_0_41 br_0_41 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c41 bl_0_41 br_0_41 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c41 bl_0_41 br_0_41 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c41 bl_0_41 br_0_41 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c41 bl_0_41 br_0_41 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c41 bl_0_41 br_0_41 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c41 bl_0_41 br_0_41 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c41 bl_0_41 br_0_41 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c41 bl_0_41 br_0_41 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c41 bl_0_41 br_0_41 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c41 bl_0_41 br_0_41 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c41 bl_0_41 br_0_41 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c41 bl_0_41 br_0_41 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c41 bl_0_41 br_0_41 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c41 bl_0_41 br_0_41 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c41 bl_0_41 br_0_41 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c41 bl_0_41 br_0_41 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c41 bl_0_41 br_0_41 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c41 bl_0_41 br_0_41 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c41 bl_0_41 br_0_41 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c41 bl_0_41 br_0_41 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c41 bl_0_41 br_0_41 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c41 bl_0_41 br_0_41 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c41 bl_0_41 br_0_41 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c41 bl_0_41 br_0_41 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c41 bl_0_41 br_0_41 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c41 bl_0_41 br_0_41 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c41 bl_0_41 br_0_41 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c41 bl_0_41 br_0_41 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c41 bl_0_41 br_0_41 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c41 bl_0_41 br_0_41 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c41 bl_0_41 br_0_41 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c41 bl_0_41 br_0_41 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c41 bl_0_41 br_0_41 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c41 bl_0_41 br_0_41 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c41 bl_0_41 br_0_41 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c41 bl_0_41 br_0_41 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c41 bl_0_41 br_0_41 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c42 bl_0_42 br_0_42 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c42 bl_0_42 br_0_42 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c42 bl_0_42 br_0_42 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c42 bl_0_42 br_0_42 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c42 bl_0_42 br_0_42 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c42 bl_0_42 br_0_42 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c42 bl_0_42 br_0_42 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c42 bl_0_42 br_0_42 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c42 bl_0_42 br_0_42 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c42 bl_0_42 br_0_42 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c42 bl_0_42 br_0_42 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c42 bl_0_42 br_0_42 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c42 bl_0_42 br_0_42 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c42 bl_0_42 br_0_42 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c42 bl_0_42 br_0_42 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c42 bl_0_42 br_0_42 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c42 bl_0_42 br_0_42 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c42 bl_0_42 br_0_42 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c42 bl_0_42 br_0_42 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c42 bl_0_42 br_0_42 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c42 bl_0_42 br_0_42 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c42 bl_0_42 br_0_42 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c42 bl_0_42 br_0_42 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c42 bl_0_42 br_0_42 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c42 bl_0_42 br_0_42 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c42 bl_0_42 br_0_42 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c42 bl_0_42 br_0_42 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c42 bl_0_42 br_0_42 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c42 bl_0_42 br_0_42 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c42 bl_0_42 br_0_42 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c42 bl_0_42 br_0_42 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c42 bl_0_42 br_0_42 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c42 bl_0_42 br_0_42 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c42 bl_0_42 br_0_42 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c42 bl_0_42 br_0_42 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c42 bl_0_42 br_0_42 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c42 bl_0_42 br_0_42 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c42 bl_0_42 br_0_42 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c42 bl_0_42 br_0_42 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c42 bl_0_42 br_0_42 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c42 bl_0_42 br_0_42 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c42 bl_0_42 br_0_42 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c42 bl_0_42 br_0_42 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c42 bl_0_42 br_0_42 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c42 bl_0_42 br_0_42 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c42 bl_0_42 br_0_42 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c42 bl_0_42 br_0_42 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c42 bl_0_42 br_0_42 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c42 bl_0_42 br_0_42 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c42 bl_0_42 br_0_42 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c42 bl_0_42 br_0_42 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c42 bl_0_42 br_0_42 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c42 bl_0_42 br_0_42 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c42 bl_0_42 br_0_42 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c42 bl_0_42 br_0_42 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c42 bl_0_42 br_0_42 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c42 bl_0_42 br_0_42 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c42 bl_0_42 br_0_42 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c42 bl_0_42 br_0_42 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c42 bl_0_42 br_0_42 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c42 bl_0_42 br_0_42 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c42 bl_0_42 br_0_42 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c42 bl_0_42 br_0_42 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c42 bl_0_42 br_0_42 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c43 bl_0_43 br_0_43 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c43 bl_0_43 br_0_43 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c43 bl_0_43 br_0_43 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c43 bl_0_43 br_0_43 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c43 bl_0_43 br_0_43 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c43 bl_0_43 br_0_43 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c43 bl_0_43 br_0_43 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c43 bl_0_43 br_0_43 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c43 bl_0_43 br_0_43 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c43 bl_0_43 br_0_43 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c43 bl_0_43 br_0_43 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c43 bl_0_43 br_0_43 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c43 bl_0_43 br_0_43 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c43 bl_0_43 br_0_43 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c43 bl_0_43 br_0_43 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c43 bl_0_43 br_0_43 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c43 bl_0_43 br_0_43 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c43 bl_0_43 br_0_43 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c43 bl_0_43 br_0_43 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c43 bl_0_43 br_0_43 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c43 bl_0_43 br_0_43 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c43 bl_0_43 br_0_43 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c43 bl_0_43 br_0_43 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c43 bl_0_43 br_0_43 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c43 bl_0_43 br_0_43 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c43 bl_0_43 br_0_43 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c43 bl_0_43 br_0_43 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c43 bl_0_43 br_0_43 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c43 bl_0_43 br_0_43 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c43 bl_0_43 br_0_43 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c43 bl_0_43 br_0_43 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c43 bl_0_43 br_0_43 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c43 bl_0_43 br_0_43 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c43 bl_0_43 br_0_43 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c43 bl_0_43 br_0_43 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c43 bl_0_43 br_0_43 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c43 bl_0_43 br_0_43 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c43 bl_0_43 br_0_43 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c43 bl_0_43 br_0_43 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c43 bl_0_43 br_0_43 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c43 bl_0_43 br_0_43 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c43 bl_0_43 br_0_43 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c43 bl_0_43 br_0_43 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c43 bl_0_43 br_0_43 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c43 bl_0_43 br_0_43 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c43 bl_0_43 br_0_43 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c43 bl_0_43 br_0_43 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c43 bl_0_43 br_0_43 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c43 bl_0_43 br_0_43 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c43 bl_0_43 br_0_43 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c43 bl_0_43 br_0_43 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c43 bl_0_43 br_0_43 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c43 bl_0_43 br_0_43 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c43 bl_0_43 br_0_43 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c43 bl_0_43 br_0_43 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c43 bl_0_43 br_0_43 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c43 bl_0_43 br_0_43 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c43 bl_0_43 br_0_43 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c43 bl_0_43 br_0_43 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c43 bl_0_43 br_0_43 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c43 bl_0_43 br_0_43 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c43 bl_0_43 br_0_43 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c43 bl_0_43 br_0_43 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c43 bl_0_43 br_0_43 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c44 bl_0_44 br_0_44 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c44 bl_0_44 br_0_44 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c44 bl_0_44 br_0_44 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c44 bl_0_44 br_0_44 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c44 bl_0_44 br_0_44 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c44 bl_0_44 br_0_44 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c44 bl_0_44 br_0_44 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c44 bl_0_44 br_0_44 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c44 bl_0_44 br_0_44 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c44 bl_0_44 br_0_44 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c44 bl_0_44 br_0_44 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c44 bl_0_44 br_0_44 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c44 bl_0_44 br_0_44 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c44 bl_0_44 br_0_44 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c44 bl_0_44 br_0_44 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c44 bl_0_44 br_0_44 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c44 bl_0_44 br_0_44 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c44 bl_0_44 br_0_44 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c44 bl_0_44 br_0_44 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c44 bl_0_44 br_0_44 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c44 bl_0_44 br_0_44 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c44 bl_0_44 br_0_44 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c44 bl_0_44 br_0_44 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c44 bl_0_44 br_0_44 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c44 bl_0_44 br_0_44 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c44 bl_0_44 br_0_44 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c44 bl_0_44 br_0_44 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c44 bl_0_44 br_0_44 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c44 bl_0_44 br_0_44 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c44 bl_0_44 br_0_44 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c44 bl_0_44 br_0_44 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c44 bl_0_44 br_0_44 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c44 bl_0_44 br_0_44 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c44 bl_0_44 br_0_44 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c44 bl_0_44 br_0_44 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c44 bl_0_44 br_0_44 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c44 bl_0_44 br_0_44 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c44 bl_0_44 br_0_44 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c44 bl_0_44 br_0_44 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c44 bl_0_44 br_0_44 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c44 bl_0_44 br_0_44 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c44 bl_0_44 br_0_44 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c44 bl_0_44 br_0_44 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c44 bl_0_44 br_0_44 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c44 bl_0_44 br_0_44 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c44 bl_0_44 br_0_44 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c44 bl_0_44 br_0_44 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c44 bl_0_44 br_0_44 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c44 bl_0_44 br_0_44 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c44 bl_0_44 br_0_44 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c44 bl_0_44 br_0_44 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c44 bl_0_44 br_0_44 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c44 bl_0_44 br_0_44 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c44 bl_0_44 br_0_44 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c44 bl_0_44 br_0_44 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c44 bl_0_44 br_0_44 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c44 bl_0_44 br_0_44 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c44 bl_0_44 br_0_44 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c44 bl_0_44 br_0_44 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c44 bl_0_44 br_0_44 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c44 bl_0_44 br_0_44 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c44 bl_0_44 br_0_44 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c44 bl_0_44 br_0_44 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c44 bl_0_44 br_0_44 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c45 bl_0_45 br_0_45 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c45 bl_0_45 br_0_45 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c45 bl_0_45 br_0_45 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c45 bl_0_45 br_0_45 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c45 bl_0_45 br_0_45 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c45 bl_0_45 br_0_45 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c45 bl_0_45 br_0_45 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c45 bl_0_45 br_0_45 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c45 bl_0_45 br_0_45 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c45 bl_0_45 br_0_45 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c45 bl_0_45 br_0_45 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c45 bl_0_45 br_0_45 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c45 bl_0_45 br_0_45 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c45 bl_0_45 br_0_45 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c45 bl_0_45 br_0_45 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c45 bl_0_45 br_0_45 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c45 bl_0_45 br_0_45 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c45 bl_0_45 br_0_45 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c45 bl_0_45 br_0_45 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c45 bl_0_45 br_0_45 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c45 bl_0_45 br_0_45 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c45 bl_0_45 br_0_45 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c45 bl_0_45 br_0_45 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c45 bl_0_45 br_0_45 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c45 bl_0_45 br_0_45 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c45 bl_0_45 br_0_45 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c45 bl_0_45 br_0_45 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c45 bl_0_45 br_0_45 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c45 bl_0_45 br_0_45 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c45 bl_0_45 br_0_45 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c45 bl_0_45 br_0_45 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c45 bl_0_45 br_0_45 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c45 bl_0_45 br_0_45 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c45 bl_0_45 br_0_45 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c45 bl_0_45 br_0_45 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c45 bl_0_45 br_0_45 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c45 bl_0_45 br_0_45 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c45 bl_0_45 br_0_45 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c45 bl_0_45 br_0_45 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c45 bl_0_45 br_0_45 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c45 bl_0_45 br_0_45 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c45 bl_0_45 br_0_45 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c45 bl_0_45 br_0_45 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c45 bl_0_45 br_0_45 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c45 bl_0_45 br_0_45 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c45 bl_0_45 br_0_45 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c45 bl_0_45 br_0_45 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c45 bl_0_45 br_0_45 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c45 bl_0_45 br_0_45 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c45 bl_0_45 br_0_45 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c45 bl_0_45 br_0_45 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c45 bl_0_45 br_0_45 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c45 bl_0_45 br_0_45 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c45 bl_0_45 br_0_45 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c45 bl_0_45 br_0_45 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c45 bl_0_45 br_0_45 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c45 bl_0_45 br_0_45 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c45 bl_0_45 br_0_45 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c45 bl_0_45 br_0_45 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c45 bl_0_45 br_0_45 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c45 bl_0_45 br_0_45 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c45 bl_0_45 br_0_45 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c45 bl_0_45 br_0_45 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c45 bl_0_45 br_0_45 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c46 bl_0_46 br_0_46 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c46 bl_0_46 br_0_46 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c46 bl_0_46 br_0_46 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c46 bl_0_46 br_0_46 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c46 bl_0_46 br_0_46 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c46 bl_0_46 br_0_46 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c46 bl_0_46 br_0_46 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c46 bl_0_46 br_0_46 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c46 bl_0_46 br_0_46 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c46 bl_0_46 br_0_46 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c46 bl_0_46 br_0_46 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c46 bl_0_46 br_0_46 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c46 bl_0_46 br_0_46 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c46 bl_0_46 br_0_46 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c46 bl_0_46 br_0_46 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c46 bl_0_46 br_0_46 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c46 bl_0_46 br_0_46 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c46 bl_0_46 br_0_46 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c46 bl_0_46 br_0_46 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c46 bl_0_46 br_0_46 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c46 bl_0_46 br_0_46 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c46 bl_0_46 br_0_46 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c46 bl_0_46 br_0_46 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c46 bl_0_46 br_0_46 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c46 bl_0_46 br_0_46 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c46 bl_0_46 br_0_46 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c46 bl_0_46 br_0_46 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c46 bl_0_46 br_0_46 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c46 bl_0_46 br_0_46 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c46 bl_0_46 br_0_46 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c46 bl_0_46 br_0_46 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c46 bl_0_46 br_0_46 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c46 bl_0_46 br_0_46 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c46 bl_0_46 br_0_46 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c46 bl_0_46 br_0_46 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c46 bl_0_46 br_0_46 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c46 bl_0_46 br_0_46 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c46 bl_0_46 br_0_46 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c46 bl_0_46 br_0_46 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c46 bl_0_46 br_0_46 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c46 bl_0_46 br_0_46 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c46 bl_0_46 br_0_46 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c46 bl_0_46 br_0_46 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c46 bl_0_46 br_0_46 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c46 bl_0_46 br_0_46 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c46 bl_0_46 br_0_46 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c46 bl_0_46 br_0_46 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c46 bl_0_46 br_0_46 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c46 bl_0_46 br_0_46 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c46 bl_0_46 br_0_46 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c46 bl_0_46 br_0_46 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c46 bl_0_46 br_0_46 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c46 bl_0_46 br_0_46 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c46 bl_0_46 br_0_46 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c46 bl_0_46 br_0_46 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c46 bl_0_46 br_0_46 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c46 bl_0_46 br_0_46 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c46 bl_0_46 br_0_46 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c46 bl_0_46 br_0_46 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c46 bl_0_46 br_0_46 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c46 bl_0_46 br_0_46 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c46 bl_0_46 br_0_46 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c46 bl_0_46 br_0_46 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c46 bl_0_46 br_0_46 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c47 bl_0_47 br_0_47 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c47 bl_0_47 br_0_47 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c47 bl_0_47 br_0_47 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c47 bl_0_47 br_0_47 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c47 bl_0_47 br_0_47 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c47 bl_0_47 br_0_47 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c47 bl_0_47 br_0_47 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c47 bl_0_47 br_0_47 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c47 bl_0_47 br_0_47 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c47 bl_0_47 br_0_47 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c47 bl_0_47 br_0_47 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c47 bl_0_47 br_0_47 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c47 bl_0_47 br_0_47 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c47 bl_0_47 br_0_47 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c47 bl_0_47 br_0_47 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c47 bl_0_47 br_0_47 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c47 bl_0_47 br_0_47 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c47 bl_0_47 br_0_47 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c47 bl_0_47 br_0_47 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c47 bl_0_47 br_0_47 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c47 bl_0_47 br_0_47 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c47 bl_0_47 br_0_47 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c47 bl_0_47 br_0_47 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c47 bl_0_47 br_0_47 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c47 bl_0_47 br_0_47 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c47 bl_0_47 br_0_47 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c47 bl_0_47 br_0_47 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c47 bl_0_47 br_0_47 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c47 bl_0_47 br_0_47 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c47 bl_0_47 br_0_47 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c47 bl_0_47 br_0_47 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c47 bl_0_47 br_0_47 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c47 bl_0_47 br_0_47 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c47 bl_0_47 br_0_47 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c47 bl_0_47 br_0_47 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c47 bl_0_47 br_0_47 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c47 bl_0_47 br_0_47 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c47 bl_0_47 br_0_47 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c47 bl_0_47 br_0_47 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c47 bl_0_47 br_0_47 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c47 bl_0_47 br_0_47 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c47 bl_0_47 br_0_47 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c47 bl_0_47 br_0_47 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c47 bl_0_47 br_0_47 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c47 bl_0_47 br_0_47 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c47 bl_0_47 br_0_47 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c47 bl_0_47 br_0_47 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c47 bl_0_47 br_0_47 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c47 bl_0_47 br_0_47 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c47 bl_0_47 br_0_47 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c47 bl_0_47 br_0_47 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c47 bl_0_47 br_0_47 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c47 bl_0_47 br_0_47 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c47 bl_0_47 br_0_47 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c47 bl_0_47 br_0_47 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c47 bl_0_47 br_0_47 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c47 bl_0_47 br_0_47 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c47 bl_0_47 br_0_47 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c47 bl_0_47 br_0_47 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c47 bl_0_47 br_0_47 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c47 bl_0_47 br_0_47 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c47 bl_0_47 br_0_47 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c47 bl_0_47 br_0_47 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c47 bl_0_47 br_0_47 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c48 bl_0_48 br_0_48 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c48 bl_0_48 br_0_48 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c48 bl_0_48 br_0_48 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c48 bl_0_48 br_0_48 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c48 bl_0_48 br_0_48 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c48 bl_0_48 br_0_48 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c48 bl_0_48 br_0_48 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c48 bl_0_48 br_0_48 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c48 bl_0_48 br_0_48 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c48 bl_0_48 br_0_48 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c48 bl_0_48 br_0_48 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c48 bl_0_48 br_0_48 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c48 bl_0_48 br_0_48 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c48 bl_0_48 br_0_48 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c48 bl_0_48 br_0_48 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c48 bl_0_48 br_0_48 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c48 bl_0_48 br_0_48 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c48 bl_0_48 br_0_48 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c48 bl_0_48 br_0_48 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c48 bl_0_48 br_0_48 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c48 bl_0_48 br_0_48 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c48 bl_0_48 br_0_48 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c48 bl_0_48 br_0_48 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c48 bl_0_48 br_0_48 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c48 bl_0_48 br_0_48 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c48 bl_0_48 br_0_48 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c48 bl_0_48 br_0_48 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c48 bl_0_48 br_0_48 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c48 bl_0_48 br_0_48 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c48 bl_0_48 br_0_48 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c48 bl_0_48 br_0_48 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c48 bl_0_48 br_0_48 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c48 bl_0_48 br_0_48 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c48 bl_0_48 br_0_48 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c48 bl_0_48 br_0_48 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c48 bl_0_48 br_0_48 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c48 bl_0_48 br_0_48 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c48 bl_0_48 br_0_48 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c48 bl_0_48 br_0_48 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c48 bl_0_48 br_0_48 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c48 bl_0_48 br_0_48 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c48 bl_0_48 br_0_48 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c48 bl_0_48 br_0_48 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c48 bl_0_48 br_0_48 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c48 bl_0_48 br_0_48 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c48 bl_0_48 br_0_48 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c48 bl_0_48 br_0_48 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c48 bl_0_48 br_0_48 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c48 bl_0_48 br_0_48 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c48 bl_0_48 br_0_48 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c48 bl_0_48 br_0_48 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c48 bl_0_48 br_0_48 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c48 bl_0_48 br_0_48 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c48 bl_0_48 br_0_48 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c48 bl_0_48 br_0_48 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c48 bl_0_48 br_0_48 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c48 bl_0_48 br_0_48 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c48 bl_0_48 br_0_48 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c48 bl_0_48 br_0_48 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c48 bl_0_48 br_0_48 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c48 bl_0_48 br_0_48 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c48 bl_0_48 br_0_48 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c48 bl_0_48 br_0_48 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c48 bl_0_48 br_0_48 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c49 bl_0_49 br_0_49 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c49 bl_0_49 br_0_49 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c49 bl_0_49 br_0_49 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c49 bl_0_49 br_0_49 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c49 bl_0_49 br_0_49 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c49 bl_0_49 br_0_49 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c49 bl_0_49 br_0_49 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c49 bl_0_49 br_0_49 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c49 bl_0_49 br_0_49 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c49 bl_0_49 br_0_49 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c49 bl_0_49 br_0_49 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c49 bl_0_49 br_0_49 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c49 bl_0_49 br_0_49 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c49 bl_0_49 br_0_49 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c49 bl_0_49 br_0_49 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c49 bl_0_49 br_0_49 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c49 bl_0_49 br_0_49 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c49 bl_0_49 br_0_49 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c49 bl_0_49 br_0_49 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c49 bl_0_49 br_0_49 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c49 bl_0_49 br_0_49 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c49 bl_0_49 br_0_49 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c49 bl_0_49 br_0_49 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c49 bl_0_49 br_0_49 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c49 bl_0_49 br_0_49 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c49 bl_0_49 br_0_49 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c49 bl_0_49 br_0_49 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c49 bl_0_49 br_0_49 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c49 bl_0_49 br_0_49 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c49 bl_0_49 br_0_49 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c49 bl_0_49 br_0_49 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c49 bl_0_49 br_0_49 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c49 bl_0_49 br_0_49 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c49 bl_0_49 br_0_49 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c49 bl_0_49 br_0_49 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c49 bl_0_49 br_0_49 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c49 bl_0_49 br_0_49 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c49 bl_0_49 br_0_49 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c49 bl_0_49 br_0_49 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c49 bl_0_49 br_0_49 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c49 bl_0_49 br_0_49 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c49 bl_0_49 br_0_49 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c49 bl_0_49 br_0_49 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c49 bl_0_49 br_0_49 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c49 bl_0_49 br_0_49 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c49 bl_0_49 br_0_49 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c49 bl_0_49 br_0_49 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c49 bl_0_49 br_0_49 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c49 bl_0_49 br_0_49 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c49 bl_0_49 br_0_49 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c49 bl_0_49 br_0_49 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c49 bl_0_49 br_0_49 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c49 bl_0_49 br_0_49 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c49 bl_0_49 br_0_49 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c49 bl_0_49 br_0_49 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c49 bl_0_49 br_0_49 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c49 bl_0_49 br_0_49 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c49 bl_0_49 br_0_49 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c49 bl_0_49 br_0_49 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c49 bl_0_49 br_0_49 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c49 bl_0_49 br_0_49 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c49 bl_0_49 br_0_49 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c49 bl_0_49 br_0_49 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c49 bl_0_49 br_0_49 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c50 bl_0_50 br_0_50 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c50 bl_0_50 br_0_50 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c50 bl_0_50 br_0_50 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c50 bl_0_50 br_0_50 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c50 bl_0_50 br_0_50 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c50 bl_0_50 br_0_50 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c50 bl_0_50 br_0_50 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c50 bl_0_50 br_0_50 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c50 bl_0_50 br_0_50 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c50 bl_0_50 br_0_50 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c50 bl_0_50 br_0_50 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c50 bl_0_50 br_0_50 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c50 bl_0_50 br_0_50 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c50 bl_0_50 br_0_50 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c50 bl_0_50 br_0_50 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c50 bl_0_50 br_0_50 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c50 bl_0_50 br_0_50 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c50 bl_0_50 br_0_50 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c50 bl_0_50 br_0_50 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c50 bl_0_50 br_0_50 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c50 bl_0_50 br_0_50 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c50 bl_0_50 br_0_50 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c50 bl_0_50 br_0_50 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c50 bl_0_50 br_0_50 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c50 bl_0_50 br_0_50 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c50 bl_0_50 br_0_50 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c50 bl_0_50 br_0_50 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c50 bl_0_50 br_0_50 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c50 bl_0_50 br_0_50 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c50 bl_0_50 br_0_50 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c50 bl_0_50 br_0_50 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c50 bl_0_50 br_0_50 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c50 bl_0_50 br_0_50 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c50 bl_0_50 br_0_50 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c50 bl_0_50 br_0_50 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c50 bl_0_50 br_0_50 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c50 bl_0_50 br_0_50 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c50 bl_0_50 br_0_50 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c50 bl_0_50 br_0_50 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c50 bl_0_50 br_0_50 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c50 bl_0_50 br_0_50 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c50 bl_0_50 br_0_50 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c50 bl_0_50 br_0_50 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c50 bl_0_50 br_0_50 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c50 bl_0_50 br_0_50 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c50 bl_0_50 br_0_50 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c50 bl_0_50 br_0_50 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c50 bl_0_50 br_0_50 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c50 bl_0_50 br_0_50 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c50 bl_0_50 br_0_50 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c50 bl_0_50 br_0_50 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c50 bl_0_50 br_0_50 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c50 bl_0_50 br_0_50 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c50 bl_0_50 br_0_50 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c50 bl_0_50 br_0_50 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c50 bl_0_50 br_0_50 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c50 bl_0_50 br_0_50 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c50 bl_0_50 br_0_50 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c50 bl_0_50 br_0_50 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c50 bl_0_50 br_0_50 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c50 bl_0_50 br_0_50 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c50 bl_0_50 br_0_50 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c50 bl_0_50 br_0_50 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c50 bl_0_50 br_0_50 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c51 bl_0_51 br_0_51 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c51 bl_0_51 br_0_51 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c51 bl_0_51 br_0_51 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c51 bl_0_51 br_0_51 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c51 bl_0_51 br_0_51 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c51 bl_0_51 br_0_51 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c51 bl_0_51 br_0_51 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c51 bl_0_51 br_0_51 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c51 bl_0_51 br_0_51 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c51 bl_0_51 br_0_51 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c51 bl_0_51 br_0_51 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c51 bl_0_51 br_0_51 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c51 bl_0_51 br_0_51 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c51 bl_0_51 br_0_51 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c51 bl_0_51 br_0_51 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c51 bl_0_51 br_0_51 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c51 bl_0_51 br_0_51 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c51 bl_0_51 br_0_51 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c51 bl_0_51 br_0_51 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c51 bl_0_51 br_0_51 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c51 bl_0_51 br_0_51 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c51 bl_0_51 br_0_51 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c51 bl_0_51 br_0_51 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c51 bl_0_51 br_0_51 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c51 bl_0_51 br_0_51 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c51 bl_0_51 br_0_51 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c51 bl_0_51 br_0_51 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c51 bl_0_51 br_0_51 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c51 bl_0_51 br_0_51 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c51 bl_0_51 br_0_51 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c51 bl_0_51 br_0_51 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c51 bl_0_51 br_0_51 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c51 bl_0_51 br_0_51 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c51 bl_0_51 br_0_51 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c51 bl_0_51 br_0_51 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c51 bl_0_51 br_0_51 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c51 bl_0_51 br_0_51 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c51 bl_0_51 br_0_51 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c51 bl_0_51 br_0_51 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c51 bl_0_51 br_0_51 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c51 bl_0_51 br_0_51 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c51 bl_0_51 br_0_51 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c51 bl_0_51 br_0_51 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c51 bl_0_51 br_0_51 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c51 bl_0_51 br_0_51 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c51 bl_0_51 br_0_51 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c51 bl_0_51 br_0_51 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c51 bl_0_51 br_0_51 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c51 bl_0_51 br_0_51 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c51 bl_0_51 br_0_51 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c51 bl_0_51 br_0_51 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c51 bl_0_51 br_0_51 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c51 bl_0_51 br_0_51 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c51 bl_0_51 br_0_51 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c51 bl_0_51 br_0_51 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c51 bl_0_51 br_0_51 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c51 bl_0_51 br_0_51 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c51 bl_0_51 br_0_51 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c51 bl_0_51 br_0_51 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c51 bl_0_51 br_0_51 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c51 bl_0_51 br_0_51 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c51 bl_0_51 br_0_51 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c51 bl_0_51 br_0_51 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c51 bl_0_51 br_0_51 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c52 bl_0_52 br_0_52 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c52 bl_0_52 br_0_52 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c52 bl_0_52 br_0_52 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c52 bl_0_52 br_0_52 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c52 bl_0_52 br_0_52 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c52 bl_0_52 br_0_52 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c52 bl_0_52 br_0_52 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c52 bl_0_52 br_0_52 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c52 bl_0_52 br_0_52 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c52 bl_0_52 br_0_52 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c52 bl_0_52 br_0_52 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c52 bl_0_52 br_0_52 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c52 bl_0_52 br_0_52 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c52 bl_0_52 br_0_52 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c52 bl_0_52 br_0_52 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c52 bl_0_52 br_0_52 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c52 bl_0_52 br_0_52 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c52 bl_0_52 br_0_52 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c52 bl_0_52 br_0_52 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c52 bl_0_52 br_0_52 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c52 bl_0_52 br_0_52 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c52 bl_0_52 br_0_52 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c52 bl_0_52 br_0_52 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c52 bl_0_52 br_0_52 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c52 bl_0_52 br_0_52 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c52 bl_0_52 br_0_52 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c52 bl_0_52 br_0_52 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c52 bl_0_52 br_0_52 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c52 bl_0_52 br_0_52 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c52 bl_0_52 br_0_52 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c52 bl_0_52 br_0_52 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c52 bl_0_52 br_0_52 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c52 bl_0_52 br_0_52 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c52 bl_0_52 br_0_52 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c52 bl_0_52 br_0_52 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c52 bl_0_52 br_0_52 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c52 bl_0_52 br_0_52 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c52 bl_0_52 br_0_52 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c52 bl_0_52 br_0_52 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c52 bl_0_52 br_0_52 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c52 bl_0_52 br_0_52 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c52 bl_0_52 br_0_52 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c52 bl_0_52 br_0_52 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c52 bl_0_52 br_0_52 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c52 bl_0_52 br_0_52 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c52 bl_0_52 br_0_52 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c52 bl_0_52 br_0_52 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c52 bl_0_52 br_0_52 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c52 bl_0_52 br_0_52 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c52 bl_0_52 br_0_52 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c52 bl_0_52 br_0_52 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c52 bl_0_52 br_0_52 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c52 bl_0_52 br_0_52 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c52 bl_0_52 br_0_52 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c52 bl_0_52 br_0_52 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c52 bl_0_52 br_0_52 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c52 bl_0_52 br_0_52 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c52 bl_0_52 br_0_52 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c52 bl_0_52 br_0_52 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c52 bl_0_52 br_0_52 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c52 bl_0_52 br_0_52 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c52 bl_0_52 br_0_52 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c52 bl_0_52 br_0_52 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c52 bl_0_52 br_0_52 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c53 bl_0_53 br_0_53 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c53 bl_0_53 br_0_53 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c53 bl_0_53 br_0_53 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c53 bl_0_53 br_0_53 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c53 bl_0_53 br_0_53 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c53 bl_0_53 br_0_53 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c53 bl_0_53 br_0_53 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c53 bl_0_53 br_0_53 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c53 bl_0_53 br_0_53 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c53 bl_0_53 br_0_53 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c53 bl_0_53 br_0_53 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c53 bl_0_53 br_0_53 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c53 bl_0_53 br_0_53 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c53 bl_0_53 br_0_53 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c53 bl_0_53 br_0_53 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c53 bl_0_53 br_0_53 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c53 bl_0_53 br_0_53 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c53 bl_0_53 br_0_53 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c53 bl_0_53 br_0_53 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c53 bl_0_53 br_0_53 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c53 bl_0_53 br_0_53 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c53 bl_0_53 br_0_53 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c53 bl_0_53 br_0_53 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c53 bl_0_53 br_0_53 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c53 bl_0_53 br_0_53 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c53 bl_0_53 br_0_53 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c53 bl_0_53 br_0_53 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c53 bl_0_53 br_0_53 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c53 bl_0_53 br_0_53 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c53 bl_0_53 br_0_53 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c53 bl_0_53 br_0_53 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c53 bl_0_53 br_0_53 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c53 bl_0_53 br_0_53 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c53 bl_0_53 br_0_53 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c53 bl_0_53 br_0_53 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c53 bl_0_53 br_0_53 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c53 bl_0_53 br_0_53 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c53 bl_0_53 br_0_53 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c53 bl_0_53 br_0_53 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c53 bl_0_53 br_0_53 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c53 bl_0_53 br_0_53 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c53 bl_0_53 br_0_53 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c53 bl_0_53 br_0_53 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c53 bl_0_53 br_0_53 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c53 bl_0_53 br_0_53 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c53 bl_0_53 br_0_53 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c53 bl_0_53 br_0_53 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c53 bl_0_53 br_0_53 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c53 bl_0_53 br_0_53 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c53 bl_0_53 br_0_53 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c53 bl_0_53 br_0_53 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c53 bl_0_53 br_0_53 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c53 bl_0_53 br_0_53 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c53 bl_0_53 br_0_53 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c53 bl_0_53 br_0_53 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c53 bl_0_53 br_0_53 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c53 bl_0_53 br_0_53 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c53 bl_0_53 br_0_53 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c53 bl_0_53 br_0_53 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c53 bl_0_53 br_0_53 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c53 bl_0_53 br_0_53 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c53 bl_0_53 br_0_53 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c53 bl_0_53 br_0_53 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c53 bl_0_53 br_0_53 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c54 bl_0_54 br_0_54 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c54 bl_0_54 br_0_54 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c54 bl_0_54 br_0_54 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c54 bl_0_54 br_0_54 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c54 bl_0_54 br_0_54 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c54 bl_0_54 br_0_54 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c54 bl_0_54 br_0_54 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c54 bl_0_54 br_0_54 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c54 bl_0_54 br_0_54 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c54 bl_0_54 br_0_54 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c54 bl_0_54 br_0_54 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c54 bl_0_54 br_0_54 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c54 bl_0_54 br_0_54 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c54 bl_0_54 br_0_54 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c54 bl_0_54 br_0_54 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c54 bl_0_54 br_0_54 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c54 bl_0_54 br_0_54 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c54 bl_0_54 br_0_54 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c54 bl_0_54 br_0_54 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c54 bl_0_54 br_0_54 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c54 bl_0_54 br_0_54 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c54 bl_0_54 br_0_54 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c54 bl_0_54 br_0_54 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c54 bl_0_54 br_0_54 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c54 bl_0_54 br_0_54 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c54 bl_0_54 br_0_54 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c54 bl_0_54 br_0_54 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c54 bl_0_54 br_0_54 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c54 bl_0_54 br_0_54 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c54 bl_0_54 br_0_54 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c54 bl_0_54 br_0_54 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c54 bl_0_54 br_0_54 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c54 bl_0_54 br_0_54 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c54 bl_0_54 br_0_54 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c54 bl_0_54 br_0_54 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c54 bl_0_54 br_0_54 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c54 bl_0_54 br_0_54 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c54 bl_0_54 br_0_54 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c54 bl_0_54 br_0_54 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c54 bl_0_54 br_0_54 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c54 bl_0_54 br_0_54 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c54 bl_0_54 br_0_54 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c54 bl_0_54 br_0_54 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c54 bl_0_54 br_0_54 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c54 bl_0_54 br_0_54 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c54 bl_0_54 br_0_54 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c54 bl_0_54 br_0_54 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c54 bl_0_54 br_0_54 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c54 bl_0_54 br_0_54 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c54 bl_0_54 br_0_54 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c54 bl_0_54 br_0_54 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c54 bl_0_54 br_0_54 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c54 bl_0_54 br_0_54 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c54 bl_0_54 br_0_54 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c54 bl_0_54 br_0_54 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c54 bl_0_54 br_0_54 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c54 bl_0_54 br_0_54 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c54 bl_0_54 br_0_54 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c54 bl_0_54 br_0_54 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c54 bl_0_54 br_0_54 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c54 bl_0_54 br_0_54 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c54 bl_0_54 br_0_54 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c54 bl_0_54 br_0_54 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c54 bl_0_54 br_0_54 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c55 bl_0_55 br_0_55 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c55 bl_0_55 br_0_55 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c55 bl_0_55 br_0_55 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c55 bl_0_55 br_0_55 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c55 bl_0_55 br_0_55 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c55 bl_0_55 br_0_55 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c55 bl_0_55 br_0_55 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c55 bl_0_55 br_0_55 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c55 bl_0_55 br_0_55 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c55 bl_0_55 br_0_55 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c55 bl_0_55 br_0_55 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c55 bl_0_55 br_0_55 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c55 bl_0_55 br_0_55 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c55 bl_0_55 br_0_55 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c55 bl_0_55 br_0_55 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c55 bl_0_55 br_0_55 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c55 bl_0_55 br_0_55 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c55 bl_0_55 br_0_55 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c55 bl_0_55 br_0_55 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c55 bl_0_55 br_0_55 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c55 bl_0_55 br_0_55 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c55 bl_0_55 br_0_55 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c55 bl_0_55 br_0_55 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c55 bl_0_55 br_0_55 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c55 bl_0_55 br_0_55 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c55 bl_0_55 br_0_55 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c55 bl_0_55 br_0_55 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c55 bl_0_55 br_0_55 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c55 bl_0_55 br_0_55 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c55 bl_0_55 br_0_55 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c55 bl_0_55 br_0_55 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c55 bl_0_55 br_0_55 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c55 bl_0_55 br_0_55 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c55 bl_0_55 br_0_55 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c55 bl_0_55 br_0_55 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c55 bl_0_55 br_0_55 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c55 bl_0_55 br_0_55 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c55 bl_0_55 br_0_55 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c55 bl_0_55 br_0_55 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c55 bl_0_55 br_0_55 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c55 bl_0_55 br_0_55 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c55 bl_0_55 br_0_55 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c55 bl_0_55 br_0_55 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c55 bl_0_55 br_0_55 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c55 bl_0_55 br_0_55 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c55 bl_0_55 br_0_55 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c55 bl_0_55 br_0_55 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c55 bl_0_55 br_0_55 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c55 bl_0_55 br_0_55 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c55 bl_0_55 br_0_55 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c55 bl_0_55 br_0_55 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c55 bl_0_55 br_0_55 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c55 bl_0_55 br_0_55 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c55 bl_0_55 br_0_55 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c55 bl_0_55 br_0_55 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c55 bl_0_55 br_0_55 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c55 bl_0_55 br_0_55 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c55 bl_0_55 br_0_55 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c55 bl_0_55 br_0_55 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c55 bl_0_55 br_0_55 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c55 bl_0_55 br_0_55 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c55 bl_0_55 br_0_55 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c55 bl_0_55 br_0_55 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c55 bl_0_55 br_0_55 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c56 bl_0_56 br_0_56 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c56 bl_0_56 br_0_56 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c56 bl_0_56 br_0_56 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c56 bl_0_56 br_0_56 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c56 bl_0_56 br_0_56 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c56 bl_0_56 br_0_56 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c56 bl_0_56 br_0_56 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c56 bl_0_56 br_0_56 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c56 bl_0_56 br_0_56 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c56 bl_0_56 br_0_56 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c56 bl_0_56 br_0_56 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c56 bl_0_56 br_0_56 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c56 bl_0_56 br_0_56 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c56 bl_0_56 br_0_56 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c56 bl_0_56 br_0_56 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c56 bl_0_56 br_0_56 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c56 bl_0_56 br_0_56 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c56 bl_0_56 br_0_56 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c56 bl_0_56 br_0_56 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c56 bl_0_56 br_0_56 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c56 bl_0_56 br_0_56 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c56 bl_0_56 br_0_56 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c56 bl_0_56 br_0_56 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c56 bl_0_56 br_0_56 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c56 bl_0_56 br_0_56 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c56 bl_0_56 br_0_56 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c56 bl_0_56 br_0_56 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c56 bl_0_56 br_0_56 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c56 bl_0_56 br_0_56 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c56 bl_0_56 br_0_56 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c56 bl_0_56 br_0_56 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c56 bl_0_56 br_0_56 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c56 bl_0_56 br_0_56 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c56 bl_0_56 br_0_56 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c56 bl_0_56 br_0_56 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c56 bl_0_56 br_0_56 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c56 bl_0_56 br_0_56 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c56 bl_0_56 br_0_56 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c56 bl_0_56 br_0_56 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c56 bl_0_56 br_0_56 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c56 bl_0_56 br_0_56 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c56 bl_0_56 br_0_56 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c56 bl_0_56 br_0_56 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c56 bl_0_56 br_0_56 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c56 bl_0_56 br_0_56 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c56 bl_0_56 br_0_56 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c56 bl_0_56 br_0_56 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c56 bl_0_56 br_0_56 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c56 bl_0_56 br_0_56 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c56 bl_0_56 br_0_56 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c56 bl_0_56 br_0_56 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c56 bl_0_56 br_0_56 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c56 bl_0_56 br_0_56 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c56 bl_0_56 br_0_56 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c56 bl_0_56 br_0_56 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c56 bl_0_56 br_0_56 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c56 bl_0_56 br_0_56 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c56 bl_0_56 br_0_56 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c56 bl_0_56 br_0_56 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c56 bl_0_56 br_0_56 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c56 bl_0_56 br_0_56 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c56 bl_0_56 br_0_56 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c56 bl_0_56 br_0_56 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c56 bl_0_56 br_0_56 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c57 bl_0_57 br_0_57 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c57 bl_0_57 br_0_57 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c57 bl_0_57 br_0_57 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c57 bl_0_57 br_0_57 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c57 bl_0_57 br_0_57 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c57 bl_0_57 br_0_57 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c57 bl_0_57 br_0_57 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c57 bl_0_57 br_0_57 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c57 bl_0_57 br_0_57 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c57 bl_0_57 br_0_57 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c57 bl_0_57 br_0_57 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c57 bl_0_57 br_0_57 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c57 bl_0_57 br_0_57 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c57 bl_0_57 br_0_57 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c57 bl_0_57 br_0_57 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c57 bl_0_57 br_0_57 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c57 bl_0_57 br_0_57 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c57 bl_0_57 br_0_57 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c57 bl_0_57 br_0_57 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c57 bl_0_57 br_0_57 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c57 bl_0_57 br_0_57 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c57 bl_0_57 br_0_57 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c57 bl_0_57 br_0_57 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c57 bl_0_57 br_0_57 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c57 bl_0_57 br_0_57 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c57 bl_0_57 br_0_57 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c57 bl_0_57 br_0_57 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c57 bl_0_57 br_0_57 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c57 bl_0_57 br_0_57 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c57 bl_0_57 br_0_57 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c57 bl_0_57 br_0_57 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c57 bl_0_57 br_0_57 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c57 bl_0_57 br_0_57 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c57 bl_0_57 br_0_57 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c57 bl_0_57 br_0_57 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c57 bl_0_57 br_0_57 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c57 bl_0_57 br_0_57 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c57 bl_0_57 br_0_57 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c57 bl_0_57 br_0_57 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c57 bl_0_57 br_0_57 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c57 bl_0_57 br_0_57 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c57 bl_0_57 br_0_57 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c57 bl_0_57 br_0_57 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c57 bl_0_57 br_0_57 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c57 bl_0_57 br_0_57 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c57 bl_0_57 br_0_57 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c57 bl_0_57 br_0_57 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c57 bl_0_57 br_0_57 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c57 bl_0_57 br_0_57 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c57 bl_0_57 br_0_57 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c57 bl_0_57 br_0_57 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c57 bl_0_57 br_0_57 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c57 bl_0_57 br_0_57 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c57 bl_0_57 br_0_57 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c57 bl_0_57 br_0_57 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c57 bl_0_57 br_0_57 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c57 bl_0_57 br_0_57 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c57 bl_0_57 br_0_57 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c57 bl_0_57 br_0_57 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c57 bl_0_57 br_0_57 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c57 bl_0_57 br_0_57 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c57 bl_0_57 br_0_57 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c57 bl_0_57 br_0_57 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c57 bl_0_57 br_0_57 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c58 bl_0_58 br_0_58 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c58 bl_0_58 br_0_58 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c58 bl_0_58 br_0_58 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c58 bl_0_58 br_0_58 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c58 bl_0_58 br_0_58 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c58 bl_0_58 br_0_58 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c58 bl_0_58 br_0_58 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c58 bl_0_58 br_0_58 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c58 bl_0_58 br_0_58 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c58 bl_0_58 br_0_58 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c58 bl_0_58 br_0_58 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c58 bl_0_58 br_0_58 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c58 bl_0_58 br_0_58 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c58 bl_0_58 br_0_58 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c58 bl_0_58 br_0_58 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c58 bl_0_58 br_0_58 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c58 bl_0_58 br_0_58 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c58 bl_0_58 br_0_58 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c58 bl_0_58 br_0_58 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c58 bl_0_58 br_0_58 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c58 bl_0_58 br_0_58 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c58 bl_0_58 br_0_58 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c58 bl_0_58 br_0_58 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c58 bl_0_58 br_0_58 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c58 bl_0_58 br_0_58 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c58 bl_0_58 br_0_58 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c58 bl_0_58 br_0_58 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c58 bl_0_58 br_0_58 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c58 bl_0_58 br_0_58 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c58 bl_0_58 br_0_58 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c58 bl_0_58 br_0_58 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c58 bl_0_58 br_0_58 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c58 bl_0_58 br_0_58 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c58 bl_0_58 br_0_58 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c58 bl_0_58 br_0_58 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c58 bl_0_58 br_0_58 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c58 bl_0_58 br_0_58 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c58 bl_0_58 br_0_58 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c58 bl_0_58 br_0_58 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c58 bl_0_58 br_0_58 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c58 bl_0_58 br_0_58 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c58 bl_0_58 br_0_58 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c58 bl_0_58 br_0_58 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c58 bl_0_58 br_0_58 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c58 bl_0_58 br_0_58 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c58 bl_0_58 br_0_58 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c58 bl_0_58 br_0_58 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c58 bl_0_58 br_0_58 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c58 bl_0_58 br_0_58 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c58 bl_0_58 br_0_58 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c58 bl_0_58 br_0_58 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c58 bl_0_58 br_0_58 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c58 bl_0_58 br_0_58 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c58 bl_0_58 br_0_58 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c58 bl_0_58 br_0_58 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c58 bl_0_58 br_0_58 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c58 bl_0_58 br_0_58 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c58 bl_0_58 br_0_58 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c58 bl_0_58 br_0_58 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c58 bl_0_58 br_0_58 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c58 bl_0_58 br_0_58 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c58 bl_0_58 br_0_58 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c58 bl_0_58 br_0_58 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c58 bl_0_58 br_0_58 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c59 bl_0_59 br_0_59 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c59 bl_0_59 br_0_59 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c59 bl_0_59 br_0_59 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c59 bl_0_59 br_0_59 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c59 bl_0_59 br_0_59 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c59 bl_0_59 br_0_59 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c59 bl_0_59 br_0_59 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c59 bl_0_59 br_0_59 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c59 bl_0_59 br_0_59 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c59 bl_0_59 br_0_59 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c59 bl_0_59 br_0_59 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c59 bl_0_59 br_0_59 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c59 bl_0_59 br_0_59 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c59 bl_0_59 br_0_59 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c59 bl_0_59 br_0_59 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c59 bl_0_59 br_0_59 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c59 bl_0_59 br_0_59 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c59 bl_0_59 br_0_59 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c59 bl_0_59 br_0_59 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c59 bl_0_59 br_0_59 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c59 bl_0_59 br_0_59 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c59 bl_0_59 br_0_59 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c59 bl_0_59 br_0_59 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c59 bl_0_59 br_0_59 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c59 bl_0_59 br_0_59 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c59 bl_0_59 br_0_59 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c59 bl_0_59 br_0_59 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c59 bl_0_59 br_0_59 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c59 bl_0_59 br_0_59 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c59 bl_0_59 br_0_59 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c59 bl_0_59 br_0_59 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c59 bl_0_59 br_0_59 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c59 bl_0_59 br_0_59 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c59 bl_0_59 br_0_59 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c59 bl_0_59 br_0_59 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c59 bl_0_59 br_0_59 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c59 bl_0_59 br_0_59 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c59 bl_0_59 br_0_59 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c59 bl_0_59 br_0_59 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c59 bl_0_59 br_0_59 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c59 bl_0_59 br_0_59 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c59 bl_0_59 br_0_59 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c59 bl_0_59 br_0_59 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c59 bl_0_59 br_0_59 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c59 bl_0_59 br_0_59 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c59 bl_0_59 br_0_59 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c59 bl_0_59 br_0_59 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c59 bl_0_59 br_0_59 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c59 bl_0_59 br_0_59 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c59 bl_0_59 br_0_59 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c59 bl_0_59 br_0_59 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c59 bl_0_59 br_0_59 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c59 bl_0_59 br_0_59 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c59 bl_0_59 br_0_59 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c59 bl_0_59 br_0_59 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c59 bl_0_59 br_0_59 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c59 bl_0_59 br_0_59 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c59 bl_0_59 br_0_59 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c59 bl_0_59 br_0_59 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c59 bl_0_59 br_0_59 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c59 bl_0_59 br_0_59 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c59 bl_0_59 br_0_59 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c59 bl_0_59 br_0_59 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c59 bl_0_59 br_0_59 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c60 bl_0_60 br_0_60 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c60 bl_0_60 br_0_60 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c60 bl_0_60 br_0_60 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c60 bl_0_60 br_0_60 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c60 bl_0_60 br_0_60 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c60 bl_0_60 br_0_60 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c60 bl_0_60 br_0_60 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c60 bl_0_60 br_0_60 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c60 bl_0_60 br_0_60 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c60 bl_0_60 br_0_60 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c60 bl_0_60 br_0_60 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c60 bl_0_60 br_0_60 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c60 bl_0_60 br_0_60 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c60 bl_0_60 br_0_60 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c60 bl_0_60 br_0_60 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c60 bl_0_60 br_0_60 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c60 bl_0_60 br_0_60 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c60 bl_0_60 br_0_60 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c60 bl_0_60 br_0_60 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c60 bl_0_60 br_0_60 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c60 bl_0_60 br_0_60 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c60 bl_0_60 br_0_60 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c60 bl_0_60 br_0_60 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c60 bl_0_60 br_0_60 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c60 bl_0_60 br_0_60 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c60 bl_0_60 br_0_60 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c60 bl_0_60 br_0_60 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c60 bl_0_60 br_0_60 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c60 bl_0_60 br_0_60 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c60 bl_0_60 br_0_60 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c60 bl_0_60 br_0_60 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c60 bl_0_60 br_0_60 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c60 bl_0_60 br_0_60 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c60 bl_0_60 br_0_60 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c60 bl_0_60 br_0_60 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c60 bl_0_60 br_0_60 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c60 bl_0_60 br_0_60 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c60 bl_0_60 br_0_60 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c60 bl_0_60 br_0_60 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c60 bl_0_60 br_0_60 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c60 bl_0_60 br_0_60 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c60 bl_0_60 br_0_60 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c60 bl_0_60 br_0_60 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c60 bl_0_60 br_0_60 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c60 bl_0_60 br_0_60 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c60 bl_0_60 br_0_60 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c60 bl_0_60 br_0_60 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c60 bl_0_60 br_0_60 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c60 bl_0_60 br_0_60 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c60 bl_0_60 br_0_60 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c60 bl_0_60 br_0_60 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c60 bl_0_60 br_0_60 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c60 bl_0_60 br_0_60 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c60 bl_0_60 br_0_60 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c60 bl_0_60 br_0_60 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c60 bl_0_60 br_0_60 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c60 bl_0_60 br_0_60 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c60 bl_0_60 br_0_60 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c60 bl_0_60 br_0_60 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c60 bl_0_60 br_0_60 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c60 bl_0_60 br_0_60 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c60 bl_0_60 br_0_60 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c60 bl_0_60 br_0_60 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c60 bl_0_60 br_0_60 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c61 bl_0_61 br_0_61 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c61 bl_0_61 br_0_61 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c61 bl_0_61 br_0_61 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c61 bl_0_61 br_0_61 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c61 bl_0_61 br_0_61 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c61 bl_0_61 br_0_61 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c61 bl_0_61 br_0_61 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c61 bl_0_61 br_0_61 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c61 bl_0_61 br_0_61 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c61 bl_0_61 br_0_61 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c61 bl_0_61 br_0_61 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c61 bl_0_61 br_0_61 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c61 bl_0_61 br_0_61 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c61 bl_0_61 br_0_61 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c61 bl_0_61 br_0_61 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c61 bl_0_61 br_0_61 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c61 bl_0_61 br_0_61 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c61 bl_0_61 br_0_61 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c61 bl_0_61 br_0_61 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c61 bl_0_61 br_0_61 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c61 bl_0_61 br_0_61 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c61 bl_0_61 br_0_61 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c61 bl_0_61 br_0_61 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c61 bl_0_61 br_0_61 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c61 bl_0_61 br_0_61 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c61 bl_0_61 br_0_61 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c61 bl_0_61 br_0_61 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c61 bl_0_61 br_0_61 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c61 bl_0_61 br_0_61 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c61 bl_0_61 br_0_61 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c61 bl_0_61 br_0_61 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c61 bl_0_61 br_0_61 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c61 bl_0_61 br_0_61 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c61 bl_0_61 br_0_61 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c61 bl_0_61 br_0_61 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c61 bl_0_61 br_0_61 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c61 bl_0_61 br_0_61 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c61 bl_0_61 br_0_61 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c61 bl_0_61 br_0_61 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c61 bl_0_61 br_0_61 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c61 bl_0_61 br_0_61 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c61 bl_0_61 br_0_61 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c61 bl_0_61 br_0_61 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c61 bl_0_61 br_0_61 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c61 bl_0_61 br_0_61 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c61 bl_0_61 br_0_61 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c61 bl_0_61 br_0_61 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c61 bl_0_61 br_0_61 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c61 bl_0_61 br_0_61 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c61 bl_0_61 br_0_61 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c61 bl_0_61 br_0_61 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c61 bl_0_61 br_0_61 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c61 bl_0_61 br_0_61 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c61 bl_0_61 br_0_61 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c61 bl_0_61 br_0_61 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c61 bl_0_61 br_0_61 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c61 bl_0_61 br_0_61 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c61 bl_0_61 br_0_61 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c61 bl_0_61 br_0_61 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c61 bl_0_61 br_0_61 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c61 bl_0_61 br_0_61 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c61 bl_0_61 br_0_61 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c61 bl_0_61 br_0_61 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c61 bl_0_61 br_0_61 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c62 bl_0_62 br_0_62 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c62 bl_0_62 br_0_62 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c62 bl_0_62 br_0_62 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c62 bl_0_62 br_0_62 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c62 bl_0_62 br_0_62 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c62 bl_0_62 br_0_62 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c62 bl_0_62 br_0_62 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c62 bl_0_62 br_0_62 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c62 bl_0_62 br_0_62 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c62 bl_0_62 br_0_62 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c62 bl_0_62 br_0_62 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c62 bl_0_62 br_0_62 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c62 bl_0_62 br_0_62 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c62 bl_0_62 br_0_62 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c62 bl_0_62 br_0_62 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c62 bl_0_62 br_0_62 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c62 bl_0_62 br_0_62 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c62 bl_0_62 br_0_62 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c62 bl_0_62 br_0_62 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c62 bl_0_62 br_0_62 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c62 bl_0_62 br_0_62 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c62 bl_0_62 br_0_62 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c62 bl_0_62 br_0_62 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c62 bl_0_62 br_0_62 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c62 bl_0_62 br_0_62 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c62 bl_0_62 br_0_62 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c62 bl_0_62 br_0_62 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c62 bl_0_62 br_0_62 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c62 bl_0_62 br_0_62 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c62 bl_0_62 br_0_62 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c62 bl_0_62 br_0_62 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c62 bl_0_62 br_0_62 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c62 bl_0_62 br_0_62 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c62 bl_0_62 br_0_62 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c62 bl_0_62 br_0_62 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c62 bl_0_62 br_0_62 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c62 bl_0_62 br_0_62 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c62 bl_0_62 br_0_62 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c62 bl_0_62 br_0_62 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c62 bl_0_62 br_0_62 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c62 bl_0_62 br_0_62 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c62 bl_0_62 br_0_62 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c62 bl_0_62 br_0_62 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c62 bl_0_62 br_0_62 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c62 bl_0_62 br_0_62 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c62 bl_0_62 br_0_62 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c62 bl_0_62 br_0_62 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c62 bl_0_62 br_0_62 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c62 bl_0_62 br_0_62 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c62 bl_0_62 br_0_62 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c62 bl_0_62 br_0_62 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c62 bl_0_62 br_0_62 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c62 bl_0_62 br_0_62 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c62 bl_0_62 br_0_62 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c62 bl_0_62 br_0_62 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c62 bl_0_62 br_0_62 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c62 bl_0_62 br_0_62 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c62 bl_0_62 br_0_62 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c62 bl_0_62 br_0_62 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c62 bl_0_62 br_0_62 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c62 bl_0_62 br_0_62 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c62 bl_0_62 br_0_62 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c62 bl_0_62 br_0_62 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c62 bl_0_62 br_0_62 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c63 bl_0_63 br_0_63 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c63 bl_0_63 br_0_63 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c63 bl_0_63 br_0_63 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c63 bl_0_63 br_0_63 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c63 bl_0_63 br_0_63 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c63 bl_0_63 br_0_63 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c63 bl_0_63 br_0_63 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c63 bl_0_63 br_0_63 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c63 bl_0_63 br_0_63 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c63 bl_0_63 br_0_63 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c63 bl_0_63 br_0_63 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c63 bl_0_63 br_0_63 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c63 bl_0_63 br_0_63 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c63 bl_0_63 br_0_63 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c63 bl_0_63 br_0_63 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c63 bl_0_63 br_0_63 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c63 bl_0_63 br_0_63 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c63 bl_0_63 br_0_63 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c63 bl_0_63 br_0_63 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c63 bl_0_63 br_0_63 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c63 bl_0_63 br_0_63 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c63 bl_0_63 br_0_63 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c63 bl_0_63 br_0_63 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c63 bl_0_63 br_0_63 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c63 bl_0_63 br_0_63 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c63 bl_0_63 br_0_63 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c63 bl_0_63 br_0_63 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c63 bl_0_63 br_0_63 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c63 bl_0_63 br_0_63 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c63 bl_0_63 br_0_63 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c63 bl_0_63 br_0_63 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c63 bl_0_63 br_0_63 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c63 bl_0_63 br_0_63 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c63 bl_0_63 br_0_63 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c63 bl_0_63 br_0_63 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c63 bl_0_63 br_0_63 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c63 bl_0_63 br_0_63 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c63 bl_0_63 br_0_63 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c63 bl_0_63 br_0_63 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c63 bl_0_63 br_0_63 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c63 bl_0_63 br_0_63 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c63 bl_0_63 br_0_63 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c63 bl_0_63 br_0_63 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c63 bl_0_63 br_0_63 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c63 bl_0_63 br_0_63 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c63 bl_0_63 br_0_63 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c63 bl_0_63 br_0_63 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c63 bl_0_63 br_0_63 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c63 bl_0_63 br_0_63 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c63 bl_0_63 br_0_63 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c63 bl_0_63 br_0_63 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c63 bl_0_63 br_0_63 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c63 bl_0_63 br_0_63 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c63 bl_0_63 br_0_63 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c63 bl_0_63 br_0_63 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c63 bl_0_63 br_0_63 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c63 bl_0_63 br_0_63 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c63 bl_0_63 br_0_63 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c63 bl_0_63 br_0_63 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c63 bl_0_63 br_0_63 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c63 bl_0_63 br_0_63 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c63 bl_0_63 br_0_63 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c63 bl_0_63 br_0_63 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c63 bl_0_63 br_0_63 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c64 bl_0_64 br_0_64 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c64 bl_0_64 br_0_64 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c64 bl_0_64 br_0_64 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c64 bl_0_64 br_0_64 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c64 bl_0_64 br_0_64 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c64 bl_0_64 br_0_64 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c64 bl_0_64 br_0_64 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c64 bl_0_64 br_0_64 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c64 bl_0_64 br_0_64 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c64 bl_0_64 br_0_64 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c64 bl_0_64 br_0_64 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c64 bl_0_64 br_0_64 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c64 bl_0_64 br_0_64 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c64 bl_0_64 br_0_64 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c64 bl_0_64 br_0_64 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c64 bl_0_64 br_0_64 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c64 bl_0_64 br_0_64 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c64 bl_0_64 br_0_64 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c64 bl_0_64 br_0_64 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c64 bl_0_64 br_0_64 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c64 bl_0_64 br_0_64 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c64 bl_0_64 br_0_64 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c64 bl_0_64 br_0_64 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c64 bl_0_64 br_0_64 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c64 bl_0_64 br_0_64 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c64 bl_0_64 br_0_64 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c64 bl_0_64 br_0_64 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c64 bl_0_64 br_0_64 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c64 bl_0_64 br_0_64 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c64 bl_0_64 br_0_64 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c64 bl_0_64 br_0_64 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c64 bl_0_64 br_0_64 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c64 bl_0_64 br_0_64 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c64 bl_0_64 br_0_64 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c64 bl_0_64 br_0_64 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c64 bl_0_64 br_0_64 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c64 bl_0_64 br_0_64 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c64 bl_0_64 br_0_64 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c64 bl_0_64 br_0_64 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c64 bl_0_64 br_0_64 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c64 bl_0_64 br_0_64 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c64 bl_0_64 br_0_64 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c64 bl_0_64 br_0_64 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c64 bl_0_64 br_0_64 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c64 bl_0_64 br_0_64 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c64 bl_0_64 br_0_64 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c64 bl_0_64 br_0_64 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c64 bl_0_64 br_0_64 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c64 bl_0_64 br_0_64 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c64 bl_0_64 br_0_64 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c64 bl_0_64 br_0_64 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c64 bl_0_64 br_0_64 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c64 bl_0_64 br_0_64 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c64 bl_0_64 br_0_64 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c64 bl_0_64 br_0_64 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c64 bl_0_64 br_0_64 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c64 bl_0_64 br_0_64 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c64 bl_0_64 br_0_64 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c64 bl_0_64 br_0_64 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c64 bl_0_64 br_0_64 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c64 bl_0_64 br_0_64 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c64 bl_0_64 br_0_64 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c64 bl_0_64 br_0_64 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c64 bl_0_64 br_0_64 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c65 bl_0_65 br_0_65 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c65 bl_0_65 br_0_65 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c65 bl_0_65 br_0_65 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c65 bl_0_65 br_0_65 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c65 bl_0_65 br_0_65 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c65 bl_0_65 br_0_65 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c65 bl_0_65 br_0_65 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c65 bl_0_65 br_0_65 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c65 bl_0_65 br_0_65 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c65 bl_0_65 br_0_65 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c65 bl_0_65 br_0_65 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c65 bl_0_65 br_0_65 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c65 bl_0_65 br_0_65 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c65 bl_0_65 br_0_65 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c65 bl_0_65 br_0_65 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c65 bl_0_65 br_0_65 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c65 bl_0_65 br_0_65 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c65 bl_0_65 br_0_65 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c65 bl_0_65 br_0_65 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c65 bl_0_65 br_0_65 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c65 bl_0_65 br_0_65 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c65 bl_0_65 br_0_65 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c65 bl_0_65 br_0_65 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c65 bl_0_65 br_0_65 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c65 bl_0_65 br_0_65 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c65 bl_0_65 br_0_65 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c65 bl_0_65 br_0_65 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c65 bl_0_65 br_0_65 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c65 bl_0_65 br_0_65 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c65 bl_0_65 br_0_65 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c65 bl_0_65 br_0_65 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c65 bl_0_65 br_0_65 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c65 bl_0_65 br_0_65 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c65 bl_0_65 br_0_65 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c65 bl_0_65 br_0_65 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c65 bl_0_65 br_0_65 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c65 bl_0_65 br_0_65 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c65 bl_0_65 br_0_65 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c65 bl_0_65 br_0_65 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c65 bl_0_65 br_0_65 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c65 bl_0_65 br_0_65 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c65 bl_0_65 br_0_65 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c65 bl_0_65 br_0_65 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c65 bl_0_65 br_0_65 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c65 bl_0_65 br_0_65 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c65 bl_0_65 br_0_65 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c65 bl_0_65 br_0_65 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c65 bl_0_65 br_0_65 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c65 bl_0_65 br_0_65 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c65 bl_0_65 br_0_65 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c65 bl_0_65 br_0_65 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c65 bl_0_65 br_0_65 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c65 bl_0_65 br_0_65 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c65 bl_0_65 br_0_65 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c65 bl_0_65 br_0_65 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c65 bl_0_65 br_0_65 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c65 bl_0_65 br_0_65 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c65 bl_0_65 br_0_65 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c65 bl_0_65 br_0_65 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c65 bl_0_65 br_0_65 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c65 bl_0_65 br_0_65 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c65 bl_0_65 br_0_65 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c65 bl_0_65 br_0_65 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c65 bl_0_65 br_0_65 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c66 bl_0_66 br_0_66 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c66 bl_0_66 br_0_66 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c66 bl_0_66 br_0_66 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c66 bl_0_66 br_0_66 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c66 bl_0_66 br_0_66 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c66 bl_0_66 br_0_66 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c66 bl_0_66 br_0_66 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c66 bl_0_66 br_0_66 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c66 bl_0_66 br_0_66 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c66 bl_0_66 br_0_66 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c66 bl_0_66 br_0_66 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c66 bl_0_66 br_0_66 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c66 bl_0_66 br_0_66 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c66 bl_0_66 br_0_66 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c66 bl_0_66 br_0_66 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c66 bl_0_66 br_0_66 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c66 bl_0_66 br_0_66 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c66 bl_0_66 br_0_66 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c66 bl_0_66 br_0_66 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c66 bl_0_66 br_0_66 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c66 bl_0_66 br_0_66 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c66 bl_0_66 br_0_66 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c66 bl_0_66 br_0_66 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c66 bl_0_66 br_0_66 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c66 bl_0_66 br_0_66 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c66 bl_0_66 br_0_66 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c66 bl_0_66 br_0_66 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c66 bl_0_66 br_0_66 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c66 bl_0_66 br_0_66 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c66 bl_0_66 br_0_66 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c66 bl_0_66 br_0_66 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c66 bl_0_66 br_0_66 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c66 bl_0_66 br_0_66 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c66 bl_0_66 br_0_66 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c66 bl_0_66 br_0_66 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c66 bl_0_66 br_0_66 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c66 bl_0_66 br_0_66 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c66 bl_0_66 br_0_66 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c66 bl_0_66 br_0_66 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c66 bl_0_66 br_0_66 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c66 bl_0_66 br_0_66 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c66 bl_0_66 br_0_66 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c66 bl_0_66 br_0_66 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c66 bl_0_66 br_0_66 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c66 bl_0_66 br_0_66 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c66 bl_0_66 br_0_66 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c66 bl_0_66 br_0_66 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c66 bl_0_66 br_0_66 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c66 bl_0_66 br_0_66 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c66 bl_0_66 br_0_66 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c66 bl_0_66 br_0_66 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c66 bl_0_66 br_0_66 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c66 bl_0_66 br_0_66 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c66 bl_0_66 br_0_66 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c66 bl_0_66 br_0_66 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c66 bl_0_66 br_0_66 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c66 bl_0_66 br_0_66 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c66 bl_0_66 br_0_66 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c66 bl_0_66 br_0_66 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c66 bl_0_66 br_0_66 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c66 bl_0_66 br_0_66 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c66 bl_0_66 br_0_66 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c66 bl_0_66 br_0_66 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c66 bl_0_66 br_0_66 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c67 bl_0_67 br_0_67 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c67 bl_0_67 br_0_67 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c67 bl_0_67 br_0_67 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c67 bl_0_67 br_0_67 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c67 bl_0_67 br_0_67 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c67 bl_0_67 br_0_67 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c67 bl_0_67 br_0_67 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c67 bl_0_67 br_0_67 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c67 bl_0_67 br_0_67 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c67 bl_0_67 br_0_67 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c67 bl_0_67 br_0_67 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c67 bl_0_67 br_0_67 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c67 bl_0_67 br_0_67 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c67 bl_0_67 br_0_67 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c67 bl_0_67 br_0_67 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c67 bl_0_67 br_0_67 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c67 bl_0_67 br_0_67 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c67 bl_0_67 br_0_67 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c67 bl_0_67 br_0_67 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c67 bl_0_67 br_0_67 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c67 bl_0_67 br_0_67 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c67 bl_0_67 br_0_67 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c67 bl_0_67 br_0_67 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c67 bl_0_67 br_0_67 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c67 bl_0_67 br_0_67 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c67 bl_0_67 br_0_67 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c67 bl_0_67 br_0_67 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c67 bl_0_67 br_0_67 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c67 bl_0_67 br_0_67 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c67 bl_0_67 br_0_67 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c67 bl_0_67 br_0_67 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c67 bl_0_67 br_0_67 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c67 bl_0_67 br_0_67 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c67 bl_0_67 br_0_67 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c67 bl_0_67 br_0_67 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c67 bl_0_67 br_0_67 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c67 bl_0_67 br_0_67 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c67 bl_0_67 br_0_67 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c67 bl_0_67 br_0_67 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c67 bl_0_67 br_0_67 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c67 bl_0_67 br_0_67 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c67 bl_0_67 br_0_67 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c67 bl_0_67 br_0_67 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c67 bl_0_67 br_0_67 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c67 bl_0_67 br_0_67 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c67 bl_0_67 br_0_67 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c67 bl_0_67 br_0_67 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c67 bl_0_67 br_0_67 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c67 bl_0_67 br_0_67 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c67 bl_0_67 br_0_67 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c67 bl_0_67 br_0_67 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c67 bl_0_67 br_0_67 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c67 bl_0_67 br_0_67 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c67 bl_0_67 br_0_67 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c67 bl_0_67 br_0_67 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c67 bl_0_67 br_0_67 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c67 bl_0_67 br_0_67 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c67 bl_0_67 br_0_67 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c67 bl_0_67 br_0_67 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c67 bl_0_67 br_0_67 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c67 bl_0_67 br_0_67 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c67 bl_0_67 br_0_67 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c67 bl_0_67 br_0_67 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c67 bl_0_67 br_0_67 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c68 bl_0_68 br_0_68 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c68 bl_0_68 br_0_68 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c68 bl_0_68 br_0_68 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c68 bl_0_68 br_0_68 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c68 bl_0_68 br_0_68 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c68 bl_0_68 br_0_68 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c68 bl_0_68 br_0_68 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c68 bl_0_68 br_0_68 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c68 bl_0_68 br_0_68 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c68 bl_0_68 br_0_68 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c68 bl_0_68 br_0_68 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c68 bl_0_68 br_0_68 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c68 bl_0_68 br_0_68 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c68 bl_0_68 br_0_68 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c68 bl_0_68 br_0_68 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c68 bl_0_68 br_0_68 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c68 bl_0_68 br_0_68 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c68 bl_0_68 br_0_68 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c68 bl_0_68 br_0_68 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c68 bl_0_68 br_0_68 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c68 bl_0_68 br_0_68 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c68 bl_0_68 br_0_68 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c68 bl_0_68 br_0_68 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c68 bl_0_68 br_0_68 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c68 bl_0_68 br_0_68 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c68 bl_0_68 br_0_68 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c68 bl_0_68 br_0_68 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c68 bl_0_68 br_0_68 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c68 bl_0_68 br_0_68 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c68 bl_0_68 br_0_68 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c68 bl_0_68 br_0_68 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c68 bl_0_68 br_0_68 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c68 bl_0_68 br_0_68 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c68 bl_0_68 br_0_68 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c68 bl_0_68 br_0_68 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c68 bl_0_68 br_0_68 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c68 bl_0_68 br_0_68 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c68 bl_0_68 br_0_68 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c68 bl_0_68 br_0_68 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c68 bl_0_68 br_0_68 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c68 bl_0_68 br_0_68 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c68 bl_0_68 br_0_68 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c68 bl_0_68 br_0_68 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c68 bl_0_68 br_0_68 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c68 bl_0_68 br_0_68 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c68 bl_0_68 br_0_68 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c68 bl_0_68 br_0_68 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c68 bl_0_68 br_0_68 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c68 bl_0_68 br_0_68 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c68 bl_0_68 br_0_68 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c68 bl_0_68 br_0_68 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c68 bl_0_68 br_0_68 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c68 bl_0_68 br_0_68 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c68 bl_0_68 br_0_68 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c68 bl_0_68 br_0_68 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c68 bl_0_68 br_0_68 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c68 bl_0_68 br_0_68 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c68 bl_0_68 br_0_68 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c68 bl_0_68 br_0_68 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c68 bl_0_68 br_0_68 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c68 bl_0_68 br_0_68 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c68 bl_0_68 br_0_68 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c68 bl_0_68 br_0_68 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c68 bl_0_68 br_0_68 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c69 bl_0_69 br_0_69 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c69 bl_0_69 br_0_69 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c69 bl_0_69 br_0_69 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c69 bl_0_69 br_0_69 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c69 bl_0_69 br_0_69 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c69 bl_0_69 br_0_69 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c69 bl_0_69 br_0_69 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c69 bl_0_69 br_0_69 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c69 bl_0_69 br_0_69 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c69 bl_0_69 br_0_69 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c69 bl_0_69 br_0_69 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c69 bl_0_69 br_0_69 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c69 bl_0_69 br_0_69 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c69 bl_0_69 br_0_69 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c69 bl_0_69 br_0_69 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c69 bl_0_69 br_0_69 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c69 bl_0_69 br_0_69 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c69 bl_0_69 br_0_69 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c69 bl_0_69 br_0_69 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c69 bl_0_69 br_0_69 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c69 bl_0_69 br_0_69 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c69 bl_0_69 br_0_69 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c69 bl_0_69 br_0_69 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c69 bl_0_69 br_0_69 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c69 bl_0_69 br_0_69 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c69 bl_0_69 br_0_69 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c69 bl_0_69 br_0_69 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c69 bl_0_69 br_0_69 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c69 bl_0_69 br_0_69 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c69 bl_0_69 br_0_69 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c69 bl_0_69 br_0_69 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c69 bl_0_69 br_0_69 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c69 bl_0_69 br_0_69 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c69 bl_0_69 br_0_69 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c69 bl_0_69 br_0_69 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c69 bl_0_69 br_0_69 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c69 bl_0_69 br_0_69 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c69 bl_0_69 br_0_69 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c69 bl_0_69 br_0_69 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c69 bl_0_69 br_0_69 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c69 bl_0_69 br_0_69 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c69 bl_0_69 br_0_69 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c69 bl_0_69 br_0_69 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c69 bl_0_69 br_0_69 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c69 bl_0_69 br_0_69 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c69 bl_0_69 br_0_69 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c69 bl_0_69 br_0_69 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c69 bl_0_69 br_0_69 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c69 bl_0_69 br_0_69 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c69 bl_0_69 br_0_69 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c69 bl_0_69 br_0_69 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c69 bl_0_69 br_0_69 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c69 bl_0_69 br_0_69 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c69 bl_0_69 br_0_69 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c69 bl_0_69 br_0_69 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c69 bl_0_69 br_0_69 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c69 bl_0_69 br_0_69 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c69 bl_0_69 br_0_69 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c69 bl_0_69 br_0_69 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c69 bl_0_69 br_0_69 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c69 bl_0_69 br_0_69 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c69 bl_0_69 br_0_69 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c69 bl_0_69 br_0_69 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c69 bl_0_69 br_0_69 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c70 bl_0_70 br_0_70 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c70 bl_0_70 br_0_70 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c70 bl_0_70 br_0_70 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c70 bl_0_70 br_0_70 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c70 bl_0_70 br_0_70 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c70 bl_0_70 br_0_70 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c70 bl_0_70 br_0_70 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c70 bl_0_70 br_0_70 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c70 bl_0_70 br_0_70 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c70 bl_0_70 br_0_70 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c70 bl_0_70 br_0_70 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c70 bl_0_70 br_0_70 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c70 bl_0_70 br_0_70 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c70 bl_0_70 br_0_70 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c70 bl_0_70 br_0_70 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c70 bl_0_70 br_0_70 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c70 bl_0_70 br_0_70 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c70 bl_0_70 br_0_70 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c70 bl_0_70 br_0_70 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c70 bl_0_70 br_0_70 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c70 bl_0_70 br_0_70 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c70 bl_0_70 br_0_70 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c70 bl_0_70 br_0_70 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c70 bl_0_70 br_0_70 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c70 bl_0_70 br_0_70 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c70 bl_0_70 br_0_70 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c70 bl_0_70 br_0_70 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c70 bl_0_70 br_0_70 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c70 bl_0_70 br_0_70 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c70 bl_0_70 br_0_70 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c70 bl_0_70 br_0_70 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c70 bl_0_70 br_0_70 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c70 bl_0_70 br_0_70 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c70 bl_0_70 br_0_70 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c70 bl_0_70 br_0_70 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c70 bl_0_70 br_0_70 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c70 bl_0_70 br_0_70 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c70 bl_0_70 br_0_70 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c70 bl_0_70 br_0_70 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c70 bl_0_70 br_0_70 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c70 bl_0_70 br_0_70 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c70 bl_0_70 br_0_70 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c70 bl_0_70 br_0_70 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c70 bl_0_70 br_0_70 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c70 bl_0_70 br_0_70 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c70 bl_0_70 br_0_70 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c70 bl_0_70 br_0_70 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c70 bl_0_70 br_0_70 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c70 bl_0_70 br_0_70 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c70 bl_0_70 br_0_70 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c70 bl_0_70 br_0_70 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c70 bl_0_70 br_0_70 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c70 bl_0_70 br_0_70 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c70 bl_0_70 br_0_70 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c70 bl_0_70 br_0_70 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c70 bl_0_70 br_0_70 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c70 bl_0_70 br_0_70 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c70 bl_0_70 br_0_70 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c70 bl_0_70 br_0_70 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c70 bl_0_70 br_0_70 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c70 bl_0_70 br_0_70 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c70 bl_0_70 br_0_70 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c70 bl_0_70 br_0_70 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c70 bl_0_70 br_0_70 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c71 bl_0_71 br_0_71 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c71 bl_0_71 br_0_71 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c71 bl_0_71 br_0_71 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c71 bl_0_71 br_0_71 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c71 bl_0_71 br_0_71 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c71 bl_0_71 br_0_71 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c71 bl_0_71 br_0_71 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c71 bl_0_71 br_0_71 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c71 bl_0_71 br_0_71 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c71 bl_0_71 br_0_71 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c71 bl_0_71 br_0_71 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c71 bl_0_71 br_0_71 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c71 bl_0_71 br_0_71 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c71 bl_0_71 br_0_71 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c71 bl_0_71 br_0_71 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c71 bl_0_71 br_0_71 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c71 bl_0_71 br_0_71 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c71 bl_0_71 br_0_71 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c71 bl_0_71 br_0_71 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c71 bl_0_71 br_0_71 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c71 bl_0_71 br_0_71 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c71 bl_0_71 br_0_71 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c71 bl_0_71 br_0_71 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c71 bl_0_71 br_0_71 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c71 bl_0_71 br_0_71 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c71 bl_0_71 br_0_71 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c71 bl_0_71 br_0_71 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c71 bl_0_71 br_0_71 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c71 bl_0_71 br_0_71 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c71 bl_0_71 br_0_71 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c71 bl_0_71 br_0_71 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c71 bl_0_71 br_0_71 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c71 bl_0_71 br_0_71 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c71 bl_0_71 br_0_71 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c71 bl_0_71 br_0_71 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c71 bl_0_71 br_0_71 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c71 bl_0_71 br_0_71 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c71 bl_0_71 br_0_71 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c71 bl_0_71 br_0_71 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c71 bl_0_71 br_0_71 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c71 bl_0_71 br_0_71 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c71 bl_0_71 br_0_71 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c71 bl_0_71 br_0_71 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c71 bl_0_71 br_0_71 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c71 bl_0_71 br_0_71 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c71 bl_0_71 br_0_71 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c71 bl_0_71 br_0_71 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c71 bl_0_71 br_0_71 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c71 bl_0_71 br_0_71 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c71 bl_0_71 br_0_71 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c71 bl_0_71 br_0_71 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c71 bl_0_71 br_0_71 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c71 bl_0_71 br_0_71 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c71 bl_0_71 br_0_71 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c71 bl_0_71 br_0_71 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c71 bl_0_71 br_0_71 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c71 bl_0_71 br_0_71 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c71 bl_0_71 br_0_71 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c71 bl_0_71 br_0_71 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c71 bl_0_71 br_0_71 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c71 bl_0_71 br_0_71 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c71 bl_0_71 br_0_71 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c71 bl_0_71 br_0_71 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c71 bl_0_71 br_0_71 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c72 bl_0_72 br_0_72 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c72 bl_0_72 br_0_72 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c72 bl_0_72 br_0_72 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c72 bl_0_72 br_0_72 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c72 bl_0_72 br_0_72 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c72 bl_0_72 br_0_72 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c72 bl_0_72 br_0_72 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c72 bl_0_72 br_0_72 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c72 bl_0_72 br_0_72 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c72 bl_0_72 br_0_72 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c72 bl_0_72 br_0_72 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c72 bl_0_72 br_0_72 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c72 bl_0_72 br_0_72 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c72 bl_0_72 br_0_72 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c72 bl_0_72 br_0_72 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c72 bl_0_72 br_0_72 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c72 bl_0_72 br_0_72 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c72 bl_0_72 br_0_72 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c72 bl_0_72 br_0_72 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c72 bl_0_72 br_0_72 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c72 bl_0_72 br_0_72 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c72 bl_0_72 br_0_72 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c72 bl_0_72 br_0_72 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c72 bl_0_72 br_0_72 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c72 bl_0_72 br_0_72 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c72 bl_0_72 br_0_72 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c72 bl_0_72 br_0_72 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c72 bl_0_72 br_0_72 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c72 bl_0_72 br_0_72 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c72 bl_0_72 br_0_72 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c72 bl_0_72 br_0_72 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c72 bl_0_72 br_0_72 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c72 bl_0_72 br_0_72 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c72 bl_0_72 br_0_72 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c72 bl_0_72 br_0_72 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c72 bl_0_72 br_0_72 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c72 bl_0_72 br_0_72 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c72 bl_0_72 br_0_72 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c72 bl_0_72 br_0_72 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c72 bl_0_72 br_0_72 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c72 bl_0_72 br_0_72 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c72 bl_0_72 br_0_72 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c72 bl_0_72 br_0_72 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c72 bl_0_72 br_0_72 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c72 bl_0_72 br_0_72 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c72 bl_0_72 br_0_72 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c72 bl_0_72 br_0_72 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c72 bl_0_72 br_0_72 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c72 bl_0_72 br_0_72 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c72 bl_0_72 br_0_72 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c72 bl_0_72 br_0_72 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c72 bl_0_72 br_0_72 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c72 bl_0_72 br_0_72 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c72 bl_0_72 br_0_72 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c72 bl_0_72 br_0_72 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c72 bl_0_72 br_0_72 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c72 bl_0_72 br_0_72 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c72 bl_0_72 br_0_72 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c72 bl_0_72 br_0_72 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c72 bl_0_72 br_0_72 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c72 bl_0_72 br_0_72 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c72 bl_0_72 br_0_72 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c72 bl_0_72 br_0_72 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c72 bl_0_72 br_0_72 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c73 bl_0_73 br_0_73 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c73 bl_0_73 br_0_73 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c73 bl_0_73 br_0_73 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c73 bl_0_73 br_0_73 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c73 bl_0_73 br_0_73 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c73 bl_0_73 br_0_73 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c73 bl_0_73 br_0_73 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c73 bl_0_73 br_0_73 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c73 bl_0_73 br_0_73 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c73 bl_0_73 br_0_73 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c73 bl_0_73 br_0_73 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c73 bl_0_73 br_0_73 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c73 bl_0_73 br_0_73 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c73 bl_0_73 br_0_73 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c73 bl_0_73 br_0_73 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c73 bl_0_73 br_0_73 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c73 bl_0_73 br_0_73 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c73 bl_0_73 br_0_73 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c73 bl_0_73 br_0_73 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c73 bl_0_73 br_0_73 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c73 bl_0_73 br_0_73 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c73 bl_0_73 br_0_73 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c73 bl_0_73 br_0_73 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c73 bl_0_73 br_0_73 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c73 bl_0_73 br_0_73 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c73 bl_0_73 br_0_73 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c73 bl_0_73 br_0_73 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c73 bl_0_73 br_0_73 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c73 bl_0_73 br_0_73 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c73 bl_0_73 br_0_73 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c73 bl_0_73 br_0_73 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c73 bl_0_73 br_0_73 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c73 bl_0_73 br_0_73 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c73 bl_0_73 br_0_73 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c73 bl_0_73 br_0_73 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c73 bl_0_73 br_0_73 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c73 bl_0_73 br_0_73 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c73 bl_0_73 br_0_73 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c73 bl_0_73 br_0_73 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c73 bl_0_73 br_0_73 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c73 bl_0_73 br_0_73 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c73 bl_0_73 br_0_73 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c73 bl_0_73 br_0_73 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c73 bl_0_73 br_0_73 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c73 bl_0_73 br_0_73 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c73 bl_0_73 br_0_73 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c73 bl_0_73 br_0_73 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c73 bl_0_73 br_0_73 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c73 bl_0_73 br_0_73 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c73 bl_0_73 br_0_73 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c73 bl_0_73 br_0_73 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c73 bl_0_73 br_0_73 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c73 bl_0_73 br_0_73 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c73 bl_0_73 br_0_73 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c73 bl_0_73 br_0_73 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c73 bl_0_73 br_0_73 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c73 bl_0_73 br_0_73 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c73 bl_0_73 br_0_73 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c73 bl_0_73 br_0_73 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c73 bl_0_73 br_0_73 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c73 bl_0_73 br_0_73 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c73 bl_0_73 br_0_73 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c73 bl_0_73 br_0_73 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c73 bl_0_73 br_0_73 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c74 bl_0_74 br_0_74 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c74 bl_0_74 br_0_74 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c74 bl_0_74 br_0_74 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c74 bl_0_74 br_0_74 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c74 bl_0_74 br_0_74 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c74 bl_0_74 br_0_74 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c74 bl_0_74 br_0_74 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c74 bl_0_74 br_0_74 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c74 bl_0_74 br_0_74 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c74 bl_0_74 br_0_74 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c74 bl_0_74 br_0_74 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c74 bl_0_74 br_0_74 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c74 bl_0_74 br_0_74 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c74 bl_0_74 br_0_74 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c74 bl_0_74 br_0_74 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c74 bl_0_74 br_0_74 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c74 bl_0_74 br_0_74 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c74 bl_0_74 br_0_74 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c74 bl_0_74 br_0_74 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c74 bl_0_74 br_0_74 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c74 bl_0_74 br_0_74 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c74 bl_0_74 br_0_74 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c74 bl_0_74 br_0_74 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c74 bl_0_74 br_0_74 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c74 bl_0_74 br_0_74 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c74 bl_0_74 br_0_74 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c74 bl_0_74 br_0_74 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c74 bl_0_74 br_0_74 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c74 bl_0_74 br_0_74 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c74 bl_0_74 br_0_74 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c74 bl_0_74 br_0_74 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c74 bl_0_74 br_0_74 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c74 bl_0_74 br_0_74 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c74 bl_0_74 br_0_74 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c74 bl_0_74 br_0_74 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c74 bl_0_74 br_0_74 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c74 bl_0_74 br_0_74 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c74 bl_0_74 br_0_74 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c74 bl_0_74 br_0_74 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c74 bl_0_74 br_0_74 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c74 bl_0_74 br_0_74 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c74 bl_0_74 br_0_74 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c74 bl_0_74 br_0_74 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c74 bl_0_74 br_0_74 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c74 bl_0_74 br_0_74 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c74 bl_0_74 br_0_74 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c74 bl_0_74 br_0_74 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c74 bl_0_74 br_0_74 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c74 bl_0_74 br_0_74 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c74 bl_0_74 br_0_74 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c74 bl_0_74 br_0_74 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c74 bl_0_74 br_0_74 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c74 bl_0_74 br_0_74 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c74 bl_0_74 br_0_74 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c74 bl_0_74 br_0_74 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c74 bl_0_74 br_0_74 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c74 bl_0_74 br_0_74 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c74 bl_0_74 br_0_74 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c74 bl_0_74 br_0_74 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c74 bl_0_74 br_0_74 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c74 bl_0_74 br_0_74 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c74 bl_0_74 br_0_74 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c74 bl_0_74 br_0_74 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c74 bl_0_74 br_0_74 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c75 bl_0_75 br_0_75 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c75 bl_0_75 br_0_75 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c75 bl_0_75 br_0_75 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c75 bl_0_75 br_0_75 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c75 bl_0_75 br_0_75 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c75 bl_0_75 br_0_75 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c75 bl_0_75 br_0_75 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c75 bl_0_75 br_0_75 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c75 bl_0_75 br_0_75 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c75 bl_0_75 br_0_75 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c75 bl_0_75 br_0_75 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c75 bl_0_75 br_0_75 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c75 bl_0_75 br_0_75 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c75 bl_0_75 br_0_75 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c75 bl_0_75 br_0_75 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c75 bl_0_75 br_0_75 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c75 bl_0_75 br_0_75 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c75 bl_0_75 br_0_75 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c75 bl_0_75 br_0_75 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c75 bl_0_75 br_0_75 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c75 bl_0_75 br_0_75 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c75 bl_0_75 br_0_75 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c75 bl_0_75 br_0_75 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c75 bl_0_75 br_0_75 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c75 bl_0_75 br_0_75 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c75 bl_0_75 br_0_75 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c75 bl_0_75 br_0_75 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c75 bl_0_75 br_0_75 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c75 bl_0_75 br_0_75 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c75 bl_0_75 br_0_75 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c75 bl_0_75 br_0_75 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c75 bl_0_75 br_0_75 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c75 bl_0_75 br_0_75 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c75 bl_0_75 br_0_75 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c75 bl_0_75 br_0_75 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c75 bl_0_75 br_0_75 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c75 bl_0_75 br_0_75 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c75 bl_0_75 br_0_75 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c75 bl_0_75 br_0_75 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c75 bl_0_75 br_0_75 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c75 bl_0_75 br_0_75 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c75 bl_0_75 br_0_75 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c75 bl_0_75 br_0_75 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c75 bl_0_75 br_0_75 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c75 bl_0_75 br_0_75 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c75 bl_0_75 br_0_75 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c75 bl_0_75 br_0_75 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c75 bl_0_75 br_0_75 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c75 bl_0_75 br_0_75 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c75 bl_0_75 br_0_75 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c75 bl_0_75 br_0_75 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c75 bl_0_75 br_0_75 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c75 bl_0_75 br_0_75 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c75 bl_0_75 br_0_75 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c75 bl_0_75 br_0_75 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c75 bl_0_75 br_0_75 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c75 bl_0_75 br_0_75 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c75 bl_0_75 br_0_75 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c75 bl_0_75 br_0_75 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c75 bl_0_75 br_0_75 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c75 bl_0_75 br_0_75 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c75 bl_0_75 br_0_75 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c75 bl_0_75 br_0_75 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c75 bl_0_75 br_0_75 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c76 bl_0_76 br_0_76 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c76 bl_0_76 br_0_76 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c76 bl_0_76 br_0_76 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c76 bl_0_76 br_0_76 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c76 bl_0_76 br_0_76 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c76 bl_0_76 br_0_76 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c76 bl_0_76 br_0_76 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c76 bl_0_76 br_0_76 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c76 bl_0_76 br_0_76 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c76 bl_0_76 br_0_76 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c76 bl_0_76 br_0_76 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c76 bl_0_76 br_0_76 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c76 bl_0_76 br_0_76 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c76 bl_0_76 br_0_76 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c76 bl_0_76 br_0_76 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c76 bl_0_76 br_0_76 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c76 bl_0_76 br_0_76 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c76 bl_0_76 br_0_76 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c76 bl_0_76 br_0_76 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c76 bl_0_76 br_0_76 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c76 bl_0_76 br_0_76 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c76 bl_0_76 br_0_76 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c76 bl_0_76 br_0_76 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c76 bl_0_76 br_0_76 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c76 bl_0_76 br_0_76 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c76 bl_0_76 br_0_76 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c76 bl_0_76 br_0_76 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c76 bl_0_76 br_0_76 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c76 bl_0_76 br_0_76 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c76 bl_0_76 br_0_76 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c76 bl_0_76 br_0_76 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c76 bl_0_76 br_0_76 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c76 bl_0_76 br_0_76 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c76 bl_0_76 br_0_76 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c76 bl_0_76 br_0_76 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c76 bl_0_76 br_0_76 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c76 bl_0_76 br_0_76 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c76 bl_0_76 br_0_76 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c76 bl_0_76 br_0_76 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c76 bl_0_76 br_0_76 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c76 bl_0_76 br_0_76 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c76 bl_0_76 br_0_76 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c76 bl_0_76 br_0_76 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c76 bl_0_76 br_0_76 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c76 bl_0_76 br_0_76 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c76 bl_0_76 br_0_76 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c76 bl_0_76 br_0_76 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c76 bl_0_76 br_0_76 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c76 bl_0_76 br_0_76 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c76 bl_0_76 br_0_76 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c76 bl_0_76 br_0_76 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c76 bl_0_76 br_0_76 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c76 bl_0_76 br_0_76 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c76 bl_0_76 br_0_76 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c76 bl_0_76 br_0_76 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c76 bl_0_76 br_0_76 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c76 bl_0_76 br_0_76 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c76 bl_0_76 br_0_76 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c76 bl_0_76 br_0_76 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c76 bl_0_76 br_0_76 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c76 bl_0_76 br_0_76 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c76 bl_0_76 br_0_76 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c76 bl_0_76 br_0_76 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c76 bl_0_76 br_0_76 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c77 bl_0_77 br_0_77 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c77 bl_0_77 br_0_77 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c77 bl_0_77 br_0_77 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c77 bl_0_77 br_0_77 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c77 bl_0_77 br_0_77 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c77 bl_0_77 br_0_77 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c77 bl_0_77 br_0_77 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c77 bl_0_77 br_0_77 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c77 bl_0_77 br_0_77 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c77 bl_0_77 br_0_77 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c77 bl_0_77 br_0_77 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c77 bl_0_77 br_0_77 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c77 bl_0_77 br_0_77 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c77 bl_0_77 br_0_77 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c77 bl_0_77 br_0_77 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c77 bl_0_77 br_0_77 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c77 bl_0_77 br_0_77 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c77 bl_0_77 br_0_77 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c77 bl_0_77 br_0_77 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c77 bl_0_77 br_0_77 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c77 bl_0_77 br_0_77 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c77 bl_0_77 br_0_77 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c77 bl_0_77 br_0_77 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c77 bl_0_77 br_0_77 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c77 bl_0_77 br_0_77 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c77 bl_0_77 br_0_77 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c77 bl_0_77 br_0_77 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c77 bl_0_77 br_0_77 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c77 bl_0_77 br_0_77 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c77 bl_0_77 br_0_77 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c77 bl_0_77 br_0_77 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c77 bl_0_77 br_0_77 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c77 bl_0_77 br_0_77 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c77 bl_0_77 br_0_77 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c77 bl_0_77 br_0_77 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c77 bl_0_77 br_0_77 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c77 bl_0_77 br_0_77 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c77 bl_0_77 br_0_77 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c77 bl_0_77 br_0_77 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c77 bl_0_77 br_0_77 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c77 bl_0_77 br_0_77 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c77 bl_0_77 br_0_77 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c77 bl_0_77 br_0_77 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c77 bl_0_77 br_0_77 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c77 bl_0_77 br_0_77 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c77 bl_0_77 br_0_77 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c77 bl_0_77 br_0_77 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c77 bl_0_77 br_0_77 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c77 bl_0_77 br_0_77 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c77 bl_0_77 br_0_77 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c77 bl_0_77 br_0_77 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c77 bl_0_77 br_0_77 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c77 bl_0_77 br_0_77 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c77 bl_0_77 br_0_77 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c77 bl_0_77 br_0_77 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c77 bl_0_77 br_0_77 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c77 bl_0_77 br_0_77 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c77 bl_0_77 br_0_77 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c77 bl_0_77 br_0_77 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c77 bl_0_77 br_0_77 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c77 bl_0_77 br_0_77 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c77 bl_0_77 br_0_77 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c77 bl_0_77 br_0_77 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c77 bl_0_77 br_0_77 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c78 bl_0_78 br_0_78 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c78 bl_0_78 br_0_78 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c78 bl_0_78 br_0_78 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c78 bl_0_78 br_0_78 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c78 bl_0_78 br_0_78 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c78 bl_0_78 br_0_78 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c78 bl_0_78 br_0_78 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c78 bl_0_78 br_0_78 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c78 bl_0_78 br_0_78 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c78 bl_0_78 br_0_78 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c78 bl_0_78 br_0_78 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c78 bl_0_78 br_0_78 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c78 bl_0_78 br_0_78 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c78 bl_0_78 br_0_78 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c78 bl_0_78 br_0_78 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c78 bl_0_78 br_0_78 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c78 bl_0_78 br_0_78 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c78 bl_0_78 br_0_78 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c78 bl_0_78 br_0_78 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c78 bl_0_78 br_0_78 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c78 bl_0_78 br_0_78 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c78 bl_0_78 br_0_78 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c78 bl_0_78 br_0_78 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c78 bl_0_78 br_0_78 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c78 bl_0_78 br_0_78 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c78 bl_0_78 br_0_78 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c78 bl_0_78 br_0_78 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c78 bl_0_78 br_0_78 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c78 bl_0_78 br_0_78 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c78 bl_0_78 br_0_78 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c78 bl_0_78 br_0_78 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c78 bl_0_78 br_0_78 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c78 bl_0_78 br_0_78 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c78 bl_0_78 br_0_78 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c78 bl_0_78 br_0_78 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c78 bl_0_78 br_0_78 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c78 bl_0_78 br_0_78 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c78 bl_0_78 br_0_78 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c78 bl_0_78 br_0_78 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c78 bl_0_78 br_0_78 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c78 bl_0_78 br_0_78 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c78 bl_0_78 br_0_78 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c78 bl_0_78 br_0_78 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c78 bl_0_78 br_0_78 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c78 bl_0_78 br_0_78 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c78 bl_0_78 br_0_78 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c78 bl_0_78 br_0_78 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c78 bl_0_78 br_0_78 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c78 bl_0_78 br_0_78 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c78 bl_0_78 br_0_78 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c78 bl_0_78 br_0_78 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c78 bl_0_78 br_0_78 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c78 bl_0_78 br_0_78 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c78 bl_0_78 br_0_78 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c78 bl_0_78 br_0_78 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c78 bl_0_78 br_0_78 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c78 bl_0_78 br_0_78 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c78 bl_0_78 br_0_78 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c78 bl_0_78 br_0_78 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c78 bl_0_78 br_0_78 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c78 bl_0_78 br_0_78 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c78 bl_0_78 br_0_78 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c78 bl_0_78 br_0_78 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c78 bl_0_78 br_0_78 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c79 bl_0_79 br_0_79 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c79 bl_0_79 br_0_79 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c79 bl_0_79 br_0_79 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c79 bl_0_79 br_0_79 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c79 bl_0_79 br_0_79 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c79 bl_0_79 br_0_79 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c79 bl_0_79 br_0_79 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c79 bl_0_79 br_0_79 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c79 bl_0_79 br_0_79 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c79 bl_0_79 br_0_79 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c79 bl_0_79 br_0_79 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c79 bl_0_79 br_0_79 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c79 bl_0_79 br_0_79 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c79 bl_0_79 br_0_79 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c79 bl_0_79 br_0_79 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c79 bl_0_79 br_0_79 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c79 bl_0_79 br_0_79 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c79 bl_0_79 br_0_79 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c79 bl_0_79 br_0_79 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c79 bl_0_79 br_0_79 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c79 bl_0_79 br_0_79 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c79 bl_0_79 br_0_79 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c79 bl_0_79 br_0_79 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c79 bl_0_79 br_0_79 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c79 bl_0_79 br_0_79 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c79 bl_0_79 br_0_79 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c79 bl_0_79 br_0_79 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c79 bl_0_79 br_0_79 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c79 bl_0_79 br_0_79 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c79 bl_0_79 br_0_79 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c79 bl_0_79 br_0_79 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c79 bl_0_79 br_0_79 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c79 bl_0_79 br_0_79 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c79 bl_0_79 br_0_79 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c79 bl_0_79 br_0_79 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c79 bl_0_79 br_0_79 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c79 bl_0_79 br_0_79 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c79 bl_0_79 br_0_79 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c79 bl_0_79 br_0_79 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c79 bl_0_79 br_0_79 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c79 bl_0_79 br_0_79 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c79 bl_0_79 br_0_79 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c79 bl_0_79 br_0_79 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c79 bl_0_79 br_0_79 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c79 bl_0_79 br_0_79 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c79 bl_0_79 br_0_79 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c79 bl_0_79 br_0_79 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c79 bl_0_79 br_0_79 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c79 bl_0_79 br_0_79 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c79 bl_0_79 br_0_79 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c79 bl_0_79 br_0_79 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c79 bl_0_79 br_0_79 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c79 bl_0_79 br_0_79 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c79 bl_0_79 br_0_79 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c79 bl_0_79 br_0_79 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c79 bl_0_79 br_0_79 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c79 bl_0_79 br_0_79 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c79 bl_0_79 br_0_79 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c79 bl_0_79 br_0_79 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c79 bl_0_79 br_0_79 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c79 bl_0_79 br_0_79 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c79 bl_0_79 br_0_79 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c79 bl_0_79 br_0_79 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c79 bl_0_79 br_0_79 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c80 bl_0_80 br_0_80 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c80 bl_0_80 br_0_80 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c80 bl_0_80 br_0_80 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c80 bl_0_80 br_0_80 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c80 bl_0_80 br_0_80 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c80 bl_0_80 br_0_80 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c80 bl_0_80 br_0_80 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c80 bl_0_80 br_0_80 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c80 bl_0_80 br_0_80 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c80 bl_0_80 br_0_80 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c80 bl_0_80 br_0_80 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c80 bl_0_80 br_0_80 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c80 bl_0_80 br_0_80 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c80 bl_0_80 br_0_80 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c80 bl_0_80 br_0_80 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c80 bl_0_80 br_0_80 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c80 bl_0_80 br_0_80 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c80 bl_0_80 br_0_80 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c80 bl_0_80 br_0_80 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c80 bl_0_80 br_0_80 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c80 bl_0_80 br_0_80 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c80 bl_0_80 br_0_80 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c80 bl_0_80 br_0_80 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c80 bl_0_80 br_0_80 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c80 bl_0_80 br_0_80 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c80 bl_0_80 br_0_80 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c80 bl_0_80 br_0_80 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c80 bl_0_80 br_0_80 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c80 bl_0_80 br_0_80 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c80 bl_0_80 br_0_80 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c80 bl_0_80 br_0_80 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c80 bl_0_80 br_0_80 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c80 bl_0_80 br_0_80 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c80 bl_0_80 br_0_80 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c80 bl_0_80 br_0_80 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c80 bl_0_80 br_0_80 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c80 bl_0_80 br_0_80 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c80 bl_0_80 br_0_80 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c80 bl_0_80 br_0_80 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c80 bl_0_80 br_0_80 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c80 bl_0_80 br_0_80 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c80 bl_0_80 br_0_80 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c80 bl_0_80 br_0_80 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c80 bl_0_80 br_0_80 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c80 bl_0_80 br_0_80 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c80 bl_0_80 br_0_80 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c80 bl_0_80 br_0_80 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c80 bl_0_80 br_0_80 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c80 bl_0_80 br_0_80 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c80 bl_0_80 br_0_80 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c80 bl_0_80 br_0_80 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c80 bl_0_80 br_0_80 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c80 bl_0_80 br_0_80 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c80 bl_0_80 br_0_80 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c80 bl_0_80 br_0_80 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c80 bl_0_80 br_0_80 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c80 bl_0_80 br_0_80 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c80 bl_0_80 br_0_80 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c80 bl_0_80 br_0_80 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c80 bl_0_80 br_0_80 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c80 bl_0_80 br_0_80 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c80 bl_0_80 br_0_80 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c80 bl_0_80 br_0_80 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c80 bl_0_80 br_0_80 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c81 bl_0_81 br_0_81 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c81 bl_0_81 br_0_81 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c81 bl_0_81 br_0_81 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c81 bl_0_81 br_0_81 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c81 bl_0_81 br_0_81 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c81 bl_0_81 br_0_81 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c81 bl_0_81 br_0_81 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c81 bl_0_81 br_0_81 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c81 bl_0_81 br_0_81 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c81 bl_0_81 br_0_81 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c81 bl_0_81 br_0_81 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c81 bl_0_81 br_0_81 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c81 bl_0_81 br_0_81 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c81 bl_0_81 br_0_81 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c81 bl_0_81 br_0_81 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c81 bl_0_81 br_0_81 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c81 bl_0_81 br_0_81 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c81 bl_0_81 br_0_81 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c81 bl_0_81 br_0_81 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c81 bl_0_81 br_0_81 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c81 bl_0_81 br_0_81 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c81 bl_0_81 br_0_81 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c81 bl_0_81 br_0_81 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c81 bl_0_81 br_0_81 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c81 bl_0_81 br_0_81 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c81 bl_0_81 br_0_81 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c81 bl_0_81 br_0_81 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c81 bl_0_81 br_0_81 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c81 bl_0_81 br_0_81 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c81 bl_0_81 br_0_81 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c81 bl_0_81 br_0_81 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c81 bl_0_81 br_0_81 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c81 bl_0_81 br_0_81 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c81 bl_0_81 br_0_81 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c81 bl_0_81 br_0_81 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c81 bl_0_81 br_0_81 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c81 bl_0_81 br_0_81 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c81 bl_0_81 br_0_81 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c81 bl_0_81 br_0_81 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c81 bl_0_81 br_0_81 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c81 bl_0_81 br_0_81 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c81 bl_0_81 br_0_81 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c81 bl_0_81 br_0_81 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c81 bl_0_81 br_0_81 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c81 bl_0_81 br_0_81 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c81 bl_0_81 br_0_81 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c81 bl_0_81 br_0_81 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c81 bl_0_81 br_0_81 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c81 bl_0_81 br_0_81 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c81 bl_0_81 br_0_81 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c81 bl_0_81 br_0_81 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c81 bl_0_81 br_0_81 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c81 bl_0_81 br_0_81 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c81 bl_0_81 br_0_81 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c81 bl_0_81 br_0_81 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c81 bl_0_81 br_0_81 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c81 bl_0_81 br_0_81 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c81 bl_0_81 br_0_81 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c81 bl_0_81 br_0_81 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c81 bl_0_81 br_0_81 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c81 bl_0_81 br_0_81 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c81 bl_0_81 br_0_81 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c81 bl_0_81 br_0_81 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c81 bl_0_81 br_0_81 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c82 bl_0_82 br_0_82 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c82 bl_0_82 br_0_82 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c82 bl_0_82 br_0_82 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c82 bl_0_82 br_0_82 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c82 bl_0_82 br_0_82 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c82 bl_0_82 br_0_82 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c82 bl_0_82 br_0_82 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c82 bl_0_82 br_0_82 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c82 bl_0_82 br_0_82 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c82 bl_0_82 br_0_82 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c82 bl_0_82 br_0_82 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c82 bl_0_82 br_0_82 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c82 bl_0_82 br_0_82 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c82 bl_0_82 br_0_82 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c82 bl_0_82 br_0_82 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c82 bl_0_82 br_0_82 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c82 bl_0_82 br_0_82 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c82 bl_0_82 br_0_82 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c82 bl_0_82 br_0_82 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c82 bl_0_82 br_0_82 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c82 bl_0_82 br_0_82 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c82 bl_0_82 br_0_82 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c82 bl_0_82 br_0_82 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c82 bl_0_82 br_0_82 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c82 bl_0_82 br_0_82 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c82 bl_0_82 br_0_82 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c82 bl_0_82 br_0_82 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c82 bl_0_82 br_0_82 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c82 bl_0_82 br_0_82 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c82 bl_0_82 br_0_82 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c82 bl_0_82 br_0_82 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c82 bl_0_82 br_0_82 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c82 bl_0_82 br_0_82 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c82 bl_0_82 br_0_82 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c82 bl_0_82 br_0_82 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c82 bl_0_82 br_0_82 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c82 bl_0_82 br_0_82 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c82 bl_0_82 br_0_82 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c82 bl_0_82 br_0_82 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c82 bl_0_82 br_0_82 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c82 bl_0_82 br_0_82 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c82 bl_0_82 br_0_82 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c82 bl_0_82 br_0_82 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c82 bl_0_82 br_0_82 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c82 bl_0_82 br_0_82 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c82 bl_0_82 br_0_82 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c82 bl_0_82 br_0_82 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c82 bl_0_82 br_0_82 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c82 bl_0_82 br_0_82 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c82 bl_0_82 br_0_82 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c82 bl_0_82 br_0_82 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c82 bl_0_82 br_0_82 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c82 bl_0_82 br_0_82 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c82 bl_0_82 br_0_82 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c82 bl_0_82 br_0_82 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c82 bl_0_82 br_0_82 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c82 bl_0_82 br_0_82 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c82 bl_0_82 br_0_82 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c82 bl_0_82 br_0_82 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c82 bl_0_82 br_0_82 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c82 bl_0_82 br_0_82 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c82 bl_0_82 br_0_82 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c82 bl_0_82 br_0_82 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c82 bl_0_82 br_0_82 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c83 bl_0_83 br_0_83 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c83 bl_0_83 br_0_83 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c83 bl_0_83 br_0_83 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c83 bl_0_83 br_0_83 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c83 bl_0_83 br_0_83 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c83 bl_0_83 br_0_83 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c83 bl_0_83 br_0_83 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c83 bl_0_83 br_0_83 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c83 bl_0_83 br_0_83 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c83 bl_0_83 br_0_83 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c83 bl_0_83 br_0_83 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c83 bl_0_83 br_0_83 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c83 bl_0_83 br_0_83 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c83 bl_0_83 br_0_83 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c83 bl_0_83 br_0_83 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c83 bl_0_83 br_0_83 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c83 bl_0_83 br_0_83 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c83 bl_0_83 br_0_83 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c83 bl_0_83 br_0_83 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c83 bl_0_83 br_0_83 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c83 bl_0_83 br_0_83 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c83 bl_0_83 br_0_83 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c83 bl_0_83 br_0_83 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c83 bl_0_83 br_0_83 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c83 bl_0_83 br_0_83 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c83 bl_0_83 br_0_83 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c83 bl_0_83 br_0_83 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c83 bl_0_83 br_0_83 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c83 bl_0_83 br_0_83 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c83 bl_0_83 br_0_83 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c83 bl_0_83 br_0_83 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c83 bl_0_83 br_0_83 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c83 bl_0_83 br_0_83 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c83 bl_0_83 br_0_83 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c83 bl_0_83 br_0_83 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c83 bl_0_83 br_0_83 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c83 bl_0_83 br_0_83 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c83 bl_0_83 br_0_83 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c83 bl_0_83 br_0_83 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c83 bl_0_83 br_0_83 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c83 bl_0_83 br_0_83 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c83 bl_0_83 br_0_83 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c83 bl_0_83 br_0_83 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c83 bl_0_83 br_0_83 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c83 bl_0_83 br_0_83 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c83 bl_0_83 br_0_83 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c83 bl_0_83 br_0_83 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c83 bl_0_83 br_0_83 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c83 bl_0_83 br_0_83 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c83 bl_0_83 br_0_83 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c83 bl_0_83 br_0_83 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c83 bl_0_83 br_0_83 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c83 bl_0_83 br_0_83 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c83 bl_0_83 br_0_83 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c83 bl_0_83 br_0_83 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c83 bl_0_83 br_0_83 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c83 bl_0_83 br_0_83 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c83 bl_0_83 br_0_83 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c83 bl_0_83 br_0_83 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c83 bl_0_83 br_0_83 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c83 bl_0_83 br_0_83 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c83 bl_0_83 br_0_83 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c83 bl_0_83 br_0_83 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c83 bl_0_83 br_0_83 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c84 bl_0_84 br_0_84 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c84 bl_0_84 br_0_84 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c84 bl_0_84 br_0_84 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c84 bl_0_84 br_0_84 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c84 bl_0_84 br_0_84 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c84 bl_0_84 br_0_84 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c84 bl_0_84 br_0_84 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c84 bl_0_84 br_0_84 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c84 bl_0_84 br_0_84 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c84 bl_0_84 br_0_84 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c84 bl_0_84 br_0_84 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c84 bl_0_84 br_0_84 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c84 bl_0_84 br_0_84 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c84 bl_0_84 br_0_84 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c84 bl_0_84 br_0_84 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c84 bl_0_84 br_0_84 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c84 bl_0_84 br_0_84 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c84 bl_0_84 br_0_84 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c84 bl_0_84 br_0_84 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c84 bl_0_84 br_0_84 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c84 bl_0_84 br_0_84 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c84 bl_0_84 br_0_84 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c84 bl_0_84 br_0_84 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c84 bl_0_84 br_0_84 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c84 bl_0_84 br_0_84 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c84 bl_0_84 br_0_84 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c84 bl_0_84 br_0_84 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c84 bl_0_84 br_0_84 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c84 bl_0_84 br_0_84 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c84 bl_0_84 br_0_84 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c84 bl_0_84 br_0_84 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c84 bl_0_84 br_0_84 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c84 bl_0_84 br_0_84 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c84 bl_0_84 br_0_84 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c84 bl_0_84 br_0_84 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c84 bl_0_84 br_0_84 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c84 bl_0_84 br_0_84 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c84 bl_0_84 br_0_84 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c84 bl_0_84 br_0_84 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c84 bl_0_84 br_0_84 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c84 bl_0_84 br_0_84 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c84 bl_0_84 br_0_84 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c84 bl_0_84 br_0_84 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c84 bl_0_84 br_0_84 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c84 bl_0_84 br_0_84 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c84 bl_0_84 br_0_84 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c84 bl_0_84 br_0_84 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c84 bl_0_84 br_0_84 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c84 bl_0_84 br_0_84 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c84 bl_0_84 br_0_84 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c84 bl_0_84 br_0_84 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c84 bl_0_84 br_0_84 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c84 bl_0_84 br_0_84 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c84 bl_0_84 br_0_84 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c84 bl_0_84 br_0_84 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c84 bl_0_84 br_0_84 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c84 bl_0_84 br_0_84 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c84 bl_0_84 br_0_84 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c84 bl_0_84 br_0_84 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c84 bl_0_84 br_0_84 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c84 bl_0_84 br_0_84 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c84 bl_0_84 br_0_84 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c84 bl_0_84 br_0_84 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c84 bl_0_84 br_0_84 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c85 bl_0_85 br_0_85 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c85 bl_0_85 br_0_85 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c85 bl_0_85 br_0_85 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c85 bl_0_85 br_0_85 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c85 bl_0_85 br_0_85 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c85 bl_0_85 br_0_85 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c85 bl_0_85 br_0_85 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c85 bl_0_85 br_0_85 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c85 bl_0_85 br_0_85 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c85 bl_0_85 br_0_85 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c85 bl_0_85 br_0_85 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c85 bl_0_85 br_0_85 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c85 bl_0_85 br_0_85 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c85 bl_0_85 br_0_85 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c85 bl_0_85 br_0_85 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c85 bl_0_85 br_0_85 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c85 bl_0_85 br_0_85 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c85 bl_0_85 br_0_85 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c85 bl_0_85 br_0_85 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c85 bl_0_85 br_0_85 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c85 bl_0_85 br_0_85 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c85 bl_0_85 br_0_85 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c85 bl_0_85 br_0_85 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c85 bl_0_85 br_0_85 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c85 bl_0_85 br_0_85 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c85 bl_0_85 br_0_85 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c85 bl_0_85 br_0_85 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c85 bl_0_85 br_0_85 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c85 bl_0_85 br_0_85 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c85 bl_0_85 br_0_85 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c85 bl_0_85 br_0_85 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c85 bl_0_85 br_0_85 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c85 bl_0_85 br_0_85 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c85 bl_0_85 br_0_85 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c85 bl_0_85 br_0_85 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c85 bl_0_85 br_0_85 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c85 bl_0_85 br_0_85 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c85 bl_0_85 br_0_85 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c85 bl_0_85 br_0_85 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c85 bl_0_85 br_0_85 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c85 bl_0_85 br_0_85 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c85 bl_0_85 br_0_85 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c85 bl_0_85 br_0_85 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c85 bl_0_85 br_0_85 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c85 bl_0_85 br_0_85 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c85 bl_0_85 br_0_85 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c85 bl_0_85 br_0_85 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c85 bl_0_85 br_0_85 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c85 bl_0_85 br_0_85 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c85 bl_0_85 br_0_85 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c85 bl_0_85 br_0_85 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c85 bl_0_85 br_0_85 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c85 bl_0_85 br_0_85 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c85 bl_0_85 br_0_85 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c85 bl_0_85 br_0_85 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c85 bl_0_85 br_0_85 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c85 bl_0_85 br_0_85 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c85 bl_0_85 br_0_85 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c85 bl_0_85 br_0_85 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c85 bl_0_85 br_0_85 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c85 bl_0_85 br_0_85 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c85 bl_0_85 br_0_85 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c85 bl_0_85 br_0_85 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c85 bl_0_85 br_0_85 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c86 bl_0_86 br_0_86 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c86 bl_0_86 br_0_86 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c86 bl_0_86 br_0_86 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c86 bl_0_86 br_0_86 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c86 bl_0_86 br_0_86 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c86 bl_0_86 br_0_86 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c86 bl_0_86 br_0_86 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c86 bl_0_86 br_0_86 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c86 bl_0_86 br_0_86 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c86 bl_0_86 br_0_86 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c86 bl_0_86 br_0_86 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c86 bl_0_86 br_0_86 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c86 bl_0_86 br_0_86 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c86 bl_0_86 br_0_86 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c86 bl_0_86 br_0_86 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c86 bl_0_86 br_0_86 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c86 bl_0_86 br_0_86 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c86 bl_0_86 br_0_86 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c86 bl_0_86 br_0_86 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c86 bl_0_86 br_0_86 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c86 bl_0_86 br_0_86 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c86 bl_0_86 br_0_86 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c86 bl_0_86 br_0_86 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c86 bl_0_86 br_0_86 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c86 bl_0_86 br_0_86 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c86 bl_0_86 br_0_86 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c86 bl_0_86 br_0_86 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c86 bl_0_86 br_0_86 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c86 bl_0_86 br_0_86 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c86 bl_0_86 br_0_86 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c86 bl_0_86 br_0_86 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c86 bl_0_86 br_0_86 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c86 bl_0_86 br_0_86 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c86 bl_0_86 br_0_86 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c86 bl_0_86 br_0_86 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c86 bl_0_86 br_0_86 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c86 bl_0_86 br_0_86 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c86 bl_0_86 br_0_86 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c86 bl_0_86 br_0_86 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c86 bl_0_86 br_0_86 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c86 bl_0_86 br_0_86 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c86 bl_0_86 br_0_86 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c86 bl_0_86 br_0_86 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c86 bl_0_86 br_0_86 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c86 bl_0_86 br_0_86 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c86 bl_0_86 br_0_86 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c86 bl_0_86 br_0_86 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c86 bl_0_86 br_0_86 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c86 bl_0_86 br_0_86 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c86 bl_0_86 br_0_86 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c86 bl_0_86 br_0_86 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c86 bl_0_86 br_0_86 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c86 bl_0_86 br_0_86 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c86 bl_0_86 br_0_86 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c86 bl_0_86 br_0_86 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c86 bl_0_86 br_0_86 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c86 bl_0_86 br_0_86 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c86 bl_0_86 br_0_86 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c86 bl_0_86 br_0_86 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c86 bl_0_86 br_0_86 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c86 bl_0_86 br_0_86 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c86 bl_0_86 br_0_86 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c86 bl_0_86 br_0_86 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c86 bl_0_86 br_0_86 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c87 bl_0_87 br_0_87 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c87 bl_0_87 br_0_87 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c87 bl_0_87 br_0_87 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c87 bl_0_87 br_0_87 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c87 bl_0_87 br_0_87 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c87 bl_0_87 br_0_87 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c87 bl_0_87 br_0_87 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c87 bl_0_87 br_0_87 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c87 bl_0_87 br_0_87 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c87 bl_0_87 br_0_87 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c87 bl_0_87 br_0_87 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c87 bl_0_87 br_0_87 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c87 bl_0_87 br_0_87 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c87 bl_0_87 br_0_87 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c87 bl_0_87 br_0_87 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c87 bl_0_87 br_0_87 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c87 bl_0_87 br_0_87 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c87 bl_0_87 br_0_87 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c87 bl_0_87 br_0_87 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c87 bl_0_87 br_0_87 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c87 bl_0_87 br_0_87 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c87 bl_0_87 br_0_87 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c87 bl_0_87 br_0_87 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c87 bl_0_87 br_0_87 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c87 bl_0_87 br_0_87 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c87 bl_0_87 br_0_87 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c87 bl_0_87 br_0_87 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c87 bl_0_87 br_0_87 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c87 bl_0_87 br_0_87 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c87 bl_0_87 br_0_87 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c87 bl_0_87 br_0_87 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c87 bl_0_87 br_0_87 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c87 bl_0_87 br_0_87 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c87 bl_0_87 br_0_87 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c87 bl_0_87 br_0_87 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c87 bl_0_87 br_0_87 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c87 bl_0_87 br_0_87 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c87 bl_0_87 br_0_87 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c87 bl_0_87 br_0_87 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c87 bl_0_87 br_0_87 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c87 bl_0_87 br_0_87 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c87 bl_0_87 br_0_87 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c87 bl_0_87 br_0_87 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c87 bl_0_87 br_0_87 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c87 bl_0_87 br_0_87 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c87 bl_0_87 br_0_87 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c87 bl_0_87 br_0_87 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c87 bl_0_87 br_0_87 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c87 bl_0_87 br_0_87 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c87 bl_0_87 br_0_87 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c87 bl_0_87 br_0_87 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c87 bl_0_87 br_0_87 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c87 bl_0_87 br_0_87 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c87 bl_0_87 br_0_87 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c87 bl_0_87 br_0_87 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c87 bl_0_87 br_0_87 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c87 bl_0_87 br_0_87 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c87 bl_0_87 br_0_87 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c87 bl_0_87 br_0_87 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c87 bl_0_87 br_0_87 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c87 bl_0_87 br_0_87 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c87 bl_0_87 br_0_87 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c87 bl_0_87 br_0_87 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c87 bl_0_87 br_0_87 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c88 bl_0_88 br_0_88 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c88 bl_0_88 br_0_88 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c88 bl_0_88 br_0_88 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c88 bl_0_88 br_0_88 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c88 bl_0_88 br_0_88 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c88 bl_0_88 br_0_88 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c88 bl_0_88 br_0_88 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c88 bl_0_88 br_0_88 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c88 bl_0_88 br_0_88 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c88 bl_0_88 br_0_88 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c88 bl_0_88 br_0_88 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c88 bl_0_88 br_0_88 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c88 bl_0_88 br_0_88 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c88 bl_0_88 br_0_88 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c88 bl_0_88 br_0_88 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c88 bl_0_88 br_0_88 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c88 bl_0_88 br_0_88 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c88 bl_0_88 br_0_88 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c88 bl_0_88 br_0_88 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c88 bl_0_88 br_0_88 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c88 bl_0_88 br_0_88 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c88 bl_0_88 br_0_88 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c88 bl_0_88 br_0_88 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c88 bl_0_88 br_0_88 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c88 bl_0_88 br_0_88 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c88 bl_0_88 br_0_88 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c88 bl_0_88 br_0_88 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c88 bl_0_88 br_0_88 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c88 bl_0_88 br_0_88 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c88 bl_0_88 br_0_88 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c88 bl_0_88 br_0_88 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c88 bl_0_88 br_0_88 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c88 bl_0_88 br_0_88 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c88 bl_0_88 br_0_88 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c88 bl_0_88 br_0_88 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c88 bl_0_88 br_0_88 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c88 bl_0_88 br_0_88 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c88 bl_0_88 br_0_88 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c88 bl_0_88 br_0_88 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c88 bl_0_88 br_0_88 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c88 bl_0_88 br_0_88 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c88 bl_0_88 br_0_88 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c88 bl_0_88 br_0_88 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c88 bl_0_88 br_0_88 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c88 bl_0_88 br_0_88 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c88 bl_0_88 br_0_88 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c88 bl_0_88 br_0_88 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c88 bl_0_88 br_0_88 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c88 bl_0_88 br_0_88 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c88 bl_0_88 br_0_88 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c88 bl_0_88 br_0_88 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c88 bl_0_88 br_0_88 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c88 bl_0_88 br_0_88 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c88 bl_0_88 br_0_88 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c88 bl_0_88 br_0_88 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c88 bl_0_88 br_0_88 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c88 bl_0_88 br_0_88 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c88 bl_0_88 br_0_88 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c88 bl_0_88 br_0_88 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c88 bl_0_88 br_0_88 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c88 bl_0_88 br_0_88 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c88 bl_0_88 br_0_88 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c88 bl_0_88 br_0_88 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c88 bl_0_88 br_0_88 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c89 bl_0_89 br_0_89 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c89 bl_0_89 br_0_89 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c89 bl_0_89 br_0_89 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c89 bl_0_89 br_0_89 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c89 bl_0_89 br_0_89 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c89 bl_0_89 br_0_89 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c89 bl_0_89 br_0_89 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c89 bl_0_89 br_0_89 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c89 bl_0_89 br_0_89 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c89 bl_0_89 br_0_89 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c89 bl_0_89 br_0_89 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c89 bl_0_89 br_0_89 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c89 bl_0_89 br_0_89 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c89 bl_0_89 br_0_89 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c89 bl_0_89 br_0_89 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c89 bl_0_89 br_0_89 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c89 bl_0_89 br_0_89 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c89 bl_0_89 br_0_89 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c89 bl_0_89 br_0_89 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c89 bl_0_89 br_0_89 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c89 bl_0_89 br_0_89 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c89 bl_0_89 br_0_89 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c89 bl_0_89 br_0_89 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c89 bl_0_89 br_0_89 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c89 bl_0_89 br_0_89 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c89 bl_0_89 br_0_89 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c89 bl_0_89 br_0_89 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c89 bl_0_89 br_0_89 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c89 bl_0_89 br_0_89 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c89 bl_0_89 br_0_89 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c89 bl_0_89 br_0_89 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c89 bl_0_89 br_0_89 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c89 bl_0_89 br_0_89 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c89 bl_0_89 br_0_89 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c89 bl_0_89 br_0_89 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c89 bl_0_89 br_0_89 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c89 bl_0_89 br_0_89 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c89 bl_0_89 br_0_89 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c89 bl_0_89 br_0_89 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c89 bl_0_89 br_0_89 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c89 bl_0_89 br_0_89 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c89 bl_0_89 br_0_89 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c89 bl_0_89 br_0_89 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c89 bl_0_89 br_0_89 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c89 bl_0_89 br_0_89 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c89 bl_0_89 br_0_89 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c89 bl_0_89 br_0_89 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c89 bl_0_89 br_0_89 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c89 bl_0_89 br_0_89 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c89 bl_0_89 br_0_89 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c89 bl_0_89 br_0_89 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c89 bl_0_89 br_0_89 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c89 bl_0_89 br_0_89 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c89 bl_0_89 br_0_89 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c89 bl_0_89 br_0_89 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c89 bl_0_89 br_0_89 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c89 bl_0_89 br_0_89 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c89 bl_0_89 br_0_89 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c89 bl_0_89 br_0_89 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c89 bl_0_89 br_0_89 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c89 bl_0_89 br_0_89 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c89 bl_0_89 br_0_89 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c89 bl_0_89 br_0_89 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c89 bl_0_89 br_0_89 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c90 bl_0_90 br_0_90 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c90 bl_0_90 br_0_90 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c90 bl_0_90 br_0_90 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c90 bl_0_90 br_0_90 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c90 bl_0_90 br_0_90 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c90 bl_0_90 br_0_90 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c90 bl_0_90 br_0_90 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c90 bl_0_90 br_0_90 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c90 bl_0_90 br_0_90 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c90 bl_0_90 br_0_90 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c90 bl_0_90 br_0_90 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c90 bl_0_90 br_0_90 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c90 bl_0_90 br_0_90 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c90 bl_0_90 br_0_90 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c90 bl_0_90 br_0_90 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c90 bl_0_90 br_0_90 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c90 bl_0_90 br_0_90 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c90 bl_0_90 br_0_90 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c90 bl_0_90 br_0_90 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c90 bl_0_90 br_0_90 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c90 bl_0_90 br_0_90 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c90 bl_0_90 br_0_90 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c90 bl_0_90 br_0_90 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c90 bl_0_90 br_0_90 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c90 bl_0_90 br_0_90 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c90 bl_0_90 br_0_90 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c90 bl_0_90 br_0_90 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c90 bl_0_90 br_0_90 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c90 bl_0_90 br_0_90 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c90 bl_0_90 br_0_90 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c90 bl_0_90 br_0_90 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c90 bl_0_90 br_0_90 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c90 bl_0_90 br_0_90 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c90 bl_0_90 br_0_90 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c90 bl_0_90 br_0_90 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c90 bl_0_90 br_0_90 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c90 bl_0_90 br_0_90 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c90 bl_0_90 br_0_90 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c90 bl_0_90 br_0_90 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c90 bl_0_90 br_0_90 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c90 bl_0_90 br_0_90 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c90 bl_0_90 br_0_90 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c90 bl_0_90 br_0_90 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c90 bl_0_90 br_0_90 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c90 bl_0_90 br_0_90 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c90 bl_0_90 br_0_90 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c90 bl_0_90 br_0_90 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c90 bl_0_90 br_0_90 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c90 bl_0_90 br_0_90 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c90 bl_0_90 br_0_90 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c90 bl_0_90 br_0_90 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c90 bl_0_90 br_0_90 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c90 bl_0_90 br_0_90 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c90 bl_0_90 br_0_90 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c90 bl_0_90 br_0_90 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c90 bl_0_90 br_0_90 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c90 bl_0_90 br_0_90 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c90 bl_0_90 br_0_90 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c90 bl_0_90 br_0_90 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c90 bl_0_90 br_0_90 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c90 bl_0_90 br_0_90 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c90 bl_0_90 br_0_90 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c90 bl_0_90 br_0_90 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c90 bl_0_90 br_0_90 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c91 bl_0_91 br_0_91 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c91 bl_0_91 br_0_91 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c91 bl_0_91 br_0_91 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c91 bl_0_91 br_0_91 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c91 bl_0_91 br_0_91 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c91 bl_0_91 br_0_91 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c91 bl_0_91 br_0_91 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c91 bl_0_91 br_0_91 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c91 bl_0_91 br_0_91 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c91 bl_0_91 br_0_91 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c91 bl_0_91 br_0_91 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c91 bl_0_91 br_0_91 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c91 bl_0_91 br_0_91 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c91 bl_0_91 br_0_91 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c91 bl_0_91 br_0_91 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c91 bl_0_91 br_0_91 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c91 bl_0_91 br_0_91 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c91 bl_0_91 br_0_91 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c91 bl_0_91 br_0_91 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c91 bl_0_91 br_0_91 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c91 bl_0_91 br_0_91 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c91 bl_0_91 br_0_91 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c91 bl_0_91 br_0_91 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c91 bl_0_91 br_0_91 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c91 bl_0_91 br_0_91 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c91 bl_0_91 br_0_91 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c91 bl_0_91 br_0_91 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c91 bl_0_91 br_0_91 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c91 bl_0_91 br_0_91 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c91 bl_0_91 br_0_91 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c91 bl_0_91 br_0_91 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c91 bl_0_91 br_0_91 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c91 bl_0_91 br_0_91 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c91 bl_0_91 br_0_91 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c91 bl_0_91 br_0_91 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c91 bl_0_91 br_0_91 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c91 bl_0_91 br_0_91 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c91 bl_0_91 br_0_91 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c91 bl_0_91 br_0_91 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c91 bl_0_91 br_0_91 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c91 bl_0_91 br_0_91 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c91 bl_0_91 br_0_91 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c91 bl_0_91 br_0_91 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c91 bl_0_91 br_0_91 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c91 bl_0_91 br_0_91 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c91 bl_0_91 br_0_91 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c91 bl_0_91 br_0_91 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c91 bl_0_91 br_0_91 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c91 bl_0_91 br_0_91 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c91 bl_0_91 br_0_91 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c91 bl_0_91 br_0_91 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c91 bl_0_91 br_0_91 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c91 bl_0_91 br_0_91 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c91 bl_0_91 br_0_91 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c91 bl_0_91 br_0_91 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c91 bl_0_91 br_0_91 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c91 bl_0_91 br_0_91 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c91 bl_0_91 br_0_91 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c91 bl_0_91 br_0_91 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c91 bl_0_91 br_0_91 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c91 bl_0_91 br_0_91 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c91 bl_0_91 br_0_91 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c91 bl_0_91 br_0_91 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c91 bl_0_91 br_0_91 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c92 bl_0_92 br_0_92 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c92 bl_0_92 br_0_92 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c92 bl_0_92 br_0_92 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c92 bl_0_92 br_0_92 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c92 bl_0_92 br_0_92 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c92 bl_0_92 br_0_92 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c92 bl_0_92 br_0_92 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c92 bl_0_92 br_0_92 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c92 bl_0_92 br_0_92 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c92 bl_0_92 br_0_92 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c92 bl_0_92 br_0_92 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c92 bl_0_92 br_0_92 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c92 bl_0_92 br_0_92 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c92 bl_0_92 br_0_92 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c92 bl_0_92 br_0_92 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c92 bl_0_92 br_0_92 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c92 bl_0_92 br_0_92 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c92 bl_0_92 br_0_92 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c92 bl_0_92 br_0_92 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c92 bl_0_92 br_0_92 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c92 bl_0_92 br_0_92 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c92 bl_0_92 br_0_92 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c92 bl_0_92 br_0_92 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c92 bl_0_92 br_0_92 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c92 bl_0_92 br_0_92 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c92 bl_0_92 br_0_92 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c92 bl_0_92 br_0_92 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c92 bl_0_92 br_0_92 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c92 bl_0_92 br_0_92 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c92 bl_0_92 br_0_92 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c92 bl_0_92 br_0_92 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c92 bl_0_92 br_0_92 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c92 bl_0_92 br_0_92 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c92 bl_0_92 br_0_92 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c92 bl_0_92 br_0_92 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c92 bl_0_92 br_0_92 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c92 bl_0_92 br_0_92 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c92 bl_0_92 br_0_92 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c92 bl_0_92 br_0_92 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c92 bl_0_92 br_0_92 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c92 bl_0_92 br_0_92 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c92 bl_0_92 br_0_92 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c92 bl_0_92 br_0_92 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c92 bl_0_92 br_0_92 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c92 bl_0_92 br_0_92 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c92 bl_0_92 br_0_92 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c92 bl_0_92 br_0_92 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c92 bl_0_92 br_0_92 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c92 bl_0_92 br_0_92 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c92 bl_0_92 br_0_92 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c92 bl_0_92 br_0_92 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c92 bl_0_92 br_0_92 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c92 bl_0_92 br_0_92 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c92 bl_0_92 br_0_92 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c92 bl_0_92 br_0_92 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c92 bl_0_92 br_0_92 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c92 bl_0_92 br_0_92 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c92 bl_0_92 br_0_92 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c92 bl_0_92 br_0_92 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c92 bl_0_92 br_0_92 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c92 bl_0_92 br_0_92 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c92 bl_0_92 br_0_92 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c92 bl_0_92 br_0_92 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c92 bl_0_92 br_0_92 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c93 bl_0_93 br_0_93 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c93 bl_0_93 br_0_93 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c93 bl_0_93 br_0_93 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c93 bl_0_93 br_0_93 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c93 bl_0_93 br_0_93 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c93 bl_0_93 br_0_93 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c93 bl_0_93 br_0_93 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c93 bl_0_93 br_0_93 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c93 bl_0_93 br_0_93 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c93 bl_0_93 br_0_93 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c93 bl_0_93 br_0_93 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c93 bl_0_93 br_0_93 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c93 bl_0_93 br_0_93 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c93 bl_0_93 br_0_93 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c93 bl_0_93 br_0_93 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c93 bl_0_93 br_0_93 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c93 bl_0_93 br_0_93 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c93 bl_0_93 br_0_93 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c93 bl_0_93 br_0_93 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c93 bl_0_93 br_0_93 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c93 bl_0_93 br_0_93 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c93 bl_0_93 br_0_93 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c93 bl_0_93 br_0_93 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c93 bl_0_93 br_0_93 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c93 bl_0_93 br_0_93 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c93 bl_0_93 br_0_93 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c93 bl_0_93 br_0_93 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c93 bl_0_93 br_0_93 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c93 bl_0_93 br_0_93 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c93 bl_0_93 br_0_93 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c93 bl_0_93 br_0_93 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c93 bl_0_93 br_0_93 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c93 bl_0_93 br_0_93 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c93 bl_0_93 br_0_93 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c93 bl_0_93 br_0_93 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c93 bl_0_93 br_0_93 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c93 bl_0_93 br_0_93 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c93 bl_0_93 br_0_93 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c93 bl_0_93 br_0_93 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c93 bl_0_93 br_0_93 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c93 bl_0_93 br_0_93 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c93 bl_0_93 br_0_93 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c93 bl_0_93 br_0_93 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c93 bl_0_93 br_0_93 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c93 bl_0_93 br_0_93 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c93 bl_0_93 br_0_93 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c93 bl_0_93 br_0_93 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c93 bl_0_93 br_0_93 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c93 bl_0_93 br_0_93 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c93 bl_0_93 br_0_93 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c93 bl_0_93 br_0_93 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c93 bl_0_93 br_0_93 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c93 bl_0_93 br_0_93 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c93 bl_0_93 br_0_93 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c93 bl_0_93 br_0_93 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c93 bl_0_93 br_0_93 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c93 bl_0_93 br_0_93 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c93 bl_0_93 br_0_93 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c93 bl_0_93 br_0_93 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c93 bl_0_93 br_0_93 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c93 bl_0_93 br_0_93 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c93 bl_0_93 br_0_93 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c93 bl_0_93 br_0_93 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c93 bl_0_93 br_0_93 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c94 bl_0_94 br_0_94 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c94 bl_0_94 br_0_94 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c94 bl_0_94 br_0_94 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c94 bl_0_94 br_0_94 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c94 bl_0_94 br_0_94 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c94 bl_0_94 br_0_94 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c94 bl_0_94 br_0_94 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c94 bl_0_94 br_0_94 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c94 bl_0_94 br_0_94 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c94 bl_0_94 br_0_94 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c94 bl_0_94 br_0_94 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c94 bl_0_94 br_0_94 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c94 bl_0_94 br_0_94 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c94 bl_0_94 br_0_94 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c94 bl_0_94 br_0_94 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c94 bl_0_94 br_0_94 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c94 bl_0_94 br_0_94 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c94 bl_0_94 br_0_94 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c94 bl_0_94 br_0_94 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c94 bl_0_94 br_0_94 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c94 bl_0_94 br_0_94 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c94 bl_0_94 br_0_94 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c94 bl_0_94 br_0_94 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c94 bl_0_94 br_0_94 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c94 bl_0_94 br_0_94 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c94 bl_0_94 br_0_94 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c94 bl_0_94 br_0_94 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c94 bl_0_94 br_0_94 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c94 bl_0_94 br_0_94 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c94 bl_0_94 br_0_94 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c94 bl_0_94 br_0_94 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c94 bl_0_94 br_0_94 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c94 bl_0_94 br_0_94 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c94 bl_0_94 br_0_94 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c94 bl_0_94 br_0_94 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c94 bl_0_94 br_0_94 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c94 bl_0_94 br_0_94 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c94 bl_0_94 br_0_94 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c94 bl_0_94 br_0_94 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c94 bl_0_94 br_0_94 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c94 bl_0_94 br_0_94 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c94 bl_0_94 br_0_94 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c94 bl_0_94 br_0_94 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c94 bl_0_94 br_0_94 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c94 bl_0_94 br_0_94 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c94 bl_0_94 br_0_94 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c94 bl_0_94 br_0_94 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c94 bl_0_94 br_0_94 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c94 bl_0_94 br_0_94 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c94 bl_0_94 br_0_94 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c94 bl_0_94 br_0_94 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c94 bl_0_94 br_0_94 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c94 bl_0_94 br_0_94 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c94 bl_0_94 br_0_94 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c94 bl_0_94 br_0_94 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c94 bl_0_94 br_0_94 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c94 bl_0_94 br_0_94 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c94 bl_0_94 br_0_94 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c94 bl_0_94 br_0_94 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c94 bl_0_94 br_0_94 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c94 bl_0_94 br_0_94 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c94 bl_0_94 br_0_94 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c94 bl_0_94 br_0_94 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c94 bl_0_94 br_0_94 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c95 bl_0_95 br_0_95 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c95 bl_0_95 br_0_95 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c95 bl_0_95 br_0_95 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c95 bl_0_95 br_0_95 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c95 bl_0_95 br_0_95 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c95 bl_0_95 br_0_95 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c95 bl_0_95 br_0_95 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c95 bl_0_95 br_0_95 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c95 bl_0_95 br_0_95 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c95 bl_0_95 br_0_95 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c95 bl_0_95 br_0_95 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c95 bl_0_95 br_0_95 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c95 bl_0_95 br_0_95 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c95 bl_0_95 br_0_95 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c95 bl_0_95 br_0_95 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c95 bl_0_95 br_0_95 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c95 bl_0_95 br_0_95 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c95 bl_0_95 br_0_95 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c95 bl_0_95 br_0_95 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c95 bl_0_95 br_0_95 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c95 bl_0_95 br_0_95 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c95 bl_0_95 br_0_95 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c95 bl_0_95 br_0_95 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c95 bl_0_95 br_0_95 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c95 bl_0_95 br_0_95 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c95 bl_0_95 br_0_95 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c95 bl_0_95 br_0_95 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c95 bl_0_95 br_0_95 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c95 bl_0_95 br_0_95 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c95 bl_0_95 br_0_95 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c95 bl_0_95 br_0_95 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c95 bl_0_95 br_0_95 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c95 bl_0_95 br_0_95 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c95 bl_0_95 br_0_95 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c95 bl_0_95 br_0_95 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c95 bl_0_95 br_0_95 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c95 bl_0_95 br_0_95 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c95 bl_0_95 br_0_95 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c95 bl_0_95 br_0_95 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c95 bl_0_95 br_0_95 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c95 bl_0_95 br_0_95 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c95 bl_0_95 br_0_95 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c95 bl_0_95 br_0_95 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c95 bl_0_95 br_0_95 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c95 bl_0_95 br_0_95 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c95 bl_0_95 br_0_95 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c95 bl_0_95 br_0_95 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c95 bl_0_95 br_0_95 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c95 bl_0_95 br_0_95 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c95 bl_0_95 br_0_95 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c95 bl_0_95 br_0_95 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c95 bl_0_95 br_0_95 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c95 bl_0_95 br_0_95 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c95 bl_0_95 br_0_95 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c95 bl_0_95 br_0_95 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c95 bl_0_95 br_0_95 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c95 bl_0_95 br_0_95 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c95 bl_0_95 br_0_95 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c95 bl_0_95 br_0_95 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c95 bl_0_95 br_0_95 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c95 bl_0_95 br_0_95 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c95 bl_0_95 br_0_95 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c95 bl_0_95 br_0_95 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c95 bl_0_95 br_0_95 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c96 bl_0_96 br_0_96 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c96 bl_0_96 br_0_96 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c96 bl_0_96 br_0_96 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c96 bl_0_96 br_0_96 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c96 bl_0_96 br_0_96 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c96 bl_0_96 br_0_96 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c96 bl_0_96 br_0_96 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c96 bl_0_96 br_0_96 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c96 bl_0_96 br_0_96 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c96 bl_0_96 br_0_96 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c96 bl_0_96 br_0_96 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c96 bl_0_96 br_0_96 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c96 bl_0_96 br_0_96 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c96 bl_0_96 br_0_96 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c96 bl_0_96 br_0_96 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c96 bl_0_96 br_0_96 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c96 bl_0_96 br_0_96 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c96 bl_0_96 br_0_96 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c96 bl_0_96 br_0_96 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c96 bl_0_96 br_0_96 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c96 bl_0_96 br_0_96 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c96 bl_0_96 br_0_96 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c96 bl_0_96 br_0_96 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c96 bl_0_96 br_0_96 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c96 bl_0_96 br_0_96 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c96 bl_0_96 br_0_96 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c96 bl_0_96 br_0_96 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c96 bl_0_96 br_0_96 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c96 bl_0_96 br_0_96 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c96 bl_0_96 br_0_96 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c96 bl_0_96 br_0_96 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c96 bl_0_96 br_0_96 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c96 bl_0_96 br_0_96 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c96 bl_0_96 br_0_96 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c96 bl_0_96 br_0_96 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c96 bl_0_96 br_0_96 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c96 bl_0_96 br_0_96 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c96 bl_0_96 br_0_96 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c96 bl_0_96 br_0_96 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c96 bl_0_96 br_0_96 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c96 bl_0_96 br_0_96 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c96 bl_0_96 br_0_96 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c96 bl_0_96 br_0_96 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c96 bl_0_96 br_0_96 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c96 bl_0_96 br_0_96 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c96 bl_0_96 br_0_96 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c96 bl_0_96 br_0_96 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c96 bl_0_96 br_0_96 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c96 bl_0_96 br_0_96 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c96 bl_0_96 br_0_96 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c96 bl_0_96 br_0_96 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c96 bl_0_96 br_0_96 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c96 bl_0_96 br_0_96 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c96 bl_0_96 br_0_96 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c96 bl_0_96 br_0_96 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c96 bl_0_96 br_0_96 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c96 bl_0_96 br_0_96 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c96 bl_0_96 br_0_96 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c96 bl_0_96 br_0_96 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c96 bl_0_96 br_0_96 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c96 bl_0_96 br_0_96 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c96 bl_0_96 br_0_96 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c96 bl_0_96 br_0_96 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c96 bl_0_96 br_0_96 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c97 bl_0_97 br_0_97 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c97 bl_0_97 br_0_97 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c97 bl_0_97 br_0_97 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c97 bl_0_97 br_0_97 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c97 bl_0_97 br_0_97 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c97 bl_0_97 br_0_97 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c97 bl_0_97 br_0_97 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c97 bl_0_97 br_0_97 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c97 bl_0_97 br_0_97 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c97 bl_0_97 br_0_97 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c97 bl_0_97 br_0_97 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c97 bl_0_97 br_0_97 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c97 bl_0_97 br_0_97 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c97 bl_0_97 br_0_97 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c97 bl_0_97 br_0_97 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c97 bl_0_97 br_0_97 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c97 bl_0_97 br_0_97 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c97 bl_0_97 br_0_97 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c97 bl_0_97 br_0_97 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c97 bl_0_97 br_0_97 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c97 bl_0_97 br_0_97 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c97 bl_0_97 br_0_97 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c97 bl_0_97 br_0_97 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c97 bl_0_97 br_0_97 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c97 bl_0_97 br_0_97 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c97 bl_0_97 br_0_97 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c97 bl_0_97 br_0_97 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c97 bl_0_97 br_0_97 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c97 bl_0_97 br_0_97 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c97 bl_0_97 br_0_97 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c97 bl_0_97 br_0_97 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c97 bl_0_97 br_0_97 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c97 bl_0_97 br_0_97 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c97 bl_0_97 br_0_97 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c97 bl_0_97 br_0_97 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c97 bl_0_97 br_0_97 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c97 bl_0_97 br_0_97 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c97 bl_0_97 br_0_97 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c97 bl_0_97 br_0_97 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c97 bl_0_97 br_0_97 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c97 bl_0_97 br_0_97 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c97 bl_0_97 br_0_97 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c97 bl_0_97 br_0_97 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c97 bl_0_97 br_0_97 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c97 bl_0_97 br_0_97 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c97 bl_0_97 br_0_97 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c97 bl_0_97 br_0_97 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c97 bl_0_97 br_0_97 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c97 bl_0_97 br_0_97 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c97 bl_0_97 br_0_97 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c97 bl_0_97 br_0_97 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c97 bl_0_97 br_0_97 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c97 bl_0_97 br_0_97 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c97 bl_0_97 br_0_97 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c97 bl_0_97 br_0_97 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c97 bl_0_97 br_0_97 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c97 bl_0_97 br_0_97 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c97 bl_0_97 br_0_97 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c97 bl_0_97 br_0_97 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c97 bl_0_97 br_0_97 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c97 bl_0_97 br_0_97 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c97 bl_0_97 br_0_97 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c97 bl_0_97 br_0_97 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c97 bl_0_97 br_0_97 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c98 bl_0_98 br_0_98 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c98 bl_0_98 br_0_98 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c98 bl_0_98 br_0_98 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c98 bl_0_98 br_0_98 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c98 bl_0_98 br_0_98 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c98 bl_0_98 br_0_98 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c98 bl_0_98 br_0_98 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c98 bl_0_98 br_0_98 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c98 bl_0_98 br_0_98 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c98 bl_0_98 br_0_98 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c98 bl_0_98 br_0_98 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c98 bl_0_98 br_0_98 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c98 bl_0_98 br_0_98 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c98 bl_0_98 br_0_98 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c98 bl_0_98 br_0_98 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c98 bl_0_98 br_0_98 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c98 bl_0_98 br_0_98 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c98 bl_0_98 br_0_98 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c98 bl_0_98 br_0_98 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c98 bl_0_98 br_0_98 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c98 bl_0_98 br_0_98 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c98 bl_0_98 br_0_98 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c98 bl_0_98 br_0_98 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c98 bl_0_98 br_0_98 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c98 bl_0_98 br_0_98 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c98 bl_0_98 br_0_98 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c98 bl_0_98 br_0_98 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c98 bl_0_98 br_0_98 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c98 bl_0_98 br_0_98 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c98 bl_0_98 br_0_98 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c98 bl_0_98 br_0_98 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c98 bl_0_98 br_0_98 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c98 bl_0_98 br_0_98 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c98 bl_0_98 br_0_98 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c98 bl_0_98 br_0_98 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c98 bl_0_98 br_0_98 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c98 bl_0_98 br_0_98 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c98 bl_0_98 br_0_98 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c98 bl_0_98 br_0_98 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c98 bl_0_98 br_0_98 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c98 bl_0_98 br_0_98 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c98 bl_0_98 br_0_98 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c98 bl_0_98 br_0_98 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c98 bl_0_98 br_0_98 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c98 bl_0_98 br_0_98 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c98 bl_0_98 br_0_98 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c98 bl_0_98 br_0_98 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c98 bl_0_98 br_0_98 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c98 bl_0_98 br_0_98 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c98 bl_0_98 br_0_98 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c98 bl_0_98 br_0_98 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c98 bl_0_98 br_0_98 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c98 bl_0_98 br_0_98 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c98 bl_0_98 br_0_98 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c98 bl_0_98 br_0_98 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c98 bl_0_98 br_0_98 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c98 bl_0_98 br_0_98 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c98 bl_0_98 br_0_98 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c98 bl_0_98 br_0_98 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c98 bl_0_98 br_0_98 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c98 bl_0_98 br_0_98 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c98 bl_0_98 br_0_98 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c98 bl_0_98 br_0_98 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c98 bl_0_98 br_0_98 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c99 bl_0_99 br_0_99 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c99 bl_0_99 br_0_99 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c99 bl_0_99 br_0_99 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c99 bl_0_99 br_0_99 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c99 bl_0_99 br_0_99 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c99 bl_0_99 br_0_99 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c99 bl_0_99 br_0_99 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c99 bl_0_99 br_0_99 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c99 bl_0_99 br_0_99 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c99 bl_0_99 br_0_99 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c99 bl_0_99 br_0_99 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c99 bl_0_99 br_0_99 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c99 bl_0_99 br_0_99 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c99 bl_0_99 br_0_99 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c99 bl_0_99 br_0_99 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c99 bl_0_99 br_0_99 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c99 bl_0_99 br_0_99 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c99 bl_0_99 br_0_99 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c99 bl_0_99 br_0_99 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c99 bl_0_99 br_0_99 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c99 bl_0_99 br_0_99 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c99 bl_0_99 br_0_99 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c99 bl_0_99 br_0_99 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c99 bl_0_99 br_0_99 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c99 bl_0_99 br_0_99 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c99 bl_0_99 br_0_99 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c99 bl_0_99 br_0_99 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c99 bl_0_99 br_0_99 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c99 bl_0_99 br_0_99 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c99 bl_0_99 br_0_99 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c99 bl_0_99 br_0_99 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c99 bl_0_99 br_0_99 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c99 bl_0_99 br_0_99 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c99 bl_0_99 br_0_99 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c99 bl_0_99 br_0_99 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c99 bl_0_99 br_0_99 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c99 bl_0_99 br_0_99 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c99 bl_0_99 br_0_99 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c99 bl_0_99 br_0_99 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c99 bl_0_99 br_0_99 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c99 bl_0_99 br_0_99 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c99 bl_0_99 br_0_99 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c99 bl_0_99 br_0_99 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c99 bl_0_99 br_0_99 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c99 bl_0_99 br_0_99 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c99 bl_0_99 br_0_99 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c99 bl_0_99 br_0_99 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c99 bl_0_99 br_0_99 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c99 bl_0_99 br_0_99 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c99 bl_0_99 br_0_99 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c99 bl_0_99 br_0_99 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c99 bl_0_99 br_0_99 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c99 bl_0_99 br_0_99 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c99 bl_0_99 br_0_99 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c99 bl_0_99 br_0_99 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c99 bl_0_99 br_0_99 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c99 bl_0_99 br_0_99 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c99 bl_0_99 br_0_99 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c99 bl_0_99 br_0_99 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c99 bl_0_99 br_0_99 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c99 bl_0_99 br_0_99 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c99 bl_0_99 br_0_99 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c99 bl_0_99 br_0_99 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c99 bl_0_99 br_0_99 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c100 bl_0_100 br_0_100 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c100 bl_0_100 br_0_100 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c100 bl_0_100 br_0_100 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c100 bl_0_100 br_0_100 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c100 bl_0_100 br_0_100 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c100 bl_0_100 br_0_100 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c100 bl_0_100 br_0_100 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c100 bl_0_100 br_0_100 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c100 bl_0_100 br_0_100 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c100 bl_0_100 br_0_100 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c100 bl_0_100 br_0_100 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c100 bl_0_100 br_0_100 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c100 bl_0_100 br_0_100 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c100 bl_0_100 br_0_100 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c100 bl_0_100 br_0_100 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c100 bl_0_100 br_0_100 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c100 bl_0_100 br_0_100 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c100 bl_0_100 br_0_100 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c100 bl_0_100 br_0_100 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c100 bl_0_100 br_0_100 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c100 bl_0_100 br_0_100 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c100 bl_0_100 br_0_100 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c100 bl_0_100 br_0_100 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c100 bl_0_100 br_0_100 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c100 bl_0_100 br_0_100 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c100 bl_0_100 br_0_100 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c100 bl_0_100 br_0_100 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c100 bl_0_100 br_0_100 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c100 bl_0_100 br_0_100 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c100 bl_0_100 br_0_100 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c100 bl_0_100 br_0_100 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c100 bl_0_100 br_0_100 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c100 bl_0_100 br_0_100 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c100 bl_0_100 br_0_100 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c100 bl_0_100 br_0_100 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c100 bl_0_100 br_0_100 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c100 bl_0_100 br_0_100 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c100 bl_0_100 br_0_100 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c100 bl_0_100 br_0_100 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c100 bl_0_100 br_0_100 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c100 bl_0_100 br_0_100 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c100 bl_0_100 br_0_100 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c100 bl_0_100 br_0_100 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c100 bl_0_100 br_0_100 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c100 bl_0_100 br_0_100 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c100 bl_0_100 br_0_100 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c100 bl_0_100 br_0_100 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c100 bl_0_100 br_0_100 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c100 bl_0_100 br_0_100 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c100 bl_0_100 br_0_100 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c100 bl_0_100 br_0_100 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c100 bl_0_100 br_0_100 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c100 bl_0_100 br_0_100 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c100 bl_0_100 br_0_100 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c100 bl_0_100 br_0_100 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c100 bl_0_100 br_0_100 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c100 bl_0_100 br_0_100 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c100 bl_0_100 br_0_100 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c100 bl_0_100 br_0_100 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c100 bl_0_100 br_0_100 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c100 bl_0_100 br_0_100 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c100 bl_0_100 br_0_100 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c100 bl_0_100 br_0_100 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c100 bl_0_100 br_0_100 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c101 bl_0_101 br_0_101 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c101 bl_0_101 br_0_101 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c101 bl_0_101 br_0_101 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c101 bl_0_101 br_0_101 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c101 bl_0_101 br_0_101 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c101 bl_0_101 br_0_101 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c101 bl_0_101 br_0_101 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c101 bl_0_101 br_0_101 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c101 bl_0_101 br_0_101 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c101 bl_0_101 br_0_101 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c101 bl_0_101 br_0_101 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c101 bl_0_101 br_0_101 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c101 bl_0_101 br_0_101 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c101 bl_0_101 br_0_101 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c101 bl_0_101 br_0_101 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c101 bl_0_101 br_0_101 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c101 bl_0_101 br_0_101 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c101 bl_0_101 br_0_101 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c101 bl_0_101 br_0_101 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c101 bl_0_101 br_0_101 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c101 bl_0_101 br_0_101 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c101 bl_0_101 br_0_101 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c101 bl_0_101 br_0_101 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c101 bl_0_101 br_0_101 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c101 bl_0_101 br_0_101 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c101 bl_0_101 br_0_101 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c101 bl_0_101 br_0_101 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c101 bl_0_101 br_0_101 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c101 bl_0_101 br_0_101 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c101 bl_0_101 br_0_101 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c101 bl_0_101 br_0_101 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c101 bl_0_101 br_0_101 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c101 bl_0_101 br_0_101 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c101 bl_0_101 br_0_101 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c101 bl_0_101 br_0_101 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c101 bl_0_101 br_0_101 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c101 bl_0_101 br_0_101 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c101 bl_0_101 br_0_101 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c101 bl_0_101 br_0_101 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c101 bl_0_101 br_0_101 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c101 bl_0_101 br_0_101 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c101 bl_0_101 br_0_101 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c101 bl_0_101 br_0_101 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c101 bl_0_101 br_0_101 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c101 bl_0_101 br_0_101 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c101 bl_0_101 br_0_101 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c101 bl_0_101 br_0_101 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c101 bl_0_101 br_0_101 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c101 bl_0_101 br_0_101 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c101 bl_0_101 br_0_101 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c101 bl_0_101 br_0_101 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c101 bl_0_101 br_0_101 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c101 bl_0_101 br_0_101 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c101 bl_0_101 br_0_101 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c101 bl_0_101 br_0_101 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c101 bl_0_101 br_0_101 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c101 bl_0_101 br_0_101 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c101 bl_0_101 br_0_101 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c101 bl_0_101 br_0_101 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c101 bl_0_101 br_0_101 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c101 bl_0_101 br_0_101 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c101 bl_0_101 br_0_101 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c101 bl_0_101 br_0_101 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c101 bl_0_101 br_0_101 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c102 bl_0_102 br_0_102 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c102 bl_0_102 br_0_102 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c102 bl_0_102 br_0_102 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c102 bl_0_102 br_0_102 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c102 bl_0_102 br_0_102 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c102 bl_0_102 br_0_102 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c102 bl_0_102 br_0_102 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c102 bl_0_102 br_0_102 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c102 bl_0_102 br_0_102 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c102 bl_0_102 br_0_102 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c102 bl_0_102 br_0_102 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c102 bl_0_102 br_0_102 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c102 bl_0_102 br_0_102 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c102 bl_0_102 br_0_102 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c102 bl_0_102 br_0_102 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c102 bl_0_102 br_0_102 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c102 bl_0_102 br_0_102 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c102 bl_0_102 br_0_102 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c102 bl_0_102 br_0_102 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c102 bl_0_102 br_0_102 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c102 bl_0_102 br_0_102 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c102 bl_0_102 br_0_102 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c102 bl_0_102 br_0_102 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c102 bl_0_102 br_0_102 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c102 bl_0_102 br_0_102 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c102 bl_0_102 br_0_102 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c102 bl_0_102 br_0_102 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c102 bl_0_102 br_0_102 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c102 bl_0_102 br_0_102 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c102 bl_0_102 br_0_102 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c102 bl_0_102 br_0_102 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c102 bl_0_102 br_0_102 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c102 bl_0_102 br_0_102 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c102 bl_0_102 br_0_102 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c102 bl_0_102 br_0_102 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c102 bl_0_102 br_0_102 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c102 bl_0_102 br_0_102 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c102 bl_0_102 br_0_102 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c102 bl_0_102 br_0_102 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c102 bl_0_102 br_0_102 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c102 bl_0_102 br_0_102 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c102 bl_0_102 br_0_102 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c102 bl_0_102 br_0_102 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c102 bl_0_102 br_0_102 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c102 bl_0_102 br_0_102 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c102 bl_0_102 br_0_102 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c102 bl_0_102 br_0_102 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c102 bl_0_102 br_0_102 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c102 bl_0_102 br_0_102 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c102 bl_0_102 br_0_102 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c102 bl_0_102 br_0_102 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c102 bl_0_102 br_0_102 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c102 bl_0_102 br_0_102 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c102 bl_0_102 br_0_102 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c102 bl_0_102 br_0_102 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c102 bl_0_102 br_0_102 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c102 bl_0_102 br_0_102 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c102 bl_0_102 br_0_102 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c102 bl_0_102 br_0_102 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c102 bl_0_102 br_0_102 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c102 bl_0_102 br_0_102 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c102 bl_0_102 br_0_102 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c102 bl_0_102 br_0_102 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c102 bl_0_102 br_0_102 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c103 bl_0_103 br_0_103 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c103 bl_0_103 br_0_103 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c103 bl_0_103 br_0_103 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c103 bl_0_103 br_0_103 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c103 bl_0_103 br_0_103 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c103 bl_0_103 br_0_103 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c103 bl_0_103 br_0_103 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c103 bl_0_103 br_0_103 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c103 bl_0_103 br_0_103 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c103 bl_0_103 br_0_103 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c103 bl_0_103 br_0_103 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c103 bl_0_103 br_0_103 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c103 bl_0_103 br_0_103 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c103 bl_0_103 br_0_103 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c103 bl_0_103 br_0_103 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c103 bl_0_103 br_0_103 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c103 bl_0_103 br_0_103 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c103 bl_0_103 br_0_103 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c103 bl_0_103 br_0_103 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c103 bl_0_103 br_0_103 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c103 bl_0_103 br_0_103 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c103 bl_0_103 br_0_103 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c103 bl_0_103 br_0_103 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c103 bl_0_103 br_0_103 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c103 bl_0_103 br_0_103 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c103 bl_0_103 br_0_103 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c103 bl_0_103 br_0_103 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c103 bl_0_103 br_0_103 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c103 bl_0_103 br_0_103 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c103 bl_0_103 br_0_103 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c103 bl_0_103 br_0_103 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c103 bl_0_103 br_0_103 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c103 bl_0_103 br_0_103 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c103 bl_0_103 br_0_103 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c103 bl_0_103 br_0_103 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c103 bl_0_103 br_0_103 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c103 bl_0_103 br_0_103 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c103 bl_0_103 br_0_103 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c103 bl_0_103 br_0_103 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c103 bl_0_103 br_0_103 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c103 bl_0_103 br_0_103 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c103 bl_0_103 br_0_103 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c103 bl_0_103 br_0_103 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c103 bl_0_103 br_0_103 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c103 bl_0_103 br_0_103 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c103 bl_0_103 br_0_103 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c103 bl_0_103 br_0_103 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c103 bl_0_103 br_0_103 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c103 bl_0_103 br_0_103 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c103 bl_0_103 br_0_103 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c103 bl_0_103 br_0_103 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c103 bl_0_103 br_0_103 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c103 bl_0_103 br_0_103 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c103 bl_0_103 br_0_103 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c103 bl_0_103 br_0_103 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c103 bl_0_103 br_0_103 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c103 bl_0_103 br_0_103 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c103 bl_0_103 br_0_103 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c103 bl_0_103 br_0_103 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c103 bl_0_103 br_0_103 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c103 bl_0_103 br_0_103 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c103 bl_0_103 br_0_103 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c103 bl_0_103 br_0_103 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c103 bl_0_103 br_0_103 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c104 bl_0_104 br_0_104 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c104 bl_0_104 br_0_104 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c104 bl_0_104 br_0_104 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c104 bl_0_104 br_0_104 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c104 bl_0_104 br_0_104 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c104 bl_0_104 br_0_104 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c104 bl_0_104 br_0_104 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c104 bl_0_104 br_0_104 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c104 bl_0_104 br_0_104 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c104 bl_0_104 br_0_104 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c104 bl_0_104 br_0_104 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c104 bl_0_104 br_0_104 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c104 bl_0_104 br_0_104 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c104 bl_0_104 br_0_104 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c104 bl_0_104 br_0_104 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c104 bl_0_104 br_0_104 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c104 bl_0_104 br_0_104 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c104 bl_0_104 br_0_104 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c104 bl_0_104 br_0_104 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c104 bl_0_104 br_0_104 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c104 bl_0_104 br_0_104 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c104 bl_0_104 br_0_104 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c104 bl_0_104 br_0_104 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c104 bl_0_104 br_0_104 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c104 bl_0_104 br_0_104 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c104 bl_0_104 br_0_104 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c104 bl_0_104 br_0_104 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c104 bl_0_104 br_0_104 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c104 bl_0_104 br_0_104 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c104 bl_0_104 br_0_104 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c104 bl_0_104 br_0_104 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c104 bl_0_104 br_0_104 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c104 bl_0_104 br_0_104 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c104 bl_0_104 br_0_104 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c104 bl_0_104 br_0_104 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c104 bl_0_104 br_0_104 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c104 bl_0_104 br_0_104 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c104 bl_0_104 br_0_104 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c104 bl_0_104 br_0_104 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c104 bl_0_104 br_0_104 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c104 bl_0_104 br_0_104 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c104 bl_0_104 br_0_104 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c104 bl_0_104 br_0_104 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c104 bl_0_104 br_0_104 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c104 bl_0_104 br_0_104 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c104 bl_0_104 br_0_104 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c104 bl_0_104 br_0_104 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c104 bl_0_104 br_0_104 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c104 bl_0_104 br_0_104 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c104 bl_0_104 br_0_104 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c104 bl_0_104 br_0_104 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c104 bl_0_104 br_0_104 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c104 bl_0_104 br_0_104 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c104 bl_0_104 br_0_104 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c104 bl_0_104 br_0_104 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c104 bl_0_104 br_0_104 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c104 bl_0_104 br_0_104 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c104 bl_0_104 br_0_104 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c104 bl_0_104 br_0_104 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c104 bl_0_104 br_0_104 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c104 bl_0_104 br_0_104 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c104 bl_0_104 br_0_104 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c104 bl_0_104 br_0_104 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c104 bl_0_104 br_0_104 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c105 bl_0_105 br_0_105 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c105 bl_0_105 br_0_105 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c105 bl_0_105 br_0_105 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c105 bl_0_105 br_0_105 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c105 bl_0_105 br_0_105 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c105 bl_0_105 br_0_105 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c105 bl_0_105 br_0_105 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c105 bl_0_105 br_0_105 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c105 bl_0_105 br_0_105 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c105 bl_0_105 br_0_105 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c105 bl_0_105 br_0_105 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c105 bl_0_105 br_0_105 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c105 bl_0_105 br_0_105 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c105 bl_0_105 br_0_105 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c105 bl_0_105 br_0_105 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c105 bl_0_105 br_0_105 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c105 bl_0_105 br_0_105 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c105 bl_0_105 br_0_105 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c105 bl_0_105 br_0_105 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c105 bl_0_105 br_0_105 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c105 bl_0_105 br_0_105 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c105 bl_0_105 br_0_105 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c105 bl_0_105 br_0_105 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c105 bl_0_105 br_0_105 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c105 bl_0_105 br_0_105 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c105 bl_0_105 br_0_105 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c105 bl_0_105 br_0_105 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c105 bl_0_105 br_0_105 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c105 bl_0_105 br_0_105 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c105 bl_0_105 br_0_105 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c105 bl_0_105 br_0_105 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c105 bl_0_105 br_0_105 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c105 bl_0_105 br_0_105 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c105 bl_0_105 br_0_105 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c105 bl_0_105 br_0_105 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c105 bl_0_105 br_0_105 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c105 bl_0_105 br_0_105 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c105 bl_0_105 br_0_105 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c105 bl_0_105 br_0_105 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c105 bl_0_105 br_0_105 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c105 bl_0_105 br_0_105 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c105 bl_0_105 br_0_105 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c105 bl_0_105 br_0_105 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c105 bl_0_105 br_0_105 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c105 bl_0_105 br_0_105 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c105 bl_0_105 br_0_105 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c105 bl_0_105 br_0_105 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c105 bl_0_105 br_0_105 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c105 bl_0_105 br_0_105 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c105 bl_0_105 br_0_105 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c105 bl_0_105 br_0_105 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c105 bl_0_105 br_0_105 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c105 bl_0_105 br_0_105 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c105 bl_0_105 br_0_105 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c105 bl_0_105 br_0_105 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c105 bl_0_105 br_0_105 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c105 bl_0_105 br_0_105 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c105 bl_0_105 br_0_105 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c105 bl_0_105 br_0_105 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c105 bl_0_105 br_0_105 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c105 bl_0_105 br_0_105 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c105 bl_0_105 br_0_105 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c105 bl_0_105 br_0_105 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c105 bl_0_105 br_0_105 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c106 bl_0_106 br_0_106 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c106 bl_0_106 br_0_106 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c106 bl_0_106 br_0_106 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c106 bl_0_106 br_0_106 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c106 bl_0_106 br_0_106 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c106 bl_0_106 br_0_106 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c106 bl_0_106 br_0_106 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c106 bl_0_106 br_0_106 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c106 bl_0_106 br_0_106 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c106 bl_0_106 br_0_106 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c106 bl_0_106 br_0_106 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c106 bl_0_106 br_0_106 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c106 bl_0_106 br_0_106 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c106 bl_0_106 br_0_106 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c106 bl_0_106 br_0_106 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c106 bl_0_106 br_0_106 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c106 bl_0_106 br_0_106 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c106 bl_0_106 br_0_106 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c106 bl_0_106 br_0_106 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c106 bl_0_106 br_0_106 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c106 bl_0_106 br_0_106 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c106 bl_0_106 br_0_106 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c106 bl_0_106 br_0_106 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c106 bl_0_106 br_0_106 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c106 bl_0_106 br_0_106 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c106 bl_0_106 br_0_106 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c106 bl_0_106 br_0_106 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c106 bl_0_106 br_0_106 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c106 bl_0_106 br_0_106 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c106 bl_0_106 br_0_106 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c106 bl_0_106 br_0_106 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c106 bl_0_106 br_0_106 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c106 bl_0_106 br_0_106 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c106 bl_0_106 br_0_106 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c106 bl_0_106 br_0_106 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c106 bl_0_106 br_0_106 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c106 bl_0_106 br_0_106 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c106 bl_0_106 br_0_106 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c106 bl_0_106 br_0_106 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c106 bl_0_106 br_0_106 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c106 bl_0_106 br_0_106 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c106 bl_0_106 br_0_106 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c106 bl_0_106 br_0_106 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c106 bl_0_106 br_0_106 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c106 bl_0_106 br_0_106 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c106 bl_0_106 br_0_106 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c106 bl_0_106 br_0_106 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c106 bl_0_106 br_0_106 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c106 bl_0_106 br_0_106 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c106 bl_0_106 br_0_106 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c106 bl_0_106 br_0_106 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c106 bl_0_106 br_0_106 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c106 bl_0_106 br_0_106 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c106 bl_0_106 br_0_106 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c106 bl_0_106 br_0_106 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c106 bl_0_106 br_0_106 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c106 bl_0_106 br_0_106 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c106 bl_0_106 br_0_106 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c106 bl_0_106 br_0_106 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c106 bl_0_106 br_0_106 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c106 bl_0_106 br_0_106 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c106 bl_0_106 br_0_106 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c106 bl_0_106 br_0_106 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c106 bl_0_106 br_0_106 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c107 bl_0_107 br_0_107 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c107 bl_0_107 br_0_107 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c107 bl_0_107 br_0_107 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c107 bl_0_107 br_0_107 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c107 bl_0_107 br_0_107 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c107 bl_0_107 br_0_107 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c107 bl_0_107 br_0_107 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c107 bl_0_107 br_0_107 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c107 bl_0_107 br_0_107 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c107 bl_0_107 br_0_107 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c107 bl_0_107 br_0_107 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c107 bl_0_107 br_0_107 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c107 bl_0_107 br_0_107 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c107 bl_0_107 br_0_107 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c107 bl_0_107 br_0_107 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c107 bl_0_107 br_0_107 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c107 bl_0_107 br_0_107 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c107 bl_0_107 br_0_107 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c107 bl_0_107 br_0_107 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c107 bl_0_107 br_0_107 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c107 bl_0_107 br_0_107 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c107 bl_0_107 br_0_107 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c107 bl_0_107 br_0_107 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c107 bl_0_107 br_0_107 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c107 bl_0_107 br_0_107 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c107 bl_0_107 br_0_107 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c107 bl_0_107 br_0_107 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c107 bl_0_107 br_0_107 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c107 bl_0_107 br_0_107 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c107 bl_0_107 br_0_107 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c107 bl_0_107 br_0_107 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c107 bl_0_107 br_0_107 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c107 bl_0_107 br_0_107 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c107 bl_0_107 br_0_107 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c107 bl_0_107 br_0_107 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c107 bl_0_107 br_0_107 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c107 bl_0_107 br_0_107 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c107 bl_0_107 br_0_107 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c107 bl_0_107 br_0_107 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c107 bl_0_107 br_0_107 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c107 bl_0_107 br_0_107 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c107 bl_0_107 br_0_107 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c107 bl_0_107 br_0_107 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c107 bl_0_107 br_0_107 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c107 bl_0_107 br_0_107 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c107 bl_0_107 br_0_107 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c107 bl_0_107 br_0_107 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c107 bl_0_107 br_0_107 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c107 bl_0_107 br_0_107 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c107 bl_0_107 br_0_107 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c107 bl_0_107 br_0_107 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c107 bl_0_107 br_0_107 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c107 bl_0_107 br_0_107 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c107 bl_0_107 br_0_107 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c107 bl_0_107 br_0_107 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c107 bl_0_107 br_0_107 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c107 bl_0_107 br_0_107 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c107 bl_0_107 br_0_107 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c107 bl_0_107 br_0_107 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c107 bl_0_107 br_0_107 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c107 bl_0_107 br_0_107 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c107 bl_0_107 br_0_107 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c107 bl_0_107 br_0_107 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c107 bl_0_107 br_0_107 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c108 bl_0_108 br_0_108 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c108 bl_0_108 br_0_108 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c108 bl_0_108 br_0_108 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c108 bl_0_108 br_0_108 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c108 bl_0_108 br_0_108 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c108 bl_0_108 br_0_108 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c108 bl_0_108 br_0_108 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c108 bl_0_108 br_0_108 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c108 bl_0_108 br_0_108 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c108 bl_0_108 br_0_108 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c108 bl_0_108 br_0_108 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c108 bl_0_108 br_0_108 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c108 bl_0_108 br_0_108 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c108 bl_0_108 br_0_108 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c108 bl_0_108 br_0_108 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c108 bl_0_108 br_0_108 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c108 bl_0_108 br_0_108 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c108 bl_0_108 br_0_108 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c108 bl_0_108 br_0_108 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c108 bl_0_108 br_0_108 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c108 bl_0_108 br_0_108 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c108 bl_0_108 br_0_108 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c108 bl_0_108 br_0_108 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c108 bl_0_108 br_0_108 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c108 bl_0_108 br_0_108 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c108 bl_0_108 br_0_108 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c108 bl_0_108 br_0_108 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c108 bl_0_108 br_0_108 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c108 bl_0_108 br_0_108 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c108 bl_0_108 br_0_108 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c108 bl_0_108 br_0_108 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c108 bl_0_108 br_0_108 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c108 bl_0_108 br_0_108 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c108 bl_0_108 br_0_108 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c108 bl_0_108 br_0_108 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c108 bl_0_108 br_0_108 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c108 bl_0_108 br_0_108 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c108 bl_0_108 br_0_108 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c108 bl_0_108 br_0_108 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c108 bl_0_108 br_0_108 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c108 bl_0_108 br_0_108 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c108 bl_0_108 br_0_108 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c108 bl_0_108 br_0_108 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c108 bl_0_108 br_0_108 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c108 bl_0_108 br_0_108 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c108 bl_0_108 br_0_108 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c108 bl_0_108 br_0_108 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c108 bl_0_108 br_0_108 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c108 bl_0_108 br_0_108 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c108 bl_0_108 br_0_108 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c108 bl_0_108 br_0_108 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c108 bl_0_108 br_0_108 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c108 bl_0_108 br_0_108 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c108 bl_0_108 br_0_108 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c108 bl_0_108 br_0_108 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c108 bl_0_108 br_0_108 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c108 bl_0_108 br_0_108 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c108 bl_0_108 br_0_108 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c108 bl_0_108 br_0_108 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c108 bl_0_108 br_0_108 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c108 bl_0_108 br_0_108 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c108 bl_0_108 br_0_108 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c108 bl_0_108 br_0_108 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c108 bl_0_108 br_0_108 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c109 bl_0_109 br_0_109 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c109 bl_0_109 br_0_109 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c109 bl_0_109 br_0_109 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c109 bl_0_109 br_0_109 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c109 bl_0_109 br_0_109 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c109 bl_0_109 br_0_109 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c109 bl_0_109 br_0_109 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c109 bl_0_109 br_0_109 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c109 bl_0_109 br_0_109 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c109 bl_0_109 br_0_109 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c109 bl_0_109 br_0_109 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c109 bl_0_109 br_0_109 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c109 bl_0_109 br_0_109 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c109 bl_0_109 br_0_109 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c109 bl_0_109 br_0_109 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c109 bl_0_109 br_0_109 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c109 bl_0_109 br_0_109 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c109 bl_0_109 br_0_109 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c109 bl_0_109 br_0_109 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c109 bl_0_109 br_0_109 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c109 bl_0_109 br_0_109 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c109 bl_0_109 br_0_109 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c109 bl_0_109 br_0_109 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c109 bl_0_109 br_0_109 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c109 bl_0_109 br_0_109 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c109 bl_0_109 br_0_109 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c109 bl_0_109 br_0_109 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c109 bl_0_109 br_0_109 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c109 bl_0_109 br_0_109 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c109 bl_0_109 br_0_109 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c109 bl_0_109 br_0_109 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c109 bl_0_109 br_0_109 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c109 bl_0_109 br_0_109 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c109 bl_0_109 br_0_109 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c109 bl_0_109 br_0_109 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c109 bl_0_109 br_0_109 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c109 bl_0_109 br_0_109 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c109 bl_0_109 br_0_109 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c109 bl_0_109 br_0_109 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c109 bl_0_109 br_0_109 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c109 bl_0_109 br_0_109 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c109 bl_0_109 br_0_109 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c109 bl_0_109 br_0_109 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c109 bl_0_109 br_0_109 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c109 bl_0_109 br_0_109 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c109 bl_0_109 br_0_109 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c109 bl_0_109 br_0_109 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c109 bl_0_109 br_0_109 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c109 bl_0_109 br_0_109 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c109 bl_0_109 br_0_109 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c109 bl_0_109 br_0_109 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c109 bl_0_109 br_0_109 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c109 bl_0_109 br_0_109 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c109 bl_0_109 br_0_109 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c109 bl_0_109 br_0_109 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c109 bl_0_109 br_0_109 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c109 bl_0_109 br_0_109 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c109 bl_0_109 br_0_109 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c109 bl_0_109 br_0_109 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c109 bl_0_109 br_0_109 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c109 bl_0_109 br_0_109 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c109 bl_0_109 br_0_109 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c109 bl_0_109 br_0_109 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c109 bl_0_109 br_0_109 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c110 bl_0_110 br_0_110 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c110 bl_0_110 br_0_110 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c110 bl_0_110 br_0_110 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c110 bl_0_110 br_0_110 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c110 bl_0_110 br_0_110 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c110 bl_0_110 br_0_110 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c110 bl_0_110 br_0_110 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c110 bl_0_110 br_0_110 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c110 bl_0_110 br_0_110 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c110 bl_0_110 br_0_110 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c110 bl_0_110 br_0_110 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c110 bl_0_110 br_0_110 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c110 bl_0_110 br_0_110 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c110 bl_0_110 br_0_110 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c110 bl_0_110 br_0_110 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c110 bl_0_110 br_0_110 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c110 bl_0_110 br_0_110 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c110 bl_0_110 br_0_110 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c110 bl_0_110 br_0_110 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c110 bl_0_110 br_0_110 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c110 bl_0_110 br_0_110 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c110 bl_0_110 br_0_110 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c110 bl_0_110 br_0_110 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c110 bl_0_110 br_0_110 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c110 bl_0_110 br_0_110 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c110 bl_0_110 br_0_110 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c110 bl_0_110 br_0_110 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c110 bl_0_110 br_0_110 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c110 bl_0_110 br_0_110 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c110 bl_0_110 br_0_110 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c110 bl_0_110 br_0_110 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c110 bl_0_110 br_0_110 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c110 bl_0_110 br_0_110 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c110 bl_0_110 br_0_110 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c110 bl_0_110 br_0_110 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c110 bl_0_110 br_0_110 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c110 bl_0_110 br_0_110 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c110 bl_0_110 br_0_110 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c110 bl_0_110 br_0_110 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c110 bl_0_110 br_0_110 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c110 bl_0_110 br_0_110 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c110 bl_0_110 br_0_110 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c110 bl_0_110 br_0_110 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c110 bl_0_110 br_0_110 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c110 bl_0_110 br_0_110 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c110 bl_0_110 br_0_110 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c110 bl_0_110 br_0_110 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c110 bl_0_110 br_0_110 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c110 bl_0_110 br_0_110 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c110 bl_0_110 br_0_110 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c110 bl_0_110 br_0_110 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c110 bl_0_110 br_0_110 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c110 bl_0_110 br_0_110 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c110 bl_0_110 br_0_110 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c110 bl_0_110 br_0_110 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c110 bl_0_110 br_0_110 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c110 bl_0_110 br_0_110 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c110 bl_0_110 br_0_110 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c110 bl_0_110 br_0_110 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c110 bl_0_110 br_0_110 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c110 bl_0_110 br_0_110 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c110 bl_0_110 br_0_110 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c110 bl_0_110 br_0_110 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c110 bl_0_110 br_0_110 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c111 bl_0_111 br_0_111 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c111 bl_0_111 br_0_111 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c111 bl_0_111 br_0_111 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c111 bl_0_111 br_0_111 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c111 bl_0_111 br_0_111 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c111 bl_0_111 br_0_111 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c111 bl_0_111 br_0_111 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c111 bl_0_111 br_0_111 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c111 bl_0_111 br_0_111 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c111 bl_0_111 br_0_111 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c111 bl_0_111 br_0_111 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c111 bl_0_111 br_0_111 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c111 bl_0_111 br_0_111 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c111 bl_0_111 br_0_111 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c111 bl_0_111 br_0_111 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c111 bl_0_111 br_0_111 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c111 bl_0_111 br_0_111 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c111 bl_0_111 br_0_111 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c111 bl_0_111 br_0_111 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c111 bl_0_111 br_0_111 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c111 bl_0_111 br_0_111 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c111 bl_0_111 br_0_111 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c111 bl_0_111 br_0_111 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c111 bl_0_111 br_0_111 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c111 bl_0_111 br_0_111 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c111 bl_0_111 br_0_111 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c111 bl_0_111 br_0_111 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c111 bl_0_111 br_0_111 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c111 bl_0_111 br_0_111 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c111 bl_0_111 br_0_111 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c111 bl_0_111 br_0_111 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c111 bl_0_111 br_0_111 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c111 bl_0_111 br_0_111 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c111 bl_0_111 br_0_111 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c111 bl_0_111 br_0_111 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c111 bl_0_111 br_0_111 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c111 bl_0_111 br_0_111 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c111 bl_0_111 br_0_111 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c111 bl_0_111 br_0_111 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c111 bl_0_111 br_0_111 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c111 bl_0_111 br_0_111 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c111 bl_0_111 br_0_111 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c111 bl_0_111 br_0_111 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c111 bl_0_111 br_0_111 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c111 bl_0_111 br_0_111 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c111 bl_0_111 br_0_111 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c111 bl_0_111 br_0_111 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c111 bl_0_111 br_0_111 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c111 bl_0_111 br_0_111 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c111 bl_0_111 br_0_111 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c111 bl_0_111 br_0_111 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c111 bl_0_111 br_0_111 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c111 bl_0_111 br_0_111 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c111 bl_0_111 br_0_111 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c111 bl_0_111 br_0_111 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c111 bl_0_111 br_0_111 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c111 bl_0_111 br_0_111 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c111 bl_0_111 br_0_111 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c111 bl_0_111 br_0_111 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c111 bl_0_111 br_0_111 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c111 bl_0_111 br_0_111 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c111 bl_0_111 br_0_111 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c111 bl_0_111 br_0_111 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c111 bl_0_111 br_0_111 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c112 bl_0_112 br_0_112 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c112 bl_0_112 br_0_112 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c112 bl_0_112 br_0_112 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c112 bl_0_112 br_0_112 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c112 bl_0_112 br_0_112 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c112 bl_0_112 br_0_112 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c112 bl_0_112 br_0_112 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c112 bl_0_112 br_0_112 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c112 bl_0_112 br_0_112 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c112 bl_0_112 br_0_112 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c112 bl_0_112 br_0_112 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c112 bl_0_112 br_0_112 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c112 bl_0_112 br_0_112 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c112 bl_0_112 br_0_112 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c112 bl_0_112 br_0_112 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c112 bl_0_112 br_0_112 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c112 bl_0_112 br_0_112 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c112 bl_0_112 br_0_112 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c112 bl_0_112 br_0_112 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c112 bl_0_112 br_0_112 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c112 bl_0_112 br_0_112 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c112 bl_0_112 br_0_112 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c112 bl_0_112 br_0_112 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c112 bl_0_112 br_0_112 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c112 bl_0_112 br_0_112 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c112 bl_0_112 br_0_112 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c112 bl_0_112 br_0_112 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c112 bl_0_112 br_0_112 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c112 bl_0_112 br_0_112 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c112 bl_0_112 br_0_112 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c112 bl_0_112 br_0_112 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c112 bl_0_112 br_0_112 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c112 bl_0_112 br_0_112 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c112 bl_0_112 br_0_112 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c112 bl_0_112 br_0_112 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c112 bl_0_112 br_0_112 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c112 bl_0_112 br_0_112 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c112 bl_0_112 br_0_112 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c112 bl_0_112 br_0_112 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c112 bl_0_112 br_0_112 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c112 bl_0_112 br_0_112 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c112 bl_0_112 br_0_112 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c112 bl_0_112 br_0_112 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c112 bl_0_112 br_0_112 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c112 bl_0_112 br_0_112 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c112 bl_0_112 br_0_112 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c112 bl_0_112 br_0_112 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c112 bl_0_112 br_0_112 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c112 bl_0_112 br_0_112 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c112 bl_0_112 br_0_112 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c112 bl_0_112 br_0_112 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c112 bl_0_112 br_0_112 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c112 bl_0_112 br_0_112 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c112 bl_0_112 br_0_112 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c112 bl_0_112 br_0_112 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c112 bl_0_112 br_0_112 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c112 bl_0_112 br_0_112 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c112 bl_0_112 br_0_112 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c112 bl_0_112 br_0_112 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c112 bl_0_112 br_0_112 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c112 bl_0_112 br_0_112 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c112 bl_0_112 br_0_112 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c112 bl_0_112 br_0_112 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c112 bl_0_112 br_0_112 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c113 bl_0_113 br_0_113 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c113 bl_0_113 br_0_113 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c113 bl_0_113 br_0_113 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c113 bl_0_113 br_0_113 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c113 bl_0_113 br_0_113 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c113 bl_0_113 br_0_113 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c113 bl_0_113 br_0_113 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c113 bl_0_113 br_0_113 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c113 bl_0_113 br_0_113 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c113 bl_0_113 br_0_113 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c113 bl_0_113 br_0_113 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c113 bl_0_113 br_0_113 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c113 bl_0_113 br_0_113 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c113 bl_0_113 br_0_113 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c113 bl_0_113 br_0_113 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c113 bl_0_113 br_0_113 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c113 bl_0_113 br_0_113 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c113 bl_0_113 br_0_113 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c113 bl_0_113 br_0_113 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c113 bl_0_113 br_0_113 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c113 bl_0_113 br_0_113 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c113 bl_0_113 br_0_113 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c113 bl_0_113 br_0_113 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c113 bl_0_113 br_0_113 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c113 bl_0_113 br_0_113 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c113 bl_0_113 br_0_113 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c113 bl_0_113 br_0_113 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c113 bl_0_113 br_0_113 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c113 bl_0_113 br_0_113 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c113 bl_0_113 br_0_113 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c113 bl_0_113 br_0_113 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c113 bl_0_113 br_0_113 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c113 bl_0_113 br_0_113 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c113 bl_0_113 br_0_113 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c113 bl_0_113 br_0_113 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c113 bl_0_113 br_0_113 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c113 bl_0_113 br_0_113 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c113 bl_0_113 br_0_113 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c113 bl_0_113 br_0_113 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c113 bl_0_113 br_0_113 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c113 bl_0_113 br_0_113 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c113 bl_0_113 br_0_113 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c113 bl_0_113 br_0_113 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c113 bl_0_113 br_0_113 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c113 bl_0_113 br_0_113 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c113 bl_0_113 br_0_113 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c113 bl_0_113 br_0_113 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c113 bl_0_113 br_0_113 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c113 bl_0_113 br_0_113 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c113 bl_0_113 br_0_113 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c113 bl_0_113 br_0_113 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c113 bl_0_113 br_0_113 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c113 bl_0_113 br_0_113 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c113 bl_0_113 br_0_113 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c113 bl_0_113 br_0_113 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c113 bl_0_113 br_0_113 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c113 bl_0_113 br_0_113 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c113 bl_0_113 br_0_113 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c113 bl_0_113 br_0_113 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c113 bl_0_113 br_0_113 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c113 bl_0_113 br_0_113 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c113 bl_0_113 br_0_113 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c113 bl_0_113 br_0_113 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c113 bl_0_113 br_0_113 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c114 bl_0_114 br_0_114 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c114 bl_0_114 br_0_114 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c114 bl_0_114 br_0_114 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c114 bl_0_114 br_0_114 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c114 bl_0_114 br_0_114 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c114 bl_0_114 br_0_114 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c114 bl_0_114 br_0_114 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c114 bl_0_114 br_0_114 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c114 bl_0_114 br_0_114 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c114 bl_0_114 br_0_114 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c114 bl_0_114 br_0_114 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c114 bl_0_114 br_0_114 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c114 bl_0_114 br_0_114 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c114 bl_0_114 br_0_114 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c114 bl_0_114 br_0_114 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c114 bl_0_114 br_0_114 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c114 bl_0_114 br_0_114 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c114 bl_0_114 br_0_114 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c114 bl_0_114 br_0_114 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c114 bl_0_114 br_0_114 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c114 bl_0_114 br_0_114 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c114 bl_0_114 br_0_114 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c114 bl_0_114 br_0_114 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c114 bl_0_114 br_0_114 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c114 bl_0_114 br_0_114 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c114 bl_0_114 br_0_114 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c114 bl_0_114 br_0_114 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c114 bl_0_114 br_0_114 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c114 bl_0_114 br_0_114 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c114 bl_0_114 br_0_114 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c114 bl_0_114 br_0_114 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c114 bl_0_114 br_0_114 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c114 bl_0_114 br_0_114 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c114 bl_0_114 br_0_114 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c114 bl_0_114 br_0_114 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c114 bl_0_114 br_0_114 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c114 bl_0_114 br_0_114 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c114 bl_0_114 br_0_114 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c114 bl_0_114 br_0_114 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c114 bl_0_114 br_0_114 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c114 bl_0_114 br_0_114 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c114 bl_0_114 br_0_114 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c114 bl_0_114 br_0_114 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c114 bl_0_114 br_0_114 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c114 bl_0_114 br_0_114 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c114 bl_0_114 br_0_114 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c114 bl_0_114 br_0_114 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c114 bl_0_114 br_0_114 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c114 bl_0_114 br_0_114 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c114 bl_0_114 br_0_114 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c114 bl_0_114 br_0_114 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c114 bl_0_114 br_0_114 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c114 bl_0_114 br_0_114 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c114 bl_0_114 br_0_114 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c114 bl_0_114 br_0_114 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c114 bl_0_114 br_0_114 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c114 bl_0_114 br_0_114 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c114 bl_0_114 br_0_114 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c114 bl_0_114 br_0_114 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c114 bl_0_114 br_0_114 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c114 bl_0_114 br_0_114 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c114 bl_0_114 br_0_114 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c114 bl_0_114 br_0_114 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c114 bl_0_114 br_0_114 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c115 bl_0_115 br_0_115 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c115 bl_0_115 br_0_115 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c115 bl_0_115 br_0_115 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c115 bl_0_115 br_0_115 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c115 bl_0_115 br_0_115 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c115 bl_0_115 br_0_115 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c115 bl_0_115 br_0_115 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c115 bl_0_115 br_0_115 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c115 bl_0_115 br_0_115 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c115 bl_0_115 br_0_115 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c115 bl_0_115 br_0_115 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c115 bl_0_115 br_0_115 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c115 bl_0_115 br_0_115 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c115 bl_0_115 br_0_115 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c115 bl_0_115 br_0_115 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c115 bl_0_115 br_0_115 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c115 bl_0_115 br_0_115 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c115 bl_0_115 br_0_115 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c115 bl_0_115 br_0_115 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c115 bl_0_115 br_0_115 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c115 bl_0_115 br_0_115 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c115 bl_0_115 br_0_115 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c115 bl_0_115 br_0_115 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c115 bl_0_115 br_0_115 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c115 bl_0_115 br_0_115 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c115 bl_0_115 br_0_115 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c115 bl_0_115 br_0_115 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c115 bl_0_115 br_0_115 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c115 bl_0_115 br_0_115 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c115 bl_0_115 br_0_115 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c115 bl_0_115 br_0_115 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c115 bl_0_115 br_0_115 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c115 bl_0_115 br_0_115 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c115 bl_0_115 br_0_115 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c115 bl_0_115 br_0_115 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c115 bl_0_115 br_0_115 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c115 bl_0_115 br_0_115 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c115 bl_0_115 br_0_115 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c115 bl_0_115 br_0_115 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c115 bl_0_115 br_0_115 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c115 bl_0_115 br_0_115 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c115 bl_0_115 br_0_115 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c115 bl_0_115 br_0_115 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c115 bl_0_115 br_0_115 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c115 bl_0_115 br_0_115 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c115 bl_0_115 br_0_115 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c115 bl_0_115 br_0_115 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c115 bl_0_115 br_0_115 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c115 bl_0_115 br_0_115 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c115 bl_0_115 br_0_115 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c115 bl_0_115 br_0_115 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c115 bl_0_115 br_0_115 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c115 bl_0_115 br_0_115 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c115 bl_0_115 br_0_115 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c115 bl_0_115 br_0_115 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c115 bl_0_115 br_0_115 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c115 bl_0_115 br_0_115 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c115 bl_0_115 br_0_115 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c115 bl_0_115 br_0_115 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c115 bl_0_115 br_0_115 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c115 bl_0_115 br_0_115 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c115 bl_0_115 br_0_115 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c115 bl_0_115 br_0_115 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c115 bl_0_115 br_0_115 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c116 bl_0_116 br_0_116 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c116 bl_0_116 br_0_116 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c116 bl_0_116 br_0_116 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c116 bl_0_116 br_0_116 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c116 bl_0_116 br_0_116 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c116 bl_0_116 br_0_116 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c116 bl_0_116 br_0_116 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c116 bl_0_116 br_0_116 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c116 bl_0_116 br_0_116 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c116 bl_0_116 br_0_116 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c116 bl_0_116 br_0_116 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c116 bl_0_116 br_0_116 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c116 bl_0_116 br_0_116 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c116 bl_0_116 br_0_116 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c116 bl_0_116 br_0_116 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c116 bl_0_116 br_0_116 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c116 bl_0_116 br_0_116 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c116 bl_0_116 br_0_116 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c116 bl_0_116 br_0_116 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c116 bl_0_116 br_0_116 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c116 bl_0_116 br_0_116 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c116 bl_0_116 br_0_116 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c116 bl_0_116 br_0_116 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c116 bl_0_116 br_0_116 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c116 bl_0_116 br_0_116 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c116 bl_0_116 br_0_116 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c116 bl_0_116 br_0_116 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c116 bl_0_116 br_0_116 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c116 bl_0_116 br_0_116 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c116 bl_0_116 br_0_116 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c116 bl_0_116 br_0_116 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c116 bl_0_116 br_0_116 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c116 bl_0_116 br_0_116 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c116 bl_0_116 br_0_116 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c116 bl_0_116 br_0_116 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c116 bl_0_116 br_0_116 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c116 bl_0_116 br_0_116 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c116 bl_0_116 br_0_116 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c116 bl_0_116 br_0_116 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c116 bl_0_116 br_0_116 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c116 bl_0_116 br_0_116 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c116 bl_0_116 br_0_116 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c116 bl_0_116 br_0_116 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c116 bl_0_116 br_0_116 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c116 bl_0_116 br_0_116 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c116 bl_0_116 br_0_116 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c116 bl_0_116 br_0_116 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c116 bl_0_116 br_0_116 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c116 bl_0_116 br_0_116 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c116 bl_0_116 br_0_116 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c116 bl_0_116 br_0_116 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c116 bl_0_116 br_0_116 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c116 bl_0_116 br_0_116 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c116 bl_0_116 br_0_116 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c116 bl_0_116 br_0_116 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c116 bl_0_116 br_0_116 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c116 bl_0_116 br_0_116 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c116 bl_0_116 br_0_116 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c116 bl_0_116 br_0_116 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c116 bl_0_116 br_0_116 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c116 bl_0_116 br_0_116 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c116 bl_0_116 br_0_116 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c116 bl_0_116 br_0_116 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c116 bl_0_116 br_0_116 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c117 bl_0_117 br_0_117 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c117 bl_0_117 br_0_117 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c117 bl_0_117 br_0_117 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c117 bl_0_117 br_0_117 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c117 bl_0_117 br_0_117 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c117 bl_0_117 br_0_117 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c117 bl_0_117 br_0_117 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c117 bl_0_117 br_0_117 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c117 bl_0_117 br_0_117 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c117 bl_0_117 br_0_117 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c117 bl_0_117 br_0_117 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c117 bl_0_117 br_0_117 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c117 bl_0_117 br_0_117 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c117 bl_0_117 br_0_117 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c117 bl_0_117 br_0_117 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c117 bl_0_117 br_0_117 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c117 bl_0_117 br_0_117 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c117 bl_0_117 br_0_117 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c117 bl_0_117 br_0_117 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c117 bl_0_117 br_0_117 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c117 bl_0_117 br_0_117 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c117 bl_0_117 br_0_117 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c117 bl_0_117 br_0_117 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c117 bl_0_117 br_0_117 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c117 bl_0_117 br_0_117 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c117 bl_0_117 br_0_117 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c117 bl_0_117 br_0_117 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c117 bl_0_117 br_0_117 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c117 bl_0_117 br_0_117 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c117 bl_0_117 br_0_117 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c117 bl_0_117 br_0_117 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c117 bl_0_117 br_0_117 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c117 bl_0_117 br_0_117 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c117 bl_0_117 br_0_117 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c117 bl_0_117 br_0_117 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c117 bl_0_117 br_0_117 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c117 bl_0_117 br_0_117 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c117 bl_0_117 br_0_117 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c117 bl_0_117 br_0_117 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c117 bl_0_117 br_0_117 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c117 bl_0_117 br_0_117 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c117 bl_0_117 br_0_117 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c117 bl_0_117 br_0_117 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c117 bl_0_117 br_0_117 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c117 bl_0_117 br_0_117 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c117 bl_0_117 br_0_117 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c117 bl_0_117 br_0_117 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c117 bl_0_117 br_0_117 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c117 bl_0_117 br_0_117 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c117 bl_0_117 br_0_117 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c117 bl_0_117 br_0_117 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c117 bl_0_117 br_0_117 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c117 bl_0_117 br_0_117 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c117 bl_0_117 br_0_117 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c117 bl_0_117 br_0_117 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c117 bl_0_117 br_0_117 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c117 bl_0_117 br_0_117 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c117 bl_0_117 br_0_117 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c117 bl_0_117 br_0_117 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c117 bl_0_117 br_0_117 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c117 bl_0_117 br_0_117 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c117 bl_0_117 br_0_117 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c117 bl_0_117 br_0_117 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c117 bl_0_117 br_0_117 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c118 bl_0_118 br_0_118 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c118 bl_0_118 br_0_118 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c118 bl_0_118 br_0_118 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c118 bl_0_118 br_0_118 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c118 bl_0_118 br_0_118 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c118 bl_0_118 br_0_118 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c118 bl_0_118 br_0_118 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c118 bl_0_118 br_0_118 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c118 bl_0_118 br_0_118 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c118 bl_0_118 br_0_118 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c118 bl_0_118 br_0_118 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c118 bl_0_118 br_0_118 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c118 bl_0_118 br_0_118 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c118 bl_0_118 br_0_118 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c118 bl_0_118 br_0_118 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c118 bl_0_118 br_0_118 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c118 bl_0_118 br_0_118 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c118 bl_0_118 br_0_118 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c118 bl_0_118 br_0_118 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c118 bl_0_118 br_0_118 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c118 bl_0_118 br_0_118 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c118 bl_0_118 br_0_118 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c118 bl_0_118 br_0_118 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c118 bl_0_118 br_0_118 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c118 bl_0_118 br_0_118 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c118 bl_0_118 br_0_118 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c118 bl_0_118 br_0_118 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c118 bl_0_118 br_0_118 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c118 bl_0_118 br_0_118 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c118 bl_0_118 br_0_118 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c118 bl_0_118 br_0_118 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c118 bl_0_118 br_0_118 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c118 bl_0_118 br_0_118 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c118 bl_0_118 br_0_118 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c118 bl_0_118 br_0_118 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c118 bl_0_118 br_0_118 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c118 bl_0_118 br_0_118 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c118 bl_0_118 br_0_118 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c118 bl_0_118 br_0_118 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c118 bl_0_118 br_0_118 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c118 bl_0_118 br_0_118 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c118 bl_0_118 br_0_118 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c118 bl_0_118 br_0_118 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c118 bl_0_118 br_0_118 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c118 bl_0_118 br_0_118 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c118 bl_0_118 br_0_118 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c118 bl_0_118 br_0_118 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c118 bl_0_118 br_0_118 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c118 bl_0_118 br_0_118 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c118 bl_0_118 br_0_118 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c118 bl_0_118 br_0_118 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c118 bl_0_118 br_0_118 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c118 bl_0_118 br_0_118 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c118 bl_0_118 br_0_118 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c118 bl_0_118 br_0_118 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c118 bl_0_118 br_0_118 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c118 bl_0_118 br_0_118 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c118 bl_0_118 br_0_118 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c118 bl_0_118 br_0_118 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c118 bl_0_118 br_0_118 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c118 bl_0_118 br_0_118 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c118 bl_0_118 br_0_118 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c118 bl_0_118 br_0_118 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c118 bl_0_118 br_0_118 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c119 bl_0_119 br_0_119 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c119 bl_0_119 br_0_119 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c119 bl_0_119 br_0_119 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c119 bl_0_119 br_0_119 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c119 bl_0_119 br_0_119 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c119 bl_0_119 br_0_119 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c119 bl_0_119 br_0_119 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c119 bl_0_119 br_0_119 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c119 bl_0_119 br_0_119 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c119 bl_0_119 br_0_119 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c119 bl_0_119 br_0_119 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c119 bl_0_119 br_0_119 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c119 bl_0_119 br_0_119 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c119 bl_0_119 br_0_119 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c119 bl_0_119 br_0_119 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c119 bl_0_119 br_0_119 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c119 bl_0_119 br_0_119 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c119 bl_0_119 br_0_119 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c119 bl_0_119 br_0_119 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c119 bl_0_119 br_0_119 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c119 bl_0_119 br_0_119 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c119 bl_0_119 br_0_119 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c119 bl_0_119 br_0_119 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c119 bl_0_119 br_0_119 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c119 bl_0_119 br_0_119 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c119 bl_0_119 br_0_119 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c119 bl_0_119 br_0_119 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c119 bl_0_119 br_0_119 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c119 bl_0_119 br_0_119 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c119 bl_0_119 br_0_119 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c119 bl_0_119 br_0_119 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c119 bl_0_119 br_0_119 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c119 bl_0_119 br_0_119 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c119 bl_0_119 br_0_119 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c119 bl_0_119 br_0_119 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c119 bl_0_119 br_0_119 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c119 bl_0_119 br_0_119 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c119 bl_0_119 br_0_119 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c119 bl_0_119 br_0_119 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c119 bl_0_119 br_0_119 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c119 bl_0_119 br_0_119 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c119 bl_0_119 br_0_119 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c119 bl_0_119 br_0_119 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c119 bl_0_119 br_0_119 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c119 bl_0_119 br_0_119 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c119 bl_0_119 br_0_119 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c119 bl_0_119 br_0_119 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c119 bl_0_119 br_0_119 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c119 bl_0_119 br_0_119 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c119 bl_0_119 br_0_119 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c119 bl_0_119 br_0_119 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c119 bl_0_119 br_0_119 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c119 bl_0_119 br_0_119 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c119 bl_0_119 br_0_119 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c119 bl_0_119 br_0_119 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c119 bl_0_119 br_0_119 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c119 bl_0_119 br_0_119 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c119 bl_0_119 br_0_119 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c119 bl_0_119 br_0_119 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c119 bl_0_119 br_0_119 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c119 bl_0_119 br_0_119 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c119 bl_0_119 br_0_119 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c119 bl_0_119 br_0_119 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c119 bl_0_119 br_0_119 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c120 bl_0_120 br_0_120 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c120 bl_0_120 br_0_120 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c120 bl_0_120 br_0_120 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c120 bl_0_120 br_0_120 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c120 bl_0_120 br_0_120 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c120 bl_0_120 br_0_120 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c120 bl_0_120 br_0_120 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c120 bl_0_120 br_0_120 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c120 bl_0_120 br_0_120 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c120 bl_0_120 br_0_120 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c120 bl_0_120 br_0_120 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c120 bl_0_120 br_0_120 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c120 bl_0_120 br_0_120 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c120 bl_0_120 br_0_120 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c120 bl_0_120 br_0_120 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c120 bl_0_120 br_0_120 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c120 bl_0_120 br_0_120 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c120 bl_0_120 br_0_120 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c120 bl_0_120 br_0_120 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c120 bl_0_120 br_0_120 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c120 bl_0_120 br_0_120 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c120 bl_0_120 br_0_120 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c120 bl_0_120 br_0_120 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c120 bl_0_120 br_0_120 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c120 bl_0_120 br_0_120 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c120 bl_0_120 br_0_120 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c120 bl_0_120 br_0_120 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c120 bl_0_120 br_0_120 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c120 bl_0_120 br_0_120 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c120 bl_0_120 br_0_120 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c120 bl_0_120 br_0_120 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c120 bl_0_120 br_0_120 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c120 bl_0_120 br_0_120 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c120 bl_0_120 br_0_120 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c120 bl_0_120 br_0_120 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c120 bl_0_120 br_0_120 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c120 bl_0_120 br_0_120 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c120 bl_0_120 br_0_120 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c120 bl_0_120 br_0_120 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c120 bl_0_120 br_0_120 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c120 bl_0_120 br_0_120 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c120 bl_0_120 br_0_120 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c120 bl_0_120 br_0_120 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c120 bl_0_120 br_0_120 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c120 bl_0_120 br_0_120 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c120 bl_0_120 br_0_120 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c120 bl_0_120 br_0_120 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c120 bl_0_120 br_0_120 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c120 bl_0_120 br_0_120 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c120 bl_0_120 br_0_120 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c120 bl_0_120 br_0_120 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c120 bl_0_120 br_0_120 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c120 bl_0_120 br_0_120 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c120 bl_0_120 br_0_120 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c120 bl_0_120 br_0_120 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c120 bl_0_120 br_0_120 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c120 bl_0_120 br_0_120 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c120 bl_0_120 br_0_120 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c120 bl_0_120 br_0_120 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c120 bl_0_120 br_0_120 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c120 bl_0_120 br_0_120 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c120 bl_0_120 br_0_120 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c120 bl_0_120 br_0_120 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c120 bl_0_120 br_0_120 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c121 bl_0_121 br_0_121 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c121 bl_0_121 br_0_121 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c121 bl_0_121 br_0_121 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c121 bl_0_121 br_0_121 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c121 bl_0_121 br_0_121 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c121 bl_0_121 br_0_121 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c121 bl_0_121 br_0_121 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c121 bl_0_121 br_0_121 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c121 bl_0_121 br_0_121 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c121 bl_0_121 br_0_121 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c121 bl_0_121 br_0_121 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c121 bl_0_121 br_0_121 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c121 bl_0_121 br_0_121 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c121 bl_0_121 br_0_121 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c121 bl_0_121 br_0_121 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c121 bl_0_121 br_0_121 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c121 bl_0_121 br_0_121 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c121 bl_0_121 br_0_121 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c121 bl_0_121 br_0_121 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c121 bl_0_121 br_0_121 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c121 bl_0_121 br_0_121 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c121 bl_0_121 br_0_121 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c121 bl_0_121 br_0_121 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c121 bl_0_121 br_0_121 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c121 bl_0_121 br_0_121 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c121 bl_0_121 br_0_121 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c121 bl_0_121 br_0_121 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c121 bl_0_121 br_0_121 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c121 bl_0_121 br_0_121 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c121 bl_0_121 br_0_121 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c121 bl_0_121 br_0_121 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c121 bl_0_121 br_0_121 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c121 bl_0_121 br_0_121 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c121 bl_0_121 br_0_121 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c121 bl_0_121 br_0_121 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c121 bl_0_121 br_0_121 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c121 bl_0_121 br_0_121 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c121 bl_0_121 br_0_121 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c121 bl_0_121 br_0_121 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c121 bl_0_121 br_0_121 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c121 bl_0_121 br_0_121 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c121 bl_0_121 br_0_121 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c121 bl_0_121 br_0_121 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c121 bl_0_121 br_0_121 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c121 bl_0_121 br_0_121 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c121 bl_0_121 br_0_121 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c121 bl_0_121 br_0_121 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c121 bl_0_121 br_0_121 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c121 bl_0_121 br_0_121 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c121 bl_0_121 br_0_121 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c121 bl_0_121 br_0_121 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c121 bl_0_121 br_0_121 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c121 bl_0_121 br_0_121 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c121 bl_0_121 br_0_121 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c121 bl_0_121 br_0_121 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c121 bl_0_121 br_0_121 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c121 bl_0_121 br_0_121 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c121 bl_0_121 br_0_121 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c121 bl_0_121 br_0_121 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c121 bl_0_121 br_0_121 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c121 bl_0_121 br_0_121 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c121 bl_0_121 br_0_121 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c121 bl_0_121 br_0_121 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c121 bl_0_121 br_0_121 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c122 bl_0_122 br_0_122 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c122 bl_0_122 br_0_122 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c122 bl_0_122 br_0_122 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c122 bl_0_122 br_0_122 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c122 bl_0_122 br_0_122 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c122 bl_0_122 br_0_122 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c122 bl_0_122 br_0_122 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c122 bl_0_122 br_0_122 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c122 bl_0_122 br_0_122 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c122 bl_0_122 br_0_122 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c122 bl_0_122 br_0_122 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c122 bl_0_122 br_0_122 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c122 bl_0_122 br_0_122 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c122 bl_0_122 br_0_122 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c122 bl_0_122 br_0_122 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c122 bl_0_122 br_0_122 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c122 bl_0_122 br_0_122 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c122 bl_0_122 br_0_122 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c122 bl_0_122 br_0_122 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c122 bl_0_122 br_0_122 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c122 bl_0_122 br_0_122 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c122 bl_0_122 br_0_122 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c122 bl_0_122 br_0_122 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c122 bl_0_122 br_0_122 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c122 bl_0_122 br_0_122 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c122 bl_0_122 br_0_122 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c122 bl_0_122 br_0_122 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c122 bl_0_122 br_0_122 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c122 bl_0_122 br_0_122 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c122 bl_0_122 br_0_122 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c122 bl_0_122 br_0_122 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c122 bl_0_122 br_0_122 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c122 bl_0_122 br_0_122 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c122 bl_0_122 br_0_122 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c122 bl_0_122 br_0_122 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c122 bl_0_122 br_0_122 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c122 bl_0_122 br_0_122 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c122 bl_0_122 br_0_122 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c122 bl_0_122 br_0_122 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c122 bl_0_122 br_0_122 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c122 bl_0_122 br_0_122 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c122 bl_0_122 br_0_122 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c122 bl_0_122 br_0_122 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c122 bl_0_122 br_0_122 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c122 bl_0_122 br_0_122 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c122 bl_0_122 br_0_122 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c122 bl_0_122 br_0_122 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c122 bl_0_122 br_0_122 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c122 bl_0_122 br_0_122 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c122 bl_0_122 br_0_122 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c122 bl_0_122 br_0_122 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c122 bl_0_122 br_0_122 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c122 bl_0_122 br_0_122 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c122 bl_0_122 br_0_122 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c122 bl_0_122 br_0_122 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c122 bl_0_122 br_0_122 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c122 bl_0_122 br_0_122 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c122 bl_0_122 br_0_122 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c122 bl_0_122 br_0_122 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c122 bl_0_122 br_0_122 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c122 bl_0_122 br_0_122 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c122 bl_0_122 br_0_122 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c122 bl_0_122 br_0_122 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c122 bl_0_122 br_0_122 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c123 bl_0_123 br_0_123 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c123 bl_0_123 br_0_123 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c123 bl_0_123 br_0_123 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c123 bl_0_123 br_0_123 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c123 bl_0_123 br_0_123 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c123 bl_0_123 br_0_123 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c123 bl_0_123 br_0_123 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c123 bl_0_123 br_0_123 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c123 bl_0_123 br_0_123 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c123 bl_0_123 br_0_123 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c123 bl_0_123 br_0_123 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c123 bl_0_123 br_0_123 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c123 bl_0_123 br_0_123 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c123 bl_0_123 br_0_123 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c123 bl_0_123 br_0_123 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c123 bl_0_123 br_0_123 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c123 bl_0_123 br_0_123 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c123 bl_0_123 br_0_123 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c123 bl_0_123 br_0_123 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c123 bl_0_123 br_0_123 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c123 bl_0_123 br_0_123 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c123 bl_0_123 br_0_123 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c123 bl_0_123 br_0_123 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c123 bl_0_123 br_0_123 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c123 bl_0_123 br_0_123 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c123 bl_0_123 br_0_123 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c123 bl_0_123 br_0_123 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c123 bl_0_123 br_0_123 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c123 bl_0_123 br_0_123 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c123 bl_0_123 br_0_123 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c123 bl_0_123 br_0_123 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c123 bl_0_123 br_0_123 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c123 bl_0_123 br_0_123 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c123 bl_0_123 br_0_123 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c123 bl_0_123 br_0_123 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c123 bl_0_123 br_0_123 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c123 bl_0_123 br_0_123 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c123 bl_0_123 br_0_123 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c123 bl_0_123 br_0_123 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c123 bl_0_123 br_0_123 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c123 bl_0_123 br_0_123 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c123 bl_0_123 br_0_123 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c123 bl_0_123 br_0_123 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c123 bl_0_123 br_0_123 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c123 bl_0_123 br_0_123 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c123 bl_0_123 br_0_123 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c123 bl_0_123 br_0_123 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c123 bl_0_123 br_0_123 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c123 bl_0_123 br_0_123 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c123 bl_0_123 br_0_123 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c123 bl_0_123 br_0_123 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c123 bl_0_123 br_0_123 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c123 bl_0_123 br_0_123 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c123 bl_0_123 br_0_123 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c123 bl_0_123 br_0_123 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c123 bl_0_123 br_0_123 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c123 bl_0_123 br_0_123 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c123 bl_0_123 br_0_123 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c123 bl_0_123 br_0_123 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c123 bl_0_123 br_0_123 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c123 bl_0_123 br_0_123 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c123 bl_0_123 br_0_123 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c123 bl_0_123 br_0_123 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c123 bl_0_123 br_0_123 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c124 bl_0_124 br_0_124 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c124 bl_0_124 br_0_124 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c124 bl_0_124 br_0_124 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c124 bl_0_124 br_0_124 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c124 bl_0_124 br_0_124 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c124 bl_0_124 br_0_124 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c124 bl_0_124 br_0_124 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c124 bl_0_124 br_0_124 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c124 bl_0_124 br_0_124 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c124 bl_0_124 br_0_124 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c124 bl_0_124 br_0_124 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c124 bl_0_124 br_0_124 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c124 bl_0_124 br_0_124 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c124 bl_0_124 br_0_124 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c124 bl_0_124 br_0_124 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c124 bl_0_124 br_0_124 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c124 bl_0_124 br_0_124 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c124 bl_0_124 br_0_124 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c124 bl_0_124 br_0_124 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c124 bl_0_124 br_0_124 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c124 bl_0_124 br_0_124 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c124 bl_0_124 br_0_124 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c124 bl_0_124 br_0_124 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c124 bl_0_124 br_0_124 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c124 bl_0_124 br_0_124 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c124 bl_0_124 br_0_124 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c124 bl_0_124 br_0_124 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c124 bl_0_124 br_0_124 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c124 bl_0_124 br_0_124 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c124 bl_0_124 br_0_124 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c124 bl_0_124 br_0_124 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c124 bl_0_124 br_0_124 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c124 bl_0_124 br_0_124 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c124 bl_0_124 br_0_124 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c124 bl_0_124 br_0_124 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c124 bl_0_124 br_0_124 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c124 bl_0_124 br_0_124 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c124 bl_0_124 br_0_124 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c124 bl_0_124 br_0_124 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c124 bl_0_124 br_0_124 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c124 bl_0_124 br_0_124 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c124 bl_0_124 br_0_124 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c124 bl_0_124 br_0_124 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c124 bl_0_124 br_0_124 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c124 bl_0_124 br_0_124 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c124 bl_0_124 br_0_124 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c124 bl_0_124 br_0_124 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c124 bl_0_124 br_0_124 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c124 bl_0_124 br_0_124 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c124 bl_0_124 br_0_124 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c124 bl_0_124 br_0_124 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c124 bl_0_124 br_0_124 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c124 bl_0_124 br_0_124 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c124 bl_0_124 br_0_124 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c124 bl_0_124 br_0_124 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c124 bl_0_124 br_0_124 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c124 bl_0_124 br_0_124 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c124 bl_0_124 br_0_124 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c124 bl_0_124 br_0_124 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c124 bl_0_124 br_0_124 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c124 bl_0_124 br_0_124 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c124 bl_0_124 br_0_124 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c124 bl_0_124 br_0_124 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c124 bl_0_124 br_0_124 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c125 bl_0_125 br_0_125 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c125 bl_0_125 br_0_125 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c125 bl_0_125 br_0_125 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c125 bl_0_125 br_0_125 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c125 bl_0_125 br_0_125 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c125 bl_0_125 br_0_125 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c125 bl_0_125 br_0_125 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c125 bl_0_125 br_0_125 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c125 bl_0_125 br_0_125 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c125 bl_0_125 br_0_125 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c125 bl_0_125 br_0_125 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c125 bl_0_125 br_0_125 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c125 bl_0_125 br_0_125 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c125 bl_0_125 br_0_125 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c125 bl_0_125 br_0_125 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c125 bl_0_125 br_0_125 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c125 bl_0_125 br_0_125 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c125 bl_0_125 br_0_125 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c125 bl_0_125 br_0_125 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c125 bl_0_125 br_0_125 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c125 bl_0_125 br_0_125 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c125 bl_0_125 br_0_125 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c125 bl_0_125 br_0_125 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c125 bl_0_125 br_0_125 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c125 bl_0_125 br_0_125 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c125 bl_0_125 br_0_125 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c125 bl_0_125 br_0_125 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c125 bl_0_125 br_0_125 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c125 bl_0_125 br_0_125 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c125 bl_0_125 br_0_125 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c125 bl_0_125 br_0_125 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c125 bl_0_125 br_0_125 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c125 bl_0_125 br_0_125 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c125 bl_0_125 br_0_125 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c125 bl_0_125 br_0_125 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c125 bl_0_125 br_0_125 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c125 bl_0_125 br_0_125 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c125 bl_0_125 br_0_125 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c125 bl_0_125 br_0_125 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c125 bl_0_125 br_0_125 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c125 bl_0_125 br_0_125 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c125 bl_0_125 br_0_125 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c125 bl_0_125 br_0_125 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c125 bl_0_125 br_0_125 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c125 bl_0_125 br_0_125 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c125 bl_0_125 br_0_125 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c125 bl_0_125 br_0_125 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c125 bl_0_125 br_0_125 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c125 bl_0_125 br_0_125 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c125 bl_0_125 br_0_125 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c125 bl_0_125 br_0_125 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c125 bl_0_125 br_0_125 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c125 bl_0_125 br_0_125 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c125 bl_0_125 br_0_125 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c125 bl_0_125 br_0_125 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c125 bl_0_125 br_0_125 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c125 bl_0_125 br_0_125 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c125 bl_0_125 br_0_125 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c125 bl_0_125 br_0_125 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c125 bl_0_125 br_0_125 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c125 bl_0_125 br_0_125 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c125 bl_0_125 br_0_125 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c125 bl_0_125 br_0_125 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c125 bl_0_125 br_0_125 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c126 bl_0_126 br_0_126 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c126 bl_0_126 br_0_126 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c126 bl_0_126 br_0_126 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c126 bl_0_126 br_0_126 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c126 bl_0_126 br_0_126 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c126 bl_0_126 br_0_126 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c126 bl_0_126 br_0_126 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c126 bl_0_126 br_0_126 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c126 bl_0_126 br_0_126 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c126 bl_0_126 br_0_126 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c126 bl_0_126 br_0_126 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c126 bl_0_126 br_0_126 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c126 bl_0_126 br_0_126 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c126 bl_0_126 br_0_126 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c126 bl_0_126 br_0_126 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c126 bl_0_126 br_0_126 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c126 bl_0_126 br_0_126 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c126 bl_0_126 br_0_126 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c126 bl_0_126 br_0_126 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c126 bl_0_126 br_0_126 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c126 bl_0_126 br_0_126 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c126 bl_0_126 br_0_126 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c126 bl_0_126 br_0_126 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c126 bl_0_126 br_0_126 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c126 bl_0_126 br_0_126 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c126 bl_0_126 br_0_126 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c126 bl_0_126 br_0_126 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c126 bl_0_126 br_0_126 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c126 bl_0_126 br_0_126 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c126 bl_0_126 br_0_126 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c126 bl_0_126 br_0_126 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c126 bl_0_126 br_0_126 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c126 bl_0_126 br_0_126 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c126 bl_0_126 br_0_126 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c126 bl_0_126 br_0_126 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c126 bl_0_126 br_0_126 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c126 bl_0_126 br_0_126 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c126 bl_0_126 br_0_126 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c126 bl_0_126 br_0_126 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c126 bl_0_126 br_0_126 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c126 bl_0_126 br_0_126 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c126 bl_0_126 br_0_126 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c126 bl_0_126 br_0_126 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c126 bl_0_126 br_0_126 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c126 bl_0_126 br_0_126 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c126 bl_0_126 br_0_126 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c126 bl_0_126 br_0_126 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c126 bl_0_126 br_0_126 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c126 bl_0_126 br_0_126 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c126 bl_0_126 br_0_126 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c126 bl_0_126 br_0_126 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c126 bl_0_126 br_0_126 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c126 bl_0_126 br_0_126 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c126 bl_0_126 br_0_126 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c126 bl_0_126 br_0_126 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c126 bl_0_126 br_0_126 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c126 bl_0_126 br_0_126 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c126 bl_0_126 br_0_126 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c126 bl_0_126 br_0_126 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c126 bl_0_126 br_0_126 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c126 bl_0_126 br_0_126 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c126 bl_0_126 br_0_126 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c126 bl_0_126 br_0_126 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c126 bl_0_126 br_0_126 wl_0_63 vdd gnd cell_1rw -Xbit_r0_c127 bl_0_127 br_0_127 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c127 bl_0_127 br_0_127 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c127 bl_0_127 br_0_127 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c127 bl_0_127 br_0_127 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c127 bl_0_127 br_0_127 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c127 bl_0_127 br_0_127 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c127 bl_0_127 br_0_127 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c127 bl_0_127 br_0_127 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c127 bl_0_127 br_0_127 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c127 bl_0_127 br_0_127 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c127 bl_0_127 br_0_127 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c127 bl_0_127 br_0_127 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c127 bl_0_127 br_0_127 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c127 bl_0_127 br_0_127 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c127 bl_0_127 br_0_127 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c127 bl_0_127 br_0_127 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c127 bl_0_127 br_0_127 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c127 bl_0_127 br_0_127 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c127 bl_0_127 br_0_127 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c127 bl_0_127 br_0_127 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c127 bl_0_127 br_0_127 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c127 bl_0_127 br_0_127 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c127 bl_0_127 br_0_127 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c127 bl_0_127 br_0_127 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c127 bl_0_127 br_0_127 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c127 bl_0_127 br_0_127 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c127 bl_0_127 br_0_127 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c127 bl_0_127 br_0_127 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c127 bl_0_127 br_0_127 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c127 bl_0_127 br_0_127 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c127 bl_0_127 br_0_127 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c127 bl_0_127 br_0_127 wl_0_31 vdd gnd cell_1rw -Xbit_r32_c127 bl_0_127 br_0_127 wl_0_32 vdd gnd cell_1rw -Xbit_r33_c127 bl_0_127 br_0_127 wl_0_33 vdd gnd cell_1rw -Xbit_r34_c127 bl_0_127 br_0_127 wl_0_34 vdd gnd cell_1rw -Xbit_r35_c127 bl_0_127 br_0_127 wl_0_35 vdd gnd cell_1rw -Xbit_r36_c127 bl_0_127 br_0_127 wl_0_36 vdd gnd cell_1rw -Xbit_r37_c127 bl_0_127 br_0_127 wl_0_37 vdd gnd cell_1rw -Xbit_r38_c127 bl_0_127 br_0_127 wl_0_38 vdd gnd cell_1rw -Xbit_r39_c127 bl_0_127 br_0_127 wl_0_39 vdd gnd cell_1rw -Xbit_r40_c127 bl_0_127 br_0_127 wl_0_40 vdd gnd cell_1rw -Xbit_r41_c127 bl_0_127 br_0_127 wl_0_41 vdd gnd cell_1rw -Xbit_r42_c127 bl_0_127 br_0_127 wl_0_42 vdd gnd cell_1rw -Xbit_r43_c127 bl_0_127 br_0_127 wl_0_43 vdd gnd cell_1rw -Xbit_r44_c127 bl_0_127 br_0_127 wl_0_44 vdd gnd cell_1rw -Xbit_r45_c127 bl_0_127 br_0_127 wl_0_45 vdd gnd cell_1rw -Xbit_r46_c127 bl_0_127 br_0_127 wl_0_46 vdd gnd cell_1rw -Xbit_r47_c127 bl_0_127 br_0_127 wl_0_47 vdd gnd cell_1rw -Xbit_r48_c127 bl_0_127 br_0_127 wl_0_48 vdd gnd cell_1rw -Xbit_r49_c127 bl_0_127 br_0_127 wl_0_49 vdd gnd cell_1rw -Xbit_r50_c127 bl_0_127 br_0_127 wl_0_50 vdd gnd cell_1rw -Xbit_r51_c127 bl_0_127 br_0_127 wl_0_51 vdd gnd cell_1rw -Xbit_r52_c127 bl_0_127 br_0_127 wl_0_52 vdd gnd cell_1rw -Xbit_r53_c127 bl_0_127 br_0_127 wl_0_53 vdd gnd cell_1rw -Xbit_r54_c127 bl_0_127 br_0_127 wl_0_54 vdd gnd cell_1rw -Xbit_r55_c127 bl_0_127 br_0_127 wl_0_55 vdd gnd cell_1rw -Xbit_r56_c127 bl_0_127 br_0_127 wl_0_56 vdd gnd cell_1rw -Xbit_r57_c127 bl_0_127 br_0_127 wl_0_57 vdd gnd cell_1rw -Xbit_r58_c127 bl_0_127 br_0_127 wl_0_58 vdd gnd cell_1rw -Xbit_r59_c127 bl_0_127 br_0_127 wl_0_59 vdd gnd cell_1rw -Xbit_r60_c127 bl_0_127 br_0_127 wl_0_60 vdd gnd cell_1rw -Xbit_r61_c127 bl_0_127 br_0_127 wl_0_61 vdd gnd cell_1rw -Xbit_r62_c127 bl_0_127 br_0_127 wl_0_62 vdd gnd cell_1rw -Xbit_r63_c127 bl_0_127 br_0_127 wl_0_63 vdd gnd cell_1rw -.ENDS bitcell_array - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B bl_0_32:B br_0_32:B bl_0_33:B br_0_33:B bl_0_34:B br_0_34:B bl_0_35:B br_0_35:B bl_0_36:B br_0_36:B bl_0_37:B br_0_37:B bl_0_38:B br_0_38:B bl_0_39:B br_0_39:B bl_0_40:B br_0_40:B bl_0_41:B br_0_41:B bl_0_42:B br_0_42:B bl_0_43:B br_0_43:B bl_0_44:B br_0_44:B bl_0_45:B br_0_45:B bl_0_46:B br_0_46:B bl_0_47:B br_0_47:B bl_0_48:B br_0_48:B bl_0_49:B br_0_49:B bl_0_50:B br_0_50:B bl_0_51:B br_0_51:B bl_0_52:B br_0_52:B bl_0_53:B br_0_53:B bl_0_54:B br_0_54:B bl_0_55:B br_0_55:B bl_0_56:B br_0_56:B bl_0_57:B br_0_57:B bl_0_58:B br_0_58:B bl_0_59:B br_0_59:B bl_0_60:B br_0_60:B bl_0_61:B br_0_61:B bl_0_62:B br_0_62:B bl_0_63:B br_0_63:B bl_0_64:B br_0_64:B bl_0_65:B br_0_65:B bl_0_66:B br_0_66:B bl_0_67:B br_0_67:B bl_0_68:B br_0_68:B bl_0_69:B br_0_69:B bl_0_70:B br_0_70:B bl_0_71:B br_0_71:B bl_0_72:B br_0_72:B bl_0_73:B br_0_73:B bl_0_74:B br_0_74:B bl_0_75:B br_0_75:B bl_0_76:B br_0_76:B bl_0_77:B br_0_77:B bl_0_78:B br_0_78:B bl_0_79:B br_0_79:B bl_0_80:B br_0_80:B bl_0_81:B br_0_81:B bl_0_82:B br_0_82:B bl_0_83:B br_0_83:B bl_0_84:B br_0_84:B bl_0_85:B br_0_85:B bl_0_86:B br_0_86:B bl_0_87:B br_0_87:B bl_0_88:B br_0_88:B bl_0_89:B br_0_89:B bl_0_90:B br_0_90:B bl_0_91:B br_0_91:B bl_0_92:B br_0_92:B bl_0_93:B br_0_93:B bl_0_94:B br_0_94:B bl_0_95:B br_0_95:B bl_0_96:B br_0_96:B bl_0_97:B br_0_97:B bl_0_98:B br_0_98:B bl_0_99:B br_0_99:B bl_0_100:B br_0_100:B bl_0_101:B br_0_101:B bl_0_102:B br_0_102:B bl_0_103:B br_0_103:B bl_0_104:B br_0_104:B bl_0_105:B br_0_105:B bl_0_106:B br_0_106:B bl_0_107:B br_0_107:B bl_0_108:B br_0_108:B bl_0_109:B br_0_109:B bl_0_110:B br_0_110:B bl_0_111:B br_0_111:B bl_0_112:B br_0_112:B bl_0_113:B br_0_113:B bl_0_114:B br_0_114:B bl_0_115:B br_0_115:B bl_0_116:B br_0_116:B bl_0_117:B br_0_117:B bl_0_118:B br_0_118:B bl_0_119:B br_0_119:B bl_0_120:B br_0_120:B bl_0_121:B br_0_121:B bl_0_122:B br_0_122:B bl_0_123:B br_0_123:B bl_0_124:B br_0_124:B bl_0_125:B br_0_125:B bl_0_126:B br_0_126:B bl_0_127:B br_0_127:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I wl_0_35:I wl_0_36:I wl_0_37:I wl_0_38:I wl_0_39:I wl_0_40:I wl_0_41:I wl_0_42:I wl_0_43:I wl_0_44:I wl_0_45:I wl_0_46:I wl_0_47:I wl_0_48:I wl_0_49:I wl_0_50:I wl_0_51:I wl_0_52:I wl_0_53:I wl_0_54:I wl_0_55:I wl_0_56:I wl_0_57:I wl_0_58:I wl_0_59:I wl_0_60:I wl_0_61:I wl_0_62:I wl_0_63:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INOUT : bl_0_32 -* INOUT : br_0_32 -* INOUT : bl_0_33 -* INOUT : br_0_33 -* INOUT : bl_0_34 -* INOUT : br_0_34 -* INOUT : bl_0_35 -* INOUT : br_0_35 -* INOUT : bl_0_36 -* INOUT : br_0_36 -* INOUT : bl_0_37 -* INOUT : br_0_37 -* INOUT : bl_0_38 -* INOUT : br_0_38 -* INOUT : bl_0_39 -* INOUT : br_0_39 -* INOUT : bl_0_40 -* INOUT : br_0_40 -* INOUT : bl_0_41 -* INOUT : br_0_41 -* INOUT : bl_0_42 -* INOUT : br_0_42 -* INOUT : bl_0_43 -* INOUT : br_0_43 -* INOUT : bl_0_44 -* INOUT : br_0_44 -* INOUT : bl_0_45 -* INOUT : br_0_45 -* INOUT : bl_0_46 -* INOUT : br_0_46 -* INOUT : bl_0_47 -* INOUT : br_0_47 -* INOUT : bl_0_48 -* INOUT : br_0_48 -* INOUT : bl_0_49 -* INOUT : br_0_49 -* INOUT : bl_0_50 -* INOUT : br_0_50 -* INOUT : bl_0_51 -* INOUT : br_0_51 -* INOUT : bl_0_52 -* INOUT : br_0_52 -* INOUT : bl_0_53 -* INOUT : br_0_53 -* INOUT : bl_0_54 -* INOUT : br_0_54 -* INOUT : bl_0_55 -* INOUT : br_0_55 -* INOUT : bl_0_56 -* INOUT : br_0_56 -* INOUT : bl_0_57 -* INOUT : br_0_57 -* INOUT : bl_0_58 -* INOUT : br_0_58 -* INOUT : bl_0_59 -* INOUT : br_0_59 -* INOUT : bl_0_60 -* INOUT : br_0_60 -* INOUT : bl_0_61 -* INOUT : br_0_61 -* INOUT : bl_0_62 -* INOUT : br_0_62 -* INOUT : bl_0_63 -* INOUT : br_0_63 -* INOUT : bl_0_64 -* INOUT : br_0_64 -* INOUT : bl_0_65 -* INOUT : br_0_65 -* INOUT : bl_0_66 -* INOUT : br_0_66 -* INOUT : bl_0_67 -* INOUT : br_0_67 -* INOUT : bl_0_68 -* INOUT : br_0_68 -* INOUT : bl_0_69 -* INOUT : br_0_69 -* INOUT : bl_0_70 -* INOUT : br_0_70 -* INOUT : bl_0_71 -* INOUT : br_0_71 -* INOUT : bl_0_72 -* INOUT : br_0_72 -* INOUT : bl_0_73 -* INOUT : br_0_73 -* INOUT : bl_0_74 -* INOUT : br_0_74 -* INOUT : bl_0_75 -* INOUT : br_0_75 -* INOUT : bl_0_76 -* INOUT : br_0_76 -* INOUT : bl_0_77 -* INOUT : br_0_77 -* INOUT : bl_0_78 -* INOUT : br_0_78 -* INOUT : bl_0_79 -* INOUT : br_0_79 -* INOUT : bl_0_80 -* INOUT : br_0_80 -* INOUT : bl_0_81 -* INOUT : br_0_81 -* INOUT : bl_0_82 -* INOUT : br_0_82 -* INOUT : bl_0_83 -* INOUT : br_0_83 -* INOUT : bl_0_84 -* INOUT : br_0_84 -* INOUT : bl_0_85 -* INOUT : br_0_85 -* INOUT : bl_0_86 -* INOUT : br_0_86 -* INOUT : bl_0_87 -* INOUT : br_0_87 -* INOUT : bl_0_88 -* INOUT : br_0_88 -* INOUT : bl_0_89 -* INOUT : br_0_89 -* INOUT : bl_0_90 -* INOUT : br_0_90 -* INOUT : bl_0_91 -* INOUT : br_0_91 -* INOUT : bl_0_92 -* INOUT : br_0_92 -* INOUT : bl_0_93 -* INOUT : br_0_93 -* INOUT : bl_0_94 -* INOUT : br_0_94 -* INOUT : bl_0_95 -* INOUT : br_0_95 -* INOUT : bl_0_96 -* INOUT : br_0_96 -* INOUT : bl_0_97 -* INOUT : br_0_97 -* INOUT : bl_0_98 -* INOUT : br_0_98 -* INOUT : bl_0_99 -* INOUT : br_0_99 -* INOUT : bl_0_100 -* INOUT : br_0_100 -* INOUT : bl_0_101 -* INOUT : br_0_101 -* INOUT : bl_0_102 -* INOUT : br_0_102 -* INOUT : bl_0_103 -* INOUT : br_0_103 -* INOUT : bl_0_104 -* INOUT : br_0_104 -* INOUT : bl_0_105 -* INOUT : br_0_105 -* INOUT : bl_0_106 -* INOUT : br_0_106 -* INOUT : bl_0_107 -* INOUT : br_0_107 -* INOUT : bl_0_108 -* INOUT : br_0_108 -* INOUT : bl_0_109 -* INOUT : br_0_109 -* INOUT : bl_0_110 -* INOUT : br_0_110 -* INOUT : bl_0_111 -* INOUT : br_0_111 -* INOUT : bl_0_112 -* INOUT : br_0_112 -* INOUT : bl_0_113 -* INOUT : br_0_113 -* INOUT : bl_0_114 -* INOUT : br_0_114 -* INOUT : bl_0_115 -* INOUT : br_0_115 -* INOUT : bl_0_116 -* INOUT : br_0_116 -* INOUT : bl_0_117 -* INOUT : br_0_117 -* INOUT : bl_0_118 -* INOUT : br_0_118 -* INOUT : bl_0_119 -* INOUT : br_0_119 -* INOUT : bl_0_120 -* INOUT : br_0_120 -* INOUT : bl_0_121 -* INOUT : br_0_121 -* INOUT : bl_0_122 -* INOUT : br_0_122 -* INOUT : bl_0_123 -* INOUT : br_0_123 -* INOUT : bl_0_124 -* INOUT : br_0_124 -* INOUT : bl_0_125 -* INOUT : br_0_125 -* INOUT : bl_0_126 -* INOUT : br_0_126 -* INOUT : bl_0_127 -* INOUT : br_0_127 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* INPUT : wl_0_35 -* INPUT : wl_0_36 -* INPUT : wl_0_37 -* INPUT : wl_0_38 -* INPUT : wl_0_39 -* INPUT : wl_0_40 -* INPUT : wl_0_41 -* INPUT : wl_0_42 -* INPUT : wl_0_43 -* INPUT : wl_0_44 -* INPUT : wl_0_45 -* INPUT : wl_0_46 -* INPUT : wl_0_47 -* INPUT : wl_0_48 -* INPUT : wl_0_49 -* INPUT : wl_0_50 -* INPUT : wl_0_51 -* INPUT : wl_0_52 -* INPUT : wl_0_53 -* INPUT : wl_0_54 -* INPUT : wl_0_55 -* INPUT : wl_0_56 -* INPUT : wl_0_57 -* INPUT : wl_0_58 -* INPUT : wl_0_59 -* INPUT : wl_0_60 -* INPUT : wl_0_61 -* INPUT : wl_0_62 -* INPUT : wl_0_63 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 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wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 data_32 bl_32 br_32 data_33 bl_33 br_33 data_34 bl_34 br_34 data_35 bl_35 br_35 data_36 bl_36 br_36 data_37 bl_37 br_37 data_38 bl_38 br_38 data_39 bl_39 br_39 data_40 bl_40 br_40 data_41 bl_41 br_41 data_42 bl_42 br_42 data_43 bl_43 br_43 data_44 bl_44 br_44 data_45 bl_45 br_45 data_46 bl_46 br_46 data_47 bl_47 br_47 data_48 bl_48 br_48 data_49 bl_49 br_49 data_50 bl_50 br_50 data_51 bl_51 br_51 data_52 bl_52 br_52 data_53 bl_53 br_53 data_54 bl_54 br_54 data_55 bl_55 br_55 data_56 bl_56 br_56 data_57 bl_57 br_57 data_58 bl_58 br_58 data_59 bl_59 br_59 data_60 bl_60 br_60 data_61 bl_61 br_61 data_62 bl_62 br_62 data_63 bl_63 br_63 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I data_32:O bl_32:I br_32:I data_33:O bl_33:I br_33:I data_34:O bl_34:I br_34:I data_35:O bl_35:I br_35:I data_36:O bl_36:I br_36:I data_37:O bl_37:I br_37:I data_38:O bl_38:I br_38:I data_39:O bl_39:I br_39:I data_40:O bl_40:I br_40:I data_41:O bl_41:I br_41:I data_42:O bl_42:I br_42:I data_43:O bl_43:I br_43:I data_44:O bl_44:I br_44:I data_45:O bl_45:I br_45:I data_46:O bl_46:I br_46:I data_47:O bl_47:I br_47:I data_48:O bl_48:I br_48:I data_49:O bl_49:I br_49:I data_50:O bl_50:I br_50:I data_51:O bl_51:I br_51:I data_52:O bl_52:I br_52:I data_53:O bl_53:I br_53:I data_54:O bl_54:I br_54:I data_55:O bl_55:I br_55:I data_56:O bl_56:I br_56:I data_57:O bl_57:I br_57:I data_58:O bl_58:I br_58:I data_59:O bl_59:I br_59:I data_60:O bl_60:I br_60:I data_61:O bl_61:I br_61:I data_62:O bl_62:I br_62:I data_63:O bl_63:I br_63:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* OUTPUT: data_2 -* INPUT : bl_2 -* INPUT : br_2 -* OUTPUT: data_3 -* INPUT : bl_3 -* INPUT : br_3 -* OUTPUT: data_4 -* INPUT : bl_4 -* INPUT : br_4 -* OUTPUT: data_5 -* INPUT : bl_5 -* INPUT : br_5 -* OUTPUT: data_6 -* INPUT : bl_6 -* INPUT : br_6 -* OUTPUT: data_7 -* INPUT : bl_7 -* INPUT : br_7 -* OUTPUT: data_8 -* INPUT : bl_8 -* INPUT : br_8 -* OUTPUT: data_9 -* INPUT : bl_9 -* INPUT : br_9 -* OUTPUT: data_10 -* INPUT : bl_10 -* INPUT : br_10 -* OUTPUT: data_11 -* INPUT : bl_11 -* INPUT : br_11 -* OUTPUT: data_12 -* INPUT : bl_12 -* INPUT : br_12 -* OUTPUT: data_13 -* INPUT : bl_13 -* INPUT : br_13 -* OUTPUT: data_14 -* INPUT : bl_14 -* INPUT : br_14 -* OUTPUT: data_15 -* INPUT : bl_15 -* INPUT : br_15 -* OUTPUT: data_16 -* INPUT : bl_16 -* INPUT : br_16 -* OUTPUT: data_17 -* INPUT : bl_17 -* INPUT : br_17 -* OUTPUT: data_18 -* INPUT : bl_18 -* INPUT : br_18 -* OUTPUT: data_19 -* INPUT : bl_19 -* INPUT : br_19 -* OUTPUT: data_20 -* INPUT : bl_20 -* INPUT : br_20 -* OUTPUT: data_21 -* INPUT : bl_21 -* INPUT : br_21 -* OUTPUT: data_22 -* INPUT : bl_22 -* INPUT : br_22 -* OUTPUT: data_23 -* INPUT : bl_23 -* INPUT : br_23 -* OUTPUT: data_24 -* INPUT : bl_24 -* INPUT : br_24 -* OUTPUT: data_25 -* INPUT : bl_25 -* INPUT : br_25 -* OUTPUT: data_26 -* INPUT : bl_26 -* INPUT : br_26 -* OUTPUT: data_27 -* INPUT : bl_27 -* INPUT : br_27 -* OUTPUT: data_28 -* INPUT : bl_28 -* INPUT : br_28 -* OUTPUT: data_29 -* INPUT : bl_29 -* INPUT : br_29 -* OUTPUT: data_30 -* INPUT : bl_30 -* INPUT : br_30 -* OUTPUT: data_31 -* INPUT : bl_31 -* INPUT : br_31 -* OUTPUT: data_32 -* INPUT : bl_32 -* INPUT : br_32 -* OUTPUT: data_33 -* INPUT : bl_33 -* INPUT : br_33 -* OUTPUT: data_34 -* INPUT : bl_34 -* INPUT : br_34 -* OUTPUT: data_35 -* INPUT : bl_35 -* INPUT : br_35 -* OUTPUT: data_36 -* INPUT : bl_36 -* INPUT : br_36 -* OUTPUT: data_37 -* INPUT : bl_37 -* INPUT : br_37 -* OUTPUT: data_38 -* INPUT : bl_38 -* INPUT : br_38 -* OUTPUT: data_39 -* INPUT : bl_39 -* INPUT : br_39 -* OUTPUT: data_40 -* INPUT : bl_40 -* INPUT : br_40 -* OUTPUT: data_41 -* INPUT : bl_41 -* INPUT : br_41 -* OUTPUT: data_42 -* INPUT : bl_42 -* INPUT : br_42 -* OUTPUT: data_43 -* INPUT : bl_43 -* INPUT : br_43 -* OUTPUT: data_44 -* INPUT : bl_44 -* INPUT : br_44 -* OUTPUT: data_45 -* INPUT : bl_45 -* INPUT : br_45 -* OUTPUT: data_46 -* INPUT : bl_46 -* INPUT : br_46 -* OUTPUT: data_47 -* INPUT : bl_47 -* INPUT : br_47 -* OUTPUT: data_48 -* INPUT : bl_48 -* INPUT : br_48 -* OUTPUT: data_49 -* INPUT : bl_49 -* INPUT : br_49 -* OUTPUT: data_50 -* INPUT : bl_50 -* INPUT : br_50 -* OUTPUT: data_51 -* INPUT : bl_51 -* INPUT : br_51 -* OUTPUT: data_52 -* INPUT : bl_52 -* INPUT : br_52 -* OUTPUT: data_53 -* INPUT : bl_53 -* INPUT : br_53 -* OUTPUT: data_54 -* INPUT : bl_54 -* INPUT : br_54 -* OUTPUT: data_55 -* INPUT : bl_55 -* INPUT : br_55 -* OUTPUT: data_56 -* INPUT : bl_56 -* INPUT : br_56 -* OUTPUT: data_57 -* INPUT : bl_57 -* INPUT : br_57 -* OUTPUT: data_58 -* INPUT : bl_58 -* INPUT : br_58 -* OUTPUT: data_59 -* INPUT : bl_59 -* INPUT : br_59 -* OUTPUT: data_60 -* INPUT : bl_60 -* INPUT : br_60 -* OUTPUT: data_61 -* INPUT : bl_61 -* INPUT : br_61 -* OUTPUT: data_62 -* INPUT : bl_62 -* INPUT : br_62 -* OUTPUT: data_63 -* INPUT : bl_63 -* INPUT : br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 2 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp -Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp -Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp -Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp -Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp -Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp -Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp -Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp -Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp -Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp -Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp -Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp -Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp -Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp -Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp -Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp -Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp -Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp -Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp -Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp -Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp -Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp -Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp -Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp -Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp -Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp -Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp -Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp -Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp -Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp -Xsa_d32 bl_32 br_32 data_32 en vdd gnd sense_amp -Xsa_d33 bl_33 br_33 data_33 en vdd gnd sense_amp -Xsa_d34 bl_34 br_34 data_34 en vdd gnd sense_amp -Xsa_d35 bl_35 br_35 data_35 en vdd gnd sense_amp -Xsa_d36 bl_36 br_36 data_36 en vdd gnd sense_amp -Xsa_d37 bl_37 br_37 data_37 en vdd gnd sense_amp -Xsa_d38 bl_38 br_38 data_38 en vdd gnd sense_amp -Xsa_d39 bl_39 br_39 data_39 en vdd gnd sense_amp -Xsa_d40 bl_40 br_40 data_40 en vdd gnd sense_amp -Xsa_d41 bl_41 br_41 data_41 en vdd gnd sense_amp -Xsa_d42 bl_42 br_42 data_42 en vdd gnd sense_amp -Xsa_d43 bl_43 br_43 data_43 en vdd gnd sense_amp -Xsa_d44 bl_44 br_44 data_44 en vdd gnd sense_amp -Xsa_d45 bl_45 br_45 data_45 en vdd gnd sense_amp -Xsa_d46 bl_46 br_46 data_46 en vdd gnd sense_amp -Xsa_d47 bl_47 br_47 data_47 en vdd gnd sense_amp -Xsa_d48 bl_48 br_48 data_48 en vdd gnd sense_amp -Xsa_d49 bl_49 br_49 data_49 en vdd gnd sense_amp -Xsa_d50 bl_50 br_50 data_50 en vdd gnd sense_amp -Xsa_d51 bl_51 br_51 data_51 en vdd gnd sense_amp -Xsa_d52 bl_52 br_52 data_52 en vdd gnd sense_amp -Xsa_d53 bl_53 br_53 data_53 en vdd gnd sense_amp -Xsa_d54 bl_54 br_54 data_54 en vdd gnd sense_amp -Xsa_d55 bl_55 br_55 data_55 en vdd gnd sense_amp -Xsa_d56 bl_56 br_56 data_56 en vdd gnd sense_amp -Xsa_d57 bl_57 br_57 data_57 en vdd gnd sense_amp -Xsa_d58 bl_58 br_58 data_58 en vdd gnd sense_amp -Xsa_d59 bl_59 br_59 data_59 en vdd gnd sense_amp -Xsa_d60 bl_60 br_60 data_60 en vdd gnd sense_amp -Xsa_d61 bl_61 br_61 data_61 en vdd gnd sense_amp -Xsa_d62 bl_62 br_62 data_62 en vdd gnd sense_amp -Xsa_d63 bl_63 br_63 data_63 en vdd gnd sense_amp -.ENDS sense_amp_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 bl_128 br_128 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O bl_64:O br_64:O bl_65:O br_65:O bl_66:O br_66:O bl_67:O br_67:O bl_68:O br_68:O bl_69:O br_69:O bl_70:O br_70:O bl_71:O br_71:O bl_72:O br_72:O bl_73:O br_73:O bl_74:O br_74:O bl_75:O br_75:O bl_76:O br_76:O bl_77:O br_77:O bl_78:O br_78:O bl_79:O br_79:O bl_80:O br_80:O bl_81:O br_81:O bl_82:O br_82:O bl_83:O br_83:O bl_84:O br_84:O bl_85:O br_85:O bl_86:O br_86:O bl_87:O br_87:O bl_88:O br_88:O bl_89:O br_89:O bl_90:O br_90:O bl_91:O br_91:O bl_92:O br_92:O bl_93:O br_93:O bl_94:O br_94:O bl_95:O br_95:O bl_96:O br_96:O bl_97:O br_97:O bl_98:O br_98:O bl_99:O br_99:O bl_100:O br_100:O bl_101:O br_101:O bl_102:O br_102:O bl_103:O br_103:O bl_104:O br_104:O bl_105:O br_105:O bl_106:O br_106:O bl_107:O br_107:O bl_108:O br_108:O bl_109:O br_109:O bl_110:O br_110:O bl_111:O br_111:O bl_112:O br_112:O bl_113:O br_113:O bl_114:O br_114:O bl_115:O br_115:O bl_116:O br_116:O bl_117:O br_117:O bl_118:O br_118:O bl_119:O br_119:O bl_120:O br_120:O bl_121:O br_121:O bl_122:O br_122:O bl_123:O br_123:O bl_124:O br_124:O bl_125:O br_125:O bl_126:O br_126:O bl_127:O br_127:O bl_128:O br_128:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* OUTPUT: bl_64 -* OUTPUT: br_64 -* OUTPUT: bl_65 -* OUTPUT: br_65 -* OUTPUT: bl_66 -* OUTPUT: br_66 -* OUTPUT: bl_67 -* OUTPUT: br_67 -* OUTPUT: bl_68 -* OUTPUT: br_68 -* OUTPUT: bl_69 -* OUTPUT: br_69 -* OUTPUT: bl_70 -* OUTPUT: br_70 -* OUTPUT: bl_71 -* OUTPUT: br_71 -* OUTPUT: bl_72 -* OUTPUT: br_72 -* OUTPUT: bl_73 -* OUTPUT: br_73 -* OUTPUT: bl_74 -* OUTPUT: br_74 -* OUTPUT: bl_75 -* OUTPUT: br_75 -* OUTPUT: bl_76 -* OUTPUT: br_76 -* OUTPUT: bl_77 -* OUTPUT: br_77 -* OUTPUT: bl_78 -* OUTPUT: br_78 -* OUTPUT: bl_79 -* OUTPUT: br_79 -* OUTPUT: bl_80 -* OUTPUT: br_80 -* OUTPUT: bl_81 -* OUTPUT: br_81 -* OUTPUT: bl_82 -* OUTPUT: br_82 -* OUTPUT: bl_83 -* OUTPUT: br_83 -* OUTPUT: bl_84 -* OUTPUT: br_84 -* OUTPUT: bl_85 -* OUTPUT: br_85 -* OUTPUT: bl_86 -* OUTPUT: br_86 -* OUTPUT: bl_87 -* OUTPUT: br_87 -* OUTPUT: bl_88 -* OUTPUT: br_88 -* OUTPUT: bl_89 -* OUTPUT: br_89 -* OUTPUT: bl_90 -* OUTPUT: br_90 -* OUTPUT: bl_91 -* OUTPUT: br_91 -* OUTPUT: bl_92 -* OUTPUT: br_92 -* OUTPUT: bl_93 -* OUTPUT: br_93 -* OUTPUT: bl_94 -* OUTPUT: br_94 -* OUTPUT: bl_95 -* OUTPUT: br_95 -* OUTPUT: bl_96 -* OUTPUT: br_96 -* OUTPUT: bl_97 -* OUTPUT: br_97 -* OUTPUT: bl_98 -* OUTPUT: br_98 -* OUTPUT: bl_99 -* OUTPUT: br_99 -* OUTPUT: bl_100 -* OUTPUT: br_100 -* OUTPUT: bl_101 -* OUTPUT: br_101 -* OUTPUT: bl_102 -* OUTPUT: br_102 -* OUTPUT: bl_103 -* OUTPUT: br_103 -* OUTPUT: bl_104 -* OUTPUT: br_104 -* OUTPUT: bl_105 -* OUTPUT: br_105 -* OUTPUT: bl_106 -* OUTPUT: br_106 -* OUTPUT: bl_107 -* OUTPUT: br_107 -* OUTPUT: bl_108 -* OUTPUT: br_108 -* OUTPUT: bl_109 -* OUTPUT: br_109 -* OUTPUT: bl_110 -* OUTPUT: br_110 -* OUTPUT: bl_111 -* OUTPUT: br_111 -* OUTPUT: bl_112 -* OUTPUT: br_112 -* OUTPUT: bl_113 -* OUTPUT: br_113 -* OUTPUT: bl_114 -* OUTPUT: br_114 -* OUTPUT: bl_115 -* OUTPUT: br_115 -* OUTPUT: bl_116 -* OUTPUT: br_116 -* OUTPUT: bl_117 -* OUTPUT: br_117 -* OUTPUT: bl_118 -* OUTPUT: br_118 -* OUTPUT: bl_119 -* OUTPUT: br_119 -* OUTPUT: bl_120 -* OUTPUT: br_120 -* OUTPUT: bl_121 -* OUTPUT: br_121 -* OUTPUT: bl_122 -* OUTPUT: br_122 -* OUTPUT: bl_123 -* OUTPUT: br_123 -* OUTPUT: bl_124 -* OUTPUT: br_124 -* OUTPUT: bl_125 -* OUTPUT: br_125 -* OUTPUT: bl_126 -* OUTPUT: br_126 -* OUTPUT: bl_127 -* OUTPUT: br_127 -* OUTPUT: bl_128 -* OUTPUT: br_128 -* INPUT : en_bar -* POWER : vdd -* cols: 129 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 -Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 -Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 -Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 -Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 -Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 -Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 -Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 -Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 -Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 -Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 -Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 -Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 -Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 -Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 -Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 -Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 -Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 -Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 -Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 -Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 -Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 -Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 -Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 -Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 -Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 -Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 -Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 -Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 -Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 -Xpre_column_33 bl_33 br_33 en_bar vdd precharge_0 -Xpre_column_34 bl_34 br_34 en_bar vdd precharge_0 -Xpre_column_35 bl_35 br_35 en_bar vdd precharge_0 -Xpre_column_36 bl_36 br_36 en_bar vdd precharge_0 -Xpre_column_37 bl_37 br_37 en_bar vdd precharge_0 -Xpre_column_38 bl_38 br_38 en_bar vdd precharge_0 -Xpre_column_39 bl_39 br_39 en_bar vdd precharge_0 -Xpre_column_40 bl_40 br_40 en_bar vdd precharge_0 -Xpre_column_41 bl_41 br_41 en_bar vdd precharge_0 -Xpre_column_42 bl_42 br_42 en_bar vdd precharge_0 -Xpre_column_43 bl_43 br_43 en_bar vdd precharge_0 -Xpre_column_44 bl_44 br_44 en_bar vdd precharge_0 -Xpre_column_45 bl_45 br_45 en_bar vdd precharge_0 -Xpre_column_46 bl_46 br_46 en_bar vdd precharge_0 -Xpre_column_47 bl_47 br_47 en_bar vdd precharge_0 -Xpre_column_48 bl_48 br_48 en_bar vdd precharge_0 -Xpre_column_49 bl_49 br_49 en_bar vdd precharge_0 -Xpre_column_50 bl_50 br_50 en_bar vdd precharge_0 -Xpre_column_51 bl_51 br_51 en_bar vdd precharge_0 -Xpre_column_52 bl_52 br_52 en_bar vdd precharge_0 -Xpre_column_53 bl_53 br_53 en_bar vdd precharge_0 -Xpre_column_54 bl_54 br_54 en_bar vdd precharge_0 -Xpre_column_55 bl_55 br_55 en_bar vdd precharge_0 -Xpre_column_56 bl_56 br_56 en_bar vdd precharge_0 -Xpre_column_57 bl_57 br_57 en_bar vdd precharge_0 -Xpre_column_58 bl_58 br_58 en_bar vdd precharge_0 -Xpre_column_59 bl_59 br_59 en_bar vdd precharge_0 -Xpre_column_60 bl_60 br_60 en_bar vdd precharge_0 -Xpre_column_61 bl_61 br_61 en_bar vdd precharge_0 -Xpre_column_62 bl_62 br_62 en_bar vdd precharge_0 -Xpre_column_63 bl_63 br_63 en_bar vdd precharge_0 -Xpre_column_64 bl_64 br_64 en_bar vdd precharge_0 -Xpre_column_65 bl_65 br_65 en_bar vdd precharge_0 -Xpre_column_66 bl_66 br_66 en_bar vdd precharge_0 -Xpre_column_67 bl_67 br_67 en_bar vdd precharge_0 -Xpre_column_68 bl_68 br_68 en_bar vdd precharge_0 -Xpre_column_69 bl_69 br_69 en_bar vdd precharge_0 -Xpre_column_70 bl_70 br_70 en_bar vdd precharge_0 -Xpre_column_71 bl_71 br_71 en_bar vdd precharge_0 -Xpre_column_72 bl_72 br_72 en_bar vdd precharge_0 -Xpre_column_73 bl_73 br_73 en_bar vdd precharge_0 -Xpre_column_74 bl_74 br_74 en_bar vdd precharge_0 -Xpre_column_75 bl_75 br_75 en_bar vdd precharge_0 -Xpre_column_76 bl_76 br_76 en_bar vdd precharge_0 -Xpre_column_77 bl_77 br_77 en_bar vdd precharge_0 -Xpre_column_78 bl_78 br_78 en_bar vdd precharge_0 -Xpre_column_79 bl_79 br_79 en_bar vdd precharge_0 -Xpre_column_80 bl_80 br_80 en_bar vdd precharge_0 -Xpre_column_81 bl_81 br_81 en_bar vdd precharge_0 -Xpre_column_82 bl_82 br_82 en_bar vdd precharge_0 -Xpre_column_83 bl_83 br_83 en_bar vdd precharge_0 -Xpre_column_84 bl_84 br_84 en_bar vdd precharge_0 -Xpre_column_85 bl_85 br_85 en_bar vdd precharge_0 -Xpre_column_86 bl_86 br_86 en_bar vdd precharge_0 -Xpre_column_87 bl_87 br_87 en_bar vdd precharge_0 -Xpre_column_88 bl_88 br_88 en_bar vdd precharge_0 -Xpre_column_89 bl_89 br_89 en_bar vdd precharge_0 -Xpre_column_90 bl_90 br_90 en_bar vdd precharge_0 -Xpre_column_91 bl_91 br_91 en_bar vdd precharge_0 -Xpre_column_92 bl_92 br_92 en_bar vdd precharge_0 -Xpre_column_93 bl_93 br_93 en_bar vdd precharge_0 -Xpre_column_94 bl_94 br_94 en_bar vdd precharge_0 -Xpre_column_95 bl_95 br_95 en_bar vdd precharge_0 -Xpre_column_96 bl_96 br_96 en_bar vdd precharge_0 -Xpre_column_97 bl_97 br_97 en_bar vdd precharge_0 -Xpre_column_98 bl_98 br_98 en_bar vdd precharge_0 -Xpre_column_99 bl_99 br_99 en_bar vdd precharge_0 -Xpre_column_100 bl_100 br_100 en_bar vdd precharge_0 -Xpre_column_101 bl_101 br_101 en_bar vdd precharge_0 -Xpre_column_102 bl_102 br_102 en_bar vdd precharge_0 -Xpre_column_103 bl_103 br_103 en_bar vdd precharge_0 -Xpre_column_104 bl_104 br_104 en_bar vdd precharge_0 -Xpre_column_105 bl_105 br_105 en_bar vdd precharge_0 -Xpre_column_106 bl_106 br_106 en_bar vdd precharge_0 -Xpre_column_107 bl_107 br_107 en_bar vdd precharge_0 -Xpre_column_108 bl_108 br_108 en_bar vdd precharge_0 -Xpre_column_109 bl_109 br_109 en_bar vdd precharge_0 -Xpre_column_110 bl_110 br_110 en_bar vdd precharge_0 -Xpre_column_111 bl_111 br_111 en_bar vdd precharge_0 -Xpre_column_112 bl_112 br_112 en_bar vdd precharge_0 -Xpre_column_113 bl_113 br_113 en_bar vdd precharge_0 -Xpre_column_114 bl_114 br_114 en_bar vdd precharge_0 -Xpre_column_115 bl_115 br_115 en_bar vdd precharge_0 -Xpre_column_116 bl_116 br_116 en_bar vdd precharge_0 -Xpre_column_117 bl_117 br_117 en_bar vdd precharge_0 -Xpre_column_118 bl_118 br_118 en_bar vdd precharge_0 -Xpre_column_119 bl_119 br_119 en_bar vdd precharge_0 -Xpre_column_120 bl_120 br_120 en_bar vdd precharge_0 -Xpre_column_121 bl_121 br_121 en_bar vdd precharge_0 -Xpre_column_122 bl_122 br_122 en_bar vdd precharge_0 -Xpre_column_123 bl_123 br_123 en_bar vdd precharge_0 -Xpre_column_124 bl_124 br_124 en_bar vdd precharge_0 -Xpre_column_125 bl_125 br_125 en_bar vdd precharge_0 -Xpre_column_126 bl_126 br_126 en_bar vdd precharge_0 -Xpre_column_127 bl_127 br_127 en_bar vdd precharge_0 -Xpre_column_128 bl_128 br_128 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 data_32 data_33 data_34 data_35 data_36 data_37 data_38 data_39 data_40 data_41 data_42 data_43 data_44 data_45 data_46 data_47 data_48 data_49 data_50 data_51 data_52 data_53 data_54 data_55 data_56 data_57 data_58 data_59 data_60 data_61 data_62 data_63 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 en vdd gnd -*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I data_32:I data_33:I data_34:I data_35:I data_36:I data_37:I data_38:I data_39:I data_40:I data_41:I data_42:I data_43:I data_44:I data_45:I data_46:I data_47:I data_48:I data_49:I data_50:I data_51:I data_52:I data_53:I data_54:I data_55:I data_56:I data_57:I data_58:I data_59:I data_60:I data_61:I data_62:I data_63:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O bl_33:O br_33:O bl_34:O br_34:O bl_35:O br_35:O bl_36:O br_36:O bl_37:O br_37:O bl_38:O br_38:O bl_39:O br_39:O bl_40:O br_40:O bl_41:O br_41:O bl_42:O br_42:O bl_43:O br_43:O bl_44:O br_44:O bl_45:O br_45:O bl_46:O br_46:O bl_47:O br_47:O bl_48:O br_48:O bl_49:O br_49:O bl_50:O br_50:O bl_51:O br_51:O bl_52:O br_52:O bl_53:O br_53:O bl_54:O br_54:O bl_55:O br_55:O bl_56:O br_56:O bl_57:O br_57:O bl_58:O br_58:O bl_59:O br_59:O bl_60:O br_60:O bl_61:O br_61:O bl_62:O br_62:O bl_63:O br_63:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* INPUT : data_2 -* INPUT : data_3 -* INPUT : data_4 -* INPUT : data_5 -* INPUT : data_6 -* INPUT : data_7 -* INPUT : data_8 -* INPUT : data_9 -* INPUT : data_10 -* INPUT : data_11 -* INPUT : data_12 -* INPUT : data_13 -* INPUT : data_14 -* INPUT : data_15 -* INPUT : data_16 -* INPUT : data_17 -* INPUT : data_18 -* INPUT : data_19 -* INPUT : data_20 -* INPUT : data_21 -* INPUT : data_22 -* INPUT : data_23 -* INPUT : data_24 -* INPUT : data_25 -* INPUT : data_26 -* INPUT : data_27 -* INPUT : data_28 -* INPUT : data_29 -* INPUT : data_30 -* INPUT : data_31 -* INPUT : data_32 -* INPUT : data_33 -* INPUT : data_34 -* INPUT : data_35 -* INPUT : data_36 -* INPUT : data_37 -* INPUT : data_38 -* INPUT : data_39 -* INPUT : data_40 -* INPUT : data_41 -* INPUT : data_42 -* INPUT : data_43 -* INPUT : data_44 -* INPUT : data_45 -* INPUT : data_46 -* INPUT : data_47 -* INPUT : data_48 -* INPUT : data_49 -* INPUT : data_50 -* INPUT : data_51 -* INPUT : data_52 -* INPUT : data_53 -* INPUT : data_54 -* INPUT : data_55 -* INPUT : data_56 -* INPUT : data_57 -* INPUT : data_58 -* INPUT : data_59 -* INPUT : data_60 -* INPUT : data_61 -* INPUT : data_62 -* INPUT : data_63 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* OUTPUT: bl_33 -* OUTPUT: br_33 -* OUTPUT: bl_34 -* OUTPUT: br_34 -* OUTPUT: bl_35 -* OUTPUT: br_35 -* OUTPUT: bl_36 -* OUTPUT: br_36 -* OUTPUT: bl_37 -* OUTPUT: br_37 -* OUTPUT: bl_38 -* OUTPUT: br_38 -* OUTPUT: bl_39 -* OUTPUT: br_39 -* OUTPUT: bl_40 -* OUTPUT: br_40 -* OUTPUT: bl_41 -* OUTPUT: br_41 -* OUTPUT: bl_42 -* OUTPUT: br_42 -* OUTPUT: bl_43 -* OUTPUT: br_43 -* OUTPUT: bl_44 -* OUTPUT: br_44 -* OUTPUT: bl_45 -* OUTPUT: br_45 -* OUTPUT: bl_46 -* OUTPUT: br_46 -* OUTPUT: bl_47 -* OUTPUT: br_47 -* OUTPUT: bl_48 -* OUTPUT: br_48 -* OUTPUT: bl_49 -* OUTPUT: br_49 -* OUTPUT: bl_50 -* OUTPUT: br_50 -* OUTPUT: bl_51 -* OUTPUT: br_51 -* OUTPUT: bl_52 -* OUTPUT: br_52 -* OUTPUT: bl_53 -* OUTPUT: br_53 -* OUTPUT: bl_54 -* OUTPUT: br_54 -* OUTPUT: bl_55 -* OUTPUT: br_55 -* OUTPUT: bl_56 -* OUTPUT: br_56 -* OUTPUT: bl_57 -* OUTPUT: br_57 -* OUTPUT: bl_58 -* OUTPUT: br_58 -* OUTPUT: bl_59 -* OUTPUT: br_59 -* OUTPUT: bl_60 -* OUTPUT: br_60 -* OUTPUT: bl_61 -* OUTPUT: br_61 -* OUTPUT: bl_62 -* OUTPUT: br_62 -* OUTPUT: bl_63 -* OUTPUT: br_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 64 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver2 data_1 bl_1 br_1 en vdd gnd write_driver -Xwrite_driver4 data_2 bl_2 br_2 en vdd gnd write_driver -Xwrite_driver6 data_3 bl_3 br_3 en vdd gnd write_driver -Xwrite_driver8 data_4 bl_4 br_4 en vdd gnd write_driver -Xwrite_driver10 data_5 bl_5 br_5 en vdd gnd write_driver -Xwrite_driver12 data_6 bl_6 br_6 en vdd gnd write_driver -Xwrite_driver14 data_7 bl_7 br_7 en vdd gnd write_driver -Xwrite_driver16 data_8 bl_8 br_8 en vdd gnd write_driver -Xwrite_driver18 data_9 bl_9 br_9 en vdd gnd write_driver -Xwrite_driver20 data_10 bl_10 br_10 en vdd gnd write_driver -Xwrite_driver22 data_11 bl_11 br_11 en vdd gnd write_driver -Xwrite_driver24 data_12 bl_12 br_12 en vdd gnd write_driver -Xwrite_driver26 data_13 bl_13 br_13 en vdd gnd write_driver -Xwrite_driver28 data_14 bl_14 br_14 en vdd gnd write_driver -Xwrite_driver30 data_15 bl_15 br_15 en vdd gnd write_driver -Xwrite_driver32 data_16 bl_16 br_16 en vdd gnd write_driver -Xwrite_driver34 data_17 bl_17 br_17 en vdd gnd write_driver -Xwrite_driver36 data_18 bl_18 br_18 en vdd gnd write_driver -Xwrite_driver38 data_19 bl_19 br_19 en vdd gnd write_driver -Xwrite_driver40 data_20 bl_20 br_20 en vdd gnd write_driver -Xwrite_driver42 data_21 bl_21 br_21 en vdd gnd write_driver -Xwrite_driver44 data_22 bl_22 br_22 en vdd gnd write_driver -Xwrite_driver46 data_23 bl_23 br_23 en vdd gnd write_driver -Xwrite_driver48 data_24 bl_24 br_24 en vdd gnd write_driver -Xwrite_driver50 data_25 bl_25 br_25 en vdd gnd write_driver -Xwrite_driver52 data_26 bl_26 br_26 en vdd gnd write_driver -Xwrite_driver54 data_27 bl_27 br_27 en vdd gnd write_driver -Xwrite_driver56 data_28 bl_28 br_28 en vdd gnd write_driver -Xwrite_driver58 data_29 bl_29 br_29 en vdd gnd write_driver -Xwrite_driver60 data_30 bl_30 br_30 en vdd gnd write_driver -Xwrite_driver62 data_31 bl_31 br_31 en vdd gnd write_driver -Xwrite_driver64 data_32 bl_32 br_32 en vdd gnd write_driver -Xwrite_driver66 data_33 bl_33 br_33 en vdd gnd write_driver -Xwrite_driver68 data_34 bl_34 br_34 en vdd gnd write_driver -Xwrite_driver70 data_35 bl_35 br_35 en vdd gnd write_driver -Xwrite_driver72 data_36 bl_36 br_36 en vdd gnd write_driver -Xwrite_driver74 data_37 bl_37 br_37 en vdd gnd write_driver -Xwrite_driver76 data_38 bl_38 br_38 en vdd gnd write_driver -Xwrite_driver78 data_39 bl_39 br_39 en vdd gnd write_driver -Xwrite_driver80 data_40 bl_40 br_40 en vdd gnd write_driver -Xwrite_driver82 data_41 bl_41 br_41 en vdd gnd write_driver -Xwrite_driver84 data_42 bl_42 br_42 en vdd gnd write_driver -Xwrite_driver86 data_43 bl_43 br_43 en vdd gnd write_driver -Xwrite_driver88 data_44 bl_44 br_44 en vdd gnd write_driver -Xwrite_driver90 data_45 bl_45 br_45 en vdd gnd write_driver -Xwrite_driver92 data_46 bl_46 br_46 en vdd gnd write_driver -Xwrite_driver94 data_47 bl_47 br_47 en vdd gnd write_driver -Xwrite_driver96 data_48 bl_48 br_48 en vdd gnd write_driver -Xwrite_driver98 data_49 bl_49 br_49 en vdd gnd write_driver -Xwrite_driver100 data_50 bl_50 br_50 en vdd gnd write_driver -Xwrite_driver102 data_51 bl_51 br_51 en vdd gnd write_driver -Xwrite_driver104 data_52 bl_52 br_52 en vdd gnd write_driver -Xwrite_driver106 data_53 bl_53 br_53 en vdd gnd write_driver -Xwrite_driver108 data_54 bl_54 br_54 en vdd gnd write_driver -Xwrite_driver110 data_55 bl_55 br_55 en vdd gnd write_driver -Xwrite_driver112 data_56 bl_56 br_56 en vdd gnd write_driver -Xwrite_driver114 data_57 bl_57 br_57 en vdd gnd write_driver -Xwrite_driver116 data_58 bl_58 br_58 en vdd gnd write_driver -Xwrite_driver118 data_59 bl_59 br_59 en vdd gnd write_driver -Xwrite_driver120 data_60 bl_60 br_60 en vdd gnd write_driver -Xwrite_driver122 data_61 bl_61 br_61 en vdd gnd write_driver -Xwrite_driver124 data_62 bl_62 br_62 en vdd gnd write_driver -Xwrite_driver126 data_63 bl_63 br_63 en vdd gnd write_driver -.ENDS write_driver_array - -* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -.SUBCKT column_mux bl br bl_out br_out sel gnd -*.PININFO bl:B br:B bl_out:B br_out:B sel:B gnd:B -* INOUT : bl -* INOUT : br -* INOUT : bl_out -* INOUT : br_out -* INOUT : sel -* INOUT : gnd -Mmux_tx1 bl sel bl_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mmux_tx2 br sel br_out gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -.ENDS column_mux - -.SUBCKT column_mux_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd -*.PININFO bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B sel_0:B sel_1:B bl_out_0:B br_out_0:B bl_out_1:B br_out_1:B bl_out_2:B br_out_2:B bl_out_3:B br_out_3:B bl_out_4:B br_out_4:B bl_out_5:B br_out_5:B bl_out_6:B br_out_6:B bl_out_7:B br_out_7:B bl_out_8:B br_out_8:B bl_out_9:B br_out_9:B bl_out_10:B br_out_10:B bl_out_11:B br_out_11:B bl_out_12:B br_out_12:B bl_out_13:B br_out_13:B bl_out_14:B br_out_14:B bl_out_15:B br_out_15:B bl_out_16:B br_out_16:B bl_out_17:B br_out_17:B bl_out_18:B br_out_18:B bl_out_19:B br_out_19:B bl_out_20:B br_out_20:B bl_out_21:B br_out_21:B bl_out_22:B br_out_22:B bl_out_23:B br_out_23:B bl_out_24:B br_out_24:B bl_out_25:B br_out_25:B bl_out_26:B br_out_26:B bl_out_27:B br_out_27:B bl_out_28:B br_out_28:B bl_out_29:B br_out_29:B bl_out_30:B br_out_30:B bl_out_31:B br_out_31:B bl_out_32:B br_out_32:B bl_out_33:B br_out_33:B bl_out_34:B br_out_34:B bl_out_35:B br_out_35:B bl_out_36:B br_out_36:B bl_out_37:B br_out_37:B bl_out_38:B br_out_38:B bl_out_39:B br_out_39:B bl_out_40:B br_out_40:B bl_out_41:B br_out_41:B bl_out_42:B br_out_42:B bl_out_43:B br_out_43:B bl_out_44:B br_out_44:B bl_out_45:B br_out_45:B bl_out_46:B br_out_46:B bl_out_47:B br_out_47:B bl_out_48:B br_out_48:B bl_out_49:B br_out_49:B bl_out_50:B br_out_50:B bl_out_51:B br_out_51:B bl_out_52:B br_out_52:B bl_out_53:B br_out_53:B bl_out_54:B br_out_54:B bl_out_55:B br_out_55:B bl_out_56:B br_out_56:B bl_out_57:B br_out_57:B bl_out_58:B br_out_58:B bl_out_59:B br_out_59:B bl_out_60:B br_out_60:B bl_out_61:B br_out_61:B bl_out_62:B br_out_62:B bl_out_63:B br_out_63:B gnd:B -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* INOUT : sel_0 -* INOUT : sel_1 -* INOUT : bl_out_0 -* INOUT : br_out_0 -* INOUT : bl_out_1 -* INOUT : br_out_1 -* INOUT : bl_out_2 -* INOUT : br_out_2 -* INOUT : bl_out_3 -* INOUT : br_out_3 -* INOUT : bl_out_4 -* INOUT : br_out_4 -* INOUT : bl_out_5 -* INOUT : br_out_5 -* INOUT : bl_out_6 -* INOUT : br_out_6 -* INOUT : bl_out_7 -* INOUT : br_out_7 -* INOUT : bl_out_8 -* INOUT : br_out_8 -* INOUT : bl_out_9 -* INOUT : br_out_9 -* INOUT : bl_out_10 -* INOUT : br_out_10 -* INOUT : bl_out_11 -* INOUT : br_out_11 -* INOUT : bl_out_12 -* INOUT : br_out_12 -* INOUT : bl_out_13 -* INOUT : br_out_13 -* INOUT : bl_out_14 -* INOUT : br_out_14 -* INOUT : bl_out_15 -* INOUT : br_out_15 -* INOUT : bl_out_16 -* INOUT : br_out_16 -* INOUT : bl_out_17 -* INOUT : br_out_17 -* INOUT : bl_out_18 -* INOUT : br_out_18 -* INOUT : bl_out_19 -* INOUT : br_out_19 -* INOUT : bl_out_20 -* INOUT : br_out_20 -* INOUT : bl_out_21 -* INOUT : br_out_21 -* INOUT : bl_out_22 -* INOUT : br_out_22 -* INOUT : bl_out_23 -* INOUT : br_out_23 -* INOUT : bl_out_24 -* INOUT : br_out_24 -* INOUT : bl_out_25 -* INOUT : br_out_25 -* INOUT : bl_out_26 -* INOUT : br_out_26 -* INOUT : bl_out_27 -* INOUT : br_out_27 -* INOUT : bl_out_28 -* INOUT : br_out_28 -* INOUT : bl_out_29 -* INOUT : br_out_29 -* INOUT : bl_out_30 -* INOUT : br_out_30 -* INOUT : bl_out_31 -* INOUT : br_out_31 -* INOUT : bl_out_32 -* INOUT : br_out_32 -* INOUT : bl_out_33 -* INOUT : br_out_33 -* INOUT : bl_out_34 -* INOUT : br_out_34 -* INOUT : bl_out_35 -* INOUT : br_out_35 -* INOUT : bl_out_36 -* INOUT : br_out_36 -* INOUT : bl_out_37 -* INOUT : br_out_37 -* INOUT : bl_out_38 -* INOUT : br_out_38 -* INOUT : bl_out_39 -* INOUT : br_out_39 -* INOUT : bl_out_40 -* INOUT : br_out_40 -* INOUT : bl_out_41 -* INOUT : br_out_41 -* INOUT : bl_out_42 -* INOUT : br_out_42 -* INOUT : bl_out_43 -* INOUT : br_out_43 -* INOUT : bl_out_44 -* INOUT : br_out_44 -* INOUT : bl_out_45 -* INOUT : br_out_45 -* INOUT : bl_out_46 -* INOUT : br_out_46 -* INOUT : bl_out_47 -* INOUT : br_out_47 -* INOUT : bl_out_48 -* INOUT : br_out_48 -* INOUT : bl_out_49 -* INOUT : br_out_49 -* INOUT : bl_out_50 -* INOUT : br_out_50 -* INOUT : bl_out_51 -* INOUT : br_out_51 -* INOUT : bl_out_52 -* INOUT : br_out_52 -* INOUT : bl_out_53 -* INOUT : br_out_53 -* INOUT : bl_out_54 -* INOUT : br_out_54 -* INOUT : bl_out_55 -* INOUT : br_out_55 -* INOUT : bl_out_56 -* INOUT : br_out_56 -* INOUT : bl_out_57 -* INOUT : br_out_57 -* INOUT : bl_out_58 -* INOUT : br_out_58 -* INOUT : bl_out_59 -* INOUT : br_out_59 -* INOUT : bl_out_60 -* INOUT : br_out_60 -* INOUT : bl_out_61 -* INOUT : br_out_61 -* INOUT : bl_out_62 -* INOUT : br_out_62 -* INOUT : bl_out_63 -* INOUT : br_out_63 -* INOUT : gnd -* cols: 128 word_size: 64 bl: bl br: br -XXMUX0 bl_0 br_0 bl_out_0 br_out_0 sel_0 gnd column_mux -XXMUX1 bl_1 br_1 bl_out_0 br_out_0 sel_1 gnd column_mux -XXMUX2 bl_2 br_2 bl_out_1 br_out_1 sel_0 gnd column_mux -XXMUX3 bl_3 br_3 bl_out_1 br_out_1 sel_1 gnd column_mux -XXMUX4 bl_4 br_4 bl_out_2 br_out_2 sel_0 gnd column_mux -XXMUX5 bl_5 br_5 bl_out_2 br_out_2 sel_1 gnd column_mux -XXMUX6 bl_6 br_6 bl_out_3 br_out_3 sel_0 gnd column_mux -XXMUX7 bl_7 br_7 bl_out_3 br_out_3 sel_1 gnd column_mux -XXMUX8 bl_8 br_8 bl_out_4 br_out_4 sel_0 gnd column_mux -XXMUX9 bl_9 br_9 bl_out_4 br_out_4 sel_1 gnd column_mux -XXMUX10 bl_10 br_10 bl_out_5 br_out_5 sel_0 gnd column_mux -XXMUX11 bl_11 br_11 bl_out_5 br_out_5 sel_1 gnd column_mux -XXMUX12 bl_12 br_12 bl_out_6 br_out_6 sel_0 gnd column_mux -XXMUX13 bl_13 br_13 bl_out_6 br_out_6 sel_1 gnd column_mux -XXMUX14 bl_14 br_14 bl_out_7 br_out_7 sel_0 gnd column_mux -XXMUX15 bl_15 br_15 bl_out_7 br_out_7 sel_1 gnd column_mux -XXMUX16 bl_16 br_16 bl_out_8 br_out_8 sel_0 gnd column_mux -XXMUX17 bl_17 br_17 bl_out_8 br_out_8 sel_1 gnd column_mux -XXMUX18 bl_18 br_18 bl_out_9 br_out_9 sel_0 gnd column_mux -XXMUX19 bl_19 br_19 bl_out_9 br_out_9 sel_1 gnd column_mux -XXMUX20 bl_20 br_20 bl_out_10 br_out_10 sel_0 gnd column_mux -XXMUX21 bl_21 br_21 bl_out_10 br_out_10 sel_1 gnd column_mux -XXMUX22 bl_22 br_22 bl_out_11 br_out_11 sel_0 gnd column_mux -XXMUX23 bl_23 br_23 bl_out_11 br_out_11 sel_1 gnd column_mux -XXMUX24 bl_24 br_24 bl_out_12 br_out_12 sel_0 gnd column_mux -XXMUX25 bl_25 br_25 bl_out_12 br_out_12 sel_1 gnd column_mux -XXMUX26 bl_26 br_26 bl_out_13 br_out_13 sel_0 gnd column_mux -XXMUX27 bl_27 br_27 bl_out_13 br_out_13 sel_1 gnd column_mux -XXMUX28 bl_28 br_28 bl_out_14 br_out_14 sel_0 gnd column_mux -XXMUX29 bl_29 br_29 bl_out_14 br_out_14 sel_1 gnd column_mux -XXMUX30 bl_30 br_30 bl_out_15 br_out_15 sel_0 gnd column_mux -XXMUX31 bl_31 br_31 bl_out_15 br_out_15 sel_1 gnd column_mux -XXMUX32 bl_32 br_32 bl_out_16 br_out_16 sel_0 gnd column_mux -XXMUX33 bl_33 br_33 bl_out_16 br_out_16 sel_1 gnd column_mux -XXMUX34 bl_34 br_34 bl_out_17 br_out_17 sel_0 gnd column_mux -XXMUX35 bl_35 br_35 bl_out_17 br_out_17 sel_1 gnd column_mux -XXMUX36 bl_36 br_36 bl_out_18 br_out_18 sel_0 gnd column_mux -XXMUX37 bl_37 br_37 bl_out_18 br_out_18 sel_1 gnd column_mux -XXMUX38 bl_38 br_38 bl_out_19 br_out_19 sel_0 gnd column_mux -XXMUX39 bl_39 br_39 bl_out_19 br_out_19 sel_1 gnd column_mux -XXMUX40 bl_40 br_40 bl_out_20 br_out_20 sel_0 gnd column_mux -XXMUX41 bl_41 br_41 bl_out_20 br_out_20 sel_1 gnd column_mux -XXMUX42 bl_42 br_42 bl_out_21 br_out_21 sel_0 gnd column_mux -XXMUX43 bl_43 br_43 bl_out_21 br_out_21 sel_1 gnd column_mux -XXMUX44 bl_44 br_44 bl_out_22 br_out_22 sel_0 gnd column_mux -XXMUX45 bl_45 br_45 bl_out_22 br_out_22 sel_1 gnd column_mux -XXMUX46 bl_46 br_46 bl_out_23 br_out_23 sel_0 gnd column_mux -XXMUX47 bl_47 br_47 bl_out_23 br_out_23 sel_1 gnd column_mux -XXMUX48 bl_48 br_48 bl_out_24 br_out_24 sel_0 gnd column_mux -XXMUX49 bl_49 br_49 bl_out_24 br_out_24 sel_1 gnd column_mux -XXMUX50 bl_50 br_50 bl_out_25 br_out_25 sel_0 gnd column_mux -XXMUX51 bl_51 br_51 bl_out_25 br_out_25 sel_1 gnd column_mux -XXMUX52 bl_52 br_52 bl_out_26 br_out_26 sel_0 gnd column_mux -XXMUX53 bl_53 br_53 bl_out_26 br_out_26 sel_1 gnd column_mux -XXMUX54 bl_54 br_54 bl_out_27 br_out_27 sel_0 gnd column_mux -XXMUX55 bl_55 br_55 bl_out_27 br_out_27 sel_1 gnd column_mux -XXMUX56 bl_56 br_56 bl_out_28 br_out_28 sel_0 gnd column_mux -XXMUX57 bl_57 br_57 bl_out_28 br_out_28 sel_1 gnd column_mux -XXMUX58 bl_58 br_58 bl_out_29 br_out_29 sel_0 gnd column_mux -XXMUX59 bl_59 br_59 bl_out_29 br_out_29 sel_1 gnd column_mux -XXMUX60 bl_60 br_60 bl_out_30 br_out_30 sel_0 gnd column_mux -XXMUX61 bl_61 br_61 bl_out_30 br_out_30 sel_1 gnd column_mux -XXMUX62 bl_62 br_62 bl_out_31 br_out_31 sel_0 gnd column_mux -XXMUX63 bl_63 br_63 bl_out_31 br_out_31 sel_1 gnd column_mux -XXMUX64 bl_64 br_64 bl_out_32 br_out_32 sel_0 gnd column_mux -XXMUX65 bl_65 br_65 bl_out_32 br_out_32 sel_1 gnd column_mux -XXMUX66 bl_66 br_66 bl_out_33 br_out_33 sel_0 gnd column_mux -XXMUX67 bl_67 br_67 bl_out_33 br_out_33 sel_1 gnd column_mux -XXMUX68 bl_68 br_68 bl_out_34 br_out_34 sel_0 gnd column_mux -XXMUX69 bl_69 br_69 bl_out_34 br_out_34 sel_1 gnd column_mux -XXMUX70 bl_70 br_70 bl_out_35 br_out_35 sel_0 gnd column_mux -XXMUX71 bl_71 br_71 bl_out_35 br_out_35 sel_1 gnd column_mux -XXMUX72 bl_72 br_72 bl_out_36 br_out_36 sel_0 gnd column_mux -XXMUX73 bl_73 br_73 bl_out_36 br_out_36 sel_1 gnd column_mux -XXMUX74 bl_74 br_74 bl_out_37 br_out_37 sel_0 gnd column_mux -XXMUX75 bl_75 br_75 bl_out_37 br_out_37 sel_1 gnd column_mux -XXMUX76 bl_76 br_76 bl_out_38 br_out_38 sel_0 gnd column_mux -XXMUX77 bl_77 br_77 bl_out_38 br_out_38 sel_1 gnd column_mux -XXMUX78 bl_78 br_78 bl_out_39 br_out_39 sel_0 gnd column_mux -XXMUX79 bl_79 br_79 bl_out_39 br_out_39 sel_1 gnd column_mux -XXMUX80 bl_80 br_80 bl_out_40 br_out_40 sel_0 gnd column_mux -XXMUX81 bl_81 br_81 bl_out_40 br_out_40 sel_1 gnd column_mux -XXMUX82 bl_82 br_82 bl_out_41 br_out_41 sel_0 gnd column_mux -XXMUX83 bl_83 br_83 bl_out_41 br_out_41 sel_1 gnd column_mux -XXMUX84 bl_84 br_84 bl_out_42 br_out_42 sel_0 gnd column_mux -XXMUX85 bl_85 br_85 bl_out_42 br_out_42 sel_1 gnd column_mux -XXMUX86 bl_86 br_86 bl_out_43 br_out_43 sel_0 gnd column_mux -XXMUX87 bl_87 br_87 bl_out_43 br_out_43 sel_1 gnd column_mux -XXMUX88 bl_88 br_88 bl_out_44 br_out_44 sel_0 gnd column_mux -XXMUX89 bl_89 br_89 bl_out_44 br_out_44 sel_1 gnd column_mux -XXMUX90 bl_90 br_90 bl_out_45 br_out_45 sel_0 gnd column_mux -XXMUX91 bl_91 br_91 bl_out_45 br_out_45 sel_1 gnd column_mux -XXMUX92 bl_92 br_92 bl_out_46 br_out_46 sel_0 gnd column_mux -XXMUX93 bl_93 br_93 bl_out_46 br_out_46 sel_1 gnd column_mux -XXMUX94 bl_94 br_94 bl_out_47 br_out_47 sel_0 gnd column_mux -XXMUX95 bl_95 br_95 bl_out_47 br_out_47 sel_1 gnd column_mux -XXMUX96 bl_96 br_96 bl_out_48 br_out_48 sel_0 gnd column_mux -XXMUX97 bl_97 br_97 bl_out_48 br_out_48 sel_1 gnd column_mux -XXMUX98 bl_98 br_98 bl_out_49 br_out_49 sel_0 gnd column_mux -XXMUX99 bl_99 br_99 bl_out_49 br_out_49 sel_1 gnd column_mux -XXMUX100 bl_100 br_100 bl_out_50 br_out_50 sel_0 gnd column_mux -XXMUX101 bl_101 br_101 bl_out_50 br_out_50 sel_1 gnd column_mux -XXMUX102 bl_102 br_102 bl_out_51 br_out_51 sel_0 gnd column_mux -XXMUX103 bl_103 br_103 bl_out_51 br_out_51 sel_1 gnd column_mux -XXMUX104 bl_104 br_104 bl_out_52 br_out_52 sel_0 gnd column_mux -XXMUX105 bl_105 br_105 bl_out_52 br_out_52 sel_1 gnd column_mux -XXMUX106 bl_106 br_106 bl_out_53 br_out_53 sel_0 gnd column_mux -XXMUX107 bl_107 br_107 bl_out_53 br_out_53 sel_1 gnd column_mux -XXMUX108 bl_108 br_108 bl_out_54 br_out_54 sel_0 gnd column_mux -XXMUX109 bl_109 br_109 bl_out_54 br_out_54 sel_1 gnd column_mux -XXMUX110 bl_110 br_110 bl_out_55 br_out_55 sel_0 gnd column_mux -XXMUX111 bl_111 br_111 bl_out_55 br_out_55 sel_1 gnd column_mux -XXMUX112 bl_112 br_112 bl_out_56 br_out_56 sel_0 gnd column_mux -XXMUX113 bl_113 br_113 bl_out_56 br_out_56 sel_1 gnd column_mux -XXMUX114 bl_114 br_114 bl_out_57 br_out_57 sel_0 gnd column_mux -XXMUX115 bl_115 br_115 bl_out_57 br_out_57 sel_1 gnd column_mux -XXMUX116 bl_116 br_116 bl_out_58 br_out_58 sel_0 gnd column_mux -XXMUX117 bl_117 br_117 bl_out_58 br_out_58 sel_1 gnd column_mux -XXMUX118 bl_118 br_118 bl_out_59 br_out_59 sel_0 gnd column_mux -XXMUX119 bl_119 br_119 bl_out_59 br_out_59 sel_1 gnd column_mux -XXMUX120 bl_120 br_120 bl_out_60 br_out_60 sel_0 gnd column_mux -XXMUX121 bl_121 br_121 bl_out_60 br_out_60 sel_1 gnd column_mux -XXMUX122 bl_122 br_122 bl_out_61 br_out_61 sel_0 gnd column_mux -XXMUX123 bl_123 br_123 bl_out_61 br_out_61 sel_1 gnd column_mux -XXMUX124 bl_124 br_124 bl_out_62 br_out_62 sel_0 gnd column_mux -XXMUX125 bl_125 br_125 bl_out_62 br_out_62 sel_1 gnd column_mux -XXMUX126 bl_126 br_126 bl_out_63 br_out_63 sel_0 gnd column_mux -XXMUX127 bl_127 br_127 bl_out_63 br_out_63 sel_1 gnd column_mux -.ENDS column_mux_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 dout_32 dout_33 dout_34 dout_35 dout_36 dout_37 dout_38 dout_39 dout_40 dout_41 dout_42 dout_43 dout_44 dout_45 dout_46 dout_47 dout_48 dout_49 dout_50 dout_51 dout_52 dout_53 dout_54 dout_55 dout_56 dout_57 dout_58 dout_59 dout_60 dout_61 dout_62 dout_63 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 sel_0 sel_1 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B bl_32:B br_32:B bl_33:B br_33:B bl_34:B br_34:B bl_35:B br_35:B bl_36:B br_36:B bl_37:B br_37:B bl_38:B br_38:B bl_39:B br_39:B bl_40:B br_40:B bl_41:B br_41:B bl_42:B br_42:B bl_43:B br_43:B bl_44:B br_44:B bl_45:B br_45:B bl_46:B br_46:B bl_47:B br_47:B bl_48:B br_48:B bl_49:B br_49:B bl_50:B br_50:B bl_51:B br_51:B bl_52:B br_52:B bl_53:B br_53:B bl_54:B br_54:B bl_55:B br_55:B bl_56:B br_56:B bl_57:B br_57:B bl_58:B br_58:B bl_59:B br_59:B bl_60:B br_60:B bl_61:B br_61:B bl_62:B br_62:B bl_63:B br_63:B bl_64:B br_64:B bl_65:B br_65:B bl_66:B br_66:B bl_67:B br_67:B bl_68:B br_68:B bl_69:B br_69:B bl_70:B br_70:B bl_71:B br_71:B bl_72:B br_72:B bl_73:B br_73:B bl_74:B br_74:B bl_75:B br_75:B bl_76:B br_76:B bl_77:B br_77:B bl_78:B br_78:B bl_79:B br_79:B bl_80:B br_80:B bl_81:B br_81:B bl_82:B br_82:B bl_83:B br_83:B bl_84:B br_84:B bl_85:B br_85:B bl_86:B br_86:B bl_87:B br_87:B bl_88:B br_88:B bl_89:B br_89:B bl_90:B br_90:B bl_91:B br_91:B bl_92:B br_92:B bl_93:B br_93:B bl_94:B br_94:B bl_95:B br_95:B bl_96:B br_96:B bl_97:B br_97:B bl_98:B br_98:B bl_99:B br_99:B bl_100:B br_100:B bl_101:B br_101:B bl_102:B br_102:B bl_103:B br_103:B bl_104:B br_104:B bl_105:B br_105:B bl_106:B br_106:B bl_107:B br_107:B bl_108:B br_108:B bl_109:B br_109:B bl_110:B br_110:B bl_111:B br_111:B bl_112:B br_112:B bl_113:B br_113:B bl_114:B br_114:B bl_115:B br_115:B bl_116:B br_116:B bl_117:B br_117:B bl_118:B br_118:B bl_119:B br_119:B bl_120:B br_120:B bl_121:B br_121:B bl_122:B br_122:B bl_123:B br_123:B bl_124:B br_124:B bl_125:B br_125:B bl_126:B br_126:B bl_127:B br_127:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O dout_32:O dout_33:O dout_34:O dout_35:O dout_36:O dout_37:O dout_38:O dout_39:O dout_40:O dout_41:O dout_42:O dout_43:O dout_44:O dout_45:O dout_46:O dout_47:O dout_48:O dout_49:O dout_50:O dout_51:O dout_52:O dout_53:O dout_54:O dout_55:O dout_56:O dout_57:O dout_58:O dout_59:O dout_60:O dout_61:O dout_62:O dout_63:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I din_32:I din_33:I din_34:I din_35:I din_36:I din_37:I din_38:I din_39:I din_40:I din_41:I din_42:I din_43:I din_44:I din_45:I din_46:I din_47:I din_48:I din_49:I din_50:I din_51:I din_52:I din_53:I din_54:I din_55:I din_56:I din_57:I din_58:I din_59:I din_60:I din_61:I din_62:I din_63:I sel_0:I sel_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* INOUT : bl_32 -* INOUT : br_32 -* INOUT : bl_33 -* INOUT : br_33 -* INOUT : bl_34 -* INOUT : br_34 -* INOUT : bl_35 -* INOUT : br_35 -* INOUT : bl_36 -* INOUT : br_36 -* INOUT : bl_37 -* INOUT : br_37 -* INOUT : bl_38 -* INOUT : br_38 -* INOUT : bl_39 -* INOUT : br_39 -* INOUT : bl_40 -* INOUT : br_40 -* INOUT : bl_41 -* INOUT : br_41 -* INOUT : bl_42 -* INOUT : br_42 -* INOUT : bl_43 -* INOUT : br_43 -* INOUT : bl_44 -* INOUT : br_44 -* INOUT : bl_45 -* INOUT : br_45 -* INOUT : bl_46 -* INOUT : br_46 -* INOUT : bl_47 -* INOUT : br_47 -* INOUT : bl_48 -* INOUT : br_48 -* INOUT : bl_49 -* INOUT : br_49 -* INOUT : bl_50 -* INOUT : br_50 -* INOUT : bl_51 -* INOUT : br_51 -* INOUT : bl_52 -* INOUT : br_52 -* INOUT : bl_53 -* INOUT : br_53 -* INOUT : bl_54 -* INOUT : br_54 -* INOUT : bl_55 -* INOUT : br_55 -* INOUT : bl_56 -* INOUT : br_56 -* INOUT : bl_57 -* INOUT : br_57 -* INOUT : bl_58 -* INOUT : br_58 -* INOUT : bl_59 -* INOUT : br_59 -* INOUT : bl_60 -* INOUT : br_60 -* INOUT : bl_61 -* INOUT : br_61 -* INOUT : bl_62 -* INOUT : br_62 -* INOUT : bl_63 -* INOUT : br_63 -* INOUT : bl_64 -* INOUT : br_64 -* INOUT : bl_65 -* INOUT : br_65 -* INOUT : bl_66 -* INOUT : br_66 -* INOUT : bl_67 -* INOUT : br_67 -* INOUT : bl_68 -* INOUT : br_68 -* INOUT : bl_69 -* INOUT : br_69 -* INOUT : bl_70 -* INOUT : br_70 -* INOUT : bl_71 -* INOUT : br_71 -* INOUT : bl_72 -* INOUT : br_72 -* INOUT : bl_73 -* INOUT : br_73 -* INOUT : bl_74 -* INOUT : br_74 -* INOUT : bl_75 -* INOUT : br_75 -* INOUT : bl_76 -* INOUT : br_76 -* INOUT : bl_77 -* INOUT : br_77 -* INOUT : bl_78 -* INOUT : br_78 -* INOUT : bl_79 -* INOUT : br_79 -* INOUT : bl_80 -* INOUT : br_80 -* INOUT : bl_81 -* INOUT : br_81 -* INOUT : bl_82 -* INOUT : br_82 -* INOUT : bl_83 -* INOUT : br_83 -* INOUT : bl_84 -* INOUT : br_84 -* INOUT : bl_85 -* INOUT : br_85 -* INOUT : bl_86 -* INOUT : br_86 -* INOUT : bl_87 -* INOUT : br_87 -* INOUT : bl_88 -* INOUT : br_88 -* INOUT : bl_89 -* INOUT : br_89 -* INOUT : bl_90 -* INOUT : br_90 -* INOUT : bl_91 -* INOUT : br_91 -* INOUT : bl_92 -* INOUT : br_92 -* INOUT : bl_93 -* INOUT : br_93 -* INOUT : bl_94 -* INOUT : br_94 -* INOUT : bl_95 -* INOUT : br_95 -* INOUT : bl_96 -* INOUT : br_96 -* INOUT : bl_97 -* INOUT : br_97 -* INOUT : bl_98 -* INOUT : br_98 -* INOUT : bl_99 -* INOUT : br_99 -* INOUT : bl_100 -* INOUT : br_100 -* INOUT : bl_101 -* INOUT : br_101 -* INOUT : bl_102 -* INOUT : br_102 -* INOUT : bl_103 -* INOUT : br_103 -* INOUT : bl_104 -* INOUT : br_104 -* INOUT : bl_105 -* INOUT : br_105 -* INOUT : bl_106 -* INOUT : br_106 -* INOUT : bl_107 -* INOUT : br_107 -* INOUT : bl_108 -* INOUT : br_108 -* INOUT : bl_109 -* INOUT : br_109 -* INOUT : bl_110 -* INOUT : br_110 -* INOUT : bl_111 -* INOUT : br_111 -* INOUT : bl_112 -* INOUT : br_112 -* INOUT : bl_113 -* INOUT : br_113 -* INOUT : bl_114 -* INOUT : br_114 -* INOUT : bl_115 -* INOUT : br_115 -* INOUT : bl_116 -* INOUT : br_116 -* INOUT : bl_117 -* INOUT : br_117 -* INOUT : bl_118 -* INOUT : br_118 -* INOUT : bl_119 -* INOUT : br_119 -* INOUT : bl_120 -* INOUT : br_120 -* INOUT : bl_121 -* INOUT : br_121 -* INOUT : bl_122 -* INOUT : br_122 -* INOUT : bl_123 -* INOUT : br_123 -* INOUT : bl_124 -* INOUT : br_124 -* INOUT : bl_125 -* INOUT : br_125 -* INOUT : bl_126 -* INOUT : br_126 -* INOUT : bl_127 -* INOUT : br_127 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* OUTPUT: dout_32 -* OUTPUT: dout_33 -* OUTPUT: dout_34 -* OUTPUT: dout_35 -* OUTPUT: dout_36 -* OUTPUT: dout_37 -* OUTPUT: dout_38 -* OUTPUT: dout_39 -* OUTPUT: dout_40 -* OUTPUT: dout_41 -* OUTPUT: dout_42 -* OUTPUT: dout_43 -* OUTPUT: dout_44 -* OUTPUT: dout_45 -* OUTPUT: dout_46 -* OUTPUT: dout_47 -* OUTPUT: dout_48 -* OUTPUT: dout_49 -* OUTPUT: dout_50 -* OUTPUT: dout_51 -* OUTPUT: dout_52 -* OUTPUT: dout_53 -* OUTPUT: dout_54 -* OUTPUT: dout_55 -* OUTPUT: dout_56 -* OUTPUT: dout_57 -* OUTPUT: dout_58 -* OUTPUT: dout_59 -* OUTPUT: dout_60 -* OUTPUT: dout_61 -* OUTPUT: dout_62 -* OUTPUT: dout_63 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : din_32 -* INPUT : din_33 -* INPUT : din_34 -* INPUT : din_35 -* INPUT : din_36 -* INPUT : din_37 -* INPUT : din_38 -* INPUT : din_39 -* INPUT : din_40 -* INPUT : din_41 -* INPUT : din_42 -* INPUT : din_43 -* INPUT : din_44 -* INPUT : din_45 -* INPUT : din_46 -* INPUT : din_47 -* INPUT : din_48 -* INPUT : din_49 -* INPUT : din_50 -* INPUT : din_51 -* INPUT : din_52 -* INPUT : din_53 -* INPUT : din_54 -* INPUT : din_55 -* INPUT : din_56 -* INPUT : din_57 -* INPUT : din_58 -* INPUT : din_59 -* INPUT : din_60 -* INPUT : din_61 -* INPUT : din_62 -* INPUT : din_63 -* INPUT : sel_0 -* INPUT : sel_1 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_out_0 br_out_0 dout_1 bl_out_1 br_out_1 dout_2 bl_out_2 br_out_2 dout_3 bl_out_3 br_out_3 dout_4 bl_out_4 br_out_4 dout_5 bl_out_5 br_out_5 dout_6 bl_out_6 br_out_6 dout_7 bl_out_7 br_out_7 dout_8 bl_out_8 br_out_8 dout_9 bl_out_9 br_out_9 dout_10 bl_out_10 br_out_10 dout_11 bl_out_11 br_out_11 dout_12 bl_out_12 br_out_12 dout_13 bl_out_13 br_out_13 dout_14 bl_out_14 br_out_14 dout_15 bl_out_15 br_out_15 dout_16 bl_out_16 br_out_16 dout_17 bl_out_17 br_out_17 dout_18 bl_out_18 br_out_18 dout_19 bl_out_19 br_out_19 dout_20 bl_out_20 br_out_20 dout_21 bl_out_21 br_out_21 dout_22 bl_out_22 br_out_22 dout_23 bl_out_23 br_out_23 dout_24 bl_out_24 br_out_24 dout_25 bl_out_25 br_out_25 dout_26 bl_out_26 br_out_26 dout_27 bl_out_27 br_out_27 dout_28 bl_out_28 br_out_28 dout_29 bl_out_29 br_out_29 dout_30 bl_out_30 br_out_30 dout_31 bl_out_31 br_out_31 dout_32 bl_out_32 br_out_32 dout_33 bl_out_33 br_out_33 dout_34 bl_out_34 br_out_34 dout_35 bl_out_35 br_out_35 dout_36 bl_out_36 br_out_36 dout_37 bl_out_37 br_out_37 dout_38 bl_out_38 br_out_38 dout_39 bl_out_39 br_out_39 dout_40 bl_out_40 br_out_40 dout_41 bl_out_41 br_out_41 dout_42 bl_out_42 br_out_42 dout_43 bl_out_43 br_out_43 dout_44 bl_out_44 br_out_44 dout_45 bl_out_45 br_out_45 dout_46 bl_out_46 br_out_46 dout_47 bl_out_47 br_out_47 dout_48 bl_out_48 br_out_48 dout_49 bl_out_49 br_out_49 dout_50 bl_out_50 br_out_50 dout_51 bl_out_51 br_out_51 dout_52 bl_out_52 br_out_52 dout_53 bl_out_53 br_out_53 dout_54 bl_out_54 br_out_54 dout_55 bl_out_55 br_out_55 dout_56 bl_out_56 br_out_56 dout_57 bl_out_57 br_out_57 dout_58 bl_out_58 br_out_58 dout_59 bl_out_59 br_out_59 dout_60 bl_out_60 br_out_60 dout_61 bl_out_61 br_out_61 dout_62 bl_out_62 br_out_62 dout_63 bl_out_63 br_out_63 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 din_32 din_33 din_34 din_35 din_36 din_37 din_38 din_39 din_40 din_41 din_42 din_43 din_44 din_45 din_46 din_47 din_48 din_49 din_50 din_51 din_52 din_53 din_54 din_55 din_56 din_57 din_58 din_59 din_60 din_61 din_62 din_63 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 w_en vdd gnd write_driver_array -Xcolumn_mux_array0 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 bl_33 br_33 bl_34 br_34 bl_35 br_35 bl_36 br_36 bl_37 br_37 bl_38 br_38 bl_39 br_39 bl_40 br_40 bl_41 br_41 bl_42 br_42 bl_43 br_43 bl_44 br_44 bl_45 br_45 bl_46 br_46 bl_47 br_47 bl_48 br_48 bl_49 br_49 bl_50 br_50 bl_51 br_51 bl_52 br_52 bl_53 br_53 bl_54 br_54 bl_55 br_55 bl_56 br_56 bl_57 br_57 bl_58 br_58 bl_59 br_59 bl_60 br_60 bl_61 br_61 bl_62 br_62 bl_63 br_63 bl_64 br_64 bl_65 br_65 bl_66 br_66 bl_67 br_67 bl_68 br_68 bl_69 br_69 bl_70 br_70 bl_71 br_71 bl_72 br_72 bl_73 br_73 bl_74 br_74 bl_75 br_75 bl_76 br_76 bl_77 br_77 bl_78 br_78 bl_79 br_79 bl_80 br_80 bl_81 br_81 bl_82 br_82 bl_83 br_83 bl_84 br_84 bl_85 br_85 bl_86 br_86 bl_87 br_87 bl_88 br_88 bl_89 br_89 bl_90 br_90 bl_91 br_91 bl_92 br_92 bl_93 br_93 bl_94 br_94 bl_95 br_95 bl_96 br_96 bl_97 br_97 bl_98 br_98 bl_99 br_99 bl_100 br_100 bl_101 br_101 bl_102 br_102 bl_103 br_103 bl_104 br_104 bl_105 br_105 bl_106 br_106 bl_107 br_107 bl_108 br_108 bl_109 br_109 bl_110 br_110 bl_111 br_111 bl_112 br_112 bl_113 br_113 bl_114 br_114 bl_115 br_115 bl_116 br_116 bl_117 br_117 bl_118 br_118 bl_119 br_119 bl_120 br_120 bl_121 br_121 bl_122 br_122 bl_123 br_123 bl_124 br_124 bl_125 br_125 bl_126 br_126 bl_127 br_127 sel_0 sel_1 bl_out_0 br_out_0 bl_out_1 br_out_1 bl_out_2 br_out_2 bl_out_3 br_out_3 bl_out_4 br_out_4 bl_out_5 br_out_5 bl_out_6 br_out_6 bl_out_7 br_out_7 bl_out_8 br_out_8 bl_out_9 br_out_9 bl_out_10 br_out_10 bl_out_11 br_out_11 bl_out_12 br_out_12 bl_out_13 br_out_13 bl_out_14 br_out_14 bl_out_15 br_out_15 bl_out_16 br_out_16 bl_out_17 br_out_17 bl_out_18 br_out_18 bl_out_19 br_out_19 bl_out_20 br_out_20 bl_out_21 br_out_21 bl_out_22 br_out_22 bl_out_23 br_out_23 bl_out_24 br_out_24 bl_out_25 br_out_25 bl_out_26 br_out_26 bl_out_27 br_out_27 bl_out_28 br_out_28 bl_out_29 br_out_29 bl_out_30 br_out_30 bl_out_31 br_out_31 bl_out_32 br_out_32 bl_out_33 br_out_33 bl_out_34 br_out_34 bl_out_35 br_out_35 bl_out_36 br_out_36 bl_out_37 br_out_37 bl_out_38 br_out_38 bl_out_39 br_out_39 bl_out_40 br_out_40 bl_out_41 br_out_41 bl_out_42 br_out_42 bl_out_43 br_out_43 bl_out_44 br_out_44 bl_out_45 br_out_45 bl_out_46 br_out_46 bl_out_47 br_out_47 bl_out_48 br_out_48 bl_out_49 br_out_49 bl_out_50 br_out_50 bl_out_51 br_out_51 bl_out_52 br_out_52 bl_out_53 br_out_53 bl_out_54 br_out_54 bl_out_55 br_out_55 bl_out_56 br_out_56 bl_out_57 br_out_57 bl_out_58 br_out_58 bl_out_59 br_out_59 bl_out_60 br_out_60 bl_out_61 br_out_61 bl_out_62 br_out_62 bl_out_63 br_out_63 gnd column_mux_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2 - -* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p -.ENDS pinv_0 - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 32 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv_0 -.ENDS and2_dec_0 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv_0 -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 in_32 in_33 in_34 in_35 in_36 in_37 in_38 in_39 in_40 in_41 in_42 in_43 in_44 in_45 in_46 in_47 in_48 in_49 in_50 in_51 in_52 in_53 in_54 in_55 in_56 in_57 in_58 in_59 in_60 in_61 in_62 in_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I in_32:I in_33:I in_34:I in_35:I in_36:I in_37:I in_38:I in_39:I in_40:I in_41:I in_42:I in_43:I in_44:I in_45:I in_46:I in_47:I in_48:I in_49:I in_50:I in_51:I in_52:I in_53:I in_54:I in_55:I in_56:I in_57:I in_58:I in_59:I in_60:I in_61:I in_62:I in_63:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* INPUT : in_16 -* INPUT : in_17 -* INPUT : in_18 -* INPUT : in_19 -* INPUT : in_20 -* INPUT : in_21 -* INPUT : in_22 -* INPUT : in_23 -* INPUT : in_24 -* INPUT : in_25 -* INPUT : in_26 -* INPUT : in_27 -* INPUT : in_28 -* INPUT : in_29 -* INPUT : in_30 -* INPUT : in_31 -* INPUT : in_32 -* INPUT : in_33 -* INPUT : in_34 -* INPUT : in_35 -* INPUT : in_36 -* INPUT : in_37 -* INPUT : in_38 -* INPUT : in_39 -* INPUT : in_40 -* INPUT : in_41 -* INPUT : in_42 -* INPUT : in_43 -* INPUT : in_44 -* INPUT : in_45 -* INPUT : in_46 -* INPUT : in_47 -* INPUT : in_48 -* INPUT : in_49 -* INPUT : in_50 -* INPUT : in_51 -* INPUT : in_52 -* INPUT : in_53 -* INPUT : in_54 -* INPUT : in_55 -* INPUT : in_56 -* INPUT : in_57 -* INPUT : in_58 -* INPUT : in_59 -* INPUT : in_60 -* INPUT : in_61 -* INPUT : in_62 -* INPUT : in_63 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 64 cols: 128 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver -Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver -Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver -Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver -Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver -Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver -Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver -Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver -Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver -Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver -Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver -Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver -Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver -Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver -Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver -Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver -Xwl_driver_and32 in_32 en wl_32 vdd gnd wordline_driver -Xwl_driver_and33 in_33 en wl_33 vdd gnd wordline_driver -Xwl_driver_and34 in_34 en wl_34 vdd gnd wordline_driver -Xwl_driver_and35 in_35 en wl_35 vdd gnd wordline_driver -Xwl_driver_and36 in_36 en wl_36 vdd gnd wordline_driver -Xwl_driver_and37 in_37 en wl_37 vdd gnd wordline_driver -Xwl_driver_and38 in_38 en wl_38 vdd gnd wordline_driver -Xwl_driver_and39 in_39 en wl_39 vdd gnd wordline_driver -Xwl_driver_and40 in_40 en wl_40 vdd gnd wordline_driver -Xwl_driver_and41 in_41 en wl_41 vdd gnd wordline_driver -Xwl_driver_and42 in_42 en wl_42 vdd gnd wordline_driver -Xwl_driver_and43 in_43 en wl_43 vdd gnd wordline_driver -Xwl_driver_and44 in_44 en wl_44 vdd gnd wordline_driver -Xwl_driver_and45 in_45 en wl_45 vdd gnd wordline_driver -Xwl_driver_and46 in_46 en wl_46 vdd gnd wordline_driver -Xwl_driver_and47 in_47 en wl_47 vdd gnd wordline_driver -Xwl_driver_and48 in_48 en wl_48 vdd gnd wordline_driver -Xwl_driver_and49 in_49 en wl_49 vdd gnd wordline_driver -Xwl_driver_and50 in_50 en wl_50 vdd gnd wordline_driver -Xwl_driver_and51 in_51 en wl_51 vdd gnd wordline_driver -Xwl_driver_and52 in_52 en wl_52 vdd gnd wordline_driver -Xwl_driver_and53 in_53 en wl_53 vdd gnd wordline_driver -Xwl_driver_and54 in_54 en wl_54 vdd gnd wordline_driver -Xwl_driver_and55 in_55 en wl_55 vdd gnd wordline_driver -Xwl_driver_and56 in_56 en wl_56 vdd gnd wordline_driver -Xwl_driver_and57 in_57 en wl_57 vdd gnd wordline_driver -Xwl_driver_and58 in_58 en wl_58 vdd gnd wordline_driver -Xwl_driver_and59 in_59 en wl_59 vdd gnd wordline_driver -Xwl_driver_and60 in_60 en wl_60 vdd gnd wordline_driver -Xwl_driver_and61 in_61 en wl_61 vdd gnd wordline_driver -Xwl_driver_and62 in_62 en wl_62 vdd gnd wordline_driver -Xwl_driver_and63 in_63 en wl_63 vdd gnd wordline_driver -.ENDS wordline_driver_array - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3 - -.SUBCKT and3_dec A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand3_dec_nand A B C zb_int vdd gnd pnand3 -Xpand3_dec_inv zb_int Z vdd gnd pinv -.ENDS and3_dec - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 decode_32 decode_33 decode_34 decode_35 decode_36 decode_37 decode_38 decode_39 decode_40 decode_41 decode_42 decode_43 decode_44 decode_45 decode_46 decode_47 decode_48 decode_49 decode_50 decode_51 decode_52 decode_53 decode_54 decode_55 decode_56 decode_57 decode_58 decode_59 decode_60 decode_61 decode_62 decode_63 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O decode_32:O decode_33:O decode_34:O decode_35:O decode_36:O decode_37:O decode_38:O decode_39:O decode_40:O decode_41:O decode_42:O decode_43:O decode_44:O decode_45:O decode_46:O decode_47:O decode_48:O decode_49:O decode_50:O decode_51:O decode_52:O decode_53:O decode_54:O decode_55:O decode_56:O decode_57:O decode_58:O decode_59:O decode_60:O decode_61:O decode_62:O decode_63:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* OUTPUT: decode_16 -* OUTPUT: decode_17 -* OUTPUT: decode_18 -* OUTPUT: decode_19 -* OUTPUT: decode_20 -* OUTPUT: decode_21 -* OUTPUT: decode_22 -* OUTPUT: decode_23 -* OUTPUT: decode_24 -* OUTPUT: decode_25 -* OUTPUT: decode_26 -* OUTPUT: decode_27 -* OUTPUT: decode_28 -* OUTPUT: decode_29 -* OUTPUT: decode_30 -* OUTPUT: decode_31 -* OUTPUT: decode_32 -* OUTPUT: decode_33 -* OUTPUT: decode_34 -* OUTPUT: decode_35 -* OUTPUT: decode_36 -* OUTPUT: decode_37 -* OUTPUT: decode_38 -* OUTPUT: decode_39 -* OUTPUT: decode_40 -* OUTPUT: decode_41 -* OUTPUT: decode_42 -* OUTPUT: decode_43 -* OUTPUT: decode_44 -* OUTPUT: decode_45 -* OUTPUT: decode_46 -* OUTPUT: decode_47 -* OUTPUT: decode_48 -* OUTPUT: decode_49 -* OUTPUT: decode_50 -* OUTPUT: decode_51 -* OUTPUT: decode_52 -* OUTPUT: decode_53 -* OUTPUT: decode_54 -* OUTPUT: decode_55 -* OUTPUT: decode_56 -* OUTPUT: decode_57 -* OUTPUT: decode_58 -* OUTPUT: decode_59 -* OUTPUT: decode_60 -* OUTPUT: decode_61 -* OUTPUT: decode_62 -* OUTPUT: decode_63 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 -Xpre_2 addr_4 addr_5 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode2x4 -XDEC_AND_0 out_0 out_4 out_8 decode_0 vdd gnd and3_dec -XDEC_AND_16 out_0 out_4 out_9 decode_16 vdd gnd and3_dec -XDEC_AND_32 out_0 out_4 out_10 decode_32 vdd gnd and3_dec -XDEC_AND_48 out_0 out_4 out_11 decode_48 vdd gnd and3_dec -XDEC_AND_4 out_0 out_5 out_8 decode_4 vdd gnd and3_dec -XDEC_AND_20 out_0 out_5 out_9 decode_20 vdd gnd and3_dec -XDEC_AND_36 out_0 out_5 out_10 decode_36 vdd gnd and3_dec -XDEC_AND_52 out_0 out_5 out_11 decode_52 vdd gnd and3_dec -XDEC_AND_8 out_0 out_6 out_8 decode_8 vdd gnd and3_dec -XDEC_AND_24 out_0 out_6 out_9 decode_24 vdd gnd and3_dec -XDEC_AND_40 out_0 out_6 out_10 decode_40 vdd gnd and3_dec -XDEC_AND_56 out_0 out_6 out_11 decode_56 vdd gnd and3_dec -XDEC_AND_12 out_0 out_7 out_8 decode_12 vdd gnd and3_dec -XDEC_AND_28 out_0 out_7 out_9 decode_28 vdd gnd and3_dec -XDEC_AND_44 out_0 out_7 out_10 decode_44 vdd gnd and3_dec -XDEC_AND_60 out_0 out_7 out_11 decode_60 vdd gnd and3_dec -XDEC_AND_1 out_1 out_4 out_8 decode_1 vdd gnd and3_dec -XDEC_AND_17 out_1 out_4 out_9 decode_17 vdd gnd and3_dec -XDEC_AND_33 out_1 out_4 out_10 decode_33 vdd gnd and3_dec -XDEC_AND_49 out_1 out_4 out_11 decode_49 vdd gnd and3_dec -XDEC_AND_5 out_1 out_5 out_8 decode_5 vdd gnd and3_dec -XDEC_AND_21 out_1 out_5 out_9 decode_21 vdd gnd and3_dec -XDEC_AND_37 out_1 out_5 out_10 decode_37 vdd gnd and3_dec -XDEC_AND_53 out_1 out_5 out_11 decode_53 vdd gnd and3_dec -XDEC_AND_9 out_1 out_6 out_8 decode_9 vdd gnd and3_dec -XDEC_AND_25 out_1 out_6 out_9 decode_25 vdd gnd and3_dec -XDEC_AND_41 out_1 out_6 out_10 decode_41 vdd gnd and3_dec -XDEC_AND_57 out_1 out_6 out_11 decode_57 vdd gnd and3_dec -XDEC_AND_13 out_1 out_7 out_8 decode_13 vdd gnd and3_dec -XDEC_AND_29 out_1 out_7 out_9 decode_29 vdd gnd and3_dec -XDEC_AND_45 out_1 out_7 out_10 decode_45 vdd gnd and3_dec -XDEC_AND_61 out_1 out_7 out_11 decode_61 vdd gnd and3_dec -XDEC_AND_2 out_2 out_4 out_8 decode_2 vdd gnd and3_dec -XDEC_AND_18 out_2 out_4 out_9 decode_18 vdd gnd and3_dec -XDEC_AND_34 out_2 out_4 out_10 decode_34 vdd gnd and3_dec -XDEC_AND_50 out_2 out_4 out_11 decode_50 vdd gnd and3_dec -XDEC_AND_6 out_2 out_5 out_8 decode_6 vdd gnd and3_dec -XDEC_AND_22 out_2 out_5 out_9 decode_22 vdd gnd and3_dec -XDEC_AND_38 out_2 out_5 out_10 decode_38 vdd gnd and3_dec -XDEC_AND_54 out_2 out_5 out_11 decode_54 vdd gnd and3_dec -XDEC_AND_10 out_2 out_6 out_8 decode_10 vdd gnd and3_dec -XDEC_AND_26 out_2 out_6 out_9 decode_26 vdd gnd and3_dec -XDEC_AND_42 out_2 out_6 out_10 decode_42 vdd gnd and3_dec -XDEC_AND_58 out_2 out_6 out_11 decode_58 vdd gnd and3_dec -XDEC_AND_14 out_2 out_7 out_8 decode_14 vdd gnd and3_dec -XDEC_AND_30 out_2 out_7 out_9 decode_30 vdd gnd and3_dec -XDEC_AND_46 out_2 out_7 out_10 decode_46 vdd gnd and3_dec -XDEC_AND_62 out_2 out_7 out_11 decode_62 vdd gnd and3_dec -XDEC_AND_3 out_3 out_4 out_8 decode_3 vdd gnd and3_dec -XDEC_AND_19 out_3 out_4 out_9 decode_19 vdd gnd and3_dec -XDEC_AND_35 out_3 out_4 out_10 decode_35 vdd gnd and3_dec -XDEC_AND_51 out_3 out_4 out_11 decode_51 vdd gnd and3_dec -XDEC_AND_7 out_3 out_5 out_8 decode_7 vdd gnd and3_dec -XDEC_AND_23 out_3 out_5 out_9 decode_23 vdd gnd and3_dec -XDEC_AND_39 out_3 out_5 out_10 decode_39 vdd gnd and3_dec -XDEC_AND_55 out_3 out_5 out_11 decode_55 vdd gnd and3_dec -XDEC_AND_11 out_3 out_6 out_8 decode_11 vdd gnd and3_dec -XDEC_AND_27 out_3 out_6 out_9 decode_27 vdd gnd and3_dec -XDEC_AND_43 out_3 out_6 out_10 decode_43 vdd gnd and3_dec -XDEC_AND_59 out_3 out_6 out_11 decode_59 vdd gnd and3_dec -XDEC_AND_15 out_3 out_7 out_8 decode_15 vdd gnd and3_dec -XDEC_AND_31 out_3 out_7 out_9 decode_31 vdd gnd and3_dec -XDEC_AND_47 out_3 out_7 out_10 decode_47 vdd gnd and3_dec -XDEC_AND_63 out_3 out_7 out_11 decode_63 vdd gnd and3_dec -.ENDS hierarchical_decoder - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I addr_5:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O wl_32:O wl_33:O wl_34:O wl_35:O wl_36:O wl_37:O wl_38:O wl_39:O wl_40:O wl_41:O wl_42:O wl_43:O wl_44:O wl_45:O wl_46:O wl_47:O wl_48:O wl_49:O wl_50:O wl_51:O wl_52:O wl_53:O wl_54:O wl_55:O wl_56:O wl_57:O wl_58:O wl_59:O wl_60:O wl_61:O wl_62:O wl_63:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : addr_5 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: wl_32 -* OUTPUT: wl_33 -* OUTPUT: wl_34 -* OUTPUT: wl_35 -* OUTPUT: wl_36 -* OUTPUT: wl_37 -* OUTPUT: wl_38 -* OUTPUT: wl_39 -* OUTPUT: wl_40 -* OUTPUT: wl_41 -* OUTPUT: wl_42 -* OUTPUT: wl_43 -* OUTPUT: wl_44 -* OUTPUT: wl_45 -* OUTPUT: wl_46 -* OUTPUT: wl_47 -* OUTPUT: wl_48 -* OUTPUT: wl_49 -* OUTPUT: wl_50 -* OUTPUT: wl_51 -* OUTPUT: wl_52 -* OUTPUT: wl_53 -* OUTPUT: wl_54 -* OUTPUT: wl_55 -* OUTPUT: wl_56 -* OUTPUT: wl_57 -* OUTPUT: wl_58 -* OUTPUT: wl_59 -* OUTPUT: wl_60 -* OUTPUT: wl_61 -* OUTPUT: wl_62 -* OUTPUT: wl_63 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 addr_5 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 dec_out_32 dec_out_33 dec_out_34 dec_out_35 dec_out_36 dec_out_37 dec_out_38 dec_out_39 dec_out_40 dec_out_41 dec_out_42 dec_out_43 dec_out_44 dec_out_45 dec_out_46 dec_out_47 dec_out_48 dec_out_49 dec_out_50 dec_out_51 dec_out_52 dec_out_53 dec_out_54 dec_out_55 dec_out_56 dec_out_57 dec_out_58 dec_out_59 dec_out_60 dec_out_61 dec_out_62 dec_out_63 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_32 wl_33 wl_34 wl_35 wl_36 wl_37 wl_38 wl_39 wl_40 wl_41 wl_42 wl_43 wl_44 wl_45 wl_46 wl_47 wl_48 wl_49 wl_50 wl_51 wl_52 wl_53 wl_54 wl_55 wl_56 wl_57 wl_58 wl_59 wl_60 wl_61 wl_62 wl_63 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O dout0_32:O dout0_33:O dout0_34:O dout0_35:O dout0_36:O dout0_37:O dout0_38:O dout0_39:O dout0_40:O dout0_41:O dout0_42:O dout0_43:O dout0_44:O dout0_45:O dout0_46:O dout0_47:O dout0_48:O dout0_49:O dout0_50:O dout0_51:O dout0_52:O dout0_53:O dout0_54:O dout0_55:O dout0_56:O dout0_57:O dout0_58:O dout0_59:O dout0_60:O dout0_61:O dout0_62:O dout0_63:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I din0_32:I din0_33:I din0_34:I din0_35:I din0_36:I din0_37:I din0_38:I din0_39:I din0_40:I din0_41:I din0_42:I din0_43:I din0_44:I din0_45:I din0_46:I din0_47:I din0_48:I din0_49:I din0_50:I din0_51:I din0_52:I din0_53:I din0_54:I din0_55:I din0_56:I din0_57:I din0_58:I din0_59:I din0_60:I din0_61:I din0_62:I din0_63:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I addr0_5:I addr0_6:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: dout0_2 -* OUTPUT: dout0_3 -* OUTPUT: dout0_4 -* OUTPUT: dout0_5 -* OUTPUT: dout0_6 -* OUTPUT: dout0_7 -* OUTPUT: dout0_8 -* OUTPUT: dout0_9 -* OUTPUT: dout0_10 -* OUTPUT: dout0_11 -* OUTPUT: dout0_12 -* OUTPUT: dout0_13 -* OUTPUT: dout0_14 -* OUTPUT: dout0_15 -* OUTPUT: dout0_16 -* OUTPUT: dout0_17 -* OUTPUT: dout0_18 -* OUTPUT: dout0_19 -* OUTPUT: dout0_20 -* OUTPUT: dout0_21 -* OUTPUT: dout0_22 -* OUTPUT: dout0_23 -* OUTPUT: dout0_24 -* OUTPUT: dout0_25 -* OUTPUT: dout0_26 -* OUTPUT: dout0_27 -* OUTPUT: dout0_28 -* OUTPUT: dout0_29 -* OUTPUT: dout0_30 -* OUTPUT: dout0_31 -* OUTPUT: dout0_32 -* OUTPUT: dout0_33 -* OUTPUT: dout0_34 -* OUTPUT: dout0_35 -* OUTPUT: dout0_36 -* OUTPUT: dout0_37 -* OUTPUT: dout0_38 -* OUTPUT: dout0_39 -* OUTPUT: dout0_40 -* OUTPUT: dout0_41 -* OUTPUT: dout0_42 -* OUTPUT: dout0_43 -* OUTPUT: dout0_44 -* OUTPUT: dout0_45 -* OUTPUT: dout0_46 -* OUTPUT: dout0_47 -* OUTPUT: dout0_48 -* OUTPUT: dout0_49 -* OUTPUT: dout0_50 -* OUTPUT: dout0_51 -* OUTPUT: dout0_52 -* OUTPUT: dout0_53 -* OUTPUT: dout0_54 -* OUTPUT: dout0_55 -* OUTPUT: dout0_56 -* OUTPUT: dout0_57 -* OUTPUT: dout0_58 -* OUTPUT: dout0_59 -* OUTPUT: dout0_60 -* OUTPUT: dout0_61 -* OUTPUT: dout0_62 -* OUTPUT: dout0_63 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : din0_2 -* INPUT : din0_3 -* INPUT : din0_4 -* INPUT : din0_5 -* INPUT : din0_6 -* INPUT : din0_7 -* INPUT : din0_8 -* INPUT : din0_9 -* INPUT : din0_10 -* INPUT : din0_11 -* INPUT : din0_12 -* INPUT : din0_13 -* INPUT : din0_14 -* INPUT : din0_15 -* INPUT : din0_16 -* INPUT : din0_17 -* INPUT : din0_18 -* INPUT : din0_19 -* INPUT : din0_20 -* INPUT : din0_21 -* INPUT : din0_22 -* INPUT : din0_23 -* INPUT : din0_24 -* INPUT : din0_25 -* INPUT : din0_26 -* INPUT : din0_27 -* INPUT : din0_28 -* INPUT : din0_29 -* INPUT : din0_30 -* INPUT : din0_31 -* INPUT : din0_32 -* INPUT : din0_33 -* INPUT : din0_34 -* INPUT : din0_35 -* INPUT : din0_36 -* INPUT : din0_37 -* INPUT : din0_38 -* INPUT : din0_39 -* INPUT : din0_40 -* INPUT : din0_41 -* INPUT : din0_42 -* INPUT : din0_43 -* INPUT : din0_44 -* INPUT : din0_45 -* INPUT : din0_46 -* INPUT : din0_47 -* INPUT : din0_48 -* INPUT : din0_49 -* INPUT : din0_50 -* INPUT : din0_51 -* INPUT : din0_52 -* INPUT : din0_53 -* INPUT : din0_54 -* INPUT : din0_55 -* INPUT : din0_56 -* INPUT : din0_57 -* INPUT : din0_58 -* INPUT : din0_59 -* INPUT : din0_60 -* INPUT : din0_61 -* INPUT : din0_62 -* INPUT : din0_63 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : addr0_4 -* INPUT : addr0_5 -* INPUT : addr0_6 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 bl_0_32 br_0_32 bl_0_33 br_0_33 bl_0_34 br_0_34 bl_0_35 br_0_35 bl_0_36 br_0_36 bl_0_37 br_0_37 bl_0_38 br_0_38 bl_0_39 br_0_39 bl_0_40 br_0_40 bl_0_41 br_0_41 bl_0_42 br_0_42 bl_0_43 br_0_43 bl_0_44 br_0_44 bl_0_45 br_0_45 bl_0_46 br_0_46 bl_0_47 br_0_47 bl_0_48 br_0_48 bl_0_49 br_0_49 bl_0_50 br_0_50 bl_0_51 br_0_51 bl_0_52 br_0_52 bl_0_53 br_0_53 bl_0_54 br_0_54 bl_0_55 br_0_55 bl_0_56 br_0_56 bl_0_57 br_0_57 bl_0_58 br_0_58 bl_0_59 br_0_59 bl_0_60 br_0_60 bl_0_61 br_0_61 bl_0_62 br_0_62 bl_0_63 br_0_63 bl_0_64 br_0_64 bl_0_65 br_0_65 bl_0_66 br_0_66 bl_0_67 br_0_67 bl_0_68 br_0_68 bl_0_69 br_0_69 bl_0_70 br_0_70 bl_0_71 br_0_71 bl_0_72 br_0_72 bl_0_73 br_0_73 bl_0_74 br_0_74 bl_0_75 br_0_75 bl_0_76 br_0_76 bl_0_77 br_0_77 bl_0_78 br_0_78 bl_0_79 br_0_79 bl_0_80 br_0_80 bl_0_81 br_0_81 bl_0_82 br_0_82 bl_0_83 br_0_83 bl_0_84 br_0_84 bl_0_85 br_0_85 bl_0_86 br_0_86 bl_0_87 br_0_87 bl_0_88 br_0_88 bl_0_89 br_0_89 bl_0_90 br_0_90 bl_0_91 br_0_91 bl_0_92 br_0_92 bl_0_93 br_0_93 bl_0_94 br_0_94 bl_0_95 br_0_95 bl_0_96 br_0_96 bl_0_97 br_0_97 bl_0_98 br_0_98 bl_0_99 br_0_99 bl_0_100 br_0_100 bl_0_101 br_0_101 bl_0_102 br_0_102 bl_0_103 br_0_103 bl_0_104 br_0_104 bl_0_105 br_0_105 bl_0_106 br_0_106 bl_0_107 br_0_107 bl_0_108 br_0_108 bl_0_109 br_0_109 bl_0_110 br_0_110 bl_0_111 br_0_111 bl_0_112 br_0_112 bl_0_113 br_0_113 bl_0_114 br_0_114 bl_0_115 br_0_115 bl_0_116 br_0_116 bl_0_117 br_0_117 bl_0_118 br_0_118 bl_0_119 br_0_119 bl_0_120 br_0_120 bl_0_121 br_0_121 bl_0_122 br_0_122 bl_0_123 br_0_123 bl_0_124 br_0_124 bl_0_125 br_0_125 bl_0_126 br_0_126 bl_0_127 br_0_127 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 dout0_32 dout0_33 dout0_34 dout0_35 dout0_36 dout0_37 dout0_38 dout0_39 dout0_40 dout0_41 dout0_42 dout0_43 dout0_44 dout0_45 dout0_46 dout0_47 dout0_48 dout0_49 dout0_50 dout0_51 dout0_52 dout0_53 dout0_54 dout0_55 dout0_56 dout0_57 dout0_58 dout0_59 dout0_60 dout0_61 dout0_62 dout0_63 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 din0_32 din0_33 din0_34 din0_35 din0_36 din0_37 din0_38 din0_39 din0_40 din0_41 din0_42 din0_43 din0_44 din0_45 din0_46 din0_47 din0_48 din0_49 din0_50 din0_51 din0_52 din0_53 din0_54 din0_55 din0_56 din0_57 din0_58 din0_59 din0_60 din0_61 din0_62 din0_63 sel0_0 sel0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_1 addr0_2 addr0_3 addr0_4 addr0_5 addr0_6 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 wl_0_35 wl_0_36 wl_0_37 wl_0_38 wl_0_39 wl_0_40 wl_0_41 wl_0_42 wl_0_43 wl_0_44 wl_0_45 wl_0_46 wl_0_47 wl_0_48 wl_0_49 wl_0_50 wl_0_51 wl_0_52 wl_0_53 wl_0_54 wl_0_55 wl_0_56 wl_0_57 wl_0_58 wl_0_59 wl_0_60 wl_0_61 wl_0_62 wl_0_63 rbl_wl0 vdd gnd port_address -Xcol_address_decoder0 addr0_0 sel0_0 sel0_1 vdd gnd pinvbuf -.ENDS bank - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_2 -Xdff_buf_inv2 Qb Q vdd gnd pinv_3 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_0 - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -.SUBCKT pinv_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p -.ENDS pinv_4 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_4 -.ENDS pdriver - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -* spice ptx M{0} {1} n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=67.2u l=0.4u pd=135.20u ps=135.20u as=67.20p ad=67.20p -Mpinv_nmos Z A gnd gnd n m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p -.ENDS pinv_11 - -* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p -.ENDS pinv_9 - -* spice ptx M{0} {1} n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=22.400000000000002u l=0.4u pd=45.60u ps=45.60u as=22.40p ad=22.40p -Mpinv_nmos Z A gnd gnd n m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -.ENDS pinv_10 - -* spice ptx M{0} {1} n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p - -* spice ptx M{0} {1} p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p - -.SUBCKT pinv_12 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=200.0u l=0.4u pd=400.80u ps=400.80u as=200.00p ad=200.00p -Mpinv_nmos Z A gnd gnd n m=1 w=100.0u l=0.4u pd=200.80u ps=200.80u as=100.00p ad=100.00p -.ENDS pinv_12 - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_7 - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_8 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 1, 2, 5, 14, 42, 125] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 -Xbuf_inv6 Zb5_int Zb6_int vdd gnd pinv_10 -Xbuf_inv7 Zb6_int Zb7_int vdd gnd pinv_11 -Xbuf_inv8 Zb7_int Z vdd gnd pinv_12 -.ENDS pdriver_0 - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3_0 - -* spice ptx M{0} {1} p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p - -* spice ptx M{0} {1} n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -.SUBCKT pinv_16 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=102.4u l=0.4u pd=205.60u ps=205.60u as=102.40p ad=102.40p -Mpinv_nmos Z A gnd gnd n m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -.ENDS pinv_16 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [64] -Xbuf_inv1 A Z vdd gnd pinv_16 -.ENDS pdriver_3 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -.SUBCKT pinv_17 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_17 - -* spice ptx M{0} {1} p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p - -* spice ptx M{0} {1} n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p - -.SUBCKT pinv_18 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=68.8u l=0.4u pd=138.40u ps=138.40u as=68.80p ad=68.80p -Mpinv_nmos Z A gnd gnd n m=1 w=34.4u l=0.4u pd=69.60u ps=69.60u as=34.40p ad=34.40p -.ENDS pinv_18 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 2, 5, 14, 43] -Xbuf_inv1 A Zb1_int vdd gnd pinv_7 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_7 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_8 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_9 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_10 -Xbuf_inv6 Zb5_int Z vdd gnd pinv_18 -.ENDS pdriver_4 - -* spice ptx M{0} {1} p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p - -* spice ptx M{0} {1} n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p - -.SUBCKT pinv_15 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=115.2u l=0.4u pd=231.20u ps=231.20u as=115.20p ad=115.20p -Mpinv_nmos Z A gnd gnd n m=1 w=57.6u l=0.4u pd=116.00u ps=116.00u as=57.60p ad=57.60p -.ENDS pinv_15 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [72] -Xbuf_inv1 A Z vdd gnd pinv_15 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT pinv_19 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_19 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_19 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_19 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_19 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_19 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_19 -Xdinv1 dout_1 dout_2 vdd gnd pinv_19 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_19 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_19 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_19 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_19 -Xdinv2 dout_2 dout_3 vdd gnd pinv_19 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_19 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_19 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_19 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_19 -Xdinv3 dout_3 dout_4 vdd gnd pinv_19 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_19 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_19 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_19 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_19 -Xdinv4 dout_4 dout_5 vdd gnd pinv_19 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_19 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_19 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_19 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_19 -Xdinv5 dout_5 dout_6 vdd gnd pinv_19 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_19 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_19 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_19 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_19 -Xdinv6 dout_6 dout_7 vdd gnd pinv_19 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_19 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_19 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_19 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_19 -Xdinv7 dout_7 dout_8 vdd gnd pinv_19 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_19 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_19 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_19 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_19 -Xdinv8 dout_8 out vdd gnd pinv_19 -Xdload_8_0 out n_8_0 vdd gnd pinv_19 -Xdload_8_1 out n_8_1 vdd gnd pinv_19 -Xdload_8_2 out n_8_2 vdd gnd pinv_19 -Xdload_8_3 out n_8_3 vdd gnd pinv_19 -.ENDS delay_chain - -* spice ptx M{0} {1} p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p - -* spice ptx M{0} {1} n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p - -.SUBCKT pinv_14 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=33.6u l=0.4u pd=68.00u ps=68.00u as=33.60p ad=33.60p -Mpinv_nmos Z A gnd gnd n m=1 w=16.8u l=0.4u pd=34.40u ps=34.40u as=16.80p ad=16.80p -.ENDS pinv_14 - -* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p - -.SUBCKT pinv_13 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p -.ENDS pinv_13 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [7, 21] -Xbuf_inv1 A Zb1_int vdd gnd pinv_13 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_14 -.ENDS pdriver_1 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_1 - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 64 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_17 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 -Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_17 -Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 -Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 -Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain -Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 -Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT sram_64_128_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] vdd gnd -*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I din0[32]:I din0[33]:I din0[34]:I din0[35]:I din0[36]:I din0[37]:I din0[38]:I din0[39]:I din0[40]:I din0[41]:I din0[42]:I din0[43]:I din0[44]:I din0[45]:I din0[46]:I din0[47]:I din0[48]:I din0[49]:I din0[50]:I din0[51]:I din0[52]:I din0[53]:I din0[54]:I din0[55]:I din0[56]:I din0[57]:I din0[58]:I din0[59]:I din0[60]:I din0[61]:I din0[62]:I din0[63]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I addr0[5]:I addr0[6]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O dout0[32]:O dout0[33]:O dout0[34]:O dout0[35]:O dout0[36]:O dout0[37]:O dout0[38]:O dout0[39]:O dout0[40]:O dout0[41]:O dout0[42]:O dout0[43]:O dout0[44]:O dout0[45]:O dout0[46]:O dout0[47]:O dout0[48]:O dout0[49]:O dout0[50]:O dout0[51]:O dout0[52]:O dout0[53]:O dout0[54]:O dout0[55]:O dout0[56]:O dout0[57]:O dout0[58]:O dout0[59]:O dout0[60]:O dout0[61]:O dout0[62]:O dout0[63]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : din0[2] -* INPUT : din0[3] -* INPUT : din0[4] -* INPUT : din0[5] -* INPUT : din0[6] -* INPUT : din0[7] -* INPUT : din0[8] -* INPUT : din0[9] -* INPUT : din0[10] -* INPUT : din0[11] -* INPUT : din0[12] -* INPUT : din0[13] -* INPUT : din0[14] -* INPUT : din0[15] -* INPUT : din0[16] -* INPUT : din0[17] -* INPUT : din0[18] -* INPUT : din0[19] -* INPUT : din0[20] -* INPUT : din0[21] -* INPUT : din0[22] -* INPUT : din0[23] -* INPUT : din0[24] -* INPUT : din0[25] -* INPUT : din0[26] -* INPUT : din0[27] -* INPUT : din0[28] -* INPUT : din0[29] -* INPUT : din0[30] -* INPUT : din0[31] -* INPUT : din0[32] -* INPUT : din0[33] -* INPUT : din0[34] -* INPUT : din0[35] -* INPUT : din0[36] -* INPUT : din0[37] -* INPUT : din0[38] -* INPUT : din0[39] -* INPUT : din0[40] -* INPUT : din0[41] -* INPUT : din0[42] -* INPUT : din0[43] -* INPUT : din0[44] -* INPUT : din0[45] -* INPUT : din0[46] -* INPUT : din0[47] -* INPUT : din0[48] -* INPUT : din0[49] -* INPUT : din0[50] -* INPUT : din0[51] -* INPUT : din0[52] -* INPUT : din0[53] -* INPUT : din0[54] -* INPUT : din0[55] -* INPUT : din0[56] -* INPUT : din0[57] -* INPUT : din0[58] -* INPUT : din0[59] -* INPUT : din0[60] -* INPUT : din0[61] -* INPUT : din0[62] -* INPUT : din0[63] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : addr0[4] -* INPUT : addr0[5] -* INPUT : addr0[6] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* OUTPUT: dout0[2] -* OUTPUT: dout0[3] -* OUTPUT: dout0[4] -* OUTPUT: dout0[5] -* OUTPUT: dout0[6] -* OUTPUT: dout0[7] -* OUTPUT: dout0[8] -* OUTPUT: dout0[9] -* OUTPUT: dout0[10] -* OUTPUT: dout0[11] -* OUTPUT: dout0[12] -* OUTPUT: dout0[13] -* OUTPUT: dout0[14] -* OUTPUT: dout0[15] -* OUTPUT: dout0[16] -* OUTPUT: dout0[17] -* OUTPUT: dout0[18] -* OUTPUT: dout0[19] -* OUTPUT: dout0[20] -* OUTPUT: dout0[21] -* OUTPUT: dout0[22] -* OUTPUT: dout0[23] -* OUTPUT: dout0[24] -* OUTPUT: dout0[25] -* OUTPUT: dout0[26] -* OUTPUT: dout0[27] -* OUTPUT: dout0[28] -* OUTPUT: dout0[29] -* OUTPUT: dout0[30] -* OUTPUT: dout0[31] -* OUTPUT: dout0[32] -* OUTPUT: dout0[33] -* OUTPUT: dout0[34] -* OUTPUT: dout0[35] -* OUTPUT: dout0[36] -* OUTPUT: dout0[37] -* OUTPUT: dout0[38] -* OUTPUT: dout0[39] -* OUTPUT: dout0[40] -* OUTPUT: dout0[41] -* OUTPUT: dout0[42] -* OUTPUT: dout0[43] -* OUTPUT: dout0[44] -* OUTPUT: dout0[45] -* OUTPUT: dout0[46] -* OUTPUT: dout0[47] -* OUTPUT: dout0[48] -* OUTPUT: dout0[49] -* OUTPUT: dout0[50] -* OUTPUT: dout0[51] -* OUTPUT: dout0[52] -* OUTPUT: dout0[53] -* OUTPUT: dout0[54] -* OUTPUT: dout0[55] -* OUTPUT: dout0[56] -* OUTPUT: dout0[57] -* OUTPUT: dout0[58] -* OUTPUT: dout0[59] -* OUTPUT: dout0[60] -* OUTPUT: dout0[61] -* OUTPUT: dout0[62] -* OUTPUT: dout0[63] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] dout0[32] dout0[33] dout0[34] dout0[35] dout0[36] dout0[37] dout0[38] dout0[39] dout0[40] dout0[41] dout0[42] dout0[43] dout0[44] dout0[45] dout0[46] dout0[47] dout0[48] dout0[49] dout0[50] dout0[51] dout0[52] dout0[53] dout0[54] dout0[55] dout0[56] dout0[57] dout0[58] dout0[59] dout0[60] dout0[61] dout0[62] dout0[63] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 a0_0 a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[1] addr0[2] addr0[3] addr0[4] addr0[5] addr0[6] a0_1 a0_2 a0_3 a0_4 a0_5 a0_6 clk_buf0 vdd gnd row_addr_dff -Xcol_address0 addr0[0] a0_0 clk_buf0 vdd gnd col_addr_dff -Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] din0[32] din0[33] din0[34] din0[35] din0[36] din0[37] din0[38] din0[39] din0[40] din0[41] din0[42] din0[43] din0[44] din0[45] din0[46] din0[47] din0[48] din0[49] din0[50] din0[51] din0[52] din0[53] din0[54] din0[55] din0[56] din0[57] din0[58] din0[59] din0[60] din0[61] din0[62] din0[63] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 bank_din0_32 bank_din0_33 bank_din0_34 bank_din0_35 bank_din0_36 bank_din0_37 bank_din0_38 bank_din0_39 bank_din0_40 bank_din0_41 bank_din0_42 bank_din0_43 bank_din0_44 bank_din0_45 bank_din0_46 bank_din0_47 bank_din0_48 bank_din0_49 bank_din0_50 bank_din0_51 bank_din0_52 bank_din0_53 bank_din0_54 bank_din0_55 bank_din0_56 bank_din0_57 bank_din0_58 bank_din0_59 bank_din0_60 bank_din0_61 bank_din0_62 bank_din0_63 clk_buf0 vdd gnd data_dff -.ENDS sram_64_128_scn4m_subm diff --git a/2x16/delay_sram_2_16_scn4m_subm.sp b/2x16/delay_sram_2_16_scn4m_subm.sp deleted file mode 100644 index 33a1cce7..00000000 --- a/2x16/delay_sram_2_16_scn4m_subm.sp +++ /dev/null @@ -1,1162 +0,0 @@ -************************************************** -* OpenRAM generated memory with exclusively delay based logic -* Words: 16 -* Data bits: 2 -* Banks: 1 -* Column mux: 1:1 -* Trimmed: False -* LVS: False -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I dout_0:O dout_1:O dout_2:O dout_3:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 4 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -.ENDS row_addr_dff - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* POWER : vdd -* GROUND: gnd -* rows: 16 cols: 2 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -.ENDS bitcell_array - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 vdd gnd dummy_array -Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_1 -Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* INPUT : en_bar -* POWER : vdd -* cols: 3 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 1 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -.ENDS sense_amp_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd -*.PININFO data_0:I data_1:I bl_0:O br_0:O bl_1:O br_1:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver -.ENDS write_driver_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 dout_0 dout_1 din_0 din_1 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B dout_0:O dout_1:O din_0:I din_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 bl_0 br_0 bl_1 br_1 w_en vdd gnd write_driver_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2 - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 -XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec -XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec -XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec -XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec -XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec -XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec -XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec -XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec -XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec -XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec -XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec -XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec -XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec -XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec -XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec -XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec -.ENDS hierarchical_decoder - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec_0 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 16 cols: 2 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -.ENDS wordline_driver_array - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 rbl_bl_0_0 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O rbl_bl_0_0:O din0_0:I din0_1:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 dout0_0 dout0_1 din0_0 din0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 rbl_wl0 vdd gnd port_address -.ENDS bank - -* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p - -* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p -.ENDS pinv_7 - -.SUBCKT pinv_5 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_5 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 5] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_7 -.ENDS pdriver_1 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_1 - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p -.ENDS pinv_2 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_2 -.ENDS pdriver - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_0 - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_11 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_6 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_6 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [2] -Xbuf_inv1 A Z vdd gnd pinv_6 -.ENDS pdriver_3 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3_0 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -* spice ptx M{0} {1} p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p - -* spice ptx M{0} {1} n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p -Mpinv_nmos Z A gnd gnd n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p -.ENDS pinv_8 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 2, 5, 15] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Z vdd gnd pinv_8 -.ENDS pdriver_0 - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_1 - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_0 - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_0 -Xdff_buf_inv2 Qb Q vdd gnd pinv_1 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_10 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_5 -.ENDS pdriver_4 - -* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p - -* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p -Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -.ENDS pinv_9 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [10] -Xbuf_inv1 A Z vdd gnd pinv_9 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -* Used for tiling delay chain to desired length -.SUBCKT delay_chain_segment in out vdd gnd -Xdinv0 in dout_1 vdd gnd pinv_11 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 -Xdinv1 dout_1 out vdd gnd pinv_11 -Xdload_1_0 out n_1_0 vdd gnd pinv_11 -Xdload_1_1 out n_1_1 vdd gnd pinv_11 -Xdload_1_2 out n_1_2 vdd gnd pinv_11 -Xdload_1_3 out n_1_3 vdd gnd pinv_11 -.ENDS delay_chain_segment - -.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd -Xdelay1 in out1 vdd gnd delay_chain_segment -Xdelay2 out1 out2 vdd gnd delay_chain_segment -Xdelay3 out2 out3 vdd gnd delay_chain_segment -Xdelay4 out3 out4 vdd gnd delay_chain_segment -Xdelay5 out4 out5 vdd gnd delay_chain_segment -Xdelay6 out5 out6 vdd gnd delay_chain_segment -Xdelay7 out6 out7 vdd gnd delay_chain_segment -Xdelay8 out7 out8 vdd gnd delay_chain_segment -Xdelay9 out8 out9 vdd gnd delay_chain_segment -Xdelay10 out9 out10 vdd gnd delay_chain_segment -Xdelay11 out10 out11 vdd gnd delay_chain_segment -Xdelay12 out11 out12 vdd gnd delay_chain_segment -Xdelay13 out12 out13 vdd gnd delay_chain_segment -Xdelay14 out13 out14 vdd gnd delay_chain_segment -Xdelay15 out14 out15 vdd gnd delay_chain_segment -Xdelay16 out15 out16 vdd gnd delay_chain_segment -.ENDS multi_delay_chain - -.SUBCKT glitch_generator in glitch1_bar glitch2_bar glitch3_bar vdd gnd -*.PININFO in:I glitch1_bar:O glitch2_bar:O glitch3_bar:O vdd:B gnd:B -Xmulti_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain -Xinv_g1 out6 g1_end vdd gnd pinv_11 -Xinv_g2 out7 g2_end vdd gnd pinv_11 -Xinv_g3 out16 g3_end vdd gnd pinv_11 -Xnand2_g1 out2 g1_end glitch1_bar vdd gnd pnand2 -Xnand2_g2 in g2_end glitch2_bar vdd gnd pnand2 -Xnand2_g3 out6 g3_end glitch3_bar vdd gnd pnand2 -.ENDS glitch_generator - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl (NO LONGER USED) -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -* is cs_buf needed on larger memories? -Xbuf_cs cs cs_buf vdd gnd pdriver_0 -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xglitch_generator gated_clk_buf glitch1_bar glitch2_bar glitch3_bar vdd gnd glitch_generator -Xinv_g3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 -Xand_s_en we_bar gated_clk_bar glitch3_bar s_en vdd gnd pand3 -Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 -Xand_wl_en cs_buf glitch2_bar wl_en vdd gnd pand2 -Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 2 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -.ENDS data_dff - -.SUBCKT sram_2_16_scn4m_subm din0[0] din0[1] addr0[0] addr0[1] addr0[2] addr0[3] csb0 web0 clk0 dout0[0] dout0[1] vdd gnd -*.PININFO din0[0]:I din0[1]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] rbl_bl0 bank_din0_0 bank_din0_1 a0_0 a0_1 a0_2 a0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] a0_0 a0_1 a0_2 a0_3 clk_buf0 vdd gnd row_addr_dff -Xdata_dff0 din0[0] din0[1] bank_din0_0 bank_din0_1 clk_buf0 vdd gnd data_dff -.ENDS sram_2_16_scn4m_subm diff --git a/2x16/sram_2_16_scn4m_subm.html b/2x16/sram_2_16_scn4m_subm.html deleted file mode 100644 index 7a189353..00000000 --- a/2x16/sram_2_16_scn4m_subm.html +++ /dev/null @@ -1,35 +0,0 @@ - - -VLSIDAOpenRAM

sram_2_16_scn4m_subm.html

Compiled at: 2022-01-19

DRC errors: skipped

LVS errors: skipped

Git commit id: 06d391b3e365127628434b98044035232615f4b0

Ports and Configuration

TypeValue
WORD_SIZE2
NUM_WORDS16
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0
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Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)200MHz
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Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[1:0] setup rising0.0090.009ns
din0[1:0] setup falling0.0090.009ns
din0[1:0] hold rising0.0010.001ns
din0[1:0] hold falling0.0010.001ns
dout0[1:0] cell rise1.2571.347ns
dout0[1:0] cell fall1.2571.347ns
dout0[1:0] rise transition0.0060.015ns
dout0[1:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[3:0] setup rising0.0090.009ns
addr0[3:0] setup falling0.0090.009ns
addr0[3:0] hold rising0.0010.001ns
addr0[3:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns
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Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising3.4010mW
!csb0 & clk0 & !web0Read Falling3.4010mW
!csb0 & !clk0 & web0Write Rising3.4010mW
!csb0 & !clk0 & web0Write Falling3.4010mW
csb0leakage0.000194mW
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Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib
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Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_2_16_scn4m_subm.html
.libSynthesis modelssram_2_16_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_2_16_scn4m_subm.log
.pyOpenRAM configuration filesram_2_16_scn4m_subm.py
.spSPICE netlistssram_2_16_scn4m_subm.sp
.vVerilog simulation modelssram_2_16_scn4m_subm.v
diff --git a/2x16/sram_2_16_scn4m_subm.lvs.sp b/2x16/sram_2_16_scn4m_subm.lvs.sp deleted file mode 100644 index 61329998..00000000 --- a/2x16/sram_2_16_scn4m_subm.lvs.sp +++ /dev/null @@ -1,1171 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 16 -* Data bits: 2 -* Banks: 1 -* Column mux: 1:1 -* Trimmed: False -* LVS: True -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I dout_0:O dout_1:O dout_2:O dout_3:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 4 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -.ENDS row_addr_dff - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* POWER : vdd -* GROUND: gnd -* rows: 16 cols: 2 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -.ENDS bitcell_array - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 vdd gnd dummy_array -Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_1 -Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* INPUT : en_bar -* POWER : vdd -* cols: 3 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 1 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -.ENDS sense_amp_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd -*.PININFO data_0:I data_1:I bl_0:O br_0:O bl_1:O br_1:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver -.ENDS write_driver_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 dout_0 dout_1 din_0 din_1 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B dout_0:O dout_1:O din_0:I din_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 bl_0 br_0 bl_1 br_1 w_en vdd gnd write_driver_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2 - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 -XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec -XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec -XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec -XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec -XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec -XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec -XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec -XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec -XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec -XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec -XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec -XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec -XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec -XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec -XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec -XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec -.ENDS hierarchical_decoder - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec_0 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 16 cols: 2 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -.ENDS wordline_driver_array - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 rbl_bl_0_0 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O rbl_bl_0_0:O din0_0:I din0_1:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 dout0_0 dout0_1 din0_0 din0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 rbl_wl0 vdd gnd port_address -.ENDS bank - -* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p - -* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u -.ENDS pinv_7 - -.SUBCKT pinv_5 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_5 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 5] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_7 -.ENDS pdriver_1 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2_1 - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u -.ENDS pinv_2 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_2 -.ENDS pdriver - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2_0 - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_11 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_11 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 -Xdinv1 dout_1 dout_2 vdd gnd pinv_11 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_11 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_11 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_11 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_11 -Xdinv2 dout_2 dout_3 vdd gnd pinv_11 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_11 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_11 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_11 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_11 -Xdinv3 dout_3 dout_4 vdd gnd pinv_11 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_11 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_11 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_11 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_11 -Xdinv4 dout_4 dout_5 vdd gnd pinv_11 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_11 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_11 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_11 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_11 -Xdinv5 dout_5 dout_6 vdd gnd pinv_11 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_11 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_11 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_11 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_11 -Xdinv6 dout_6 dout_7 vdd gnd pinv_11 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_11 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_11 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_11 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_11 -Xdinv7 dout_7 dout_8 vdd gnd pinv_11 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_11 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_11 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_11 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_11 -Xdinv8 dout_8 out vdd gnd pinv_11 -Xdload_8_0 out n_8_0 vdd gnd pinv_11 -Xdload_8_1 out n_8_1 vdd gnd pinv_11 -Xdload_8_2 out n_8_2 vdd gnd pinv_11 -Xdload_8_3 out n_8_3 vdd gnd pinv_11 -.ENDS delay_chain - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_6 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pinv_6 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [2] -Xbuf_inv1 A Z vdd gnd pinv_6 -.ENDS pdriver_3 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand3_0 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -* spice ptx M{0} {1} p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p - -* spice ptx M{0} {1} n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=24.0u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=12.0u l=0.4u -.ENDS pinv_8 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 2, 5, 15] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Z vdd gnd pinv_8 -.ENDS pdriver_0 - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u -.ENDS pinv_1 - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pinv_0 - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_0 -Xdff_buf_inv2 Qb Q vdd gnd pinv_1 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_10 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_5 -.ENDS pdriver_4 - -* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p - -* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u -.ENDS pinv_9 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [10] -Xbuf_inv1 A Z vdd gnd pinv_9 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 -Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_10 -Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 -Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 -Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain -Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 -Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 2 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -.ENDS data_dff - -.SUBCKT sram_2_16_scn4m_subm din0[0] din0[1] addr0[0] addr0[1] addr0[2] addr0[3] csb0 web0 clk0 dout0[0] dout0[1] vdd gnd -*.PININFO din0[0]:I din0[1]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] rbl_bl0 bank_din0_0 bank_din0_1 a0_0 a0_1 a0_2 a0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] a0_0 a0_1 a0_2 a0_3 clk_buf0 vdd gnd row_addr_dff -Xdata_dff0 din0[0] din0[1] bank_din0_0 bank_din0_1 clk_buf0 vdd gnd data_dff -.ENDS sram_2_16_scn4m_subm diff --git a/2x16/sram_2_16_scn4m_subm.sp b/2x16/sram_2_16_scn4m_subm.sp deleted file mode 100644 index fd519df6..00000000 --- a/2x16/sram_2_16_scn4m_subm.sp +++ /dev/null @@ -1,1171 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 16 -* Data bits: 2 -* Banks: 1 -* Column mux: 1:1 -* Trimmed: False -* LVS: False -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I dout_0:O dout_1:O dout_2:O dout_3:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 4 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -.ENDS row_addr_dff - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* POWER : vdd -* GROUND: gnd -* rows: 16 cols: 2 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -.ENDS bitcell_array - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl_0_0 vdd gnd dummy_array -Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_1 -Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* INPUT : en_bar -* POWER : vdd -* cols: 3 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 1 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -.ENDS sense_amp_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd -*.PININFO data_0:I data_1:I bl_0:O br_0:O bl_1:O br_1:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver -.ENDS write_driver_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 dout_0 dout_1 din_0 din_1 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B dout_0:O dout_1:O din_0:I din_1:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 bl_0 br_0 bl_1 br_1 w_en vdd gnd write_driver_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2 - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd hierarchical_predecode2x4 -XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec -XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec -XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec -XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec -XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec -XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec -XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec -XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec -XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec -XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec -XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec -XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec -XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec -XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec -XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec -XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec -.ENDS hierarchical_decoder - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec_0 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 16 cols: 2 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -.ENDS wordline_driver_array - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 rbl_bl_0_0 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O rbl_bl_0_0:O din0_0:I din0_1:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 dout0_0 dout0_1 din0_0 din0_1 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 rbl_wl0 vdd gnd port_address -.ENDS bank - -* spice ptx M{0} {1} n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p - -* spice ptx M{0} {1} p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -Mpinv_nmos Z A gnd gnd n m=1 w=4.0u l=0.4u pd=8.80u ps=8.80u as=4.00p ad=4.00p -.ENDS pinv_7 - -.SUBCKT pinv_5 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_5 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 5] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_7 -.ENDS pdriver_1 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_1 - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p -.ENDS pinv_2 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_2 -.ENDS pdriver - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_0 - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_11 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_11 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 -Xdinv1 dout_1 dout_2 vdd gnd pinv_11 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_11 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_11 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_11 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_11 -Xdinv2 dout_2 dout_3 vdd gnd pinv_11 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_11 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_11 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_11 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_11 -Xdinv3 dout_3 dout_4 vdd gnd pinv_11 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_11 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_11 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_11 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_11 -Xdinv4 dout_4 dout_5 vdd gnd pinv_11 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_11 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_11 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_11 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_11 -Xdinv5 dout_5 dout_6 vdd gnd pinv_11 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_11 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_11 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_11 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_11 -Xdinv6 dout_6 dout_7 vdd gnd pinv_11 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_11 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_11 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_11 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_11 -Xdinv7 dout_7 dout_8 vdd gnd pinv_11 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_11 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_11 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_11 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_11 -Xdinv8 dout_8 out vdd gnd pinv_11 -Xdload_8_0 out n_8_0 vdd gnd pinv_11 -Xdload_8_1 out n_8_1 vdd gnd pinv_11 -Xdload_8_2 out n_8_2 vdd gnd pinv_11 -Xdload_8_3 out n_8_3 vdd gnd pinv_11 -.ENDS delay_chain - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_6 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_6 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [2] -Xbuf_inv1 A Z vdd gnd pinv_6 -.ENDS pdriver_3 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3_0 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -* spice ptx M{0} {1} p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p - -* spice ptx M{0} {1} n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=24.0u l=0.4u pd=48.80u ps=48.80u as=24.00p ad=24.00p -Mpinv_nmos Z A gnd gnd n m=1 w=12.0u l=0.4u pd=24.80u ps=24.80u as=12.00p ad=12.00p -.ENDS pinv_8 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 2, 5, 15] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Z vdd gnd pinv_8 -.ENDS pdriver_0 - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_1 - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_0 - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_0 -Xdff_buf_inv2 Qb Q vdd gnd pinv_1 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_10 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1] -Xbuf_inv1 A Zb1_int vdd gnd pinv_5 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_5 -.ENDS pdriver_4 - -* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p - -* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p -Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -.ENDS pinv_9 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [10] -Xbuf_inv1 A Z vdd gnd pinv_9 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 -Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_10 -Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 -Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 -Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain -Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 -Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 2 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -.ENDS data_dff - -.SUBCKT sram_2_16_scn4m_subm din0[0] din0[1] addr0[0] addr0[1] addr0[2] addr0[3] csb0 web0 clk0 dout0[0] dout0[1] vdd gnd -*.PININFO din0[0]:I din0[1]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] rbl_bl0 bank_din0_0 bank_din0_1 a0_0 a0_1 a0_2 a0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] a0_0 a0_1 a0_2 a0_3 clk_buf0 vdd gnd row_addr_dff -Xdata_dff0 din0[0] din0[1] bank_din0_0 bank_din0_1 clk_buf0 vdd gnd data_dff -.ENDS sram_2_16_scn4m_subm diff --git a/32x32/delay_sram_32_32_scn4m_subm.sp b/32x32/delay_sram_32_32_scn4m_subm.sp deleted file mode 100644 index bc30863f..00000000 --- a/32x32/delay_sram_32_32_scn4m_subm.sp +++ /dev/null @@ -1,3590 +0,0 @@ -************************************************** -* OpenRAM generated memory: delay version -* Words: 32 -* Data bits: 32 -* Banks: 1 -* Column mux: 1:1 -* Trimmed: False -* LVS: False -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 dout_0 dout_1 dout_2 dout_3 dout_4 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 5 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff -.ENDS row_addr_dff - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* POWER : vdd -* GROUND: gnd -* rows: 32 cols: 32 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw -.ENDS bitcell_array - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw -Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw -Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw -Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw -Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw -Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw -Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw -Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw -Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw -Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw -Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw -Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw -Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw -Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw -Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw -Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw -Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 vdd gnd dummy_array -Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_1 -Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 en vdd gnd -*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* INPUT : data_2 -* INPUT : data_3 -* INPUT : data_4 -* INPUT : data_5 -* INPUT : data_6 -* INPUT : data_7 -* INPUT : data_8 -* INPUT : data_9 -* INPUT : data_10 -* INPUT : data_11 -* INPUT : data_12 -* INPUT : data_13 -* INPUT : data_14 -* INPUT : data_15 -* INPUT : data_16 -* INPUT : data_17 -* INPUT : data_18 -* INPUT : data_19 -* INPUT : data_20 -* INPUT : data_21 -* INPUT : data_22 -* INPUT : data_23 -* INPUT : data_24 -* INPUT : data_25 -* INPUT : data_26 -* INPUT : data_27 -* INPUT : data_28 -* INPUT : data_29 -* INPUT : data_30 -* INPUT : data_31 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 32 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver -Xwrite_driver2 data_2 bl_2 br_2 en vdd gnd write_driver -Xwrite_driver3 data_3 bl_3 br_3 en vdd gnd write_driver -Xwrite_driver4 data_4 bl_4 br_4 en vdd gnd write_driver -Xwrite_driver5 data_5 bl_5 br_5 en vdd gnd write_driver -Xwrite_driver6 data_6 bl_6 br_6 en vdd gnd write_driver -Xwrite_driver7 data_7 bl_7 br_7 en vdd gnd write_driver -Xwrite_driver8 data_8 bl_8 br_8 en vdd gnd write_driver -Xwrite_driver9 data_9 bl_9 br_9 en vdd gnd write_driver -Xwrite_driver10 data_10 bl_10 br_10 en vdd gnd write_driver -Xwrite_driver11 data_11 bl_11 br_11 en vdd gnd write_driver -Xwrite_driver12 data_12 bl_12 br_12 en vdd gnd write_driver -Xwrite_driver13 data_13 bl_13 br_13 en vdd gnd write_driver -Xwrite_driver14 data_14 bl_14 br_14 en vdd gnd write_driver -Xwrite_driver15 data_15 bl_15 br_15 en vdd gnd write_driver -Xwrite_driver16 data_16 bl_16 br_16 en vdd gnd write_driver -Xwrite_driver17 data_17 bl_17 br_17 en vdd gnd write_driver -Xwrite_driver18 data_18 bl_18 br_18 en vdd gnd write_driver -Xwrite_driver19 data_19 bl_19 br_19 en vdd gnd write_driver -Xwrite_driver20 data_20 bl_20 br_20 en vdd gnd write_driver -Xwrite_driver21 data_21 bl_21 br_21 en vdd gnd write_driver -Xwrite_driver22 data_22 bl_22 br_22 en vdd gnd write_driver -Xwrite_driver23 data_23 bl_23 br_23 en vdd gnd write_driver -Xwrite_driver24 data_24 bl_24 br_24 en vdd gnd write_driver -Xwrite_driver25 data_25 bl_25 br_25 en vdd gnd write_driver -Xwrite_driver26 data_26 bl_26 br_26 en vdd gnd write_driver -Xwrite_driver27 data_27 bl_27 br_27 en vdd gnd write_driver -Xwrite_driver28 data_28 bl_28 br_28 en vdd gnd write_driver -Xwrite_driver29 data_29 bl_29 br_29 en vdd gnd write_driver -Xwrite_driver30 data_30 bl_30 br_30 en vdd gnd write_driver -Xwrite_driver31 data_31 bl_31 br_31 en vdd gnd write_driver -.ENDS write_driver_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* INPUT : en_bar -* POWER : vdd -* cols: 33 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 -Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 -Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 -Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 -Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 -Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 -Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 -Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 -Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 -Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 -Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 -Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 -Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 -Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 -Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 -Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 -Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 -Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 -Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 -Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 -Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 -Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 -Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 -Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 -Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 -Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 -Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 -Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 -Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 -Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* OUTPUT: data_2 -* INPUT : bl_2 -* INPUT : br_2 -* OUTPUT: data_3 -* INPUT : bl_3 -* INPUT : br_3 -* OUTPUT: data_4 -* INPUT : bl_4 -* INPUT : br_4 -* OUTPUT: data_5 -* INPUT : bl_5 -* INPUT : br_5 -* OUTPUT: data_6 -* INPUT : bl_6 -* INPUT : br_6 -* OUTPUT: data_7 -* INPUT : bl_7 -* INPUT : br_7 -* OUTPUT: data_8 -* INPUT : bl_8 -* INPUT : br_8 -* OUTPUT: data_9 -* INPUT : bl_9 -* INPUT : br_9 -* OUTPUT: data_10 -* INPUT : bl_10 -* INPUT : br_10 -* OUTPUT: data_11 -* INPUT : bl_11 -* INPUT : br_11 -* OUTPUT: data_12 -* INPUT : bl_12 -* INPUT : br_12 -* OUTPUT: data_13 -* INPUT : bl_13 -* INPUT : br_13 -* OUTPUT: data_14 -* INPUT : bl_14 -* INPUT : br_14 -* OUTPUT: data_15 -* INPUT : bl_15 -* INPUT : br_15 -* OUTPUT: data_16 -* INPUT : bl_16 -* INPUT : br_16 -* OUTPUT: data_17 -* INPUT : bl_17 -* INPUT : br_17 -* OUTPUT: data_18 -* INPUT : bl_18 -* INPUT : br_18 -* OUTPUT: data_19 -* INPUT : bl_19 -* INPUT : br_19 -* OUTPUT: data_20 -* INPUT : bl_20 -* INPUT : br_20 -* OUTPUT: data_21 -* INPUT : bl_21 -* INPUT : br_21 -* OUTPUT: data_22 -* INPUT : bl_22 -* INPUT : br_22 -* OUTPUT: data_23 -* INPUT : bl_23 -* INPUT : br_23 -* OUTPUT: data_24 -* INPUT : bl_24 -* INPUT : br_24 -* OUTPUT: data_25 -* INPUT : bl_25 -* INPUT : br_25 -* OUTPUT: data_26 -* INPUT : bl_26 -* INPUT : br_26 -* OUTPUT: data_27 -* INPUT : bl_27 -* INPUT : br_27 -* OUTPUT: data_28 -* INPUT : bl_28 -* INPUT : br_28 -* OUTPUT: data_29 -* INPUT : bl_29 -* INPUT : br_29 -* OUTPUT: data_30 -* INPUT : bl_30 -* INPUT : br_30 -* OUTPUT: data_31 -* INPUT : bl_31 -* INPUT : br_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 1 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp -Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp -Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp -Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp -Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp -Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp -Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp -Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp -Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp -Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp -Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp -Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp -Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp -Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp -Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp -Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp -Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp -Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp -Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp -Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp -Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp -Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp -Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp -Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp -Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp -Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp -Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp -Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp -Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp -Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp -.ENDS sense_amp_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 dout_2 bl_2 br_2 dout_3 bl_3 br_3 dout_4 bl_4 br_4 dout_5 bl_5 br_5 dout_6 bl_6 br_6 dout_7 bl_7 br_7 dout_8 bl_8 br_8 dout_9 bl_9 br_9 dout_10 bl_10 br_10 dout_11 bl_11 br_11 dout_12 bl_12 br_12 dout_13 bl_13 br_13 dout_14 bl_14 br_14 dout_15 bl_15 br_15 dout_16 bl_16 br_16 dout_17 bl_17 br_17 dout_18 bl_18 br_18 dout_19 bl_19 br_19 dout_20 bl_20 br_20 dout_21 bl_21 br_21 dout_22 bl_22 br_22 dout_23 bl_23 br_23 dout_24 bl_24 br_24 dout_25 bl_25 br_25 dout_26 bl_26 br_26 dout_27 bl_27 br_27 dout_28 bl_28 br_28 dout_29 bl_29 br_29 dout_30 bl_30 br_30 dout_31 bl_31 br_31 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 w_en vdd gnd write_driver_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p -Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -.ENDS pinv_0 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv_0 -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* INPUT : in_16 -* INPUT : in_17 -* INPUT : in_18 -* INPUT : in_19 -* INPUT : in_20 -* INPUT : in_21 -* INPUT : in_22 -* INPUT : in_23 -* INPUT : in_24 -* INPUT : in_25 -* INPUT : in_26 -* INPUT : in_27 -* INPUT : in_28 -* INPUT : in_29 -* INPUT : in_30 -* INPUT : in_31 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 32 cols: 32 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver -Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver -Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver -Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver -Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver -Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver -Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver -Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver -Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver -Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver -Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver -Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver -Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver -Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver -Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver -Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver -.ENDS wordline_driver_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3 - -.SUBCKT and3_dec A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand3_dec_nand A B C zb_int vdd gnd pnand3 -Xpand3_dec_inv zb_int Z vdd gnd pinv -.ENDS and3_dec - -.SUBCKT hierarchical_predecode3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd -*.PININFO in_0:I in_1:I in_2:I out_0:O out_1:O out_2:O out_3:O out_4:O out_5:O out_6:O out_7:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* OUTPUT: out_4 -* OUTPUT: out_5 -* OUTPUT: out_6 -* OUTPUT: out_7 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -Xpre_inv_2 in_2 inbar_2 vdd gnd pinv -XXpre3x8_and_0 inbar_0 inbar_1 inbar_2 out_0 vdd gnd and3_dec -XXpre3x8_and_1 in_0 inbar_1 inbar_2 out_1 vdd gnd and3_dec -XXpre3x8_and_2 inbar_0 in_1 inbar_2 out_2 vdd gnd and3_dec -XXpre3x8_and_3 in_0 in_1 inbar_2 out_3 vdd gnd and3_dec -XXpre3x8_and_4 inbar_0 inbar_1 in_2 out_4 vdd gnd and3_dec -XXpre3x8_and_5 in_0 inbar_1 in_2 out_5 vdd gnd and3_dec -XXpre3x8_and_6 inbar_0 in_1 in_2 out_6 vdd gnd and3_dec -XXpre3x8_and_7 in_0 in_1 in_2 out_7 vdd gnd and3_dec -.ENDS hierarchical_predecode3x8 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* OUTPUT: decode_16 -* OUTPUT: decode_17 -* OUTPUT: decode_18 -* OUTPUT: decode_19 -* OUTPUT: decode_20 -* OUTPUT: decode_21 -* OUTPUT: decode_22 -* OUTPUT: decode_23 -* OUTPUT: decode_24 -* OUTPUT: decode_25 -* OUTPUT: decode_26 -* OUTPUT: decode_27 -* OUTPUT: decode_28 -* OUTPUT: decode_29 -* OUTPUT: decode_30 -* OUTPUT: decode_31 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre3x8_0 addr_2 addr_3 addr_4 out_4 out_5 out_6 out_7 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode3x8 -XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec -XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec -XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec -XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec -XDEC_AND_16 out_0 out_8 decode_16 vdd gnd and2_dec -XDEC_AND_20 out_0 out_9 decode_20 vdd gnd and2_dec -XDEC_AND_24 out_0 out_10 decode_24 vdd gnd and2_dec -XDEC_AND_28 out_0 out_11 decode_28 vdd gnd and2_dec -XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec -XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec -XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec -XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec -XDEC_AND_17 out_1 out_8 decode_17 vdd gnd and2_dec -XDEC_AND_21 out_1 out_9 decode_21 vdd gnd and2_dec -XDEC_AND_25 out_1 out_10 decode_25 vdd gnd and2_dec -XDEC_AND_29 out_1 out_11 decode_29 vdd gnd and2_dec -XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec -XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec -XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec -XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec -XDEC_AND_18 out_2 out_8 decode_18 vdd gnd and2_dec -XDEC_AND_22 out_2 out_9 decode_22 vdd gnd and2_dec -XDEC_AND_26 out_2 out_10 decode_26 vdd gnd and2_dec -XDEC_AND_30 out_2 out_11 decode_30 vdd gnd and2_dec -XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec -XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec -XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec -XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec -XDEC_AND_19 out_3 out_8 decode_19 vdd gnd and2_dec -XDEC_AND_23 out_3 out_9 decode_23 vdd gnd and2_dec -XDEC_AND_27 out_3 out_10 decode_27 vdd gnd and2_dec -XDEC_AND_31 out_3 out_11 decode_31 vdd gnd and2_dec -.ENDS hierarchical_decoder - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 8 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv_0 -.ENDS and2_dec_0 - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: dout0_2 -* OUTPUT: dout0_3 -* OUTPUT: dout0_4 -* OUTPUT: dout0_5 -* OUTPUT: dout0_6 -* OUTPUT: dout0_7 -* OUTPUT: dout0_8 -* OUTPUT: dout0_9 -* OUTPUT: dout0_10 -* OUTPUT: dout0_11 -* OUTPUT: dout0_12 -* OUTPUT: dout0_13 -* OUTPUT: dout0_14 -* OUTPUT: dout0_15 -* OUTPUT: dout0_16 -* OUTPUT: dout0_17 -* OUTPUT: dout0_18 -* OUTPUT: dout0_19 -* OUTPUT: dout0_20 -* OUTPUT: dout0_21 -* OUTPUT: dout0_22 -* OUTPUT: dout0_23 -* OUTPUT: dout0_24 -* OUTPUT: dout0_25 -* OUTPUT: dout0_26 -* OUTPUT: dout0_27 -* OUTPUT: dout0_28 -* OUTPUT: dout0_29 -* OUTPUT: dout0_30 -* OUTPUT: dout0_31 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : din0_2 -* INPUT : din0_3 -* INPUT : din0_4 -* INPUT : din0_5 -* INPUT : din0_6 -* INPUT : din0_7 -* INPUT : din0_8 -* INPUT : din0_9 -* INPUT : din0_10 -* INPUT : din0_11 -* INPUT : din0_12 -* INPUT : din0_13 -* INPUT : din0_14 -* INPUT : din0_15 -* INPUT : din0_16 -* INPUT : din0_17 -* INPUT : din0_18 -* INPUT : din0_19 -* INPUT : din0_20 -* INPUT : din0_21 -* INPUT : din0_22 -* INPUT : din0_23 -* INPUT : din0_24 -* INPUT : din0_25 -* INPUT : din0_26 -* INPUT : din0_27 -* INPUT : din0_28 -* INPUT : din0_29 -* INPUT : din0_30 -* INPUT : din0_31 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : addr0_4 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 rbl_wl0 vdd gnd port_address -.ENDS bank - -.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 32 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff -Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff -Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff -Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff -Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff -Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff -Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff -Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff -Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff -Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff -Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff -Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff -Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff -Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff -Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff -Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff -Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff -Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff -Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff -Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff -Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff -Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff -Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff -Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff -Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff -Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff -Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff -Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff -Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff -Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff -.ENDS data_dff - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3_0 - -* spice ptx M{0} {1} p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p - -* spice ptx M{0} {1} n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p - -.SUBCKT pinv_13 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p -Mpinv_nmos Z A gnd gnd n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p -.ENDS pinv_13 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [40] -Xbuf_inv1 A Z vdd gnd pinv_13 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_1 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_1 - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_2 - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_1 -Xdff_buf_inv2 Qb Q vdd gnd pinv_2 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p - -.SUBCKT pinv_14 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p -.ENDS pinv_14 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [32] -Xbuf_inv1 A Z vdd gnd pinv_14 -.ENDS pdriver_3 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -.SUBCKT pinv_18 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_18 - -* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p - -* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_12 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p -Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -.ENDS pinv_12 - -* spice ptx M{0} {1} p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p - -* spice ptx M{0} {1} n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p -Mpinv_nmos Z A gnd gnd n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p -.ENDS pinv_11 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [3, 10] -Xbuf_inv1 A Zb1_int vdd gnd pinv_11 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_12 -.ENDS pdriver_1 - -* spice ptx M{0} {1} p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p - -* spice ptx M{0} {1} n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p -Mpinv_nmos Z A gnd gnd n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p -.ENDS pinv_10 - -* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p - -* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p -.ENDS pinv_8 - -* spice ptx M{0} {1} n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p - -* spice ptx M{0} {1} p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p -Mpinv_nmos Z A gnd gnd n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p -.ENDS pinv_9 - -.SUBCKT pinv_6 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_6 - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_7 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 2, 7, 22, 67] -Xbuf_inv1 A Zb1_int vdd gnd pinv_6 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 -Xbuf_inv6 Zb5_int Z vdd gnd pinv_10 -.ENDS pdriver_0 - -.SUBCKT pinv_15 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_15 - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -.SUBCKT pinv_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p -.ENDS pinv_3 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_3 -.ENDS pdriver - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_0 - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -.SUBCKT pinv_16 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_16 - -* spice ptx M{0} {1} n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p - -* spice ptx M{0} {1} p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p - -.SUBCKT pinv_17 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p -Mpinv_nmos Z A gnd gnd n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p -.ENDS pinv_17 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 4, 11] -Xbuf_inv1 A Zb1_int vdd gnd pinv_6 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_16 -Xbuf_inv4 Zb3_int Z vdd gnd pinv_17 -.ENDS pdriver_4 - -* Used for tiling delay chain to desired length -.SUBCKT delay_chain_segment in out vdd gnd -Xdinv0 in dout_1 vdd gnd pinv_11 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_11 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_11 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_11 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_11 -Xdinv1 dout_1 out vdd gnd pinv_11 -Xdload_1_0 out n_1_0 vdd gnd pinv_11 -Xdload_1_1 out n_1_1 vdd gnd pinv_11 -Xdload_1_2 out n_1_2 vdd gnd pinv_11 -Xdload_1_3 out n_1_3 vdd gnd pinv_11 -.ENDS delay_chain_segment - -.SUBCKT multi_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd -Xdelay1 in out1 vdd gnd delay_chain_segment -Xdelay2 out1 out2 vdd gnd delay_chain_segment -Xdelay3 out2 out3 vdd gnd delay_chain_segment -Xdelay4 out3 out4 vdd gnd delay_chain_segment -Xdelay5 out4 out5 vdd gnd delay_chain_segment -Xdelay6 out5 out6 vdd gnd delay_chain_segment -Xdelay7 out6 out7 vdd gnd delay_chain_segment -Xdelay8 out7 out8 vdd gnd delay_chain_segment -Xdelay9 out8 out9 vdd gnd delay_chain_segment -Xdelay10 out9 out10 vdd gnd delay_chain_segment -Xdelay11 out10 out11 vdd gnd delay_chain_segment -Xdelay12 out11 out12 vdd gnd delay_chain_segment -Xdelay13 out12 out13 vdd gnd delay_chain_segment -Xdelay14 out13 out14 vdd gnd delay_chain_segment -Xdelay15 out14 out15 vdd gnd delay_chain_segment -Xdelay16 out15 out16 vdd gnd delay_chain_segment -.ENDS multi_delay_chain - -.SUBCKT glitch_generator in glitch1_bar glitch2_bar glitch3_bar vdd gnd -*.PININFO in:I glitch1_bar:O glitch2_bar:O glitch3_bar:O vdd:B gnd:B -Xmulti_delay_chain in out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 out16 vdd gnd multi_delay_chain -Xinv_g1 out6 g1_end vdd gnd pinv_11 -Xinv_g2 out7 g2_end vdd gnd pinv_11 -Xinv_g3 out16 g3_end vdd gnd pinv_11 -Xnand2_g1 out2 g1_end glitch1_bar vdd gnd pnand2 -Xnand2_g2 in g2_end glitch2_bar vdd gnd pnand2 -Xnand2_g3 out6 g3_end glitch3_bar vdd gnd pnand2 -.ENDS glitch_generator - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl (NO LONGER USED) -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 2 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -* is cs_buf needed on larger memories? -Xbuf_cs cs cs_buf vdd gnd pdriver_0 -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_10 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xglitch_generator gated_clk_buf glitch1_bar glitch2_bar glitch3_bar vdd gnd glitch_generator -Xinv_g3_buf glitch3_bar glitch3_buf vdd gnd pinv_11 -Xand_s_en we_bar gated_clk_bar glitch3_bar s_en vdd gnd pand3 -Xand_w_en we glitch2_bar glitch3_buf w_en vdd gnd pand3 -Xand_wl_en cs_buf glitch2_bar wl_en vdd gnd pand2 -Xbuf_p_en_bar glitch1_bar p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT sram_32_32_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] vdd gnd -*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : din0[2] -* INPUT : din0[3] -* INPUT : din0[4] -* INPUT : din0[5] -* INPUT : din0[6] -* INPUT : din0[7] -* INPUT : din0[8] -* INPUT : din0[9] -* INPUT : din0[10] -* INPUT : din0[11] -* INPUT : din0[12] -* INPUT : din0[13] -* INPUT : din0[14] -* INPUT : din0[15] -* INPUT : din0[16] -* INPUT : din0[17] -* INPUT : din0[18] -* INPUT : din0[19] -* INPUT : din0[20] -* INPUT : din0[21] -* INPUT : din0[22] -* INPUT : din0[23] -* INPUT : din0[24] -* INPUT : din0[25] -* INPUT : din0[26] -* INPUT : din0[27] -* INPUT : din0[28] -* INPUT : din0[29] -* INPUT : din0[30] -* INPUT : din0[31] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : addr0[4] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* OUTPUT: dout0[2] -* OUTPUT: dout0[3] -* OUTPUT: dout0[4] -* OUTPUT: dout0[5] -* OUTPUT: dout0[6] -* OUTPUT: dout0[7] -* OUTPUT: dout0[8] -* OUTPUT: dout0[9] -* OUTPUT: dout0[10] -* OUTPUT: dout0[11] -* OUTPUT: dout0[12] -* OUTPUT: dout0[13] -* OUTPUT: dout0[14] -* OUTPUT: dout0[15] -* OUTPUT: dout0[16] -* OUTPUT: dout0[17] -* OUTPUT: dout0[18] -* OUTPUT: dout0[19] -* OUTPUT: dout0[20] -* OUTPUT: dout0[21] -* OUTPUT: dout0[22] -* OUTPUT: dout0[23] -* OUTPUT: dout0[24] -* OUTPUT: dout0[25] -* OUTPUT: dout0[26] -* OUTPUT: dout0[27] -* OUTPUT: dout0[28] -* OUTPUT: dout0[29] -* OUTPUT: dout0[30] -* OUTPUT: dout0[31] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 a0_0 a0_1 a0_2 a0_3 a0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] a0_0 a0_1 a0_2 a0_3 a0_4 clk_buf0 vdd gnd row_addr_dff -Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 clk_buf0 vdd gnd data_dff -.ENDS sram_32_32_scn4m_subm diff --git a/32x32/sram_32_32_scn4m_subm.html b/32x32/sram_32_32_scn4m_subm.html deleted file mode 100644 index f3040ca0..00000000 --- a/32x32/sram_32_32_scn4m_subm.html +++ /dev/null @@ -1,35 +0,0 @@ - - -VLSIDAOpenRAM

sram_32_32_scn4m_subm.html

Compiled at: 2022-01-19

DRC errors: skipped

LVS errors: skipped

Git commit id: 06d391b3e365127628434b98044035232615f4b0

Ports and Configuration

TypeValue
WORD_SIZE32
NUM_WORDS32
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0
-

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)169MHz
-

Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[31:0] setup rising0.0090.009ns
din0[31:0] setup falling0.0090.009ns
din0[31:0] hold rising0.0010.001ns
din0[31:0] hold falling0.0010.001ns
dout0[31:0] cell rise1.51.591ns
dout0[31:0] cell fall1.51.591ns
dout0[31:0] rise transition0.0060.015ns
dout0[31:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[4:0] setup rising0.0090.009ns
addr0[4:0] setup falling0.0090.009ns
addr0[4:0] hold rising0.0010.001ns
addr0[4:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns
-

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising6.1899mW
!csb0 & clk0 & !web0Read Falling6.1899mW
!csb0 & !clk0 & web0Write Rising6.1899mW
!csb0 & !clk0 & web0Write Falling6.1899mW
csb0leakage0.001294mW
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Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib
-

Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_32_32_scn4m_subm.html
.libSynthesis modelssram_32_32_scn4m_subm_TT_5p0V_25C.lib
.logOpenRAM compile logsram_32_32_scn4m_subm.log
.pyOpenRAM configuration filesram_32_32_scn4m_subm.py
.spSPICE netlistssram_32_32_scn4m_subm.sp
.vVerilog simulation modelssram_32_32_scn4m_subm.v
diff --git a/32x32/sram_32_32_scn4m_subm.lvs.sp b/32x32/sram_32_32_scn4m_subm.lvs.sp deleted file mode 100644 index de7b0f17..00000000 --- a/32x32/sram_32_32_scn4m_subm.lvs.sp +++ /dev/null @@ -1,3599 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 32 -* Data bits: 32 -* Banks: 1 -* Column mux: 1:1 -* Trimmed: False -* LVS: True -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 dout_0 dout_1 dout_2 dout_3 dout_4 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 5 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff -.ENDS row_addr_dff - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* POWER : vdd -* GROUND: gnd -* rows: 32 cols: 32 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw -.ENDS bitcell_array - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw -Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw -Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw -Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw -Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw -Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw -Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw -Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw -Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw -Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw -Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw -Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw -Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw -Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw -Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw -Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw -Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 vdd gnd dummy_array -Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_1 -Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 en vdd gnd -*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* INPUT : data_2 -* INPUT : data_3 -* INPUT : data_4 -* INPUT : data_5 -* INPUT : data_6 -* INPUT : data_7 -* INPUT : data_8 -* INPUT : data_9 -* INPUT : data_10 -* INPUT : data_11 -* INPUT : data_12 -* INPUT : data_13 -* INPUT : data_14 -* INPUT : data_15 -* INPUT : data_16 -* INPUT : data_17 -* INPUT : data_18 -* INPUT : data_19 -* INPUT : data_20 -* INPUT : data_21 -* INPUT : data_22 -* INPUT : data_23 -* INPUT : data_24 -* INPUT : data_25 -* INPUT : data_26 -* INPUT : data_27 -* INPUT : data_28 -* INPUT : data_29 -* INPUT : data_30 -* INPUT : data_31 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 32 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver -Xwrite_driver2 data_2 bl_2 br_2 en vdd gnd write_driver -Xwrite_driver3 data_3 bl_3 br_3 en vdd gnd write_driver -Xwrite_driver4 data_4 bl_4 br_4 en vdd gnd write_driver -Xwrite_driver5 data_5 bl_5 br_5 en vdd gnd write_driver -Xwrite_driver6 data_6 bl_6 br_6 en vdd gnd write_driver -Xwrite_driver7 data_7 bl_7 br_7 en vdd gnd write_driver -Xwrite_driver8 data_8 bl_8 br_8 en vdd gnd write_driver -Xwrite_driver9 data_9 bl_9 br_9 en vdd gnd write_driver -Xwrite_driver10 data_10 bl_10 br_10 en vdd gnd write_driver -Xwrite_driver11 data_11 bl_11 br_11 en vdd gnd write_driver -Xwrite_driver12 data_12 bl_12 br_12 en vdd gnd write_driver -Xwrite_driver13 data_13 bl_13 br_13 en vdd gnd write_driver -Xwrite_driver14 data_14 bl_14 br_14 en vdd gnd write_driver -Xwrite_driver15 data_15 bl_15 br_15 en vdd gnd write_driver -Xwrite_driver16 data_16 bl_16 br_16 en vdd gnd write_driver -Xwrite_driver17 data_17 bl_17 br_17 en vdd gnd write_driver -Xwrite_driver18 data_18 bl_18 br_18 en vdd gnd write_driver -Xwrite_driver19 data_19 bl_19 br_19 en vdd gnd write_driver -Xwrite_driver20 data_20 bl_20 br_20 en vdd gnd write_driver -Xwrite_driver21 data_21 bl_21 br_21 en vdd gnd write_driver -Xwrite_driver22 data_22 bl_22 br_22 en vdd gnd write_driver -Xwrite_driver23 data_23 bl_23 br_23 en vdd gnd write_driver -Xwrite_driver24 data_24 bl_24 br_24 en vdd gnd write_driver -Xwrite_driver25 data_25 bl_25 br_25 en vdd gnd write_driver -Xwrite_driver26 data_26 bl_26 br_26 en vdd gnd write_driver -Xwrite_driver27 data_27 bl_27 br_27 en vdd gnd write_driver -Xwrite_driver28 data_28 bl_28 br_28 en vdd gnd write_driver -Xwrite_driver29 data_29 bl_29 br_29 en vdd gnd write_driver -Xwrite_driver30 data_30 bl_30 br_30 en vdd gnd write_driver -Xwrite_driver31 data_31 bl_31 br_31 en vdd gnd write_driver -.ENDS write_driver_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* INPUT : en_bar -* POWER : vdd -* cols: 33 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 -Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 -Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 -Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 -Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 -Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 -Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 -Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 -Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 -Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 -Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 -Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 -Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 -Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 -Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 -Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 -Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 -Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 -Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 -Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 -Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 -Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 -Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 -Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 -Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 -Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 -Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 -Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 -Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 -Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* OUTPUT: data_2 -* INPUT : bl_2 -* INPUT : br_2 -* OUTPUT: data_3 -* INPUT : bl_3 -* INPUT : br_3 -* OUTPUT: data_4 -* INPUT : bl_4 -* INPUT : br_4 -* OUTPUT: data_5 -* INPUT : bl_5 -* INPUT : br_5 -* OUTPUT: data_6 -* INPUT : bl_6 -* INPUT : br_6 -* OUTPUT: data_7 -* INPUT : bl_7 -* INPUT : br_7 -* OUTPUT: data_8 -* INPUT : bl_8 -* INPUT : br_8 -* OUTPUT: data_9 -* INPUT : bl_9 -* INPUT : br_9 -* OUTPUT: data_10 -* INPUT : bl_10 -* INPUT : br_10 -* OUTPUT: data_11 -* INPUT : bl_11 -* INPUT : br_11 -* OUTPUT: data_12 -* INPUT : bl_12 -* INPUT : br_12 -* OUTPUT: data_13 -* INPUT : bl_13 -* INPUT : br_13 -* OUTPUT: data_14 -* INPUT : bl_14 -* INPUT : br_14 -* OUTPUT: data_15 -* INPUT : bl_15 -* INPUT : br_15 -* OUTPUT: data_16 -* INPUT : bl_16 -* INPUT : br_16 -* OUTPUT: data_17 -* INPUT : bl_17 -* INPUT : br_17 -* OUTPUT: data_18 -* INPUT : bl_18 -* INPUT : br_18 -* OUTPUT: data_19 -* INPUT : bl_19 -* INPUT : br_19 -* OUTPUT: data_20 -* INPUT : bl_20 -* INPUT : br_20 -* OUTPUT: data_21 -* INPUT : bl_21 -* INPUT : br_21 -* OUTPUT: data_22 -* INPUT : bl_22 -* INPUT : br_22 -* OUTPUT: data_23 -* INPUT : bl_23 -* INPUT : br_23 -* OUTPUT: data_24 -* INPUT : bl_24 -* INPUT : br_24 -* OUTPUT: data_25 -* INPUT : bl_25 -* INPUT : br_25 -* OUTPUT: data_26 -* INPUT : bl_26 -* INPUT : br_26 -* OUTPUT: data_27 -* INPUT : bl_27 -* INPUT : br_27 -* OUTPUT: data_28 -* INPUT : bl_28 -* INPUT : br_28 -* OUTPUT: data_29 -* INPUT : bl_29 -* INPUT : br_29 -* OUTPUT: data_30 -* INPUT : bl_30 -* INPUT : br_30 -* OUTPUT: data_31 -* INPUT : bl_31 -* INPUT : br_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 1 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp -Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp -Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp -Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp -Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp -Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp -Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp -Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp -Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp -Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp -Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp -Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp -Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp -Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp -Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp -Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp -Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp -Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp -Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp -Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp -Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp -Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp -Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp -Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp -Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp -Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp -Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp -Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp -Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp -Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp -.ENDS sense_amp_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 dout_2 bl_2 br_2 dout_3 bl_3 br_3 dout_4 bl_4 br_4 dout_5 bl_5 br_5 dout_6 bl_6 br_6 dout_7 bl_7 br_7 dout_8 bl_8 br_8 dout_9 bl_9 br_9 dout_10 bl_10 br_10 dout_11 bl_11 br_11 dout_12 bl_12 br_12 dout_13 bl_13 br_13 dout_14 bl_14 br_14 dout_15 bl_15 br_15 dout_16 bl_16 br_16 dout_17 bl_17 br_17 dout_18 bl_18 br_18 dout_19 bl_19 br_19 dout_20 bl_20 br_20 dout_21 bl_21 br_21 dout_22 bl_22 br_22 dout_23 bl_23 br_23 dout_24 bl_24 br_24 dout_25 bl_25 br_25 dout_26 bl_26 br_26 dout_27 bl_27 br_27 dout_28 bl_28 br_28 dout_29 bl_29 br_29 dout_30 bl_30 br_30 dout_31 bl_31 br_31 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 w_en vdd gnd write_driver_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u -.ENDS pinv_0 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv_0 -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* INPUT : in_16 -* INPUT : in_17 -* INPUT : in_18 -* INPUT : in_19 -* INPUT : in_20 -* INPUT : in_21 -* INPUT : in_22 -* INPUT : in_23 -* INPUT : in_24 -* INPUT : in_25 -* INPUT : in_26 -* INPUT : in_27 -* INPUT : in_28 -* INPUT : in_29 -* INPUT : in_30 -* INPUT : in_31 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 32 cols: 32 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver -Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver -Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver -Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver -Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver -Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver -Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver -Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver -Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver -Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver -Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver -Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver -Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver -Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver -Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver -Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver -.ENDS wordline_driver_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand3 - -.SUBCKT and3_dec A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand3_dec_nand A B C zb_int vdd gnd pnand3 -Xpand3_dec_inv zb_int Z vdd gnd pinv -.ENDS and3_dec - -.SUBCKT hierarchical_predecode3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd -*.PININFO in_0:I in_1:I in_2:I out_0:O out_1:O out_2:O out_3:O out_4:O out_5:O out_6:O out_7:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* OUTPUT: out_4 -* OUTPUT: out_5 -* OUTPUT: out_6 -* OUTPUT: out_7 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -Xpre_inv_2 in_2 inbar_2 vdd gnd pinv -XXpre3x8_and_0 inbar_0 inbar_1 inbar_2 out_0 vdd gnd and3_dec -XXpre3x8_and_1 in_0 inbar_1 inbar_2 out_1 vdd gnd and3_dec -XXpre3x8_and_2 inbar_0 in_1 inbar_2 out_2 vdd gnd and3_dec -XXpre3x8_and_3 in_0 in_1 inbar_2 out_3 vdd gnd and3_dec -XXpre3x8_and_4 inbar_0 inbar_1 in_2 out_4 vdd gnd and3_dec -XXpre3x8_and_5 in_0 inbar_1 in_2 out_5 vdd gnd and3_dec -XXpre3x8_and_6 inbar_0 in_1 in_2 out_6 vdd gnd and3_dec -XXpre3x8_and_7 in_0 in_1 in_2 out_7 vdd gnd and3_dec -.ENDS hierarchical_predecode3x8 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* OUTPUT: decode_16 -* OUTPUT: decode_17 -* OUTPUT: decode_18 -* OUTPUT: decode_19 -* OUTPUT: decode_20 -* OUTPUT: decode_21 -* OUTPUT: decode_22 -* OUTPUT: decode_23 -* OUTPUT: decode_24 -* OUTPUT: decode_25 -* OUTPUT: decode_26 -* OUTPUT: decode_27 -* OUTPUT: decode_28 -* OUTPUT: decode_29 -* OUTPUT: decode_30 -* OUTPUT: decode_31 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre3x8_0 addr_2 addr_3 addr_4 out_4 out_5 out_6 out_7 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode3x8 -XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec -XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec -XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec -XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec -XDEC_AND_16 out_0 out_8 decode_16 vdd gnd and2_dec -XDEC_AND_20 out_0 out_9 decode_20 vdd gnd and2_dec -XDEC_AND_24 out_0 out_10 decode_24 vdd gnd and2_dec -XDEC_AND_28 out_0 out_11 decode_28 vdd gnd and2_dec -XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec -XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec -XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec -XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec -XDEC_AND_17 out_1 out_8 decode_17 vdd gnd and2_dec -XDEC_AND_21 out_1 out_9 decode_21 vdd gnd and2_dec -XDEC_AND_25 out_1 out_10 decode_25 vdd gnd and2_dec -XDEC_AND_29 out_1 out_11 decode_29 vdd gnd and2_dec -XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec -XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec -XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec -XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec -XDEC_AND_18 out_2 out_8 decode_18 vdd gnd and2_dec -XDEC_AND_22 out_2 out_9 decode_22 vdd gnd and2_dec -XDEC_AND_26 out_2 out_10 decode_26 vdd gnd and2_dec -XDEC_AND_30 out_2 out_11 decode_30 vdd gnd and2_dec -XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec -XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec -XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec -XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec -XDEC_AND_19 out_3 out_8 decode_19 vdd gnd and2_dec -XDEC_AND_23 out_3 out_9 decode_23 vdd gnd and2_dec -XDEC_AND_27 out_3 out_10 decode_27 vdd gnd and2_dec -XDEC_AND_31 out_3 out_11 decode_31 vdd gnd and2_dec -.ENDS hierarchical_decoder - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 8 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv_0 -.ENDS and2_dec_0 - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: dout0_2 -* OUTPUT: dout0_3 -* OUTPUT: dout0_4 -* OUTPUT: dout0_5 -* OUTPUT: dout0_6 -* OUTPUT: dout0_7 -* OUTPUT: dout0_8 -* OUTPUT: dout0_9 -* OUTPUT: dout0_10 -* OUTPUT: dout0_11 -* OUTPUT: dout0_12 -* OUTPUT: dout0_13 -* OUTPUT: dout0_14 -* OUTPUT: dout0_15 -* OUTPUT: dout0_16 -* OUTPUT: dout0_17 -* OUTPUT: dout0_18 -* OUTPUT: dout0_19 -* OUTPUT: dout0_20 -* OUTPUT: dout0_21 -* OUTPUT: dout0_22 -* OUTPUT: dout0_23 -* OUTPUT: dout0_24 -* OUTPUT: dout0_25 -* OUTPUT: dout0_26 -* OUTPUT: dout0_27 -* OUTPUT: dout0_28 -* OUTPUT: dout0_29 -* OUTPUT: dout0_30 -* OUTPUT: dout0_31 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : din0_2 -* INPUT : din0_3 -* INPUT : din0_4 -* INPUT : din0_5 -* INPUT : din0_6 -* INPUT : din0_7 -* INPUT : din0_8 -* INPUT : din0_9 -* INPUT : din0_10 -* INPUT : din0_11 -* INPUT : din0_12 -* INPUT : din0_13 -* INPUT : din0_14 -* INPUT : din0_15 -* INPUT : din0_16 -* INPUT : din0_17 -* INPUT : din0_18 -* INPUT : din0_19 -* INPUT : din0_20 -* INPUT : din0_21 -* INPUT : din0_22 -* INPUT : din0_23 -* INPUT : din0_24 -* INPUT : din0_25 -* INPUT : din0_26 -* INPUT : din0_27 -* INPUT : din0_28 -* INPUT : din0_29 -* INPUT : din0_30 -* INPUT : din0_31 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : addr0_4 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 rbl_wl0 vdd gnd port_address -.ENDS bank - -.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 32 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff -Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff -Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff -Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff -Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff -Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff -Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff -Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff -Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff -Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff -Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff -Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff -Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff -Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff -Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff -Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff -Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff -Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff -Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff -Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff -Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff -Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff -Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff -Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff -Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff -Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff -Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff -Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff -Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff -Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff -.ENDS data_dff - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand3_0 - -* spice ptx M{0} {1} p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p - -* spice ptx M{0} {1} n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p - -.SUBCKT pinv_13 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=64.0u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=32.0u l=0.4u -.ENDS pinv_13 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [40] -Xbuf_inv1 A Z vdd gnd pinv_13 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2_1 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pinv_1 - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u -.ENDS pinv_2 - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_1 -Xdff_buf_inv2 Qb Q vdd gnd pinv_2 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p - -.SUBCKT pinv_14 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u -.ENDS pinv_14 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [32] -Xbuf_inv1 A Z vdd gnd pinv_14 -.ENDS pdriver_3 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -.SUBCKT pinv_18 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_18 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_18 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_18 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_18 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_18 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_18 -Xdinv1 dout_1 dout_2 vdd gnd pinv_18 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_18 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_18 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_18 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_18 -Xdinv2 dout_2 dout_3 vdd gnd pinv_18 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_18 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_18 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_18 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_18 -Xdinv3 dout_3 dout_4 vdd gnd pinv_18 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_18 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_18 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_18 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_18 -Xdinv4 dout_4 dout_5 vdd gnd pinv_18 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_18 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_18 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_18 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_18 -Xdinv5 dout_5 dout_6 vdd gnd pinv_18 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_18 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_18 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_18 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_18 -Xdinv6 dout_6 dout_7 vdd gnd pinv_18 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_18 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_18 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_18 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_18 -Xdinv7 dout_7 dout_8 vdd gnd pinv_18 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_18 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_18 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_18 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_18 -Xdinv8 dout_8 out vdd gnd pinv_18 -Xdload_8_0 out n_8_0 vdd gnd pinv_18 -Xdload_8_1 out n_8_1 vdd gnd pinv_18 -Xdload_8_2 out n_8_2 vdd gnd pinv_18 -Xdload_8_3 out n_8_3 vdd gnd pinv_18 -.ENDS delay_chain - -* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p - -* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_12 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u -.ENDS pinv_12 - -* spice ptx M{0} {1} p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p - -* spice ptx M{0} {1} n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=4.800000000000001u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=2.4000000000000004u l=0.4u -.ENDS pinv_11 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [3, 10] -Xbuf_inv1 A Zb1_int vdd gnd pinv_11 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_12 -.ENDS pdriver_1 - -* spice ptx M{0} {1} p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p - -* spice ptx M{0} {1} n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=107.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=53.6u l=0.4u -.ENDS pinv_10 - -* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p - -* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u -.ENDS pinv_8 - -* spice ptx M{0} {1} n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p - -* spice ptx M{0} {1} p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=35.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=17.6u l=0.4u -.ENDS pinv_9 - -.SUBCKT pinv_6 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_6 - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pinv_7 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 2, 7, 22, 67] -Xbuf_inv1 A Zb1_int vdd gnd pinv_6 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 -Xbuf_inv6 Zb5_int Z vdd gnd pinv_10 -.ENDS pdriver_0 - -.SUBCKT pinv_15 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u -.ENDS pinv_15 - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -.SUBCKT pinv_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u -.ENDS pinv_3 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_3 -.ENDS pdriver - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u -.ENDS pnand2_0 - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -.SUBCKT pinv_16 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u -.ENDS pinv_16 - -* spice ptx M{0} {1} n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p - -* spice ptx M{0} {1} p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p - -.SUBCKT pinv_17 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=17.6u l=0.4u -Mpinv_nmos Z A gnd gnd n m=1 w=8.8u l=0.4u -.ENDS pinv_17 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 4, 11] -Xbuf_inv1 A Zb1_int vdd gnd pinv_6 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_16 -Xbuf_inv4 Zb3_int Z vdd gnd pinv_17 -.ENDS pdriver_4 - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 32 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_15 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 -Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_15 -Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 -Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 -Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain -Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 -Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT sram_32_32_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] vdd gnd -*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : din0[2] -* INPUT : din0[3] -* INPUT : din0[4] -* INPUT : din0[5] -* INPUT : din0[6] -* INPUT : din0[7] -* INPUT : din0[8] -* INPUT : din0[9] -* INPUT : din0[10] -* INPUT : din0[11] -* INPUT : din0[12] -* INPUT : din0[13] -* INPUT : din0[14] -* INPUT : din0[15] -* INPUT : din0[16] -* INPUT : din0[17] -* INPUT : din0[18] -* INPUT : din0[19] -* INPUT : din0[20] -* INPUT : din0[21] -* INPUT : din0[22] -* INPUT : din0[23] -* INPUT : din0[24] -* INPUT : din0[25] -* INPUT : din0[26] -* INPUT : din0[27] -* INPUT : din0[28] -* INPUT : din0[29] -* INPUT : din0[30] -* INPUT : din0[31] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : addr0[4] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* OUTPUT: dout0[2] -* OUTPUT: dout0[3] -* OUTPUT: dout0[4] -* OUTPUT: dout0[5] -* OUTPUT: dout0[6] -* OUTPUT: dout0[7] -* OUTPUT: dout0[8] -* OUTPUT: dout0[9] -* OUTPUT: dout0[10] -* OUTPUT: dout0[11] -* OUTPUT: dout0[12] -* OUTPUT: dout0[13] -* OUTPUT: dout0[14] -* OUTPUT: dout0[15] -* OUTPUT: dout0[16] -* OUTPUT: dout0[17] -* OUTPUT: dout0[18] -* OUTPUT: dout0[19] -* OUTPUT: dout0[20] -* OUTPUT: dout0[21] -* OUTPUT: dout0[22] -* OUTPUT: dout0[23] -* OUTPUT: dout0[24] -* OUTPUT: dout0[25] -* OUTPUT: dout0[26] -* OUTPUT: dout0[27] -* OUTPUT: dout0[28] -* OUTPUT: dout0[29] -* OUTPUT: dout0[30] -* OUTPUT: dout0[31] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 a0_0 a0_1 a0_2 a0_3 a0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] a0_0 a0_1 a0_2 a0_3 a0_4 clk_buf0 vdd gnd row_addr_dff -Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 clk_buf0 vdd gnd data_dff -.ENDS sram_32_32_scn4m_subm diff --git a/32x32/sram_32_32_scn4m_subm.sp b/32x32/sram_32_32_scn4m_subm.sp deleted file mode 100644 index 06c6d8fb..00000000 --- a/32x32/sram_32_32_scn4m_subm.sp +++ /dev/null @@ -1,3599 +0,0 @@ -************************************************** -* OpenRAM generated memory. -* Words: 32 -* Data bits: 32 -* Banks: 1 -* Column mux: 1:1 -* Trimmed: False -* LVS: False -************************************************** -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd - -* SPICE3 file created from dff.ext - technology: scmos - -M1000 vdd clk a_24_24# vdd p w=8u l=0.4u -M1001 a_84_296# D vdd vdd p w=4u l=0.4u -M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u -M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u -M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u -M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u -M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u -M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u -M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u -M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd n w=4u l=0.4u -M1011 Q a_280_24# vdd vdd p w=8u l=0.4u -M1012 a_84_24# D gnd gnd n w=2u l=0.4u -M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u -M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u -M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u -M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u -M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u -M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u -M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u -M1020 gnd Q a_320_24# gnd n w=2u l=0.4u -M1021 Q a_280_24# gnd gnd n w=4u l=0.4u - -.ENDS - -.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 din_4 dout_0 dout_1 dout_2 dout_3 dout_4 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 5 cols: 1 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff -Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff -Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff -Xdff_r4_c0 din_4 dout_4 clk vdd gnd dff -.ENDS row_addr_dff - -*********************** "cell_1rw" ****************************** -.SUBCKT cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Q_bar wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT bitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* POWER : vdd -* GROUND: gnd -* rows: 32 cols: 32 -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c1 bl_0_1 br_0_1 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c1 bl_0_1 br_0_1 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c1 bl_0_1 br_0_1 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c1 bl_0_1 br_0_1 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c1 bl_0_1 br_0_1 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c1 bl_0_1 br_0_1 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c1 bl_0_1 br_0_1 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c1 bl_0_1 br_0_1 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c1 bl_0_1 br_0_1 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c1 bl_0_1 br_0_1 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c1 bl_0_1 br_0_1 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c1 bl_0_1 br_0_1 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c1 bl_0_1 br_0_1 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c1 bl_0_1 br_0_1 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c1 bl_0_1 br_0_1 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c1 bl_0_1 br_0_1 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c1 bl_0_1 br_0_1 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c1 bl_0_1 br_0_1 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c1 bl_0_1 br_0_1 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c1 bl_0_1 br_0_1 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c1 bl_0_1 br_0_1 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c1 bl_0_1 br_0_1 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c1 bl_0_1 br_0_1 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c1 bl_0_1 br_0_1 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c1 bl_0_1 br_0_1 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c1 bl_0_1 br_0_1 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c1 bl_0_1 br_0_1 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c1 bl_0_1 br_0_1 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c1 bl_0_1 br_0_1 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c1 bl_0_1 br_0_1 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c1 bl_0_1 br_0_1 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c2 bl_0_2 br_0_2 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c2 bl_0_2 br_0_2 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c2 bl_0_2 br_0_2 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c2 bl_0_2 br_0_2 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c2 bl_0_2 br_0_2 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c2 bl_0_2 br_0_2 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c2 bl_0_2 br_0_2 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c2 bl_0_2 br_0_2 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c2 bl_0_2 br_0_2 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c2 bl_0_2 br_0_2 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c2 bl_0_2 br_0_2 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c2 bl_0_2 br_0_2 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c2 bl_0_2 br_0_2 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c2 bl_0_2 br_0_2 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c2 bl_0_2 br_0_2 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c2 bl_0_2 br_0_2 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c2 bl_0_2 br_0_2 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c2 bl_0_2 br_0_2 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c2 bl_0_2 br_0_2 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c2 bl_0_2 br_0_2 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c2 bl_0_2 br_0_2 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c2 bl_0_2 br_0_2 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c2 bl_0_2 br_0_2 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c2 bl_0_2 br_0_2 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c2 bl_0_2 br_0_2 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c2 bl_0_2 br_0_2 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c2 bl_0_2 br_0_2 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c2 bl_0_2 br_0_2 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c2 bl_0_2 br_0_2 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c2 bl_0_2 br_0_2 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c2 bl_0_2 br_0_2 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c3 bl_0_3 br_0_3 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c3 bl_0_3 br_0_3 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c3 bl_0_3 br_0_3 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c3 bl_0_3 br_0_3 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c3 bl_0_3 br_0_3 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c3 bl_0_3 br_0_3 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c3 bl_0_3 br_0_3 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c3 bl_0_3 br_0_3 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c3 bl_0_3 br_0_3 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c3 bl_0_3 br_0_3 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c3 bl_0_3 br_0_3 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c3 bl_0_3 br_0_3 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c3 bl_0_3 br_0_3 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c3 bl_0_3 br_0_3 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c3 bl_0_3 br_0_3 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c3 bl_0_3 br_0_3 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c3 bl_0_3 br_0_3 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c3 bl_0_3 br_0_3 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c3 bl_0_3 br_0_3 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c3 bl_0_3 br_0_3 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c3 bl_0_3 br_0_3 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c3 bl_0_3 br_0_3 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c3 bl_0_3 br_0_3 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c3 bl_0_3 br_0_3 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c3 bl_0_3 br_0_3 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c3 bl_0_3 br_0_3 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c3 bl_0_3 br_0_3 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c3 bl_0_3 br_0_3 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c3 bl_0_3 br_0_3 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c3 bl_0_3 br_0_3 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c3 bl_0_3 br_0_3 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c4 bl_0_4 br_0_4 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c4 bl_0_4 br_0_4 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c4 bl_0_4 br_0_4 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c4 bl_0_4 br_0_4 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c4 bl_0_4 br_0_4 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c4 bl_0_4 br_0_4 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c4 bl_0_4 br_0_4 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c4 bl_0_4 br_0_4 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c4 bl_0_4 br_0_4 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c4 bl_0_4 br_0_4 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c4 bl_0_4 br_0_4 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c4 bl_0_4 br_0_4 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c4 bl_0_4 br_0_4 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c4 bl_0_4 br_0_4 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c4 bl_0_4 br_0_4 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c4 bl_0_4 br_0_4 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c4 bl_0_4 br_0_4 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c4 bl_0_4 br_0_4 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c4 bl_0_4 br_0_4 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c4 bl_0_4 br_0_4 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c4 bl_0_4 br_0_4 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c4 bl_0_4 br_0_4 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c4 bl_0_4 br_0_4 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c4 bl_0_4 br_0_4 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c4 bl_0_4 br_0_4 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c4 bl_0_4 br_0_4 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c4 bl_0_4 br_0_4 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c4 bl_0_4 br_0_4 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c4 bl_0_4 br_0_4 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c4 bl_0_4 br_0_4 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c4 bl_0_4 br_0_4 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c5 bl_0_5 br_0_5 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c5 bl_0_5 br_0_5 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c5 bl_0_5 br_0_5 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c5 bl_0_5 br_0_5 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c5 bl_0_5 br_0_5 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c5 bl_0_5 br_0_5 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c5 bl_0_5 br_0_5 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c5 bl_0_5 br_0_5 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c5 bl_0_5 br_0_5 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c5 bl_0_5 br_0_5 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c5 bl_0_5 br_0_5 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c5 bl_0_5 br_0_5 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c5 bl_0_5 br_0_5 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c5 bl_0_5 br_0_5 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c5 bl_0_5 br_0_5 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c5 bl_0_5 br_0_5 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c5 bl_0_5 br_0_5 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c5 bl_0_5 br_0_5 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c5 bl_0_5 br_0_5 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c5 bl_0_5 br_0_5 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c5 bl_0_5 br_0_5 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c5 bl_0_5 br_0_5 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c5 bl_0_5 br_0_5 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c5 bl_0_5 br_0_5 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c5 bl_0_5 br_0_5 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c5 bl_0_5 br_0_5 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c5 bl_0_5 br_0_5 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c5 bl_0_5 br_0_5 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c5 bl_0_5 br_0_5 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c5 bl_0_5 br_0_5 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c5 bl_0_5 br_0_5 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c6 bl_0_6 br_0_6 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c6 bl_0_6 br_0_6 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c6 bl_0_6 br_0_6 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c6 bl_0_6 br_0_6 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c6 bl_0_6 br_0_6 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c6 bl_0_6 br_0_6 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c6 bl_0_6 br_0_6 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c6 bl_0_6 br_0_6 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c6 bl_0_6 br_0_6 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c6 bl_0_6 br_0_6 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c6 bl_0_6 br_0_6 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c6 bl_0_6 br_0_6 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c6 bl_0_6 br_0_6 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c6 bl_0_6 br_0_6 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c6 bl_0_6 br_0_6 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c6 bl_0_6 br_0_6 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c6 bl_0_6 br_0_6 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c6 bl_0_6 br_0_6 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c6 bl_0_6 br_0_6 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c6 bl_0_6 br_0_6 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c6 bl_0_6 br_0_6 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c6 bl_0_6 br_0_6 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c6 bl_0_6 br_0_6 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c6 bl_0_6 br_0_6 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c6 bl_0_6 br_0_6 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c6 bl_0_6 br_0_6 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c6 bl_0_6 br_0_6 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c6 bl_0_6 br_0_6 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c6 bl_0_6 br_0_6 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c6 bl_0_6 br_0_6 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c6 bl_0_6 br_0_6 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c7 bl_0_7 br_0_7 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c7 bl_0_7 br_0_7 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c7 bl_0_7 br_0_7 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c7 bl_0_7 br_0_7 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c7 bl_0_7 br_0_7 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c7 bl_0_7 br_0_7 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c7 bl_0_7 br_0_7 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c7 bl_0_7 br_0_7 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c7 bl_0_7 br_0_7 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c7 bl_0_7 br_0_7 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c7 bl_0_7 br_0_7 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c7 bl_0_7 br_0_7 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c7 bl_0_7 br_0_7 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c7 bl_0_7 br_0_7 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c7 bl_0_7 br_0_7 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c7 bl_0_7 br_0_7 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c7 bl_0_7 br_0_7 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c7 bl_0_7 br_0_7 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c7 bl_0_7 br_0_7 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c7 bl_0_7 br_0_7 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c7 bl_0_7 br_0_7 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c7 bl_0_7 br_0_7 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c7 bl_0_7 br_0_7 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c7 bl_0_7 br_0_7 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c7 bl_0_7 br_0_7 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c7 bl_0_7 br_0_7 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c7 bl_0_7 br_0_7 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c7 bl_0_7 br_0_7 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c7 bl_0_7 br_0_7 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c7 bl_0_7 br_0_7 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c7 bl_0_7 br_0_7 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c8 bl_0_8 br_0_8 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c8 bl_0_8 br_0_8 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c8 bl_0_8 br_0_8 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c8 bl_0_8 br_0_8 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c8 bl_0_8 br_0_8 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c8 bl_0_8 br_0_8 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c8 bl_0_8 br_0_8 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c8 bl_0_8 br_0_8 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c8 bl_0_8 br_0_8 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c8 bl_0_8 br_0_8 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c8 bl_0_8 br_0_8 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c8 bl_0_8 br_0_8 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c8 bl_0_8 br_0_8 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c8 bl_0_8 br_0_8 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c8 bl_0_8 br_0_8 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c8 bl_0_8 br_0_8 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c8 bl_0_8 br_0_8 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c8 bl_0_8 br_0_8 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c8 bl_0_8 br_0_8 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c8 bl_0_8 br_0_8 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c8 bl_0_8 br_0_8 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c8 bl_0_8 br_0_8 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c8 bl_0_8 br_0_8 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c8 bl_0_8 br_0_8 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c8 bl_0_8 br_0_8 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c8 bl_0_8 br_0_8 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c8 bl_0_8 br_0_8 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c8 bl_0_8 br_0_8 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c8 bl_0_8 br_0_8 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c8 bl_0_8 br_0_8 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c8 bl_0_8 br_0_8 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c9 bl_0_9 br_0_9 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c9 bl_0_9 br_0_9 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c9 bl_0_9 br_0_9 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c9 bl_0_9 br_0_9 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c9 bl_0_9 br_0_9 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c9 bl_0_9 br_0_9 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c9 bl_0_9 br_0_9 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c9 bl_0_9 br_0_9 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c9 bl_0_9 br_0_9 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c9 bl_0_9 br_0_9 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c9 bl_0_9 br_0_9 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c9 bl_0_9 br_0_9 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c9 bl_0_9 br_0_9 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c9 bl_0_9 br_0_9 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c9 bl_0_9 br_0_9 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c9 bl_0_9 br_0_9 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c9 bl_0_9 br_0_9 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c9 bl_0_9 br_0_9 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c9 bl_0_9 br_0_9 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c9 bl_0_9 br_0_9 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c9 bl_0_9 br_0_9 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c9 bl_0_9 br_0_9 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c9 bl_0_9 br_0_9 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c9 bl_0_9 br_0_9 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c9 bl_0_9 br_0_9 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c9 bl_0_9 br_0_9 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c9 bl_0_9 br_0_9 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c9 bl_0_9 br_0_9 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c9 bl_0_9 br_0_9 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c9 bl_0_9 br_0_9 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c9 bl_0_9 br_0_9 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c10 bl_0_10 br_0_10 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c10 bl_0_10 br_0_10 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c10 bl_0_10 br_0_10 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c10 bl_0_10 br_0_10 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c10 bl_0_10 br_0_10 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c10 bl_0_10 br_0_10 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c10 bl_0_10 br_0_10 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c10 bl_0_10 br_0_10 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c10 bl_0_10 br_0_10 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c10 bl_0_10 br_0_10 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c10 bl_0_10 br_0_10 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c10 bl_0_10 br_0_10 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c10 bl_0_10 br_0_10 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c10 bl_0_10 br_0_10 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c10 bl_0_10 br_0_10 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c10 bl_0_10 br_0_10 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c10 bl_0_10 br_0_10 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c10 bl_0_10 br_0_10 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c10 bl_0_10 br_0_10 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c10 bl_0_10 br_0_10 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c10 bl_0_10 br_0_10 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c10 bl_0_10 br_0_10 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c10 bl_0_10 br_0_10 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c10 bl_0_10 br_0_10 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c10 bl_0_10 br_0_10 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c10 bl_0_10 br_0_10 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c10 bl_0_10 br_0_10 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c10 bl_0_10 br_0_10 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c10 bl_0_10 br_0_10 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c10 bl_0_10 br_0_10 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c10 bl_0_10 br_0_10 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c11 bl_0_11 br_0_11 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c11 bl_0_11 br_0_11 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c11 bl_0_11 br_0_11 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c11 bl_0_11 br_0_11 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c11 bl_0_11 br_0_11 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c11 bl_0_11 br_0_11 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c11 bl_0_11 br_0_11 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c11 bl_0_11 br_0_11 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c11 bl_0_11 br_0_11 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c11 bl_0_11 br_0_11 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c11 bl_0_11 br_0_11 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c11 bl_0_11 br_0_11 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c11 bl_0_11 br_0_11 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c11 bl_0_11 br_0_11 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c11 bl_0_11 br_0_11 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c11 bl_0_11 br_0_11 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c11 bl_0_11 br_0_11 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c11 bl_0_11 br_0_11 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c11 bl_0_11 br_0_11 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c11 bl_0_11 br_0_11 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c11 bl_0_11 br_0_11 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c11 bl_0_11 br_0_11 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c11 bl_0_11 br_0_11 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c11 bl_0_11 br_0_11 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c11 bl_0_11 br_0_11 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c11 bl_0_11 br_0_11 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c11 bl_0_11 br_0_11 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c11 bl_0_11 br_0_11 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c11 bl_0_11 br_0_11 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c11 bl_0_11 br_0_11 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c11 bl_0_11 br_0_11 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c12 bl_0_12 br_0_12 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c12 bl_0_12 br_0_12 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c12 bl_0_12 br_0_12 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c12 bl_0_12 br_0_12 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c12 bl_0_12 br_0_12 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c12 bl_0_12 br_0_12 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c12 bl_0_12 br_0_12 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c12 bl_0_12 br_0_12 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c12 bl_0_12 br_0_12 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c12 bl_0_12 br_0_12 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c12 bl_0_12 br_0_12 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c12 bl_0_12 br_0_12 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c12 bl_0_12 br_0_12 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c12 bl_0_12 br_0_12 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c12 bl_0_12 br_0_12 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c12 bl_0_12 br_0_12 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c12 bl_0_12 br_0_12 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c12 bl_0_12 br_0_12 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c12 bl_0_12 br_0_12 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c12 bl_0_12 br_0_12 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c12 bl_0_12 br_0_12 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c12 bl_0_12 br_0_12 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c12 bl_0_12 br_0_12 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c12 bl_0_12 br_0_12 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c12 bl_0_12 br_0_12 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c12 bl_0_12 br_0_12 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c12 bl_0_12 br_0_12 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c12 bl_0_12 br_0_12 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c12 bl_0_12 br_0_12 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c12 bl_0_12 br_0_12 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c12 bl_0_12 br_0_12 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c13 bl_0_13 br_0_13 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c13 bl_0_13 br_0_13 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c13 bl_0_13 br_0_13 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c13 bl_0_13 br_0_13 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c13 bl_0_13 br_0_13 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c13 bl_0_13 br_0_13 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c13 bl_0_13 br_0_13 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c13 bl_0_13 br_0_13 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c13 bl_0_13 br_0_13 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c13 bl_0_13 br_0_13 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c13 bl_0_13 br_0_13 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c13 bl_0_13 br_0_13 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c13 bl_0_13 br_0_13 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c13 bl_0_13 br_0_13 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c13 bl_0_13 br_0_13 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c13 bl_0_13 br_0_13 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c13 bl_0_13 br_0_13 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c13 bl_0_13 br_0_13 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c13 bl_0_13 br_0_13 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c13 bl_0_13 br_0_13 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c13 bl_0_13 br_0_13 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c13 bl_0_13 br_0_13 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c13 bl_0_13 br_0_13 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c13 bl_0_13 br_0_13 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c13 bl_0_13 br_0_13 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c13 bl_0_13 br_0_13 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c13 bl_0_13 br_0_13 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c13 bl_0_13 br_0_13 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c13 bl_0_13 br_0_13 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c13 bl_0_13 br_0_13 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c13 bl_0_13 br_0_13 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c14 bl_0_14 br_0_14 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c14 bl_0_14 br_0_14 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c14 bl_0_14 br_0_14 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c14 bl_0_14 br_0_14 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c14 bl_0_14 br_0_14 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c14 bl_0_14 br_0_14 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c14 bl_0_14 br_0_14 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c14 bl_0_14 br_0_14 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c14 bl_0_14 br_0_14 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c14 bl_0_14 br_0_14 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c14 bl_0_14 br_0_14 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c14 bl_0_14 br_0_14 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c14 bl_0_14 br_0_14 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c14 bl_0_14 br_0_14 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c14 bl_0_14 br_0_14 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c14 bl_0_14 br_0_14 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c14 bl_0_14 br_0_14 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c14 bl_0_14 br_0_14 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c14 bl_0_14 br_0_14 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c14 bl_0_14 br_0_14 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c14 bl_0_14 br_0_14 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c14 bl_0_14 br_0_14 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c14 bl_0_14 br_0_14 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c14 bl_0_14 br_0_14 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c14 bl_0_14 br_0_14 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c14 bl_0_14 br_0_14 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c14 bl_0_14 br_0_14 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c14 bl_0_14 br_0_14 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c14 bl_0_14 br_0_14 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c14 bl_0_14 br_0_14 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c14 bl_0_14 br_0_14 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c15 bl_0_15 br_0_15 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c15 bl_0_15 br_0_15 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c15 bl_0_15 br_0_15 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c15 bl_0_15 br_0_15 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c15 bl_0_15 br_0_15 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c15 bl_0_15 br_0_15 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c15 bl_0_15 br_0_15 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c15 bl_0_15 br_0_15 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c15 bl_0_15 br_0_15 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c15 bl_0_15 br_0_15 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c15 bl_0_15 br_0_15 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c15 bl_0_15 br_0_15 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c15 bl_0_15 br_0_15 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c15 bl_0_15 br_0_15 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c15 bl_0_15 br_0_15 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c15 bl_0_15 br_0_15 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c15 bl_0_15 br_0_15 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c15 bl_0_15 br_0_15 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c15 bl_0_15 br_0_15 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c15 bl_0_15 br_0_15 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c15 bl_0_15 br_0_15 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c15 bl_0_15 br_0_15 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c15 bl_0_15 br_0_15 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c15 bl_0_15 br_0_15 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c15 bl_0_15 br_0_15 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c15 bl_0_15 br_0_15 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c15 bl_0_15 br_0_15 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c15 bl_0_15 br_0_15 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c15 bl_0_15 br_0_15 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c15 bl_0_15 br_0_15 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c15 bl_0_15 br_0_15 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c16 bl_0_16 br_0_16 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c16 bl_0_16 br_0_16 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c16 bl_0_16 br_0_16 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c16 bl_0_16 br_0_16 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c16 bl_0_16 br_0_16 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c16 bl_0_16 br_0_16 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c16 bl_0_16 br_0_16 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c16 bl_0_16 br_0_16 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c16 bl_0_16 br_0_16 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c16 bl_0_16 br_0_16 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c16 bl_0_16 br_0_16 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c16 bl_0_16 br_0_16 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c16 bl_0_16 br_0_16 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c16 bl_0_16 br_0_16 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c16 bl_0_16 br_0_16 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c16 bl_0_16 br_0_16 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c16 bl_0_16 br_0_16 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c16 bl_0_16 br_0_16 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c16 bl_0_16 br_0_16 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c16 bl_0_16 br_0_16 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c16 bl_0_16 br_0_16 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c16 bl_0_16 br_0_16 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c16 bl_0_16 br_0_16 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c16 bl_0_16 br_0_16 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c16 bl_0_16 br_0_16 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c16 bl_0_16 br_0_16 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c16 bl_0_16 br_0_16 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c16 bl_0_16 br_0_16 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c16 bl_0_16 br_0_16 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c16 bl_0_16 br_0_16 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c16 bl_0_16 br_0_16 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c17 bl_0_17 br_0_17 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c17 bl_0_17 br_0_17 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c17 bl_0_17 br_0_17 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c17 bl_0_17 br_0_17 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c17 bl_0_17 br_0_17 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c17 bl_0_17 br_0_17 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c17 bl_0_17 br_0_17 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c17 bl_0_17 br_0_17 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c17 bl_0_17 br_0_17 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c17 bl_0_17 br_0_17 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c17 bl_0_17 br_0_17 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c17 bl_0_17 br_0_17 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c17 bl_0_17 br_0_17 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c17 bl_0_17 br_0_17 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c17 bl_0_17 br_0_17 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c17 bl_0_17 br_0_17 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c17 bl_0_17 br_0_17 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c17 bl_0_17 br_0_17 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c17 bl_0_17 br_0_17 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c17 bl_0_17 br_0_17 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c17 bl_0_17 br_0_17 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c17 bl_0_17 br_0_17 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c17 bl_0_17 br_0_17 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c17 bl_0_17 br_0_17 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c17 bl_0_17 br_0_17 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c17 bl_0_17 br_0_17 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c17 bl_0_17 br_0_17 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c17 bl_0_17 br_0_17 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c17 bl_0_17 br_0_17 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c17 bl_0_17 br_0_17 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c17 bl_0_17 br_0_17 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c18 bl_0_18 br_0_18 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c18 bl_0_18 br_0_18 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c18 bl_0_18 br_0_18 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c18 bl_0_18 br_0_18 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c18 bl_0_18 br_0_18 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c18 bl_0_18 br_0_18 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c18 bl_0_18 br_0_18 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c18 bl_0_18 br_0_18 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c18 bl_0_18 br_0_18 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c18 bl_0_18 br_0_18 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c18 bl_0_18 br_0_18 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c18 bl_0_18 br_0_18 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c18 bl_0_18 br_0_18 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c18 bl_0_18 br_0_18 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c18 bl_0_18 br_0_18 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c18 bl_0_18 br_0_18 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c18 bl_0_18 br_0_18 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c18 bl_0_18 br_0_18 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c18 bl_0_18 br_0_18 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c18 bl_0_18 br_0_18 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c18 bl_0_18 br_0_18 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c18 bl_0_18 br_0_18 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c18 bl_0_18 br_0_18 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c18 bl_0_18 br_0_18 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c18 bl_0_18 br_0_18 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c18 bl_0_18 br_0_18 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c18 bl_0_18 br_0_18 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c18 bl_0_18 br_0_18 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c18 bl_0_18 br_0_18 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c18 bl_0_18 br_0_18 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c18 bl_0_18 br_0_18 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c19 bl_0_19 br_0_19 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c19 bl_0_19 br_0_19 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c19 bl_0_19 br_0_19 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c19 bl_0_19 br_0_19 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c19 bl_0_19 br_0_19 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c19 bl_0_19 br_0_19 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c19 bl_0_19 br_0_19 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c19 bl_0_19 br_0_19 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c19 bl_0_19 br_0_19 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c19 bl_0_19 br_0_19 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c19 bl_0_19 br_0_19 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c19 bl_0_19 br_0_19 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c19 bl_0_19 br_0_19 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c19 bl_0_19 br_0_19 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c19 bl_0_19 br_0_19 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c19 bl_0_19 br_0_19 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c19 bl_0_19 br_0_19 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c19 bl_0_19 br_0_19 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c19 bl_0_19 br_0_19 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c19 bl_0_19 br_0_19 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c19 bl_0_19 br_0_19 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c19 bl_0_19 br_0_19 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c19 bl_0_19 br_0_19 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c19 bl_0_19 br_0_19 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c19 bl_0_19 br_0_19 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c19 bl_0_19 br_0_19 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c19 bl_0_19 br_0_19 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c19 bl_0_19 br_0_19 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c19 bl_0_19 br_0_19 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c19 bl_0_19 br_0_19 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c19 bl_0_19 br_0_19 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c20 bl_0_20 br_0_20 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c20 bl_0_20 br_0_20 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c20 bl_0_20 br_0_20 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c20 bl_0_20 br_0_20 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c20 bl_0_20 br_0_20 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c20 bl_0_20 br_0_20 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c20 bl_0_20 br_0_20 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c20 bl_0_20 br_0_20 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c20 bl_0_20 br_0_20 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c20 bl_0_20 br_0_20 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c20 bl_0_20 br_0_20 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c20 bl_0_20 br_0_20 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c20 bl_0_20 br_0_20 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c20 bl_0_20 br_0_20 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c20 bl_0_20 br_0_20 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c20 bl_0_20 br_0_20 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c20 bl_0_20 br_0_20 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c20 bl_0_20 br_0_20 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c20 bl_0_20 br_0_20 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c20 bl_0_20 br_0_20 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c20 bl_0_20 br_0_20 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c20 bl_0_20 br_0_20 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c20 bl_0_20 br_0_20 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c20 bl_0_20 br_0_20 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c20 bl_0_20 br_0_20 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c20 bl_0_20 br_0_20 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c20 bl_0_20 br_0_20 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c20 bl_0_20 br_0_20 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c20 bl_0_20 br_0_20 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c20 bl_0_20 br_0_20 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c20 bl_0_20 br_0_20 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c21 bl_0_21 br_0_21 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c21 bl_0_21 br_0_21 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c21 bl_0_21 br_0_21 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c21 bl_0_21 br_0_21 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c21 bl_0_21 br_0_21 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c21 bl_0_21 br_0_21 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c21 bl_0_21 br_0_21 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c21 bl_0_21 br_0_21 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c21 bl_0_21 br_0_21 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c21 bl_0_21 br_0_21 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c21 bl_0_21 br_0_21 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c21 bl_0_21 br_0_21 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c21 bl_0_21 br_0_21 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c21 bl_0_21 br_0_21 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c21 bl_0_21 br_0_21 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c21 bl_0_21 br_0_21 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c21 bl_0_21 br_0_21 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c21 bl_0_21 br_0_21 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c21 bl_0_21 br_0_21 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c21 bl_0_21 br_0_21 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c21 bl_0_21 br_0_21 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c21 bl_0_21 br_0_21 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c21 bl_0_21 br_0_21 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c21 bl_0_21 br_0_21 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c21 bl_0_21 br_0_21 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c21 bl_0_21 br_0_21 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c21 bl_0_21 br_0_21 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c21 bl_0_21 br_0_21 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c21 bl_0_21 br_0_21 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c21 bl_0_21 br_0_21 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c21 bl_0_21 br_0_21 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c22 bl_0_22 br_0_22 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c22 bl_0_22 br_0_22 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c22 bl_0_22 br_0_22 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c22 bl_0_22 br_0_22 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c22 bl_0_22 br_0_22 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c22 bl_0_22 br_0_22 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c22 bl_0_22 br_0_22 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c22 bl_0_22 br_0_22 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c22 bl_0_22 br_0_22 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c22 bl_0_22 br_0_22 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c22 bl_0_22 br_0_22 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c22 bl_0_22 br_0_22 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c22 bl_0_22 br_0_22 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c22 bl_0_22 br_0_22 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c22 bl_0_22 br_0_22 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c22 bl_0_22 br_0_22 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c22 bl_0_22 br_0_22 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c22 bl_0_22 br_0_22 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c22 bl_0_22 br_0_22 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c22 bl_0_22 br_0_22 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c22 bl_0_22 br_0_22 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c22 bl_0_22 br_0_22 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c22 bl_0_22 br_0_22 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c22 bl_0_22 br_0_22 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c22 bl_0_22 br_0_22 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c22 bl_0_22 br_0_22 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c22 bl_0_22 br_0_22 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c22 bl_0_22 br_0_22 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c22 bl_0_22 br_0_22 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c22 bl_0_22 br_0_22 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c22 bl_0_22 br_0_22 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c23 bl_0_23 br_0_23 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c23 bl_0_23 br_0_23 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c23 bl_0_23 br_0_23 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c23 bl_0_23 br_0_23 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c23 bl_0_23 br_0_23 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c23 bl_0_23 br_0_23 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c23 bl_0_23 br_0_23 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c23 bl_0_23 br_0_23 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c23 bl_0_23 br_0_23 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c23 bl_0_23 br_0_23 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c23 bl_0_23 br_0_23 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c23 bl_0_23 br_0_23 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c23 bl_0_23 br_0_23 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c23 bl_0_23 br_0_23 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c23 bl_0_23 br_0_23 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c23 bl_0_23 br_0_23 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c23 bl_0_23 br_0_23 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c23 bl_0_23 br_0_23 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c23 bl_0_23 br_0_23 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c23 bl_0_23 br_0_23 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c23 bl_0_23 br_0_23 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c23 bl_0_23 br_0_23 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c23 bl_0_23 br_0_23 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c23 bl_0_23 br_0_23 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c23 bl_0_23 br_0_23 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c23 bl_0_23 br_0_23 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c23 bl_0_23 br_0_23 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c23 bl_0_23 br_0_23 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c23 bl_0_23 br_0_23 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c23 bl_0_23 br_0_23 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c23 bl_0_23 br_0_23 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c24 bl_0_24 br_0_24 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c24 bl_0_24 br_0_24 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c24 bl_0_24 br_0_24 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c24 bl_0_24 br_0_24 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c24 bl_0_24 br_0_24 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c24 bl_0_24 br_0_24 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c24 bl_0_24 br_0_24 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c24 bl_0_24 br_0_24 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c24 bl_0_24 br_0_24 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c24 bl_0_24 br_0_24 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c24 bl_0_24 br_0_24 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c24 bl_0_24 br_0_24 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c24 bl_0_24 br_0_24 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c24 bl_0_24 br_0_24 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c24 bl_0_24 br_0_24 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c24 bl_0_24 br_0_24 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c24 bl_0_24 br_0_24 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c24 bl_0_24 br_0_24 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c24 bl_0_24 br_0_24 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c24 bl_0_24 br_0_24 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c24 bl_0_24 br_0_24 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c24 bl_0_24 br_0_24 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c24 bl_0_24 br_0_24 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c24 bl_0_24 br_0_24 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c24 bl_0_24 br_0_24 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c24 bl_0_24 br_0_24 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c24 bl_0_24 br_0_24 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c24 bl_0_24 br_0_24 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c24 bl_0_24 br_0_24 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c24 bl_0_24 br_0_24 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c24 bl_0_24 br_0_24 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c25 bl_0_25 br_0_25 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c25 bl_0_25 br_0_25 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c25 bl_0_25 br_0_25 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c25 bl_0_25 br_0_25 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c25 bl_0_25 br_0_25 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c25 bl_0_25 br_0_25 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c25 bl_0_25 br_0_25 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c25 bl_0_25 br_0_25 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c25 bl_0_25 br_0_25 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c25 bl_0_25 br_0_25 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c25 bl_0_25 br_0_25 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c25 bl_0_25 br_0_25 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c25 bl_0_25 br_0_25 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c25 bl_0_25 br_0_25 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c25 bl_0_25 br_0_25 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c25 bl_0_25 br_0_25 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c25 bl_0_25 br_0_25 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c25 bl_0_25 br_0_25 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c25 bl_0_25 br_0_25 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c25 bl_0_25 br_0_25 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c25 bl_0_25 br_0_25 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c25 bl_0_25 br_0_25 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c25 bl_0_25 br_0_25 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c25 bl_0_25 br_0_25 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c25 bl_0_25 br_0_25 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c25 bl_0_25 br_0_25 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c25 bl_0_25 br_0_25 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c25 bl_0_25 br_0_25 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c25 bl_0_25 br_0_25 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c25 bl_0_25 br_0_25 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c25 bl_0_25 br_0_25 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c26 bl_0_26 br_0_26 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c26 bl_0_26 br_0_26 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c26 bl_0_26 br_0_26 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c26 bl_0_26 br_0_26 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c26 bl_0_26 br_0_26 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c26 bl_0_26 br_0_26 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c26 bl_0_26 br_0_26 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c26 bl_0_26 br_0_26 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c26 bl_0_26 br_0_26 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c26 bl_0_26 br_0_26 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c26 bl_0_26 br_0_26 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c26 bl_0_26 br_0_26 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c26 bl_0_26 br_0_26 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c26 bl_0_26 br_0_26 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c26 bl_0_26 br_0_26 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c26 bl_0_26 br_0_26 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c26 bl_0_26 br_0_26 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c26 bl_0_26 br_0_26 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c26 bl_0_26 br_0_26 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c26 bl_0_26 br_0_26 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c26 bl_0_26 br_0_26 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c26 bl_0_26 br_0_26 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c26 bl_0_26 br_0_26 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c26 bl_0_26 br_0_26 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c26 bl_0_26 br_0_26 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c26 bl_0_26 br_0_26 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c26 bl_0_26 br_0_26 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c26 bl_0_26 br_0_26 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c26 bl_0_26 br_0_26 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c26 bl_0_26 br_0_26 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c26 bl_0_26 br_0_26 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c27 bl_0_27 br_0_27 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c27 bl_0_27 br_0_27 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c27 bl_0_27 br_0_27 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c27 bl_0_27 br_0_27 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c27 bl_0_27 br_0_27 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c27 bl_0_27 br_0_27 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c27 bl_0_27 br_0_27 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c27 bl_0_27 br_0_27 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c27 bl_0_27 br_0_27 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c27 bl_0_27 br_0_27 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c27 bl_0_27 br_0_27 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c27 bl_0_27 br_0_27 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c27 bl_0_27 br_0_27 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c27 bl_0_27 br_0_27 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c27 bl_0_27 br_0_27 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c27 bl_0_27 br_0_27 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c27 bl_0_27 br_0_27 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c27 bl_0_27 br_0_27 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c27 bl_0_27 br_0_27 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c27 bl_0_27 br_0_27 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c27 bl_0_27 br_0_27 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c27 bl_0_27 br_0_27 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c27 bl_0_27 br_0_27 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c27 bl_0_27 br_0_27 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c27 bl_0_27 br_0_27 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c27 bl_0_27 br_0_27 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c27 bl_0_27 br_0_27 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c27 bl_0_27 br_0_27 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c27 bl_0_27 br_0_27 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c27 bl_0_27 br_0_27 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c27 bl_0_27 br_0_27 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c28 bl_0_28 br_0_28 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c28 bl_0_28 br_0_28 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c28 bl_0_28 br_0_28 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c28 bl_0_28 br_0_28 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c28 bl_0_28 br_0_28 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c28 bl_0_28 br_0_28 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c28 bl_0_28 br_0_28 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c28 bl_0_28 br_0_28 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c28 bl_0_28 br_0_28 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c28 bl_0_28 br_0_28 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c28 bl_0_28 br_0_28 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c28 bl_0_28 br_0_28 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c28 bl_0_28 br_0_28 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c28 bl_0_28 br_0_28 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c28 bl_0_28 br_0_28 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c28 bl_0_28 br_0_28 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c28 bl_0_28 br_0_28 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c28 bl_0_28 br_0_28 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c28 bl_0_28 br_0_28 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c28 bl_0_28 br_0_28 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c28 bl_0_28 br_0_28 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c28 bl_0_28 br_0_28 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c28 bl_0_28 br_0_28 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c28 bl_0_28 br_0_28 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c28 bl_0_28 br_0_28 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c28 bl_0_28 br_0_28 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c28 bl_0_28 br_0_28 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c28 bl_0_28 br_0_28 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c28 bl_0_28 br_0_28 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c28 bl_0_28 br_0_28 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c28 bl_0_28 br_0_28 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c29 bl_0_29 br_0_29 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c29 bl_0_29 br_0_29 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c29 bl_0_29 br_0_29 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c29 bl_0_29 br_0_29 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c29 bl_0_29 br_0_29 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c29 bl_0_29 br_0_29 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c29 bl_0_29 br_0_29 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c29 bl_0_29 br_0_29 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c29 bl_0_29 br_0_29 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c29 bl_0_29 br_0_29 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c29 bl_0_29 br_0_29 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c29 bl_0_29 br_0_29 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c29 bl_0_29 br_0_29 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c29 bl_0_29 br_0_29 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c29 bl_0_29 br_0_29 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c29 bl_0_29 br_0_29 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c29 bl_0_29 br_0_29 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c29 bl_0_29 br_0_29 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c29 bl_0_29 br_0_29 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c29 bl_0_29 br_0_29 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c29 bl_0_29 br_0_29 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c29 bl_0_29 br_0_29 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c29 bl_0_29 br_0_29 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c29 bl_0_29 br_0_29 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c29 bl_0_29 br_0_29 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c29 bl_0_29 br_0_29 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c29 bl_0_29 br_0_29 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c29 bl_0_29 br_0_29 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c29 bl_0_29 br_0_29 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c29 bl_0_29 br_0_29 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c29 bl_0_29 br_0_29 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c30 bl_0_30 br_0_30 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c30 bl_0_30 br_0_30 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c30 bl_0_30 br_0_30 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c30 bl_0_30 br_0_30 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c30 bl_0_30 br_0_30 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c30 bl_0_30 br_0_30 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c30 bl_0_30 br_0_30 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c30 bl_0_30 br_0_30 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c30 bl_0_30 br_0_30 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c30 bl_0_30 br_0_30 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c30 bl_0_30 br_0_30 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c30 bl_0_30 br_0_30 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c30 bl_0_30 br_0_30 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c30 bl_0_30 br_0_30 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c30 bl_0_30 br_0_30 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c30 bl_0_30 br_0_30 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c30 bl_0_30 br_0_30 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c30 bl_0_30 br_0_30 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c30 bl_0_30 br_0_30 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c30 bl_0_30 br_0_30 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c30 bl_0_30 br_0_30 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c30 bl_0_30 br_0_30 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c30 bl_0_30 br_0_30 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c30 bl_0_30 br_0_30 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c30 bl_0_30 br_0_30 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c30 bl_0_30 br_0_30 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c30 bl_0_30 br_0_30 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c30 bl_0_30 br_0_30 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c30 bl_0_30 br_0_30 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c30 bl_0_30 br_0_30 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c30 bl_0_30 br_0_30 wl_0_31 vdd gnd cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd cell_1rw -Xbit_r1_c31 bl_0_31 br_0_31 wl_0_1 vdd gnd cell_1rw -Xbit_r2_c31 bl_0_31 br_0_31 wl_0_2 vdd gnd cell_1rw -Xbit_r3_c31 bl_0_31 br_0_31 wl_0_3 vdd gnd cell_1rw -Xbit_r4_c31 bl_0_31 br_0_31 wl_0_4 vdd gnd cell_1rw -Xbit_r5_c31 bl_0_31 br_0_31 wl_0_5 vdd gnd cell_1rw -Xbit_r6_c31 bl_0_31 br_0_31 wl_0_6 vdd gnd cell_1rw -Xbit_r7_c31 bl_0_31 br_0_31 wl_0_7 vdd gnd cell_1rw -Xbit_r8_c31 bl_0_31 br_0_31 wl_0_8 vdd gnd cell_1rw -Xbit_r9_c31 bl_0_31 br_0_31 wl_0_9 vdd gnd cell_1rw -Xbit_r10_c31 bl_0_31 br_0_31 wl_0_10 vdd gnd cell_1rw -Xbit_r11_c31 bl_0_31 br_0_31 wl_0_11 vdd gnd cell_1rw -Xbit_r12_c31 bl_0_31 br_0_31 wl_0_12 vdd gnd cell_1rw -Xbit_r13_c31 bl_0_31 br_0_31 wl_0_13 vdd gnd cell_1rw -Xbit_r14_c31 bl_0_31 br_0_31 wl_0_14 vdd gnd cell_1rw -Xbit_r15_c31 bl_0_31 br_0_31 wl_0_15 vdd gnd cell_1rw -Xbit_r16_c31 bl_0_31 br_0_31 wl_0_16 vdd gnd cell_1rw -Xbit_r17_c31 bl_0_31 br_0_31 wl_0_17 vdd gnd cell_1rw -Xbit_r18_c31 bl_0_31 br_0_31 wl_0_18 vdd gnd cell_1rw -Xbit_r19_c31 bl_0_31 br_0_31 wl_0_19 vdd gnd cell_1rw -Xbit_r20_c31 bl_0_31 br_0_31 wl_0_20 vdd gnd cell_1rw -Xbit_r21_c31 bl_0_31 br_0_31 wl_0_21 vdd gnd cell_1rw -Xbit_r22_c31 bl_0_31 br_0_31 wl_0_22 vdd gnd cell_1rw -Xbit_r23_c31 bl_0_31 br_0_31 wl_0_23 vdd gnd cell_1rw -Xbit_r24_c31 bl_0_31 br_0_31 wl_0_24 vdd gnd cell_1rw -Xbit_r25_c31 bl_0_31 br_0_31 wl_0_25 vdd gnd cell_1rw -Xbit_r26_c31 bl_0_31 br_0_31 wl_0_26 vdd gnd cell_1rw -Xbit_r27_c31 bl_0_31 br_0_31 wl_0_27 vdd gnd cell_1rw -Xbit_r28_c31 bl_0_31 br_0_31 wl_0_28 vdd gnd cell_1rw -Xbit_r29_c31 bl_0_31 br_0_31 wl_0_29 vdd gnd cell_1rw -Xbit_r30_c31 bl_0_31 br_0_31 wl_0_30 vdd gnd cell_1rw -Xbit_r31_c31 bl_0_31 br_0_31 wl_0_31 vdd gnd cell_1rw -.ENDS bitcell_array - -*********************** "dummy_cell_1rw" ****************************** -.SUBCKT dummy_cell_1rw bl br wl vdd gnd - -* Inverter 1 -M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u -M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u -M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT dummy_array_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_0 - -.SUBCKT dummy_array_2 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS dummy_array_2 - -.SUBCKT dummy_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array - -.SUBCKT dummy_array_3 bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:B br_0_0:B wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r1_c0 bl_0_0 br_0_0 wl_0_1 vdd gnd dummy_cell_1rw -Xbit_r2_c0 bl_0_0 br_0_0 wl_0_2 vdd gnd dummy_cell_1rw -Xbit_r3_c0 bl_0_0 br_0_0 wl_0_3 vdd gnd dummy_cell_1rw -Xbit_r4_c0 bl_0_0 br_0_0 wl_0_4 vdd gnd dummy_cell_1rw -Xbit_r5_c0 bl_0_0 br_0_0 wl_0_5 vdd gnd dummy_cell_1rw -Xbit_r6_c0 bl_0_0 br_0_0 wl_0_6 vdd gnd dummy_cell_1rw -Xbit_r7_c0 bl_0_0 br_0_0 wl_0_7 vdd gnd dummy_cell_1rw -Xbit_r8_c0 bl_0_0 br_0_0 wl_0_8 vdd gnd dummy_cell_1rw -Xbit_r9_c0 bl_0_0 br_0_0 wl_0_9 vdd gnd dummy_cell_1rw -Xbit_r10_c0 bl_0_0 br_0_0 wl_0_10 vdd gnd dummy_cell_1rw -Xbit_r11_c0 bl_0_0 br_0_0 wl_0_11 vdd gnd dummy_cell_1rw -Xbit_r12_c0 bl_0_0 br_0_0 wl_0_12 vdd gnd dummy_cell_1rw -Xbit_r13_c0 bl_0_0 br_0_0 wl_0_13 vdd gnd dummy_cell_1rw -Xbit_r14_c0 bl_0_0 br_0_0 wl_0_14 vdd gnd dummy_cell_1rw -Xbit_r15_c0 bl_0_0 br_0_0 wl_0_15 vdd gnd dummy_cell_1rw -Xbit_r16_c0 bl_0_0 br_0_0 wl_0_16 vdd gnd dummy_cell_1rw -Xbit_r17_c0 bl_0_0 br_0_0 wl_0_17 vdd gnd dummy_cell_1rw -Xbit_r18_c0 bl_0_0 br_0_0 wl_0_18 vdd gnd dummy_cell_1rw -Xbit_r19_c0 bl_0_0 br_0_0 wl_0_19 vdd gnd dummy_cell_1rw -Xbit_r20_c0 bl_0_0 br_0_0 wl_0_20 vdd gnd dummy_cell_1rw -Xbit_r21_c0 bl_0_0 br_0_0 wl_0_21 vdd gnd dummy_cell_1rw -Xbit_r22_c0 bl_0_0 br_0_0 wl_0_22 vdd gnd dummy_cell_1rw -Xbit_r23_c0 bl_0_0 br_0_0 wl_0_23 vdd gnd dummy_cell_1rw -Xbit_r24_c0 bl_0_0 br_0_0 wl_0_24 vdd gnd dummy_cell_1rw -Xbit_r25_c0 bl_0_0 br_0_0 wl_0_25 vdd gnd dummy_cell_1rw -Xbit_r26_c0 bl_0_0 br_0_0 wl_0_26 vdd gnd dummy_cell_1rw -Xbit_r27_c0 bl_0_0 br_0_0 wl_0_27 vdd gnd dummy_cell_1rw -Xbit_r28_c0 bl_0_0 br_0_0 wl_0_28 vdd gnd dummy_cell_1rw -Xbit_r29_c0 bl_0_0 br_0_0 wl_0_29 vdd gnd dummy_cell_1rw -Xbit_r30_c0 bl_0_0 br_0_0 wl_0_30 vdd gnd dummy_cell_1rw -Xbit_r31_c0 bl_0_0 br_0_0 wl_0_31 vdd gnd dummy_cell_1rw -Xbit_r32_c0 bl_0_0 br_0_0 wl_0_32 vdd gnd dummy_cell_1rw -Xbit_r33_c0 bl_0_0 br_0_0 wl_0_33 vdd gnd dummy_cell_1rw -Xbit_r34_c0 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS dummy_array_3 - -.SUBCKT dummy_array_1 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 vdd gnd -*.PININFO bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B wl_0_0:I vdd:B gnd:B -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : wl_0_0 -* POWER : vdd -* GROUND: gnd -Xbit_r0_c0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c1 bl_0_1 br_0_1 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c2 bl_0_2 br_0_2 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c3 bl_0_3 br_0_3 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c4 bl_0_4 br_0_4 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c5 bl_0_5 br_0_5 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c6 bl_0_6 br_0_6 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c7 bl_0_7 br_0_7 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c8 bl_0_8 br_0_8 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c9 bl_0_9 br_0_9 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c10 bl_0_10 br_0_10 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c11 bl_0_11 br_0_11 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c12 bl_0_12 br_0_12 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c13 bl_0_13 br_0_13 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c14 bl_0_14 br_0_14 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c15 bl_0_15 br_0_15 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c16 bl_0_16 br_0_16 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c17 bl_0_17 br_0_17 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c18 bl_0_18 br_0_18 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c19 bl_0_19 br_0_19 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c20 bl_0_20 br_0_20 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c21 bl_0_21 br_0_21 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c22 bl_0_22 br_0_22 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c23 bl_0_23 br_0_23 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c24 bl_0_24 br_0_24 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c25 bl_0_25 br_0_25 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c26 bl_0_26 br_0_26 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c27 bl_0_27 br_0_27 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c28 bl_0_28 br_0_28 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c29 bl_0_29 br_0_29 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c30 bl_0_30 br_0_30 wl_0_0 vdd gnd dummy_cell_1rw -Xbit_r0_c31 bl_0_31 br_0_31 wl_0_0 vdd gnd dummy_cell_1rw -.ENDS dummy_array_1 - -*********************** "cell_1rw" ****************************** -.SUBCKT replica_cell_1rw bl br wl vdd gnd -* SPICE3 file created from cell_1rw.ext - technology: scmos - -* Inverter 1 -M1000 Q vdd vdd vdd p w=0.6u l=0.8u -M1002 Q vdd gnd gnd n w=1.6u l=0.4u - -* Inverter 2 -M1001 vdd Q vdd vdd p w=0.6u l=0.8u -M1003 gnd Q vdd gnd n w=1.6u l=0.4u - -* Access transistors -M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 vdd wl br gnd n w=0.8u l=0.4u - -.ENDS - -.SUBCKT replica_column bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 wl_0_32 wl_0_33 wl_0_34 vdd gnd -*.PININFO bl_0_0:O br_0_0:O wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I wl_0_32:I wl_0_33:I wl_0_34:I vdd:B gnd:B -* OUTPUT: bl_0_0 -* OUTPUT: br_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* INPUT : wl_0_32 -* INPUT : wl_0_33 -* INPUT : wl_0_34 -* POWER : vdd -* GROUND: gnd -Xrbc_0 bl_0_0 br_0_0 wl_0_0 vdd gnd dummy_cell_1rw -Xrbc_1 bl_0_0 br_0_0 wl_0_1 vdd gnd replica_cell_1rw -Xrbc_2 bl_0_0 br_0_0 wl_0_2 vdd gnd replica_cell_1rw -Xrbc_3 bl_0_0 br_0_0 wl_0_3 vdd gnd replica_cell_1rw -Xrbc_4 bl_0_0 br_0_0 wl_0_4 vdd gnd replica_cell_1rw -Xrbc_5 bl_0_0 br_0_0 wl_0_5 vdd gnd replica_cell_1rw -Xrbc_6 bl_0_0 br_0_0 wl_0_6 vdd gnd replica_cell_1rw -Xrbc_7 bl_0_0 br_0_0 wl_0_7 vdd gnd replica_cell_1rw -Xrbc_8 bl_0_0 br_0_0 wl_0_8 vdd gnd replica_cell_1rw -Xrbc_9 bl_0_0 br_0_0 wl_0_9 vdd gnd replica_cell_1rw -Xrbc_10 bl_0_0 br_0_0 wl_0_10 vdd gnd replica_cell_1rw -Xrbc_11 bl_0_0 br_0_0 wl_0_11 vdd gnd replica_cell_1rw -Xrbc_12 bl_0_0 br_0_0 wl_0_12 vdd gnd replica_cell_1rw -Xrbc_13 bl_0_0 br_0_0 wl_0_13 vdd gnd replica_cell_1rw -Xrbc_14 bl_0_0 br_0_0 wl_0_14 vdd gnd replica_cell_1rw -Xrbc_15 bl_0_0 br_0_0 wl_0_15 vdd gnd replica_cell_1rw -Xrbc_16 bl_0_0 br_0_0 wl_0_16 vdd gnd replica_cell_1rw -Xrbc_17 bl_0_0 br_0_0 wl_0_17 vdd gnd replica_cell_1rw -Xrbc_18 bl_0_0 br_0_0 wl_0_18 vdd gnd replica_cell_1rw -Xrbc_19 bl_0_0 br_0_0 wl_0_19 vdd gnd replica_cell_1rw -Xrbc_20 bl_0_0 br_0_0 wl_0_20 vdd gnd replica_cell_1rw -Xrbc_21 bl_0_0 br_0_0 wl_0_21 vdd gnd replica_cell_1rw -Xrbc_22 bl_0_0 br_0_0 wl_0_22 vdd gnd replica_cell_1rw -Xrbc_23 bl_0_0 br_0_0 wl_0_23 vdd gnd replica_cell_1rw -Xrbc_24 bl_0_0 br_0_0 wl_0_24 vdd gnd replica_cell_1rw -Xrbc_25 bl_0_0 br_0_0 wl_0_25 vdd gnd replica_cell_1rw -Xrbc_26 bl_0_0 br_0_0 wl_0_26 vdd gnd replica_cell_1rw -Xrbc_27 bl_0_0 br_0_0 wl_0_27 vdd gnd replica_cell_1rw -Xrbc_28 bl_0_0 br_0_0 wl_0_28 vdd gnd replica_cell_1rw -Xrbc_29 bl_0_0 br_0_0 wl_0_29 vdd gnd replica_cell_1rw -Xrbc_30 bl_0_0 br_0_0 wl_0_30 vdd gnd replica_cell_1rw -Xrbc_31 bl_0_0 br_0_0 wl_0_31 vdd gnd replica_cell_1rw -Xrbc_32 bl_0_0 br_0_0 wl_0_32 vdd gnd replica_cell_1rw -Xrbc_33 bl_0_0 br_0_0 wl_0_33 vdd gnd replica_cell_1rw -Xrbc_34 bl_0_0 br_0_0 wl_0_34 vdd gnd dummy_cell_1rw -.ENDS replica_column - -.SUBCKT replica_bitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd -*.PININFO rbl_bl_0_0:B rbl_br_0_0:B bl_0_0:B br_0_0:B bl_0_1:B br_0_1:B bl_0_2:B br_0_2:B bl_0_3:B br_0_3:B bl_0_4:B br_0_4:B bl_0_5:B br_0_5:B bl_0_6:B br_0_6:B bl_0_7:B br_0_7:B bl_0_8:B br_0_8:B bl_0_9:B br_0_9:B bl_0_10:B br_0_10:B bl_0_11:B br_0_11:B bl_0_12:B br_0_12:B bl_0_13:B br_0_13:B bl_0_14:B br_0_14:B bl_0_15:B br_0_15:B bl_0_16:B br_0_16:B bl_0_17:B br_0_17:B bl_0_18:B br_0_18:B bl_0_19:B br_0_19:B bl_0_20:B br_0_20:B bl_0_21:B br_0_21:B bl_0_22:B br_0_22:B bl_0_23:B br_0_23:B bl_0_24:B br_0_24:B bl_0_25:B br_0_25:B bl_0_26:B br_0_26:B bl_0_27:B br_0_27:B bl_0_28:B br_0_28:B bl_0_29:B br_0_29:B bl_0_30:B br_0_30:B bl_0_31:B br_0_31:B rbl_wl_0_0:I wl_0_0:I wl_0_1:I wl_0_2:I wl_0_3:I wl_0_4:I wl_0_5:I wl_0_6:I wl_0_7:I wl_0_8:I wl_0_9:I wl_0_10:I wl_0_11:I wl_0_12:I wl_0_13:I wl_0_14:I wl_0_15:I wl_0_16:I wl_0_17:I wl_0_18:I wl_0_19:I wl_0_20:I wl_0_21:I wl_0_22:I wl_0_23:I wl_0_24:I wl_0_25:I wl_0_26:I wl_0_27:I wl_0_28:I wl_0_29:I wl_0_30:I wl_0_31:I vdd:B gnd:B -* INOUT : rbl_bl_0_0 -* INOUT : rbl_br_0_0 -* INOUT : bl_0_0 -* INOUT : br_0_0 -* INOUT : bl_0_1 -* INOUT : br_0_1 -* INOUT : bl_0_2 -* INOUT : br_0_2 -* INOUT : bl_0_3 -* INOUT : br_0_3 -* INOUT : bl_0_4 -* INOUT : br_0_4 -* INOUT : bl_0_5 -* INOUT : br_0_5 -* INOUT : bl_0_6 -* INOUT : br_0_6 -* INOUT : bl_0_7 -* INOUT : br_0_7 -* INOUT : bl_0_8 -* INOUT : br_0_8 -* INOUT : bl_0_9 -* INOUT : br_0_9 -* INOUT : bl_0_10 -* INOUT : br_0_10 -* INOUT : bl_0_11 -* INOUT : br_0_11 -* INOUT : bl_0_12 -* INOUT : br_0_12 -* INOUT : bl_0_13 -* INOUT : br_0_13 -* INOUT : bl_0_14 -* INOUT : br_0_14 -* INOUT : bl_0_15 -* INOUT : br_0_15 -* INOUT : bl_0_16 -* INOUT : br_0_16 -* INOUT : bl_0_17 -* INOUT : br_0_17 -* INOUT : bl_0_18 -* INOUT : br_0_18 -* INOUT : bl_0_19 -* INOUT : br_0_19 -* INOUT : bl_0_20 -* INOUT : br_0_20 -* INOUT : bl_0_21 -* INOUT : br_0_21 -* INOUT : bl_0_22 -* INOUT : br_0_22 -* INOUT : bl_0_23 -* INOUT : br_0_23 -* INOUT : bl_0_24 -* INOUT : br_0_24 -* INOUT : bl_0_25 -* INOUT : br_0_25 -* INOUT : bl_0_26 -* INOUT : br_0_26 -* INOUT : bl_0_27 -* INOUT : br_0_27 -* INOUT : bl_0_28 -* INOUT : br_0_28 -* INOUT : bl_0_29 -* INOUT : br_0_29 -* INOUT : bl_0_30 -* INOUT : br_0_30 -* INOUT : bl_0_31 -* INOUT : br_0_31 -* INPUT : rbl_wl_0_0 -* INPUT : wl_0_0 -* INPUT : wl_0_1 -* INPUT : wl_0_2 -* INPUT : wl_0_3 -* INPUT : wl_0_4 -* INPUT : wl_0_5 -* INPUT : wl_0_6 -* INPUT : wl_0_7 -* INPUT : wl_0_8 -* INPUT : wl_0_9 -* INPUT : wl_0_10 -* INPUT : wl_0_11 -* INPUT : wl_0_12 -* INPUT : wl_0_13 -* INPUT : wl_0_14 -* INPUT : wl_0_15 -* INPUT : wl_0_16 -* INPUT : wl_0_17 -* INPUT : wl_0_18 -* INPUT : wl_0_19 -* INPUT : wl_0_20 -* INPUT : wl_0_21 -* INPUT : wl_0_22 -* INPUT : wl_0_23 -* INPUT : wl_0_24 -* INPUT : wl_0_25 -* INPUT : wl_0_26 -* INPUT : wl_0_27 -* INPUT : wl_0_28 -* INPUT : wl_0_29 -* INPUT : wl_0_30 -* INPUT : wl_0_31 -* POWER : vdd -* GROUND: gnd -* rbl: None left_rbl: None right_rbl: None -Xbitcell_array bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd bitcell_array -Xreplica_col_0 rbl_bl_0_0 rbl_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd replica_column -Xdummy_row_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl_0_0 vdd gnd dummy_array -Xdummy_row_bot bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_1 -Xdummy_row_top bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 gnd vdd gnd dummy_array_0 -Xdummy_col_left dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_2 -Xdummy_col_right dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 gnd vdd gnd dummy_array_3 -.ENDS replica_bitcell_array -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=0.8u L=0.4u -M_2 din_bar din vdd vdd p W=1.4u L=0.4u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u -M_4 net_7 din gnd gnd n W=1.4u L=0.4u -M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u -M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=1.4u L=0.4u -M_10 din_gated en net_8 gnd n W=1.4u L=0.4u -M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u -M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u -M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u -M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u - - - -.ENDS $ write_driver - -.SUBCKT write_driver_array data_0 data_1 data_2 data_3 data_4 data_5 data_6 data_7 data_8 data_9 data_10 data_11 data_12 data_13 data_14 data_15 data_16 data_17 data_18 data_19 data_20 data_21 data_22 data_23 data_24 data_25 data_26 data_27 data_28 data_29 data_30 data_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 en vdd gnd -*.PININFO data_0:I data_1:I data_2:I data_3:I data_4:I data_5:I data_6:I data_7:I data_8:I data_9:I data_10:I data_11:I data_12:I data_13:I data_14:I data_15:I data_16:I data_17:I data_18:I data_19:I data_20:I data_21:I data_22:I data_23:I data_24:I data_25:I data_26:I data_27:I data_28:I data_29:I data_30:I data_31:I bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O en:I vdd:B gnd:B -* INPUT : data_0 -* INPUT : data_1 -* INPUT : data_2 -* INPUT : data_3 -* INPUT : data_4 -* INPUT : data_5 -* INPUT : data_6 -* INPUT : data_7 -* INPUT : data_8 -* INPUT : data_9 -* INPUT : data_10 -* INPUT : data_11 -* INPUT : data_12 -* INPUT : data_13 -* INPUT : data_14 -* INPUT : data_15 -* INPUT : data_16 -* INPUT : data_17 -* INPUT : data_18 -* INPUT : data_19 -* INPUT : data_20 -* INPUT : data_21 -* INPUT : data_22 -* INPUT : data_23 -* INPUT : data_24 -* INPUT : data_25 -* INPUT : data_26 -* INPUT : data_27 -* INPUT : data_28 -* INPUT : data_29 -* INPUT : data_30 -* INPUT : data_31 -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* word_size 32 -Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver -Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver -Xwrite_driver2 data_2 bl_2 br_2 en vdd gnd write_driver -Xwrite_driver3 data_3 bl_3 br_3 en vdd gnd write_driver -Xwrite_driver4 data_4 bl_4 br_4 en vdd gnd write_driver -Xwrite_driver5 data_5 bl_5 br_5 en vdd gnd write_driver -Xwrite_driver6 data_6 bl_6 br_6 en vdd gnd write_driver -Xwrite_driver7 data_7 bl_7 br_7 en vdd gnd write_driver -Xwrite_driver8 data_8 bl_8 br_8 en vdd gnd write_driver -Xwrite_driver9 data_9 bl_9 br_9 en vdd gnd write_driver -Xwrite_driver10 data_10 bl_10 br_10 en vdd gnd write_driver -Xwrite_driver11 data_11 bl_11 br_11 en vdd gnd write_driver -Xwrite_driver12 data_12 bl_12 br_12 en vdd gnd write_driver -Xwrite_driver13 data_13 bl_13 br_13 en vdd gnd write_driver -Xwrite_driver14 data_14 bl_14 br_14 en vdd gnd write_driver -Xwrite_driver15 data_15 bl_15 br_15 en vdd gnd write_driver -Xwrite_driver16 data_16 bl_16 br_16 en vdd gnd write_driver -Xwrite_driver17 data_17 bl_17 br_17 en vdd gnd write_driver -Xwrite_driver18 data_18 bl_18 br_18 en vdd gnd write_driver -Xwrite_driver19 data_19 bl_19 br_19 en vdd gnd write_driver -Xwrite_driver20 data_20 bl_20 br_20 en vdd gnd write_driver -Xwrite_driver21 data_21 bl_21 br_21 en vdd gnd write_driver -Xwrite_driver22 data_22 bl_22 br_22 en vdd gnd write_driver -Xwrite_driver23 data_23 bl_23 br_23 en vdd gnd write_driver -Xwrite_driver24 data_24 bl_24 br_24 en vdd gnd write_driver -Xwrite_driver25 data_25 bl_25 br_25 en vdd gnd write_driver -Xwrite_driver26 data_26 bl_26 br_26 en vdd gnd write_driver -Xwrite_driver27 data_27 bl_27 br_27 en vdd gnd write_driver -Xwrite_driver28 data_28 bl_28 br_28 en vdd gnd write_driver -Xwrite_driver29 data_29 bl_29 br_29 en vdd gnd write_driver -Xwrite_driver30 data_30 bl_30 br_30 en vdd gnd write_driver -Xwrite_driver31 data_31 bl_31 br_31 en vdd gnd write_driver -.ENDS write_driver_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT precharge_0 bl br en_bar vdd -*.PININFO bl:O br:O en_bar:I vdd:B -* OUTPUT: bl -* OUTPUT: br -* INPUT : en_bar -* POWER : vdd -Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS precharge_0 - -.SUBCKT precharge_array bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 bl_32 br_32 en_bar vdd -*.PININFO bl_0:O br_0:O bl_1:O br_1:O bl_2:O br_2:O bl_3:O br_3:O bl_4:O br_4:O bl_5:O br_5:O bl_6:O br_6:O bl_7:O br_7:O bl_8:O br_8:O bl_9:O br_9:O bl_10:O br_10:O bl_11:O br_11:O bl_12:O br_12:O bl_13:O br_13:O bl_14:O br_14:O bl_15:O br_15:O bl_16:O br_16:O bl_17:O br_17:O bl_18:O br_18:O bl_19:O br_19:O bl_20:O br_20:O bl_21:O br_21:O bl_22:O br_22:O bl_23:O br_23:O bl_24:O br_24:O bl_25:O br_25:O bl_26:O br_26:O bl_27:O br_27:O bl_28:O br_28:O bl_29:O br_29:O bl_30:O br_30:O bl_31:O br_31:O bl_32:O br_32:O en_bar:I vdd:B -* OUTPUT: bl_0 -* OUTPUT: br_0 -* OUTPUT: bl_1 -* OUTPUT: br_1 -* OUTPUT: bl_2 -* OUTPUT: br_2 -* OUTPUT: bl_3 -* OUTPUT: br_3 -* OUTPUT: bl_4 -* OUTPUT: br_4 -* OUTPUT: bl_5 -* OUTPUT: br_5 -* OUTPUT: bl_6 -* OUTPUT: br_6 -* OUTPUT: bl_7 -* OUTPUT: br_7 -* OUTPUT: bl_8 -* OUTPUT: br_8 -* OUTPUT: bl_9 -* OUTPUT: br_9 -* OUTPUT: bl_10 -* OUTPUT: br_10 -* OUTPUT: bl_11 -* OUTPUT: br_11 -* OUTPUT: bl_12 -* OUTPUT: br_12 -* OUTPUT: bl_13 -* OUTPUT: br_13 -* OUTPUT: bl_14 -* OUTPUT: br_14 -* OUTPUT: bl_15 -* OUTPUT: br_15 -* OUTPUT: bl_16 -* OUTPUT: br_16 -* OUTPUT: bl_17 -* OUTPUT: br_17 -* OUTPUT: bl_18 -* OUTPUT: br_18 -* OUTPUT: bl_19 -* OUTPUT: br_19 -* OUTPUT: bl_20 -* OUTPUT: br_20 -* OUTPUT: bl_21 -* OUTPUT: br_21 -* OUTPUT: bl_22 -* OUTPUT: br_22 -* OUTPUT: bl_23 -* OUTPUT: br_23 -* OUTPUT: bl_24 -* OUTPUT: br_24 -* OUTPUT: bl_25 -* OUTPUT: br_25 -* OUTPUT: bl_26 -* OUTPUT: br_26 -* OUTPUT: bl_27 -* OUTPUT: br_27 -* OUTPUT: bl_28 -* OUTPUT: br_28 -* OUTPUT: bl_29 -* OUTPUT: br_29 -* OUTPUT: bl_30 -* OUTPUT: br_30 -* OUTPUT: bl_31 -* OUTPUT: br_31 -* OUTPUT: bl_32 -* OUTPUT: br_32 -* INPUT : en_bar -* POWER : vdd -* cols: 33 size: 1 bl: bl br: br -Xpre_column_0 bl_0 br_0 en_bar vdd precharge_0 -Xpre_column_1 bl_1 br_1 en_bar vdd precharge_0 -Xpre_column_2 bl_2 br_2 en_bar vdd precharge_0 -Xpre_column_3 bl_3 br_3 en_bar vdd precharge_0 -Xpre_column_4 bl_4 br_4 en_bar vdd precharge_0 -Xpre_column_5 bl_5 br_5 en_bar vdd precharge_0 -Xpre_column_6 bl_6 br_6 en_bar vdd precharge_0 -Xpre_column_7 bl_7 br_7 en_bar vdd precharge_0 -Xpre_column_8 bl_8 br_8 en_bar vdd precharge_0 -Xpre_column_9 bl_9 br_9 en_bar vdd precharge_0 -Xpre_column_10 bl_10 br_10 en_bar vdd precharge_0 -Xpre_column_11 bl_11 br_11 en_bar vdd precharge_0 -Xpre_column_12 bl_12 br_12 en_bar vdd precharge_0 -Xpre_column_13 bl_13 br_13 en_bar vdd precharge_0 -Xpre_column_14 bl_14 br_14 en_bar vdd precharge_0 -Xpre_column_15 bl_15 br_15 en_bar vdd precharge_0 -Xpre_column_16 bl_16 br_16 en_bar vdd precharge_0 -Xpre_column_17 bl_17 br_17 en_bar vdd precharge_0 -Xpre_column_18 bl_18 br_18 en_bar vdd precharge_0 -Xpre_column_19 bl_19 br_19 en_bar vdd precharge_0 -Xpre_column_20 bl_20 br_20 en_bar vdd precharge_0 -Xpre_column_21 bl_21 br_21 en_bar vdd precharge_0 -Xpre_column_22 bl_22 br_22 en_bar vdd precharge_0 -Xpre_column_23 bl_23 br_23 en_bar vdd precharge_0 -Xpre_column_24 bl_24 br_24 en_bar vdd precharge_0 -Xpre_column_25 bl_25 br_25 en_bar vdd precharge_0 -Xpre_column_26 bl_26 br_26 en_bar vdd precharge_0 -Xpre_column_27 bl_27 br_27 en_bar vdd precharge_0 -Xpre_column_28 bl_28 br_28 en_bar vdd precharge_0 -Xpre_column_29 bl_29 br_29 en_bar vdd precharge_0 -Xpre_column_30 bl_30 br_30 en_bar vdd precharge_0 -Xpre_column_31 bl_31 br_31 en_bar vdd precharge_0 -Xpre_column_32 bl_32 br_32 en_bar vdd precharge_0 -.ENDS precharge_array -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd - -* SPICE3 file created from sense_amp.ext - technology: scmos - -M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u -M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u -M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u -M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u -M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u -M1005 bl en dout vdd p w=4.8u l=0.4u -M1006 a_48_304# en br vdd p w=4.8u l=0.4u - -.ENDS - -.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 data_2 bl_2 br_2 data_3 bl_3 br_3 data_4 bl_4 br_4 data_5 bl_5 br_5 data_6 bl_6 br_6 data_7 bl_7 br_7 data_8 bl_8 br_8 data_9 bl_9 br_9 data_10 bl_10 br_10 data_11 bl_11 br_11 data_12 bl_12 br_12 data_13 bl_13 br_13 data_14 bl_14 br_14 data_15 bl_15 br_15 data_16 bl_16 br_16 data_17 bl_17 br_17 data_18 bl_18 br_18 data_19 bl_19 br_19 data_20 bl_20 br_20 data_21 bl_21 br_21 data_22 bl_22 br_22 data_23 bl_23 br_23 data_24 bl_24 br_24 data_25 bl_25 br_25 data_26 bl_26 br_26 data_27 bl_27 br_27 data_28 bl_28 br_28 data_29 bl_29 br_29 data_30 bl_30 br_30 data_31 bl_31 br_31 en vdd gnd -*.PININFO data_0:O bl_0:I br_0:I data_1:O bl_1:I br_1:I data_2:O bl_2:I br_2:I data_3:O bl_3:I br_3:I data_4:O bl_4:I br_4:I data_5:O bl_5:I br_5:I data_6:O bl_6:I br_6:I data_7:O bl_7:I br_7:I data_8:O bl_8:I br_8:I data_9:O bl_9:I br_9:I data_10:O bl_10:I br_10:I data_11:O bl_11:I br_11:I data_12:O bl_12:I br_12:I data_13:O bl_13:I br_13:I data_14:O bl_14:I br_14:I data_15:O bl_15:I br_15:I data_16:O bl_16:I br_16:I data_17:O bl_17:I br_17:I data_18:O bl_18:I br_18:I data_19:O bl_19:I br_19:I data_20:O bl_20:I br_20:I data_21:O bl_21:I br_21:I data_22:O bl_22:I br_22:I data_23:O bl_23:I br_23:I data_24:O bl_24:I br_24:I data_25:O bl_25:I br_25:I data_26:O bl_26:I br_26:I data_27:O bl_27:I br_27:I data_28:O bl_28:I br_28:I data_29:O bl_29:I br_29:I data_30:O bl_30:I br_30:I data_31:O bl_31:I br_31:I en:I vdd:B gnd:B -* OUTPUT: data_0 -* INPUT : bl_0 -* INPUT : br_0 -* OUTPUT: data_1 -* INPUT : bl_1 -* INPUT : br_1 -* OUTPUT: data_2 -* INPUT : bl_2 -* INPUT : br_2 -* OUTPUT: data_3 -* INPUT : bl_3 -* INPUT : br_3 -* OUTPUT: data_4 -* INPUT : bl_4 -* INPUT : br_4 -* OUTPUT: data_5 -* INPUT : bl_5 -* INPUT : br_5 -* OUTPUT: data_6 -* INPUT : bl_6 -* INPUT : br_6 -* OUTPUT: data_7 -* INPUT : bl_7 -* INPUT : br_7 -* OUTPUT: data_8 -* INPUT : bl_8 -* INPUT : br_8 -* OUTPUT: data_9 -* INPUT : bl_9 -* INPUT : br_9 -* OUTPUT: data_10 -* INPUT : bl_10 -* INPUT : br_10 -* OUTPUT: data_11 -* INPUT : bl_11 -* INPUT : br_11 -* OUTPUT: data_12 -* INPUT : bl_12 -* INPUT : br_12 -* OUTPUT: data_13 -* INPUT : bl_13 -* INPUT : br_13 -* OUTPUT: data_14 -* INPUT : bl_14 -* INPUT : br_14 -* OUTPUT: data_15 -* INPUT : bl_15 -* INPUT : br_15 -* OUTPUT: data_16 -* INPUT : bl_16 -* INPUT : br_16 -* OUTPUT: data_17 -* INPUT : bl_17 -* INPUT : br_17 -* OUTPUT: data_18 -* INPUT : bl_18 -* INPUT : br_18 -* OUTPUT: data_19 -* INPUT : bl_19 -* INPUT : br_19 -* OUTPUT: data_20 -* INPUT : bl_20 -* INPUT : br_20 -* OUTPUT: data_21 -* INPUT : bl_21 -* INPUT : br_21 -* OUTPUT: data_22 -* INPUT : bl_22 -* INPUT : br_22 -* OUTPUT: data_23 -* INPUT : bl_23 -* INPUT : br_23 -* OUTPUT: data_24 -* INPUT : bl_24 -* INPUT : br_24 -* OUTPUT: data_25 -* INPUT : bl_25 -* INPUT : br_25 -* OUTPUT: data_26 -* INPUT : bl_26 -* INPUT : br_26 -* OUTPUT: data_27 -* INPUT : bl_27 -* INPUT : br_27 -* OUTPUT: data_28 -* INPUT : bl_28 -* INPUT : br_28 -* OUTPUT: data_29 -* INPUT : bl_29 -* INPUT : br_29 -* OUTPUT: data_30 -* INPUT : bl_30 -* INPUT : br_30 -* OUTPUT: data_31 -* INPUT : bl_31 -* INPUT : br_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* words_per_row: 1 -Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp -Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp -Xsa_d2 bl_2 br_2 data_2 en vdd gnd sense_amp -Xsa_d3 bl_3 br_3 data_3 en vdd gnd sense_amp -Xsa_d4 bl_4 br_4 data_4 en vdd gnd sense_amp -Xsa_d5 bl_5 br_5 data_5 en vdd gnd sense_amp -Xsa_d6 bl_6 br_6 data_6 en vdd gnd sense_amp -Xsa_d7 bl_7 br_7 data_7 en vdd gnd sense_amp -Xsa_d8 bl_8 br_8 data_8 en vdd gnd sense_amp -Xsa_d9 bl_9 br_9 data_9 en vdd gnd sense_amp -Xsa_d10 bl_10 br_10 data_10 en vdd gnd sense_amp -Xsa_d11 bl_11 br_11 data_11 en vdd gnd sense_amp -Xsa_d12 bl_12 br_12 data_12 en vdd gnd sense_amp -Xsa_d13 bl_13 br_13 data_13 en vdd gnd sense_amp -Xsa_d14 bl_14 br_14 data_14 en vdd gnd sense_amp -Xsa_d15 bl_15 br_15 data_15 en vdd gnd sense_amp -Xsa_d16 bl_16 br_16 data_16 en vdd gnd sense_amp -Xsa_d17 bl_17 br_17 data_17 en vdd gnd sense_amp -Xsa_d18 bl_18 br_18 data_18 en vdd gnd sense_amp -Xsa_d19 bl_19 br_19 data_19 en vdd gnd sense_amp -Xsa_d20 bl_20 br_20 data_20 en vdd gnd sense_amp -Xsa_d21 bl_21 br_21 data_21 en vdd gnd sense_amp -Xsa_d22 bl_22 br_22 data_22 en vdd gnd sense_amp -Xsa_d23 bl_23 br_23 data_23 en vdd gnd sense_amp -Xsa_d24 bl_24 br_24 data_24 en vdd gnd sense_amp -Xsa_d25 bl_25 br_25 data_25 en vdd gnd sense_amp -Xsa_d26 bl_26 br_26 data_26 en vdd gnd sense_amp -Xsa_d27 bl_27 br_27 data_27 en vdd gnd sense_amp -Xsa_d28 bl_28 br_28 data_28 en vdd gnd sense_amp -Xsa_d29 bl_29 br_29 data_29 en vdd gnd sense_amp -Xsa_d30 bl_30 br_30 data_30 en vdd gnd sense_amp -Xsa_d31 bl_31 br_31 data_31 en vdd gnd sense_amp -.ENDS sense_amp_array - -.SUBCKT port_data rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 s_en p_en_bar w_en vdd gnd -*.PININFO rbl_bl:B rbl_br:B bl_0:B br_0:B bl_1:B br_1:B bl_2:B br_2:B bl_3:B br_3:B bl_4:B br_4:B bl_5:B br_5:B bl_6:B br_6:B bl_7:B br_7:B bl_8:B br_8:B bl_9:B br_9:B bl_10:B br_10:B bl_11:B br_11:B bl_12:B br_12:B bl_13:B br_13:B bl_14:B br_14:B bl_15:B br_15:B bl_16:B br_16:B bl_17:B br_17:B bl_18:B br_18:B bl_19:B br_19:B bl_20:B br_20:B bl_21:B br_21:B bl_22:B br_22:B bl_23:B br_23:B bl_24:B br_24:B bl_25:B br_25:B bl_26:B br_26:B bl_27:B br_27:B bl_28:B br_28:B bl_29:B br_29:B bl_30:B br_30:B bl_31:B br_31:B dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I s_en:I p_en_bar:I w_en:I vdd:B gnd:B -* INOUT : rbl_bl -* INOUT : rbl_br -* INOUT : bl_0 -* INOUT : br_0 -* INOUT : bl_1 -* INOUT : br_1 -* INOUT : bl_2 -* INOUT : br_2 -* INOUT : bl_3 -* INOUT : br_3 -* INOUT : bl_4 -* INOUT : br_4 -* INOUT : bl_5 -* INOUT : br_5 -* INOUT : bl_6 -* INOUT : br_6 -* INOUT : bl_7 -* INOUT : br_7 -* INOUT : bl_8 -* INOUT : br_8 -* INOUT : bl_9 -* INOUT : br_9 -* INOUT : bl_10 -* INOUT : br_10 -* INOUT : bl_11 -* INOUT : br_11 -* INOUT : bl_12 -* INOUT : br_12 -* INOUT : bl_13 -* INOUT : br_13 -* INOUT : bl_14 -* INOUT : br_14 -* INOUT : bl_15 -* INOUT : br_15 -* INOUT : bl_16 -* INOUT : br_16 -* INOUT : bl_17 -* INOUT : br_17 -* INOUT : bl_18 -* INOUT : br_18 -* INOUT : bl_19 -* INOUT : br_19 -* INOUT : bl_20 -* INOUT : br_20 -* INOUT : bl_21 -* INOUT : br_21 -* INOUT : bl_22 -* INOUT : br_22 -* INOUT : bl_23 -* INOUT : br_23 -* INOUT : bl_24 -* INOUT : br_24 -* INOUT : bl_25 -* INOUT : br_25 -* INOUT : bl_26 -* INOUT : br_26 -* INOUT : bl_27 -* INOUT : br_27 -* INOUT : bl_28 -* INOUT : br_28 -* INOUT : bl_29 -* INOUT : br_29 -* INOUT : bl_30 -* INOUT : br_30 -* INOUT : bl_31 -* INOUT : br_31 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* INPUT : s_en -* INPUT : p_en_bar -* INPUT : w_en -* POWER : vdd -* GROUND: gnd -Xprecharge_array0 rbl_bl rbl_br bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 p_en_bar vdd precharge_array -Xsense_amp_array0 dout_0 bl_0 br_0 dout_1 bl_1 br_1 dout_2 bl_2 br_2 dout_3 bl_3 br_3 dout_4 bl_4 br_4 dout_5 bl_5 br_5 dout_6 bl_6 br_6 dout_7 bl_7 br_7 dout_8 bl_8 br_8 dout_9 bl_9 br_9 dout_10 bl_10 br_10 dout_11 bl_11 br_11 dout_12 bl_12 br_12 dout_13 bl_13 br_13 dout_14 bl_14 br_14 dout_15 bl_15 br_15 dout_16 bl_16 br_16 dout_17 bl_17 br_17 dout_18 bl_18 br_18 dout_19 bl_19 br_19 dout_20 bl_20 br_20 dout_21 bl_21 br_21 dout_22 bl_22 br_22 dout_23 bl_23 br_23 dout_24 bl_24 br_24 dout_25 bl_25 br_25 dout_26 bl_26 br_26 dout_27 bl_27 br_27 dout_28 bl_28 br_28 dout_29 bl_29 br_29 dout_30 bl_30 br_30 dout_31 bl_31 br_31 s_en vdd gnd sense_amp_array -Xwrite_driver_array0 din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 bl_0 br_0 bl_1 br_1 bl_2 br_2 bl_3 br_3 bl_4 br_4 bl_5 br_5 bl_6 br_6 bl_7 br_7 bl_8 br_8 bl_9 br_9 bl_10 br_10 bl_11 br_11 bl_12 br_12 bl_13 br_13 bl_14 br_14 bl_15 br_15 bl_16 br_16 bl_17 br_17 bl_18 br_18 bl_19 br_19 bl_20 br_20 bl_21 br_21 bl_22 br_22 bl_23 br_23 bl_24 br_24 bl_25 br_25 bl_26 br_26 bl_27 br_27 bl_28 br_28 bl_29 br_29 bl_30 br_30 bl_31 br_31 w_en vdd gnd write_driver_array -.ENDS port_data - -* spice ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p - -.SUBCKT pinv_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p -Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -.ENDS pinv_0 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2 - -.SUBCKT wordline_driver A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xwld_nand A B zb_int vdd gnd pnand2 -Xwl_driver zb_int Z vdd gnd pinv_0 -.ENDS wordline_driver - -.SUBCKT wordline_driver_array in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 in_16 in_17 in_18 in_19 in_20 in_21 in_22 in_23 in_24 in_25 in_26 in_27 in_28 in_29 in_30 in_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 en vdd gnd -*.PININFO in_0:I in_1:I in_2:I in_3:I in_4:I in_5:I in_6:I in_7:I in_8:I in_9:I in_10:I in_11:I in_12:I in_13:I in_14:I in_15:I in_16:I in_17:I in_18:I in_19:I in_20:I in_21:I in_22:I in_23:I in_24:I in_25:I in_26:I in_27:I in_28:I in_29:I in_30:I in_31:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O en:I vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* INPUT : in_3 -* INPUT : in_4 -* INPUT : in_5 -* INPUT : in_6 -* INPUT : in_7 -* INPUT : in_8 -* INPUT : in_9 -* INPUT : in_10 -* INPUT : in_11 -* INPUT : in_12 -* INPUT : in_13 -* INPUT : in_14 -* INPUT : in_15 -* INPUT : in_16 -* INPUT : in_17 -* INPUT : in_18 -* INPUT : in_19 -* INPUT : in_20 -* INPUT : in_21 -* INPUT : in_22 -* INPUT : in_23 -* INPUT : in_24 -* INPUT : in_25 -* INPUT : in_26 -* INPUT : in_27 -* INPUT : in_28 -* INPUT : in_29 -* INPUT : in_30 -* INPUT : in_31 -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* INPUT : en -* POWER : vdd -* GROUND: gnd -* rows: 32 cols: 32 -Xwl_driver_and0 in_0 en wl_0 vdd gnd wordline_driver -Xwl_driver_and1 in_1 en wl_1 vdd gnd wordline_driver -Xwl_driver_and2 in_2 en wl_2 vdd gnd wordline_driver -Xwl_driver_and3 in_3 en wl_3 vdd gnd wordline_driver -Xwl_driver_and4 in_4 en wl_4 vdd gnd wordline_driver -Xwl_driver_and5 in_5 en wl_5 vdd gnd wordline_driver -Xwl_driver_and6 in_6 en wl_6 vdd gnd wordline_driver -Xwl_driver_and7 in_7 en wl_7 vdd gnd wordline_driver -Xwl_driver_and8 in_8 en wl_8 vdd gnd wordline_driver -Xwl_driver_and9 in_9 en wl_9 vdd gnd wordline_driver -Xwl_driver_and10 in_10 en wl_10 vdd gnd wordline_driver -Xwl_driver_and11 in_11 en wl_11 vdd gnd wordline_driver -Xwl_driver_and12 in_12 en wl_12 vdd gnd wordline_driver -Xwl_driver_and13 in_13 en wl_13 vdd gnd wordline_driver -Xwl_driver_and14 in_14 en wl_14 vdd gnd wordline_driver -Xwl_driver_and15 in_15 en wl_15 vdd gnd wordline_driver -Xwl_driver_and16 in_16 en wl_16 vdd gnd wordline_driver -Xwl_driver_and17 in_17 en wl_17 vdd gnd wordline_driver -Xwl_driver_and18 in_18 en wl_18 vdd gnd wordline_driver -Xwl_driver_and19 in_19 en wl_19 vdd gnd wordline_driver -Xwl_driver_and20 in_20 en wl_20 vdd gnd wordline_driver -Xwl_driver_and21 in_21 en wl_21 vdd gnd wordline_driver -Xwl_driver_and22 in_22 en wl_22 vdd gnd wordline_driver -Xwl_driver_and23 in_23 en wl_23 vdd gnd wordline_driver -Xwl_driver_and24 in_24 en wl_24 vdd gnd wordline_driver -Xwl_driver_and25 in_25 en wl_25 vdd gnd wordline_driver -Xwl_driver_and26 in_26 en wl_26 vdd gnd wordline_driver -Xwl_driver_and27 in_27 en wl_27 vdd gnd wordline_driver -Xwl_driver_and28 in_28 en wl_28 vdd gnd wordline_driver -Xwl_driver_and29 in_29 en wl_29 vdd gnd wordline_driver -Xwl_driver_and30 in_30 en wl_30 vdd gnd wordline_driver -Xwl_driver_and31 in_31 en wl_31 vdd gnd wordline_driver -.ENDS wordline_driver_array - -* spice ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p - -.SUBCKT pinv A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv - -.SUBCKT and2_dec A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv -.ENDS and2_dec - -.SUBCKT hierarchical_predecode2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd -*.PININFO in_0:I in_1:I out_0:O out_1:O out_2:O out_3:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -XXpre2x4_and_0 inbar_0 inbar_1 out_0 vdd gnd and2_dec -XXpre2x4_and_1 in_0 inbar_1 out_1 vdd gnd and2_dec -XXpre2x4_and_2 inbar_0 in_1 out_2 vdd gnd and2_dec -XXpre2x4_and_3 in_0 in_1 out_3 vdd gnd and2_dec -.ENDS hierarchical_predecode2x4 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -.SUBCKT pnand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3 - -.SUBCKT and3_dec A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 1 -Xpand3_dec_nand A B C zb_int vdd gnd pnand3 -Xpand3_dec_inv zb_int Z vdd gnd pinv -.ENDS and3_dec - -.SUBCKT hierarchical_predecode3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd -*.PININFO in_0:I in_1:I in_2:I out_0:O out_1:O out_2:O out_3:O out_4:O out_5:O out_6:O out_7:O vdd:B gnd:B -* INPUT : in_0 -* INPUT : in_1 -* INPUT : in_2 -* OUTPUT: out_0 -* OUTPUT: out_1 -* OUTPUT: out_2 -* OUTPUT: out_3 -* OUTPUT: out_4 -* OUTPUT: out_5 -* OUTPUT: out_6 -* OUTPUT: out_7 -* POWER : vdd -* GROUND: gnd -Xpre_inv_0 in_0 inbar_0 vdd gnd pinv -Xpre_inv_1 in_1 inbar_1 vdd gnd pinv -Xpre_inv_2 in_2 inbar_2 vdd gnd pinv -XXpre3x8_and_0 inbar_0 inbar_1 inbar_2 out_0 vdd gnd and3_dec -XXpre3x8_and_1 in_0 inbar_1 inbar_2 out_1 vdd gnd and3_dec -XXpre3x8_and_2 inbar_0 in_1 inbar_2 out_2 vdd gnd and3_dec -XXpre3x8_and_3 in_0 in_1 inbar_2 out_3 vdd gnd and3_dec -XXpre3x8_and_4 inbar_0 inbar_1 in_2 out_4 vdd gnd and3_dec -XXpre3x8_and_5 in_0 inbar_1 in_2 out_5 vdd gnd and3_dec -XXpre3x8_and_6 inbar_0 in_1 in_2 out_6 vdd gnd and3_dec -XXpre3x8_and_7 in_0 in_1 in_2 out_7 vdd gnd and3_dec -.ENDS hierarchical_predecode3x8 - -.SUBCKT hierarchical_decoder addr_0 addr_1 addr_2 addr_3 addr_4 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 decode_16 decode_17 decode_18 decode_19 decode_20 decode_21 decode_22 decode_23 decode_24 decode_25 decode_26 decode_27 decode_28 decode_29 decode_30 decode_31 vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I decode_0:O decode_1:O decode_2:O decode_3:O decode_4:O decode_5:O decode_6:O decode_7:O decode_8:O decode_9:O decode_10:O decode_11:O decode_12:O decode_13:O decode_14:O decode_15:O decode_16:O decode_17:O decode_18:O decode_19:O decode_20:O decode_21:O decode_22:O decode_23:O decode_24:O decode_25:O decode_26:O decode_27:O decode_28:O decode_29:O decode_30:O decode_31:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* OUTPUT: decode_0 -* OUTPUT: decode_1 -* OUTPUT: decode_2 -* OUTPUT: decode_3 -* OUTPUT: decode_4 -* OUTPUT: decode_5 -* OUTPUT: decode_6 -* OUTPUT: decode_7 -* OUTPUT: decode_8 -* OUTPUT: decode_9 -* OUTPUT: decode_10 -* OUTPUT: decode_11 -* OUTPUT: decode_12 -* OUTPUT: decode_13 -* OUTPUT: decode_14 -* OUTPUT: decode_15 -* OUTPUT: decode_16 -* OUTPUT: decode_17 -* OUTPUT: decode_18 -* OUTPUT: decode_19 -* OUTPUT: decode_20 -* OUTPUT: decode_21 -* OUTPUT: decode_22 -* OUTPUT: decode_23 -* OUTPUT: decode_24 -* OUTPUT: decode_25 -* OUTPUT: decode_26 -* OUTPUT: decode_27 -* OUTPUT: decode_28 -* OUTPUT: decode_29 -* OUTPUT: decode_30 -* OUTPUT: decode_31 -* POWER : vdd -* GROUND: gnd -Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd hierarchical_predecode2x4 -Xpre3x8_0 addr_2 addr_3 addr_4 out_4 out_5 out_6 out_7 out_8 out_9 out_10 out_11 vdd gnd hierarchical_predecode3x8 -XDEC_AND_0 out_0 out_4 decode_0 vdd gnd and2_dec -XDEC_AND_4 out_0 out_5 decode_4 vdd gnd and2_dec -XDEC_AND_8 out_0 out_6 decode_8 vdd gnd and2_dec -XDEC_AND_12 out_0 out_7 decode_12 vdd gnd and2_dec -XDEC_AND_16 out_0 out_8 decode_16 vdd gnd and2_dec -XDEC_AND_20 out_0 out_9 decode_20 vdd gnd and2_dec -XDEC_AND_24 out_0 out_10 decode_24 vdd gnd and2_dec -XDEC_AND_28 out_0 out_11 decode_28 vdd gnd and2_dec -XDEC_AND_1 out_1 out_4 decode_1 vdd gnd and2_dec -XDEC_AND_5 out_1 out_5 decode_5 vdd gnd and2_dec -XDEC_AND_9 out_1 out_6 decode_9 vdd gnd and2_dec -XDEC_AND_13 out_1 out_7 decode_13 vdd gnd and2_dec -XDEC_AND_17 out_1 out_8 decode_17 vdd gnd and2_dec -XDEC_AND_21 out_1 out_9 decode_21 vdd gnd and2_dec -XDEC_AND_25 out_1 out_10 decode_25 vdd gnd and2_dec -XDEC_AND_29 out_1 out_11 decode_29 vdd gnd and2_dec -XDEC_AND_2 out_2 out_4 decode_2 vdd gnd and2_dec -XDEC_AND_6 out_2 out_5 decode_6 vdd gnd and2_dec -XDEC_AND_10 out_2 out_6 decode_10 vdd gnd and2_dec -XDEC_AND_14 out_2 out_7 decode_14 vdd gnd and2_dec -XDEC_AND_18 out_2 out_8 decode_18 vdd gnd and2_dec -XDEC_AND_22 out_2 out_9 decode_22 vdd gnd and2_dec -XDEC_AND_26 out_2 out_10 decode_26 vdd gnd and2_dec -XDEC_AND_30 out_2 out_11 decode_30 vdd gnd and2_dec -XDEC_AND_3 out_3 out_4 decode_3 vdd gnd and2_dec -XDEC_AND_7 out_3 out_5 decode_7 vdd gnd and2_dec -XDEC_AND_11 out_3 out_6 decode_11 vdd gnd and2_dec -XDEC_AND_15 out_3 out_7 decode_15 vdd gnd and2_dec -XDEC_AND_19 out_3 out_8 decode_19 vdd gnd and2_dec -XDEC_AND_23 out_3 out_9 decode_23 vdd gnd and2_dec -XDEC_AND_27 out_3 out_10 decode_27 vdd gnd and2_dec -XDEC_AND_31 out_3 out_11 decode_31 vdd gnd and2_dec -.ENDS hierarchical_decoder - -.SUBCKT and2_dec_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* size: 8 -Xpand2_dec_nand A B zb_int vdd gnd pnand2 -Xpand2_dec_inv zb_int Z vdd gnd pinv_0 -.ENDS and2_dec_0 - -.SUBCKT port_address addr_0 addr_1 addr_2 addr_3 addr_4 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 rbl_wl vdd gnd -*.PININFO addr_0:I addr_1:I addr_2:I addr_3:I addr_4:I wl_en:I wl_0:O wl_1:O wl_2:O wl_3:O wl_4:O wl_5:O wl_6:O wl_7:O wl_8:O wl_9:O wl_10:O wl_11:O wl_12:O wl_13:O wl_14:O wl_15:O wl_16:O wl_17:O wl_18:O wl_19:O wl_20:O wl_21:O wl_22:O wl_23:O wl_24:O wl_25:O wl_26:O wl_27:O wl_28:O wl_29:O wl_30:O wl_31:O rbl_wl:O vdd:B gnd:B -* INPUT : addr_0 -* INPUT : addr_1 -* INPUT : addr_2 -* INPUT : addr_3 -* INPUT : addr_4 -* INPUT : wl_en -* OUTPUT: wl_0 -* OUTPUT: wl_1 -* OUTPUT: wl_2 -* OUTPUT: wl_3 -* OUTPUT: wl_4 -* OUTPUT: wl_5 -* OUTPUT: wl_6 -* OUTPUT: wl_7 -* OUTPUT: wl_8 -* OUTPUT: wl_9 -* OUTPUT: wl_10 -* OUTPUT: wl_11 -* OUTPUT: wl_12 -* OUTPUT: wl_13 -* OUTPUT: wl_14 -* OUTPUT: wl_15 -* OUTPUT: wl_16 -* OUTPUT: wl_17 -* OUTPUT: wl_18 -* OUTPUT: wl_19 -* OUTPUT: wl_20 -* OUTPUT: wl_21 -* OUTPUT: wl_22 -* OUTPUT: wl_23 -* OUTPUT: wl_24 -* OUTPUT: wl_25 -* OUTPUT: wl_26 -* OUTPUT: wl_27 -* OUTPUT: wl_28 -* OUTPUT: wl_29 -* OUTPUT: wl_30 -* OUTPUT: wl_31 -* OUTPUT: rbl_wl -* POWER : vdd -* GROUND: gnd -Xrow_decoder addr_0 addr_1 addr_2 addr_3 addr_4 dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 vdd gnd hierarchical_decoder -Xwordline_driver dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 dec_out_16 dec_out_17 dec_out_18 dec_out_19 dec_out_20 dec_out_21 dec_out_22 dec_out_23 dec_out_24 dec_out_25 dec_out_26 dec_out_27 dec_out_28 dec_out_29 dec_out_30 dec_out_31 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_16 wl_17 wl_18 wl_19 wl_20 wl_21 wl_22 wl_23 wl_24 wl_25 wl_26 wl_27 wl_28 wl_29 wl_30 wl_31 wl_en vdd gnd wordline_driver_array -Xrbl_driver wl_en vdd rbl_wl vdd gnd and2_dec_0 -.ENDS port_address - -.SUBCKT bank dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 rbl_bl_0_0 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd -*.PININFO dout0_0:O dout0_1:O dout0_2:O dout0_3:O dout0_4:O dout0_5:O dout0_6:O dout0_7:O dout0_8:O dout0_9:O dout0_10:O dout0_11:O dout0_12:O dout0_13:O dout0_14:O dout0_15:O dout0_16:O dout0_17:O dout0_18:O dout0_19:O dout0_20:O dout0_21:O dout0_22:O dout0_23:O dout0_24:O dout0_25:O dout0_26:O dout0_27:O dout0_28:O dout0_29:O dout0_30:O dout0_31:O rbl_bl_0_0:O din0_0:I din0_1:I din0_2:I din0_3:I din0_4:I din0_5:I din0_6:I din0_7:I din0_8:I din0_9:I din0_10:I din0_11:I din0_12:I din0_13:I din0_14:I din0_15:I din0_16:I din0_17:I din0_18:I din0_19:I din0_20:I din0_21:I din0_22:I din0_23:I din0_24:I din0_25:I din0_26:I din0_27:I din0_28:I din0_29:I din0_30:I din0_31:I addr0_0:I addr0_1:I addr0_2:I addr0_3:I addr0_4:I s_en0:I p_en_bar0:I w_en0:I wl_en0:I vdd:B gnd:B -* OUTPUT: dout0_0 -* OUTPUT: dout0_1 -* OUTPUT: dout0_2 -* OUTPUT: dout0_3 -* OUTPUT: dout0_4 -* OUTPUT: dout0_5 -* OUTPUT: dout0_6 -* OUTPUT: dout0_7 -* OUTPUT: dout0_8 -* OUTPUT: dout0_9 -* OUTPUT: dout0_10 -* OUTPUT: dout0_11 -* OUTPUT: dout0_12 -* OUTPUT: dout0_13 -* OUTPUT: dout0_14 -* OUTPUT: dout0_15 -* OUTPUT: dout0_16 -* OUTPUT: dout0_17 -* OUTPUT: dout0_18 -* OUTPUT: dout0_19 -* OUTPUT: dout0_20 -* OUTPUT: dout0_21 -* OUTPUT: dout0_22 -* OUTPUT: dout0_23 -* OUTPUT: dout0_24 -* OUTPUT: dout0_25 -* OUTPUT: dout0_26 -* OUTPUT: dout0_27 -* OUTPUT: dout0_28 -* OUTPUT: dout0_29 -* OUTPUT: dout0_30 -* OUTPUT: dout0_31 -* OUTPUT: rbl_bl_0_0 -* INPUT : din0_0 -* INPUT : din0_1 -* INPUT : din0_2 -* INPUT : din0_3 -* INPUT : din0_4 -* INPUT : din0_5 -* INPUT : din0_6 -* INPUT : din0_7 -* INPUT : din0_8 -* INPUT : din0_9 -* INPUT : din0_10 -* INPUT : din0_11 -* INPUT : din0_12 -* INPUT : din0_13 -* INPUT : din0_14 -* INPUT : din0_15 -* INPUT : din0_16 -* INPUT : din0_17 -* INPUT : din0_18 -* INPUT : din0_19 -* INPUT : din0_20 -* INPUT : din0_21 -* INPUT : din0_22 -* INPUT : din0_23 -* INPUT : din0_24 -* INPUT : din0_25 -* INPUT : din0_26 -* INPUT : din0_27 -* INPUT : din0_28 -* INPUT : din0_29 -* INPUT : din0_30 -* INPUT : din0_31 -* INPUT : addr0_0 -* INPUT : addr0_1 -* INPUT : addr0_2 -* INPUT : addr0_3 -* INPUT : addr0_4 -* INPUT : s_en0 -* INPUT : p_en_bar0 -* INPUT : w_en0 -* INPUT : wl_en0 -* POWER : vdd -* GROUND: gnd -Xbitcell_array rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 rbl_wl0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 vdd gnd replica_bitcell_array -Xport_data0 rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 bl_0_1 br_0_1 bl_0_2 br_0_2 bl_0_3 br_0_3 bl_0_4 br_0_4 bl_0_5 br_0_5 bl_0_6 br_0_6 bl_0_7 br_0_7 bl_0_8 br_0_8 bl_0_9 br_0_9 bl_0_10 br_0_10 bl_0_11 br_0_11 bl_0_12 br_0_12 bl_0_13 br_0_13 bl_0_14 br_0_14 bl_0_15 br_0_15 bl_0_16 br_0_16 bl_0_17 br_0_17 bl_0_18 br_0_18 bl_0_19 br_0_19 bl_0_20 br_0_20 bl_0_21 br_0_21 bl_0_22 br_0_22 bl_0_23 br_0_23 bl_0_24 br_0_24 bl_0_25 br_0_25 bl_0_26 br_0_26 bl_0_27 br_0_27 bl_0_28 br_0_28 bl_0_29 br_0_29 bl_0_30 br_0_30 bl_0_31 br_0_31 dout0_0 dout0_1 dout0_2 dout0_3 dout0_4 dout0_5 dout0_6 dout0_7 dout0_8 dout0_9 dout0_10 dout0_11 dout0_12 dout0_13 dout0_14 dout0_15 dout0_16 dout0_17 dout0_18 dout0_19 dout0_20 dout0_21 dout0_22 dout0_23 dout0_24 dout0_25 dout0_26 dout0_27 dout0_28 dout0_29 dout0_30 dout0_31 din0_0 din0_1 din0_2 din0_3 din0_4 din0_5 din0_6 din0_7 din0_8 din0_9 din0_10 din0_11 din0_12 din0_13 din0_14 din0_15 din0_16 din0_17 din0_18 din0_19 din0_20 din0_21 din0_22 din0_23 din0_24 din0_25 din0_26 din0_27 din0_28 din0_29 din0_30 din0_31 s_en0 p_en_bar0 w_en0 vdd gnd port_data -Xport_address0 addr0_0 addr0_1 addr0_2 addr0_3 addr0_4 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16 wl_0_17 wl_0_18 wl_0_19 wl_0_20 wl_0_21 wl_0_22 wl_0_23 wl_0_24 wl_0_25 wl_0_26 wl_0_27 wl_0_28 wl_0_29 wl_0_30 wl_0_31 rbl_wl0 vdd gnd port_address -.ENDS bank - -.SUBCKT data_dff din_0 din_1 din_2 din_3 din_4 din_5 din_6 din_7 din_8 din_9 din_10 din_11 din_12 din_13 din_14 din_15 din_16 din_17 din_18 din_19 din_20 din_21 din_22 din_23 din_24 din_25 din_26 din_27 din_28 din_29 din_30 din_31 dout_0 dout_1 dout_2 dout_3 dout_4 dout_5 dout_6 dout_7 dout_8 dout_9 dout_10 dout_11 dout_12 dout_13 dout_14 dout_15 dout_16 dout_17 dout_18 dout_19 dout_20 dout_21 dout_22 dout_23 dout_24 dout_25 dout_26 dout_27 dout_28 dout_29 dout_30 dout_31 clk vdd gnd -*.PININFO din_0:I din_1:I din_2:I din_3:I din_4:I din_5:I din_6:I din_7:I din_8:I din_9:I din_10:I din_11:I din_12:I din_13:I din_14:I din_15:I din_16:I din_17:I din_18:I din_19:I din_20:I din_21:I din_22:I din_23:I din_24:I din_25:I din_26:I din_27:I din_28:I din_29:I din_30:I din_31:I dout_0:O dout_1:O dout_2:O dout_3:O dout_4:O dout_5:O dout_6:O dout_7:O dout_8:O dout_9:O dout_10:O dout_11:O dout_12:O dout_13:O dout_14:O dout_15:O dout_16:O dout_17:O dout_18:O dout_19:O dout_20:O dout_21:O dout_22:O dout_23:O dout_24:O dout_25:O dout_26:O dout_27:O dout_28:O dout_29:O dout_30:O dout_31:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* INPUT : din_2 -* INPUT : din_3 -* INPUT : din_4 -* INPUT : din_5 -* INPUT : din_6 -* INPUT : din_7 -* INPUT : din_8 -* INPUT : din_9 -* INPUT : din_10 -* INPUT : din_11 -* INPUT : din_12 -* INPUT : din_13 -* INPUT : din_14 -* INPUT : din_15 -* INPUT : din_16 -* INPUT : din_17 -* INPUT : din_18 -* INPUT : din_19 -* INPUT : din_20 -* INPUT : din_21 -* INPUT : din_22 -* INPUT : din_23 -* INPUT : din_24 -* INPUT : din_25 -* INPUT : din_26 -* INPUT : din_27 -* INPUT : din_28 -* INPUT : din_29 -* INPUT : din_30 -* INPUT : din_31 -* OUTPUT: dout_0 -* OUTPUT: dout_1 -* OUTPUT: dout_2 -* OUTPUT: dout_3 -* OUTPUT: dout_4 -* OUTPUT: dout_5 -* OUTPUT: dout_6 -* OUTPUT: dout_7 -* OUTPUT: dout_8 -* OUTPUT: dout_9 -* OUTPUT: dout_10 -* OUTPUT: dout_11 -* OUTPUT: dout_12 -* OUTPUT: dout_13 -* OUTPUT: dout_14 -* OUTPUT: dout_15 -* OUTPUT: dout_16 -* OUTPUT: dout_17 -* OUTPUT: dout_18 -* OUTPUT: dout_19 -* OUTPUT: dout_20 -* OUTPUT: dout_21 -* OUTPUT: dout_22 -* OUTPUT: dout_23 -* OUTPUT: dout_24 -* OUTPUT: dout_25 -* OUTPUT: dout_26 -* OUTPUT: dout_27 -* OUTPUT: dout_28 -* OUTPUT: dout_29 -* OUTPUT: dout_30 -* OUTPUT: dout_31 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* rows: 1 cols: 32 -Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff -Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff -Xdff_r0_c2 din_2 dout_2 clk vdd gnd dff -Xdff_r0_c3 din_3 dout_3 clk vdd gnd dff -Xdff_r0_c4 din_4 dout_4 clk vdd gnd dff -Xdff_r0_c5 din_5 dout_5 clk vdd gnd dff -Xdff_r0_c6 din_6 dout_6 clk vdd gnd dff -Xdff_r0_c7 din_7 dout_7 clk vdd gnd dff -Xdff_r0_c8 din_8 dout_8 clk vdd gnd dff -Xdff_r0_c9 din_9 dout_9 clk vdd gnd dff -Xdff_r0_c10 din_10 dout_10 clk vdd gnd dff -Xdff_r0_c11 din_11 dout_11 clk vdd gnd dff -Xdff_r0_c12 din_12 dout_12 clk vdd gnd dff -Xdff_r0_c13 din_13 dout_13 clk vdd gnd dff -Xdff_r0_c14 din_14 dout_14 clk vdd gnd dff -Xdff_r0_c15 din_15 dout_15 clk vdd gnd dff -Xdff_r0_c16 din_16 dout_16 clk vdd gnd dff -Xdff_r0_c17 din_17 dout_17 clk vdd gnd dff -Xdff_r0_c18 din_18 dout_18 clk vdd gnd dff -Xdff_r0_c19 din_19 dout_19 clk vdd gnd dff -Xdff_r0_c20 din_20 dout_20 clk vdd gnd dff -Xdff_r0_c21 din_21 dout_21 clk vdd gnd dff -Xdff_r0_c22 din_22 dout_22 clk vdd gnd dff -Xdff_r0_c23 din_23 dout_23 clk vdd gnd dff -Xdff_r0_c24 din_24 dout_24 clk vdd gnd dff -Xdff_r0_c25 din_25 dout_25 clk vdd gnd dff -Xdff_r0_c26 din_26 dout_26 clk vdd gnd dff -Xdff_r0_c27 din_27 dout_27 clk vdd gnd dff -Xdff_r0_c28 din_28 dout_28 clk vdd gnd dff -Xdff_r0_c29 din_29 dout_29 clk vdd gnd dff -Xdff_r0_c30 din_30 dout_30 clk vdd gnd dff -Xdff_r0_c31 din_31 dout_31 clk vdd gnd dff -.ENDS data_dff - -.SUBCKT pnand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand3_0 - -* spice ptx M{0} {1} p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p - -* spice ptx M{0} {1} n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p - -.SUBCKT pinv_13 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=64.0u l=0.4u pd=128.80u ps=128.80u as=64.00p ad=64.00p -Mpinv_nmos Z A gnd gnd n m=1 w=32.0u l=0.4u pd=64.80u ps=64.80u as=32.00p ad=32.00p -.ENDS pinv_13 - -.SUBCKT pdriver_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [40] -Xbuf_inv1 A Z vdd gnd pinv_13 -.ENDS pdriver_2 - -.SUBCKT pand3 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_2 -.ENDS pand3 - -.SUBCKT pnand2_1 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_1 - -* spice ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p - -* spice ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_1 - -* spice ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p - -* spice ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p - -.SUBCKT pinv_2 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_2 - -.SUBCKT dff_buf_0 D Q Qb clk vdd gnd -*.PININFO D:I Q:O Qb:O clk:I vdd:B gnd:B -* INPUT : D -* OUTPUT: Q -* OUTPUT: Qb -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_buf_dff D qint clk vdd gnd dff -Xdff_buf_inv1 qint Qb vdd gnd pinv_1 -Xdff_buf_inv2 Qb Q vdd gnd pinv_2 -.ENDS dff_buf_0 - -.SUBCKT dff_buf_array din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd -*.PININFO din_0:I din_1:I dout_0:O dout_bar_0:O dout_1:O dout_bar_1:O clk:I vdd:B gnd:B -* INPUT : din_0 -* INPUT : din_1 -* OUTPUT: dout_0 -* OUTPUT: dout_bar_0 -* OUTPUT: dout_1 -* OUTPUT: dout_bar_1 -* INPUT : clk -* POWER : vdd -* GROUND: gnd -* inv1: 2 inv2: 4 -Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_0 -Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_0 -.ENDS dff_buf_array - -* spice ptx M{0} {1} p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p - -* spice ptx M{0} {1} n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p - -.SUBCKT pinv_14 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=51.2u l=0.4u pd=103.20u ps=103.20u as=51.20p ad=51.20p -Mpinv_nmos Z A gnd gnd n m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p -.ENDS pinv_14 - -.SUBCKT pdriver_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [32] -Xbuf_inv1 A Z vdd gnd pinv_14 -.ENDS pdriver_3 - -.SUBCKT pand3_0 A B C Z vdd gnd -*.PININFO A:I B:I C:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* INPUT : C -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand3_nand A B C zb_int vdd gnd pnand3_0 -Xpand3_inv zb_int Z vdd gnd pdriver_3 -.ENDS pand3_0 - -.SUBCKT pinv_18 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_18 - -.SUBCKT delay_chain in out vdd gnd -*.PININFO in:I out:O vdd:B gnd:B -* INPUT : in -* OUTPUT: out -* POWER : vdd -* GROUND: gnd -* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4] -Xdinv0 in dout_1 vdd gnd pinv_18 -Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_18 -Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_18 -Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_18 -Xdload_0_3 dout_1 n_0_3 vdd gnd pinv_18 -Xdinv1 dout_1 dout_2 vdd gnd pinv_18 -Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_18 -Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_18 -Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_18 -Xdload_1_3 dout_2 n_1_3 vdd gnd pinv_18 -Xdinv2 dout_2 dout_3 vdd gnd pinv_18 -Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_18 -Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_18 -Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_18 -Xdload_2_3 dout_3 n_2_3 vdd gnd pinv_18 -Xdinv3 dout_3 dout_4 vdd gnd pinv_18 -Xdload_3_0 dout_4 n_3_0 vdd gnd pinv_18 -Xdload_3_1 dout_4 n_3_1 vdd gnd pinv_18 -Xdload_3_2 dout_4 n_3_2 vdd gnd pinv_18 -Xdload_3_3 dout_4 n_3_3 vdd gnd pinv_18 -Xdinv4 dout_4 dout_5 vdd gnd pinv_18 -Xdload_4_0 dout_5 n_4_0 vdd gnd pinv_18 -Xdload_4_1 dout_5 n_4_1 vdd gnd pinv_18 -Xdload_4_2 dout_5 n_4_2 vdd gnd pinv_18 -Xdload_4_3 dout_5 n_4_3 vdd gnd pinv_18 -Xdinv5 dout_5 dout_6 vdd gnd pinv_18 -Xdload_5_0 dout_6 n_5_0 vdd gnd pinv_18 -Xdload_5_1 dout_6 n_5_1 vdd gnd pinv_18 -Xdload_5_2 dout_6 n_5_2 vdd gnd pinv_18 -Xdload_5_3 dout_6 n_5_3 vdd gnd pinv_18 -Xdinv6 dout_6 dout_7 vdd gnd pinv_18 -Xdload_6_0 dout_7 n_6_0 vdd gnd pinv_18 -Xdload_6_1 dout_7 n_6_1 vdd gnd pinv_18 -Xdload_6_2 dout_7 n_6_2 vdd gnd pinv_18 -Xdload_6_3 dout_7 n_6_3 vdd gnd pinv_18 -Xdinv7 dout_7 dout_8 vdd gnd pinv_18 -Xdload_7_0 dout_8 n_7_0 vdd gnd pinv_18 -Xdload_7_1 dout_8 n_7_1 vdd gnd pinv_18 -Xdload_7_2 dout_8 n_7_2 vdd gnd pinv_18 -Xdload_7_3 dout_8 n_7_3 vdd gnd pinv_18 -Xdinv8 dout_8 out vdd gnd pinv_18 -Xdload_8_0 out n_8_0 vdd gnd pinv_18 -Xdload_8_1 out n_8_1 vdd gnd pinv_18 -Xdload_8_2 out n_8_2 vdd gnd pinv_18 -Xdload_8_3 out n_8_3 vdd gnd pinv_18 -.ENDS delay_chain - -* spice ptx M{0} {1} p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p - -* spice ptx M{0} {1} n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p - -.SUBCKT pinv_12 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=16.0u l=0.4u pd=32.80u ps=32.80u as=16.00p ad=16.00p -Mpinv_nmos Z A gnd gnd n m=1 w=8.0u l=0.4u pd=16.80u ps=16.80u as=8.00p ad=8.00p -.ENDS pinv_12 - -* spice ptx M{0} {1} p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p - -* spice ptx M{0} {1} n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p - -.SUBCKT pinv_11 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=4.800000000000001u l=0.4u pd=10.40u ps=10.40u as=4.80p ad=4.80p -Mpinv_nmos Z A gnd gnd n m=1 w=2.4000000000000004u l=0.4u pd=5.60u ps=5.60u as=2.40p ad=2.40p -.ENDS pinv_11 - -.SUBCKT pdriver_1 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [3, 10] -Xbuf_inv1 A Zb1_int vdd gnd pinv_11 -Xbuf_inv2 Zb1_int Z vdd gnd pinv_12 -.ENDS pdriver_1 - -* spice ptx M{0} {1} p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p - -* spice ptx M{0} {1} n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p - -.SUBCKT pinv_10 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=107.2u l=0.4u pd=215.20u ps=215.20u as=107.20p ad=107.20p -Mpinv_nmos Z A gnd gnd n m=1 w=53.6u l=0.4u pd=108.00u ps=108.00u as=53.60p ad=53.60p -.ENDS pinv_10 - -* spice ptx M{0} {1} n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p - -* spice ptx M{0} {1} p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p - -.SUBCKT pinv_8 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=11.200000000000001u l=0.4u pd=23.20u ps=23.20u as=11.20p ad=11.20p -Mpinv_nmos Z A gnd gnd n m=1 w=5.6000000000000005u l=0.4u pd=12.00u ps=12.00u as=5.60p ad=5.60p -.ENDS pinv_8 - -* spice ptx M{0} {1} n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p - -* spice ptx M{0} {1} p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p - -.SUBCKT pinv_9 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=35.2u l=0.4u pd=71.20u ps=71.20u as=35.20p ad=35.20p -Mpinv_nmos Z A gnd gnd n m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p -.ENDS pinv_9 - -.SUBCKT pinv_6 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_6 - -.SUBCKT pinv_7 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pinv_7 - -.SUBCKT pdriver_0 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 2, 7, 22, 67] -Xbuf_inv1 A Zb1_int vdd gnd pinv_6 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_7 -Xbuf_inv4 Zb3_int Zb4_int vdd gnd pinv_8 -Xbuf_inv5 Zb4_int Zb5_int vdd gnd pinv_9 -Xbuf_inv6 Zb5_int Z vdd gnd pinv_10 -.ENDS pdriver_0 - -.SUBCKT pinv_15 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p -.ENDS pinv_15 - -* spice ptx M{0} {1} n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p - -* spice ptx M{0} {1} p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p - -.SUBCKT pinv_3 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=19.200000000000003u l=0.4u pd=39.20u ps=39.20u as=19.20p ad=19.20p -Mpinv_nmos Z A gnd gnd n m=1 w=9.600000000000001u l=0.4u pd=20.00u ps=20.00u as=9.60p ad=9.60p -.ENDS pinv_3 - -.SUBCKT pdriver A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [12] -Xbuf_inv1 A Z vdd gnd pinv_3 -.ENDS pdriver - -.SUBCKT pnand2_0 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p -.ENDS pnand2_0 - -.SUBCKT pand2 A B Z vdd gnd -*.PININFO A:I B:I Z:O vdd:B gnd:B -* INPUT : A -* INPUT : B -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Xpand2_nand A B zb_int vdd gnd pnand2_0 -Xpand2_inv zb_int Z vdd gnd pdriver -.ENDS pand2 - -.SUBCKT pinv_16 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p -Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p -.ENDS pinv_16 - -* spice ptx M{0} {1} n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p - -* spice ptx M{0} {1} p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p - -.SUBCKT pinv_17 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -Mpinv_pmos Z A vdd vdd p m=1 w=17.6u l=0.4u pd=36.00u ps=36.00u as=17.60p ad=17.60p -Mpinv_nmos Z A gnd gnd n m=1 w=8.8u l=0.4u pd=18.40u ps=18.40u as=8.80p ad=8.80p -.ENDS pinv_17 - -.SUBCKT pdriver_4 A Z vdd gnd -*.PININFO A:I Z:O vdd:B gnd:B -* INPUT : A -* OUTPUT: Z -* POWER : vdd -* GROUND: gnd -* sizes: [1, 1, 4, 11] -Xbuf_inv1 A Zb1_int vdd gnd pinv_6 -Xbuf_inv2 Zb1_int Zb2_int vdd gnd pinv_6 -Xbuf_inv3 Zb2_int Zb3_int vdd gnd pinv_16 -Xbuf_inv4 Zb3_int Z vdd gnd pinv_17 -.ENDS pdriver_4 - -.SUBCKT control_logic_rw csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd -*.PININFO csb:I web:I clk:I rbl_bl:I s_en:O w_en:O p_en_bar:O wl_en:O clk_buf:O vdd:B gnd:B -* INPUT : csb -* INPUT : web -* INPUT : clk -* INPUT : rbl_bl -* OUTPUT: s_en -* OUTPUT: w_en -* OUTPUT: p_en_bar -* OUTPUT: wl_en -* OUTPUT: clk_buf -* POWER : vdd -* GROUND: gnd -* word_size 32 -Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array -Xclkbuf clk clk_buf vdd gnd pdriver_0 -Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_15 -Xand2_gated_clk_bar clk_bar cs gated_clk_bar vdd gnd pand2 -Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2 -Xbuf_wl_en gated_clk_bar wl_en vdd gnd pdriver_1 -Xrbl_bl_delay_inv rbl_bl_delay rbl_bl_delay_bar vdd gnd pinv_15 -Xw_en_and we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd pand3 -Xbuf_s_en_and rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd pand3_0 -Xdelay_chain rbl_bl rbl_bl_delay vdd gnd delay_chain -Xnand_p_en_bar gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd pnand2_1 -Xbuf_p_en_bar p_en_bar_unbuf p_en_bar vdd gnd pdriver_4 -.ENDS control_logic_rw - -.SUBCKT sram_32_32_scn4m_subm din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] csb0 web0 clk0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] vdd gnd -*.PININFO din0[0]:I din0[1]:I din0[2]:I din0[3]:I din0[4]:I din0[5]:I din0[6]:I din0[7]:I din0[8]:I din0[9]:I din0[10]:I din0[11]:I din0[12]:I din0[13]:I din0[14]:I din0[15]:I din0[16]:I din0[17]:I din0[18]:I din0[19]:I din0[20]:I din0[21]:I din0[22]:I din0[23]:I din0[24]:I din0[25]:I din0[26]:I din0[27]:I din0[28]:I din0[29]:I din0[30]:I din0[31]:I addr0[0]:I addr0[1]:I addr0[2]:I addr0[3]:I addr0[4]:I csb0:I web0:I clk0:I dout0[0]:O dout0[1]:O dout0[2]:O dout0[3]:O dout0[4]:O dout0[5]:O dout0[6]:O dout0[7]:O dout0[8]:O dout0[9]:O dout0[10]:O dout0[11]:O dout0[12]:O dout0[13]:O dout0[14]:O dout0[15]:O dout0[16]:O dout0[17]:O dout0[18]:O dout0[19]:O dout0[20]:O dout0[21]:O dout0[22]:O dout0[23]:O dout0[24]:O dout0[25]:O dout0[26]:O dout0[27]:O dout0[28]:O dout0[29]:O dout0[30]:O dout0[31]:O vdd:B gnd:B -* INPUT : din0[0] -* INPUT : din0[1] -* INPUT : din0[2] -* INPUT : din0[3] -* INPUT : din0[4] -* INPUT : din0[5] -* INPUT : din0[6] -* INPUT : din0[7] -* INPUT : din0[8] -* INPUT : din0[9] -* INPUT : din0[10] -* INPUT : din0[11] -* INPUT : din0[12] -* INPUT : din0[13] -* INPUT : din0[14] -* INPUT : din0[15] -* INPUT : din0[16] -* INPUT : din0[17] -* INPUT : din0[18] -* INPUT : din0[19] -* INPUT : din0[20] -* INPUT : din0[21] -* INPUT : din0[22] -* INPUT : din0[23] -* INPUT : din0[24] -* INPUT : din0[25] -* INPUT : din0[26] -* INPUT : din0[27] -* INPUT : din0[28] -* INPUT : din0[29] -* INPUT : din0[30] -* INPUT : din0[31] -* INPUT : addr0[0] -* INPUT : addr0[1] -* INPUT : addr0[2] -* INPUT : addr0[3] -* INPUT : addr0[4] -* INPUT : csb0 -* INPUT : web0 -* INPUT : clk0 -* OUTPUT: dout0[0] -* OUTPUT: dout0[1] -* OUTPUT: dout0[2] -* OUTPUT: dout0[3] -* OUTPUT: dout0[4] -* OUTPUT: dout0[5] -* OUTPUT: dout0[6] -* OUTPUT: dout0[7] -* OUTPUT: dout0[8] -* OUTPUT: dout0[9] -* OUTPUT: dout0[10] -* OUTPUT: dout0[11] -* OUTPUT: dout0[12] -* OUTPUT: dout0[13] -* OUTPUT: dout0[14] -* OUTPUT: dout0[15] -* OUTPUT: dout0[16] -* OUTPUT: dout0[17] -* OUTPUT: dout0[18] -* OUTPUT: dout0[19] -* OUTPUT: dout0[20] -* OUTPUT: dout0[21] -* OUTPUT: dout0[22] -* OUTPUT: dout0[23] -* OUTPUT: dout0[24] -* OUTPUT: dout0[25] -* OUTPUT: dout0[26] -* OUTPUT: dout0[27] -* OUTPUT: dout0[28] -* OUTPUT: dout0[29] -* OUTPUT: dout0[30] -* OUTPUT: dout0[31] -* POWER : vdd -* GROUND: gnd -Xbank0 dout0[0] dout0[1] dout0[2] dout0[3] dout0[4] dout0[5] dout0[6] dout0[7] dout0[8] dout0[9] dout0[10] dout0[11] dout0[12] dout0[13] dout0[14] dout0[15] dout0[16] dout0[17] dout0[18] dout0[19] dout0[20] dout0[21] dout0[22] dout0[23] dout0[24] dout0[25] dout0[26] dout0[27] dout0[28] dout0[29] dout0[30] dout0[31] rbl_bl0 bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 a0_0 a0_1 a0_2 a0_3 a0_4 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank -Xcontrol0 csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw -Xrow_address0 addr0[0] addr0[1] addr0[2] addr0[3] addr0[4] a0_0 a0_1 a0_2 a0_3 a0_4 clk_buf0 vdd gnd row_addr_dff -Xdata_dff0 din0[0] din0[1] din0[2] din0[3] din0[4] din0[5] din0[6] din0[7] din0[8] din0[9] din0[10] din0[11] din0[12] din0[13] din0[14] din0[15] din0[16] din0[17] din0[18] din0[19] din0[20] din0[21] din0[22] din0[23] din0[24] din0[25] din0[26] din0[27] din0[28] din0[29] din0[30] din0[31] bank_din0_0 bank_din0_1 bank_din0_2 bank_din0_3 bank_din0_4 bank_din0_5 bank_din0_6 bank_din0_7 bank_din0_8 bank_din0_9 bank_din0_10 bank_din0_11 bank_din0_12 bank_din0_13 bank_din0_14 bank_din0_15 bank_din0_16 bank_din0_17 bank_din0_18 bank_din0_19 bank_din0_20 bank_din0_21 bank_din0_22 bank_din0_23 bank_din0_24 bank_din0_25 bank_din0_26 bank_din0_27 bank_din0_28 bank_din0_29 bank_din0_30 bank_din0_31 clk_buf0 vdd gnd data_dff -.ENDS sram_32_32_scn4m_subm From 7567db6fe9586ebd6ec441a65d8fe187c719e81f Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 13 Jul 2022 17:46:37 -0700 Subject: [PATCH 030/102] add rw port unit test for delay control --- .../tests/16_control_logic_delay_rw_test.py | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 compiler/tests/16_control_logic_delay_rw_test.py diff --git a/compiler/tests/16_control_logic_delay_rw_test.py b/compiler/tests/16_control_logic_delay_rw_test.py new file mode 100644 index 00000000..cb592b5a --- /dev/null +++ b/compiler/tests/16_control_logic_delay_rw_test.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class control_logic_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(1, "Testing sample for control_logic_rw") + a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 74bf3770d9909460fe92f3c568d31cba7633269a Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 13 Jul 2022 17:50:22 -0700 Subject: [PATCH 031/102] move pins to m3, route in pin down to avoid m3 collision --- compiler/modules/multi_delay_chain.py | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 4c06d91e..527400ae 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -202,30 +202,30 @@ class multi_delay_chain(design.design): self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0)) def add_layout_pins(self): - # input is A pin of first inverter - # It gets routed to the left a bit to prevent pin access errors - # due to the output pin when going up to M3 + # It gets routed down a bit to prevent overlapping adjacent + # M3 when connecting to vertical bus a_pin = self.driver_inst_list[0].get_pin("A") - mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy()) + mid_loc = vector(a_pin.cx(), a_pin.cy() - self.m3_pitch) # Not 100% sure correct self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m2", + to_layer="m3", offset=mid_loc) - self.add_path(a_pin.layer, [a_pin.center(), mid_loc]) + self.add_path("m3", [a_pin.center(), mid_loc]) self.add_layout_pin_rect_center(text="in", - layer="m2", + layer="m3", offset=mid_loc) - delay_number = 1 + delay_index = 1 + for pin_number in self.pinout_list: - # output is A pin of last load/fanout inverter + # pin is A pin of right-most load/fanout inverter output_driver_inst = self.driver_inst_list[pin_number - 1] a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A") self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m1", + to_layer="m3", offset=a_pin.center()) - self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)), - layer="m1", + self.add_layout_pin_rect_center(text="delay{}".format(str(delay_index)), + layer="m3", offset=a_pin.center()) - delay_number += 1 + delay_index += 1 From 231dca5b51f8850b505fd37479add67a37f3ce17 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 13 Jul 2022 17:53:08 -0700 Subject: [PATCH 032/102] route w_en A and B inputs via M3, fix delay chain outputs connection to vertical bus --- compiler/modules/control_logic_delay.py | 39 ++++++++++++++++++------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index bbcc86de..03496a0b 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -395,7 +395,10 @@ class control_logic_delay(design.design): delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \ ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) - self.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus) + self.connect_vertical_bus(delay_map, + self.delay_inst, + self.input_bus, + self.m2_stack[::-1]) # glitch{1-3} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration @@ -652,15 +655,7 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.w_en_gate_inst) - def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted, not sure if this implementation works. - if self.port_type == "rw": - input_name = "we" - else: - input_name = "cs" - - wen_map = zip(["A", "B"], [input_name, "glitch2"]) - self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus) # if there are problems, look here - + def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted out_pin = self.glitch3_bar_inv_inst.get_pin("Z") out_pos = out_pin.center() in_pin = self.w_en_gate_inst.get_pin("C") @@ -669,7 +664,29 @@ class control_logic_delay(design.design): self.add_path(out_pin.layer, [out_pos, mid1, in_pos]) self.add_via_stack_center(from_layer=out_pin.layer, to_layer=in_pin.layer, - offset=in_pin.center()) + offset=in_pos) + + if self.port_type == "rw": + input_name = "we" + else: + input_name = "cs" + + # This is the second gate over, so it needs to be on M3 + wen_map = zip(["A", "B"], [input_name, "glitch2"]) + self.connect_vertical_bus(wen_map, + self.w_en_gate_inst, + self.input_bus, + self.m2_stack[::-1]) + # The pins are on M1, so we need more vias as well + a_pin = self.w_en_gate_inst.get_pin("A") + self.add_via_stack_center(from_layer=a_pin.layer, + to_layer="m3", + offset=a_pin.center()) + + b_pin = self.w_en_gate_inst.get_pin("B") + self.add_via_stack_center(from_layer=b_pin.layer, + to_layer="m3", + offset=b_pin.center()) self.connect_output(self.w_en_gate_inst, "Z", "w_en") From 7f52e63aca794b3eeb32188b1c81fe101d95b31c Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sat, 16 Jul 2022 09:56:09 -0700 Subject: [PATCH 033/102] route glitch3 to inverter on wen row --- compiler/modules/control_logic_delay.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 03496a0b..47142e36 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -656,6 +656,9 @@ class control_logic_delay(design.design): self.row_end_inst.append(self.w_en_gate_inst) def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted + glitch3_map = zip(["A"], ["glitch3"]) + self.connect_vertical_bus(glitch3_map, self.glitch3_bar_inv_inst, self.input_bus) + out_pin = self.glitch3_bar_inv_inst.get_pin("Z") out_pos = out_pin.center() in_pin = self.w_en_gate_inst.get_pin("C") From 9182ad7c61405443f2df4779b8518f9bba111d22 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sun, 17 Jul 2022 17:08:11 -0700 Subject: [PATCH 034/102] add m4 spacing for route_rails same as control_logic.py --- compiler/modules/control_logic_delay.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 47142e36..fe0cd35e 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -282,7 +282,8 @@ class control_logic_delay(design.design): def route_rails(self): """ Add the input signal inverted tracks """ height = self.control_logic_center.y - self.m2_pitch - offset = vector(self.ctrl_dff_array.width, 0) + # DFF spacing plus the power routing + offset = vector(self.ctrl_dff_array.width + self.m4_pitch, 0) self.input_bus = self.create_vertical_bus("m2", offset, @@ -353,7 +354,7 @@ class control_logic_delay(design.design): # Max of modules or logic rows self.width = max([inst.rx() for inst in self.row_end_inst]) if (self.port_type == "rw") or (self.port_type == "r"): - # TODO: why not w ports here? + # TODO: why not w ports here? Is this because there is no delay chain in w port? self.width = max(self.delay_inst.rx(), self.width) self.width += self.m2_pitch @@ -680,6 +681,7 @@ class control_logic_delay(design.design): self.w_en_gate_inst, self.input_bus, self.m2_stack[::-1]) + # The pins are on M1, so we need more vias as well a_pin = self.w_en_gate_inst.get_pin("A") self.add_via_stack_center(from_layer=a_pin.layer, From 2611468dd7580b157c241fa6a4fa8ddbba084fa7 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 18 Jul 2022 10:43:54 -0700 Subject: [PATCH 035/102] replace route_supply with route supplies from control_logic.py --- compiler/modules/control_logic_delay.py | 68 +++++++++++++++++++++---- 1 file changed, 57 insertions(+), 11 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index fe0cd35e..a0dd5a5f 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -373,7 +373,7 @@ class control_logic_delay(design.design): self.route_clk_buf() self.route_gated_clk_bar() self.route_gated_clk_buf() - self.route_supply() + self.route_supplies() def create_delay(self): """ Create the delay chain """ @@ -752,28 +752,74 @@ class control_logic_delay(design.design): start=out_pos, end=right_pos) - def route_supply(self): + def route_supplies(self): """ Add vdd and gnd to the instance cells """ - supply_layer = self.dff.get_pin("vdd").layer + pin_layer = self.dff.get_pin("vdd").layer + supply_layer = self.supply_stack[2] + + # FIXME: We should be able to replace this with route_vertical_pins instead + # but we may have to make the logic gates a separate module so that they + # have row pins of the same width max_row_x_loc = max([inst.rx() for inst in self.row_end_inst]) + min_row_x_loc = self.control_x_offset + + vdd_pin_locs = [] + gnd_pin_locs = [] + + last_via = None for inst in self.row_end_inst: pins = inst.get_pins("vdd") for pin in pins: - if pin.layer == supply_layer: + if pin.layer == pin_layer: row_loc = pin.rc() pin_loc = vector(max_row_x_loc, pin.rc().y) - self.add_power_pin("vdd", pin_loc, start_layer=pin.layer) - self.add_path(supply_layer, [row_loc, pin_loc]) + vdd_pin_locs.append(pin_loc) + last_via = self.add_via_stack_center(from_layer=pin_layer, + to_layer=supply_layer, + offset=pin_loc, + min_area=True) + self.add_path(pin_layer, [row_loc, pin_loc]) pins = inst.get_pins("gnd") for pin in pins: - if pin.layer == supply_layer: + if pin.layer == pin_layer: row_loc = pin.rc() - pin_loc = vector(max_row_x_loc, pin.rc().y) - self.add_power_pin("gnd", pin_loc, start_layer=pin.layer) - self.add_path(supply_layer, [row_loc, pin_loc]) + pin_loc = vector(min_row_x_loc, pin.rc().y) + gnd_pin_locs.append(pin_loc) + last_via = self.add_via_stack_center(from_layer=pin_layer, + to_layer=supply_layer, + offset=pin_loc, + min_area=True) + self.add_path(pin_layer, [row_loc, pin_loc]) + + if last_via: + via_height=last_via.mod.second_layer_height + via_width=last_via.mod.second_layer_width + else: + via_height=None + via_width=0 + + min_y = min([x.y for x in vdd_pin_locs]) + max_y = max([x.y for x in vdd_pin_locs]) + bot_pos = vector(max_row_x_loc, min_y - 0.5 * via_height) + top_pos = vector(max_row_x_loc, max_y + 0.5 * via_height) + self.add_layout_pin_segment_center(text="vdd", + layer=supply_layer, + start=bot_pos, + end=top_pos, + width=via_width) + + min_y = min([x.y for x in gnd_pin_locs]) + max_y = max([x.y for x in gnd_pin_locs]) + bot_pos = vector(min_row_x_loc, min_y - 0.5 * via_height) + top_pos = vector(min_row_x_loc, max_y + 0.5 * via_height) + self.add_layout_pin_segment_center(text="gnd", + layer=supply_layer, + start=bot_pos, + end=top_pos, + width=via_width) self.copy_layout_pin(self.delay_inst, "gnd") self.copy_layout_pin(self.delay_inst, "vdd") @@ -827,7 +873,7 @@ class control_logic_delay(design.design): # Connect this at the bottom of the buffer out_pin = inst.get_pin("Z") out_pos = out_pin.center() - mid1 = vector(out_pos.x, out_pos.y - 0.4 * inst.mod.height) + mid1 = vector(out_pos.x, out_pos.y - 0.3 * inst.mod.height) mid2 = vector(self.input_bus[name].cx(), mid1.y) bus_pos = self.input_bus[name].center() self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) From 73021be8eba80d667cadc457e847e5a0e7eecd20 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 18 Jul 2022 10:49:55 -0700 Subject: [PATCH 036/102] copy vertical bus spacing from control_logic.py --- compiler/modules/control_logic_delay.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index a0dd5a5f..cac58c12 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -315,7 +315,8 @@ class control_logic_delay(design.design): self.place_dffs() # All of the control logic is placed to the right of the DFFs and bus - self.control_x_offset = self.ctrl_dff_array.width + self.internal_bus_width + # as well as the power supply stripe + self.control_x_offset = self.ctrl_dff_array.width + self.internal_bus_width + self.m4_pitch row = 0 # Add the logic on the right of the bus From 12c58b0457a74b4ee3e560f67ead74c278363f6b Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 18 Jul 2022 12:32:12 -0700 Subject: [PATCH 037/102] use spice names for delay chain output pins in layout --- compiler/modules/control_logic_delay.py | 5 ++++- compiler/modules/multi_delay_chain.py | 5 +---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index cac58c12..43c8b044 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -394,7 +394,10 @@ class control_logic_delay(design.design): self.delay_inst.place(offset, mirror="MX") def route_delay(self): - delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \ + # this is a bit of a hack because I would prefer to just name these pins delay in the layout + # instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py + out_pins = ["out{}".format(str(pin)) for pin in self.multi_delay_chain.pinout_list] + delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \ ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) self.connect_vertical_bus(delay_map, diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 527400ae..7c861b6a 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -216,8 +216,6 @@ class multi_delay_chain(design.design): layer="m3", offset=mid_loc) - delay_index = 1 - for pin_number in self.pinout_list: # pin is A pin of right-most load/fanout inverter output_driver_inst = self.driver_inst_list[pin_number - 1] @@ -225,7 +223,6 @@ class multi_delay_chain(design.design): self.add_via_stack_center(from_layer=a_pin.layer, to_layer="m3", offset=a_pin.center()) - self.add_layout_pin_rect_center(text="delay{}".format(str(delay_index)), + self.add_layout_pin_rect_center(text="out{}".format(str(pin_number)), layer="m3", offset=a_pin.center()) - delay_index += 1 From 08ac1c176a6aa5569a713dad88d0da58c772bf34 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 19 Jul 2022 14:00:51 -0700 Subject: [PATCH 038/102] connect in pin via m2 instead of m3, passes lvs now --- compiler/modules/multi_delay_chain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 7c861b6a..340afcd6 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -210,7 +210,7 @@ class multi_delay_chain(design.design): self.add_via_stack_center(from_layer=a_pin.layer, to_layer="m3", offset=mid_loc) - self.add_path("m3", [a_pin.center(), mid_loc]) + self.add_path("m2", [a_pin.center(), mid_loc]) self.add_layout_pin_rect_center(text="in", layer="m3", From 5fa0689c024711551abdc9ded0219d71369df40e Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 19 Jul 2022 17:57:19 -0700 Subject: [PATCH 039/102] fix drc error in wlen_row --- compiler/modules/control_logic_delay.py | 2 +- compiler/modules/multi_delay_chain.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 43c8b044..cf9ac8cd 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -573,7 +573,7 @@ class control_logic_delay(design.design): out_pos = out_pin.center() in_pin = self.wl_en_driver_inst.get_pin("A") in_pos = in_pin.center() - mid1 = vector(in_pos.x, out_pos.y) + mid1 = vector(out_pos.x, in_pos.y) self.add_path(out_pin.layer, [out_pos, mid1, in_pos]) self.add_via_stack_center(from_layer=out_pin.layer, to_layer=in_pin.layer, diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 340afcd6..81735448 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -206,7 +206,7 @@ class multi_delay_chain(design.design): # It gets routed down a bit to prevent overlapping adjacent # M3 when connecting to vertical bus a_pin = self.driver_inst_list[0].get_pin("A") - mid_loc = vector(a_pin.cx(), a_pin.cy() - self.m3_pitch) # Not 100% sure correct + mid_loc = vector(a_pin.cx(), a_pin.cy() - self.m3_pitch) self.add_via_stack_center(from_layer=a_pin.layer, to_layer="m3", offset=mid_loc) From 75efc476f7b3478c10251407c4ae367fa92a270d Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Tue, 19 Jul 2022 17:58:33 -0700 Subject: [PATCH 040/102] add remaining tests --- .../16_control_logic_delay_multiport_test.py | 60 +++++++++++++++++++ .../tests/16_control_logic_delay_r_test.py | 36 +++++++++++ .../tests/16_control_logic_delay_w_test.py | 35 +++++++++++ 3 files changed, 131 insertions(+) create mode 100644 compiler/tests/16_control_logic_delay_multiport_test.py create mode 100644 compiler/tests/16_control_logic_delay_r_test.py create mode 100644 compiler/tests/16_control_logic_delay_w_test.py diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py new file mode 100644 index 00000000..448f14d4 --- /dev/null +++ b/compiler/tests/16_control_logic_delay_multiport_test.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +#Copyright (c) 2016-2021 Regents of the University of California and The Board +#of Regents for the Oklahoma Agricultural and Mechanical College +#(acting for and on behalf of Oklahoma State University) +#All rights reserved. +# +""" +Run a regression test on a control_logic_delay +""" + +import unittest +from testutils import header,openram_test +import sys, os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class control_logic_delay_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + import control_logic_delay + import tech + + # check control logic for multi-port + OPTS.bitcell = "pbitcell" + OPTS.replica_bitcell = "replica_pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 1 + OPTS.num_r_ports = 1 + + debug.info(1, "Testing sample for control_logic_delay for multiport, only write control logic") + a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="rw") + self.local_check(a) + + # OPTS.num_rw_ports = 0 + # OPTS.num_w_ports = 1 + debug.info(1, "Testing sample for control_logic_delay for multiport, only write control logic") + a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="w") + self.local_check(a) + + # OPTS.num_w_ports = 0 + # OPTS.num_r_ports = 1 + debug.info(1, "Testing sample for control_logic_delay for multiport, only read control logic") + a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="r") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() diff --git a/compiler/tests/16_control_logic_delay_r_test.py b/compiler/tests/16_control_logic_delay_r_test.py new file mode 100644 index 00000000..ec1e401b --- /dev/null +++ b/compiler/tests/16_control_logic_delay_r_test.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class control_logic_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(1, "Testing sample for control_logic_r") + a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="r") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_delay_w_test.py b/compiler/tests/16_control_logic_delay_w_test.py new file mode 100644 index 00000000..748a3f0d --- /dev/null +++ b/compiler/tests/16_control_logic_delay_w_test.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class control_logic_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(1, "Testing sample for control_logic_w") + a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="w") + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 480862c7656efd1bef1501f8e8271593a0f6aaa7 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Fri, 22 Jul 2022 11:24:54 -0700 Subject: [PATCH 041/102] remove sys.path.append calls from tests --- compiler/tests/16_control_logic_delay_multiport_test.py | 2 +- compiler/tests/16_control_logic_delay_r_test.py | 2 +- compiler/tests/16_control_logic_delay_rw_test.py | 2 +- compiler/tests/16_control_logic_delay_w_test.py | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) mode change 100644 => 100755 compiler/tests/16_control_logic_delay_multiport_test.py mode change 100644 => 100755 compiler/tests/16_control_logic_delay_r_test.py mode change 100644 => 100755 compiler/tests/16_control_logic_delay_rw_test.py mode change 100644 => 100755 compiler/tests/16_control_logic_delay_w_test.py diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py old mode 100644 new mode 100755 index 448f14d4..7ea40309 --- a/compiler/tests/16_control_logic_delay_multiport_test.py +++ b/compiler/tests/16_control_logic_delay_multiport_test.py @@ -13,7 +13,7 @@ Run a regression test on a control_logic_delay import unittest from testutils import header,openram_test import sys, os -sys.path.append(os.path.join(sys.path[0],"..")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/16_control_logic_delay_r_test.py b/compiler/tests/16_control_logic_delay_r_test.py old mode 100644 new mode 100755 index ec1e401b..1a184b39 --- a/compiler/tests/16_control_logic_delay_r_test.py +++ b/compiler/tests/16_control_logic_delay_r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/16_control_logic_delay_rw_test.py b/compiler/tests/16_control_logic_delay_rw_test.py old mode 100644 new mode 100755 index cb592b5a..2c2f6cf7 --- a/compiler/tests/16_control_logic_delay_rw_test.py +++ b/compiler/tests/16_control_logic_delay_rw_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/16_control_logic_delay_w_test.py b/compiler/tests/16_control_logic_delay_w_test.py old mode 100644 new mode 100755 index 748a3f0d..989b190a --- a/compiler/tests/16_control_logic_delay_w_test.py +++ b/compiler/tests/16_control_logic_delay_w_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory From b82213caffdd45188eeb3279f482aa9fa5871118 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Fri, 22 Jul 2022 12:56:47 -0700 Subject: [PATCH 042/102] use packages for imports in modules --- compiler/modules/control_logic_delay.py | 10 +++++----- compiler/modules/multi_delay_chain.py | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index cf9ac8cd..43d6c1ed 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -5,16 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design import debug from sram_factory import factory import math -from vector import vector +from base import vector from globals import OPTS -import logical_effort +from base import logical_effort -class control_logic_delay(design.design): +class control_logic_delay(design): """ Dynamically generated Control logic for the total SRAM circuit. Variant: delay-based @@ -44,7 +44,7 @@ class control_logic_delay(design.design): self.num_words = num_rows * words_per_row self.enable_delay_chain_resizing = False - self.inv_parasitic_delay = logical_effort.logical_effort.pinv + self.inv_parasitic_delay = logical_effort.pinv # Determines how much larger the sen delay should be. Accounts for possible error in model. # FIXME: This should be made a parameter diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 81735448..dcb38110 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from globals import OPTS from sram_factory import factory -class multi_delay_chain(design.design): +class multi_delay_chain(design): """ Generate a delay chain with the given number of stages, fanout, and output pins. Fanout list contains the electrical effort (fanout) of each stage. @@ -34,7 +34,7 @@ class multi_delay_chain(design.design): # number of inverters including any fanout loads. self.fanout_list = fanout_list self.rows = len(self.fanout_list) - + # defaults to signle output at end of delay chain if not pinout_list: self.pinout_list = [self.rows] # TODO: check for off-by-one here From f01e73328dd03a150b008f2a543dbb14785b1bb7 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Fri, 22 Jul 2022 13:03:09 -0700 Subject: [PATCH 043/102] remove superfluous imports from multiport test --- compiler/tests/16_control_logic_delay_multiport_test.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py index 7ea40309..590b2d7c 100755 --- a/compiler/tests/16_control_logic_delay_multiport_test.py +++ b/compiler/tests/16_control_logic_delay_multiport_test.py @@ -24,8 +24,6 @@ class control_logic_delay_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import control_logic_delay - import tech # check control logic for multi-port OPTS.bitcell = "pbitcell" From 7abaf0463ee72612a6e258553390959fa904f2b5 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 9 Mar 2023 10:05:17 -0800 Subject: [PATCH 044/102] create no rbl no dummy tests --- ...plica_bitcell_array_dummies_1rw_1r_test.py | 43 +++++++++++++++++++ ..._replica_bitcell_array_dummies_1rw_test.py | 40 +++++++++++++++++ ...replica_bitcell_array_norbl_1rw_1r_test.py | 2 +- ...ed_replica_bitcell_array_norbl_1rw_test.py | 2 +- ...plica_bitcell_array_dummies_1rw_1r_test.py | 43 +++++++++++++++++++ ..._replica_bitcell_array_dummies_1rw_test.py | 40 +++++++++++++++++ ...replica_bitcell_array_norbl_1rw_1r_test.py | 2 +- ...14_replica_bitcell_array_norbl_1rw_test.py | 2 +- 8 files changed, 170 insertions(+), 4 deletions(-) create mode 100755 compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py create mode 100755 compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py create mode 100755 compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py create mode 100755 compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py new file mode 100755 index 00000000..bc432c6b --- /dev/null +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class capped_replica_bitcell_array_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 non-replica array for dp cell") + a = factory.create(module_type="capped_replica_bitcell_array", + cols=4, + rows=4, + rbl=[1, 1]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py new file mode 100755 index 00000000..175689c3 --- /dev/null +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class capped_replica_bitcell_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Testing 4x4 array for bitcell") + a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py index bc432c6b..e9a61609 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py @@ -29,7 +29,7 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, - rbl=[1, 1]) + rbl=[0, 0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py index 175689c3..e845d32b 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py @@ -26,7 +26,7 @@ class capped_replica_bitcell_array_test(openram_test): factory.reset() debug.info(2, "Testing 4x4 array for bitcell") - a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) + a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py new file mode 100755 index 00000000..ebdc9584 --- /dev/null +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class replica_bitcell_array_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 non-replica array for dp cell") + a = factory.create(module_type="replica_bitcell_array", + cols=4, + rows=4, + rbl=[1, 1]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py new file mode 100755 index 00000000..e893c3ca --- /dev/null +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class replica_bitcell_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Testing 4x4 array for bitcell") + a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py index ebdc9584..78f77ece 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py @@ -29,7 +29,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test): a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, - rbl=[1, 1]) + rbl=[0, 0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py index e893c3ca..df20a19a 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py @@ -26,7 +26,7 @@ class replica_bitcell_array_test(openram_test): factory.reset() debug.info(2, "Testing 4x4 array for bitcell") - a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) + a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) self.local_check(a) openram.end_openram() From 41344a980b7c33b364efc2d2dda120bd2a73836b Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 9 Mar 2023 10:07:02 -0800 Subject: [PATCH 045/102] change array modules to allow rbl=[0, 0] --- .../modules/capped_replica_bitcell_array.py | 31 +++-------- compiler/modules/replica_bitcell_array.py | 52 ++++++++----------- 2 files changed, 28 insertions(+), 55 deletions(-) diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index 65193bab..8e1395d1 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -33,7 +33,10 @@ class capped_replica_bitcell_array(bitcell_base_array): self.column_size = cols self.row_size = rows # This is how many RBLs are in all the arrays - self.rbl = rbl + if rbl is not None: + self.rbl = rbl + else: + self.rbl = [0] * len(self.all_ports) # This specifies which RBL to put on the left or right by port number # This could be an empty list if left_rbl is not None: @@ -64,28 +67,7 @@ class capped_replica_bitcell_array(bitcell_base_array): self.create_instances() def add_modules(self): - """ Array and dummy/replica columns - - d or D = dummy cell (caps to distinguish grouping) - r or R = replica cell (caps to distinguish grouping) - b or B = bitcell - replica columns 1 - v v - bdDDDDDDDDDDDDDDdb <- Dummy row - bdDDDDDDDDDDDDDDrb <- Dummy row - br--------------rb - br| Array |rb - br| row x col |rb - br--------------rb - brDDDDDDDDDDDDDDdb <- Dummy row - bdDDDDDDDDDDDDDDdb <- Dummy row - - ^^^^^^^^^^^^^^^ - dummy rows cols x 1 - - ^ dummy columns ^ - 1 x (rows + 4) - """ + """ Array and cap rows/columns """ self.replica_bitcell_array = factory.create(module_type="replica_bitcell_array", cols=self.column_size, @@ -132,7 +114,7 @@ class capped_replica_bitcell_array(bitcell_base_array): # + right replica column(s) column_offset=1 + len(self.left_rbl) + self.column_size + self.rbl[0], rows=self.row_size + self.extra_rows, - mirror=(self.rbl[0] + 1) %2) + mirror=(self.rbl[0] + 1) % 2) def add_pins(self): @@ -219,6 +201,7 @@ class capped_replica_bitcell_array(bitcell_base_array): # row-based or column based power and ground lines. self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0])) self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2])) + # FIXME: custom sky130 replica module has a better version of this offset self.unused_offset = vector(0.25, 0.25) # This is a bitcell x bitcell offset to scale diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 87a96827..c079e448 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -36,7 +36,10 @@ class replica_bitcell_array(bitcell_base_array): self.column_size = cols self.row_size = rows # This is how many RBLs are in all the arrays - self.rbl = rbl + if rbl is not None: + self.rbl = rbl + else: + self.rbl = [0] * len(self.all_ports) # This specifies which RBL to put on the left or right by port number # This could be an empty list if left_rbl is not None: @@ -47,7 +50,7 @@ class replica_bitcell_array(bitcell_base_array): if right_rbl is not None: self.right_rbl = right_rbl else: - self.right_rbl=[] + self.right_rbl = [] self.rbls = self.left_rbl + self.right_rbl debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl), @@ -64,28 +67,7 @@ class replica_bitcell_array(bitcell_base_array): self.create_instances() def add_modules(self): - """ Array and dummy/replica columns - - d or D = dummy cell (caps to distinguish grouping) - r or R = replica cell (caps to distinguish grouping) - b or B = bitcell - replica columns 1 - v v - bdDDDDDDDDDDDDDDdb <- Dummy row - bdDDDDDDDDDDDDDDrb <- Dummy row - br--------------rb - br| Array |rb - br| row x col |rb - br--------------rb - brDDDDDDDDDDDDDDdb <- Dummy row - bdDDDDDDDDDDDDDDdb <- Dummy row - - ^^^^^^^^^^^^^^^ - dummy rows cols x 1 - - ^ dummy columns ^ - 1 x (rows + 4) - """ + """ Array and dummy/replica columns """ # Bitcell array self.bitcell_array = factory.create(module_type="bitcell_array", column_offset=1 + len(self.left_rbl), @@ -97,6 +79,7 @@ class replica_bitcell_array(bitcell_base_array): for port in self.all_ports: if port in self.left_rbl: + # TODO: merge comments from other commit... to fix these comments... # We will always have self.rbl[0] rows of replica wordlines below # the array. # These go from the top (where the bitcell array starts ) down @@ -123,7 +106,9 @@ class replica_bitcell_array(bitcell_base_array): self.dummy_row = factory.create(module_type="dummy_array", cols=self.column_size, rows=1, - # dummy column + left replica column + # cap column + left replica column + # FIXME: these col offsets should really start at 0 because + # this is the left edge of the array... but changing them all is work column_offset=1 + len(self.left_rbl), mirror=0) @@ -175,6 +160,8 @@ class replica_bitcell_array(bitcell_base_array): self.unused_wordline_names = [] for port in self.all_ports: + if self.rbl[port] == 0: + continue # TODO: there's probably a better way to do this check for bit in self.all_ports: self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit)) if bit != port: @@ -225,9 +212,12 @@ class replica_bitcell_array(bitcell_base_array): self.dummy_row_replica_insts = [] # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! for port in self.all_ports: # TODO: tie to self.rbl or whatever - self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), - mod=self.dummy_row)) - self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + self.supplies) + if self.rbl[port] != 0: + self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), + mod=self.dummy_row)) + self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + self.supplies) + else: + self.dummy_row_replica_insts.append(None) def create_layout(self): @@ -249,8 +239,8 @@ class replica_bitcell_array(bitcell_base_array): # Array was at (0, 0) but move everything so it is at the lower left # We move DOWN the number of left RBL even if we didn't add the column to this bitcell array # Note that this doesn't include the row/col cap - array_offset = self.bitcell_offset.scale(len(self.left_rbl), self.rbl[0]) - self.translate_all(array_offset.scale(-1, -1)) + array_offset = self.bitcell_offset.scale(-len(self.left_rbl), -self.rbl[0]) + self.translate_all(array_offset) self.add_layout_pins() @@ -359,7 +349,7 @@ class replica_bitcell_array(bitcell_base_array): height=self.height) def route_supplies(self): - + """ just copy supply pins from all instances """ for inst in self.insts: for pin_name in ["vdd", "gnd"]: self.copy_layout_pin(inst, pin_name) From 710f0fbae58c3a33c00fef4856490d1926ae5f6a Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 9 Mar 2023 14:37:07 -0800 Subject: [PATCH 046/102] update local/global tests for no rbls --- .../15_global_bitcell_array_1rw_1r_test.py | 4 ---- ....py => 15_global_bitcell_array_1rw_test.py} | 11 ++++++----- .../15_local_bitcell_array_1rw_1r_test.py | 18 +++++++++++------- ...t.py => 15_local_bitcell_array_1rw_test.py} | 13 +++++++++++-- 4 files changed, 28 insertions(+), 18 deletions(-) rename compiler/tests/{15_global_bitcell_array_test.py => 15_global_bitcell_array_1rw_test.py} (80%) rename compiler/tests/{15_local_bitcell_array_test.py => 15_local_bitcell_array_1rw_test.py} (75%) diff --git a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py index 480b8931..2e4ec339 100755 --- a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py @@ -32,10 +32,6 @@ class global_bitcell_array_test(openram_test): a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) self.local_check(a) - # debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") - # a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0]) - # self.local_check(a) - openram.end_openram() diff --git a/compiler/tests/15_global_bitcell_array_test.py b/compiler/tests/15_global_bitcell_array_1rw_test.py similarity index 80% rename from compiler/tests/15_global_bitcell_array_test.py rename to compiler/tests/15_global_bitcell_array_1rw_test.py index 20f50735..5335e164 100755 --- a/compiler/tests/15_global_bitcell_array_test.py +++ b/compiler/tests/15_global_bitcell_array_1rw_test.py @@ -17,18 +17,19 @@ from openram import OPTS # @unittest.skip("SKIPPING 05_global_bitcell_array_test") -class global_bitcell_array_test(openram_test): +class global_bitcell_array_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - # debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell") - # a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) - # self.local_check(a) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell") - a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4) + a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py index 07959a05..b80342eb 100755 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py @@ -28,19 +28,23 @@ class local_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica") + debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica columns or dummy rows") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) + self.local_check(a) + + debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica column but with dummy rows") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") + debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with left replica column and dummy rows") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") + debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with right replica column and dummy rows") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) + self.local_check(a) + + debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with both replica columns and dummy rows") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_1rw_test.py similarity index 75% rename from compiler/tests/15_local_bitcell_array_test.py rename to compiler/tests/15_local_bitcell_array_1rw_test.py index 655b8c78..bfe14b45 100755 --- a/compiler/tests/15_local_bitcell_array_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_test.py @@ -17,13 +17,22 @@ from openram import OPTS # @unittest.skip("SKIPPING 05_local_bitcell_array_test") -class local_bitcell_array_test(openram_test): +class local_bitcell_array_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica") + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column or dummy row") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) + self.local_check(a) + + debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column but with dummy row") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0]) self.local_check(a) From e20f28580fcf5039862f5c5e5c8bc8f5592bae87 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 9 Mar 2023 14:44:05 -0800 Subject: [PATCH 047/102] support no rbls in local array --- compiler/modules/local_bitcell_array.py | 28 ++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index f2bb8022..d0399801 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -31,7 +31,10 @@ class local_bitcell_array(bitcell_base_array): self.rows = rows self.cols = cols # This is how many RBLs are in all the arrays - self.rbl = rbl + if rbl is not None: + self.rbl = rbl + else: + self.rbl = [0] * len(self.all_ports) # This specifies which RBL to put on the left or right by port number # This could be an empty list if left_rbl is not None: @@ -84,8 +87,11 @@ class local_bitcell_array(bitcell_base_array): left_rbl=self.left_rbl, right_rbl=self.right_rbl) + # FIXME: this won't allow asymetric configurations such as rbl=[0, 1] + # but neither does a lot of this code... + rows = self.rows + (sum(self.rbl) != 0) self.wl_array = factory.create(module_type="wordline_buffer_array", - rows=self.rows + 1, + rows=rows, cols=self.cols) def add_pins(self): @@ -136,7 +142,8 @@ class local_bitcell_array(bitcell_base_array): self.wl_insts.append(self.add_inst(name="wl_driver{}".format(port), mod=self.wl_array)) temp = [] - temp += [self.get_rbl_wordline_names(port)[port]] + if self.rbl[port] != 0: + temp += [self.get_rbl_wordline_names(port)[port]] if port == 0: temp += self.get_wordline_names(port) else: @@ -180,8 +187,9 @@ class local_bitcell_array(bitcell_base_array): self.bitcell_array_inst.place(bitcell_array_offset) if len(self.all_ports) > 1: + rbl_wl_adder = self.cell.height * (self.rbl[1] != 0) wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing, - self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height) + self.bitcell_array.get_replica_bottom() + self.wl_array.height + rbl_wl_adder) self.wl_insts[1].place(wl_offset, mirror="XY") @@ -209,10 +217,16 @@ class local_bitcell_array(bitcell_base_array): # Route the global wordlines for port in self.all_ports: - if port == 0: - wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port) + if self.rbl[port] != 0: + if port == 0: + wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port) + else: + wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port)[::-1] else: - wordline_names = [self.get_rbl_wordline_names(port)[port]] + self.get_wordline_names(port)[::-1] + if port == 0: + wordline_names = self.get_wordline_names(port) + else: + wordline_names = self.get_wordline_names(port)[::-1] wordline_pins = self.wl_array.get_inputs() From 299512eba29daefeafcc636838055a9542f86617 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 22 Mar 2023 18:56:52 -0700 Subject: [PATCH 048/102] standardize array tests --- ...plica_bitcell_array_bothrbl_1rw_1r_test.py | 11 ++--- ...plica_bitcell_array_dummies_1rw_1r_test.py | 9 ++--- ..._replica_bitcell_array_dummies_1rw_test.py | 5 +-- ...plica_bitcell_array_leftrbl_1rw_1r_test.py | 10 ++--- ..._replica_bitcell_array_leftrbl_1rw_test.py | 5 +-- ...replica_bitcell_array_norbl_1rw_1r_test.py | 9 ++--- ...ed_replica_bitcell_array_norbl_1rw_test.py | 5 +-- ...lica_bitcell_array_rightrbl_1rw_1r_test.py | 10 ++--- ...replica_bitcell_array_rightrbl_1rw_test.py | 39 ++++++++++++++++++ ...plica_bitcell_array_bothrbl_1rw_1r_test.py | 11 ++--- ...plica_bitcell_array_dummies_1rw_1r_test.py | 9 ++--- ..._replica_bitcell_array_dummies_1rw_test.py | 4 +- ...plica_bitcell_array_leftrbl_1rw_1r_test.py | 10 ++--- ..._replica_bitcell_array_leftrbl_1rw_test.py | 4 +- ...replica_bitcell_array_norbl_1rw_1r_test.py | 9 ++--- ...14_replica_bitcell_array_norbl_1rw_test.py | 5 +-- ...lica_bitcell_array_rightrbl_1rw_1r_test.py | 12 ++---- ...replica_bitcell_array_rightrbl_1rw_test.py | 39 ++++++++++++++++++ .../15_local_bitcell_array_1rw_1r_test.py | 10 ++--- ...local_bitcell_array_bothrbl_1rw_1r_test.py | 40 +++++++++++++++++++ ...local_bitcell_array_dummies_1rw_1r_test.py | 40 +++++++++++++++++++ ...15_local_bitcell_array_dummies_1rw_test.py | 40 +++++++++++++++++++ ...local_bitcell_array_leftrbl_1rw_1r_test.py | 39 ++++++++++++++++++ ...15_local_bitcell_array_leftrbl_1rw_test.py | 40 +++++++++++++++++++ ...5_local_bitcell_array_norbl_1rw_1r_test.py | 40 +++++++++++++++++++ .../15_local_bitcell_array_norbl_1rw_test.py | 40 +++++++++++++++++++ ...ocal_bitcell_array_rightrbl_1rw_1r_test.py | 39 ++++++++++++++++++ ...5_local_bitcell_array_rightrbl_1rw_test.py | 40 +++++++++++++++++++ 28 files changed, 484 insertions(+), 90 deletions(-) create mode 100755 compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py create mode 100755 compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_dummies_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_norbl_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py diff --git a/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py index a2f57e45..2237a21f 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_bothrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,13 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 array left and right replica for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0], - right_rbl=[1]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with both replica columns") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py index bc432c6b..f361b4af 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_dummies_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with dummy rows only") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py index 175689c3..6ce8a1c0 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_test(openram_test): +class capped_replica_bitcell_array_dummies_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 capped replica array for 1rw cell with dummy row only") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py index 3e1bd805..72bc698c 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,12 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with left replica column") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py index b4ba91d1..5d1523ae 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_test(openram_test): +class capped_replica_bitcell_array_leftrbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 capped replica array for 1rw cell with left replica column") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py index e9a61609..c1ea6516 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_norbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[0, 0]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell without replica columns or dummy rows") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[0, 0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py index e845d32b..5eb5f98e 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_test(openram_test): +class capped_replica_bitcell_array_norbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py index deac7075..22433884 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,12 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - right_rbl=[1]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with right replica column") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py new file mode 100755 index 00000000..bd654d73 --- /dev/null +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class capped_replica_bitcell_array_rightrbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + debug.info(2, "Testing 7x5 capped replica array for 1rw cell with right replica column") + a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py index d6e075a4..504e0390 100755 --- a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_bothrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,13 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 array left and right replica for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0], - right_rbl=[1]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with both replica columns") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py index ebdc9584..13e0169a 100755 --- a/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_dummies_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with dummy rows only") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py index e893c3ca..465260b4 100755 --- a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_dummies_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,7 +25,7 @@ class replica_bitcell_array_test(openram_test): OPTS.num_w_ports = 0 factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 replica array for 1rw cell with dummy row only") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py index 36254cb5..d4b514df 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,12 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with left replica column") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py index f77a571d..9127a934 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_leftrbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,7 +25,7 @@ class replica_bitcell_array_test(openram_test): OPTS.num_w_ports = 0 factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py index 78f77ece..d2869183 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_norbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[0, 0]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell without replica columns or dummy rows") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[0, 0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py index df20a19a..bc292041 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_norbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py index 8d1d8f23..c2f29c2f 100755 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -14,23 +14,19 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_rightrbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 + OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - right_rbl=[1]) + debug.info(2, "Testing 7x5 replica array for 1rw cell with right replica column") + a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py new file mode 100755 index 00000000..18ccb00c --- /dev/null +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py index b80342eb..8f9cebc0 100755 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py @@ -28,23 +28,23 @@ class local_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica columns or dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell without replica columns or dummy rows") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica column but with dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with dummy rows only") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with left replica column and dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with left replica column") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with right replica column and dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with right replica column") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with both replica columns and dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with both replica columns") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) diff --git a/compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py new file mode 100755 index 00000000..08e4c5ee --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_bothrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with both replica columns") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py new file mode 100755 index 00000000..80667466 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_dummies_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with dummy rows only") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_dummies_1rw_test.py b/compiler/tests/15_local_bitcell_array_dummies_1rw_test.py new file mode 100755 index 00000000..20d2398e --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_dummies_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_dummies_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with dummy row only") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py new file mode 100755 index 00000000..0e1f2918 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_leftrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with left replica column") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py new file mode 100755 index 00000000..756da97e --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_leftrbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with left replica column") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py new file mode 100755 index 00000000..f86188c2 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_norbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell without replica columns or dummy rows") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_norbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_norbl_1rw_test.py new file mode 100755 index 00000000..795fd14e --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_norbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_norbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell without replica column or dummy row") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[0, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py new file mode 100755 index 00000000..88c0099d --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_rightrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with right replica column") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py new file mode 100755 index 00000000..b8427d82 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_rightrbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with right replica column") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 9181f6a21816a6156beac34d10d7dd85e078f835 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 3 Apr 2023 10:08:57 -0700 Subject: [PATCH 049/102] standardize 14* test structure --- .../tests/14_capped_replica_bitcell_array_dummies_1rw_test.py | 1 + .../14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py | 1 + .../tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py | 1 + .../tests/14_capped_replica_bitcell_array_norbl_1rw_test.py | 1 + .../14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py | 1 + .../tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py | 1 + compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py | 2 +- compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py | 1 + compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py | 2 +- compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py | 1 + compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py | 1 + compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py | 1 + 12 files changed, 12 insertions(+), 2 deletions(-) diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py index 6ce8a1c0..c0ff770f 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_dummies_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell with dummy row only") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py index 72bc698c..53b4231b 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class capped_replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py index 5d1523ae..7ed5fdf9 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_leftrbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell with left replica column") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py index 5eb5f98e..56080536 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_norbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py index 22433884..c8d322c4 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class capped_replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py index bd654d73..1386b2cc 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_rightrbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell with right replica column") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py index 465260b4..f5a2a3e1 100755 --- a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py @@ -23,8 +23,8 @@ class replica_bitcell_array_dummies_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() - factory.reset() debug.info(2, "Testing 7x5 replica array for 1rw cell with dummy row only") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py index d4b514df..8f091ada 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py index 9127a934..1a4944bf 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py @@ -23,8 +23,8 @@ class replica_bitcell_array_leftrbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() - factory.reset() debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py index bc292041..be19330f 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py @@ -23,6 +23,7 @@ class replica_bitcell_array_norbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py index c2f29c2f..8c32fb01 100755 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class replica_bitcell_array_rightrbl_1rw_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py index 18ccb00c..6d3a73c5 100755 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py @@ -31,6 +31,7 @@ class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() From 83b25138d0a4d5b17741017a12eb545d1d9f301b Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 3 Apr 2023 10:11:49 -0700 Subject: [PATCH 050/102] apply 14* standard to 15_local tests --- .../15_local_bitcell_array_1rw_1r_test.py | 59 ------------------- .../tests/15_local_bitcell_array_1rw_test.py | 51 ---------------- ...local_bitcell_array_leftrbl_1rw_1r_test.py | 1 + ...ocal_bitcell_array_rightrbl_1rw_1r_test.py | 1 + 4 files changed, 2 insertions(+), 110 deletions(-) delete mode 100755 compiler/tests/15_local_bitcell_array_1rw_1r_test.py delete mode 100755 compiler/tests/15_local_bitcell_array_1rw_test.py diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py deleted file mode 100755 index 8f9cebc0..00000000 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -# @unittest.skip("SKIPPING 05_local_bitcell_array_test") -class local_bitcell_array_1rw_1r_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 0 - openram.setup_bitcell() - - debug.info(2, "Testing 4x4 local array for 1rw1r cell without replica columns or dummy rows") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with dummy rows only") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with left replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with right replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local array for 1rw1r cell with both replica columns") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) - self.local_check(a) - - openram.end_openram() - - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_1rw_test.py b/compiler/tests/15_local_bitcell_array_1rw_test.py deleted file mode 100755 index bfe14b45..00000000 --- a/compiler/tests/15_local_bitcell_array_1rw_test.py +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -# @unittest.skip("SKIPPING 05_local_bitcell_array_test") -class local_bitcell_array_1rw_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 0 - OPTS.num_w_ports = 0 - openram.setup_bitcell() - - debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column or dummy row") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column but with dummy row") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0]) - self.local_check(a) - - debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) - self.local_check(a) - - openram.end_openram() - - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py index 0e1f2918..65be2de1 100755 --- a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class local_bitcell_array_leftrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py index 88c0099d..cc392587 100755 --- a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class local_bitcell_array_rightrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() From d00ba73bc9b6eaff80b9e909eb90420d12128f60 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Apr 2023 14:47:15 -0700 Subject: [PATCH 051/102] add no rbl support to global array --- compiler/modules/global_bitcell_array.py | 83 ++++++++++++++---------- 1 file changed, 50 insertions(+), 33 deletions(-) diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index be50037f..e75f537d 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -20,14 +20,31 @@ class global_bitcell_array(bitcell_base_array): Rows is an integer number for all local arrays. Cols is a list of the array widths. """ - def __init__(self, rows, cols, name=""): + def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""): # The total of all columns will be the number of columns super().__init__(name=name, rows=rows, cols=sum(cols), column_offset=0) self.column_sizes = cols self.col_offsets = [0] + list(cumsum(cols)[:-1]) - debug.check(len(self.all_ports)<=2, "Only support dual port or less in global bitcell array.") - self.rbl = [1, 1 if len(self.all_ports)>1 else 0] + debug.check(len(self.all_ports) < 3, "Only support dual port or less in global bitcell array.") + + # This is how many RBLs are in all the arrays + if rbl is not None: + self.rbl = rbl + else: + self.rbl = [0] * len(self.all_ports) + # This specifies which RBL to put on the left or right by port number + # This could be an empty list + if left_rbl is not None: + self.left_rbl = left_rbl + else: + self.left_rbl = [] + # This could be an empty list + if right_rbl is not None: + self.right_rbl = right_rbl + else: + self.right_rbl=[] + self.rbls = self.left_rbl + self.right_rbl self.create_netlist() if not OPTS.netlist_only: @@ -56,14 +73,13 @@ class global_bitcell_array(bitcell_base_array): self.local_mods = [] # Special case of a single local array - # so it should contain the left and possibly right RBL if len(self.column_sizes) == 1: la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=self.column_sizes[0], rbl=self.rbl, - left_rbl=[0], - right_rbl=[1] if len(self.all_ports) > 1 else []) + left_rbl=self.left_rbl, + right_rbl=self.right_rbl) self.local_mods.append(la) return @@ -74,14 +90,14 @@ class global_bitcell_array(bitcell_base_array): rows=self.row_size, cols=cols, rbl=self.rbl, - left_rbl=[0]) - # Add the right RBL to the last subarray - elif i == len(self.column_sizes) - 1 and len(self.all_ports) > 1: + left_rbl=self.left_rbl) + # Add the right RBLs to the last subarray + elif i == len(self.column_sizes) - 1: la = factory.create(module_type="local_bitcell_array", rows=self.row_size, cols=cols, rbl=self.rbl, - right_rbl=[1]) + right_rbl=self.right_rbl) # Middle subarrays do not have any RBLs else: la = factory.create(module_type="local_bitcell_array", @@ -100,13 +116,16 @@ class global_bitcell_array(bitcell_base_array): self.add_pin("gnd", "GROUND") def add_bitline_pins(self): + # FIXME: aren't these already defined via inheritence by bitcell base array? self.bitline_names = [[] for x in self.all_ports] self.rbl_bitline_names = [[] for x in self.all_ports] - for port in self.all_ports: - self.rbl_bitline_names[0].append("rbl_bl_{}_0".format(port)) - for port in self.all_ports: - self.rbl_bitline_names[0].append("rbl_br_{}_0".format(port)) + # The bit is which port the RBL is for + for bit in self.rbls: + for port in self.all_ports: + self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit)) + for port in self.all_ports: + self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit)) for col in range(self.column_size): for port in self.all_ports: @@ -114,21 +133,16 @@ class global_bitcell_array(bitcell_base_array): for port in self.all_ports: self.bitline_names[port].append("br_{0}_{1}".format(port, col)) - if len(self.all_ports) > 1: - for port in self.all_ports: - self.rbl_bitline_names[1].append("rbl_bl_{}_1".format(port)) - for port in self.all_ports: - self.rbl_bitline_names[1].append("rbl_br_{}_1".format(port)) - # Make a flat list too self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl] # Make a flat list too self.all_rbl_bitline_names = [x for sl in zip(*self.rbl_bitline_names) for x in sl] - self.add_pin_list(self.rbl_bitline_names[0], "INOUT") + for port in self.left_rbl: + self.add_pin_list(self.rbl_bitline_names[port], "INOUT") self.add_pin_list(self.all_bitline_names, "INOUT") - if len(self.all_ports) > 1: - self.add_pin_list(self.rbl_bitline_names[1], "INOUT") + for port in self.right_rbl: + self.add_pin_list(self.rbl_bitline_names[port], "INOUT") def add_wordline_pins(self): @@ -137,6 +151,8 @@ class global_bitcell_array(bitcell_base_array): self.wordline_names = [[] for x in self.all_ports] for bit in self.all_ports: + if self.rbl[bit] == 0: + continue for port in self.all_ports: self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit)) @@ -239,17 +255,18 @@ class global_bitcell_array(bitcell_base_array): start=left_pin.lc(), end=right_pin.rc()) - # Replica bitlines - self.copy_layout_pin(self.local_insts[0], "rbl_bl_0_0") - self.copy_layout_pin(self.local_insts[0], "rbl_br_0_0") + if len(self.rbls) > 0: + # Replica bitlines + self.copy_layout_pin(self.local_insts[0], "rbl_bl_0_0") + self.copy_layout_pin(self.local_insts[0], "rbl_br_0_0") - if len(self.all_ports) > 1: - self.copy_layout_pin(self.local_insts[0], "rbl_bl_1_0") - self.copy_layout_pin(self.local_insts[0], "rbl_br_1_0") - self.copy_layout_pin(self.local_insts[-1], "rbl_bl_0_1") - self.copy_layout_pin(self.local_insts[-1], "rbl_br_0_1") - self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_1") - self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_1") + if len(self.all_ports) > 1: + self.copy_layout_pin(self.local_insts[0], "rbl_bl_1_0") + self.copy_layout_pin(self.local_insts[0], "rbl_br_1_0") + self.copy_layout_pin(self.local_insts[-1], "rbl_bl_0_1") + self.copy_layout_pin(self.local_insts[-1], "rbl_br_0_1") + self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_1") + self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_1") for inst in self.insts: self.copy_power_pins(inst, "vdd") From ae6d2716025a892b9af5ca022595dff6d45480e8 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Apr 2023 15:33:45 -0700 Subject: [PATCH 052/102] add support for no rbl to port data --- compiler/modules/port_data.py | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 37b6b76d..724d3fb3 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -18,13 +18,14 @@ from openram import OPTS class port_data(design): """ Create the data port (column mux, sense amps, write driver, etc.) for the given port number. - Port 0 always has the RBL on the left while port 1 is on the right. + When RBLs present: port 0 always has the RBL on the left while port 1 is on the right. """ - def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="",): + def __init__(self, sram_config, port, has_rbl, num_spare_cols=None, bit_offsets=None, name="",): sram_config.set_local_config(self) self.port = port + self.has_rbl = has_rbl if self.write_size != self.word_size: self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: @@ -115,8 +116,9 @@ class port_data(design): def add_pins(self): """ Adding pins for port data module""" - self.add_pin("rbl_bl", "INOUT") - self.add_pin("rbl_br", "INOUT") + if self.has_rbl: + self.add_pin("rbl_bl", "INOUT") + self.add_pin("rbl_br", "INOUT") for bit in range(self.num_cols): self.add_pin("bl_{0}".format(bit), "INOUT") self.add_pin("br_{0}".format(bit), "INOUT") @@ -209,8 +211,9 @@ class port_data(design): # Append an offset on the right precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width] + # has_rbl is a boolean treated as 1 if true 0 if false typical python self.precharge_array = factory.create(module_type="precharge_array", - columns=self.num_cols + self.num_spare_cols + 1, + columns=self.num_cols + self.num_spare_cols + self.has_rbl, offsets=precharge_bit_offsets, bitcell_bl=self.bl_names[self.port], bitcell_br=self.br_names[self.port], @@ -294,7 +297,7 @@ class port_data(design): mod=self.precharge_array) temp = [] # Use left BLs for RBL - if self.port==0: + if self.port==0 and self.has_rbl: temp.append("rbl_bl") temp.append("rbl_br") for bit in range(self.num_cols): @@ -306,7 +309,7 @@ class port_data(design): temp.append("sparebr_{0}".format(bit)) # Use right BLs for RBL - if self.port==1: + if self.port==1 and self.has_rbl: temp.append("rbl_bl") temp.append("rbl_br") temp.extend(["p_en_bar", "vdd"]) @@ -683,11 +686,11 @@ class port_data(design): """ Add the bitline pins for the given port """ # Connect one bitline to the RBL and offset the indices for the other BLs - if self.port==0: + if self.port==0 and self.has_rbl: self.copy_layout_pin(self.precharge_array_inst, "bl_0", "rbl_bl") self.copy_layout_pin(self.precharge_array_inst, "br_0", "rbl_br") bit_offset=1 - elif self.port==1: + elif self.port==1 and self.has_rbl: self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(self.num_cols + self.num_spare_cols), "rbl_bl") self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(self.num_cols + self.num_spare_cols), "rbl_br") bit_offset=0 From efbb6587844249750683dee8ebb74c000cd37697 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Apr 2023 16:04:20 -0700 Subject: [PATCH 053/102] add no rbl support to port address --- compiler/modules/port_address.py | 111 +++++++++++++++++-------------- 1 file changed, 60 insertions(+), 51 deletions(-) diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 1621f7cf..89e05dd8 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -18,11 +18,12 @@ class port_address(design): Create the address port (row decoder and wordline driver).. """ - def __init__(self, cols, rows, port, name=""): + def __init__(self, cols, rows, port, has_rbl, name=""): self.num_cols = cols self.num_rows = rows self.port = port + self.has_rbl = has_rbl self.addr_size = ceil(log(self.num_rows, 2)) if name == "": @@ -41,7 +42,8 @@ class port_address(design): self.add_modules() self.create_row_decoder() self.create_wordline_driver() - self.create_rbl_driver() + if self.has_rbl: + self.create_rbl_driver() def create_layout(self): if "li" in layer: @@ -63,7 +65,8 @@ class port_address(design): for bit in range(self.num_rows): self.add_pin("wl_{0}".format(bit), "OUTPUT") - self.add_pin("rbl_wl", "OUTPUT") + if self.has_rbl: + self.add_pin("rbl_wl", "OUTPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -76,12 +79,13 @@ class port_address(design): def route_supplies(self): """ Propagate all vdd/gnd pins up to this level for all modules """ - if layer_props.wordline_driver.vertical_supply: - self.copy_layout_pin(self.rbl_driver_inst, "vdd") - else: - rbl_pos = self.rbl_driver_inst.get_pin("vdd").rc() - self.add_power_pin("vdd", rbl_pos) - self.add_path("m4", [rbl_pos, self.wordline_driver_array_inst.get_pins("vdd")[0].rc()]) + if self.has_rbl: + if layer_props.wordline_driver.vertical_supply: + self.copy_layout_pin(self.rbl_driver_inst, "vdd") + else: + rbl_pos = self.rbl_driver_inst.get_pin("vdd").rc() + self.add_power_pin("vdd", rbl_pos) + self.add_path("m4", [rbl_pos, self.wordline_driver_array_inst.get_pins("vdd")[0].rc()]) self.copy_layout_pin(self.wordline_driver_array_inst, "vdd") self.copy_layout_pin(self.wordline_driver_array_inst, "gnd") @@ -90,11 +94,12 @@ class port_address(design): self.copy_layout_pin(self.row_decoder_inst, "gnd") # Also connect the B input of the RBL and_dec to vdd - if OPTS.local_array_size == 0: - rbl_b_pin = self.rbl_driver_inst.get_pin("B") - rbl_loc = rbl_b_pin.center() - vector(3 * self.m1_pitch, 0) - self.add_path(rbl_b_pin.layer, [rbl_b_pin.center(), rbl_loc]) - self.add_power_pin("vdd", rbl_loc, start_layer=rbl_b_pin.layer) + if self.has_rbl: + if OPTS.local_array_size == 0: + rbl_b_pin = self.rbl_driver_inst.get_pin("B") + rbl_loc = rbl_b_pin.center() - vector(3 * self.m1_pitch, 0) + self.add_path(rbl_b_pin.layer, [rbl_b_pin.center(), rbl_loc]) + self.add_power_pin("vdd", rbl_loc, start_layer=rbl_b_pin.layer) def route_pins(self): for row in range(self.addr_size): @@ -105,7 +110,8 @@ class port_address(design): driver_name = "wl_{}".format(row) self.copy_layout_pin(self.wordline_driver_array_inst, driver_name) - self.copy_layout_pin(self.rbl_driver_inst, "Z", "rbl_wl") + if self.has_rbl: + self.copy_layout_pin(self.rbl_driver_inst, "Z", "rbl_wl") def route_internal(self): for row in range(self.num_rows): @@ -125,24 +131,25 @@ class port_address(design): offset=driver_in_pos) # Route the RBL from the enable input - en_pin = self.wordline_driver_array_inst.get_pin("en") - if self.port == 0: - en_pos = en_pin.bc() - else: - en_pos = en_pin.uc() - rbl_in_pin = self.rbl_driver_inst.get_pin("A") - rbl_in_pos = rbl_in_pin.center() + if self.has_rbl: + en_pin = self.wordline_driver_array_inst.get_pin("en") + if self.port == 0: + en_pos = en_pin.bc() + else: + en_pos = en_pin.uc() + rbl_in_pin = self.rbl_driver_inst.get_pin("A") + rbl_in_pos = rbl_in_pin.center() - self.add_via_stack_center(from_layer=rbl_in_pin.layer, - to_layer=en_pin.layer, - offset=rbl_in_pos) - self.add_zjog(layer=en_pin.layer, - start=rbl_in_pos, - end=en_pos, - first_direction="V") - self.add_layout_pin_rect_center(text="wl_en", - layer=en_pin.layer, - offset=rbl_in_pos) + self.add_via_stack_center(from_layer=rbl_in_pin.layer, + to_layer=en_pin.layer, + offset=rbl_in_pos) + self.add_zjog(layer=en_pin.layer, + start=rbl_in_pos, + end=en_pos, + first_direction="V") + self.add_layout_pin_rect_center(text="wl_en", + layer=en_pin.layer, + offset=rbl_in_pos) def add_modules(self): @@ -164,16 +171,17 @@ class port_address(design): # to compensate for the local array inverters b = factory.create(module_type=OPTS.bitcell) - if local_array_size > 0: - # The local wordline driver will change the polarity - self.rbl_driver = factory.create(module_type="inv_dec", - size=driver_size, - height=b.height) - else: - # There is no local wordline driver - self.rbl_driver = factory.create(module_type="and2_dec", - size=driver_size, - height=b.height) + if self.has_rbl: + if local_array_size > 0: + # The local wordline driver will change the polarity + self.rbl_driver = factory.create(module_type="inv_dec", + size=driver_size, + height=b.height) + else: + # There is no local wordline driver + self.rbl_driver = factory.create(module_type="and2_dec", + size=driver_size, + height=b.height) def create_row_decoder(self): """ Create the hierarchical row decoder """ @@ -231,16 +239,17 @@ class port_address(design): wordline_driver_array_offset = vector(self.row_decoder_inst.rx(), 0) self.wordline_driver_array_inst.place(wordline_driver_array_offset) - # This m4_pitch corresponds to the offset space for jog routing in the - # wordline_driver_array - rbl_driver_offset = wordline_driver_array_offset + vector(2 * self.m4_pitch, 0) + if self.has_rbl: + # This m4_pitch corresponds to the offset space for jog routing in the + # wordline_driver_array + rbl_driver_offset = wordline_driver_array_offset + vector(2 * self.m4_pitch, 0) - if self.port == 0: - self.rbl_driver_inst.place(rbl_driver_offset, "MX") - else: - rbl_driver_offset += vector(0, - self.wordline_driver_array.height) - self.rbl_driver_inst.place(rbl_driver_offset) + if self.port == 0: + self.rbl_driver_inst.place(rbl_driver_offset, "MX") + else: + rbl_driver_offset += vector(0, + self.wordline_driver_array.height) + self.rbl_driver_inst.place(rbl_driver_offset) # Pass this up self.predecoder_height = self.row_decoder.predecoder_height From 3c7f35d2958782303248075f1057da8987147c14 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Fri, 7 Apr 2023 10:02:38 -0700 Subject: [PATCH 054/102] add no rbl support to bank module --- compiler/modules/bank.py | 59 ++++++++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 8cf92961..47dcad44 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -85,7 +85,8 @@ class bank(design): for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout{0}_{1}".format(port, bit), "OUTPUT") for port in self.all_ports: - self.add_pin("rbl_bl_{0}_{0}".format(port), "OUTPUT") + if self.has_rbl: + self.add_pin("rbl_bl_{0}_{0}".format(port), "OUTPUT") for port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_pin("din{0}_{1}".format(port, bit), "INPUT") @@ -118,7 +119,8 @@ class bank(design): for port in self.all_ports: self.route_bitlines(port) - self.route_rbl(port) + if self.has_rbl: + self.route_rbl(port) self.route_port_address(port) self.route_column_address_lines(port) self.route_control_lines(port) @@ -360,6 +362,18 @@ class bank(design): def add_modules(self): """ Add all the modules using the class loader """ + # delay control logic does not have RBLs + if OPTS.control_logic != "control_logic_delay": + self.has_rbl = True + rbl = [1, 1 if len(self.all_ports)>1 else 0] + left_rbl = [0] + right_rbl = [1] if len(self.all_ports)>1 else [] + else: + self.has_rbl = False + rbl = [0, 0] + left_rbl = [] + right_rbl = [] + local_array_size = OPTS.local_array_size if local_array_size > 0: @@ -372,21 +386,25 @@ class bank(design): cols.append(local_array_size + final_size) self.bitcell_array = factory.create(module_type="global_bitcell_array", cols=cols, - rows=self.num_rows) + rows=self.num_rows, + rbl=rbl, + left_rbl=left_rbl, + right_rbl=right_rbl) else: self.bitcell_array = factory.create(module_type="capped_replica_bitcell_array", cols=self.num_cols + self.num_spare_cols, rows=self.num_rows, - rbl=[1, 1 if len(self.all_ports)>1 else 0], - left_rbl=[0], - right_rbl=[1] if len(self.all_ports)>1 else []) + rbl=rbl, + left_rbl=left_rbl, + right_rbl=right_rbl) self.port_address = [] for port in self.all_ports: self.port_address.append(factory.create(module_type="port_address", cols=self.num_cols + self.num_spare_cols, rows=self.num_rows, - port=port)) + port=port, + has_rbl=self.has_rbl)) self.port_data = [] self.bit_offsets = self.get_column_offsets() @@ -394,6 +412,7 @@ class bank(design): self.port_data.append(factory.create(module_type="port_data", sram_config=self.sram_config, port=port, + has_rbl=self.has_rbl, bit_offsets=self.bit_offsets)) def create_bitcell_array(self): @@ -407,9 +426,10 @@ class bank(design): # gnd temp = self.bitcell_array.get_inouts() - temp.append("rbl_wl0") + if self.has_rbl: + temp.append("rbl_wl0") temp.extend(self.bitcell_array.get_wordline_names()) - if len(self.all_ports) > 1: + if len(self.all_ports) > 1 and self.has_rbl: temp.append("rbl_wl1") temp.append("vdd") @@ -432,7 +452,8 @@ class bank(design): mod=self.port_data[port]) temp = [] - temp.extend(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)]) + if self.has_rbl: + temp.extend(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)]) temp.extend(self.bitcell_array.get_bitline_names(port)) if port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): @@ -480,7 +501,8 @@ class bank(design): temp.append("wl_en{}".format(port)) wordline_names = self.bitcell_array.get_wordline_names(port) temp.extend(wordline_names) - temp.append("rbl_wl{}".format(port)) + if self.has_rbl: + temp.append("rbl_wl{}".format(port)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) @@ -719,8 +741,9 @@ class bank(design): inst2_br_name=inst2_br_name) # Connect the replica bitlines - for (array_name, data_name) in zip(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)], ["rbl_bl", "rbl_br"]): - self.connect_bitline(inst1, inst2, array_name, data_name) + if self.has_rbl: + for (array_name, data_name) in zip(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)], ["rbl_bl", "rbl_br"]): + self.connect_bitline(inst1, inst2, array_name, data_name) def route_port_data_out(self, port): """ Add pins for the port data out """ @@ -841,7 +864,10 @@ class bank(design): def route_port_address_out(self, port, side="left"): """ Connecting Wordline driver output to Bitcell WL connection """ - driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + ["rbl_wl"] + driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + if self.has_rbl: + driver_names = driver_names + ["rbl_wl"] + # rbl_wl in next two lines will be ignored by zip once driver_names is exhausted in the no rbl case rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]): # The mid guarantees we exit the input cell to the right. @@ -875,7 +901,10 @@ class bank(design): def route_port_address_right(self, port): """ Connecting Wordline driver output to Bitcell WL connection """ - driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + ["rbl_wl"] + driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + if self.has_rbl: + driver_names = driver_names + ["rbl_wl"] + # rbl_wl in next two lines will be ignored by zip once driver_names is exhausted in the no rbl case rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]): # The mid guarantees we exit the input cell to the right. From 5b701d828e079c2ae7a1ed70a38ab97eb5c3182a Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Fri, 7 Apr 2023 10:32:11 -0700 Subject: [PATCH 055/102] remove unused function --- compiler/modules/bank.py | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 47dcad44..d3ca8e3a 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -115,8 +115,6 @@ class bank(design): """ Create routing amoung the modules """ self.route_central_bus() - self.route_unused_wordlines() - for port in self.all_ports: self.route_bitlines(port) if self.has_rbl: @@ -1000,36 +998,6 @@ class bank(design): # layer="m1", # offset=data_pin.center()) - def route_unused_wordlines(self): - """ Connect the unused RBL and dummy wordlines to gnd """ - gnd_wl_names = [] - return - # Connect unused RBL WL to gnd - # All RBL WL names - array_rbl_names = set(self.bitcell_array.get_rbl_wordline_names()) - # List of used RBL WL names - rbl_wl_names = set() - for port in self.all_ports: - rbl_wl_names.add(self.bitcell_array.get_rbl_wordline_names(port)[port]) - gnd_wl_names = list((array_rbl_names - rbl_wl_names)) - - for wl_name in gnd_wl_names: - pin = self.bitcell_array_inst.get_pin(wl_name) - pin_layer = pin.layer - layer_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer)) - left_pin_loc = pin.lc() - right_pin_loc = pin.rc() - - # Place the pins a track outside of the array - left_loc = left_pin_loc - vector(layer_pitch, 0) - right_loc = right_pin_loc + vector(layer_pitch, 0) - self.add_power_pin("gnd", left_loc, directions=("H", "H")) - self.add_power_pin("gnd", right_loc, directions=("H", "H")) - - # Add a path to connect to the array - self.add_path(pin_layer, [left_loc, left_pin_loc]) - self.add_path(pin_layer, [right_loc, right_pin_loc]) - def route_control_lines(self, port): """ Route the control lines of the entire bank """ From dff94a032e0c10dc33e67bad78843476065cb3ed Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Fri, 7 Apr 2023 11:30:15 -0700 Subject: [PATCH 056/102] fix bug in right rbl dual port replica array test --- .../14_replica_bitcell_array_rightrbl_1rw_1r_test.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py index 8c32fb01..6d3a73c5 100755 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -14,19 +14,19 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_rightrbl_1rw_test(openram_test): +class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 0 + OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 7x5 replica array for 1rw cell with right replica column") - a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) self.local_check(a) openram.end_openram() From 670b40642b992b5a28022b7d7e2a144207e3b49f Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 10 Apr 2023 10:38:52 -0700 Subject: [PATCH 057/102] add no rbl tests to 15 global array tests --- ...global_bitcell_array_norbl_1rw_1r_test.py} | 11 ++--- ...15_global_bitcell_array_norbl_1rw_test.py} | 13 +++--- ...15_global_bitcell_array_rbl_1rw_1r_test.py | 40 +++++++++++++++++++ .../15_global_bitcell_array_rbl_1rw_test.py | 40 +++++++++++++++++++ 4 files changed, 89 insertions(+), 15 deletions(-) rename compiler/tests/{15_global_bitcell_array_1rw_1r_test.py => 15_global_bitcell_array_norbl_1rw_1r_test.py} (78%) rename compiler/tests/{15_global_bitcell_array_1rw_test.py => 15_global_bitcell_array_norbl_1rw_test.py} (78%) create mode 100755 compiler/tests/15_global_bitcell_array_rbl_1rw_1r_test.py create mode 100755 compiler/tests/15_global_bitcell_array_rbl_1rw_test.py diff --git a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_norbl_1rw_1r_test.py similarity index 78% rename from compiler/tests/15_global_bitcell_array_1rw_1r_test.py rename to compiler/tests/15_global_bitcell_array_norbl_1rw_1r_test.py index 2e4ec339..0c887e16 100755 --- a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_global_bitcell_array_norbl_1rw_1r_test.py @@ -1,9 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2023 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz # All rights reserved. # import sys, os @@ -16,8 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -# @unittest.skip("SKIPPING 05_global_bitcell_array_test") -class global_bitcell_array_test(openram_test): +class global_bitcell_array_norbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -28,8 +25,8 @@ class global_bitcell_array_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 2 x 4x4 global bitcell array for cell_1rw_1r") - a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) + debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw1r cell without replica columns") + a = factory.create(module_type="global_bitcell_array", cols=[4, 4, 4], rows=4, rbl=[0, 0], left_rbl=[], right_rbl=[]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/15_global_bitcell_array_1rw_test.py b/compiler/tests/15_global_bitcell_array_norbl_1rw_test.py similarity index 78% rename from compiler/tests/15_global_bitcell_array_1rw_test.py rename to compiler/tests/15_global_bitcell_array_norbl_1rw_test.py index 5335e164..e1dbffc4 100755 --- a/compiler/tests/15_global_bitcell_array_1rw_test.py +++ b/compiler/tests/15_global_bitcell_array_norbl_1rw_test.py @@ -1,9 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2023 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz # All rights reserved. # import sys, os @@ -11,13 +9,12 @@ import unittest from testutils import * import openram -from openram.sram_factory import factory from openram import debug +from openram.sram_factory import factory from openram import OPTS -# @unittest.skip("SKIPPING 05_global_bitcell_array_test") -class global_bitcell_array_1rw_test(openram_test): +class global_bitcell_array_norbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -28,8 +25,8 @@ class global_bitcell_array_1rw_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell") - a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4) + debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw cell without replica column") + a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, rbl=[0, 0], left_rbl=[]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/15_global_bitcell_array_rbl_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_rbl_1rw_1r_test.py new file mode 100755 index 00000000..c5ef0b92 --- /dev/null +++ b/compiler/tests/15_global_bitcell_array_rbl_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class global_bitcell_array_rbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw1r cell with replica columns") + a = factory.create(module_type="global_bitcell_array", cols=[4, 4, 4], rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_global_bitcell_array_rbl_1rw_test.py b/compiler/tests/15_global_bitcell_array_rbl_1rw_test.py new file mode 100755 index 00000000..b86c2c84 --- /dev/null +++ b/compiler/tests/15_global_bitcell_array_rbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class global_bitcell_array_rbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw cell with left replica column") + a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, rbl=[1, 0], left_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From eea748ff3efb3eaf165ba8aad1d79feaedcd1907 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 10 Apr 2023 11:16:10 -0700 Subject: [PATCH 058/102] remove test for unsupported config --- ...replica_bitcell_array_rightrbl_1rw_test.py | 40 ------------------- ...replica_bitcell_array_rightrbl_1rw_test.py | 40 ------------------- ...5_local_bitcell_array_rightrbl_1rw_test.py | 40 ------------------- 3 files changed, 120 deletions(-) delete mode 100755 compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py delete mode 100755 compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py delete mode 100755 compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py deleted file mode 100755 index 1386b2cc..00000000 --- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -class capped_replica_bitcell_array_rightrbl_1rw_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 0 - OPTS.num_w_ports = 0 - openram.setup_bitcell() - - debug.info(2, "Testing 7x5 capped replica array for 1rw cell with right replica column") - a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) - self.local_check(a) - - openram.end_openram() - - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py deleted file mode 100755 index 6d3a73c5..00000000 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 0 - openram.setup_bitcell() - - debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) - self.local_check(a) - - openram.end_openram() - - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py deleted file mode 100755 index b8427d82..00000000 --- a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -class local_bitcell_array_rightrbl_1rw_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 0 - OPTS.num_w_ports = 0 - openram.setup_bitcell() - - debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with right replica column") - a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) - self.local_check(a) - - openram.end_openram() - - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) From 744ba0e892c1de9474ad486cd338ce8787dce833 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 25 Apr 2023 09:24:18 -0700 Subject: [PATCH 059/102] fix precharge bit offsets in no rbl case --- compiler/modules/port_data.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 724d3fb3..cefdb871 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -204,12 +204,15 @@ class port_data(design): precharge_width = cell.width + strap.width else: precharge_width = cell.width - if self.port == 0: - # Append an offset on the left - precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets + if self.has_rbl: + if self.port == 0: + # Append an offset on the left + precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets + else: + # Append an offset on the right + precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width] else: - # Append an offset on the right - precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width] + precharge_bit_offsets = self.bit_offsets # has_rbl is a boolean treated as 1 if true 0 if false typical python self.precharge_array = factory.create(module_type="precharge_array", @@ -561,7 +564,7 @@ class port_data(design): inst1 = self.precharge_array_inst inst1_bls_templ="{inst}_{bit}" - if self.port==0: + if self.port==0 and self.has_rbl: start_bit=1 else: start_bit=0 From 123149503b80dec347e7ee08b350e739ec370b21 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 25 Apr 2023 09:27:56 -0700 Subject: [PATCH 060/102] add a bank test with no rbl --- .../tests/19_single_bank_nomux_norbl_test.py | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100755 compiler/tests/19_single_bank_nomux_norbl_test.py diff --git a/compiler/tests/19_single_bank_nomux_norbl_test.py b/compiler/tests/19_single_bank_nomux_norbl_test.py new file mode 100755 index 00000000..4f8eec1d --- /dev/null +++ b/compiler/tests/19_single_bank_nomux_norbl_test.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class single_bank_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config + + if OPTS.tech_name == "sky130": + num_spare_rows = 1 + num_spare_cols = 1 + else: + num_spare_rows = 0 + num_spare_cols = 0 + + c = sram_config(word_size=4, + num_words=16, + num_spare_cols=num_spare_cols, + num_spare_rows=num_spare_rows) + + c.words_per_row=1 + OPTS.control_logic = "control_logic_delay" + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 79e5c1ad8651604a37517496d18dd8748da0a140 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 16 May 2023 14:36:58 -0700 Subject: [PATCH 061/102] add dp norbl bank test --- .../19_single_bank_nomux_norbl_1rw_1r_test.py | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py diff --git a/compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py new file mode 100644 index 00000000..47ebfa7c --- /dev/null +++ b/compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class single_bank_nomux_norbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + c = sram_config(word_size=4, + num_words=16) + + c.words_per_row=1 + OPTS.control_logic = "control_logic_delay" + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 2709f61317255a8edd30d58c91ba7ffdde02fd5d Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 16 May 2023 14:38:51 -0700 Subject: [PATCH 062/102] fix index out of bounds bug --- compiler/modules/bank.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index d3ca8e3a..561d68c3 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -865,8 +865,10 @@ class bank(design): driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] if self.has_rbl: driver_names = driver_names + ["rbl_wl"] - # rbl_wl in next two lines will be ignored by zip once driver_names is exhausted in the no rbl case - rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] + rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] + else: + rbl_wl_name = None + # rbl_wl in next line will be ignored by zip once driver_names is exhausted in the no rbl case for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]): # The mid guarantees we exit the input cell to the right. driver_wl_pin = self.port_address_inst[port].get_pin(driver_name) From 0b5039cc899c102b64f9735cd4153bd14de2e038 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 5 Jun 2023 12:08:22 -0700 Subject: [PATCH 063/102] make norbl bank test executable --- compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py diff --git a/compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py old mode 100644 new mode 100755 From 5b10f06be6ba779a8aeab5ce589ca702b44188e4 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 5 Jun 2023 15:26:11 -0700 Subject: [PATCH 064/102] place wl_en pin on wl drivers in absence of rbl_wl driver --- compiler/modules/port_address.py | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 89e05dd8..ffe605c7 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -131,14 +131,16 @@ class port_address(design): offset=driver_in_pos) # Route the RBL from the enable input + en_pin = self.wordline_driver_array_inst.get_pin("en") + if self.port == 0: + en_pos = en_pin.bc() + else: + en_pos = en_pin.uc() + if self.has_rbl: - en_pin = self.wordline_driver_array_inst.get_pin("en") - if self.port == 0: - en_pos = en_pin.bc() - else: - en_pos = en_pin.uc() rbl_in_pin = self.rbl_driver_inst.get_pin("A") rbl_in_pos = rbl_in_pin.center() + wl_en_offset = rbl_in_pos self.add_via_stack_center(from_layer=rbl_in_pin.layer, to_layer=en_pin.layer, @@ -147,9 +149,12 @@ class port_address(design): start=rbl_in_pos, end=en_pos, first_direction="V") - self.add_layout_pin_rect_center(text="wl_en", - layer=en_pin.layer, - offset=rbl_in_pos) + else: + wl_en_offset = en_pos + + self.add_layout_pin_rect_center(text="wl_en", + layer=en_pin.layer, + offset=wl_en_offset) def add_modules(self): From df827fbd3daa07a129aff3b2952f04f134be8106 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 5 Jun 2023 15:26:26 -0700 Subject: [PATCH 065/102] add norbl whole sram test --- .../20_sram_1bank_nomux_norbl_1rw_1r_test.py | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100755 compiler/tests/20_sram_1bank_nomux_norbl_1rw_1r_test.py diff --git a/compiler/tests/20_sram_1bank_nomux_norbl_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_norbl_1rw_1r_test.py new file mode 100755 index 00000000..f883398c --- /dev/null +++ b/compiler/tests/20_sram_1bank_nomux_norbl_1rw_1r_test.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class sram_1bank_nomux_norbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + + c.words_per_row=1 + OPTS.control_logic = "control_logic_delay" + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 157935c91540d1ede9e86bf4363267a0537b9b36 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 6 Jun 2023 12:21:04 -0700 Subject: [PATCH 066/102] update test/module imports related to delay control --- compiler/modules/control_logic_delay.py | 14 ++++++++------ compiler/modules/multi_delay_chain.py | 10 +++++----- .../16_control_logic_delay_multiport_test.py | 19 ++++++++++--------- .../tests/16_control_logic_delay_r_test.py | 16 ++++++++-------- .../tests/16_control_logic_delay_rw_test.py | 16 ++++++++-------- .../tests/16_control_logic_delay_w_test.py | 17 +++++++++-------- 6 files changed, 48 insertions(+), 44 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 43d6c1ed..8ba5b4f4 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -5,13 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from base import design -import debug -from sram_factory import factory + import math -from base import vector -from globals import OPTS -from base import logical_effort +from openram import debug +from openram import OPTS +from openram.base import design +from openram.base import vector +from openram.base import logical_effort +from openram.sram_factory import factory +from .control_logic_base import control_logic_base class control_logic_delay(design): diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index dcb38110..37664f1b 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -5,11 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from base import design -from base import vector -from globals import OPTS -from sram_factory import factory +from openram import debug +from openram.base import design +from openram.base import vector +from openram.sram_factory import factory +from openram import OPTS class multi_delay_chain(design): diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py index 590b2d7c..1cebd4b7 100755 --- a/compiler/tests/16_control_logic_delay_multiport_test.py +++ b/compiler/tests/16_control_logic_delay_multiport_test.py @@ -10,20 +10,21 @@ Run a regression test on a control_logic_delay """ -import unittest -from testutils import header,openram_test import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS -import globals -from globals import OPTS -from sram_factory import factory -import debug class control_logic_delay_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) # check control logic for multi-port OPTS.bitcell = "pbitcell" @@ -48,11 +49,11 @@ class control_logic_delay_test(openram_test): a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="r") self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main() diff --git a/compiler/tests/16_control_logic_delay_r_test.py b/compiler/tests/16_control_logic_delay_r_test.py index 1a184b39..4d46f5c9 100755 --- a/compiler/tests/16_control_logic_delay_r_test.py +++ b/compiler/tests/16_control_logic_delay_r_test.py @@ -6,31 +6,31 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for control_logic_r") a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="r") self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_delay_rw_test.py b/compiler/tests/16_control_logic_delay_rw_test.py index 2c2f6cf7..61933369 100755 --- a/compiler/tests/16_control_logic_delay_rw_test.py +++ b/compiler/tests/16_control_logic_delay_rw_test.py @@ -6,31 +6,31 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for control_logic_rw") a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/16_control_logic_delay_w_test.py b/compiler/tests/16_control_logic_delay_w_test.py index 989b190a..e97d3486 100755 --- a/compiler/tests/16_control_logic_delay_w_test.py +++ b/compiler/tests/16_control_logic_delay_w_test.py @@ -6,30 +6,31 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Testing sample for control_logic_w") a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="w") self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) From 9fdf8a8341054f8874432c9300a574e1b6f92e4a Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 6 Jun 2023 13:15:17 -0700 Subject: [PATCH 067/102] ommit rbl pins in sram_1bank when appropriate --- compiler/modules/sram_1bank.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index 6ad45ee3..9f26e2eb 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -50,6 +50,9 @@ class sram_1bank(design, verilog, lef): # Route a M3/M4 grid self.supply_stack = self.m3_stack + # delay control logic does not have RBLs + self.has_rbl = OPTS.control_logic != "control_logic_delay" + def add_pins(self): """ Add pins for entire SRAM. """ @@ -517,8 +520,9 @@ class sram_1bank(design, verilog, lef): for port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): temp.append("dout{0}[{1}]".format(port, bit)) - for port in self.all_ports: - temp.append("rbl_bl{0}".format(port)) + if self.has_rbl: + for port in self.all_ports: + temp.append("rbl_bl{0}".format(port)) for port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): temp.append("bank_din{0}_{1}".format(port, bit)) @@ -693,7 +697,7 @@ class sram_1bank(design, verilog, lef): if port in self.readwrite_ports: temp.append("web{}".format(port)) temp.append("clk{}".format(port)) - if OPTS.control_logic != "control_logic_delay": + if self.has_rbl: temp.append("rbl_bl{}".format(port)) # Outputs From a70dcc5c850f4366c0f97c921f44db7be0f49b6b Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 6 Jun 2023 14:43:18 -0700 Subject: [PATCH 068/102] reword comments in replica bitcell array module --- compiler/modules/replica_bitcell_array.py | 37 +++++++++++------------ 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index c079e448..b3661aff 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -16,11 +16,11 @@ from .bitcell_base_array import bitcell_base_array class replica_bitcell_array(bitcell_base_array): """ Creates a bitcell array of cols x rows and then adds the replica - and dummy columns and rows. Replica columns are on the left and + columns and dummy rows. Replica columns are on the left and right, respectively and connected to the given bitcell ports. - Dummy are the outside columns/rows with WL and BL tied to gnd. - Requires a regular bitcell array, replica bitcell, and dummy - bitcell (BL/BR disconnected). + Dummy rows are on the top and bottom passing through the RBL WLs. + Requires a regular bitcell array and (if using replica topology) + replica bitcell and dummy bitcell (BL/BR disconnected). """ def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""): super().__init__(name=name, rows=rows, cols=cols, column_offset=0) @@ -36,17 +36,21 @@ class replica_bitcell_array(bitcell_base_array): self.column_size = cols self.row_size = rows # This is how many RBLs are in all the arrays + # Even if the RBL is not placed in this array, the module still needs + # to place dummy rows with rbl wordlines so that they will have the same + # load as the regular wordlines (and so the arrays are the same size) if rbl is not None: self.rbl = rbl else: self.rbl = [0] * len(self.all_ports) - # This specifies which RBL to put on the left or right by port number - # This could be an empty list + # This specifies how many RBLs to put on the left by port number. + # For example, left_rbl = [0, 1] means there will be two + # RBLs on the left, one for port 0 and another for port 1. if left_rbl is not None: self.left_rbl = left_rbl else: self.left_rbl = [] - # This could be an empty list + # Similar to left_rbl but on the right side of the array if right_rbl is not None: self.right_rbl = right_rbl else: @@ -54,7 +58,7 @@ class replica_bitcell_array(bitcell_base_array): self.rbls = self.left_rbl + self.right_rbl debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl), - "Invalid number of RBLs for port configuration.") + "Cannot have more left + right RBLs than total RBLs") self.create_netlist() if not OPTS.netlist_only: @@ -78,19 +82,14 @@ class replica_bitcell_array(bitcell_base_array): self.replica_columns = {} for port in self.all_ports: + # We will always have self.rbl[0] dummy rows below the array + # for the replica wordlines. if port in self.left_rbl: - # TODO: merge comments from other commit... to fix these comments... - # We will always have self.rbl[0] rows of replica wordlines below - # the array. - # These go from the top (where the bitcell array starts ) down + # These go top down starting from the bottom of the bitcell array. replica_bit = self.rbl[0] - port - 1 column_offset = len(self.left_rbl) - elif port in self.right_rbl: - - # We will always have self.rbl[0] rows of replica wordlines below - # the array. - # These go from the bottom up + # These go bottom up starting from the top of the bitcell array. replica_bit = self.rbl[0] + self.row_size + port - 1 column_offset = len(self.left_rbl) + self.column_size + 1 else: @@ -102,7 +101,7 @@ class replica_bitcell_array(bitcell_base_array): column_offset=column_offset, replica_bit=replica_bit) - # Dummy row + # Dummy row (for replica wordlines) self.dummy_row = factory.create(module_type="dummy_array", cols=self.column_size, rows=1, @@ -133,7 +132,7 @@ class replica_bitcell_array(bitcell_base_array): self.add_pin("gnd", "GROUND") def add_bitline_pins(self): - # The bit is which port the RBL is for + # The bit represents which port the RBL is for for bit in self.rbls: for port in self.all_ports: self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit)) From b9492051b66756222d169b99515fbc797c8f3437 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 1 Aug 2022 12:08:34 -0700 Subject: [PATCH 069/102] use control_logic_base in control_logic_delay --- compiler/modules/control_logic_delay.py | 502 +----------------------- 1 file changed, 7 insertions(+), 495 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 8ba5b4f4..0d959e26 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -16,7 +16,7 @@ from openram.sram_factory import factory from .control_logic_base import control_logic_base -class control_logic_delay(design): +class control_logic_delay(control_logic_base): """ Dynamically generated Control logic for the total SRAM circuit. Variant: delay-based @@ -24,58 +24,7 @@ class control_logic_delay(design): def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""): """ Constructor """ - name = "control_logic_" + port_type - super().__init__(name) - debug.info(1, "Creating {}".format(name)) - self.add_comment("num_rows: {0}".format(num_rows)) - self.add_comment("words_per_row: {0}".format(words_per_row)) - self.add_comment("word_size {0}".format(word_size)) - - self.sram=sram - self.num_rows = num_rows - self.words_per_row = words_per_row - self.word_size = word_size - self.port_type = port_type - - if not spare_columns: - self.num_spare_cols = 0 - else: - self.num_spare_cols = spare_columns - - self.num_cols = word_size * words_per_row + self.num_spare_cols - self.num_words = num_rows * words_per_row - - self.enable_delay_chain_resizing = False - self.inv_parasitic_delay = logical_effort.pinv - - # Determines how much larger the sen delay should be. Accounts for possible error in model. - # FIXME: This should be made a parameter - self.wl_timing_tolerance = 1 - self.wl_stage_efforts = None - self.sen_stage_efforts = None - - if self.port_type == "rw": - self.num_control_signals = 2 - else: - self.num_control_signals = 1 - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def create_netlist(self): - self.setup_signal_busses() - self.add_pins() - self.add_modules() - self.create_instances() - - def create_layout(self): - """ Create layout and route between modules """ - self.place_instances() - self.route_all() - # self.add_lvs_correspondence_points() - self.add_boundary() - self.DRC_LVS() + super().__init__(num_rows, words_per_row, word_size, spare_columns, sram, port_type, name) def add_pins(self): """ Add the pins to the control logic module. """ @@ -152,100 +101,10 @@ class control_logic_delay(design): debug.check(OPTS.delay_chain_stages % 2, "Must use odd number of delay chain stages for inverting delay chain.") - self.multi_delay_chain=factory.create(module_type = "multi_delay_chain", + self.delay_chain=factory.create(module_type = "multi_delay_chain", fanout_list = 29 * [ OPTS.delay_chain_fanout_per_stage ], # TODO: generate this programatically pinout_list = [2, 12, 13, 15, 29]) # TODO: generate this list programatically - # not being used - def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): - """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" - from math import ceil - previous_delay_chain_delay = (previous_fanout + 1 + self.inv_parasitic_delay) * previous_stages - debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) - - # This can be anything >=2 - delay_fanout = 3 - # The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each - # inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value - required_delay = self.wl_delay * self.wl_timing_tolerance - (self.sen_delay - previous_delay_chain_delay) - debug.check(required_delay > 0, "Cannot size delay chain to have negative delay") - delay_per_stage = delay_fanout + 1 + self.inv_parasitic_delay - delay_stages = ceil(required_delay / delay_per_stage) - # force an even number of stages. - if delay_stages % 2 == 1: - delay_stages += 1 - # Fanout can be varied as well but is a little more complicated but potentially optimal. - debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay)) - return (delay_stages, delay_fanout) - - # not being used - def get_dynamic_delay_fanout_list(self, previous_stages, previous_fanout): - """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" - - previous_delay_per_stage = previous_fanout + 1 + self.inv_parasitic_delay - previous_delay_chain_delay = previous_delay_per_stage * previous_stages - debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) - - fanout_rise = fanout_fall = 2 # This can be anything >=2 - # The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each - # inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value - required_delay_fall = self.wl_delay_fall * self.wl_timing_tolerance - \ - (self.sen_delay_fall - previous_delay_chain_delay / 2) - required_delay_rise = self.wl_delay_rise * self.wl_timing_tolerance - \ - (self.sen_delay_rise - previous_delay_chain_delay / 2) - debug.info(2, - "Required delays from chain: fall={}, rise={}".format(required_delay_fall, - required_delay_rise)) - - # If the fanout is different between rise/fall by this amount. Stage algorithm is made more pessimistic. - WARNING_FANOUT_DIFF = 5 - stages_close = False - # The stages need to be equal (or at least a even number of stages with matching rise/fall delays) - while True: - stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall, - fanout_fall) - stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise, - fanout_rise) - debug.info(1, - "Fall stages={}, rise stages={}".format(stages_fall, - stages_rise)) - if abs(stages_fall - stages_rise) == 1 and not stages_close: - stages_close = True - safe_fanout_rise = fanout_rise - safe_fanout_fall = fanout_fall - - if stages_fall == stages_rise: - break - elif abs(stages_fall - stages_rise) == 1 and WARNING_FANOUT_DIFF < abs(fanout_fall - fanout_rise): - debug.info(1, "Delay chain fanouts between stages are large. Making chain size larger for safety.") - fanout_rise = safe_fanout_rise - fanout_fall = safe_fanout_fall - break - # There should also be a condition to make sure the fanout does not get too large. - # Otherwise, increase the fanout of delay with the most stages, calculate new stages - elif stages_fall>stages_rise: - fanout_fall+=1 - else: - fanout_rise+=1 - - total_stages = max(stages_fall, stages_rise) * 2 - debug.info(1, "New Delay chain: stages={}, fanout_rise={}, fanout_fall={}".format(total_stages, fanout_rise, fanout_fall)) - - # Creates interleaved fanout list of rise/fall delays. Assumes fall is the first stage. - stage_list = [fanout_fall if i % 2==0 else fanout_rise for i in range(total_stages)] - return stage_list - - # only used by above unused function - def calculate_stages_with_fixed_fanout(self, required_delay, fanout): - from math import ceil - # Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay - # 3 is the minimum delay per stage (with pinv=0). - if required_delay <= 3 + self.inv_parasitic_delay: - return 1 - delay_per_stage = fanout + 1 + self.inv_parasitic_delay - delay_stages = ceil(required_delay / delay_per_stage) - return delay_stages - def setup_signal_busses(self): """ Setup bus names, determine the size of the busses etc """ @@ -281,17 +140,6 @@ class control_logic_delay(design): self.supply_list = ["vdd", "gnd"] - def route_rails(self): - """ Add the input signal inverted tracks """ - height = self.control_logic_center.y - self.m2_pitch - # DFF spacing plus the power routing - offset = vector(self.ctrl_dff_array.width + self.m4_pitch, 0) - - self.input_bus = self.create_vertical_bus("m2", - offset, - self.internal_bus_list, - height) - def create_instances(self): """ Create all the instances """ self.create_dffs() @@ -307,21 +155,8 @@ class control_logic_delay(design): self.create_sen_row() self.create_pen_row() - def place_instances(self): - """ Place all the instances """ - # Keep track of all right-most instances to determine row boundary - # and add the vdd/gnd pins - self.row_end_inst = [] - - # Add the control flops on the left of the bus - self.place_dffs() - - # All of the control logic is placed to the right of the DFFs and bus - # as well as the power supply stripe - self.control_x_offset = self.ctrl_dff_array.width + self.internal_bus_width + self.m4_pitch - + def place_logic_rows(self): row = 0 - # Add the logic on the right of the bus self.place_clk_buf_row(row) row += 1 self.place_gated_clk_bar_row(row) @@ -341,25 +176,8 @@ class control_logic_delay(design): self.place_glitch2_row(row) row += 1 self.place_glitch3_row(row) - row += 1 - control_center_y = self.glitch3_nand_inst.uy() + self.m3_pitch - - # Delay chain always gets placed at row 4 - self.place_delay(4) - height = self.delay_inst.uy() - - # This offset is used for placement of the control logic in the SRAM level. - self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y) - - # Extra pitch on top and right - self.height = height + 2 * self.m1_pitch - # Max of modules or logic rows - self.width = max([inst.rx() for inst in self.row_end_inst]) - if (self.port_type == "rw") or (self.port_type == "r"): - # TODO: why not w ports here? Is this because there is no delay chain in w port? - self.width = max(self.delay_inst.rx(), self.width) - self.width += self.m2_pitch + self.control_center_y = self.glitch3_nand_inst.uy() + self.m3_pitch def route_all(self): """ Routing between modules """ @@ -381,24 +199,13 @@ class control_logic_delay(design): def create_delay(self): """ Create the delay chain """ self.delay_inst=self.add_inst(name="multi_delay_chain", - mod=self.multi_delay_chain) + mod=self.delay_chain) self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5", "vdd", "gnd"]) - def place_delay(self, row): - """ Place the delay chain """ - debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.") - - # It is flipped on X axis - y_off = row * self.and2.height + self.multi_delay_chain.height - - # Add to the right of the control rows and routing channel - offset = vector(0, y_off) - self.delay_inst.place(offset, mirror="MX") - def route_delay(self): # this is a bit of a hack because I would prefer to just name these pins delay in the layout # instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py - out_pins = ["out{}".format(str(pin)) for pin in self.multi_delay_chain.pinout_list] + out_pins = ["out{}".format(str(pin)) for pin in self.delay_chain.pinout_list] delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \ ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) @@ -447,109 +254,6 @@ class control_logic_delay(design): self.connect_vertical_bus(glitch3_map, self.glitch3_nand_inst, self.input_bus) - def create_clk_buf_row(self): - """ Create the multistage and gated clock buffer """ - self.clk_buf_inst = self.add_inst(name="clkbuf", - mod=self.clk_buf_driver) - self.connect_inst(["clk", "clk_buf", "vdd", "gnd"]) - - def place_clk_buf_row(self, row): - x_offset = self.control_x_offset - - x_offset = self.place_util(self.clk_buf_inst, x_offset, row) - - self.row_end_inst.append(self.clk_buf_inst) - - def route_clk_buf(self): - clk_pin = self.clk_buf_inst.get_pin("A") - clk_pos = clk_pin.center() - self.add_layout_pin_rect_center(text="clk", - layer="m2", - offset=clk_pos) - self.add_via_stack_center(from_layer=clk_pin.layer, - to_layer="m2", - offset=clk_pos) - - self.route_output_to_bus_jogged(self.clk_buf_inst, - "clk_buf") - self.connect_output(self.clk_buf_inst, "Z", "clk_buf") - - def create_gated_clk_bar_row(self): - self.clk_bar_inst = self.add_inst(name="inv_clk_bar", - mod=self.inv) - self.connect_inst(["clk_buf", "clk_bar", "vdd", "gnd"]) - - self.gated_clk_bar_inst = self.add_inst(name="and2_gated_clk_bar", - mod=self.and2) - self.connect_inst(["clk_bar", "cs", "gated_clk_bar", "vdd", "gnd"]) - - def place_gated_clk_bar_row(self, row): - x_offset = self.control_x_offset - - x_offset = self.place_util(self.clk_bar_inst, x_offset, row) - x_offset = self.place_util(self.gated_clk_bar_inst, x_offset, row) - - self.row_end_inst.append(self.gated_clk_bar_inst) - - def route_gated_clk_bar(self): - clkbuf_map = zip(["A"], ["clk_buf"]) - self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.input_bus) - - out_pin = self.clk_bar_inst.get_pin("Z") - out_pos = out_pin.center() - in_pin = self.gated_clk_bar_inst.get_pin("A") - in_pos = in_pin.center() - self.add_zjog(out_pin.layer, out_pos, in_pos) - self.add_via_stack_center(from_layer=out_pin.layer, - to_layer=in_pin.layer, - offset=in_pos) - - - # This is the second gate over, so it needs to be on M3 - clkbuf_map = zip(["B"], ["cs"]) - self.connect_vertical_bus(clkbuf_map, - self.gated_clk_bar_inst, - self.input_bus, - self.m2_stack[::-1]) - # The pin is on M1, so we need another via as well - b_pin = self.gated_clk_bar_inst.get_pin("B") - self.add_via_stack_center(from_layer=b_pin.layer, - to_layer="m3", - offset=b_pin.center()) - - # This is the second gate over, so it needs to be on M3 - self.route_output_to_bus_jogged(self.gated_clk_bar_inst, - "gated_clk_bar") - - def create_gated_clk_buf_row(self): - self.gated_clk_buf_inst = self.add_inst(name="and2_gated_clk_buf", - mod=self.and2) - self.connect_inst(["clk_buf", "cs", "gated_clk_buf", "vdd", "gnd"]) - - def place_gated_clk_buf_row(self, row): - x_offset = self.control_x_offset - - x_offset = self.place_util(self.gated_clk_buf_inst, x_offset, row) - - self.row_end_inst.append(self.gated_clk_buf_inst) - - def route_gated_clk_buf(self): - clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"]) - self.connect_vertical_bus(clkbuf_map, - self.gated_clk_buf_inst, - self.input_bus) - - clkbuf_map = zip(["Z"], ["gated_clk_buf"]) - self.connect_vertical_bus(clkbuf_map, - self.gated_clk_buf_inst, - self.input_bus, - self.m2_stack[::-1]) - # The pin is on M1, so we need another via as well - z_pin = self.gated_clk_buf_inst.get_pin("Z") - self.add_via_stack_center(from_layer=z_pin.layer, - to_layer="m2", - offset=z_pin.center()) - def create_wlen_row(self): self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf", mod=self.wl_en_and) @@ -700,195 +404,3 @@ class control_logic_delay(design): offset=b_pin.center()) self.connect_output(self.w_en_gate_inst, "Z", "w_en") - - def create_dffs(self): - self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", - mod=self.ctrl_dff_array) - inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list - self.connect_inst(inst_pins) - - def place_dffs(self): - self.ctrl_dff_inst.place(vector(0, 0)) - - def route_dffs(self): - if self.port_type == "rw": - dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) - elif self.port_type == "r": - dff_out_map = zip(["dout_bar_0"], ["cs"]) - else: - dff_out_map = zip(["dout_bar_0"], ["cs"]) - self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1]) - - # Connect the clock rail to the other clock rail - # by routing in the supply rail track to avoid channel conflicts - in_pos = self.ctrl_dff_inst.get_pin("clk").uc() - mid_pos = vector(in_pos.x, self.gated_clk_buf_inst.get_pin("vdd").cy() - self.m1_pitch) - rail_pos = vector(self.input_bus["clk_buf"].cx(), mid_pos.y) - self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos]) - self.add_via_center(layers=self.m1_stack, - offset=rail_pos) - - self.copy_layout_pin(self.ctrl_dff_inst, "din_0", "csb") - if (self.port_type == "rw"): - self.copy_layout_pin(self.ctrl_dff_inst, "din_1", "web") - - def get_offset(self, row): - """ Compute the y-offset and mirroring """ - y_off = row * self.and2.height - if row % 2: - y_off += self.and2.height - mirror="MX" - else: - mirror="R0" - - return (y_off, mirror) - - def connect_output(self, inst, pin_name, out_name): - """ Create an output pin on the right side from the pin of a given instance. """ - - out_pin = inst.get_pin(pin_name) - out_pos = out_pin.center() - right_pos = out_pos + vector(self.width - out_pin.cx(), 0) - - self.add_via_stack_center(from_layer=out_pin.layer, - to_layer="m2", - offset=out_pos) - self.add_layout_pin_segment_center(text=out_name, - layer="m2", - start=out_pos, - end=right_pos) - - def route_supplies(self): - """ Add vdd and gnd to the instance cells """ - - pin_layer = self.dff.get_pin("vdd").layer - supply_layer = self.supply_stack[2] - - - # FIXME: We should be able to replace this with route_vertical_pins instead - # but we may have to make the logic gates a separate module so that they - # have row pins of the same width - max_row_x_loc = max([inst.rx() for inst in self.row_end_inst]) - min_row_x_loc = self.control_x_offset - - vdd_pin_locs = [] - gnd_pin_locs = [] - - last_via = None - for inst in self.row_end_inst: - pins = inst.get_pins("vdd") - for pin in pins: - if pin.layer == pin_layer: - row_loc = pin.rc() - pin_loc = vector(max_row_x_loc, pin.rc().y) - vdd_pin_locs.append(pin_loc) - last_via = self.add_via_stack_center(from_layer=pin_layer, - to_layer=supply_layer, - offset=pin_loc, - min_area=True) - self.add_path(pin_layer, [row_loc, pin_loc]) - - pins = inst.get_pins("gnd") - for pin in pins: - if pin.layer == pin_layer: - row_loc = pin.rc() - pin_loc = vector(min_row_x_loc, pin.rc().y) - gnd_pin_locs.append(pin_loc) - last_via = self.add_via_stack_center(from_layer=pin_layer, - to_layer=supply_layer, - offset=pin_loc, - min_area=True) - self.add_path(pin_layer, [row_loc, pin_loc]) - - if last_via: - via_height=last_via.mod.second_layer_height - via_width=last_via.mod.second_layer_width - else: - via_height=None - via_width=0 - - min_y = min([x.y for x in vdd_pin_locs]) - max_y = max([x.y for x in vdd_pin_locs]) - bot_pos = vector(max_row_x_loc, min_y - 0.5 * via_height) - top_pos = vector(max_row_x_loc, max_y + 0.5 * via_height) - self.add_layout_pin_segment_center(text="vdd", - layer=supply_layer, - start=bot_pos, - end=top_pos, - width=via_width) - - min_y = min([x.y for x in gnd_pin_locs]) - max_y = max([x.y for x in gnd_pin_locs]) - bot_pos = vector(min_row_x_loc, min_y - 0.5 * via_height) - top_pos = vector(min_row_x_loc, max_y + 0.5 * via_height) - self.add_layout_pin_segment_center(text="gnd", - layer=supply_layer, - start=bot_pos, - end=top_pos, - width=via_width) - - self.copy_layout_pin(self.delay_inst, "gnd") - self.copy_layout_pin(self.delay_inst, "vdd") - - self.copy_layout_pin(self.ctrl_dff_inst, "gnd") - self.copy_layout_pin(self.ctrl_dff_inst, "vdd") - - # not used - def add_lvs_correspondence_points(self): - """ This adds some points for easier debugging if LVS goes wrong. - These should probably be turned off by default though, since extraction - will show these as ports in the extracted netlist. - """ - # pin=self.clk_inv1.get_pin("Z") - # self.add_label_pin(text="clk1_bar", - # layer="m1", - # offset=pin.ll(), - # height=pin.height(), - # width=pin.width()) - - # pin=self.clk_inv2.get_pin("Z") - # self.add_label_pin(text="clk2", - # layer="m1", - # offset=pin.ll(), - # height=pin.height(), - # width=pin.width()) - - pin=self.delay_inst.get_pin("out") - self.add_label_pin(text="out", - layer=pin.layer, - offset=pin.ll(), - height=pin.height(), - width=pin.width()) - - def graph_exclude_dffs(self): - """Exclude dffs from graph as they do not represent critical path""" - - self.graph_inst_exclude.add(self.ctrl_dff_inst) - if self.port_type=="rw" or self.port_type=="w": - self.graph_inst_exclude.add(self.w_en_gate_inst) - - def place_util(self, inst, x_offset, row): - """ Utility to place a row and compute the next offset """ - - (y_offset, mirror) = self.get_offset(row) - offset = vector(x_offset, y_offset) - inst.place(offset, mirror) - return x_offset + inst.width - - def route_output_to_bus_jogged(self, inst, name): - # Connect this at the bottom of the buffer - out_pin = inst.get_pin("Z") - out_pos = out_pin.center() - mid1 = vector(out_pos.x, out_pos.y - 0.3 * inst.mod.height) - mid2 = vector(self.input_bus[name].cx(), mid1.y) - bus_pos = self.input_bus[name].center() - self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos]) - self.add_via_stack_center(from_layer=out_pin.layer, - to_layer="m2", - offset=out_pos) - - def get_left_pins(self, name): - """ - Return the left side supply pins to connect to a vertical stripe. - """ - return(self.cntrl_dff_inst.get_pins(name) + self.delay_inst.get_pins(name)) From a48842ff72b12624494b870e33fdc46186382773 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 1 Aug 2022 15:41:09 -0700 Subject: [PATCH 070/102] fix code format issues from 00 test --- compiler/modules/control_logic_delay.py | 12 ++++++------ compiler/modules/multi_delay_chain.py | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 0d959e26..88f455d5 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -71,7 +71,7 @@ class control_logic_delay(control_logic_base): # wl_en_unbuf is the weak timing signal that feeds wl_en_driver self.wl_en_and = factory.create(module_type="pand2", - size=1, + size=1, height=dff_height) # w_en drives every write driver @@ -207,10 +207,10 @@ class control_logic_delay(control_logic_base): # instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py out_pins = ["out{}".format(str(pin)) for pin in self.delay_chain.pinout_list] delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \ - ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) - - self.connect_vertical_bus(delay_map, - self.delay_inst, + ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) + + self.connect_vertical_bus(delay_map, + self.delay_inst, self.input_bus, self.m2_stack[::-1]) @@ -244,7 +244,7 @@ class control_logic_delay(control_logic_base): x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row) self.row_end_inst.append(self.glitch3_nand_inst) - + def route_glitches(self): glitch2_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay4", "glitch2"]) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 37664f1b..acc7f03d 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -34,7 +34,7 @@ class multi_delay_chain(design): # number of inverters including any fanout loads. self.fanout_list = fanout_list self.rows = len(self.fanout_list) - + # defaults to signle output at end of delay chain if not pinout_list: self.pinout_list = [self.rows] # TODO: check for off-by-one here @@ -43,9 +43,9 @@ class multi_delay_chain(design): # TODO: would like to sort and check pinout list for valid format but don't have time now # Check pinout bounds - # debug.check(self.pinout_list[-1] <= self.rows, + # debug.check(self.pinout_list[-1] <= self.rows, # "Ouput pin cannot exceed delay chain length.") - # debug.check(self.pinout_list[0] > 0, + # debug.check(self.pinout_list[0] > 0, # "Delay chain output pin numbers must be positive") self.create_netlist() From afd3b782b93935ffd8aeec1218a1f6a1533ffdad Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 1 Aug 2022 16:00:22 -0700 Subject: [PATCH 071/102] remove cs_bar signal bus from all control logics --- compiler/modules/control_logic.py | 2 -- compiler/modules/control_logic_base.py | 2 -- 2 files changed, 4 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index ce1a7601..be8281ef 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -118,8 +118,6 @@ class control_logic(control_logic_base): # list of output control signals (for making a vertical bus) if self.port_type == "rw": self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] - elif self.port_type == "r": - self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"] else: self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space diff --git a/compiler/modules/control_logic_base.py b/compiler/modules/control_logic_base.py index c3509121..83739055 100644 --- a/compiler/modules/control_logic_base.py +++ b/compiler/modules/control_logic_base.py @@ -328,8 +328,6 @@ class control_logic_base(design): def route_dffs(self): if self.port_type == "rw": dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) - elif self.port_type == "r": - dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: dff_out_map = zip(["dout_bar_0"], ["cs"]) self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1]) From 9256ae8c00ace16463032d02731fefec7dc4ecc9 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 7 Jun 2023 16:04:54 -0700 Subject: [PATCH 072/102] fix typos and standardize multiport control logic tests --- .../tests/16_control_logic_delay_multiport_test.py | 13 +++++++------ compiler/tests/16_control_logic_multiport_test.py | 2 +- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py index 1cebd4b7..60bb9472 100755 --- a/compiler/tests/16_control_logic_delay_multiport_test.py +++ b/compiler/tests/16_control_logic_delay_multiport_test.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -#Copyright (c) 2016-2021 Regents of the University of California and The Board -#of Regents for the Oklahoma Agricultural and Mechanical College -#(acting for and on behalf of Oklahoma State University) -#All rights reserved. +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. # """ Run a regression test on a control_logic_delay @@ -12,7 +12,7 @@ Run a regression test on a control_logic_delay import sys, os import unittest -from testutils import * +from testutils import header,openram_test import openram from openram import debug @@ -33,7 +33,7 @@ class control_logic_delay_test(openram_test): OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 - debug.info(1, "Testing sample for control_logic_delay for multiport, only write control logic") + debug.info(1, "Testing sample for control_logic_delay for multiport, combined read-write control logic") a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="rw") self.local_check(a) @@ -51,6 +51,7 @@ class control_logic_delay_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index 600740ba..daf25578 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -33,7 +33,7 @@ class control_logic_test(openram_test): OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 - debug.info(1, "Testing sample for control_logic for multiport, only write control logic") + debug.info(1, "Testing sample for control_logic for multiport, combined read-write control logic") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw") self.local_check(a) From dcf95460d0b67a7fdc182356662076756e15440f Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 7 Jun 2023 16:09:18 -0700 Subject: [PATCH 073/102] sort sky130 skipped tests numerically --- compiler/tests/Makefile | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index 3ea5d299..d413cf94 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -82,6 +82,7 @@ BROKEN_STAMPS = \ scn4m_subm/19_single_bank_global_bitline_test.ok \ scn4m_subm/21_xyce_delay_test.ok \ sky130/01_library_test.ok \ + sky130/03_wire_test.ok \ sky130/04_column_mux_pbitcell_test.ok \ sky130/04_dummy_pbitcell_test.ok \ sky130/04_pbitcell_test.ok \ @@ -89,33 +90,19 @@ BROKEN_STAMPS = \ sky130/04_pand4_test.ok \ sky130/04_precharge_pbitcell_test.ok \ sky130/04_replica_pbitcell_test.ok \ - sky130/05_pbitcell_array_test.ok \ - sky130/05_bitcell_array_test.ok \ - sky130/05_bitcell_array_1rw_1r_test.ok \ - sky130/05_dummy_array_test.ok \ - sky130/07_column_mux_array_pbitcell_test.ok \ - sky130/19_pmulti_bank_test.ok \ - sky130/19_psingle_bank_test.ok \ - sky130/19_bank_select_pbitcell_test.ok \ - sky130/20_psram_1bank_4mux_1rw_1r_test.ok \ - sky130/22_psram_1bank_2mux_func_test.ok \ - sky130/22_psram_1bank_4mux_func_test.ok \ - sky130/22_psram_1bank_8mux_func_test.ok \ - sky130/22_psram_1bank_nomux_func_test.ok \ - sky130/23_lib_sram_linear_regression_test.ok \ - sky130/23_lib_sram_model_corners_test.ok \ - sky130/23_lib_sram_model_test.ok \ - sky130/23_lib_sram_prune_test.ok \ - sky130/23_lib_sram_test.ok \ - sky130/03_wire_test.ok \ sky130/04_dummy_pbitcell_1rw1r1w_test.ok \ sky130/04_dummy_pbitcell_1rw_test.ok \ sky130/04_replica_pbitcell_1rw1r1w_test.ok \ sky130/04_replica_pbitcell_1rw_test.ok \ + sky130/05_pbitcell_array_test.ok \ + sky130/05_bitcell_array_test.ok \ + sky130/05_bitcell_array_1rw_1r_test.ok \ + sky130/05_dummy_array_test.ok \ sky130/06_hierarchical_decoder_132row_test.ok \ sky130/06_hierarchical_decoder_512row_test.ok \ sky130/06_hierarchical_decoder_64row_test.ok \ sky130/06_hierarchical_decoder_pbitcell_test.ok \ + sky130/07_column_mux_array_pbitcell_test.ok \ sky130/10_write_driver_array_spare_cols_test.ok \ sky130/10_write_driver_array_wmask_spare_cols_test.ok \ sky130/14_capped_replica_bitcell_array_leftrbl_1rw_test.ok \ @@ -138,6 +125,10 @@ BROKEN_STAMPS = \ sky130/19_single_bank_nomux_test.ok \ sky130/19_single_bank_spare_cols_test.ok \ sky130/19_single_bank_wmask_test.ok \ + sky130/19_pmulti_bank_test.ok \ + sky130/19_psingle_bank_test.ok \ + sky130/19_bank_select_pbitcell_test.ok \ + sky130/20_psram_1bank_4mux_1rw_1r_test.ok \ sky130/20_sram_1bank_2mux_1rw_1r_spare_cols_test.ok \ sky130/20_sram_1bank_2mux_1w_1r_spare_cols_test.ok \ sky130/20_sram_1bank_2mux_global_test.ok \ @@ -155,6 +146,15 @@ BROKEN_STAMPS = \ sky130/21_ngspice_delay_test.ok \ sky130/21_regression_delay_test.ok \ sky130/21_xyce_delay_test.ok \ + sky130/22_psram_1bank_2mux_func_test.ok \ + sky130/22_psram_1bank_4mux_func_test.ok \ + sky130/22_psram_1bank_8mux_func_test.ok \ + sky130/22_psram_1bank_nomux_func_test.ok \ + sky130/23_lib_sram_linear_regression_test.ok \ + sky130/23_lib_sram_model_corners_test.ok \ + sky130/23_lib_sram_model_test.ok \ + sky130/23_lib_sram_prune_test.ok \ + sky130/23_lib_sram_test.ok \ sky130/25_verilog_multibank_test.ok \ sky130/25_verilog_sram_test.ok \ sky130/30_openram_back_end_library_test.ok \ From 973b5512f0be2af26eb7301551a1bc068f9330b6 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 7 Jun 2023 17:29:58 -0700 Subject: [PATCH 074/102] add new failing sky130 tests to skip list --- compiler/tests/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index d413cf94..d0a8ef6a 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -105,9 +105,13 @@ BROKEN_STAMPS = \ sky130/07_column_mux_array_pbitcell_test.ok \ sky130/10_write_driver_array_spare_cols_test.ok \ sky130/10_write_driver_array_wmask_spare_cols_test.ok \ + sky130/14_capped_replica_bitcell_array_dummies_1rw_test.ok \ sky130/14_capped_replica_bitcell_array_leftrbl_1rw_test.ok \ + sky130/14_capped_replica_bitcell_array_norbl_1rw_1r_test.ok \ sky130/14_capped_replica_bitcell_array_norbl_1rw_test.ok \ + sky130/14_replica_bitcell_array_dummies_1rw_test.ok \ sky130/14_replica_bitcell_array_leftrbl_1rw_test.ok \ + sky130/14_replica_bitcell_array_norbl_1rw_1r_test.ok \ sky130/14_replica_bitcell_array_norbl_1rw_test.ok \ sky130/14_replica_column_1rw_1r_test.ok \ sky130/14_replica_column_1rw_test.ok \ From 539dfc979a52fdd9d8f91f0763fc59d652cfcacc Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 7 Jun 2023 17:31:12 -0700 Subject: [PATCH 075/102] conform default behavior for sky130 custom modules to unit test --- .../custom/sky130_capped_replica_bitcell_array.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/technology/sky130/custom/sky130_capped_replica_bitcell_array.py b/technology/sky130/custom/sky130_capped_replica_bitcell_array.py index 86d9925c..ab79fce3 100644 --- a/technology/sky130/custom/sky130_capped_replica_bitcell_array.py +++ b/technology/sky130/custom/sky130_capped_replica_bitcell_array.py @@ -30,9 +30,19 @@ class sky130_capped_replica_bitcell_array(sky130_bitcell_base_array): self.add_comment("rows: {0} cols: {1}".format(rows, cols)) self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl)) + # This is how many RBLs are in all the arrays self.rbl = rbl - self.left_rbl = left_rbl - self.right_rbl = right_rbl + # This specifies which RBL to put on the left or right by port number + # This could be an empty list + if left_rbl is not None: + self.left_rbl = left_rbl + else: + self.left_rbl = [] + # This could be an empty list + if right_rbl is not None: + self.right_rbl = right_rbl + else: + self.right_rbl = [] self.create_netlist() if not OPTS.netlist_only: From a51b71d4609c121a9c71058bb405b40ceb9f60ce Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 8 Jun 2023 12:36:12 -0700 Subject: [PATCH 076/102] update copyright --- compiler/modules/control_logic_delay.py | 2 +- compiler/modules/multi_delay_chain.py | 2 +- compiler/tests/16_control_logic_delay_r_test.py | 2 +- compiler/tests/16_control_logic_delay_rw_test.py | 2 +- compiler/tests/16_control_logic_delay_w_test.py | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 88f455d5..d17821b7 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2023 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index acc7f03d..547ba36f 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -1,6 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2023 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/tests/16_control_logic_delay_r_test.py b/compiler/tests/16_control_logic_delay_r_test.py index 4d46f5c9..6479269b 100755 --- a/compiler/tests/16_control_logic_delay_r_test.py +++ b/compiler/tests/16_control_logic_delay_r_test.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2023 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/tests/16_control_logic_delay_rw_test.py b/compiler/tests/16_control_logic_delay_rw_test.py index 61933369..72f870e3 100755 --- a/compiler/tests/16_control_logic_delay_rw_test.py +++ b/compiler/tests/16_control_logic_delay_rw_test.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2023 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. diff --git a/compiler/tests/16_control_logic_delay_w_test.py b/compiler/tests/16_control_logic_delay_w_test.py index e97d3486..0a071f4e 100755 --- a/compiler/tests/16_control_logic_delay_w_test.py +++ b/compiler/tests/16_control_logic_delay_w_test.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California and The Board +# Copyright (c) 2016-2023 Regents of the University of California and The Board # of Regents for the Oklahoma Agricultural and Mechanical College # (acting for and on behalf of Oklahoma State University) # All rights reserved. From ce622952ef219e0e919a4e5a7db080c0e23ee959 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 8 Jun 2023 12:36:31 -0700 Subject: [PATCH 077/102] route rbl conditionally --- compiler/modules/sram_1bank.py | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index 9f26e2eb..73b48de0 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -1296,20 +1296,20 @@ class sram_1bank(design, verilog, lef): src_pin = self.control_logic_insts[port].get_pin(signal) dest_pin = self.bank_inst.get_pin(signal + "{}".format(port)) self.connect_vbus(src_pin, dest_pin) - """ - for port in self.all_ports: - # Only input (besides pins) is the replica bitline - src_pin = self.control_logic_insts[port].get_pin("rbl_bl") - dest_pin = self.bank_inst.get_pin("rbl_bl_{0}_{0}".format(port)) - self.add_wire(self.m3_stack, - [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()]) - self.add_via_stack_center(from_layer=src_pin.layer, - to_layer="m4", - offset=src_pin.center()) - self.add_via_stack_center(from_layer=dest_pin.layer, - to_layer="m3", - offset=dest_pin.center()) - """ + + if self.has_rbl: + for port in self.all_ports: + # Only input (besides pins) is the replica bitline + src_pin = self.control_logic_insts[port].get_pin("rbl_bl") + dest_pin = self.bank_inst.get_pin("rbl_bl_{0}_{0}".format(port)) + self.add_wire(self.m3_stack, + [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()]) + self.add_via_stack_center(from_layer=src_pin.layer, + to_layer="m4", + offset=src_pin.center()) + self.add_via_stack_center(from_layer=dest_pin.layer, + to_layer="m3", + offset=dest_pin.center()) def route_row_addr_dff(self): """ From 44ed72b50d8e901fd9f089e7a5826e0cc42adee7 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 8 Jun 2023 13:10:03 -0700 Subject: [PATCH 078/102] add has_rbl=True arg to tests --- .../18_port_address_16rows_1rw_1r_test.py | 2 +- compiler/tests/18_port_address_16rows_test.py | 2 +- .../18_port_address_256rows_1rw_1r_test.py | 2 +- .../tests/18_port_address_512rows_test.py | 2 +- .../tests/18_port_data_16mux_1rw_1r_test.py | 4 ++-- compiler/tests/18_port_data_16mux_test.py | 2 +- .../tests/18_port_data_2mux_1rw_1r_test.py | 4 ++-- compiler/tests/18_port_data_2mux_test.py | 2 +- .../tests/18_port_data_4mux_1rw_1r_test.py | 4 ++-- compiler/tests/18_port_data_4mux_test.py | 2 +- .../tests/18_port_data_8mux_1rw_1r_test.py | 4 ++-- compiler/tests/18_port_data_8mux_test.py | 2 +- .../tests/18_port_data_nomux_1rw_1r_test.py | 4 ++-- compiler/tests/18_port_data_nomux_test.py | 2 +- .../tests/18_port_data_spare_cols_test.py | 24 +++++++++---------- .../tests/18_port_data_wmask_1rw_1r_test.py | 24 +++++++++---------- compiler/tests/18_port_data_wmask_test.py | 24 +++++++++---------- 17 files changed, 55 insertions(+), 55 deletions(-) diff --git a/compiler/tests/18_port_address_16rows_1rw_1r_test.py b/compiler/tests/18_port_address_16rows_1rw_1r_test.py index dce0469f..b021f3e1 100755 --- a/compiler/tests/18_port_address_16rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_16rows_1rw_1r_test.py @@ -27,7 +27,7 @@ class port_address_1rw_1r_test(openram_test): openram.setup_bitcell() debug.info(1, "Port address 16 rows") - a = factory.create("port_address", cols=16, rows=16, port=0) + a = factory.create("port_address", cols=16, rows=16, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_address_16rows_test.py b/compiler/tests/18_port_address_16rows_test.py index 52d32f31..5453e85f 100755 --- a/compiler/tests/18_port_address_16rows_test.py +++ b/compiler/tests/18_port_address_16rows_test.py @@ -21,7 +21,7 @@ class port_address_test(openram_test): openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Port address 16 rows") - a = factory.create("port_address", cols=16, rows=16, port=0) + a = factory.create("port_address", cols=16, rows=16, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_address_256rows_1rw_1r_test.py b/compiler/tests/18_port_address_256rows_1rw_1r_test.py index 28d14b33..c7a5d5b1 100755 --- a/compiler/tests/18_port_address_256rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_256rows_1rw_1r_test.py @@ -27,7 +27,7 @@ class port_address_1rw_1r_test(openram_test): openram.setup_bitcell() debug.info(1, "Port address 256 rows") - a = factory.create("port_address", cols=256, rows=256, port=1) + a = factory.create("port_address", cols=256, rows=256, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_address_512rows_test.py b/compiler/tests/18_port_address_512rows_test.py index 5c1848b0..ff7070c2 100755 --- a/compiler/tests/18_port_address_512rows_test.py +++ b/compiler/tests/18_port_address_512rows_test.py @@ -21,7 +21,7 @@ class port_address_test(openram_test): openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Port address 512 rows") - a = factory.create("port_address", cols=256, rows=512, port=0) + a = factory.create("port_address", cols=256, rows=512, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py index b4b50323..863dc37d 100755 --- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py @@ -34,9 +34,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=16 c.recompute_sizes() debug.info(1, "Sixteen way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py index 66d4c4bf..e46d1107 100755 --- a/compiler/tests/18_port_data_16mux_test.py +++ b/compiler/tests/18_port_data_16mux_test.py @@ -38,7 +38,7 @@ class port_data_test(openram_test): c.words_per_row=16 c.recompute_sizes() debug.info(1, "Sixteen way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py index fc0d9243..a0f88622 100755 --- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py @@ -33,9 +33,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py index 8eb29615..2864baee 100755 --- a/compiler/tests/18_port_data_2mux_test.py +++ b/compiler/tests/18_port_data_2mux_test.py @@ -37,7 +37,7 @@ class port_data_test(openram_test): c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py index ac81e561..a19a9698 100755 --- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py @@ -33,9 +33,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py index c3eae434..42d40335 100755 --- a/compiler/tests/18_port_data_4mux_test.py +++ b/compiler/tests/18_port_data_4mux_test.py @@ -37,7 +37,7 @@ class port_data_test(openram_test): c.words_per_row=4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py index e57d12ef..add22345 100755 --- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py @@ -34,9 +34,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py index a8f82489..700a7b59 100755 --- a/compiler/tests/18_port_data_8mux_test.py +++ b/compiler/tests/18_port_data_8mux_test.py @@ -38,7 +38,7 @@ class port_data_test(openram_test): c.words_per_row=8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py index 8b887d9b..48b2ddee 100755 --- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py @@ -32,9 +32,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py index e479de1f..ceeff4cf 100755 --- a/compiler/tests/18_port_data_nomux_test.py +++ b/compiler/tests/18_port_data_nomux_test.py @@ -36,7 +36,7 @@ class port_data_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index 0db34da0..ad05c64c 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -28,14 +28,14 @@ class port_data_spare_cols_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words=32 c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words=64 @@ -43,7 +43,7 @@ class port_data_spare_cols_test(openram_test): c.num_spare_cols=3 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.word_size=2 @@ -52,7 +52,7 @@ class port_data_spare_cols_test(openram_test): c.num_spare_cols=4 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) OPTS.num_rw_ports = 0 @@ -64,27 +64,27 @@ class port_data_spare_cols_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words=32 c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words=64 c.words_per_row=4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.word_size=2 @@ -92,9 +92,9 @@ class port_data_spare_cols_test(openram_test): c.words_per_row=8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index b731a1d0..6aadd417 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -33,28 +33,28 @@ class port_data_wmask_1rw_1r_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 128 c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) OPTS.num_rw_ports = 0 @@ -66,27 +66,27 @@ class port_data_wmask_1rw_1r_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) # c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.word_size = 8 @@ -94,9 +94,9 @@ class port_data_wmask_1rw_1r_test(openram_test): c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index 3db910c1..30565ba8 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -37,28 +37,28 @@ class port_data_wmask_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 128 c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) OPTS.num_rw_ports = 0 @@ -70,27 +70,27 @@ class port_data_wmask_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) # c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.word_size = 8 @@ -98,9 +98,9 @@ class port_data_wmask_test(openram_test): c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() From 7048a072e2344c6e053d320555c2af02c5b7cb43 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 8 Jun 2023 13:16:27 -0700 Subject: [PATCH 079/102] add local/global array sky130 skipped tests --- compiler/tests/Makefile | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index d0a8ef6a..b05bbc26 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -117,9 +117,14 @@ BROKEN_STAMPS = \ sky130/14_replica_column_1rw_test.ok \ sky130/14_replica_pbitcell_1rw1r_array_test.ok \ sky130/14_replica_pbitcell_1rw_array_test.ok \ - sky130/15_global_bitcell_array_1rw_1r_test.ok \ - sky130/15_global_bitcell_array_test.ok \ - sky130/15_local_bitcell_array_test.ok \ + sky130/15_global_bitcell_array_norbl_1rw_1r_test.ok \ + sky130/15_global_bitcell_array_norbl_1rw_test.ok \ + sky130/15_global_bitcell_array_rbl_1rw_1r_test.ok \ + sky130/15_global_bitcell_array_rbl_1rw_test.ok \ + sky130/15_local_bitcell_array_dummies_1rw_test.ok \ + sky130/15_local_bitcell_array_leftrbl_1rw_test.ok \ + sky130/15_local_bitcell_array_norbl_1rw_1r_test.ok \ + sky130/15_local_bitcell_array_norbl_1rw_test.ok \ sky130/18_port_address_512rows_test.ok \ sky130/18_port_data_spare_cols_test.ok \ sky130/19_single_bank_2mux_test.ok \ From 854bff9dce418a26b01cd93f417563f751f3c2ca Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 8 Jun 2023 13:22:12 -0700 Subject: [PATCH 080/102] add norbl bank tests to sky130 skipped tests --- compiler/tests/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index b05bbc26..77df21ca 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -132,6 +132,8 @@ BROKEN_STAMPS = \ sky130/19_single_bank_8mux_test.ok \ sky130/19_single_bank_global_bitline_test.ok \ sky130/19_single_bank_nomux_test.ok \ + sky130/19_single_bank_nomux_norbl_1rw_1r_test.ok \ + sky130/19_single_bank_nomux_norbl_test.ok \ sky130/19_single_bank_spare_cols_test.ok \ sky130/19_single_bank_wmask_test.ok \ sky130/19_pmulti_bank_test.ok \ @@ -146,6 +148,7 @@ BROKEN_STAMPS = \ sky130/20_sram_1bank_2mux_wmask_test.ok \ sky130/20_sram_1bank_4mux_test.ok \ sky130/20_sram_1bank_8mux_test.ok \ + sky130/20_sram_1bank_nomux_norbl_1rw_1r_test.ok \ sky130/20_sram_1bank_nomux_spare_cols_test.ok \ sky130/20_sram_1bank_nomux_test.ok \ sky130/20_sram_1bank_nomux_wmask_test.ok \ From 266bcd9cf225def90ebd48c80c0ee57a8aa449a7 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Sun, 11 Jun 2023 14:52:26 -0700 Subject: [PATCH 081/102] consolidate failing xyce delay tests to one in skip list --- compiler/tests/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index 77df21ca..944eb71d 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -32,6 +32,7 @@ BROKEN_STAMPS = \ %/20_psram_1bank_2mux_test.ok \ %/21_hspice_delay_test.ok \ %/21_hspice_setuphold_test.ok \ + %/21_xyce_delay_test.ok \ %/22_psram_1bank_2mux_func_test.ok \ %/22_psram_1bank_4mux_func_test.ok \ %/22_psram_1bank_8mux_func_test.ok \ @@ -70,7 +71,6 @@ BROKEN_STAMPS = \ freepdk45/14_rom_array_test.ok \ freepdk45/16_rom_control_logic_test.ok \ freepdk45/19_rom_bank_test.ok \ - freepdk45/21_xyce_delay_test.ok \ scn4m_subm/06_rom_decoder_test.ok \ scn4m_subm/07_rom_column_mux_array_test.ok \ scn4m_subm/08_rom_decoder_buffer_array_test.ok \ @@ -80,7 +80,6 @@ BROKEN_STAMPS = \ scn4m_subm/16_rom_control_logic_test.ok \ scn4m_subm/19_rom_bank_test.ok \ scn4m_subm/19_single_bank_global_bitline_test.ok \ - scn4m_subm/21_xyce_delay_test.ok \ sky130/01_library_test.ok \ sky130/03_wire_test.ok \ sky130/04_column_mux_pbitcell_test.ok \ @@ -157,7 +156,6 @@ BROKEN_STAMPS = \ sky130/21_ngspice_delay_extra_rows_test.ok \ sky130/21_ngspice_delay_test.ok \ sky130/21_regression_delay_test.ok \ - sky130/21_xyce_delay_test.ok \ sky130/22_psram_1bank_2mux_func_test.ok \ sky130/22_psram_1bank_4mux_func_test.ok \ sky130/22_psram_1bank_8mux_func_test.ok \ From 96a1d400fab03a14188d3d5d6a0d0beda60bf665 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 12 Jun 2023 12:49:11 -0700 Subject: [PATCH 082/102] add single port bank test for norbl --- .../tests/20_sram_1bank_nomux_norbl_test.py | 58 +++++++++++++++++++ compiler/tests/Makefile | 1 + 2 files changed, 59 insertions(+) create mode 100755 compiler/tests/20_sram_1bank_nomux_norbl_test.py diff --git a/compiler/tests/20_sram_1bank_nomux_norbl_test.py b/compiler/tests/20_sram_1bank_nomux_norbl_test.py new file mode 100755 index 00000000..aa1704e6 --- /dev/null +++ b/compiler/tests/20_sram_1bank_nomux_norbl_test.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class sram_1bank_nomux_norbl_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + from openram import sram_config + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + + c.words_per_row=1 + OPTS.control_logic = "control_logic_delay" + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index 944eb71d..eb1907fd 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -148,6 +148,7 @@ BROKEN_STAMPS = \ sky130/20_sram_1bank_4mux_test.ok \ sky130/20_sram_1bank_8mux_test.ok \ sky130/20_sram_1bank_nomux_norbl_1rw_1r_test.ok \ + sky130/20_sram_1bank_nomux_norbl_test.ok \ sky130/20_sram_1bank_nomux_spare_cols_test.ok \ sky130/20_sram_1bank_nomux_test.ok \ sky130/20_sram_1bank_nomux_wmask_test.ok \ From fee90283b9e72d4f4bf5a7bffde5fec94eb946d4 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 12 Jun 2023 16:56:44 -0700 Subject: [PATCH 083/102] add spacing and a comment --- compiler/modules/control_logic_delay.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index d17821b7..09b0bf37 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -99,11 +99,12 @@ class control_logic_delay(control_logic_base): self.nand2 = factory.create(module_type="pnand2", height=dff_height) + # TODO: is this needed? Should this be used or inferred from the pinout_list? debug.check(OPTS.delay_chain_stages % 2, "Must use odd number of delay chain stages for inverting delay chain.") - self.delay_chain=factory.create(module_type = "multi_delay_chain", - fanout_list = 29 * [ OPTS.delay_chain_fanout_per_stage ], # TODO: generate this programatically - pinout_list = [2, 12, 13, 15, 29]) # TODO: generate this list programatically + self.delay_chain = factory.create(module_type="multi_delay_chain", + fanout_list=29 * [OPTS.delay_chain_fanout_per_stage], # TODO: generate this programatically + pinout_list=[2, 12, 13, 15, 29]) # TODO: generate this list programatically def setup_signal_busses(self): """ Setup bus names, determine the size of the busses etc """ From bf516a927db6a4f30d1fea56a83b22265568e713 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 13 Jun 2023 13:44:32 -0700 Subject: [PATCH 084/102] add skeleton for delay chain sizing --- compiler/modules/control_logic_delay.py | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 09b0bf37..49d91d3b 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -99,12 +99,16 @@ class control_logic_delay(control_logic_base): self.nand2 = factory.create(module_type="pnand2", height=dff_height) - # TODO: is this needed? Should this be used or inferred from the pinout_list? - debug.check(OPTS.delay_chain_stages % 2, - "Must use odd number of delay chain stages for inverting delay chain.") + self.calculate_delay_chain_size() self.delay_chain = factory.create(module_type="multi_delay_chain", - fanout_list=29 * [OPTS.delay_chain_fanout_per_stage], # TODO: generate this programatically - pinout_list=[2, 12, 13, 15, 29]) # TODO: generate this list programatically + fanout_list=self.delay_chain_fanout_list, + pinout_list=self.delay_chain_pinout_list) + + def calculate_delay_chain_size(self): + self.delay_chain_pinout_list = [] + # calculate it... dummy values for now + self.delay_chain_pinout_list = [2, 12, 13, 15, 29] + self.delay_chain_fanout_list = self.delay_chain_pinout_list[-1] * [OPTS.delay_chain_fanout_per_stage] def setup_signal_busses(self): """ Setup bus names, determine the size of the busses etc """ From dbc9de6c9ab5e1b122b7155662e78484ff858a4f Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 14 Jun 2023 17:10:07 -0700 Subject: [PATCH 085/102] implement relationship between delay pinouts --- compiler/modules/control_logic_delay.py | 26 ++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 49d91d3b..10ecba0f 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -105,9 +105,29 @@ class control_logic_delay(control_logic_base): pinout_list=self.delay_chain_pinout_list) def calculate_delay_chain_size(self): - self.delay_chain_pinout_list = [] - # calculate it... dummy values for now - self.delay_chain_pinout_list = [2, 12, 13, 15, 29] + """ + calculate the pinouts needed for the delay chain based on: + wl driver delay, bl minus vth delay, precharge duration + delays 1 & 2 need to be even for polarity + delays 3 - 5 need to be odd for polarity + """ + # TODO: calculate relevant delay constants + stage_delay = None + precharge_duration = None + bitline_vth_delay = None + + delays = [] + # hardcode 2 delay stages as keepout between p_en and wl_en + delays[1] = 2 + delays[3] = delays[1] + precharge_duration / stage_delay + # delays[2] can be any even value less than delays[3] + delays[2] = delays[3] - 1 + # delays[4] hardcoded 2 delays[ ]stages as keepout between p_en and wl_en + delays[4] = delays[3] + 2 + delays[5] = delays[4] + bitline_vth_delay / stage_delay + self.delay_chain_pinout_list = delays + # FIXME: fanout should be used to control delay chain height + # for now, use default/user-defined fanout constant self.delay_chain_fanout_list = self.delay_chain_pinout_list[-1] * [OPTS.delay_chain_fanout_per_stage] def setup_signal_busses(self): From 8992c0fb68eb9fb24de806452c99e81d2bbfa20d Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 20 Jun 2023 16:22:03 -0700 Subject: [PATCH 086/102] first approximation of delay values --- compiler/modules/control_logic_delay.py | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 10ecba0f..66b9fd05 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -111,20 +111,27 @@ class control_logic_delay(control_logic_base): delays 1 & 2 need to be even for polarity delays 3 - 5 need to be odd for polarity """ - # TODO: calculate relevant delay constants - stage_delay = None - precharge_duration = None - bitline_vth_delay = None + bitcell = factory.create(module_type=OPTS.bitcell) + inverter_stage_delay = logical_effort("inv", 1, 1, OPTS.delay_chain_fanout_per_stage, 1, True).get_absolute_delay() + # FIXME: bad approximation? + precharge_duration = logical_effort("precharge", 1, 1, bitcell.module_wire_c(), 1, True).get_absolute_delay() + # time for bitline to drop from vdd by threshold voltage + # FIXME: bad approximation? + bitline_vth_delay = precharge_duration / 2 delays = [] # hardcode 2 delay stages as keepout between p_en and wl_en delays[1] = 2 - delays[3] = delays[1] + precharge_duration / stage_delay + delays[3] = delays[1] + precharge_duration / inverter_stage_delay + # round up to nearest odd integer + delays[3] = 1 - (2 * ((1 - delays[3]) // 2)) # delays[2] can be any even value less than delays[3] delays[2] = delays[3] - 1 - # delays[4] hardcoded 2 delays[ ]stages as keepout between p_en and wl_en + # hardcode 2 delay stages as keepout between p_en and wl_en delays[4] = delays[3] + 2 - delays[5] = delays[4] + bitline_vth_delay / stage_delay + delays[5] = delays[4] + bitline_vth_delay / inverter_stage_delay + # round up to nearest odd integer + delays[5] = 1 - (2 * ((1 - delays[5]) // 2)) self.delay_chain_pinout_list = delays # FIXME: fanout should be used to control delay chain height # for now, use default/user-defined fanout constant From 3cd3a6341915d8cb0ee5351c77a855526e3a5a6f Mon Sep 17 00:00:00 2001 From: vlsida-bot Date: Sat, 24 Jun 2023 16:55:37 +0000 Subject: [PATCH 087/102] Bump version: 1.2.16 -> 1.2.17 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index f69752ab..b66183a6 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.2.16 +1.2.17 From 006eacd6d03db740e04af286047235a64b71eb82 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Sun, 25 Jun 2023 10:46:58 -0700 Subject: [PATCH 088/102] add pinout message output --- compiler/modules/multi_delay_chain.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index 547ba36f..57b7f153 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -21,11 +21,12 @@ class multi_delay_chain(design): Supplying an empty pinout list will result in an output only on the last stage. """ - def __init__(self, name, fanout_list, pinout_list = None): + def __init__(self, name, fanout_list, pinout_list=None): """init function""" super().__init__(name) - debug.info(1, "creating delay chain {0}".format(str(fanout_list))) + debug.info(1, "creating delay chain with {0}".format("fanouts: " + str(fanout_list) + " pinouts: " + str(pinout_list))) self.add_comment("fanouts: {0}".format(str(fanout_list))) + self.add_comment("pinouts: {0}".format(str(pinout_list))) # Two fanouts are needed so that we can route the vdd/gnd connections for f in fanout_list: From 28ea93bd0a15251c3bc08c53664a670ed3cea179 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Sun, 25 Jun 2023 11:03:10 -0700 Subject: [PATCH 089/102] convert 1-indexing to 0-indexing --- compiler/modules/control_logic_delay.py | 108 ++++++++++++------------ 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 66b9fd05..9d4e96ad 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -108,8 +108,8 @@ class control_logic_delay(control_logic_base): """ calculate the pinouts needed for the delay chain based on: wl driver delay, bl minus vth delay, precharge duration - delays 1 & 2 need to be even for polarity - delays 3 - 5 need to be odd for polarity + delays 0 & 1 need to be even for polarity + delays 2 - 4 need to be odd for polarity """ bitcell = factory.create(module_type=OPTS.bitcell) inverter_stage_delay = logical_effort("inv", 1, 1, OPTS.delay_chain_fanout_per_stage, 1, True).get_absolute_delay() @@ -119,19 +119,19 @@ class control_logic_delay(control_logic_base): # FIXME: bad approximation? bitline_vth_delay = precharge_duration / 2 - delays = [] + delays = [None] * 5 # hardcode 2 delay stages as keepout between p_en and wl_en - delays[1] = 2 - delays[3] = delays[1] + precharge_duration / inverter_stage_delay + delays[0] = 2 + delays[2] = delays[0] + precharge_duration / inverter_stage_delay # round up to nearest odd integer - delays[3] = 1 - (2 * ((1 - delays[3]) // 2)) - # delays[2] can be any even value less than delays[3] - delays[2] = delays[3] - 1 + delays[2] = 1 - (2 * ((1 - delays[2]) // 2)) + # delays[1] can be any even value less than delays[2] + delays[1] = delays[2] - 1 # hardcode 2 delay stages as keepout between p_en and wl_en - delays[4] = delays[3] + 2 - delays[5] = delays[4] + bitline_vth_delay / inverter_stage_delay + delays[3] = delays[2] + 2 + delays[4] = delays[3] + bitline_vth_delay / inverter_stage_delay # round up to nearest odd integer - delays[5] = 1 - (2 * ((1 - delays[5]) // 2)) + delays[4] = 1 - (2 * ((1 - delays[4]) // 2)) self.delay_chain_pinout_list = delays # FIXME: fanout should be used to control delay chain height # for now, use default/user-defined fanout constant @@ -153,9 +153,9 @@ class control_logic_delay(control_logic_base): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] + self.internal_bus_list = ["glitch1", "glitch2", "delay0", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] else: - self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] + self.internal_bus_list = ["glitch1", "glitch2", "delay0", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch @@ -205,11 +205,11 @@ class control_logic_delay(control_logic_base): row += 1 self.place_wlen_row(row) row += 1 - self.place_glitch2_row(row) + self.place_glitch1_row(row) row += 1 - self.place_glitch3_row(row) + self.place_glitch2_row(row) - self.control_center_y = self.glitch3_nand_inst.uy() + self.m3_pitch + self.control_center_y = self.glitch2_nand_inst.uy() + self.m3_pitch def route_all(self): """ Routing between modules """ @@ -232,36 +232,43 @@ class control_logic_delay(control_logic_base): """ Create the delay chain """ self.delay_inst=self.add_inst(name="multi_delay_chain", mod=self.delay_chain) - self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "delay0", "delay1", "delay2", "delay3", "delay4", "vdd", "gnd"]) def route_delay(self): # this is a bit of a hack because I would prefer to just name these pins delay in the layout # instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py out_pins = ["out{}".format(str(pin)) for pin in self.delay_chain.pinout_list] delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \ - ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) + ["gated_clk_buf", "delay0", "delay1", "delay2", "delay3", "delay4"]) self.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus, self.m2_stack[::-1]) - # glitch{1-3} are internal timing signals based on different in/out + # glitch{0-2} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration def create_glitches(self): + self.glitch0_nand_inst = self.add_inst(name="nand2_glitch0", + mod=self.nand2) + self.connect_inst(["delay0", "delay2", "glitch0", "vdd", "gnd"]) + self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1", mod=self.nand2) - self.connect_inst(["delay1", "delay3", "glitch1", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "delay3", "glitch1", "vdd", "gnd"]) self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2", mod=self.nand2) - self.connect_inst(["gated_clk_buf", "delay4", "glitch2", "vdd", "gnd"]) + self.connect_inst(["delay1", "delay4", "glitch2", "vdd", "gnd"]) - self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3", - mod=self.nand2) - self.connect_inst(["delay2", "delay5", "glitch3", "vdd", "gnd"]) + # glitch0 is placed in place_pen_row() - # glitch1 is placed in place_pen_row() + def place_glitch1_row(self, row): + x_offset = self.control_x_offset + + x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row) + + self.row_end_inst.append(self.glitch1_nand_inst) def place_glitch2_row(self, row): x_offset = self.control_x_offset @@ -270,26 +277,19 @@ class control_logic_delay(control_logic_base): self.row_end_inst.append(self.glitch2_nand_inst) - def place_glitch3_row(self, row): - x_offset = self.control_x_offset - - x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row) - - self.row_end_inst.append(self.glitch3_nand_inst) - def route_glitches(self): - glitch2_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay4", "glitch2"]) + glitch1_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay3", "glitch1"]) + + self.connect_vertical_bus(glitch1_map, self.glitch1_nand_inst, self.input_bus) + + glitch2_map = zip(["A", "B", "Z"], ["delay1", "delay4", "glitch2"]) self.connect_vertical_bus(glitch2_map, self.glitch2_nand_inst, self.input_bus) - glitch3_map = zip(["A", "B", "Z"], ["delay2", "delay5", "glitch3"]) - - self.connect_vertical_bus(glitch3_map, self.glitch3_nand_inst, self.input_bus) - def create_wlen_row(self): self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf", mod=self.wl_en_and) - self.connect_inst(["cs", "glitch2", "wl_en_unbuf", "vdd", "gnd"]) + self.connect_inst(["cs", "glitch1", "wl_en_unbuf", "vdd", "gnd"]) self.wl_en_driver_inst=self.add_inst(name="buf_wl_en", mod=self.wl_en_driver) @@ -304,7 +304,7 @@ class control_logic_delay(control_logic_base): self.row_end_inst.append(self.wl_en_driver_inst) def route_wlen(self): - in_map = zip(["A", "B"], ["cs", "glitch2"]) + in_map = zip(["A", "B"], ["cs", "glitch1"]) self.connect_vertical_bus(in_map, self.wl_en_unbuf_and_inst, self.input_bus) out_pin = self.wl_en_unbuf_and_inst.get_pin("Z") @@ -321,21 +321,21 @@ class control_logic_delay(control_logic_base): def create_pen_row(self): self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar", mod=self.p_en_bar_driver) - self.connect_inst(["glitch1", "p_en_bar", "vdd", "gnd"]) + self.connect_inst(["glitch0", "p_en_bar", "vdd", "gnd"]) def place_pen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row) + x_offset = self.place_util(self.glitch0_nand_inst, x_offset, row) x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row) self.row_end_inst.append(self.p_en_bar_driver_inst) def route_pen(self): - in_map = zip(["A", "B"], ["delay1", "delay3"]) - self.connect_vertical_bus(in_map, self.glitch1_nand_inst, self.input_bus) + in_map = zip(["A", "B"], ["delay0", "delay2"]) + self.connect_vertical_bus(in_map, self.glitch0_nand_inst, self.input_bus) - out_pin = self.glitch1_nand_inst.get_pin("Z") # same code here as wl_en, refactor? + out_pin = self.glitch0_nand_inst.get_pin("Z") # same code here as wl_en, refactor? out_pos = out_pin.center() in_pin = self.p_en_bar_driver_inst.get_pin("A") in_pos = in_pin.center() @@ -355,7 +355,7 @@ class control_logic_delay(control_logic_base): self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3) - self.connect_inst(["glitch3", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) + self.connect_inst(["glitch2", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) def place_sen_row(self, row): x_offset = self.control_x_offset @@ -371,15 +371,15 @@ class control_logic_delay(control_logic_base): else: input_name = "cs" - sen_map = zip(["A", "B", "C"], ["glitch3", "gated_clk_bar", input_name]) + sen_map = zip(["A", "B", "C"], ["glitch2", "gated_clk_bar", input_name]) self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus) self.connect_output(self.s_en_gate_inst, "Z", "s_en") def create_wen_row(self): - self.glitch3_bar_inv_inst = self.add_inst(name="inv_glitch3_bar", + self.glitch2_bar_inv_inst = self.add_inst(name="inv_glitch2_bar", mod=self.inv) - self.connect_inst(["glitch3", "glitch3_bar", "vdd", "gnd"]) + self.connect_inst(["glitch2", "glitch2_bar", "vdd", "gnd"]) if self.port_type == "rw": input_name = "we" @@ -388,21 +388,21 @@ class control_logic_delay(control_logic_base): self.w_en_gate_inst = self.add_inst(name="and_w_en", mod=self.wen_and) - self.connect_inst([input_name, "glitch2", "glitch3_bar", "w_en", "vdd", "gnd"]) + self.connect_inst([input_name, "glitch1", "glitch2_bar", "w_en", "vdd", "gnd"]) def place_wen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) + x_offset = self.place_util(self.glitch2_bar_inv_inst, x_offset, row) x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) self.row_end_inst.append(self.w_en_gate_inst) def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted - glitch3_map = zip(["A"], ["glitch3"]) - self.connect_vertical_bus(glitch3_map, self.glitch3_bar_inv_inst, self.input_bus) + glitch2_map = zip(["A"], ["glitch2"]) + self.connect_vertical_bus(glitch2_map, self.glitch2_bar_inv_inst, self.input_bus) - out_pin = self.glitch3_bar_inv_inst.get_pin("Z") + out_pin = self.glitch2_bar_inv_inst.get_pin("Z") out_pos = out_pin.center() in_pin = self.w_en_gate_inst.get_pin("C") in_pos = in_pin.center() @@ -418,7 +418,7 @@ class control_logic_delay(control_logic_base): input_name = "cs" # This is the second gate over, so it needs to be on M3 - wen_map = zip(["A", "B"], [input_name, "glitch2"]) + wen_map = zip(["A", "B"], [input_name, "glitch1"]) self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus, From 14f8008c4f4c29e339abf34b7cb76f8ac4e5a60f Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 26 Jun 2023 15:37:42 -0700 Subject: [PATCH 090/102] Update index.md fix typo in index.md --- docs/source/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/index.md b/docs/source/index.md index 8efb19c6..a1f7079a 100644 --- a/docs/source/index.md +++ b/docs/source/index.md @@ -110,7 +110,7 @@ Commercial tools (optional): * Michael Grimes * Jennifer Sowash * Jesse Cirimelli-Low - https://www.youtube.com/watch?v=rd5j8mG24H4&t=0s + * Many other past students: * Jeff Butera * Tom Golubev From 3620d56790a7153f20a509a6e804af518cde763b Mon Sep 17 00:00:00 2001 From: vlsida-bot Date: Tue, 27 Jun 2023 00:22:04 +0000 Subject: [PATCH 091/102] Bump version: 1.2.17 -> 1.2.18 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index b66183a6..591bdbcd 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.2.17 +1.2.18 From 91694fdae3070f5a44d6c87e75f65e6cc800b613 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 28 Jun 2023 14:05:42 -0700 Subject: [PATCH 092/102] add fixme note for unit conversion --- compiler/base/wire_spice_model.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/base/wire_spice_model.py b/compiler/base/wire_spice_model.py index b7001965..55ef040d 100644 --- a/compiler/base/wire_spice_model.py +++ b/compiler/base/wire_spice_model.py @@ -18,6 +18,7 @@ class wire_spice_model(): def cal_wire_c(self, wire_length, wire_width): from openram.tech import spice # Convert the F/um^2 to fF/um^2 then multiple by width and length + # FIXME: shouldn't it be 1e15? total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width wire_c = total_c / self.lump_num return wire_c From e1865083d767a708e85a2ace85de28554caccdf8 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Thu, 29 Jun 2023 14:44:42 -0700 Subject: [PATCH 093/102] incomplete work on improved delay modeling --- compiler/modules/control_logic_delay.py | 39 ++++++++++++++++--------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 9d4e96ad..c287a7d9 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -11,7 +11,8 @@ from openram import debug from openram import OPTS from openram.base import design from openram.base import vector -from openram.base import logical_effort +from openram.base import logical_effort, convert_farad_to_relative_c +from openram.tech import drc, spice from openram.sram_factory import factory from .control_logic_base import control_logic_base @@ -69,7 +70,7 @@ class control_logic_delay(control_logic_base): size_list=size_list, height=dff_height) - # wl_en_unbuf is the weak timing signal that feeds wl_en_driver + # this is the weak timing signal that feeds wl_en_driver self.wl_en_and = factory.create(module_type="pand2", size=1, height=dff_height) @@ -99,39 +100,51 @@ class control_logic_delay(control_logic_base): self.nand2 = factory.create(module_type="pnand2", height=dff_height) - self.calculate_delay_chain_size() + self.compute_delay_chain_size() self.delay_chain = factory.create(module_type="multi_delay_chain", fanout_list=self.delay_chain_fanout_list, pinout_list=self.delay_chain_pinout_list) - def calculate_delay_chain_size(self): + def compute_delay_chain_size(self): """ - calculate the pinouts needed for the delay chain based on: - wl driver delay, bl minus vth delay, precharge duration + calculate the pinouts needed for the delay chain based on + wordline, bitline, and precharge delays delays 0 & 1 need to be even for polarity delays 2 - 4 need to be odd for polarity """ bitcell = factory.create(module_type=OPTS.bitcell) + # 2 access tx gate per cell + wordline_cap = OPTS.num_cols * (2 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * bitcell.width * drc("minwidth_m1")) + wordline_cap = convert_farad_to_relative_c(wordline_cap) + # 1 access tx drain per cell + bitline_cap = OPTS.num_rows * (spice["min_tx_drain_c"] + spice["wire_unit_c"] * 1e15 * bitcell.height * drc("minwidth_m2")) + bitline_cap = convert_farad_to_relative_c(bitline_cap) + inverter_stage_delay = logical_effort("inv", 1, 1, OPTS.delay_chain_fanout_per_stage, 1, True).get_absolute_delay() - # FIXME: bad approximation? - precharge_duration = logical_effort("precharge", 1, 1, bitcell.module_wire_c(), 1, True).get_absolute_delay() + # model precharge as a minimum sized inverter with the bitline as its load + # FIXME: need to add p_en line and tx delays :/ + precharge_delay = logical_effort("precharge", 1, 1, bitline_cap, 1, True).get_absolute_delay() + # size is a pessimistic version of wordline_driver module's FO4 sizing + # FIXME: need to add other gates to this and also to everything else smh + wordline_delay = logical_effort("wordline", int(OPTS.num_cols / 4) + 1, 1, wordline_cap, 1, True).get_absolute_delay() # time for bitline to drop from vdd by threshold voltage # FIXME: bad approximation? - bitline_vth_delay = precharge_duration / 2 + bitline_vth_delay = precharge_delay * .5 + sense_enable_delay = wordline_delay + bitline_vth_delay delays = [None] * 5 # hardcode 2 delay stages as keepout between p_en and wl_en delays[0] = 2 - delays[2] = delays[0] + precharge_duration / inverter_stage_delay + delays[2] = delays[0] + precharge_delay / inverter_stage_delay # round up to nearest odd integer - delays[2] = 1 - (2 * ((1 - delays[2]) // 2)) + delays[2] = int(1 - (2 * ((1 - delays[2]) // 2))) # delays[1] can be any even value less than delays[2] delays[1] = delays[2] - 1 # hardcode 2 delay stages as keepout between p_en and wl_en delays[3] = delays[2] + 2 - delays[4] = delays[3] + bitline_vth_delay / inverter_stage_delay + delays[4] = delays[3] + sense_enable_delay / inverter_stage_delay # round up to nearest odd integer - delays[4] = 1 - (2 * ((1 - delays[4]) // 2)) + delays[4] = int(1 - (2 * ((1 - delays[4]) // 2))) self.delay_chain_pinout_list = delays # FIXME: fanout should be used to control delay chain height # for now, use default/user-defined fanout constant From 5235cf966790bcab49aeac3816b8f01d9f12fdd2 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 3 Jul 2023 17:00:19 -0700 Subject: [PATCH 094/102] model p_en and wl_en delays in delay chain sizing --- compiler/modules/control_logic_delay.py | 34 +++++++++++++++++-------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index c287a7d9..737a4199 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -113,37 +113,49 @@ class control_logic_delay(control_logic_base): delays 2 - 4 need to be odd for polarity """ bitcell = factory.create(module_type=OPTS.bitcell) + # TODO: check that these spice values are up to date in tech files and if not figure out how to update them # 2 access tx gate per cell - wordline_cap = OPTS.num_cols * (2 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * bitcell.width * drc("minwidth_m1")) + wordline_cap = self.num_cols * (2 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * bitcell.width * drc("minwidth_m1")) wordline_cap = convert_farad_to_relative_c(wordline_cap) # 1 access tx drain per cell - bitline_cap = OPTS.num_rows * (spice["min_tx_drain_c"] + spice["wire_unit_c"] * 1e15 * bitcell.height * drc("minwidth_m2")) + bitline_cap = self.num_rows * (spice["min_tx_drain_c"] + spice["wire_unit_c"] * 1e15 * bitcell.height * drc("minwidth_m2")) bitline_cap = convert_farad_to_relative_c(bitline_cap) + # 3 pmos gate per cell + pen_cap = self.num_cols * (3 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * bitcell.width * drc("minwidth_m1")) + pen_cap = convert_farad_to_relative_c(pen_cap) + # number of stages in the p_en driver + pen_stages = self.p_en_bar_driver.num_stages inverter_stage_delay = logical_effort("inv", 1, 1, OPTS.delay_chain_fanout_per_stage, 1, True).get_absolute_delay() # model precharge as a minimum sized inverter with the bitline as its load - # FIXME: need to add p_en line and tx delays :/ precharge_delay = logical_effort("precharge", 1, 1, bitline_cap, 1, True).get_absolute_delay() + # exponential horn delay from logical effort paper (converted to absolute delay) + pen_signal_delay = logical_effort.tau * (pen_stages * (pen_cap ** (1 / pen_stages) + 1)) # size is a pessimistic version of wordline_driver module's FO4 sizing - # FIXME: need to add other gates to this and also to everything else smh - wordline_delay = logical_effort("wordline", int(OPTS.num_cols / 4) + 1, 1, wordline_cap, 1, True).get_absolute_delay() + wordline_driver_size = int(OPTS.num_cols / 4) + 1 + wordline_delay = logical_effort("wordline", wordline_driver_size, 1, wordline_cap, 1, True).get_absolute_delay() + # wl_en driver is always two stages so add each independently? + wlen_signal_delay = logical_effort("wlen_driver", self.wl_en_driver.size_list[0], 1, self.wl_en_driver.size_list[1], 1, True) + wlen_signal_delay += logical_effort("wlen_driver", self.wl_en_driver.size_list[1], 1, wordline_driver_size * self.num_rows, 1, True) + wlen_signal_delay = wlen_signal_delay.get_absolute_delay() # time for bitline to drop from vdd by threshold voltage # FIXME: bad approximation? bitline_vth_delay = precharge_delay * .5 sense_enable_delay = wordline_delay + bitline_vth_delay delays = [None] * 5 - # hardcode 2 delay stages as keepout between p_en and wl_en - delays[0] = 2 - delays[2] = delays[0] + precharge_delay / inverter_stage_delay + # keepout between p_en rising and wl_en falling + delays[0] = int((wlen_signal_delay + wordline_delay) / inverter_stage_delay) # could possibly subtract pen_signal_delay? + delays[0] += delays[0] % 2 + delays[2] = delays[0] + (pen_signal_delay + precharge_delay) / inverter_stage_delay # round up to nearest odd integer delays[2] = int(1 - (2 * ((1 - delays[2]) // 2))) # delays[1] can be any even value less than delays[2] delays[1] = delays[2] - 1 - # hardcode 2 delay stages as keepout between p_en and wl_en - delays[3] = delays[2] + 2 + # keepout between p_en falling and wl_en rising + delays[3] = delays[2] + pen_signal_delay / inverter_stage_delay + delays[3] = int(1 - (2 * ((1 - delays[3]) // 2))) delays[4] = delays[3] + sense_enable_delay / inverter_stage_delay - # round up to nearest odd integer delays[4] = int(1 - (2 * ((1 - delays[4]) // 2))) self.delay_chain_pinout_list = delays # FIXME: fanout should be used to control delay chain height From b4a9784835dfe36e08eb26900f9560d25c1a57bb Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Jul 2023 12:17:48 -0700 Subject: [PATCH 095/102] model vth delay swing delay --- compiler/modules/control_logic_delay.py | 31 +++++++++++++------------ 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 737a4199..b5bbe4b4 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -115,14 +115,16 @@ class control_logic_delay(control_logic_base): bitcell = factory.create(module_type=OPTS.bitcell) # TODO: check that these spice values are up to date in tech files and if not figure out how to update them # 2 access tx gate per cell - wordline_cap = self.num_cols * (2 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * bitcell.width * drc("minwidth_m1")) - wordline_cap = convert_farad_to_relative_c(wordline_cap) + wordline_area = bitcell.width * drc("minwidth_m1") + wordline_cap_ff = self.num_cols * (2 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * wordline_area) + wordline_cap = convert_farad_to_relative_c(wordline_cap_ff) # 1 access tx drain per cell - bitline_cap = self.num_rows * (spice["min_tx_drain_c"] + spice["wire_unit_c"] * 1e15 * bitcell.height * drc("minwidth_m2")) - bitline_cap = convert_farad_to_relative_c(bitline_cap) + bitline_area = bitcell.height * drc("minwidth_m2") + bitline_cap_ff = self.num_rows * (spice["min_tx_drain_c"] + spice["wire_unit_c"] * 1e15 * bitline_area) + bitline_cap = convert_farad_to_relative_c(bitline_cap_ff) # 3 pmos gate per cell - pen_cap = self.num_cols * (3 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * bitcell.width * drc("minwidth_m1")) - pen_cap = convert_farad_to_relative_c(pen_cap) + pen_cap_ff = self.num_cols * (3 * spice["min_tx_gate_c"] + spice["wire_unit_c"] * 1e15 * wordline_area) + pen_cap = convert_farad_to_relative_c(pen_cap_ff) # number of stages in the p_en driver pen_stages = self.p_en_bar_driver.num_stages @@ -132,16 +134,15 @@ class control_logic_delay(control_logic_base): # exponential horn delay from logical effort paper (converted to absolute delay) pen_signal_delay = logical_effort.tau * (pen_stages * (pen_cap ** (1 / pen_stages) + 1)) # size is a pessimistic version of wordline_driver module's FO4 sizing - wordline_driver_size = int(OPTS.num_cols / 4) + 1 + wordline_driver_size = int(self.num_cols / 4) + 1 wordline_delay = logical_effort("wordline", wordline_driver_size, 1, wordline_cap, 1, True).get_absolute_delay() # wl_en driver is always two stages so add each independently? - wlen_signal_delay = logical_effort("wlen_driver", self.wl_en_driver.size_list[0], 1, self.wl_en_driver.size_list[1], 1, True) - wlen_signal_delay += logical_effort("wlen_driver", self.wl_en_driver.size_list[1], 1, wordline_driver_size * self.num_rows, 1, True) - wlen_signal_delay = wlen_signal_delay.get_absolute_delay() - # time for bitline to drop from vdd by threshold voltage - # FIXME: bad approximation? - bitline_vth_delay = precharge_delay * .5 - sense_enable_delay = wordline_delay + bitline_vth_delay + wlen_signal_delay = logical_effort("wlen_driver", self.wl_en_driver.size_list[0], 1, self.wl_en_driver.size_list[1], 1, True).get_absolute_delay() + wlen_signal_delay += logical_effort("wlen_driver", self.wl_en_driver.size_list[1], 1, wordline_driver_size * self.num_rows, 1, True).get_absolute_delay() + # time for bitline to drop from vdd by threshold voltage once wordline enabled + bitline_vth_swing = (spice["nom_supply_voltage"] - spice["nom_threshold"]) / spice["nom_supply_voltage"] + bitline_vth_delay = abs(math.log(1 - bitline_vth_swing)) * spice["wire_unit_r"] * bitline_area * bitline_cap_ff + print("delays: delay_stage {} precharge {} pen {} wl {} wlen {} vth {}".format(inverter_stage_delay, precharge_delay, pen_signal_delay, wordline_delay, wlen_signal_delay, bitline_vth_delay)) delays = [None] * 5 # keepout between p_en rising and wl_en falling @@ -155,7 +156,7 @@ class control_logic_delay(control_logic_base): # keepout between p_en falling and wl_en rising delays[3] = delays[2] + pen_signal_delay / inverter_stage_delay delays[3] = int(1 - (2 * ((1 - delays[3]) // 2))) - delays[4] = delays[3] + sense_enable_delay / inverter_stage_delay + delays[4] = delays[3] + (wlen_signal_delay + wordline_delay + bitline_vth_delay) / inverter_stage_delay delays[4] = int(1 - (2 * ((1 - delays[4]) // 2))) self.delay_chain_pinout_list = delays # FIXME: fanout should be used to control delay chain height From d65ccfcc95b9025d23d0a75ef05dc61e443a0f08 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Jul 2023 13:17:46 -0700 Subject: [PATCH 096/102] fix column mux without rbl start_bit to 0 --- compiler/modules/port_data.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index cefdb871..aef91b7c 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -543,7 +543,7 @@ class port_data(design): if self.col_addr_size==0: return - start_bit = 1 if self.port == 0 else 0 + start_bit = 1 if self.port == 0 and self.has_rbl else 0 self.connect_bitlines(inst1=self.column_mux_array_inst, inst2=self.precharge_array_inst, From 468c972acb23036062c69712c9759c2ffa2d2c96 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Jul 2023 16:08:38 -0700 Subject: [PATCH 097/102] add optional guard band to delay chain sizing --- compiler/modules/control_logic_delay.py | 9 +++++++-- compiler/options.py | 8 ++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index b5bbe4b4..b980d9eb 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -142,21 +142,26 @@ class control_logic_delay(control_logic_base): # time for bitline to drop from vdd by threshold voltage once wordline enabled bitline_vth_swing = (spice["nom_supply_voltage"] - spice["nom_threshold"]) / spice["nom_supply_voltage"] bitline_vth_delay = abs(math.log(1 - bitline_vth_swing)) * spice["wire_unit_r"] * bitline_area * bitline_cap_ff - print("delays: delay_stage {} precharge {} pen {} wl {} wlen {} vth {}".format(inverter_stage_delay, precharge_delay, pen_signal_delay, wordline_delay, wlen_signal_delay, bitline_vth_delay)) + # print("delays: delay_stage {} precharge {} pen {} wl {} wlen {} vth {}".format(inverter_stage_delay, precharge_delay, pen_signal_delay, wordline_delay, wlen_signal_delay, bitline_vth_delay)) delays = [None] * 5 # keepout between p_en rising and wl_en falling - delays[0] = int((wlen_signal_delay + wordline_delay) / inverter_stage_delay) # could possibly subtract pen_signal_delay? + delays[0] = (wlen_signal_delay + wordline_delay) / inverter_stage_delay # could possibly subtract pen_signal_delay? + delays[0] = int(delays[0] * OPTS.delay_control_scaling_factor) + # round up to nearest even integer delays[0] += delays[0] % 2 delays[2] = delays[0] + (pen_signal_delay + precharge_delay) / inverter_stage_delay + delays[2] *= OPTS.delay_control_scaling_factor # round up to nearest odd integer delays[2] = int(1 - (2 * ((1 - delays[2]) // 2))) # delays[1] can be any even value less than delays[2] delays[1] = delays[2] - 1 # keepout between p_en falling and wl_en rising delays[3] = delays[2] + pen_signal_delay / inverter_stage_delay + delays[3] *= OPTS.delay_control_scaling_factor delays[3] = int(1 - (2 * ((1 - delays[3]) // 2))) delays[4] = delays[3] + (wlen_signal_delay + wordline_delay + bitline_vth_delay) / inverter_stage_delay + delays[4] *= OPTS.delay_control_scaling_factor delays[4] = int(1 - (2 * ((1 - delays[4]) // 2))) self.delay_chain_pinout_list = delays # FIXME: fanout should be used to control delay chain height diff --git a/compiler/options.py b/compiler/options.py index 92427ac0..d7fc74b3 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -67,9 +67,13 @@ class options(optparse.Values): # Approximate percentage of delay compared to bitlines rbl_delay_percentage = 0.5 - # Allow manual adjustment of the delay chain over automatic - auto_delay_chain_sizing = False + # delay chain is automatically sized in delay based control logic + # this multiplier can be used to add a guard band to the standard timing + # lowering it can improve performance but may cause sram to fail + delay_control_scaling_factor = 1.0 + # stages for delay chain in rbl control logic only delay_chain_stages = 9 + # fanout per stage for any control logic delay_chain_fanout_per_stage = 4 accuracy_requirement = 0.75 From 513c7e9f71a46b97bcf112591235d6978edd21dc Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 10 Jul 2023 13:12:13 -0700 Subject: [PATCH 098/102] update sram library commit --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f5e14bed..e10caba0 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git # Use this for development #SRAM_LIB_GIT_REPO ?= git@github.com:VLSIDA/sky130_fd_bd_sram.git #SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git -SRAM_LIB_GIT_COMMIT ?= a83b6468c48434d927b90058b22047843c58027b +SRAM_LIB_GIT_COMMIT ?= 060f3638be6269dd9aa82cfbbdfd9525943c1582 # Open PDKs OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks From 4e649aad6bc633e917001880235ed075ecaf1f7e Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 10 Jul 2023 13:20:20 -0700 Subject: [PATCH 099/102] fix typo bug in spice comments code --- compiler/base/hierarchy_spice.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index da92c0fb..64dc0b2b 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -68,7 +68,7 @@ class spice(): self.trim_insts = set() # Keep track of any comments to add the the spice try: - self.commments + self.comments except AttributeError: self.comments = [] @@ -82,7 +82,7 @@ class spice(): """ Add a comment to the spice file """ try: - self.commments + self.comments except AttributeError: self.comments = [] From 042a3ed14fae23756a34c1b6a3b9cb61cf4afe9b Mon Sep 17 00:00:00 2001 From: Samuel Crow <42583985+samuelkcrow@users.noreply.github.com> Date: Mon, 10 Jul 2023 14:28:19 -0700 Subject: [PATCH 100/102] skip non-scmos delay control tests for now --- compiler/tests/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index eb1907fd..5fd0929c 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -70,6 +70,10 @@ BROKEN_STAMPS = \ freepdk45/10_rom_wordline_driver_array_test.ok \ freepdk45/14_rom_array_test.ok \ freepdk45/16_rom_control_logic_test.ok \ + freepdk45/16_control_logic_delay_multiport_test.ok \ + freepdk45/16_control_logic_delay_rw_test.ok \ + freepdk45/16_control_logic_delay_r_test.ok \ + freepdk45/16_control_logic_delay_w_test.ok \ freepdk45/19_rom_bank_test.ok \ scn4m_subm/06_rom_decoder_test.ok \ scn4m_subm/07_rom_column_mux_array_test.ok \ @@ -124,6 +128,10 @@ BROKEN_STAMPS = \ sky130/15_local_bitcell_array_leftrbl_1rw_test.ok \ sky130/15_local_bitcell_array_norbl_1rw_1r_test.ok \ sky130/15_local_bitcell_array_norbl_1rw_test.ok \ + sky130/16_control_logic_delay_multiport_test.ok \ + sky130/16_control_logic_delay_rw_test.ok \ + sky130/16_control_logic_delay_r_test.ok \ + sky130/16_control_logic_delay_w_test.ok \ sky130/18_port_address_512rows_test.ok \ sky130/18_port_data_spare_cols_test.ok \ sky130/19_single_bank_2mux_test.ok \ From 37b7de465338f8d1df96105e8750ec7e7d3bd2e3 Mon Sep 17 00:00:00 2001 From: vlsida-bot Date: Tue, 11 Jul 2023 00:25:28 +0000 Subject: [PATCH 101/102] Bump version: 1.2.18 -> 1.2.19 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 591bdbcd..9ddbe16d 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.2.18 +1.2.19 From 7bd312faff775b99e291a643908bc5f9d7a0694a Mon Sep 17 00:00:00 2001 From: vlsida-bot Date: Tue, 18 Jul 2023 00:59:02 +0000 Subject: [PATCH 102/102] Bump version: 1.2.19 -> 1.2.20 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 9ddbe16d..53fc08d6 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.2.19 +1.2.20