diff --git a/README.md b/README.md
index 82fe75ed..d6b948ef 100644
--- a/README.md
+++ b/README.md
@@ -43,7 +43,7 @@ The OpenRAM compiler has very few dependencies:
 
 If you want to perform DRC and LVS, you will need either:
 + Calibre (for [FreePDK45])
-+ [Magic] 8.2.79 or higher (for [SCMOS])
++ [Magic] 8.3.27 or higher (for [SCMOS])
 + [Netgen] 1.5 (for [SCMOS])
 
 You must set two environment variables: 
@@ -81,6 +81,8 @@ We have included the most recent SCN4M_SUBM design rules from [Qflow].
 
 ## Docker Image
 
+**WARNING! Some OpenRAM dependency tools installed in the Docker image are out-of-date.**
+
 We have a pre-configured Ubuntu [Docker](https://www.docker.com/) image
 available that has all tools installed for the [SCMOS] process. It is
 available at [docker hub](https://hub.docker.com/r/vlsida/openram-ubuntu).
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index b7faaec3..3f5d61af 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -185,9 +185,8 @@ class delay(simulation):
         self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
         self.sen_meas.meta_str = sram_op.READ_ZERO        
         self.sen_meas.meta_add_delay = True
-        self.dout_volt_meas.append(self.sen_meas)
-        
-        return self.dout_volt_meas
+
+        return self.dout_volt_meas + [self.sen_meas]
      
     def create_read_bit_measures(self):
         """ Adds bit measurements for read0 and read1 cycles """
@@ -1351,7 +1350,7 @@ class delay(simulation):
         Return the analytical model results for the SRAM. 
         """
         if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
-            debug.warning("Analytical characterization results are not supported for multiport.")
+            debug.warning("In analytical mode, all ports have the timing of the first read port.")
         
         # Probe set to 0th bit, does not matter for analytical delay.
         self.set_probe('0'*self.addr_size, 0)
diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py
index 55ac4016..7698f1a3 100644
--- a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py
+++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py
@@ -1,9 +1,9 @@
 word_size = 2
 num_words = 16
 
-num_rw_ports = 1
+num_rw_ports = 0
 num_r_ports = 1
-num_w_ports = 0
+num_w_ports = 1
 
 tech_name = "scn4m_subm"
 nominal_corners_only = False
diff --git a/compiler/globals.py b/compiler/globals.py
index a192ebc9..dd4ac177 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -19,7 +19,7 @@ import re
 import copy
 import importlib
 
-VERSION = "1.1.5"
+VERSION = "1.1.6"
 NAME = "OpenRAM v{}".format(VERSION)
 USAGE = "openram.py [options] <config file>\nUse -h for help.\n"
 
diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py
index 1ec7d636..b2ab1124 100644
--- a/compiler/sram/sram.py
+++ b/compiler/sram/sram.py
@@ -101,6 +101,7 @@ class sram():
             start_time = datetime.datetime.now()
             # Output the extracted design if requested
             sp_file = OPTS.output_path + "temp_pex.sp"
+            spname = OPTS.output_path + self.s.name + ".sp"
             verify.run_pex(self.s.name, gdsname, spname, output=sp_file)
             print_time("Extraction", datetime.datetime.now(), start_time)
         else:
diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index a5dfb0e5..fc390f37 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -160,7 +160,10 @@ class sram_1bank(sram_base):
         port = 0
         # Add the col address flops below the bank to the right of the control logic
         x_offset = self.control_logic_insts[port].rx() + self.dff.width
-        y_offset = - self.data_bus_size[port] - self.dff.height
+        # Place it a data bus below the x-axis, but at least as low as the control logic to not block
+        # the control logic signals
+        y_offset = min(-self.data_bus_size[port] - self.dff.height,
+                       self.control_logic_insts[port].by())
         if self.col_addr_dff:
             self.col_addr_pos[port] = vector(x_offset,
                                              y_offset)
@@ -201,7 +204,10 @@ class sram_1bank(sram_base):
             
             # Add the col address flops below the bank to the right of the control logic
             x_offset = self.control_logic_insts[port].lx() - 2 * self.dff.width
-            y_offset = self.bank.height + self.data_bus_size[port] + self.dff.height
+            # Place it a data bus below the x-axis, but at least as high as the control logic to not block
+            # the control logic signals
+            y_offset = max(self.bank.height + self.data_bus_size[port] + self.dff.height,
+                           self.control_logic_insts[port].uy() - self.dff.height)
             if self.col_addr_dff:
                 self.col_addr_pos[port] = vector(x_offset,
                                                  y_offset)