From 5222224936765a118d31888d63153ec9174ab0b6 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 13 May 2026 16:45:52 -0700 Subject: [PATCH] route supplies from endcaps to power ring --- .../modules/capped_replica_bitcell_array.py | 6 +----- compiler/modules/col_cap_array.py | 17 ++++++----------- .../tech/tech_configs/tech_cypress_cell.py | 4 ++-- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index 5cb23683..e58b51c3 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -356,11 +356,6 @@ class capped_replica_bitcell_array(bitcell_base_array): def route_supplies(self): - if OPTS.bitcell == "pbitcell": - bitcell = factory.create(module_type="pbitcell") - else: - bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports)) - top = connect_ring_top bottom = connect_ring_bottom left = connect_ring_left @@ -370,6 +365,7 @@ class capped_replica_bitcell_array(bitcell_base_array): inst = self.dummy_row_insts[1] if 'vdd' in inst.mod.pins: array_pins = inst.get_pins('vdd') + print("found pin", inst, inst.mod, array_pins) for array_pin in array_pins: supply_pin = self.top_vdd_pin self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])]) diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index 0d60dc57..c5e8dccc 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -42,6 +42,11 @@ class col_cap_array(bitcell_base_array): self.place_array() self.add_layout_pins() + # Promote leaf vdd/gnd shapes to module pin_map (same as dummy_array) so + # parents (e.g. capped_replica_bitcell_array.route_supplies) can use + # inst.get_pins("vdd") / get_pins("gnd") on this sub-module. + self.route_supplies() + #self.height = self.dummy_cell.height #self.width = self.column_size * self.cell.width @@ -51,17 +56,7 @@ class col_cap_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ self.colend = factory.create(module_type="col_cap_{}".format(OPTS.bitcell)) - - # def create_instances(self): - # """ Create the module instances used in this design """ - # self.cell_inst = {} - # for col in range(self.column_size): - # for row in range(self.row_size): - # name = "bit_r{0}_c{1}".format(row, col) - # self.cell_inst[row, col]=self.add_inst(name=name, - # mod=self.dummy_cell) - # self.connect_inst(self.get_bitcell_pins(row, col)) - + def create_instances(self): """ Create the module instances used in this design """ self.cell_inst={} diff --git a/technology/sky130/tech/tech_configs/tech_cypress_cell.py b/technology/sky130/tech/tech_configs/tech_cypress_cell.py index 3e1d7d52..cb816f70 100644 --- a/technology/sky130/tech/tech_configs/tech_cypress_cell.py +++ b/technology/sky130/tech/tech_configs/tech_cypress_cell.py @@ -284,8 +284,8 @@ power_ring_right = True connect_ring_top = ['vdd','gnd'] connect_ring_bottom = ['vdd','gnd'] -connect_ring_left = [] -connect_ring_right = [] +connect_ring_left = ['gnd'] +connect_ring_right = ['gnd'] ################################################### # Discrete tx bins