diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index b9889601..2f641da9 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -2,7 +2,6 @@ import contact import design import debug from tech import drc, parameter, spice -from ptx import ptx from vector import vector from globals import OPTS from sram_factory import factory @@ -24,7 +23,7 @@ class pgate(design.design): def connect_pin_to_rail(self,inst,pin,supply): - """ Conencts a ptx pin to a supply rail. """ + """ Connects a ptx pin to a supply rail. """ source_pin = inst.get_pin(pin) supply_pin = self.get_pin(supply) if supply_pin.overlaps(source_pin): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index daaa28f6..0dc1b683 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -2,12 +2,12 @@ import contact import pgate import debug from tech import drc, parameter, spice -from ptx import ptx from vector import vector from math import ceil from globals import OPTS from utils import round_to_grid import logical_effort +from sram_factory import factory class pinv(pgate.pgate): """ @@ -82,8 +82,8 @@ class pinv(pgate.pgate): # Sanity check. can we make an inverter in the height with minimum tx sizes? # Assume we need 3 metal 1 pitches (2 power rails, one between the tx for the drain) # plus the tx height - nmos = ptx(tx_type="nmos") - pmos = ptx(width=drc("minwidth_tx"), tx_type="pmos") + nmos = factory.create(module_type="ptx", tx_type="nmos") + pmos = factory.create(module_type="ptx", width=drc("minwidth_tx"), tx_type="pmos") tx_height = nmos.poly_height + pmos.poly_height # rotated m1 pitch or poly to active spacing min_channel = max(contact.poly.width + self.m1_space, @@ -143,18 +143,20 @@ class pinv(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos = ptx(width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - connect_poly=True, - connect_active=True) + self.nmos = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + connect_poly=True, + connect_active=True) self.add_mod(self.nmos) - self.pmos = ptx(width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - connect_poly=True, - connect_active=True) + self.pmos = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + connect_poly=True, + connect_active=True) self.add_mod(self.pmos) def route_supply_rails(self): diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index e1e8188b..8ff4b953 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -2,10 +2,10 @@ import contact import pgate import debug from tech import drc, parameter, spice -from ptx import ptx from vector import vector from globals import OPTS import logical_effort +from sram_factory import factory class pnand2(pgate.pgate): """ @@ -56,18 +56,20 @@ class pnand2(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos = ptx(width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - connect_poly=True, - connect_active=True) + self.nmos = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + connect_poly=True, + connect_active=True) self.add_mod(self.nmos) - self.pmos = ptx(width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - connect_poly=True, - connect_active=True) + self.pmos = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + connect_poly=True, + connect_active=True) self.add_mod(self.pmos) def setup_layout_constants(self): diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 16902826..a4bbb1c0 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -2,9 +2,9 @@ import contact import pgate import debug from tech import drc, parameter, spice -from ptx import ptx from vector import vector from globals import OPTS +from sram_factory import factory class pnand3(pgate.pgate): """ @@ -56,18 +56,20 @@ class pnand3(pgate.pgate): def add_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos = ptx(width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - connect_poly=True, - connect_active=True) + self.nmos = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + connect_poly=True, + connect_active=True) self.add_mod(self.nmos) - self.pmos = ptx(width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - connect_poly=True, - connect_active=True) + self.pmos = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + connect_poly=True, + connect_active=True) self.add_mod(self.pmos) def setup_layout_constants(self): @@ -88,7 +90,7 @@ class pnand3(pgate.pgate): self.output_pos = vector(0,0.5*self.height) # This is the extra space needed to ensure DRC rules to the active contacts - nmos = ptx(tx_type="nmos") + nmos = factory.create(module_type="ptx", tx_type="nmos") extra_contact_space = max(-nmos.get_pin("D").by(),0) # This is a poly-to-poly of a flipped cell self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space, diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 21ba14ce..b28d4cd1 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -2,9 +2,9 @@ import contact import pgate import debug from tech import drc, parameter, spice -from ptx import ptx from vector import vector from globals import OPTS +from sram_factory import factory class pnor2(pgate.pgate): """ @@ -53,18 +53,20 @@ class pnor2(pgate.pgate): def create_ptx(self): """ Create the PMOS and NMOS transistors. """ - self.nmos = ptx(width=self.nmos_width, - mults=self.tx_mults, - tx_type="nmos", - connect_poly=True, - connect_active=True) + self.nmos = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + connect_poly=True, + connect_active=True) self.add_mod(self.nmos) - self.pmos = ptx(width=self.pmos_width, - mults=self.tx_mults, - tx_type="pmos", - connect_poly=True, - connect_active=True) + self.pmos = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + connect_poly=True, + connect_active=True) self.add_mod(self.pmos) def setup_layout_constants(self): diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 64ff98a1..cea9c845 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -2,7 +2,6 @@ import contact import pgate import debug from tech import drc, parameter -from ptx import ptx from vector import vector from globals import OPTS from sram_factory import factory @@ -50,8 +49,9 @@ class precharge(pgate.pgate): """ Initializes the upper and lower pmos """ - self.pmos = ptx(width=self.ptx_width, - tx_type="pmos") + self.pmos = factory.create(module_type="ptx", + width=self.ptx_width, + tx_type="pmos") self.add_mod(self.pmos) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 4b5db508..f03a22e8 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -3,7 +3,6 @@ import debug from tech import drc from vector import vector import contact -from ptx import ptx from globals import OPTS from sram_factory import factory @@ -48,7 +47,7 @@ class single_level_column_mux(design.design): # Adds nmos_lower,nmos_upper to the module self.ptx_width = self.tx_size*drc("minwidth_tx") - self.nmos = ptx(width=self.ptx_width) + self.nmos = factory.create(module_type="ptx", width=self.ptx_width) self.add_mod(self.nmos)