From 5099ff6f6c05ce7095ab9b2d197b36fd3bd3d566 Mon Sep 17 00:00:00 2001
From: jsowash <jsowash@vpn-pool-128-114-231-237.ucsc.edu>
Date: Thu, 29 Aug 2019 09:01:35 -0700
Subject: [PATCH] Changed A/Z pins to copy_layout_pin and made en (B) pin a
 single pin.

---
 compiler/modules/write_mask_and_array.py | 39 +++++++-----------------
 1 file changed, 11 insertions(+), 28 deletions(-)

diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py
index 9d29cbea..b94934bb 100644
--- a/compiler/modules/write_mask_and_array.py
+++ b/compiler/modules/write_mask_and_array.py
@@ -105,13 +105,17 @@ class write_mask_and_array(design.design):
     def add_layout_pins(self):
         self.nand2 = factory.create(module_type="pnand2")
         supply_pin=self.nand2.get_pin("vdd")
+
+        beg_en_pin = self.and2_insts[0].get_pin("B")
+        end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B")
+        self.add_layout_pin(text="en",
+                            layer="metal3",
+                            offset=beg_en_pin.ll(),
+                            width = end_en_pin.rx() - beg_en_pin.lx())
+
         for i in range(self.num_wmasks):
+            self.copy_layout_pin(self.and2_insts[i],"A","wmask_in_{0}".format(i))
             wmask_in_pin = self.and2_insts[i].get_pin("A")
-            self.add_layout_pin(text="wmask_in_{0}".format(i),
-                                layer=wmask_in_pin.layer,
-                                offset=wmask_in_pin.ll(),
-                                width=wmask_in_pin.width(),
-                                height=wmask_in_pin.height())
             self.add_via_center(layers=("metal1", "via1", "metal2"),
                                 offset=wmask_in_pin.center())
 
@@ -123,39 +127,18 @@ class write_mask_and_array(design.design):
             self.add_via_center(layers=("metal2", "via2", "metal3"),
                                 offset=en_pin.center())
 
-            # Route en pin between AND gates
-            if i < self.num_wmasks-1:
-                self.add_layout_pin(text="en",
-                                    layer="metal3",
-                                    offset=en_pin.bc(),
-                                    width = self.en_width(i),
-                                    height = drc('minwidth_metal3'))
 
-            wmask_out_pin = self.and2_insts[i].get_pin("Z")
-            self.add_layout_pin(text="wmask_out_{0}".format(i),
-                                layer=wmask_out_pin.layer,
-                                offset=wmask_out_pin.ll(),
-                                width=wmask_out_pin.width(),
-                                height=wmask_out_pin.height())
+            self.copy_layout_pin(self.and2_insts[i],"Z","wmask_out_{0}".format(i))
 
             self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0))
             self.add_power_pin("vdd", vector(supply_pin.width() + i * self.wmask_en_len, self.height))
-
+            # Route power and ground rails together
             if i < self.num_wmasks-1:
                 for n in ["gnd","vdd"]:
                     pin = self.and2_insts[i].get_pin(n)
                     next_pin = self.and2_insts[i+1].get_pin(n)
                     self.add_path("metal1",[pin.center(),next_pin.center()])
 
-
-    def en_width(self, pin):
-        en_pin = self.and2_insts[pin].get_pin("B")
-        next_en_pin = self.and2_insts[pin+1].get_pin("B")
-        width = next_en_pin.center() - en_pin.center()
-        # Return x coordinates only
-        return width[0]
-
-
     def get_cin(self):
         """Get the relative capacitance of all the input connections in the bank"""
         # The enable is connected to an and2 for every row.