diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py
index f470bc46..b23cce97 100644
--- a/compiler/modules/bitcell_base_array.py
+++ b/compiler/modules/bitcell_base_array.py
@@ -151,7 +151,7 @@ class bitcell_base_array(design):
         wl_names = self.cell.get_all_wl_names()
         for row in range(self.row_size):
             for port in self.all_ports:
-                wl_pin = self.cell_inst[self.row_size - 1 - row, 0].get_pin(wl_names[port])
+                wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
                 self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
                                     layer=wl_pin.layer,
                                     offset=wl_pin.ll().scale(0, 1),