From 4f28295e20fc24f74c5f4432e69594d84388243f Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Fri, 19 Apr 2019 01:27:06 -0700
Subject: [PATCH] Added initial graph for correct naming

---
 compiler/base/design.py           |  6 +--
 compiler/base/graph_util.py       | 66 +++++++++++++++++++++++++++++++
 compiler/base/hierarchy_design.py | 34 ++++++++++++++++
 compiler/pgates/pinv.py           |  1 -
 compiler/pgates/ptx.py            | 13 ++++++
 5 files changed, 116 insertions(+), 4 deletions(-)
 create mode 100644 compiler/base/graph_util.py

diff --git a/compiler/base/design.py b/compiler/base/design.py
index 4e76b40a..243304fe 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -18,7 +18,7 @@ class design(hierarchy_design):
         
         self.setup_drc_constants()
         self.setup_multiport_constants()
-
+        
         self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
         self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space)
         self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space)
@@ -86,8 +86,8 @@ class design(hierarchy_design):
         for port in range(OPTS.num_r_ports):
             self.read_ports.append(port_number)
             self.readonly_ports.append(port_number)
-            port_number += 1
-
+            port_number += 1                    
+        
     def analytical_power(self, corner, load):
         """ Get total power of a module  """
         total_module_power = self.return_power()
diff --git a/compiler/base/graph_util.py b/compiler/base/graph_util.py
new file mode 100644
index 00000000..b795e67f
--- /dev/null
+++ b/compiler/base/graph_util.py
@@ -0,0 +1,66 @@
+import os
+from collections import defaultdict
+
+import gdsMill
+import tech
+import math
+import globals
+import debug
+from vector import vector
+from pin_layout import pin_layout
+
+class graph():
+    """Implements a directed graph"""
+    
+    def __init__(self):
+        self.graph = defaultdict(list)
+
+    def add_edge(self, u, v):
+        """Adds edge to graph. Nodes added as well if they do not exist."""
+        if v not in self.graph[u]:
+            self.graph[u].append(v)
+
+    def add_node(self, u):
+        """Add node to graph with no edges"""
+        if not u in self.graph:
+            self.graph[u] = []
+            
+    def remove_edges(self, node):
+        """Helper function to remove edges, useful for removing vdd/gnd"""
+        self.graph[node] = []    
+            
+    def printAllPaths(self,s, d): 
+  
+        # Mark all the vertices as not visited 
+        visited = set()
+  
+        # Create an array to store paths 
+        path = [] 
+  
+        # Call the recursive helper function to print all paths 
+        self.printAllPathsUtil(s, d,visited, path)        
+            
+    def printAllPathsUtil(self, u, d, visited, path): 
+  
+        # Mark the current node as visited and store in path 
+        visited.add(u)
+        path.append(u) 
+  
+        # If current vertex is same as destination, then print 
+        # current path[] 
+        if u == d: 
+            debug.info(1,"{}".format(path)) 
+        else: 
+            # If current vertex is not destination 
+            #Recur for all the vertices adjacent to this vertex 
+            for i in self.graph[u]: 
+                if i not in visited: 
+                    self.printAllPathsUtil(i, d, visited, path) 
+                      
+        # Remove current vertex from path[] and mark it as unvisited 
+        path.pop() 
+        visited.remove(u)        
+            
+    def __str__(self):
+        """ override print function output """
+        return "Nodes: {}\nEdges:{} ".format(list(self.graph), self.graph)  
\ No newline at end of file
diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index 6a6003a2..607859a4 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -5,6 +5,7 @@ import verify
 import debug
 import os
 from globals import OPTS
+import graph_util
 
 total_drc_errors = 0 
 total_lvs_errors = 0
@@ -98,6 +99,39 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             os.remove(tempspice)
             os.remove(tempgds)
 
+    #Example graph run
+    # graph = graph_util.graph()
+    # pins = ['A','Z','vdd','gnd']
+    # d.build_graph(graph,"Xpdriver",pins)
+    # graph.remove_edges('vdd')
+    # graph.remove_edges('gnd')
+    # debug.info(1,"{}".format(graph))
+    # graph.printAllPaths('A', 'Z')    
+            
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Recursively create graph from instances in module."""
+        
+        #Translate port names to external nets
+        if len(port_nets) != len(self.pins):
+            debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1)
+        port_dict = {i:j for i,j in zip(self.pins, port_nets)}
+        debug.info(1, "Instance name={}".format(inst_name))
+        for subinst, conns in zip(self.insts, self.conns):
+            debug.info(1, "Sub-Instance={}".format(subinst))
+            subinst_name = inst_name+'.X'+subinst.name
+            subinst_ports = self.translate_nets(conns, port_dict, inst_name)
+            subinst.mod.build_graph(graph, subinst_name, subinst_ports)
+    
+    def translate_nets(self, subinst_ports, port_dict, inst_name):
+        """Converts connection names to their spice hierarchy equivalent"""
+        converted_conns = []
+        for conn in subinst_ports:
+            if conn in port_dict:
+                converted_conns.append(port_dict[conn])
+            else:
+                converted_conns.append("{}.{}".format(inst_name, conn))
+        return converted_conns        
+            
     def __str__(self):
         """ override print function output """
         return "design: " + self.name
diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py
index f00e9af7..c66c944c 100644
--- a/compiler/pgates/pinv.py
+++ b/compiler/pgates/pinv.py
@@ -38,7 +38,6 @@ class pinv(pgate.pgate):
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()
-
         # for run-time, we won't check every transitor DRC/LVS independently
         # but this may be uncommented for debug purposes
         #self.DRC_LVS()
diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py
index 3a127454..7e80a7c9 100644
--- a/compiler/pgates/ptx.py
+++ b/compiler/pgates/ptx.py
@@ -356,3 +356,16 @@ class ptx(design.design):
     def get_cin(self):
         """Returns the relative gate cin of the tx"""
         return self.tx_width/drc("minwidth_tx")
+
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds ptx edges to graph. Lowest graph level."""
+        #The ptx has four connections: (S)ource, (G)ate, (D)rain, (B)ody. The positions in spice 
+        #are hardcoded which is represented here as well.
+        #Edges are connected as follows: G->S, G->D, D<->S. Body not represented in graph.
+        if len(port_nets) != 4:
+            debug.error("Transistor has non-standard connections.",1)
+        graph.add_edge(port_nets[1],port_nets[0])
+        graph.add_edge(port_nets[1],port_nets[2])
+        graph.add_edge(port_nets[0],port_nets[2])
+        graph.add_edge(port_nets[2],port_nets[0])
+        
\ No newline at end of file