From 4f01eeb3c16425593193772302c5011a73a856a7 Mon Sep 17 00:00:00 2001 From: jsowash Date: Wed, 21 Aug 2019 12:36:53 -0700 Subject: [PATCH] Combined changes to the pin locations and vias. --- compiler/modules/write_mask_and_array.py | 8 ++++++-- compiler/sram/sram_1bank.py | 25 ++++++++++++------------ 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index bb10b5b9..a505ae22 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -103,6 +103,8 @@ class write_mask_and_array(design.design): def add_layout_pins(self): + self.nand2 = factory.create(module_type="pnand2") + supply_pin=self.nand2.get_pin("vdd") for i in range(self.num_wmasks): wmask_in_pin = self.and2_insts[i].get_pin("A") self.add_layout_pin(text="wmask_in_{0}".format(i), @@ -135,8 +137,10 @@ class write_mask_and_array(design.design): width=wmask_out_pin.width(), height=wmask_out_pin.height()) - self.add_power_pin("gnd", vector(supply_pin.width()+i*self.wmask_en_len,0)) - self.add_power_pin("vdd", vector(supply_pin.width()+i*self.wmask_en_len,self.height)) + self.add_power_pin("gnd", vector((supply_pin.lx() - 0.75 *drc('minwidth_metal1'))+i*self.wmask_en_len, + 0)) + self.add_power_pin("vdd", vector((supply_pin.lx() - 0.75*drc('minwidth_metal1'))+i*self.wmask_en_len, + self.height)) def en_width(self, pin): diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 634f569c..c4ef0816 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -362,24 +362,25 @@ class sram_1bank(sram_base): dff_names = ["dout_{}".format(x) for x in range(self.word_size)] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] for x in dff_names: - offset = self.data_dff_insts[port].get_pin(x).center() + pin_offset = self.data_dff_insts[port].get_pin(x).center() self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=offset) + offset=pin_offset) self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=offset) + offset=pin_offset) self.add_via_center(layers=("metal3", "via3", "metal4"), - offset=offset) + offset=pin_offset) bank_names = ["din{0}_{1}".format(port,x) for x in range(self.word_size)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] for x in bank_names: - offset = self.bank_inst.get_pin(x).center() + pin_offset = vector(self.bank_inst.get_pin(x).cx(), + self.bank_inst.get_pin(x).by() - 0.75 * drc('minwidth_metal1')) self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=offset) + offset=pin_offset) self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=offset) + offset=pin_offset) self.add_via_center(layers=("metal3", "via3", "metal4"), - offset=offset) . + offset=pin_offset) route_map = list(zip(bank_pins, dff_pins)) self.create_horizontal_channel_route(netlist=route_map, @@ -398,16 +399,16 @@ class sram_1bank(sram_base): dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)] dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names] for x in dff_names: - offset = self.wmask_dff_insts[port].get_pin(x).center() + offset_pin = self.wmask_dff_insts[port].get_pin(x).center() self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=offset) + offset=offset_pin) bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] for x in bank_names: - offset = self.bank_inst.get_pin(x).center() + offset_pin = self.bank_inst.get_pin(x).center() self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=offset) + offset=offset_pin) route_map = list(zip(bank_pins, dff_pins))