From 4ea0fcd0681df0d60cb98fda0595898692a37ca5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 23 Apr 2021 22:49:29 -0700 Subject: [PATCH] support multi cell wide precharge cells --- compiler/base/custom_cell_properties.py | 2 +- compiler/modules/port_data.py | 18 +++++++++++++----- compiler/modules/precharge_array.py | 2 +- compiler/modules/replica_bitcell_array.py | 2 +- compiler/options.py | 2 ++ compiler/pgates/precharge.py | 6 +++++- 6 files changed, 23 insertions(+), 9 deletions(-) diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index bb211842..76bb10ce 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -176,7 +176,7 @@ class cell_properties(): self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw" self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw" self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw" - + self.use_strap = False self._ptx = _ptx(model_is_subckt=False, bin_spice_models=False) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 36ba5d0f..c9ebc193 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -11,6 +11,7 @@ from sram_factory import factory from collections import namedtuple from vector import vector from globals import OPTS +from tech import cell_properties from tech import layer_properties as layer_props @@ -39,9 +40,12 @@ class port_data(design.design): if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = bitcell.width + strap.width self.bit_offsets = [] for i in range(self.num_cols + self.num_spare_cols): - self.bit_offsets.append(i * bitcell.width) + self.bit_offsets.append(i * precharge_width) else: self.bit_offsets = bit_offsets @@ -196,14 +200,18 @@ class port_data(design.design): # and mirroring happens correctly # Used for names/dimensions only - self.cell = factory.create(module_type=OPTS.bitcell) - + cell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = cell.width + strap.width + if self.port == 0: # Append an offset on the left - precharge_bit_offsets = [self.bit_offsets[0] - self.cell.width] + self.bit_offsets + precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets else: # Append an offset on the right - precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + self.cell.width] + precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width] + self.precharge_array = factory.create(module_type="precharge_array", columns=self.num_cols + self.num_spare_cols + 1, offsets=precharge_bit_offsets, diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 8718dfd0..ed19b387 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -76,8 +76,8 @@ class precharge_array(design.design): size=self.size, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) + self.add_mod(self.pc_cell) - self.cell = factory.create(module_type=OPTS.bitcell) def add_layout_pins(self): diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 828941ae..5618c74e 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -6,7 +6,7 @@ import debug from bitcell_base_array import bitcell_base_array -from tech import drc, spice +from tech import drc, spice, cell_properties from vector import vector from globals import OPTS from sram_factory import factory diff --git a/compiler/options.py b/compiler/options.py index e3a9a76e..469c3236 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -72,7 +72,9 @@ class options(optparse.Values): # This is the temp directory where all intermediate results are stored. try: # If user defined the temporary location in their environment, use it + openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP")) + except: openram_temp = "/tmp" diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index d1999384..c8f6d819 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -30,7 +30,11 @@ class precharge(design.design): self.beta = parameter["beta"] self.ptx_width = self.beta * parameter["min_tx_size"] self.ptx_mults = 1 - self.width = self.bitcell.width + if(cell_props.use_strap): + strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) + self.width = self.bitcell.width + strap.width + else: + self.width = self.bitcell.width self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br self.bitcell_bl_pin =self.bitcell.get_pin(self.bitcell_bl)