From 4e232c49ad27047c308d1a958499ec7dea74d360 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 7 Nov 2018 14:46:51 -0800 Subject: [PATCH] Update precharge cell for multiport. Comment out pbitcell tests. Add bitcell_1rw_1r test. Move bitcell horizontal routing to metal1. Extend precharge height for stacking. --- compiler/pgates/precharge.py | 48 ++++++++++------------- compiler/tests/08_precharge_array_test.py | 16 +++++--- 2 files changed, 31 insertions(+), 33 deletions(-) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index ea67eeb5..0bb6142f 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -170,7 +170,7 @@ class precharge(pgate.pgate): well_type="n") - self.height = well_contact_pos.y + contact.well.height + self.height = well_contact_pos.y + contact.well.height + self.m1_pitch self.add_rect(layer="nwell", offset=vector(0,0), @@ -182,19 +182,19 @@ class precharge(pgate.pgate): """Adds both bit-line and bit-line-bar to the module""" # adds the BL on metal 2 offset = vector(self.bitcell.get_pin(self.bitcell_bl).cx(),0) - vector(0.5 * self.m2_width,0) - self.add_layout_pin(text="bl", - layer="metal2", - offset=offset, - width=drc("minwidth_metal2"), - height=self.height) + self.bl_pin = self.add_layout_pin(text="bl", + layer="metal2", + offset=offset, + width=drc("minwidth_metal2"), + height=self.height) # adds the BR on metal 2 offset = vector(self.bitcell.get_pin(self.bitcell_br).cx(),0) - vector(0.5 * self.m2_width,0) - self.add_layout_pin(text="br", - layer="metal2", - offset=offset, - width=drc("minwidth_metal2"), - height=self.height) + self.br_pin = self.add_layout_pin(text="br", + layer="metal2", + offset=offset, + width=drc("minwidth_metal2"), + height=self.height) def connect_to_bitlines(self): self.add_bitline_contacts() @@ -208,29 +208,23 @@ class precharge(pgate.pgate): """Adds contacts/via from metal1 to metal2 for bit-lines""" stack=("metal1", "via1", "metal2") - pos = self.lower_pmos_inst.get_pin("S").center() + upper_y = self.upper_pmos1_inst.get_pin("S").cy() + lower_y = self.lower_pmos_inst.get_pin("S").cy() + self.add_contact_center(layers=stack, - offset=pos) - pos = self.lower_pmos_inst.get_pin("D").center() + offset = vector(self.bl_pin.cx(), upper_y)) self.add_contact_center(layers=stack, - offset=pos) - pos = self.upper_pmos1_inst.get_pin("S").center() + offset = vector(self.br_pin.cx(), upper_y)) self.add_contact_center(layers=stack, - offset=pos) - pos = self.upper_pmos2_inst.get_pin("D").center() + offset = vector(self.bl_pin.cx(), lower_y)) self.add_contact_center(layers=stack, - offset=pos) + offset = vector(self.br_pin.cx(), lower_y)) def connect_pmos(self, pmos_pin, bit_pin): """ Connect pmos pin to bitline pin """ - ll_pos = vector(min(pmos_pin.lx(),bit_pin.lx()), pmos_pin.by()) - ur_pos = vector(max(pmos_pin.rx(),bit_pin.rx()), pmos_pin.uy()) + left_pos = vector(min(pmos_pin.cx(),bit_pin.cx()), pmos_pin.cy()) + right_pos = vector(max(pmos_pin.cx(),bit_pin.cx()), pmos_pin.cy()) - width = ur_pos.x-ll_pos.x - height = ur_pos.y-ll_pos.y - self.add_rect(layer="metal2", - offset=ll_pos, - width=width, - height=height) + self.add_path("metal1", [ left_pos, right_pos] ) diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 5ea9931b..cdf6100e 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -24,18 +24,22 @@ class precharge_test(openram_test): self.local_check(pc) # check precharge array in multi-port - OPTS.bitcell = "pbitcell" + OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 + OPTS.num_w_ports = 0 - debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") + debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") self.local_check(pc) - debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)") - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(pc) + # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") + # pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") + # self.local_check(pc) + + # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)") + # pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") + # self.local_check(pc) globals.end_openram()