diff --git a/README.md b/README.md index aa5a1705..d97356a4 100644 --- a/README.md +++ b/README.md @@ -42,10 +42,12 @@ The OpenRAM compiler has very few dependencies: + [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) + Python 3.5 or higher + Python numpy (pip3 install numpy to install) ++ Python scipy (pip3 install scipy to install) If you want to perform DRC and LVS, you will need either: + Calibre (for [FreePDK45]) -+ [Magic] + [Netgen] (for [SCMOS]) ++ [Magic] 8.2.79 or higher (for [SCMOS]) ++ [Netgen] 1.5 (for [SCMOS]) You must set two environment variables: + OPENRAM\_HOME should point to the compiler source directory. diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 96e6bba8..c78b3284 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -26,7 +26,7 @@ class pbitcell_test(openram_test): debug.info(2, "Bitcell with 1 of each port: read/write, write, and read") tx = pbitcell(name="pbc") self.local_check(tx) - + OPTS.num_rw_ports=0 OPTS.num_w_ports=1 OPTS.num_r_ports=1 diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 4340bce6..799c223e 100755 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -13,7 +13,7 @@ class openram_test(unittest.TestCase): self.reset() - tempgds = OPTS.openram_temp + "temp.gds" + tempgds = "{0}{1}.gds".format(OPTS.openram_temp,w.name) w.gds_write(tempgds) import verify @@ -28,8 +28,8 @@ class openram_test(unittest.TestCase): self.reset() - tempspice = OPTS.openram_temp + "temp.sp" - tempgds = OPTS.openram_temp + "temp.gds" + tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name) + tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name) a.sp_write(tempspice) # cannot write gds in netlist_only mode @@ -37,7 +37,7 @@ class openram_test(unittest.TestCase): a.gds_write(tempgds) import verify - result=verify.run_drc(a.name, tempgds) + result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification) if result != 0: #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) @@ -45,7 +45,7 @@ class openram_test(unittest.TestCase): self.fail("DRC failed: {}".format(a.name)) - result=verify.run_lvs(a.name, tempgds, tempspice, final_verification) + result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification) if result != 0: #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid()) #debug.info(0,"Archiving failed files to {}.zip".format(zip_file)) @@ -54,6 +54,7 @@ class openram_test(unittest.TestCase): if OPTS.purge_temp: self.cleanup() + def find_feasible_test_period(self, delay_obj, sram, load, slew): """Creates a delay simulation to determine a feasible period for the functional tests to run. diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 0af8e5ef..5b4e8e3f 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -45,7 +45,10 @@ def write_magic_script(cell_name, gds_name, extract=False, final_verification=Fa #f.write("load {}_new\n".format(cell_name)) #f.write("cellname rename {0}_new {0}\n".format(cell_name)) #f.write("load {}\n".format(cell_name)) + f.write("cellname delete \(UNNAMED\)\n") f.write("writeall force\n") + f.write("select top cell\n") + f.write("expand\n") f.write("drc check\n") f.write("drc catchup\n") f.write("drc count total\n") @@ -55,14 +58,27 @@ def write_magic_script(cell_name, gds_name, extract=False, final_verification=Fa else: pre = "" if final_verification: - f.write(pre+"extract unique\n") - f.write(pre+"extract\n") - f.write(pre+"ext2spice hierarchy on\n") + f.write(pre+"extract unique\n".format(cell_name)) + else: + f.write(pre+"extract\n".format(cell_name)) + #f.write(pre+"ext2spice hierarchy on\n") + #f.write(pre+"ext2spice scale off\n") + # lvs exists in 8.2.79, but be backword compatible for now + #f.write(pre+"ext2spice lvs\n") + f.write(pre+"ext2spice hierarchy on\n") + f.write(pre+"ext2spice format ngspice\n") + f.write(pre+"ext2spice cthresh infinite\n") + f.write(pre+"ext2spice rthresh infinite\n") + f.write(pre+"ext2spice renumber off\n") f.write(pre+"ext2spice scale off\n") + f.write(pre+"ext2spice blackbox on\n") + f.write(pre+"ext2spice subcircuit top auto\n") + f.write(pre+"ext2spice global off\n") + # Can choose hspice, ngspice, or spice3, # but they all seem compatible enough. #f.write(pre+"ext2spice format ngspice\n") - f.write(pre+"ext2spice\n") + f.write(pre+"ext2spice {}\n".format(cell_name)) f.write("quit -noprompt\n") f.write("EOF\n") @@ -136,8 +152,9 @@ def run_drc(cell_name, gds_name, extract=True, final_verification=False): # etc. try: f = open(outfile, "r") - except: - debug.error("Unable to retrieve DRC results file. Is magic set up?",1) + except FileNotFoundError: + debug.error("Unable to load DRC results file from {}. Is magic set up?".format(outfile),1) + results = f.readlines() f.close() errors=1 @@ -189,7 +206,11 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): total_errors = 0 # check the result for these lines in the summary: - f = open(resultsfile, "r") + try: + f = open(resultsfile, "r") + except FileNotFoundError: + debug.error("Unable to load LVS results from {}".format(resultsfile),1) + results = f.readlines() f.close() # Look for the results after the final "Subcircuit summary:"