From 4ad920eaf7b098a9f21649ef7be41187a6407afa Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Mon, 23 Dec 2019 08:42:52 -0800
Subject: [PATCH] Small fixes to tech usage.

---
 compiler/base/contact.py | 22 +++++++++++++---------
 compiler/pgates/ptx.py   |  6 +++---
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/compiler/base/contact.py b/compiler/base/contact.py
index 8def5bfd..64433633 100644
--- a/compiler/base/contact.py
+++ b/compiler/base/contact.py
@@ -83,7 +83,7 @@ class contact(hierarchy_design.hierarchy_design):
         self.second_layer_name = second_layer
         
         # Contacts will have unique per first layer
-        if via_layer in tech.layer.keys():
+        if via_layer in tech.layer:
             self.via_layer_name = via_layer
         elif via_layer == "contact":
             if first_layer in ("active", "poly"):
@@ -171,7 +171,7 @@ class contact(hierarchy_design.hierarchy_design):
     def create_nitride_cut_enclosure(self):
         """ Special layer that encloses poly contacts in some processes """
         # Check if there is a special poly nitride cut layer
-        if "npc" not in tech.layer.keys():
+        if "npc" not in tech.layer:
             return
 
         # Only add for poly layers
@@ -224,13 +224,17 @@ class contact(hierarchy_design.hierarchy_design):
                       offset=implant_position,
                       width=implant_width,
                       height=implant_height)
-        well_position = self.first_layer_position - [drc("well_enclose_active")] * 2
-        well_width = self.first_layer_width + 2 * drc("well_enclose_active")
-        well_height = self.first_layer_height + 2 * drc("well_enclose_active")
-        self.add_rect(layer="{}well".format(self.well_type),
-                      offset=well_position,
-                      width=well_width,
-                      height=well_height)
+
+        # Optionally implant well if layer exists
+        well_layer = "{}well".format(self.well_type)
+        if well_layer in tech.layer:
+            well_position = self.first_layer_position - [drc("well_enclose_active")] * 2
+            well_width = self.first_layer_width + 2 * drc("well_enclose_active")
+            well_height = self.first_layer_height + 2 * drc("well_enclose_active")
+            self.add_rect(layer=well_layer,
+                          offset=well_position,
+                          width=well_width,
+                          height=well_height)
         
     def analytical_power(self, corner, load):
         """ Get total power of a module  """
diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py
index 5d4c015a..20c513bb 100644
--- a/compiler/pgates/ptx.py
+++ b/compiler/pgates/ptx.py
@@ -159,7 +159,7 @@ class ptx(design.design):
 
         # Well enclosure of active, ensure minwidth as well
         well_name = "{}well".format(self.well_type)
-        if layer[well_name]:
+        if well_name in layer:
             self.cell_well_width = max(self.active_width + 2 * self.well_enclose_active,
                                        self.well_width)
             self.cell_well_height = max(self.tx_width + 2 * self.well_enclose_active,
@@ -326,12 +326,12 @@ class ptx(design.design):
         Add an (optional) well and implant for the type of transistor.
         """
         well_name = "{}well".format(self.well_type)
-        if layer[well_name]:
+        if well_name in layer:
             self.add_rect(layer=well_name,
                           offset=(0,0),
                           width=self.cell_well_width,
                           height=self.cell_well_height)
-        if layer["vtg"]:
+        if "vtg" in layer:
             self.add_rect(layer="vtg",
                           offset=(0,0),
                           width=self.cell_well_width,