From 2d539a1b9588f0c6abe3bdc3a8a531fdd53030c2 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sat, 20 Oct 2018 14:13:18 -0700 Subject: [PATCH 01/78] moved css into a seperate file to organize and disambiguate docstrings from multiline strings --- compiler/datasheet/assets/datasheet.css | 26 +++++++++++++++++++++ compiler/datasheet/datasheet.py | 30 +++---------------------- 2 files changed, 29 insertions(+), 27 deletions(-) create mode 100644 compiler/datasheet/assets/datasheet.css diff --git a/compiler/datasheet/assets/datasheet.css b/compiler/datasheet/assets/datasheet.css new file mode 100644 index 00000000..5d5a04e5 --- /dev/null +++ b/compiler/datasheet/assets/datasheet.css @@ -0,0 +1,26 @@ + + diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 543c75fa..f9edb5da 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -20,34 +20,10 @@ class datasheet(): def generate_html(self): - self.html = """""" + with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/datasheet.css', 'r') as datasheet_css: + self.html += datasheet_css.read() + self.html +='

'+ self.name + '.html' + '

' -# self.html +='

{0}

' -# self.html +='

{0}

' self.html +='

Ports and Configuration (DEBUG)

' self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">") From fcfee649d5a9adc212780eac465bb61e0eb94e4b Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sat, 20 Oct 2018 14:13:18 -0700 Subject: [PATCH 02/78] moved css into a seperate file to organize and disambiguate docstrings from multiline strings --- compiler/datasheet/assets/datasheet.css | 26 +++++++++++++++++++++ compiler/datasheet/datasheet.py | 30 +++---------------------- 2 files changed, 29 insertions(+), 27 deletions(-) create mode 100644 compiler/datasheet/assets/datasheet.css diff --git a/compiler/datasheet/assets/datasheet.css b/compiler/datasheet/assets/datasheet.css new file mode 100644 index 00000000..5d5a04e5 --- /dev/null +++ b/compiler/datasheet/assets/datasheet.css @@ -0,0 +1,26 @@ + + diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 543c75fa..f9edb5da 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -20,34 +20,10 @@ class datasheet(): def generate_html(self): - self.html = """""" + with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/datasheet.css', 'r') as datasheet_css: + self.html += datasheet_css.read() + self.html +='

'+ self.name + '.html' + '

' -# self.html +='

{0}

' -# self.html +='

{0}

' self.html +='

Ports and Configuration (DEBUG)

' self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">") From f1fb174b530d9fd19b2346389fe30700773651b4 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sat, 27 Oct 2018 11:21:06 -0700 Subject: [PATCH 03/78] fixed bug where netlist_only still produced layout deliverables --- compiler/datasheet/datasheet_gen.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index e68e94df..a16959f0 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -117,12 +117,17 @@ def parse_file(f,pages): new_sheet.timing.append(timing_and_current_data_item('Standby current','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Area','2','3','4')) + if not OPTS.netlist_only: + new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','{1}.{2}'.format(OUT_DIR,NAME,'gds'))) + new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,NAME,'lef'))) + new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{1}.{2}'.format(OUT_DIR,NAME,'sp'))) new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{1}.{2}'.format(OUT_DIR,NAME,'v'))) - new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','{1}.{2}'.format(OUT_DIR,NAME,'gds'))) - new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,NAME,'lef'))) + new_sheet.dlv.append(deliverables_item('.html','This datasheet','{1}.{2}'.format(OUT_DIR,NAME,'html'))) new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) + + new_sheet.io.append(in_out_item('WORD_SIZE',WORD_SIZE)) new_sheet.io.append(in_out_item('NUM_WORDS',NUM_WORDS)) From 2da90c4b6a8634d2f78058fc4909539768148411 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sat, 27 Oct 2018 12:04:10 -0700 Subject: [PATCH 04/78] fixed double counting of characterization tuple permutations --- compiler/characterizer/lib.py | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6cc177f6..72cadc45 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -82,7 +82,7 @@ class lib: debug.info(1,"Writing to {0}".format(lib_name)) self.characterize() self.lib.close() - self.parse_info() + self.parse_info(self.corner,lib_name) def characterize(self): """ Characterize the current corner. """ @@ -501,31 +501,21 @@ class lib: self.times = self.sh.analyze(self.slews,self.slews) - def parse_info(self): + def parse_info(self,corner,lib_name): if OPTS.is_unit_test: return datasheet = open(OPTS.openram_temp +'/datasheet.info', 'a+') - - for (corner, lib_name) in zip(self.corners, self.lib_files): - -# ports = "" -# if OPTS.num_rw_ports>0: -# ports += "{}_".format(OPTS.num_rw_ports) -# if OPTS.num_w_ports>0: -# ports += "{}_".format(OPTS.num_w_ports) -# if OPTS.num_r_ports>0: -# ports += "{}_".format(OPTS.num_r_ports) - datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13}".format("sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name), + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13}\n".format("sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name), OPTS.num_words, OPTS.num_banks, OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports, OPTS.tech_name, - self.corner[1], - self.corner[2], - self.corner[0], + corner[1], + corner[2], + corner[0], round_time(self.char_sram_results["min_period"]), self.out_dir, lib_name, From 905f6f8b4325ff573a71b54445413c84b77a7a7a Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 30 Oct 2018 21:37:30 -0700 Subject: [PATCH 05/78] added docstring and renamed some functions --- .../datasheet/characterization_corners.py | 6 +++ compiler/datasheet/datasheet.py | 8 +++- compiler/datasheet/datasheet_gen.py | 46 +++++++++++++------ compiler/datasheet/deliverables.py | 6 +++ compiler/datasheet/in_out.py | 6 +++ compiler/datasheet/operating_conditions.py | 6 +++ compiler/datasheet/timing_and_current_data.py | 6 +++ 7 files changed, 68 insertions(+), 16 deletions(-) diff --git a/compiler/datasheet/characterization_corners.py b/compiler/datasheet/characterization_corners.py index 54f75c3f..494b491f 100644 --- a/compiler/datasheet/characterization_corners.py +++ b/compiler/datasheet/characterization_corners.py @@ -1,6 +1,9 @@ from flask_table import * class characterization_corners(Table): + """ + Set up characterization corners table columns and title information + """ corner_name = Col('Corner Name') process = Col('Process') power_supply = Col('Power Supply') @@ -8,6 +11,9 @@ class characterization_corners(Table): library_name_suffix = Col('Library Name Suffix') class characterization_corners_item(object): + """ + Defines the contents of a charcaterization corner table row + """ def __init__(self, corner_name, process, power_supply, temperature, library_name_suffix): self.corner_name = corner_name self.process = process diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index f9edb5da..4a3b3b69 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -8,7 +8,9 @@ import os from globals import OPTS class datasheet(): - + """ + Defines the layout,but not the data, of the html datasheet + """ def __init__(self,identifier): self.io = [] self.corners = [] @@ -20,7 +22,11 @@ class datasheet(): def generate_html(self): + """ + Generates html tables using flask-table + """ with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/datasheet.css', 'r') as datasheet_css: + #css styling is kept in a seperate file self.html += datasheet_css.read() self.html +='

'+ self.name + '.html' + '

' diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index a16959f0..a0826cf8 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -1,13 +1,16 @@ #!/usr/bin/env python3 """ -Datasheet Generator - -TODO: -locate all port elements in .lib -Locate all timing elements in .lib -Diagram generation -Improve css +This is a script to load data from the characterization and layout processes into +a web friendly html datasheet. This script requres the python-flask and flask-table +packages to be installed. """ +#TODO: +#locate all port elements in .lib +#Locate all timing elements in .lib +#Calculate area from .gds file +#Diagram generation +#Improve css + import debug from globals import OPTS @@ -24,10 +27,13 @@ if OPTS.datasheet_gen: from in_out import * else: debug.warning("Python library flask_table not found. Skipping html datasheet generation. This can be installed with pip install flask-table.") - + #make sure appropriate python libraries are installed def process_name(corner): + """ + Expands the names of the characterization corner types into something human friendly + """ if corner == "TT": return "Typical - Typical" if corner == "SS": @@ -37,12 +43,18 @@ def process_name(corner): else: return "custom" -def parse_file(f,pages): +def parse_characterizer_csv(f,pages): + """ + Parses output data of the Liberty file generator in order to construct the timing and + current table + """ with open(f) as csv_file: csv_reader = csv.reader(csv_file, delimiter=',') line_count = 0 for row in csv_reader: found = 0 + + #defines layout of csv file NAME = row[0] NUM_WORDS = row[1] NUM_BANKS = row[2] @@ -65,6 +77,7 @@ def parse_file(f,pages): #if the .lib information is for an existing datasheet compare timing data for item in sheet.operating: + #check if the new corner dataa is worse than the previous worse corner data if item.parameter == 'Operating Temperature': if float(TEMP) > float(item.max): @@ -87,14 +100,17 @@ def parse_file(f,pages): if float(math.floor(1000/float(MIN_PERIOD)) < float(item.max)): item.max = str(math.floor(1000/float(MIN_PERIOD))) except Exception: + #pass if MIN_PERIOD is zero (not supported by analyitcal model) pass - + #regardless of if there is already a corner for the current sram, append the new corner to the datasheet new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,''))) new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) if found == 0: + + #if this is the first corner for this sram, run first time configuration and set up tables new_sheet = datasheet(NAME) pages.append(new_sheet) @@ -106,7 +122,8 @@ def parse_file(f,pages): new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)*','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz')) except Exception: new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)*','','',"unknown",'MHz')) #analytical model fails to provide MIN_PERIOD - + + #place holder timing and current data new_sheet.timing.append(timing_and_current_data_item('Cycle time','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Access time','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Positive clk setup','2','3','4')) @@ -118,6 +135,7 @@ def parse_file(f,pages): new_sheet.timing.append(timing_and_current_data_item('Area','2','3','4')) if not OPTS.netlist_only: + #physical layout files should not be generated in netlist only mode new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','{1}.{2}'.format(OUT_DIR,NAME,'gds'))) new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,NAME,'lef'))) @@ -128,7 +146,7 @@ def parse_file(f,pages): new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) - + #debug table for multiport information new_sheet.io.append(in_out_item('WORD_SIZE',WORD_SIZE)) new_sheet.io.append(in_out_item('NUM_WORDS',NUM_WORDS)) new_sheet.io.append(in_out_item('NUM_BANKS',NUM_BANKS)) @@ -149,11 +167,9 @@ class datasheet_gen(): if not (os.path.isdir(in_dir)): os.mkdir(in_dir) - #if not (os.path.isdir(out_dir)): - # os.mkdir(out_dir) datasheets = [] - parse_file(in_dir + "/datasheet.info", datasheets) + parse_characterizer_csv(in_dir + "/datasheet.info", datasheets) for sheets in datasheets: diff --git a/compiler/datasheet/deliverables.py b/compiler/datasheet/deliverables.py index d5287c3a..9ba3c0e6 100644 --- a/compiler/datasheet/deliverables.py +++ b/compiler/datasheet/deliverables.py @@ -1,12 +1,18 @@ from flask_table import * class deliverables(Table): + """ + Set up delivarables table columns and title information + """ typ = Col('Type') description = Col('Description') link = Col('Link') class deliverables_item(object): + """ + Define deliverables table row elemenent information + """ def __init__(self, typ, description,link): self.typ = typ self.description = description diff --git a/compiler/datasheet/in_out.py b/compiler/datasheet/in_out.py index f656dba6..98ba9fe5 100644 --- a/compiler/datasheet/in_out.py +++ b/compiler/datasheet/in_out.py @@ -1,11 +1,17 @@ from flask_table import * class in_out(Table): + """ + Set up I/O table columns and title information for multiport debugging + """ typ = Col('Type') description = Col('Description') class in_out_item(object): + """ + Define table row element for I/O table + """ def __init__(self, typ, description): self.typ = typ self.description = description diff --git a/compiler/datasheet/operating_conditions.py b/compiler/datasheet/operating_conditions.py index e08adc61..69648174 100644 --- a/compiler/datasheet/operating_conditions.py +++ b/compiler/datasheet/operating_conditions.py @@ -1,6 +1,9 @@ from flask_table import * class operating_conditions(Table): + """ + Set up operating conditions columns and title information + """ parameter = Col('Parameter') min = Col('Min') typ = Col('Typ') @@ -8,6 +11,9 @@ class operating_conditions(Table): units = Col('Units') class operating_conditions_item(object): + """ + Define operating conditions table row element + """ def __init__(self, parameter, min, typ, max, units): self.parameter = parameter self.min = min diff --git a/compiler/datasheet/timing_and_current_data.py b/compiler/datasheet/timing_and_current_data.py index ebf489e8..ff95df49 100644 --- a/compiler/datasheet/timing_and_current_data.py +++ b/compiler/datasheet/timing_and_current_data.py @@ -1,12 +1,18 @@ from flask_table import * class timing_and_current_data(Table): + """ + Set up timing and current table columns and title information + """ parameter = Col('Parameter') min = Col('Min') max = Col('Max') units = Col('Units') class timing_and_current_data_item(object): + """ + Define timing and current data row element + """ def __init__(self, parameter, min, max, units): self.parameter = parameter self.min = min From fe196c23a991602cdcf8685e3effb8fe38dd8e0f Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 30 Oct 2018 22:32:19 -0700 Subject: [PATCH 06/78] added FF timing information --- compiler/characterizer/lib.py | 15 ++++++++-- compiler/datasheet/datasheet_gen.py | 46 +++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 4 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 72cadc45..ac15a23f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -506,7 +506,7 @@ class lib: return datasheet = open(OPTS.openram_temp +'/datasheet.info', 'a+') - datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13}\n".format("sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name), + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13},{14},{15},{16},{17},{18},{19},{20},{21}\n".format("sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name), OPTS.num_words, OPTS.num_banks, OPTS.num_rw_ports, @@ -519,7 +519,18 @@ class lib: round_time(self.char_sram_results["min_period"]), self.out_dir, lib_name, - OPTS.word_size)) + OPTS.word_size, + min(list(map(round_time,self.times["setup_times_LH"]))), + max(list(map(round_time,self.times["setup_times_LH"]))), + + min(list(map(round_time,self.times["setup_times_HL"]))), + max(list(map(round_time,self.times["setup_times_HL"]))), + + min(list(map(round_time,self.times["hold_times_LH"]))), + max(list(map(round_time,self.times["hold_times_LH"]))), + + min(list(map(round_time,self.times["hold_times_HL"]))), + max(list(map(round_time,self.times["hold_times_HL"]))))) datasheet.close() diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index a0826cf8..767990fa 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -69,10 +69,25 @@ def parse_characterizer_csv(f,pages): OUT_DIR = row[11] LIB_NAME = row[12] WORD_SIZE = row[13] + + FF_SETUP_LH_MIN = row[14] + FF_SETUP_LH_MAX = row[15] + + FF_SETUP_HL_MIN = row[16] + FF_SETUP_HL_MAX = row[17] + + FF_HOLD_LH_MIN = row[18] + FF_HOLD_LH_MAX = row[19] + + FF_HOLD_HL_MIN = row[20] + FF_HOLD_HL_MAX = row[21] + + for sheet in pages: if sheet.name == row[0]: + found = 1 #if the .lib information is for an existing datasheet compare timing data @@ -103,6 +118,31 @@ def parse_characterizer_csv(f,pages): #pass if MIN_PERIOD is zero (not supported by analyitcal model) pass + for item in sheet.timing: + if item.paramter == "CSb setup rising": + if float(FF_SETUP_LH_MIN) < float(item.min): + item.min = FF_SETUP_LH + elif float(FF_SETUP_LH_MAX) > float(item.max): + item.max = FF_SETUP_LH + + if item.paramter == "CSb setup falling": + if float(FF_SETUP_HL_MIN) > float(item.min): + item.max = FF_SETUP_HL_MIN + elif float(FF_SETUP_HL_MAX) > float(item.nax): + item.max = FF_SETUP_HL_MAX + + if item.paramter == "CSb hold rising": + if float(FF_HOLD_HL_MIN) > float(item.min): + item.max = FF_SETUP_HL_MIN + elif float(FF_HOLD_HL_MAX) > float(item.nax): + item.max = FF_SETUP_HL_MAX + + if item.paramter == "CSb hold rising": + if float(FF_HOLD_HL_MIN) > float(item.min): + item.max = FF_SETUP_HL_MIN + elif float(FF_HOLD_HL_MAX) > float(item.nax): + item.max = FF_SETUP_HL_MAX + #regardless of if there is already a corner for the current sram, append the new corner to the datasheet new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,''))) @@ -128,8 +168,10 @@ def parse_characterizer_csv(f,pages): new_sheet.timing.append(timing_and_current_data_item('Access time','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Positive clk setup','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Positive clk hold','2','3','4')) - new_sheet.timing.append(timing_and_current_data_item('RW setup','2','3','4')) - new_sheet.timing.append(timing_and_current_data_item('RW hold','2','3','4')) + new_sheet.timing.append(timing_and_current_data_item('CSb setup rising',FF_SETUP_LH_MIN,FF_SETUP_LH_MAX,'ns')) + new_sheet.timing.append(timing_and_current_data_item('CSb setup falling',FF_SETUP_HL_MIN,FF_SETUP_HL_MAX,'ns')) + new_sheet.timing.append(timing_and_current_data_item('CSb hold rising',FF_SETUP_LH_MIN,FF_SETUP_LH_MAX,'ns')) + new_sheet.timing.append(timing_and_current_data_item('CSb hold falling',FF_SETUP_HL_MIN,FF_SETUP_HL_MAX,'ns')) new_sheet.timing.append(timing_and_current_data_item('AC current','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Standby current','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Area','2','3','4')) From 70ac2e8aa4003d4efdf515804dc6db7a55811a96 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 30 Oct 2018 22:56:13 -0700 Subject: [PATCH 07/78] changed css to orange and black for Halloween; fixed CSb timing table in datasheet --- compiler/datasheet/assets/datasheet.css | 4 ++-- compiler/datasheet/datasheet_gen.py | 28 ++++++++++++------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/compiler/datasheet/assets/datasheet.css b/compiler/datasheet/assets/datasheet.css index 5d5a04e5..5d4f1470 100644 --- a/compiler/datasheet/assets/datasheet.css +++ b/compiler/datasheet/assets/datasheet.css @@ -19,8 +19,8 @@ padding-top: 11px; padding-bottom: 11px; text-align: left; - background-color: #3CAF50; - color: white; + background-color: #FF8C00; + color: black; } diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 767990fa..318d345f 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -81,8 +81,8 @@ def parse_characterizer_csv(f,pages): FF_HOLD_HL_MIN = row[20] FF_HOLD_HL_MAX = row[21] - - + + for sheet in pages: @@ -121,25 +121,25 @@ def parse_characterizer_csv(f,pages): for item in sheet.timing: if item.paramter == "CSb setup rising": if float(FF_SETUP_LH_MIN) < float(item.min): - item.min = FF_SETUP_LH + item.min = FF_SETUP_LH_MIN elif float(FF_SETUP_LH_MAX) > float(item.max): - item.max = FF_SETUP_LH + item.max = FF_SETUP_LH_MAX if item.paramter == "CSb setup falling": - if float(FF_SETUP_HL_MIN) > float(item.min): - item.max = FF_SETUP_HL_MIN + if float(FF_SETUP_HL_MIN) < float(item.min): + item.min = FF_SETUP_HL_MIN elif float(FF_SETUP_HL_MAX) > float(item.nax): item.max = FF_SETUP_HL_MAX if item.paramter == "CSb hold rising": - if float(FF_HOLD_HL_MIN) > float(item.min): - item.max = FF_SETUP_HL_MIN + if float(FF_HOLD_HL_MIN) < float(item.min): + item.min = FF_SETUP_HL_MIN elif float(FF_HOLD_HL_MAX) > float(item.nax): item.max = FF_SETUP_HL_MAX - if item.paramter == "CSb hold rising": - if float(FF_HOLD_HL_MIN) > float(item.min): - item.max = FF_SETUP_HL_MIN + if item.paramter == "CSb hold falling": + if float(FF_HOLD_HL_MIN) < float(item.min): + item.min = FF_SETUP_HL_MIN elif float(FF_HOLD_HL_MAX) > float(item.nax): item.max = FF_SETUP_HL_MAX @@ -149,7 +149,7 @@ def parse_characterizer_csv(f,pages): new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) if found == 0: - + #if this is the first corner for this sram, run first time configuration and set up tables new_sheet = datasheet(NAME) pages.append(new_sheet) @@ -170,8 +170,8 @@ def parse_characterizer_csv(f,pages): new_sheet.timing.append(timing_and_current_data_item('Positive clk hold','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('CSb setup rising',FF_SETUP_LH_MIN,FF_SETUP_LH_MAX,'ns')) new_sheet.timing.append(timing_and_current_data_item('CSb setup falling',FF_SETUP_HL_MIN,FF_SETUP_HL_MAX,'ns')) - new_sheet.timing.append(timing_and_current_data_item('CSb hold rising',FF_SETUP_LH_MIN,FF_SETUP_LH_MAX,'ns')) - new_sheet.timing.append(timing_and_current_data_item('CSb hold falling',FF_SETUP_HL_MIN,FF_SETUP_HL_MAX,'ns')) + new_sheet.timing.append(timing_and_current_data_item('CSb hold rising',FF_HOLD_LH_MIN,FF_HOLD_LH_MAX,'ns')) + new_sheet.timing.append(timing_and_current_data_item('CSb hold falling',FF_HOLD_HL_MIN,FF_HOLD_HL_MAX,'ns')) new_sheet.timing.append(timing_and_current_data_item('AC current','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Standby current','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Area','2','3','4')) From 5302fd205f313a12e46fe567d60bbcf2ac456d35 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 30 Oct 2018 23:03:05 -0700 Subject: [PATCH 08/78] fixed some final typos in datasheet --- compiler/datasheet/datasheet_gen.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 318d345f..0b63fbae 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -119,28 +119,28 @@ def parse_characterizer_csv(f,pages): pass for item in sheet.timing: - if item.paramter == "CSb setup rising": + if item.parameter == "CSb setup rising": if float(FF_SETUP_LH_MIN) < float(item.min): item.min = FF_SETUP_LH_MIN elif float(FF_SETUP_LH_MAX) > float(item.max): item.max = FF_SETUP_LH_MAX - if item.paramter == "CSb setup falling": + if item.parameter == "CSb setup falling": if float(FF_SETUP_HL_MIN) < float(item.min): item.min = FF_SETUP_HL_MIN - elif float(FF_SETUP_HL_MAX) > float(item.nax): + elif float(FF_SETUP_HL_MAX) > float(item.max): item.max = FF_SETUP_HL_MAX - if item.paramter == "CSb hold rising": + if item.parameter == "CSb hold rising": if float(FF_HOLD_HL_MIN) < float(item.min): item.min = FF_SETUP_HL_MIN - elif float(FF_HOLD_HL_MAX) > float(item.nax): + elif float(FF_HOLD_HL_MAX) > float(item.max): item.max = FF_SETUP_HL_MAX - if item.paramter == "CSb hold falling": + if item.parameter == "CSb hold falling": if float(FF_HOLD_HL_MIN) < float(item.min): item.min = FF_SETUP_HL_MIN - elif float(FF_HOLD_HL_MAX) > float(item.nax): + elif float(FF_HOLD_HL_MAX) > float(item.max): item.max = FF_SETUP_HL_MAX From 673027ac8cfbd2cc2641f12dab0519cd3c5b86ce Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 31 Oct 2018 09:37:47 -0700 Subject: [PATCH 09/78] Moved assert to check out_path earlier. Preserve temporary output directory with -d option. --- compiler/tests/30_openram_test.py | 33 ++++++++++++++++++------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 038a2e15..ab0aa4d8 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -36,21 +36,27 @@ class openram_test(openram_test): os.chmod(out_path, 0o0750) # specify the same verbosity for the system call - verbosity = "" + opts = "" for i in range(OPTS.debug_level): - verbosity += " -v" - + opts += " -v" + # keep the temp directory around + if not OPTS.purge_temp: + opts += " -d" + OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) cmd = "python3 {0}/openram.py -n -o {1} -p {2} {3} config_20_{4}.py 2>&1 > {5}/output.log".format(OPENRAM_HOME, - out_file, - out_path, - verbosity, - OPTS.tech_name, - out_path) + out_file, + out_path, + opts, + OPTS.tech_name, + out_path) debug.info(1, cmd) os.system(cmd) + + # check that the output path was created + self.assertEqual(os.path.exists(out_path),True) # assert an error until we actually check a resul for extension in ["gds", "v", "lef", "sp"]: @@ -64,9 +70,8 @@ class openram_test(openram_test): self.assertTrue(len(files)>0) # Make sure there is any .html file - if os.path.exists(out_path): - datasheets = glob.glob('{0}/*html'.format(out_path)) - self.assertTrue(len(datasheets)>0) + datasheets = glob.glob('{0}/*html'.format(out_path)) + self.assertTrue(len(datasheets)>0) # grep any errors from the output output_log = open("{0}/output.log".format(out_path),"r") @@ -76,10 +81,10 @@ class openram_test(openram_test): self.assertEqual(len(re.findall('WARNING',output)),0) - # now clean up the directory - if os.path.exists(out_path): + # now clean up the output directory (or preserve if specified to preserve temp dirs) + if os.path.exists(out_path) and OPTS.purge_temp: shutil.rmtree(out_path, ignore_errors=True) - self.assertEqual(os.path.exists(out_path),False) + self.assertEqual(os.path.exists(out_path),False) globals.end_openram() From c3d7e24df9cb528db04ed759981eb45817b94e36 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 31 Oct 2018 09:34:36 -0700 Subject: [PATCH 10/78] fixed broken links when -o flag set --- compiler/datasheet/datasheet_gen.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 0b63fbae..125511f4 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -178,13 +178,13 @@ def parse_characterizer_csv(f,pages): if not OPTS.netlist_only: #physical layout files should not be generated in netlist only mode - new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','{1}.{2}'.format(OUT_DIR,NAME,'gds'))) - new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,NAME,'lef'))) + new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'gds'))) + new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'lef'))) - new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{1}.{2}'.format(OUT_DIR,NAME,'sp'))) - new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{1}.{2}'.format(OUT_DIR,NAME,'v'))) - new_sheet.dlv.append(deliverables_item('.html','This datasheet','{1}.{2}'.format(OUT_DIR,NAME,'html'))) + new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'sp'))) + new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'v'))) + new_sheet.dlv.append(deliverables_item('.html','This datasheet','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'html'))) new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) From ce5001e0afba51d0272ec60b8091ee01c0185f13 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 31 Oct 2018 12:29:13 -0700 Subject: [PATCH 11/78] added config file to datasheet and output files --- compiler/datasheet/datasheet.py | 14 +++++++++++++- compiler/datasheet/datasheet_gen.py | 4 +++- compiler/globals.py | 3 ++- compiler/openram.py | 2 +- compiler/sram.py | 10 +++++++++- 5 files changed, 28 insertions(+), 5 deletions(-) diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 4a3b3b69..700babbb 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -28,8 +28,20 @@ class datasheet(): with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/datasheet.css', 'r') as datasheet_css: #css styling is kept in a seperate file self.html += datasheet_css.read() - + +# if OPTS.check_lvsdrc: +# DVS = 'checked' +# LVS = 'checked' +# PEX = 'checked' +# else: +# DVS = 'skipped' +# LVS = 'skipped' +# PEX = 'skipped' + + self.html +='

'+ self.name + '.html' + '

' +# self.html +='

'+ 'DVS: ' + DVS + '

' +# self.html +='

'+ 'LVS: ' + LVS + '

' self.html +='

Ports and Configuration (DEBUG)

' self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">") diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 125511f4..4609514e 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -185,7 +185,9 @@ def parse_characterizer_csv(f,pages): new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'sp'))) new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'v'))) new_sheet.dlv.append(deliverables_item('.html','This datasheet','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'html'))) - new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) + new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'lib')))) + new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'py'))) + #debug table for multiport information diff --git a/compiler/globals.py b/compiler/globals.py index 0b04079b..887b092e 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -197,6 +197,7 @@ def read_config(config_file, is_unit_test=True): config_file = re.sub(r'\.py$', "", config_file) # Expand the user if it is used config_file = os.path.expanduser(config_file) + OPTS.config_file = config_file # Add the path to the system path so we can import things in the other directory dir_name = os.path.dirname(config_file) file_name = os.path.basename(config_file) @@ -244,7 +245,7 @@ def read_config(config_file, is_unit_test=True): OPTS.num_words, ports, OPTS.tech_name) - + def end_openram(): diff --git a/compiler/openram.py b/compiler/openram.py index ee43749f..d419ea4b 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -39,7 +39,7 @@ import verify from sram import sram from sram_config import sram_config #from parser import * -output_extensions = ["sp","v","lib"] +output_extensions = ["sp","v","lib","py"] if OPTS.datasheet_gen: output_extensions.append("html") if not OPTS.netlist_only: diff --git a/compiler/sram.py b/compiler/sram.py index 1b6b104f..1ae11762 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -108,7 +108,15 @@ class sram(): print("Trimming netlist to speed up characterization.") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) - + + + # Write the config file + start_time = datetime.datetime.now() + from shutil import copyfile + copyfile(OPTS.config_file + '.py', OPTS.output_path + OPTS.output_name + '.py') + print("Config: writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) + print_time("Config", datetime.datetime.now(), start_time) + # Write the datasheet start_time = datetime.datetime.now() from datasheet_gen import datasheet_gen From 3fa1d5522e2bded2e87d860a11021573fe4a6ee0 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 1 Nov 2018 14:02:33 -0700 Subject: [PATCH 12/78] added DRC/LVS error count to datasheet --- compiler/base/hierarchy_design.py | 25 +++++++++++++++++++------ compiler/datasheet/datasheet.py | 25 ++++++++++++++----------- 2 files changed, 33 insertions(+), 17 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 320276cc..9eefc564 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -6,6 +6,8 @@ import debug import os from globals import OPTS +total_drc_errors = 0 +total_lvs_errors = 0 class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): """ @@ -13,7 +15,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): Class consisting of a set of modules and instances of these modules """ name_map = [] - def __init__(self, name): try: @@ -28,8 +29,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): self.name = name hierarchy_layout.layout.__init__(self, name) hierarchy_spice.spice.__init__(self, name) - + # Check if the name already exists, if so, give an error # because each reference must be a unique name. # These modules ensure unique names or have no changes if they @@ -70,12 +71,18 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Unit tests will check themselves. # Do not run if disabled in options. if not OPTS.is_unit_test and OPTS.check_lvsdrc: + global total_drc_errors + global total_lvs_errors tempspice = OPTS.openram_temp + "/temp.sp" tempgds = OPTS.openram_temp + "/temp.gds" self.sp_write(tempspice) self.gds_write(tempgds) - debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name)) - debug.check(verify.run_lvs(self.name, tempgds, tempspice, final_verification) == 0,"LVS failed for {0}".format(self.name)) + num_drc_errors = verify.run_drc(self.name, tempgds) + num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification) + debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors)) + debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors)) + total_drc_errors += num_drc_errors + total_lvs_errors += num_lvs_errors os.remove(tempspice) os.remove(tempgds) @@ -84,9 +91,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Unit tests will check themselves. # Do not run if disabled in options. if not OPTS.is_unit_test and OPTS.check_lvsdrc: + global total_drc_errors tempgds = OPTS.openram_temp + "/temp.gds" self.gds_write(tempgds) - debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name)) + num_errors = verify.run_drc(self.name, tempgds) + total_drc_errors += num_errors + debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error)) os.remove(tempgds) def LVS(self, final_verification=False): @@ -94,11 +104,14 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Unit tests will check themselves. # Do not run if disabled in options. if not OPTS.is_unit_test and OPTS.check_lvsdrc: + global total_lvs_errors tempspice = OPTS.openram_temp + "/temp.sp" tempgds = OPTS.openram_temp + "/temp.gds" self.sp_write(tempspice) self.gds_write(tempgds) - debug.check(verify.run_lvs(self.name, tempgds, tempspice, final_verification) == 0,"LVS failed for {0}".format(self.name)) + num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification) + total_lvs_errors += num_errors + debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors)) os.remove(tempspice) os.remove(tempgds) diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 700babbb..beded426 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -4,6 +4,8 @@ from characterization_corners import * from deliverables import * from timing_and_current_data import * from in_out import * +from hierarchy_design import total_drc_errors +from hierarchy_design import total_lvs_errors import os from globals import OPTS @@ -29,19 +31,20 @@ class datasheet(): #css styling is kept in a seperate file self.html += datasheet_css.read() -# if OPTS.check_lvsdrc: -# DVS = 'checked' -# LVS = 'checked' -# PEX = 'checked' -# else: -# DVS = 'skipped' -# LVS = 'skipped' -# PEX = 'skipped' - + if OPTS.check_lvsdrc: + + DRC = total_drc_errors + LVS = total_lvs_errors + PEX = 'n/a' + else: + DRC = 'skipped' + LVS = 'skipped' + PEX = 'skipped' + self.html +='

'+ self.name + '.html' + '

' -# self.html +='

'+ 'DVS: ' + DVS + '

' -# self.html +='

'+ 'LVS: ' + LVS + '

' + self.html +='

'+ 'DRC: ' + str(DRC) + ' errors'+'

' + self.html +='

'+ 'LVS: ' + str(LVS) + ' errors'+'

' self.html +='

Ports and Configuration (DEBUG)

' self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">") From d6c0247ff27ee4961c89bf872588661e5877baa0 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 8 Nov 2018 21:30:17 -0800 Subject: [PATCH 13/78] added area to datasheet --- compiler/characterizer/lib.py | 1 + compiler/datasheet/datasheet_gen.py | 12 ++++++------ compiler/sram.py | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index ac15a23f..3441156f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -502,6 +502,7 @@ class lib: def parse_info(self,corner,lib_name): + """ Copies important characterization data to datasheet.info to be added to datasheet """ if OPTS.is_unit_test: return datasheet = open(OPTS.openram_temp +'/datasheet.info', 'a+') diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 4609514e..5f163904 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -7,7 +7,6 @@ packages to be installed. #TODO: #locate all port elements in .lib #Locate all timing elements in .lib -#Calculate area from .gds file #Diagram generation #Improve css @@ -43,7 +42,7 @@ def process_name(corner): else: return "custom" -def parse_characterizer_csv(f,pages): +def parse_characterizer_csv(sram,f,pages): """ Parses output data of the Liberty file generator in order to construct the timing and current table @@ -174,8 +173,7 @@ def parse_characterizer_csv(f,pages): new_sheet.timing.append(timing_and_current_data_item('CSb hold falling',FF_HOLD_HL_MIN,FF_HOLD_HL_MAX,'ns')) new_sheet.timing.append(timing_and_current_data_item('AC current','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Standby current','2','3','4')) - new_sheet.timing.append(timing_and_current_data_item('Area','2','3','4')) - + if not OPTS.netlist_only: #physical layout files should not be generated in netlist only mode new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'gds'))) @@ -197,13 +195,15 @@ def parse_characterizer_csv(f,pages): new_sheet.io.append(in_out_item('NUM_RW_PORTS',NUM_RW_PORTS)) new_sheet.io.append(in_out_item('NUM_R_PORTS',NUM_R_PORTS)) new_sheet.io.append(in_out_item('NUM_W_PORTS',NUM_W_PORTS)) + new_sheet.io.append(in_out_item('Area',sram.width * sram.height)) + class datasheet_gen(): - def datasheet_write(name): + def datasheet_write(sram,name): if OPTS.datasheet_gen: in_dir = OPTS.openram_temp @@ -213,7 +213,7 @@ class datasheet_gen(): datasheets = [] - parse_characterizer_csv(in_dir + "/datasheet.info", datasheets) + parse_characterizer_csv(sram, in_dir + "/datasheet.info", datasheets) for sheets in datasheets: diff --git a/compiler/sram.py b/compiler/sram.py index 1ae11762..0c977868 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -122,7 +122,7 @@ class sram(): from datasheet_gen import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" print("Datasheet: writing to {0}".format(dname)) - datasheet_gen.datasheet_write(dname) + datasheet_gen.datasheet_write(self.s,dname) print_time("Datasheet", datetime.datetime.now(), start_time) # Write a verilog model From b8061d3a4e03684ff22d9b5fe93d87cab2a774e3 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 8 Nov 2018 00:10:51 -0800 Subject: [PATCH 14/78] Added initial code for determining the logical effort delay of the wordline. --- compiler/bitcells/bitcell.py | 7 +++++- compiler/characterizer/logical_effort.py | 16 ++++++++++++ compiler/modules/bank.py | 14 +++++++++++ compiler/modules/bitcell_array.py | 7 ++++++ compiler/modules/control_logic.py | 10 ++++++++ compiler/modules/dff.py | 12 ++++++--- compiler/modules/dff_array.py | 6 +++++ compiler/modules/dff_inv.py | 3 +++ compiler/modules/dff_inv_array.py | 6 +++++ compiler/modules/wordline_driver.py | 23 +++++++++++++++++ compiler/pgates/pinv.py | 13 +++++++++- compiler/pgates/pinvbuf.py | 11 ++++++++ compiler/pgates/pnand2.py | 11 ++++++++ compiler/sram_base.py | 32 ++++++++++++++++++++++++ technology/freepdk45/tech/tech.py | 4 +++ technology/scn4m_subm/tech/tech.py | 5 ++++ 16 files changed, 174 insertions(+), 6 deletions(-) create mode 100644 compiler/characterizer/logical_effort.py diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index 5df86c87..ef0e8e9d 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -1,7 +1,7 @@ import design import debug import utils -from tech import GDS,layer +from tech import GDS,layer, parameter class bitcell(design.design): """ @@ -93,3 +93,8 @@ class bitcell(design.design): total_power = self.return_power(dynamic, leakage) return total_power + def get_wl_cin(self): + """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" + #This is a handmade cell so the value must be entered in the tech.py file or estimated. + #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. + return parameter["6tcell_wl_cin"] diff --git a/compiler/characterizer/logical_effort.py b/compiler/characterizer/logical_effort.py new file mode 100644 index 00000000..ac6ccbc5 --- /dev/null +++ b/compiler/characterizer/logical_effort.py @@ -0,0 +1,16 @@ +import debug +from tech import drc, parameter, spice + +class logical_effort(): + """ + Class to support the values behind logical effort. Useful for storing the different components + such as logical effort, electrical effort, and parasitic delay. + """ + beta = parameter["beta"] + min_inv_cin = 1+beta + def __init__(self, size, cin, cout, parasitic): + self.cin = cin + self.cout = cout + self.logical_effort = (self.cin/size)/logical_effort.min_inv_cin + self.eletrical_effort = self.cout/self.cin + self.parasitic = parasitic \ No newline at end of file diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 1e9401b8..a369266d 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -950,4 +950,18 @@ class bank(design.design): results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay) return results + + def determine_wordline_stage_efforts(self, external_cout): + """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline""" + #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption + stage_effort_list = [] + wordline_cout = self.bitcell_array.get_wordline_cin() + external_cout + stage_effort_list += self.wordline_driver.determine_wordline_stage_efforts(wordline_cout) + return stage_effort_list + + def get_clk_cin(self): + """Get the relative capacitance of all the clk connections in the bank""" + #Current bank only uses clock (clk_buf) as an enable for the wordline driver. + total_clk_cin = self.wordline_driver.get_clk_cin() + return total_clk_cin \ No newline at end of file diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 8328a0cf..b7c8ffc8 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -225,3 +225,10 @@ class bitcell_array(design.design): def input_load(self): wl_wire = self.gen_wl_wire() return wl_wire.return_input_cap() + + def get_wordline_cin(self): + """Get the relative input capacitance from the wordline connections in all the bitcell""" + #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns + bitcell_wl_cin = self.cell.get_wl_cin() + total_cin = bitcell_wl_cin * self.column_size + return total_cin \ No newline at end of file diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 4ac32967..a2b1dd8d 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -596,4 +596,14 @@ class control_logic(design.design): height=pin.height(), width=pin.width()) + def determine_wordline_stage_efforts(self, external_cout): + """Follows the clock signal to the clk_buf signal adding each stages stage effort to a list""" + stage_effort_list = [] + #Calculate the load on clk_buf within the module and add it to external load + internal_cout = self.ctrl_dff_array.get_clk_cin() + clk_buf_cap = internal_cout+external_cout + #First stage is the clock buffer + stage_effort_list += self.clkbuf.determine_wordline_stage_efforts(clk_buf_cap) + return stage_effort_list + \ No newline at end of file diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 936bc822..19077689 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -2,7 +2,7 @@ import globals import design from math import log import design -from tech import GDS,layer +from tech import GDS,layer,spice,parameter import utils class dff(design.design): @@ -23,7 +23,6 @@ class dff(design.design): def analytical_power(self, proc, vdd, temp, load): """Returns dynamic and leakage power. Results in nW""" - from tech import spice c_eff = self.calculate_effective_capacitance(load) f = spice["default_event_rate"] power_dyn = c_eff*vdd*vdd*f @@ -34,7 +33,7 @@ class dff(design.design): def calculate_effective_capacitance(self, load): """Computes effective capacitance. Results in fF""" - from tech import spice, parameter + from tech import parameter c_load = load c_para = spice["flop_para_cap"]#ff transition_prob = spice["flop_transition_prob"] @@ -42,7 +41,12 @@ class dff(design.design): def analytical_delay(self, slew, load = 0.0): # dont know how to calculate this now, use constant in tech file - from tech import spice result = self.return_delay(spice["dff_delay"], spice["dff_slew"]) return result + + def get_clk_cin(self): + """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" + #This is a handmade cell so the value must be entered in the tech.py file or estimated. + #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. + return parameter["dff_clk_cin"] diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 97e82e24..37d1ad29 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -157,3 +157,9 @@ class dff_array(design.design): def analytical_delay(self, slew, load=0.0): return self.dff.analytical_delay(slew=slew, load=load) + + def get_clk_cin(self): + """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" + dff_clk_cin = self.dff.get_clk_cin() + total_cin = dff_clk_cin * self.rows * self.columns + return total_cin \ No newline at end of file diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 3a06c9c9..366d8647 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -148,3 +148,6 @@ class dff_inv(design.design): inv1_delay = self.inv1.analytical_delay(slew=dff_delay.slew, load=load) return dff_delay + inv1_delay + def get_clk_cin(self): + """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" + return self.dff.get_clk_cin() \ No newline at end of file diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index aafe87e2..36231b26 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -182,3 +182,9 @@ class dff_inv_array(design.design): def analytical_delay(self, slew, load=0.0): return self.dff.analytical_delay(slew=slew, load=load) + + def get_clk_cin(self): + """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" + dff_clk_cin = self.dff.get_clk_cin() + total_cin = dff_clk_cin * self.rows * self.columns + return total_cin \ No newline at end of file diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index dd1039b0..8bc89734 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -238,4 +238,27 @@ class wordline_driver(design.design): def input_load(self): + """Gets the capacitance of the wordline driver in absolute units (fF)""" return self.nand2.input_load() + + def determine_wordline_stage_efforts(self, external_cout): + """Follows the clk_buf to a wordline signal adding each stages stage effort to a list""" + stage_effort_list = [] + stage1_cout = self.nand2.get_cin() + stage1 = self.inv_no_output.get_effort_stage(stage1_cout) + stage_effort_list.append(stage1) + + stage2_cout = self.inv.get_cin() + stage2 = self.nand2.get_effort_stage(stage2_cout) + stage_effort_list.append(stage2) + + stage3 = self.inv.get_effort_stage(external_cout) + stage_effort_list.append(stage3) + + return stage_effort_list + + def get_clk_cin(self): + """Get the relative capacitance of all the clk connections in the bank""" + #Clock is connected as an input to 1 inverter per row + total_cin = self.inv_no_output.get_cin() * self.rows + return total_cin \ No newline at end of file diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 0ffd4f66..4d59b715 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -7,6 +7,7 @@ from vector import vector from math import ceil from globals import OPTS from utils import round_to_grid +import logical_effort class pinv(pgate.pgate): """ @@ -29,7 +30,8 @@ class pinv(pgate.pgate): pinv.unique_id += 1 pgate.pgate.__init__(self, name, height) debug.info(2, "create pinv structure {0} with size of {1}".format(name, size)) - + + self.size = size self.nmos_size = size self.pmos_size = beta*size self.beta = beta @@ -281,3 +283,12 @@ class pinv(pgate.pgate): c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff transition_prob = spice["inv_transition_prob"] return transition_prob*(c_load + c_para) + + def get_cin(self): + """Return the capacitance of the gate connection in generic capacitive units relative to the minimum width of a transistor""" + return self.nmos_size + self.pmos_size + + def get_effort_stage(self, cout): + """Returns an object representing the parameters for delay in tau units.""" + parasitic_delay = 1 + return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay) \ No newline at end of file diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 76b3c929..490812ad 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -187,3 +187,14 @@ class pinvbuf(design.design): inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load) return inv1_delay + inv2_delay + def determine_wordline_stage_efforts(self, external_cout): + """Get the stage efforts of the clk -> clk_buf path""" + stage_effort_list = [] + stage1_cout = self.inv1.get_cin() + self.inv2.get_cin() + stage1 = self.inv.get_effort_stage(stage1_cout) + stage_effort_list.append(stage1) + + stage2 = self.inv2.get_effort_stage(external_cout) + stage_effort_list.append(stage2) + + return stage_effort_list \ No newline at end of file diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 1a31e3be..a79a7264 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -5,6 +5,7 @@ from tech import drc, parameter, spice from ptx import ptx from vector import vector from globals import OPTS +import logical_effort class pnand2(pgate.pgate): """ @@ -21,6 +22,7 @@ class pnand2(pgate.pgate): pgate.pgate.__init__(self, name, height) debug.info(2, "create pnand2 structure {0} with size of {1}".format(name, size)) + self.size = size self.nmos_size = 2*size self.pmos_size = parameter["beta"]*size self.nmos_width = self.nmos_size*drc("minwidth_tx") @@ -242,3 +244,12 @@ class pnand2(pgate.pgate): c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff transition_prob = spice["nand2_transition_prob"] return transition_prob*(c_load + c_para) + + def get_cin(self): + """Return the relative input capacitance of a single input""" + return self.nmos_size+self.pmos_size + + def get_effort_stage(self, cout): + """Returns an object representing the parameters for delay in tau units.""" + parasitic_delay = 2 + return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay) \ No newline at end of file diff --git a/compiler/sram_base.py b/compiler/sram_base.py index a1be1f30..de755f90 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -455,4 +455,36 @@ class sram_base(design): """ LH and HL are the same in analytical model. """ return self.bank.analytical_delay(vdd,slew,load) + def calculate_delay_to_wl(self): + stage_efforts = self.determine_wordline_stage_efforts() + return 0 + def determine_wordline_stage_efforts(self): + """Get the all the stage efforts for each stage in the path from clk to a wordline""" + stage_effort_list = [] + clk_buf_cout = self.get_clk_cin() + #Assume rw only. There are important differences with multiport that will need to be accounted for. + if self.control_logic_rw != None: + stage_effort_list += self.control_logic_rw.determine_wordline_stage_efforts(clk_buf_cout) + else: + stage_effort_list += self.control_logic_r.determine_wordline_stage_efforts(clk_buf_cout) + + #Clk_buf then move to the bank/wordline driver. Get the delay stages there. + external_wordline_cout = 0 #No loading on the wordline other than in the bank. + stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout) + + return stage_effort_list + + def get_clk_cin(self): + """Gets the capacitive load the of clock (clk_buf) for the sram""" + #As clk_buf is an output of the control logic. The cap for that module is not determined here. + row_addr_clk_cin = self.row_addr_dff.get_clk_cin() + data_clk_cin = self.data_dff.get_clk_cin() + col_addr_clk_cin = 0 + if self.col_addr_size > 0: + col_addr_clk_cin = self.col_addr_dff.get_clk_cin() + + #Bank cin... + bank_clk_cin = self.bank.get_clk_cin() + + return row_addr_clk_cin + data_clk_cin + col_addr_clk_cin + bank_clk_cin diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 6cbeabdd..dd83793b 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -328,6 +328,10 @@ spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input na spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. +#Logical Effort relative values for the Handmade cells +spice["dff_clk_cin"] = 30.6 +parameter["6tcell_wl_cin"] = 3 + ################################################### ##END Spice Simulation Parameters ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 25afd844..d61ea5a4 100755 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -293,6 +293,11 @@ spice["inv_transition_prob"] = .5 # Transition probability of inverter. spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. + +#Logical Effort relative values for the Handmade cells +parameter["dff_clk_cin"] = 27.5 +parameter["6tcell_wl_cin"] = 2 + ################################################### ##END Spice Simulation Parameters ################################################### From 8957c556dbb8119c7e479c36b34ae6fad1306711 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 8 Nov 2018 20:47:34 -0800 Subject: [PATCH 15/78] Added sense amp enable delay calculation. --- compiler/bitcells/bitcell.py | 9 ++-- compiler/bitcells/bitcell_1rw_1r.py | 9 +++- compiler/bitcells/pbitcell.py | 8 +++- compiler/bitcells/replica_bitcell.py | 9 +++- compiler/bitcells/replica_bitcell_1rw_1r.py | 10 +++- compiler/bitcells/replica_pbitcell.py | 8 +++- compiler/characterizer/logical_effort.py | 21 +++++++- compiler/modules/bank.py | 17 ++++++- compiler/modules/control_logic.py | 48 ++++++++++++++++++- compiler/modules/delay_chain.py | 17 +++++++ compiler/modules/precharge_array.py | 6 +++ compiler/modules/replica_bitline.py | 27 ++++++++++- compiler/modules/sense_amp.py | 8 +++- compiler/modules/sense_amp_array.py | 4 ++ compiler/pgates/pinvbuf.py | 18 ++++++- compiler/pgates/pnand3.py | 10 ++++ compiler/pgates/precharge.py | 6 +++ compiler/pgates/ptx.py | 4 +- compiler/sram_base.py | 53 ++++++++++++++++++--- technology/freepdk45/tech/tech.py | 7 ++- technology/scn4m_subm/tech/tech.py | 3 ++ 21 files changed, 276 insertions(+), 26 deletions(-) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index ef0e8e9d..44b01cfe 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -1,7 +1,7 @@ import design import debug import utils -from tech import GDS,layer, parameter +from tech import GDS,layer,parameter,drc class bitcell(design.design): """ @@ -94,7 +94,8 @@ class bitcell(design.design): return total_power def get_wl_cin(self): - """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" + """Return the relative capacitance of the access transistor gates""" #This is a handmade cell so the value must be entered in the tech.py file or estimated. - #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width. - return parameter["6tcell_wl_cin"] + #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width. + access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] + return 2*access_tx_cin diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index 47ebe5fc..2d740d2b 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -1,7 +1,7 @@ import design import debug import utils -from tech import GDS,layer +from tech import GDS,layer,parameter,drc class bitcell_1rw_1r(design.design): """ @@ -96,3 +96,10 @@ class bitcell_1rw_1r(design.design): total_power = self.return_power(dynamic, leakage) return total_power + def get_wl_cin(self): + """Return the relative capacitance of the access transistor gates""" + #This is a handmade cell so the value must be entered in the tech.py file or estimated. + #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width. + #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed. + access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] + return 2*access_tx_cin \ No newline at end of file diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index aa860a1f..feb0d8c5 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -905,4 +905,10 @@ class pbitcell(design.design): leakage = spice["bitcell_leakage"] dynamic = 0 #temporary total_power = self.return_power(dynamic, leakage) - return total_power \ No newline at end of file + return total_power + + def get_wl_cin(self): + """Return the relative capacitance of the access transistor gates""" + #pbitcell uses the different sizing for the port access tx's. Not accounted for in this model. + access_tx_cin = self.readwrite_nmos.get_cin() + return 2*access_tx_cin \ No newline at end of file diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index ca4b72c0..d896e29e 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -1,7 +1,7 @@ import design import debug import utils -from tech import GDS,layer +from tech import GDS,layer,drc,parameter class replica_bitcell(design.design): """ @@ -21,3 +21,10 @@ class replica_bitcell(design.design): self.width = replica_bitcell.width self.height = replica_bitcell.height self.pin_map = replica_bitcell.pin_map + + def get_wl_cin(self): + """Return the relative capacitance of the access transistor gates""" + #This is a handmade cell so the value must be entered in the tech.py file or estimated. + #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width. + access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] + return 2*access_tx_cin \ No newline at end of file diff --git a/compiler/bitcells/replica_bitcell_1rw_1r.py b/compiler/bitcells/replica_bitcell_1rw_1r.py index aaf5b1dc..f5151958 100644 --- a/compiler/bitcells/replica_bitcell_1rw_1r.py +++ b/compiler/bitcells/replica_bitcell_1rw_1r.py @@ -1,7 +1,7 @@ import design import debug import utils -from tech import GDS,layer +from tech import GDS,layer,drc,parameter class replica_bitcell_1rw_1r(design.design): """ @@ -21,3 +21,11 @@ class replica_bitcell_1rw_1r(design.design): self.width = replica_bitcell_1rw_1r.width self.height = replica_bitcell_1rw_1r.height self.pin_map = replica_bitcell_1rw_1r.pin_map + + def get_wl_cin(self): + """Return the relative capacitance of the access transistor gates""" + #This is a handmade cell so the value must be entered in the tech.py file or estimated. + #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width. + #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed. + access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] + return 2*access_tx_cin \ No newline at end of file diff --git a/compiler/bitcells/replica_pbitcell.py b/compiler/bitcells/replica_pbitcell.py index 4b92d487..666d3646 100644 --- a/compiler/bitcells/replica_pbitcell.py +++ b/compiler/bitcells/replica_pbitcell.py @@ -1,6 +1,6 @@ import debug import design -from tech import drc, spice +from tech import drc, spice,parameter from vector import vector from globals import OPTS from pbitcell import pbitcell @@ -79,4 +79,8 @@ class replica_pbitcell(design.design): self.copy_layout_pin(self.prbc_inst, "wl{}".format(port)) self.copy_layout_pin(self.prbc_inst, "vdd") self.copy_layout_pin(self.prbc_inst, "gnd") - \ No newline at end of file + + def get_wl_cin(self): + """Return the relative capacitance of the access transistor gates""" + #This module is made using a pbitcell. Get the cin from that module + return self.prbc.get_wl_cin() \ No newline at end of file diff --git a/compiler/characterizer/logical_effort.py b/compiler/characterizer/logical_effort.py index ac6ccbc5..d0f32eb7 100644 --- a/compiler/characterizer/logical_effort.py +++ b/compiler/characterizer/logical_effort.py @@ -13,4 +13,23 @@ class logical_effort(): self.cout = cout self.logical_effort = (self.cin/size)/logical_effort.min_inv_cin self.eletrical_effort = self.cout/self.cin - self.parasitic = parasitic \ No newline at end of file + self.parasitic_scale = parasitic + + def __str__(self): + return "g = " + str(self.logical_effort) + ", h = " + str(self.eletrical_effort) + ", p = " + str(self.parasitic_scale)+"*pinv" + + def get_stage_effort(self): + return self.logical_effort*self.eletrical_effort + + def get_parasitic_delay(self, pinv): + return pinv * self.parasitic_scale + + def get_stage_delay(self, pinv): + return self.get_stage_effort()+self.get_parasitic_delay(pinv) + +def calculate_relative_delay(stage_effort_list, pinv=parameter["min_inv_para_delay"]): + """Calculates the total delay of a given delay path made of a list of logical effort objects.""" + total_delay = 0 + for stage in stage_effort_list: + total_delay += stage.get_stage_delay(pinv) + return total_delay \ No newline at end of file diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index a369266d..e082aeef 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -964,4 +964,19 @@ class bank(design.design): """Get the relative capacitance of all the clk connections in the bank""" #Current bank only uses clock (clk_buf) as an enable for the wordline driver. total_clk_cin = self.wordline_driver.get_clk_cin() - return total_clk_cin \ No newline at end of file + return total_clk_cin + + def get_clk_bar_cin(self): + """Get the relative capacitance of all the clk_bar connections in the bank""" + #Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array. + + #Assume single port + port = 0 + total_clk_bar_cin = self.precharge_array[port].get_en_cin() + return total_clk_bar_cin + + def get_sen_cin(self): + """Get the relative capacitance of all the sense amp enable connections in the bank""" + #Current bank only uses sen as an enable for the sense amps. + total_sen_cin = self.sense_amp_array.get_en_cin() + return total_sen_cin \ No newline at end of file diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index a2b1dd8d..49e051dd 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -603,7 +603,51 @@ class control_logic(design.design): internal_cout = self.ctrl_dff_array.get_clk_cin() clk_buf_cap = internal_cout+external_cout #First stage is the clock buffer - stage_effort_list += self.clkbuf.determine_wordline_stage_efforts(clk_buf_cap) + stage_effort_list += self.clkbuf.determine_clk_buf_stage_efforts(clk_buf_cap) return stage_effort_list - \ No newline at end of file + + def determine_sa_enable_stage_efforts(self, ext_clk_buf_cout, ext_sen_cout): + """Follows the clock signal to the sense amp enable signal adding each stages stage effort to a list""" + stage_effort_list = [] + #Calculate the load on clk_buf_bar + int_clk_buf_cout = self.get_clk_buf_bar_cin() + clk_buf_bar_cout = int_clk_buf_cout+ext_clk_buf_cout + #First stage is the clock buffer + stage1 = self.clkbuf.determine_clk_buf_bar_stage_efforts(clk_buf_bar_cout) + stage_effort_list += stage1 + + #nand2 stage + stage2_cout = self.inv1.get_cin() + stage2 = self.nand2.get_effort_stage(stage2_cout) + stage_effort_list.append(stage2) + + #inverter stage + stage3_cout = self.replica_bitline.get_en_cin() + stage3 = self.inv1.get_effort_stage(stage3_cout) + stage_effort_list.append(stage3) + + #Replica bitline stage + stage4_cout = self.inv2.get_cin() + stage4 = self.replica_bitline.determine_sen_stage_efforts(stage4_cout) + stage_effort_list += stage4 + + #inverter (inv2) stage + stage5_cout = self.inv8.get_cin() + stage5 = self.inv2.get_effort_stage(stage5_cout) + stage_effort_list.append(stage5) + + #inverter (inv8) stage, s_en output + stage6 = self.inv8.get_effort_stage(ext_sen_cout) + stage_effort_list.append(stage6) + return stage_effort_list + + def get_clk_buf_bar_cin(self): + """Get the relative capacitance off the clk_buf_bar signal internal to the control logic""" + we_nand_cin = self.nand2.get_cin() + if self.port_type == "rw": + nand_mod = self.nand3 + else: + nand_mod = self.nand2 + sen_nand_cin = nand_mod.get_cin() + return we_nand_cin + sen_nand_cin \ No newline at end of file diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index f02daecb..72dfe93a 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -219,4 +219,21 @@ class delay_chain(design.design): start=mid_point, end=mid_point.scale(1,0)) + def get_cin(self): + """Get the enable input ralative capacitance""" + #Only 1 input to the delay chain which is connected to an inverter. + dc_cin = self.inv.get_cin() + return dc_cin + + def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout): + """Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load.""" + stage_effort_list = [] + #Add a stage to the list for every stage in delay chain. Stages only differ in fanout except the last which has an external cout. + for stage_fanout in self.fanout_list: + stage_cout = self.inv.get_cin()*(stage_fanout+1) + if len(stage_effort_list) == len(self.fanout_list)-1: #last stage + stage_cout+=ext_delayed_en_cout + stage = self.inv.get_effort_stage(stage_cout) + stage_effort_list.append(stage) + return stage_effort_list \ No newline at end of file diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 7e0ee718..0b62525c 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -102,3 +102,9 @@ class precharge_array(design.design): for i in range(self.columns): offset = vector(self.pc_cell.width * i, 0) self.local_insts[i].place(offset) + + def get_en_cin(self): + """Get the relative capacitance of all the clk connections in the precharge array""" + #Assume single port + precharge_en_cin = self.pc_cell.get_en_cin() + return precharge_en_cin*self.columns \ No newline at end of file diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index 84aaa63d..c4019cd5 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -608,4 +608,29 @@ class replica_bitline(design.design): offset=pin.ll(), height=pin.height(), width=pin.width()) - + + def get_en_cin(self): + """Get the enable input relative capacitance""" + #The enable is only connected to the delay, get the cin from that module + en_cin = self.delay_chain.get_cin() + return en_cin + + def determine_sen_stage_efforts(self, ext_cout): + """Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load.""" + stage_effort_list = [] + #Stage 1 is the delay chain + stage1_cout = self.get_delayed_en_cin() + stage1 = self.delay_chain.determine_delayed_en_stage_efforts(stage1_cout) + stage_effort_list += stage1 + + #The delay chain triggers the enable on the replica bitline (rbl). This is used to track the bitline delay whereas this + #model is intended to track every but that. Therefore, the next stage is the inverter after the rbl. + stage2 = self.inv.get_effort_stage(ext_cout) + stage_effort_list.append(stage2) + + return stage_effort_list + + def get_delayed_en_cin(self): + access_tx_cin = self.access_tx.get_cin() + rbc_cin = self.replica_bitcell.get_wl_cin() + return access_tx_cin + rbc_cin \ No newline at end of file diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index e2a0e131..01477917 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -1,7 +1,7 @@ import design import debug import utils -from tech import GDS,layer +from tech import GDS,layer, parameter,drc class sense_amp(design.design): """ @@ -41,3 +41,9 @@ class sense_amp(design.design): #Power in this module currently not defined. Returns 0 nW (leakage and dynamic). total_power = self.return_power() return total_power + + def get_en_cin(self): + """Get the relative capacitance of sense amp enable gate cin""" + pmos_cin = parameter["sa_en_pmos_size"]/drc("minwidth_tx") + nmos_cin = parameter["sa_en_nmos_size"]/drc("minwidth_tx") + return 2*pmos_cin + nmos_cin \ No newline at end of file diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 1bbbf02e..806acf71 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -140,3 +140,7 @@ class sense_amp_array(design.design): def analytical_delay(self, slew, load=0.0): return self.amp.analytical_delay(slew=slew, load=load) + def get_en_cin(self): + """Get the relative capacitance of all the sense amp enable connections in the array""" + sense_amp_en_cin = self.amp.get_en_cin() + return sense_amp_en_cin * self.words_per_row \ No newline at end of file diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 490812ad..23826cd2 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -187,7 +187,7 @@ class pinvbuf(design.design): inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load) return inv1_delay + inv2_delay - def determine_wordline_stage_efforts(self, external_cout): + def determine_clk_buf_stage_efforts(self, external_cout): """Get the stage efforts of the clk -> clk_buf path""" stage_effort_list = [] stage1_cout = self.inv1.get_cin() + self.inv2.get_cin() @@ -197,4 +197,20 @@ class pinvbuf(design.design): stage2 = self.inv2.get_effort_stage(external_cout) stage_effort_list.append(stage2) + return stage_effort_list + + def determine_clk_buf_bar_stage_efforts(self, external_cout): + """Get the stage efforts of the clk -> clk_buf path""" + stage_effort_list = [] + stage1_cout = self.inv1.get_cin() + self.inv2.get_cin() + stage1 = self.inv.get_effort_stage(stage1_cout) + stage_effort_list.append(stage1) + + stage2_cout = self.inv2.get_cin() + stage2 = self.inv1.get_effort_stage(stage2_cout) + stage_effort_list.append(stage2) + + stage3 = self.inv2.get_effort_stage(external_cout) + stage_effort_list.append(stage3) + return stage_effort_list \ No newline at end of file diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 3247a371..555ee5b0 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -23,6 +23,7 @@ class pnand3(pgate.pgate): # We have trouble pitch matching a 3x sizes to the bitcell... # If we relax this, we could size this better. + self.size = size self.nmos_size = 2*size self.pmos_size = parameter["beta"]*size self.nmos_width = self.nmos_size*drc("minwidth_tx") @@ -261,3 +262,12 @@ class pnand3(pgate.pgate): c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff transition_prob = spice["nand3_transition_prob"] return transition_prob*(c_load + c_para) + + def get_cin(self): + """Return the relative input capacitance of a single input""" + return self.nmos_size+self.pmos_size + + def get_effort_stage(self, cout): + """Returns an object representing the parameters for delay in tau units.""" + parasitic_delay = 3 + return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay) \ No newline at end of file diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index ea67eeb5..0468de2a 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -234,3 +234,9 @@ class precharge(pgate.pgate): width=width, height=height) + def get_en_cin(self): + """Get the relative capacitance of the enable in the precharge cell""" + #The enable connect to three pmos gates. They all use the same size pmos. + pmos_cin = self.pmos.get_cin() + return 3*pmos_cin + \ No newline at end of file diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 07d04028..24f4377a 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -353,4 +353,6 @@ class ptx(design.design): if self.connect_active: self.connect_fingered_active(drain_positions, source_positions) - + def get_cin(self): + """Returns the relative gate cin of the tx""" + return self.tx_width/drc("minwidth_tx") \ No newline at end of file diff --git a/compiler/sram_base.py b/compiler/sram_base.py index de755f90..bcedb6ad 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -5,7 +5,7 @@ import debug from importlib import reload from vector import vector from globals import OPTS, print_time - +import logical_effort from design import design class sram_base(design): @@ -67,7 +67,8 @@ class sram_base(design): # Must create the control logic before pins to get the pins self.add_modules() self.add_pins() - + self.calculate_delay_to_wl() + self.calculate_delay_to_sen() # This is for the lib file if we don't create layout self.width=0 self.height=0 @@ -455,9 +456,12 @@ class sram_base(design): """ LH and HL are the same in analytical model. """ return self.bank.analytical_delay(vdd,slew,load) - def calculate_delay_to_wl(self): + def calculate_delay_to_wl(self): + """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" stage_efforts = self.determine_wordline_stage_efforts() - return 0 + clk_to_wl_delay = logical_effort.calculate_relative_delay(stage_efforts, 0) + debug.info(1, "Clock to wordline delay is {} delay units".format(clk_to_wl_delay)) + return clk_to_wl_delay def determine_wordline_stage_efforts(self): """Get the all the stage efforts for each stage in the path from clk to a wordline""" @@ -483,8 +487,45 @@ class sram_base(design): col_addr_clk_cin = 0 if self.col_addr_size > 0: col_addr_clk_cin = self.col_addr_dff.get_clk_cin() - - #Bank cin... bank_clk_cin = self.bank.get_clk_cin() return row_addr_clk_cin + data_clk_cin + col_addr_clk_cin + bank_clk_cin + + def calculate_delay_to_sen(self): + """Get the delay (in delay units) of the clk to a sense amp enable. + This does not incorporate the delay of the replica bitline. + """ + stage_efforts = self.determine_sa_enable_stage_efforts() + clk_to_sen_delay = logical_effort.calculate_relative_delay(stage_efforts, 0) + debug.info(1, "Clock to s_en delay is {} delay units".format(clk_to_sen_delay)) + return clk_to_sen_delay + + def determine_sa_enable_stage_efforts(self): + """Get the all the stage efforts for each stage in the path from clk to a sense amp enable""" + stage_effort_list = [] + clk_buf_bar_cout = self.get_clk_bar_cin() + clk_sen_cout = self.get_sen_cin() + #Assume rw only. There are important differences with multiport that will need to be accounted for. + if self.control_logic_rw != None: + stage_effort_list += self.control_logic_rw.determine_sa_enable_stage_efforts(clk_buf_bar_cout, clk_sen_cout) + else: + stage_effort_list += self.control_logic_r.determine_sa_enable_stage_efforts(clk_buf_bar_cout, clk_sen_cout) + + return stage_effort_list + + def get_clk_bar_cin(self): + """Gets the capacitive load the of clock (clk_buf_bar) for the sram""" + #As clk_buf_bar is an output of the control logic. The cap for that module is not determined here. + #Only the precharge cells use this signal (other than the control logic) + bank_clk_cin = self.bank.get_clk_bar_cin() + return bank_clk_cin + + def get_sen_cin(self): + """Gets the capacitive load the of sense amp enable for the sram""" + #As clk_buf_bar is an output of the control logic. The cap for that module is not determined here. + #Only the sense_amps use this signal (other than the control logic) + bank_sen_cin = self.bank.get_sen_cin() + return bank_sen_cin + + + \ No newline at end of file diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index dd83793b..14ce1953 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -329,8 +329,11 @@ spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input na spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. #Logical Effort relative values for the Handmade cells -spice["dff_clk_cin"] = 30.6 -parameter["6tcell_wl_cin"] = 3 +parameter["dff_clk_cin"] = 30.6 #relative capacitance +parameter["6tcell_wl_cin"] = 3 #relative capacitance +parameter["min_inv_para_delay"] = .5 #Tau delay units +parameter["sa_en_pmos_size"] = .72 #micro-meters +parameter["sa_en_nmos_size"] = .27 #micro-meters ################################################### ##END Spice Simulation Parameters diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index d61ea5a4..077aa5a4 100755 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -297,6 +297,9 @@ spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input no #Logical Effort relative values for the Handmade cells parameter["dff_clk_cin"] = 27.5 parameter["6tcell_wl_cin"] = 2 +parameter["min_inv_para_delay"] = .5 +parameter["sa_en_pmos_size"] = 24*_lambda_ +parameter["sa_en_nmos_size"] = 9*_lambda_ ################################################### ##END Spice Simulation Parameters From 550d5cc729c13401f9b4273aeebb69f8aa729536 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 9 Nov 2018 16:33:08 -0800 Subject: [PATCH 16/78] Fix path to config file in test 30 --- compiler/tests/30_openram_test.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index a8a16426..afa60216 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -46,12 +46,12 @@ class openram_test(openram_test): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - cmd = "python3 {0}/openram.py -n -o {1} -p {2} {3} config_20_{4}.py 2>&1 > {5}/output.log".format(OPENRAM_HOME, - out_file, - out_path, - opts, - OPTS.tech_name, - out_path) + cmd_string = "python3 {0}/openram.py -n -o {1} -p {2} {3} {0}/tests/config_20_{4}.py 2>&1 > {2}/output.log" + cmd = cmd_string.format(OPENRAM_HOME, + out_file, + out_path, + opts, + OPTS.tech_name) debug.info(1, cmd) os.system(cmd) From ea1a1c7705a00285c0c8cd764146071e894480a2 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 9 Nov 2018 17:14:52 -0800 Subject: [PATCH 17/78] Added delay chain resizing based on analytical delay. --- compiler/characterizer/logical_effort.py | 5 +- compiler/modules/control_logic.py | 90 ++++++++++++++++--- compiler/sram_base.py | 109 ++++++++++++----------- 3 files changed, 137 insertions(+), 67 deletions(-) diff --git a/compiler/characterizer/logical_effort.py b/compiler/characterizer/logical_effort.py index d0f32eb7..7d3a2eb9 100644 --- a/compiler/characterizer/logical_effort.py +++ b/compiler/characterizer/logical_effort.py @@ -8,6 +8,8 @@ class logical_effort(): """ beta = parameter["beta"] min_inv_cin = 1+beta + pinv=parameter["min_inv_para_delay"] + def __init__(self, size, cin, cout, parasitic): self.cin = cin self.cout = cout @@ -32,4 +34,5 @@ def calculate_relative_delay(stage_effort_list, pinv=parameter["min_inv_para_del total_delay = 0 for stage in stage_effort_list: total_delay += stage.get_stage_delay(pinv) - return total_delay \ No newline at end of file + return total_delay + \ No newline at end of file diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 49e051dd..21595698 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -12,13 +12,14 @@ from dff_inv_array import dff_inv_array import math from vector import vector from globals import OPTS +import logical_effort class control_logic(design.design): """ Dynamically generated Control logic for the total SRAM circuit. """ - def __init__(self, num_rows, words_per_row, port_type="rw"): + def __init__(self, num_rows, words_per_row, sram=None, port_type="rw"): """ Constructor """ name = "control_logic_" + port_type design.design.__init__(self, name) @@ -28,6 +29,11 @@ class control_logic(design.design): self.words_per_row = words_per_row self.port_type = port_type + #This is needed to resize the delay chain. Likely to be changed at some point. + self.sram=sram + self.wl_timing_tolerance = 1 #Determines how much larger the sen delay should be. Accounts for possible error in model. + self.parasitic_inv_delay = 0 #Keeping 0 for now until further testing. + if self.port_type == "rw": self.num_control_signals = 2 else: @@ -94,13 +100,19 @@ class control_logic(design.design): c = reload(__import__(OPTS.replica_bitline)) replica_bitline = getattr(c, OPTS.replica_bitline) - delay_stages, delay_fanout = self.get_delay_chain_size() + delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size() bitcell_loads = int(math.ceil(self.num_rows / 2.0)) - self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_"+self.port_type) + self.replica_bitline = replica_bitline(delay_stages_heuristic, delay_fanout_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type) + + if self.sram != None and not self.is_sen_timing_okay(): + #Resize the delay chain (by instantiating a new rbl) if the analytical timing failed. + delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) + self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + self.add_mod(self.replica_bitline) - def get_delay_chain_size(self): - """Determine the size of the delay chain used for the Sense Amp Enable """ + def get_heuristic_delay_chain_size(self): + """Use a basic heuristic to determine the size of the delay chain used for the Sense Amp Enable """ # FIXME: These should be tuned according to the additional size parameters delay_fanout = 3 # This can be anything >=2 # Delay stages Must be non-inverting @@ -112,6 +124,35 @@ class control_logic(design.design): delay_stages = 4 return (delay_stages, delay_fanout) + def is_sen_timing_okay(self): + self.wl_delay = self.get_delay_to_wl() + self.sen_delay = self.get_delay_to_sen() + + #The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before + #a re-size is warranted. + + if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay: + return False + else: + return True + + def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): + """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" + previous_delay_chain_delay = (previous_fanout+1+self.parasitic_inv_delay)*previous_stages + debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) + + delay_fanout = 3 # This can be anything >=2 + #The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each + #inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value + required_delay = self.wl_delay*self.wl_timing_tolerance - (self.sen_delay-previous_delay_chain_delay) + debug.check(required_delay > 0, "Cannot size delay chain to have negative delay") + delay_stages = int(required_delay/(delay_fanout+1+self.parasitic_inv_delay)) + if delay_stages%2 == 1: #force an even number of stages. + delay_stages+=1 + #Fanout can be varied as well but is a little more complicated but potentially optimal. + debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay)) + return (delay_stages, delay_fanout) + def setup_signal_busses(self): """ Setup bus names, determine the size of the busses etc """ @@ -595,26 +636,48 @@ class control_logic(design.design): offset=pin.ll(), height=pin.height(), width=pin.width()) + + def get_delay_to_wl(self): + """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" + debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") + stage_efforts = self.determine_wordline_stage_efforts() + clk_to_wl_delay = logical_effort.calculate_relative_delay(stage_efforts, self.parasitic_inv_delay) + debug.info(1, "Clock to wordline delay is {} delay units".format(clk_to_wl_delay)) + return clk_to_wl_delay - def determine_wordline_stage_efforts(self, external_cout): - """Follows the clock signal to the clk_buf signal adding each stages stage effort to a list""" + def determine_wordline_stage_efforts(self): + """Follows the clock signal to the clk_buf signal to the wordline signal for the total path efforts""" stage_effort_list = [] #Calculate the load on clk_buf within the module and add it to external load internal_cout = self.ctrl_dff_array.get_clk_cin() - clk_buf_cap = internal_cout+external_cout + external_cout = self.sram.get_clk_cin() #First stage is the clock buffer - stage_effort_list += self.clkbuf.determine_clk_buf_stage_efforts(clk_buf_cap) + stage_effort_list += self.clkbuf.determine_clk_buf_stage_efforts(internal_cout+external_cout) + + #Then ask the sram for the other path delays (from the bank) + stage_effort_list += self.sram.determine_wordline_stage_efforts() return stage_effort_list - def determine_sa_enable_stage_efforts(self, ext_clk_buf_cout, ext_sen_cout): + def get_delay_to_sen(self): + """Get the delay (in delay units) of the clk to a sense amp enable. + This does not incorporate the delay of the replica bitline. + """ + debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") + stage_efforts = self.determine_sa_enable_stage_efforts() + clk_to_sen_delay = logical_effort.calculate_relative_delay(stage_efforts, self.parasitic_inv_delay) + debug.info(1, "Clock to s_en delay is {} delay units".format(clk_to_sen_delay)) + return clk_to_sen_delay + + def determine_sa_enable_stage_efforts(self): """Follows the clock signal to the sense amp enable signal adding each stages stage effort to a list""" stage_effort_list = [] #Calculate the load on clk_buf_bar int_clk_buf_cout = self.get_clk_buf_bar_cin() - clk_buf_bar_cout = int_clk_buf_cout+ext_clk_buf_cout + ext_clk_buf_cout = self.sram.get_clk_bar_cin() + #First stage is the clock buffer - stage1 = self.clkbuf.determine_clk_buf_bar_stage_efforts(clk_buf_bar_cout) + stage1 = self.clkbuf.determine_clk_buf_bar_stage_efforts(int_clk_buf_cout+ext_clk_buf_cout) stage_effort_list += stage1 #nand2 stage @@ -638,7 +701,8 @@ class control_logic(design.design): stage_effort_list.append(stage5) #inverter (inv8) stage, s_en output - stage6 = self.inv8.get_effort_stage(ext_sen_cout) + clk_sen_cout = self.sram.get_sen_cin() + stage6 = self.inv8.get_effort_stage(clk_sen_cout) stage_effort_list.append(stage6) return stage_effort_list diff --git a/compiler/sram_base.py b/compiler/sram_base.py index bcedb6ad..7d52e093 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -20,7 +20,9 @@ class sram_base(design): sram_config.set_local_config(self) self.bank_insts = [] - + + #For logical effort delay calculations. + self.all_mods_except_control_done = False def add_pins(self): """ Add pins for entire SRAM. """ @@ -67,8 +69,6 @@ class sram_base(design): # Must create the control logic before pins to get the pins self.add_modules() self.add_pins() - self.calculate_delay_to_wl() - self.calculate_delay_to_sen() # This is for the lib file if we don't create layout self.width=0 self.height=0 @@ -216,22 +216,6 @@ class sram_base(design): c = reload(__import__(OPTS.bitcell)) self.mod_bitcell = getattr(c, OPTS.bitcell) self.bitcell = self.mod_bitcell() - - #c = reload(__import__(OPTS.control_logic)) - #self.mod_control_logic = getattr(c, OPTS.control_logic) - - - from control_logic import control_logic - # Create the control logic module for each port type - if OPTS.num_rw_ports>0: - self.control_logic = self.control_logic_rw = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="rw") - self.add_mod(self.control_logic_rw) - if OPTS.num_w_ports>0: - self.control_logic_w = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="w") - self.add_mod(self.control_logic_w) - if OPTS.num_r_ports>0: - self.control_logic_r = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="r") - self.add_mod(self.control_logic_r) # Create the address and control flops (but not the clk) from dff_array import dff_array @@ -261,7 +245,23 @@ class sram_base(design): self.supply_rail_width = self.bank.supply_rail_width self.supply_rail_pitch = self.bank.supply_rail_pitch + + #The control logic can resize itself based on the other modules. Requires all other modules added before control logic. + self.all_mods_except_control_done = True + #c = reload(__import__(OPTS.control_logic)) + #self.mod_control_logic = getattr(c, OPTS.control_logic) + from control_logic import control_logic + # Create the control logic module for each port type + if OPTS.num_rw_ports>0: + self.control_logic = self.control_logic_rw = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row,sram=self, port_type="rw") + self.add_mod(self.control_logic_rw) + if OPTS.num_w_ports>0: + self.control_logic_w = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row,sram=self, port_type="w") + self.add_mod(self.control_logic_w) + if OPTS.num_r_ports>0: + self.control_logic_r = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row,sram=self, port_type="r") + self.add_mod(self.control_logic_r) def create_bank(self,bank_num): """ Create a bank """ @@ -456,24 +456,26 @@ class sram_base(design): """ LH and HL are the same in analytical model. """ return self.bank.analytical_delay(vdd,slew,load) - def calculate_delay_to_wl(self): - """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" - stage_efforts = self.determine_wordline_stage_efforts() - clk_to_wl_delay = logical_effort.calculate_relative_delay(stage_efforts, 0) - debug.info(1, "Clock to wordline delay is {} delay units".format(clk_to_wl_delay)) - return clk_to_wl_delay + # def get_delay_to_wl(self): + # """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" + # debug.check(self.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") + # stage_efforts = self.determine_wordline_stage_efforts() + # clk_to_wl_delay = logical_effort.calculate_relative_delay(stage_efforts, self.pinv) + # debug.info(1, "Clock to wordline delay is {} delay units".format(clk_to_wl_delay)) + # return clk_to_wl_delay def determine_wordline_stage_efforts(self): - """Get the all the stage efforts for each stage in the path from clk to a wordline""" + """Get the all the stage efforts for each stage in the path from clk_buf to a wordline""" + #clk stage_effort_list = [] - clk_buf_cout = self.get_clk_cin() - #Assume rw only. There are important differences with multiport that will need to be accounted for. - if self.control_logic_rw != None: - stage_effort_list += self.control_logic_rw.determine_wordline_stage_efforts(clk_buf_cout) - else: - stage_effort_list += self.control_logic_r.determine_wordline_stage_efforts(clk_buf_cout) + # clk_buf_cout = self.get_clk_cin() + # #Assume rw only. There are important differences with multiport that will need to be accounted for. + # if self.control_logic_rw != None: + # stage_effort_list += self.control_logic_rw.determine_wordline_stage_efforts(clk_buf_cout) + # else: + # stage_effort_list += self.control_logic_r.determine_wordline_stage_efforts(clk_buf_cout) - #Clk_buf then move to the bank/wordline driver. Get the delay stages there. + #Clk_buf originates from the control logic so only the bank is related to the wordline path external_wordline_cout = 0 #No loading on the wordline other than in the bank. stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout) @@ -491,27 +493,28 @@ class sram_base(design): return row_addr_clk_cin + data_clk_cin + col_addr_clk_cin + bank_clk_cin - def calculate_delay_to_sen(self): - """Get the delay (in delay units) of the clk to a sense amp enable. - This does not incorporate the delay of the replica bitline. - """ - stage_efforts = self.determine_sa_enable_stage_efforts() - clk_to_sen_delay = logical_effort.calculate_relative_delay(stage_efforts, 0) - debug.info(1, "Clock to s_en delay is {} delay units".format(clk_to_sen_delay)) - return clk_to_sen_delay + # def get_delay_to_sen(self): + # """Get the delay (in delay units) of the clk to a sense amp enable. + # This does not incorporate the delay of the replica bitline. + # """ + # debug.check(self.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") + # stage_efforts = self.determine_sa_enable_stage_efforts() + # clk_to_sen_delay = logical_effort.calculate_relative_delay(stage_efforts, self.pinv) + # debug.info(1, "Clock to s_en delay is {} delay units".format(clk_to_sen_delay)) + # return clk_to_sen_delay - def determine_sa_enable_stage_efforts(self): - """Get the all the stage efforts for each stage in the path from clk to a sense amp enable""" - stage_effort_list = [] - clk_buf_bar_cout = self.get_clk_bar_cin() - clk_sen_cout = self.get_sen_cin() - #Assume rw only. There are important differences with multiport that will need to be accounted for. - if self.control_logic_rw != None: - stage_effort_list += self.control_logic_rw.determine_sa_enable_stage_efforts(clk_buf_bar_cout, clk_sen_cout) - else: - stage_effort_list += self.control_logic_r.determine_sa_enable_stage_efforts(clk_buf_bar_cout, clk_sen_cout) + # def determine_sa_enable_stage_efforts(self): + # """Get the all the stage efforts for each stage in the path from clk to a sense amp enable""" + # stage_effort_list = [] + # clk_buf_bar_cout = self.get_clk_bar_cin() + # clk_sen_cout = self.get_sen_cin() + # #Assume rw only. There are important differences with multiport that will need to be accounted for. + # if self.control_logic_rw != None: + # stage_effort_list += self.control_logic_rw.determine_sa_enable_stage_efforts(clk_buf_bar_cout, clk_sen_cout) + # else: + # stage_effort_list += self.control_logic_r.determine_sa_enable_stage_efforts(clk_buf_bar_cout, clk_sen_cout) - return stage_effort_list + # return stage_effort_list def get_clk_bar_cin(self): """Gets the capacitive load the of clock (clk_buf_bar) for the sram""" @@ -527,5 +530,5 @@ class sram_base(design): bank_sen_cin = self.bank.get_sen_cin() return bank_sen_cin - + \ No newline at end of file From 4ba07e4b94fc8c17f8021ed2f9ec1600fe1e30f1 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sat, 10 Nov 2018 20:23:26 -0800 Subject: [PATCH 18/78] Complete rewrite of parser, all ports (except clock) added on multiport sheets --- compiler/characterizer/lib.py | 134 ++++- compiler/datasheet/datasheet_gen.py | 390 +++++++++++-- compiler/datasheet/wavedrom.py | 827 ++++++++++++++++++++++++++++ 3 files changed, 1278 insertions(+), 73 deletions(-) create mode 100644 compiler/datasheet/wavedrom.py diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 5bf6f579..3909f202 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -509,32 +509,120 @@ class lib: return datasheet = open(OPTS.openram_temp +'/datasheet.info', 'a+') - datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13},{14},{15},{16},{17},{18},{19},{20},{21}\n".format("sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name), - OPTS.num_words, - OPTS.num_banks, - OPTS.num_rw_ports, - OPTS.num_w_ports, - OPTS.num_r_ports, - OPTS.tech_name, - corner[1], - corner[2], - corner[0], - round_time(self.char_sram_results["min_period"]), - self.out_dir, - lib_name, - OPTS.word_size, - min(list(map(round_time,self.times["setup_times_LH"]))), - max(list(map(round_time,self.times["setup_times_LH"]))), + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13},".format( + "sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name), + OPTS.num_words, + OPTS.num_banks, + OPTS.num_rw_ports, + OPTS.num_w_ports, + OPTS.num_r_ports, + OPTS.tech_name, + corner[2], + corner[1], + corner[0], + round_time(self.char_sram_results["min_period"]), + self.out_dir, + lib_name, + OPTS.word_size + + )) - min(list(map(round_time,self.times["setup_times_HL"]))), - max(list(map(round_time,self.times["setup_times_HL"]))), + for port in self.all_ports: + #DIN timings + if port in self.write_ports: + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( + "DIN{1}[{0}:0]".format(self.sram.word_size - 1, port), + min(list(map(round_time,self.times["setup_times_LH"]))), + max(list(map(round_time,self.times["setup_times_LH"]))), - min(list(map(round_time,self.times["hold_times_LH"]))), - max(list(map(round_time,self.times["hold_times_LH"]))), + min(list(map(round_time,self.times["setup_times_HL"]))), + max(list(map(round_time,self.times["setup_times_HL"]))), - min(list(map(round_time,self.times["hold_times_HL"]))), - max(list(map(round_time,self.times["hold_times_HL"]))))) + min(list(map(round_time,self.times["hold_times_LH"]))), + max(list(map(round_time,self.times["hold_times_LH"]))), + + min(list(map(round_time,self.times["hold_times_HL"]))), + max(list(map(round_time,self.times["hold_times_HL"]))) + + )) + + for port in self.all_ports: + #DOUT timing + if port in self.read_ports: + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( + "DOUT{1}[{0}:0]".format(self.sram.word_size - 1, port), + min(list(map(round_time,self.char_port_results[port]["delay_lh"]))), + max(list(map(round_time,self.char_port_results[port]["delay_lh"]))), + + min(list(map(round_time,self.char_port_results[port]["delay_hl"]))), + max(list(map(round_time,self.char_port_results[port]["delay_hl"]))), + + min(list(map(round_time,self.char_port_results[port]["slew_lh"]))), + max(list(map(round_time,self.char_port_results[port]["slew_lh"]))), + + min(list(map(round_time,self.char_port_results[port]["slew_hl"]))), + max(list(map(round_time,self.char_port_results[port]["slew_hl"]))) + + + )) + + for port in self.all_ports: + #CSb timings + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( + "CSb{1}[{0}:0]".format(self.sram.word_size - 1, port), + min(list(map(round_time,self.times["setup_times_LH"]))), + max(list(map(round_time,self.times["setup_times_LH"]))), + + min(list(map(round_time,self.times["setup_times_HL"]))), + max(list(map(round_time,self.times["setup_times_HL"]))), + + min(list(map(round_time,self.times["hold_times_LH"]))), + max(list(map(round_time,self.times["hold_times_LH"]))), + + min(list(map(round_time,self.times["hold_times_HL"]))), + max(list(map(round_time,self.times["hold_times_HL"]))) + + )) + + for port in self.all_ports: + #ADDR timings + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( + "ADDR{1}[{0}:0]".format(self.sram.addr_size - 1, port), + min(list(map(round_time,self.times["setup_times_LH"]))), + max(list(map(round_time,self.times["setup_times_LH"]))), + + min(list(map(round_time,self.times["setup_times_HL"]))), + max(list(map(round_time,self.times["setup_times_HL"]))), + + min(list(map(round_time,self.times["hold_times_LH"]))), + max(list(map(round_time,self.times["hold_times_LH"]))), + + min(list(map(round_time,self.times["hold_times_HL"]))), + max(list(map(round_time,self.times["hold_times_HL"]))) + + )) + + + for port in self.all_ports: + if port in self.readwrite_ports: + + #WEb timings + datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( + "WEb{1}[{0}:0]".format(self.sram.word_size - 1, port), + min(list(map(round_time,self.times["setup_times_LH"]))), + max(list(map(round_time,self.times["setup_times_LH"]))), + + min(list(map(round_time,self.times["setup_times_HL"]))), + max(list(map(round_time,self.times["setup_times_HL"]))), + + min(list(map(round_time,self.times["hold_times_LH"]))), + max(list(map(round_time,self.times["hold_times_LH"]))), + + min(list(map(round_time,self.times["hold_times_HL"]))), + max(list(map(round_time,self.times["hold_times_HL"]))) + + )) - + datasheet.write("END\n") datasheet.close() diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 5f163904..b48c2510 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -51,41 +51,70 @@ def parse_characterizer_csv(sram,f,pages): csv_reader = csv.reader(csv_file, delimiter=',') line_count = 0 for row in csv_reader: + found = 0 + col = 0 #defines layout of csv file - NAME = row[0] - NUM_WORDS = row[1] - NUM_BANKS = row[2] - NUM_RW_PORTS = row[3] - NUM_W_PORTS = row[4] - NUM_R_PORTS = row[5] - TECH_NAME = row[6] - TEMP = row[8] - VOLT = row[7] - PROC = row[9] - MIN_PERIOD = row[10] - OUT_DIR = row[11] - LIB_NAME = row[12] - WORD_SIZE = row[13] + NAME = row[col] + col += 1 - FF_SETUP_LH_MIN = row[14] - FF_SETUP_LH_MAX = row[15] + NUM_WORDS = row[col] + col += 1 - FF_SETUP_HL_MIN = row[16] - FF_SETUP_HL_MAX = row[17] + NUM_BANKS = row[col] + col += 1 - FF_HOLD_LH_MIN = row[18] - FF_HOLD_LH_MAX = row[19] + NUM_RW_PORTS = row[col] + col += 1 - FF_HOLD_HL_MIN = row[20] - FF_HOLD_HL_MAX = row[21] - + NUM_W_PORTS = row[col] + col += 1 + + NUM_R_PORTS = row[col] + col += 1 + + TECH_NAME = row[col] + col += 1 + + TEMP = row[col] + col += 1 + + VOLT = row[col] + col += 1 + + PROC = row[col] + col += 1 + + MIN_PERIOD = row[col] + col += 1 + + OUT_DIR = row[col] + col += 1 + + LIB_NAME = row[col] + col += 1 + + WORD_SIZE = row[col] + col += 1 + + FF_SETUP_LH_MIN = "1" + FF_SETUP_LH_MAX = "2" + + FF_SETUP_HL_MIN = "3" + FF_SETUP_HL_MAX = "4" + + FF_HOLD_LH_MIN = "5" + FF_HOLD_LH_MAX = "6" + + FF_HOLD_HL_MIN = "7" + FF_HOLD_HL_MAX = "8" + for sheet in pages: - if sheet.name == row[0]: + if sheet.name == NAME: found = 1 #if the .lib information is for an existing datasheet compare timing data @@ -117,31 +146,208 @@ def parse_characterizer_csv(sram,f,pages): #pass if MIN_PERIOD is zero (not supported by analyitcal model) pass - for item in sheet.timing: - if item.parameter == "CSb setup rising": - if float(FF_SETUP_LH_MIN) < float(item.min): - item.min = FF_SETUP_LH_MIN - elif float(FF_SETUP_LH_MAX) > float(item.max): - item.max = FF_SETUP_LH_MAX - if item.parameter == "CSb setup falling": - if float(FF_SETUP_HL_MIN) < float(item.min): - item.min = FF_SETUP_HL_MIN - elif float(FF_SETUP_HL_MAX) > float(item.max): - item.max = FF_SETUP_HL_MAX - if item.parameter == "CSb hold rising": - if float(FF_HOLD_HL_MIN) < float(item.min): - item.min = FF_SETUP_HL_MIN - elif float(FF_HOLD_HL_MAX) > float(item.max): - item.max = FF_SETUP_HL_MAX + while(True): + if(row[col].startswith('DIN')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + elif(row[col].startswith('DOUT')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('cell rise'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('cell fall'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('rise transition'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('fall transition'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + elif(row[col].startswith('CSb')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + + elif(row[col].startswith('WEb')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + + elif(row[col].startswith('ADDR')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + else: + break - if item.parameter == "CSb hold falling": - if float(FF_HOLD_HL_MIN) < float(item.min): - item.min = FF_SETUP_HL_MIN - elif float(FF_HOLD_HL_MAX) > float(item.max): - item.max = FF_SETUP_HL_MAX - #regardless of if there is already a corner for the current sram, append the new corner to the datasheet new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,''))) @@ -163,14 +369,98 @@ def parse_characterizer_csv(sram,f,pages): new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)*','','',"unknown",'MHz')) #analytical model fails to provide MIN_PERIOD #place holder timing and current data + new_sheet.timing.append(timing_and_current_data_item('Cycle time','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Access time','2','3','4')) + new_sheet.timing.append(timing_and_current_data_item('Positive clk setup','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Positive clk hold','2','3','4')) - new_sheet.timing.append(timing_and_current_data_item('CSb setup rising',FF_SETUP_LH_MIN,FF_SETUP_LH_MAX,'ns')) - new_sheet.timing.append(timing_and_current_data_item('CSb setup falling',FF_SETUP_HL_MIN,FF_SETUP_HL_MAX,'ns')) - new_sheet.timing.append(timing_and_current_data_item('CSb hold rising',FF_HOLD_LH_MIN,FF_HOLD_LH_MAX,'ns')) - new_sheet.timing.append(timing_and_current_data_item('CSb hold falling',FF_HOLD_HL_MIN,FF_HOLD_HL_MAX,'ns')) + + while(True): + if(row[col].startswith('DIN')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('DOUT')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} cell rise'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} cell fall'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} rise transition'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} fall transition'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('CSb')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('WEb')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('ADDR')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + else: + break + + + new_sheet.timing.append(timing_and_current_data_item('AC current','2','3','4')) new_sheet.timing.append(timing_and_current_data_item('Standby current','2','3','4')) diff --git a/compiler/datasheet/wavedrom.py b/compiler/datasheet/wavedrom.py new file mode 100644 index 00000000..e8c68c56 --- /dev/null +++ b/compiler/datasheet/wavedrom.py @@ -0,0 +1,827 @@ +#!/usr/bin/python +# The MIT License (MIT) +# +# Copyright (c) 2011-2016 Aliaksei Chapyzhenka +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. +# +# Translated to Python from original file: +# https://github.com/drom/wavedrom/blob/master/src/WaveDrom.js +# + +import sys +import json +import math +import waveskin + +font_width = 7 + +lane = { + "xs" : 20, # tmpgraphlane0.width + "ys" : 20, # tmpgraphlane0.height + "xg" : 120, # tmpgraphlane0.x + "yg" : 0, # head gap + "yh0" : 0, # head gap title + "yh1" : 0, # head gap + "yf0" : 0, # foot gap + "yf1" : 0, # foot gap + "y0" : 5, # tmpgraphlane0.y + "yo" : 30, # tmpgraphlane1.y - y0 + "tgo" : -10, # tmptextlane0.x - xg + "ym" : 15, # tmptextlane0.y - y0 + "xlabel" : 6, # tmptextlabel.x - xg + "xmax" : 1, + "scale" : 1, + "head" : {}, + "foot" : {} +} + +def genBrick (texts, extra, times) : + + R = [] + if len( texts ) == 4 : + for j in range( times ): + + R.append(texts[0]) + + for i in range ( extra ): + R.append(texts[1]) + + R.append(texts[2]) + for i in range ( extra ): + R.append(texts[3]) + + return R + + if len( texts ) == 1 : + texts.append(texts[0]) + + R.append(texts[0]) + for i in range (times * (2 * (extra + 1)) - 1) : + R.append(texts[1]) + return R + +def genFirstWaveBrick (text, extra, times) : + + pattern = { + 'p': ['pclk', '111', 'nclk', '000'], + 'n': ['nclk', '000', 'pclk', '111'], + 'P': ['Pclk', '111', 'nclk', '000'], + 'N': ['Nclk', '000', 'pclk', '111'], + 'l': ['000'], + 'L': ['000'], + '0': ['000'], + 'h': ['111'], + 'H': ['111'], + '1': ['111'], + '=': ['vvv-2'], + '2': ['vvv-2'], + '3': ['vvv-3'], + '4': ['vvv-4'], + '5': ['vvv-5'], + 'd': ['ddd'], + 'u': ['uuu'], + 'z': ['zzz'] + } + + return genBrick( pattern.get( text, ['xxx'] ) , extra, times ); + +def genWaveBrick (text, extra, times) : + + x1 = {'p':'pclk', 'n':'nclk', 'P':'Pclk', 'N':'Nclk', 'h':'pclk', 'l':'nclk', 'H':'Pclk', 'L':'Nclk'} + x2 = {'0':'0', '1':'1', 'x':'x', 'd':'d', 'u':'u', 'z':'z', '=':'v', '2':'v', '3':'v', '4':'v', '5':'v' } + x3 = {'0': '', '1': '', 'x': '', 'd': '', 'u': '', 'z': '', '=':'-2', '2':'-2', '3':'-3', '4':'-4', '5':'-5'} + y1 = { + 'p':'0', 'n':'1', + 'P':'0', 'N':'1', + 'h':'1', 'l':'0', + 'H':'1', 'L':'0', + '0':'0', '1':'1', 'x':'x', 'd':'d', 'u':'u', 'z':'z', '=':'v', '2':'v', '3':'v', '4':'v', '5':'v'} + + y2 = { + 'p': '', 'n': '', + 'P': '', 'N': '', + 'h': '', 'l': '', + 'H': '', 'L': '', + '0': '', '1': '', 'x': '', 'd': '', 'u': '', 'z': '', '=':'-2', '2':'-2', '3':'-3', '4':'-4', '5':'-5'} + + x4 = { + 'p': '111', 'n': '000', + 'P': '111', 'N': '000', + 'h': '111', 'l': '000', + 'H': '111', 'L': '000', + '0': '000', '1': '111', 'x': 'xxx', 'd': 'ddd', 'u': 'uuu', 'z': 'zzz', + '=': 'vvv-2', '2': 'vvv-2', '3': 'vvv-3', '4': 'vvv-4', '5': 'vvv-5'} + + x5 = {'p':'nclk', 'n':'pclk', 'P':'nclk', 'N':'pclk'} + x6 = {'p': '000', 'n': '111', 'P': '000', 'N': '111'} + xclude = {'hp':'111', 'Hp':'111', 'ln': '000', 'Ln': '000', 'nh':'111', 'Nh':'111', 'pl': '000', 'Pl':'000'} + + #atext = text.split() + atext = text + + tmp0 = x4.get(atext[1]) + tmp1 = x1.get(atext[1]) + if tmp1 == None : + tmp2 = x2.get(atext[1]) + if tmp2 == None : + # unknown + return genBrick(['xxx'], extra, times) + else : + tmp3 = y1.get(atext[0]) + if tmp3 == None : + # unknown + return genBrick(['xxx'], extra, times) + + # soft curves + return genBrick([tmp3 + 'm' + tmp2 + y2[atext[0]] + x3[atext[1]], tmp0], extra, times) + + else : + tmp4 = xclude.get(text) + if tmp4 != None : + tmp1 = tmp4 + + # sharp curves + tmp2 = x5.get(atext[1]) + if tmp2 == None : + # hlHL + return genBrick([tmp1, tmp0], extra, times) + else : + # pnPN + return genBrick([tmp1, tmp0, tmp2, x6[atext[1]]], extra, times) + +def parseWaveLane (text, extra) : + + R = [] + Stack = text + Next = Stack[0] + Stack = Stack[1:] + + Repeats = 1 + while len(Stack) and ( Stack[0] == '.' or Stack[0] == '|' ): # repeaters parser + Stack=Stack[1:] + Repeats += 1 + + R.extend(genFirstWaveBrick(Next, extra, Repeats)) + + while len(Stack) : + Top = Next + Next = Stack[0] + Stack = Stack[1:] + Repeats = 1 + while len(Stack) and ( Stack[0] == '.' or Stack[0] == '|' ) : # repeaters parser + Stack=Stack[1:] + Repeats += 1 + R.extend(genWaveBrick((Top + Next), extra, Repeats)) + + for i in range( lane['phase'] ): + R = R[1:] + return R + +def parseWaveLanes (sig) : + + def data_extract (e) : + tmp = e.get('data') + if tmp == None : return None + if is_type_str (tmp) : tmp=tmp.split() + return tmp + + content = [] + for sigx in sig : + lane['period'] = sigx.get('period',1) + lane['phase'] = int( sigx.get('phase',0 ) * 2 ) + sub_content=[] + sub_content.append( [sigx.get('name',' '), sigx.get('phase',0 ) ] ) + sub_content.append( parseWaveLane( sigx['wave'], int(lane['period'] * lane['hscale'] - 1 ) ) if sigx.get('wave') else None ) + sub_content.append( data_extract(sigx) ) + content.append(sub_content) + + return content + +def findLaneMarkers (lanetext) : + + lcount = 0 + gcount = 0 + ret = [] + for i in range( len( lanetext ) ) : + if lanetext[i] == 'vvv-2' or lanetext[i] == 'vvv-3' or lanetext[i] == 'vvv-4' or lanetext[i] == 'vvv-5' : + lcount += 1 + else : + if lcount !=0 : + ret.append(gcount - ((lcount + 1) / 2)) + lcount = 0 + + gcount += 1 + + if lcount != 0 : + ret.append(gcount - ((lcount + 1) / 2)) + + return ret + +def renderWaveLane (root, content, index) : + + xmax = 0 + xgmax = 0 + glengths = [] + svgns = 'http://www.w3.org/2000/svg' + xlinkns = 'http://www.w3.org/1999/xlink' + xmlns = 'http://www.w3.org/XML/1998/namespace' + for j in range( len(content) ): + name = content[j][0][0] + if name : # check name + g = [ + 'g', + { + 'id': 'wavelane_' + str(j) + '_' + str(index), + 'transform': 'translate(0,' + str(lane['y0'] + j * lane['yo']) + ')' + } + ] + root.append(g) + title = [ + 'text', + { + 'x': lane['tgo'], + 'y': lane['ym'], + 'class': 'info', + 'text-anchor': 'end', + 'xml:space': 'preserve' + }, + ['tspan', name] + ] + g.append(title) + + glengths.append( len(name) * font_width + font_width ) + + xoffset = content[j][0][1] + xoffset = math.ceil(2 * xoffset) - 2 * xoffset if xoffset > 0 else -2 * xoffset + gg = [ + 'g', + { + 'id': 'wavelane_draw_' + str(j) + '_' + str(index), + 'transform': 'translate(' + str( xoffset * lane['xs'] ) + ', 0)' + } + ] + g.append(gg) + + if content[j][1] : + for i in range( len(content[j][1]) ) : + b = [ + 'use', + { + #'id': 'use_' + str(i) + '_' + str(j) + '_' + str(index), + 'xmlns:xlink':xlinkns, + 'xlink:href': '#' + str( content[j][1][i] ), + 'transform': 'translate(' + str(i * lane['xs']) + ')' + } + ] + gg.append(b) + + if content[j][2] and len(content[j][2]) : + labels = findLaneMarkers(content[j][1]) + if len(labels) != 0 : + for k in range( len(labels) ) : + if content[j][2] and k < len(content[j][2]) : + title = [ + 'text', + { + 'x': int(labels[k]) * lane['xs'] + lane['xlabel'], + 'y': lane['ym'], + 'text-anchor': 'middle', + 'xml:space': 'preserve' + }, + ['tspan',content[j][2][k]] + ] + gg.append(title) + + + if len(content[j][1]) > xmax : + xmax = len(content[j][1]) + + lane['xmax'] = xmax + lane['xg'] = xgmax + 20 + return glengths + +def renderMarks (root, content, index) : + + def captext ( g, cxt, anchor, y ) : + + if cxt.get(anchor) and cxt[anchor].get('text') : + tmark = [ + 'text', + { + 'x': float( cxt['xmax'] ) * float( cxt['xs'] ) / 2, + 'y': y, + 'text-anchor': 'middle', + 'fill': '#000', + 'xml:space': 'preserve' + }, cxt[anchor]['text'] + ] + g.append(tmark) + + def ticktock ( g, cxt, ref1, ref2, x, dx, y, length ) : + L = [] + + if cxt.get(ref1) == None or cxt[ref1].get(ref2) == None : + return + + val = cxt[ref1][ref2] + if is_type_str( val ) : + val = val.split() + elif type( val ) is int : + offset = val + val = [] + for i in range ( length ) : + val.append(i + offset) + + if type( val ) is list : + if len( val ) == 0 : + return + elif len( val ) == 1 : + offset = val[0] + if is_type_str(offset) : + L = val + else : + for i in range ( length ) : + L[i] = i + offset + + elif len( val ) == 2: + offset = int(val[0]) + step = int(val[1]) + tmp = val[1].split('.') + if len( tmp ) == 2 : + dp = len( tmp[1] ) + + if is_type_str(offset) or is_type_str(step) : + L = val + else : + offset = step * offset + for i in range( length ) : + L[i] = "{0:.",dp,"f}".format(step * i + offset) + + else : + L = val + + else : + return + + for i in range( length ) : + tmp = L[i] + tmark = [ + 'text', + { + 'x': i * dx + x, + 'y': y, + 'text-anchor': 'middle', + 'class': 'muted', + 'xml:space': 'preserve' + }, str(tmp) + ] + g.append(tmark) + + mstep = 2 * int(lane['hscale']) + mmstep = mstep * lane['xs'] + marks = int( lane['xmax'] / mstep ) + gy = len( content ) * int(lane['yo']) + + g = ['g', {'id': 'gmarks_' + str(index)}] + root.insert(0,g) + + for i in range( marks + 1): + gg = [ + 'path', + { + 'id': 'gmark_' + str(i) + '_' + str(index), + 'd': 'm ' + str(i * mmstep) + ',' + '0' + ' 0,' + str(gy), + 'style': 'stroke:#888;stroke-width:0.5;stroke-dasharray:1,3' + } + ] + g.append( gg ) + + captext(g, lane, 'head', -33 if lane['yh0'] else -13 ) + captext(g, lane, 'foot', gy + ( 45 if lane['yf0'] else 25 ) ) + + ticktock( g, lane, 'head', 'tick', 0, mmstep, -5, marks + 1) + ticktock( g, lane, 'head', 'tock', mmstep / 2, mmstep, -5, marks) + ticktock( g, lane, 'foot', 'tick', 0, mmstep, gy + 15, marks + 1) + ticktock( g, lane, 'foot', 'tock', mmstep / 2, mmstep, gy + 15, marks) + +def renderArcs (root, source, index, top) : + + Stack = [] + Edge = {'words': [], 'frm': 0, 'shape': '', 'to': 0, 'label': ''} + Events = {} + svgns = 'http://www.w3.org/2000/svg' + xmlns = 'http://www.w3.org/XML/1998/namespace' + + if source : + for i in range (len (source) ) : + lane['period'] = source[i].get('period',1) + lane['phase'] = int( source[i].get('phase',0 ) * 2 ) + text = source[i].get('node') + if text: + Stack = text + pos = 0 + while len( Stack ) : + eventname = Stack[0] + Stack=Stack[1:] + if eventname != '.' : + Events[eventname] = { + 'x' : str( int( float( lane['xs'] ) * (2 * pos * lane['period'] * lane['hscale'] - lane['phase'] ) + float( lane['xlabel'] ) ) ), + 'y' : str( int( i * lane['yo'] + lane['y0'] + float( lane['ys'] ) * 0.5 ) ) + } + pos += 1 + + gg = [ 'g', { 'id' : 'wavearcs_' + str( index ) } ] + root.append(gg) + + if top.get('edge') : + for i in range( len ( top['edge'] ) ) : + Edge['words'] = top['edge'][i].split() + Edge['label'] = top['edge'][i][len(Edge['words'][0]):] + Edge['label'] = Edge['label'][1:] + Edge['frm'] = Edge['words'][0][0] + Edge['to'] = Edge['words'][0][-1] + Edge['shape'] = Edge['words'][0][1:-1] + frm = Events[Edge['frm']] + to = Events[Edge['to']] + gmark = [ + 'path', + { + 'id': 'gmark_' + Edge['frm'] + '_' + Edge['to'], + 'd': 'M ' + frm['x'] + ',' + frm['y'] + ' ' + to['x'] + ',' + to['y'], + 'style': 'fill:none;stroke:#00F;stroke-width:1' + } + ] + gg.append(gmark) + dx = float( to['x'] ) - float( frm['x'] ) + dy = float( to['y'] ) - float( frm['y'] ) + lx = (float(frm['x']) + float(to['x'])) / 2 + ly = (float(frm['y']) + float(to['y'])) / 2 + pattern = { + '~' : {'d': 'M ' + frm['x'] + ',' + frm['y'] + ' c ' + str(0.7 * dx) + ', 0 ' + str(0.3 * dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy) }, + '-~' : {'d': 'M ' + frm['x'] + ',' + frm['y'] + ' c ' + str(0.7 * dx) + ', 0 ' + str(dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy) }, + '~-' : {'d': 'M ' + frm['x'] + ',' + frm['y'] + ' c ' + '0' + ', 0 ' + str(0.3 * dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy) }, + '-|' : {'d': 'm ' + frm['x'] + ',' + frm['y'] + ' ' + str(dx) + ',0 0,' + str(dy)}, + '|-' : {'d': 'm ' + frm['x'] + ',' + frm['y'] + ' 0,' + str(dy) + ' ' + str(dx) + ',0'}, + '-|-' : {'d': 'm ' + frm['x'] + ',' + frm['y'] + ' ' + str(dx / 2) + ',0 0,' + str(dy) + ' ' + str(dx / 2) + ',0'}, + '->' : {'style': 'marker-end:url(#arrowhead);stroke:#0041c4;stroke-width:1;fill:none'}, + '~>' : {'style': 'marker-end:url(#arrowhead);stroke:#0041c4;stroke-width:1;fill:none', 'd': 'M ' + frm['x'] + ',' + frm['y'] + ' ' + 'c ' + str(0.7 * dx) + ', 0 ' + str(0.3 * dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy)}, + '-~>' : {'style': 'marker-end:url(#arrowhead);stroke:#0041c4;stroke-width:1;fill:none', 'd': 'M ' + frm['x'] + ',' + frm['y'] + ' ' + 'c ' + str(0.7 * dx) + ', 0 ' + str(dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy)}, + '~->' : {'style': 'marker-end:url(#arrowhead);stroke:#0041c4;stroke-width:1;fill:none', 'd': 'M ' + frm['x'] + ',' + frm['y'] + ' ' + 'c ' + '0' + ', 0 ' + str(0.3 * dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy)}, + '-|>' : {'style': 'marker-end:url(#arrowhead);stroke:#0041c4;stroke-width:1;fill:none', 'd': 'm ' + frm['x'] + ',' + frm['y'] + ' ' + str(dx) + ',0 0,' + str(dy)}, + '|->' : {'style': 'marker-end:url(#arrowhead);stroke:#0041c4;stroke-width:1;fill:none', 'd': 'm ' + frm['x'] + ',' + frm['y'] + ' 0,' + str(dy) + ' ' + str(dx) + ',0'}, + '-|->' : {'style': 'marker-end:url(#arrowhead);stroke:#0041c4;stroke-width:1;fill:none', 'd': 'm ' + frm['x'] + ',' + frm['y'] + ' ' + str(dx / 2) + ',0 0,' + str(dy) + ' ' + str(dx / 2) + ',0'}, + '<->' : {'style': 'marker-end:url(#arrowhead);marker-start:url(#arrowtail);stroke:#0041c4;stroke-width:1;fill:none'}, + '<~>' : {'style': 'marker-end:url(#arrowhead);marker-start:url(#arrowtail);stroke:#0041c4;stroke-width:1;fill:none','d': 'M ' + frm['x'] + ',' + frm['y'] + ' ' + 'c ' + str(0.7 * dx) + ', 0 ' + str(0.3 * dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy)}, + '<-~>' : {'style': 'marker-end:url(#arrowhead);marker-start:url(#arrowtail);stroke:#0041c4;stroke-width:1;fill:none','d': 'M ' + frm['x'] + ',' + frm['y'] + ' ' + 'c ' + str(0.7 * dx) + ', 0 ' + str(dx) + ', ' + str(dy) + ' ' + str(dx) + ', ' + str(dy)}, + '<-|>' : {'style': 'marker-end:url(#arrowhead);marker-start:url(#arrowtail);stroke:#0041c4;stroke-width:1;fill:none','d': 'm ' + frm['x'] + ',' + frm['y'] + ' ' + str(dx) + ',0 0,' + str(dy)}, + '<-|->': {'style': 'marker-end:url(#arrowhead);marker-start:url(#arrowtail);stroke:#0041c4;stroke-width:1;fill:none','d': 'm ' + frm['x'] + ',' + frm['y'] + ' ' + str(dx / 2) + ',0 0,' + str(dy) + ' ' + str(dx / 2) + ',0'} + } + gmark[1].update( pattern.get( Edge['shape'], { 'style': 'fill:none;stroke:#00F;stroke-width:1' } ) ) + + if Edge['label']: + if Edge['shape'] == '-~' : + lx = float(frm['x']) + (float(to['x']) - float(frm['x'])) * 0.75 + if Edge['shape'] == '~-' : + lx = float(frm['x']) + (float(to['x']) - float(frm['x'])) * 0.25 + if Edge['shape'] == '-|' : + lx = float(to['x']) + if Edge['shape'] == '|-' : + lx = float(frm['x']) + if Edge['shape'] == '-~>': + lx = float(frm['x']) + (float(to['x']) - float(frm['x'])) * 0.75 + if Edge['shape'] == '~->': + lx = float(frm['x']) + (float(to['x']) - float(frm['x'])) * 0.25 + if Edge['shape'] == '-|>' : + lx = float(to['x']) + if Edge['shape'] == '|->' : + lx = float(frm['x']) + if Edge['shape'] == '<-~>': + lx = float(frm['x']) + (float(to['x']) - float(frm['x'])) * 0.75 + if Edge['shape'] =='<-|>' : + lx = float(to['x']) + + lwidth = len( Edge['label'] ) * font_width + label = [ + 'text', + { + 'style': 'font-size:10px;', + 'text-anchor': 'middle', + 'xml:space': 'preserve', + 'x': int( lx ), + 'y': int( ly + 3 ) + }, + [ 'tspan', Edge['label'] ] + ] + underlabel = [ + 'rect', + { + 'height': 9, + 'style': 'fill:#FFF;', + 'width': lwidth, + 'x': int( lx - lwidth / 2 ), + 'y': int( ly - 5 ) + } + ] + gg.append(underlabel) + gg.append(label) + + for k in Events: + if k.islower() : + if int( Events[k]['x'] ) > 0 : + lwidth = len( k ) * font_width + underlabel = [ + 'rect', + { + 'x': float( Events[k]['x'] ) - float(lwidth) / 2, + 'y': int( Events[k]['y'] ) - 4, + 'height': 8, + 'width': lwidth, + 'style': 'fill:#FFF;' + } + ] + gg.append(underlabel) + label = [ + 'text', + { + 'style': 'font-size:8px;', + 'x': int( Events[k]['x'] ), + 'y': int( Events[k]['y'] ) + 2, + 'width': lwidth, + 'text-anchor': 'middle' + }, + k + ] + gg.append(label) + +def parseConfig (source) : + + lane['hscale'] = 1 + if lane.get('hscale0') : + lane['hscale'] = lane['hscale0'] + + if source and source.get('config') and source.get('config').get('hscale'): + hscale = round(source.get('config').get('hscale')) + if hscale > 0 : + if hscale > 100 : hscale = 100 + lane['hscale'] = hscale + + lane['yh0'] = 0 + lane['yh1'] = 0 + if source and source.get('head') : + lane['head'] = source['head'] + if source.get('head').get('tick',0) == 0 : lane['yh0'] = 20 + if source.get('head').get('tock',0) == 0 : lane['yh0'] = 20 + if source.get('head').get('text') : lane['yh1'] = 46; lane['head']['text'] = source['head']['text'] + + lane['yf0'] = 0 + lane['yf1'] = 0 + if source and source.get('foot') : + lane['foot'] = source['foot'] + if source.get('foot').get('tick',0) == 0 : lane['yf0'] = 20 + if source.get('foot').get('tock',0) == 0 : lane['yf0'] = 20 + if source.get('foot').get('text') : lane['yf1'] = 46; lane['foot']['text'] = source['foot']['text'] + +def rec (tmp, state) : + + name = str( tmp[0] ) + delta_x = 25 + + state['x'] += delta_x + for i in range( len( tmp ) ) : + if type( tmp[i] ) is list : + old_y = state['y'] + rec( tmp[i], state ) + state['groups'].append( {'x':state['xx'], 'y':old_y, 'height':state['y'] - old_y, 'name': state['name'] } ) + elif type( tmp[i] ) is dict : + state['lanes'].append(tmp[i]) + state['width'].append(state['x']) + state['y'] += 1 + + state['xx'] = state['x'] + state['x'] -= delta_x + state['name'] = name + +def insertSVGTemplate (index, parent, source) : + + e = waveskin.WaveSkin['default'] + + if source.get('config') and source.get('config').get('skin') : + if waveskin.WaveSkin.get( source.get('config').get('skin') ) : + e = waveskin.WaveSkin[ source.get('config').get('skin') ] + + if index == 0 : + lane['xs'] = int( e[3][1][2][1]['width'] ) + lane['ys'] = int( e[3][1][2][1]['height'] ) + lane['xlabel'] = int( e[3][1][2][1]['x'] ) + lane['ym'] = int( e[3][1][2][1]['y'] ) + + else : + e = ['svg', {'id': 'svg', 'xmlns': 'http://www.w3.org/2000/svg', 'xmlns:xlink': 'http://www.w3.org/1999/xlink', 'height': '0'}, + ['g', {'id': 'waves'}, + ['g', {'id': 'lanes'}], + ['g', {'id': 'groups'}] + ] + ] + + e[-1][1]['id'] = 'waves_' + str(index) + e[-1][2][1]['id'] = 'lanes_' + str(index) + e[-1][3][1]['id'] = 'groups_' + str(index) + e[1]['id'] = 'svgcontent_' + str(index) + e[1]['height'] = 0 + + parent.extend(e) + +def renderWaveForm (index, source, output) : + + xmax = 0 + root = [] + groups = [] + + if source.get('signal'): + insertSVGTemplate(index, output, source) + parseConfig( source ) + ret = {'x':0, 'y':0, 'xmax':0, 'width':[], 'lanes':[], 'groups':[] } + rec( source['signal'], ret ) + content = parseWaveLanes(ret['lanes']) + glengths = renderWaveLane(root, content, index) + for i in range( len( glengths ) ): + xmax = max( xmax, ( glengths[i] + ret['width'][i] ) ) + renderMarks(root, content, index) + renderArcs(root, ret['lanes'], index, source) + renderGaps(root, ret['lanes'], index) + renderGroups(groups, ret['groups'], index) + lane['xg'] = int( math.ceil( float( xmax - lane['tgo'] ) / float(lane['xs'] ) ) ) * lane['xs'] + width = (lane['xg'] + lane['xs'] * (lane['xmax'] + 1) ) + height = len(content) * lane['yo'] + lane['yh0'] + lane['yh1'] + lane['yf0'] + lane['yf1'] + output[1]={ + 'id' :'svgcontent_' + str(index), + 'xmlns' :"http://www.w3.org/2000/svg", + 'xmlns:xlink':"http://www.w3.org/1999/xlink", + 'width' :str(width), + 'height' :str(height), + 'viewBox' :'0 0 ' + str(width) + ' ' + str(height), + 'overflow' :"hidden" + } + output[-1][2][1]['transform']='translate(' + str(lane['xg'] + 0.5) + ', ' + str((float(lane['yh0']) + float(lane['yh1'])) + 0.5) + ')' + + output[-1][2].extend(root) + output[-1][3].extend(groups) + +def renderGroups (root, groups, index) : + + svgns = 'http://www.w3.org/2000/svg', + xmlns = 'http://www.w3.org/XML/1998/namespace' + + for i in range( len( groups ) ) : + group = [ + 'path', + { + 'id': 'group_' + str(i) + '_' + str(index), + 'd': 'm ' + str( groups[i]['x'] + 0.5 ) + ',' + str( groups[i]['y']* lane['yo'] + 3.5 + lane['yh0'] + lane['yh1'] ) + ' c -3,0 -5,2 -5,5 l 0,' + str( int( groups[i]['height'] * lane['yo'] - 16 ) ) + ' c 0,3 2,5 5,5', + 'style': 'stroke:#0041c4;stroke-width:1;fill:none' + } + ] + root.append(group) + + name = groups[i]['name'] + x = str( int( groups[i]['x'] - 10 ) ) + y = str( int( lane['yo'] * (groups[i]['y'] + (float(groups[i]['height']) / 2)) + lane['yh0'] + lane['yh1'] ) ) + label = [ + ['g', + {'transform': 'translate(' + x + ',' + y + ')'}, + ['g', {'transform': 'rotate(270)'}, + 'text', + { + 'text-anchor': 'middle', + 'class': 'info', + 'xml:space' : 'preserve' + }, + ['tspan',name] + ] + ] + ] + root.append(label) + +def renderGaps (root, source, index) : + + Stack = [] + svgns = 'http://www.w3.org/2000/svg', + xlinkns = 'http://www.w3.org/1999/xlink' + + if source: + + gg = [ + 'g', + { 'id': 'wavegaps_' + str(index) } + ] + + for i in range( len( source )): + lane['period'] = source[i].get('period',1) + lane['phase'] = int( source[i].get('phase',0 ) * 2 ) + + g = [ + 'g', + { + 'id': 'wavegap_' + str(i) + '_' + str(index), + 'transform': 'translate(0,' + str(lane['y0'] + i * lane['yo']) + ')' + } + ] + gg.append(g) + + if source[i].get('wave'): + text = source[i]['wave'] + Stack = text + pos = 0 + while len( Stack ) : + c = Stack [0] + Stack = Stack[1:] + if c == '|' : + b = [ + 'use', + { + 'xmlns:xlink':xlinkns, + 'xlink:href':'#gap', + 'transform': 'translate(' + str(int(float(lane['xs']) * ((2 * pos + 1) * float(lane['period']) * float(lane['hscale']) - float(lane['phase'])))) + ')' + } + ] + g.append(b) + pos += 1 + + root.append( gg ) + +def is_type_str( var ) : + if sys.version_info[0] < 3: + return type( var ) is str or type( var ) is unicode + else: + return type( var ) is str + +def convert_to_svg( root ) : + + svg_output = '' + + if type( root ) is list: + if len(root) >= 2 and type( root[1] ) is dict: + if len( root ) == 2 : + svg_output += '<' + root[0] + convert_to_svg( root[1] ) + '/>\n' + elif len( root ) >= 3 : + svg_output += '<' + root[0] + convert_to_svg( root[1] ) + '>\n' + if len( root ) == 3: + svg_output += convert_to_svg( root[2] ) + else: + svg_output += convert_to_svg( root[2:] ) + svg_output += '\n' + elif type( root[0] ) is list: + for eleml in root: + svg_output += convert_to_svg( eleml ) + else: + svg_output += '<' + root[0] + '>\n' + for eleml in root[1:]: + svg_output += convert_to_svg( eleml ) + svg_output += '\n' + elif type( root ) is dict: + for elemd in root : + svg_output += ' ' + elemd + '="' + str(root[elemd]) + '"' + else: + svg_output += root + + return svg_output + +if __name__ == '__main__': + + if len( sys.argv ) != 5: + print ( 'Usage : ' + sys.argv[0] + ' source svg ' ) + exit(1) + + if sys.argv[3] != 'svg' : + print ( 'Error: only SVG format supported.' ) + exit(1) + + output=[] + inputfile = sys.argv[2] + outputfile = sys.argv[4] + + with open(inputfile,'r') as f: + jinput = json.load(f) + + renderWaveForm(0,jinput,output) + svg_output = convert_to_svg(output) + + with open(outputfile,'w') as f: + f.write( svg_output ) From aadf160ce4d22db48c6a0e9b84aa5f3ef8791009 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 11 Nov 2018 06:05:14 -0800 Subject: [PATCH 19/78] added missing space in sheet --- compiler/datasheet/datasheet.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index beded426..144f1968 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -33,8 +33,8 @@ class datasheet(): if OPTS.check_lvsdrc: - DRC = total_drc_errors - LVS = total_lvs_errors + DRC = str(total_drc_errors) + ' errors' + LVS = str(total_lvs_errors) + ' errors' PEX = 'n/a' else: DRC = 'skipped' @@ -43,8 +43,8 @@ class datasheet(): self.html +='

'+ self.name + '.html' + '

' - self.html +='

'+ 'DRC: ' + str(DRC) + ' errors'+'

' - self.html +='

'+ 'LVS: ' + str(LVS) + ' errors'+'

' + self.html +='

'+ 'DRC: ' + str(DRC) + '

' + self.html +='

'+ 'LVS: ' + str(LVS) + '

' self.html +='

Ports and Configuration (DEBUG)

' self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">") From 5c4ee911aaae8e34641a7706d3107848fb890429 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 11 Nov 2018 07:22:13 -0800 Subject: [PATCH 20/78] added another VLSI logo and fixed control port numbering --- compiler/characterizer/lib.py | 4 ++-- compiler/datasheet/datasheet.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 3909f202..da96894d 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -569,7 +569,7 @@ class lib: for port in self.all_ports: #CSb timings datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( - "CSb{1}[{0}:0]".format(self.sram.word_size - 1, port), + "CSb{0}".format(port), min(list(map(round_time,self.times["setup_times_LH"]))), max(list(map(round_time,self.times["setup_times_LH"]))), @@ -608,7 +608,7 @@ class lib: #WEb timings datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( - "WEb{1}[{0}:0]".format(self.sram.word_size - 1, port), + "WEb{0}".format(port), min(list(map(round_time,self.times["setup_times_LH"]))), max(list(map(round_time,self.times["setup_times_LH"]))), diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 144f1968..70957b75 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -41,7 +41,7 @@ class datasheet(): LVS = 'skipped' PEX = 'skipped' - + self.html +='VLSIDA' self.html +='

'+ self.name + '.html' + '

' self.html +='

'+ 'DRC: ' + str(DRC) + '

' self.html +='

'+ 'LVS: ' + str(LVS) + '

' From 0dd97e54ddeb17064df7f51f46caa620238a8e63 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 11 Nov 2018 09:27:07 -0800 Subject: [PATCH 21/78] reverted css to UCSC colors, fixed header styling, added placeholder openram logo --- compiler/datasheet/assets/datasheet.css | 8 +++-- .../assets/openram_logo_placeholder.png | Bin 0 -> 44878 bytes compiler/datasheet/datasheet.py | 29 ++++++++++-------- 3 files changed, 22 insertions(+), 15 deletions(-) create mode 100644 compiler/datasheet/assets/openram_logo_placeholder.png diff --git a/compiler/datasheet/assets/datasheet.css b/compiler/datasheet/assets/datasheet.css index 5d4f1470..ff16f101 100644 --- a/compiler/datasheet/assets/datasheet.css +++ b/compiler/datasheet/assets/datasheet.css @@ -1,6 +1,6 @@ diff --git a/compiler/datasheet/assets/openram_logo_placeholder.png b/compiler/datasheet/assets/openram_logo_placeholder.png new file mode 100644 index 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'+ self.name + '.html' + '

' - self.html +='

'+ 'DRC: ' + str(DRC) + '

' - self.html +='

'+ 'LVS: ' + str(LVS) + '

' - self.html +='

Ports and Configuration (DEBUG)

' + self.html += 'VLSIDAOpenRAM' + + + + + + self.html +='

'+ self.name + '.html' + '

' + self.html +='

'+ 'DRC: ' + str(DRC) + '

' + self.html +='

'+ 'LVS: ' + str(LVS) + '

' + + self.html +='

Ports and Configuration (DEBUG)

' self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">") - self.html +='

Operating Conditions

' + self.html +='

Operating Conditions

' self.html += operating_conditions(self.operating,table_id='data').__html__() - self.html += '

Timing and Current Data

' + self.html += '

Timing and Current Data

' self.html += timing_and_current_data(self.timing,table_id='data').__html__() - self.html += '

Characterization Corners

' + self.html += '

Characterization Corners

' self.html += characterization_corners(self.corners,table_id='data').__html__() - self.html +='

Deliverables

' + self.html +='

Deliverables

' self.html += deliverables(self.dlv,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">") - self.html +='

*Feature only supported with characterizer

' + self.html +='

*Feature only supported with characterizer

' - self.html +='VLSIDA' + From fa27d647d2ad2cae92d1bbbac197426a89e6d4bb Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 13 Nov 2018 17:29:43 -0800 Subject: [PATCH 22/78] Flask directory upload POC, embed datasheet.info in html comment for parser reuse --- compiler/datasheet/datasheet.py | 7 +++++++ flask/client/client.py | 28 ++++++++++++++++++++++++++++ flask/client/testfile | 1 + flask/server/server.py | 15 +++++++++++++++ flask/server/templates/upload.html | 11 +++++++++++ 5 files changed, 62 insertions(+) create mode 100644 flask/client/client.py create mode 100644 flask/client/testfile create mode 100644 flask/server/server.py create mode 100644 flask/server/templates/upload.html diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 34eaaf3b..97635c96 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -7,6 +7,7 @@ from in_out import * from hierarchy_design import total_drc_errors from hierarchy_design import total_lvs_errors import os +import csv from globals import OPTS class datasheet(): @@ -40,6 +41,12 @@ class datasheet(): DRC = 'skipped' LVS = 'skipped' PEX = 'skipped' + + with open(OPTS.openram_temp + "/datasheet.info") as info: + self.html += '' self.html += 'VLSIDAOpenRAM' diff --git a/flask/client/client.py b/flask/client/client.py new file mode 100644 index 00000000..9dcd65e6 --- /dev/null +++ b/flask/client/client.py @@ -0,0 +1,28 @@ +import requests +import os +import sys +# TODO +# copy directory structure +# relative links to not break dataseets? +# look into proper string and packet sanitization +# index gui + results graphs + +base_url = 'http://localhost:5000/' +upload_url = 'upload' + +def send_file(path): + upload_file = open(path,'rb') + data = {'file' : upload_file} + return requests.post(url = base_url + upload_url, files = data) + +def send_mkdir(path): + +def send_directory(path): + for root, directories, filenames in os.walk(path): + for filename in filenames: + upload_file = os.path.join(root,filename) + print(upload_file) + print(send_file(upload_file)) + +send_directory(sys.argv[1]) + diff --git a/flask/client/testfile b/flask/client/testfile new file mode 100644 index 00000000..9daeafb9 --- /dev/null +++ b/flask/client/testfile @@ -0,0 +1 @@ +test diff --git a/flask/server/server.py b/flask/server/server.py new file mode 100644 index 00000000..78c39128 --- /dev/null +++ b/flask/server/server.py @@ -0,0 +1,15 @@ +import os +from flask import Flask, render_template, request +from werkzeug import secure_filename +app = Flask(__name__) + +@app.route('/uploader', methods = ['GET', 'POST']) +def upload(): + if request.method == 'POST': + f = request.files['file'] + dirname = os.path.dirname(os.path.abspath(__file__)) + f.save(dirname + '/uploads/' + secure_filename(f.filename)) + return 'file uploaded successfully' + +if __name__ == '__main__': + app.run(debug = True) diff --git a/flask/server/templates/upload.html b/flask/server/templates/upload.html new file mode 100644 index 00000000..761844f6 --- /dev/null +++ b/flask/server/templates/upload.html @@ -0,0 +1,11 @@ + + + +
+ + +
+ + + From 8b6a28b6fd6cf0153b7bbc6ab0519119dbf375f9 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 13 Nov 2018 22:24:18 -0800 Subject: [PATCH 23/78] Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell. --- compiler/characterizer/functional.py | 4 +- compiler/modules/control_logic.py | 1 + technology/scn4m_subm/gds_lib/cell_1rw_1r.gds | Bin 6202 -> 6266 bytes technology/scn4m_subm/mag_lib/cell_1rw_1r.mag | 210 +++++++++--------- technology/scn4m_subm/sp_lib/cell_1rw_1r.sp | 20 +- 5 files changed, 116 insertions(+), 119 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index b99e644c..0c60fc23 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -40,8 +40,8 @@ class functional(simulation): """Spice constants for functional test""" simulation.set_spice_constants(self) #Heuristic increase for functional period. Base feasible period typically does not pass the functional test - #for column mux of this size. Increase the feasible period by 20% for this case. - if self.sram.words_per_row >= 4: + #for column mux or srams of this size. Increase the feasible period by 20% for this case. + if self.sram.words_per_row >= 4 or self.sram.num_cols*self.sram.num_rows >= 1024: self.period = self.period*1.2 def run(self): diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 21595698..88b6390c 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -31,6 +31,7 @@ class control_logic(design.design): #This is needed to resize the delay chain. Likely to be changed at some point. self.sram=sram + #self.sram=None #disable re-sizing for debugging self.wl_timing_tolerance = 1 #Determines how much larger the sen delay should be. Accounts for possible error in model. self.parasitic_inv_delay = 0 #Keeping 0 for now until further testing. diff --git a/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds b/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds index 4254ba26d107b9392f1889275302e2b261d967b4..21f2c8c84ae9852bb18b5b1e63d7161aa74b840d 100644 GIT binary patch literal 6266 zcmbW5Ka5pH6vhwx=dr*74}}$Ul~q9271&+K%A$$E#Dc`e!h+aH6e9&Oh5{(J)Q*zG zW;-dj+|tTWZfR*rxuvDw@6G+Z^B$fd@g{eFH{Z-RXXeb@nfo>dF%{FXcwj0X#*sK0 z3%UpYJ`dxQ7)}ko`~Lp@Z`L0?(j9SfdiK-Le!2d|AHVJ2_OUgi>pz#eCVfFSrKf)4P?z{7?Vy{| zYyYKs{CJkPOMLUnU!^Tmdg>=n&Vfmr=%)1A|6v`UK5i^UEIjMEd9(E0RC($@dP@sQ zZ4B@Ay!>SZx~cNiPkj8uH}RpHE&rM4#kcsPCq8tu<)@#lUHm5f@VL72wEqX^O009s zJ!uQwR9{j*?K5`jn)Dsrl%D#DLtWyV%ssj(J@u1k>Jr;Lyj=2cO0WHE_4+xfTyMOH zIHfgfUVp63O1ddM^&i}ec=Jibp*uYnwI0z;m8bq=!{R%>-4h?W+42*co4RKG+?A*C zm-dS9y*oYeqnm0Y^^>PFQSxUJ6Wx@a`pFYxC4VNlKsTkQe&QVav&1)t_ey+Idg^DK z#AW;@ana3Id^{^!uhcbp|Ikh8X?*&RkM(EbLpNJ~a*U6;GV!6CEkAL{HSx_ucS?Ly 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b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag index 85323b17..3c3206dc 100644 --- a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag @@ -1,110 +1,106 @@ magic tech scmos -timestamp 1541193956 +timestamp 1542175986 << nwell >> -rect 0 50 54 79 +rect 0 46 54 75 << pwell >> -rect 0 0 54 50 +rect 0 0 54 46 << ntransistor >> -rect 14 35 16 41 -rect 22 29 24 41 -rect 30 29 32 41 -rect 38 35 40 41 -rect 14 17 16 25 -rect 22 17 24 25 -rect 30 17 32 25 -rect 38 17 40 25 +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 << ptransistor >> -rect 22 58 24 62 -rect 30 58 32 62 +rect 22 54 24 57 +rect 30 54 32 57 << ndiffusion >> -rect 9 39 14 41 -rect 13 35 14 39 -rect 16 35 17 41 -rect 21 33 22 41 +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 rect 17 29 22 33 -rect 24 29 25 41 -rect 29 29 30 41 -rect 32 33 33 41 -rect 37 35 38 41 -rect 40 39 45 41 -rect 40 35 41 39 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 rect 32 29 37 33 -rect 9 23 14 25 -rect 13 19 14 23 -rect 9 17 14 19 -rect 16 17 22 25 -rect 24 17 25 25 -rect 29 17 30 25 -rect 32 17 38 25 -rect 40 23 45 25 -rect 40 19 41 23 -rect 40 17 45 19 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 << pdiffusion >> -rect 21 58 22 62 -rect 24 58 25 62 -rect 29 58 30 62 -rect 32 58 33 62 +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 << ndcontact >> -rect 9 35 13 39 -rect 17 33 21 41 -rect 25 29 29 41 -rect 33 33 37 41 -rect 41 35 45 39 -rect 9 19 13 23 -rect 25 17 29 25 -rect 41 19 45 23 +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 << pdcontact >> -rect 17 58 21 62 -rect 25 58 29 62 -rect 33 58 37 62 +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 << psubstratepcontact >> rect 25 9 29 13 << nsubstratencontact >> -rect 25 72 29 76 +rect 25 68 29 72 << polysilicon >> -rect 22 62 24 64 -rect 30 62 32 64 -rect 22 48 24 58 -rect 30 55 32 58 -rect 31 51 32 55 -rect 14 41 16 46 -rect 22 44 23 48 -rect 22 41 24 44 -rect 30 41 32 51 -rect 38 41 40 46 -rect 14 33 16 35 -rect 38 33 40 35 -rect 14 25 16 26 -rect 22 25 24 29 -rect 30 25 32 29 -rect 38 25 40 26 +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 << polycontact >> -rect 27 51 31 55 -rect 10 42 14 46 -rect 23 44 27 48 -rect 40 42 44 46 -rect 12 26 16 30 -rect 38 26 42 30 +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> -rect 0 72 25 76 -rect 29 72 54 76 -rect 0 65 54 69 -rect 10 46 14 65 -rect 17 55 20 58 -rect 17 51 27 55 -rect 17 41 20 51 -rect 34 48 37 58 -rect 27 44 37 48 -rect 34 41 37 44 -rect 40 46 44 65 -rect 6 35 9 39 -rect 45 35 48 39 -rect 25 25 29 29 +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 6 33 9 37 +rect 45 33 48 37 +rect 25 23 29 29 rect 25 13 29 17 rect 0 9 25 13 rect 29 9 54 13 @@ -112,37 +108,37 @@ rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 << m2contact >> -rect 25 72 29 76 -rect 25 58 29 62 -rect 2 35 6 39 -rect 16 26 20 30 -rect 48 35 52 39 -rect 34 26 38 30 -rect 9 19 13 23 -rect 41 19 45 23 +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 rect 16 2 20 6 rect 34 2 38 6 << metal2 >> -rect 2 39 6 76 -rect 2 0 6 35 -rect 9 23 13 76 -rect 25 62 29 72 -rect 9 0 13 19 -rect 16 6 20 26 -rect 34 6 38 26 -rect 41 23 45 76 -rect 41 0 45 19 -rect 48 39 52 76 -rect 48 0 52 35 +rect 2 37 6 72 +rect 2 0 6 33 +rect 9 21 13 72 +rect 25 58 29 68 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 72 +rect 41 0 45 17 +rect 48 37 52 72 +rect 48 0 52 33 << bb >> -rect 0 0 54 74 +rect 0 0 54 70 << labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd rlabel metal1 27 4 27 4 1 wl1 rlabel psubstratepcontact 27 11 27 11 1 gnd -rlabel metal1 19 67 19 67 1 wl0 rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 74 19 74 5 vdd << end >> diff --git a/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp index 1a52d8d0..37f25f75 100644 --- a/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp +++ b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp @@ -1,14 +1,14 @@ .SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1 gnd n w=1.6u l=0.4u -MM8 RA_to_R_right Q gnd gnd n w=1.6u l=0.4u -MM7 RA_to_R_left Q_bar gnd gnd n w=1.6u l=0.4u -MM6 RA_to_R_left wl1 bl1 gnd n w=1.6u l=0.4u -MM5 Q wl0 bl0 gnd n w=1.2u l=0.4u -MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.4u -MM1 Q Q_bar gnd gnd n w=2.4u l=0.4u -MM0 Q_bar Q gnd gnd n w=2.4u l=0.4u -MM3 Q Q_bar vdd vdd p w=0.8u l=0.4u -MM2 Q_bar Q vdd vdd p w=0.8u l=0.4u +MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u +MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u +MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u +MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u +MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u +MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u +MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u +MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u .ENDS From 80bc5b49c18f8cc5e0a910d306a7e27e7a6afab1 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 14 Nov 2018 11:00:37 -0800 Subject: [PATCH 24/78] Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell. --- technology/scn4m_subm/gds_lib/cell_1rw_1r.gds | Bin 6266 -> 6330 bytes .../gds_lib/replica_cell_1rw_1r.gds | Bin 6154 -> 6282 bytes technology/scn4m_subm/mag_lib/cell_1rw_1r.mag | 20 +- .../mag_lib/replica_cell_1rw_1r.mag | 214 +++++++++--------- .../scn4m_subm/sp_lib/replica_cell_1rw_1r.sp | 20 +- 5 files changed, 124 insertions(+), 130 deletions(-) diff --git a/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds b/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds index 21f2c8c84ae9852bb18b5b1e63d7161aa74b840d..71a6dfad712d467bf3ecdd960616c44e1f0af033 100644 GIT binary patch delta 98 zcmexmu**=1fsKKQftf*uk%^&xoLb!dQeiCS4NSTq5qq2mm%{ B37`M~ diff --git a/technology/scn4m_subm/gds_lib/replica_cell_1rw_1r.gds b/technology/scn4m_subm/gds_lib/replica_cell_1rw_1r.gds index 836708c38bbe673c0c5431b6f533e66012094baa..2697651dcbb09baa6b17a15e84834f363d14a3e7 100644 GIT binary patch literal 6282 zcmbW5J#dvp6owD^BR~j=LQFJD6p)DgBruU+p*Ul~42^{aV*?6|IFoUh6hN6$J4$A3 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zLpP6?w=^Men!R{p1*_QY!U{ZIEQ?O4O_ZKnQ~yW45q zG;tM^-z(MMcU!e~?8DuzC%>-#*nfB0?bO=wo3z{Y#O5u;a DM*mrR diff --git a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag index 3c3206dc..9aec1c5d 100644 --- a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1542175986 +timestamp 1542220294 << nwell >> rect 0 46 54 75 << pwell >> @@ -47,17 +47,12 @@ rect 17 33 21 37 rect 25 29 29 37 rect 33 33 37 37 rect 41 33 45 37 -rect 9 17 13 21 rect 25 17 29 23 -rect 41 17 45 21 << pdcontact >> rect 17 54 21 58 -rect 25 54 29 58 rect 33 54 37 58 << psubstratepcontact >> rect 25 9 29 13 -<< nsubstratencontact >> -rect 25 68 29 72 << polysilicon >> rect 22 57 24 60 rect 30 57 32 60 @@ -108,16 +103,19 @@ rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 << m2contact >> -rect 25 68 29 72 -rect 25 54 29 58 rect 2 33 6 37 rect 48 33 52 37 rect 16 24 20 28 rect 34 24 38 28 -rect 9 17 13 21 -rect 41 17 45 21 rect 16 2 20 6 rect 34 2 38 6 +<< pdm12contact >> +rect 25 54 29 58 +<< ndm12contact >> +rect 9 17 13 21 +rect 41 17 45 21 +<< nsm12contact >> +rect 25 68 29 72 << metal2 >> rect 2 37 6 72 rect 2 0 6 33 @@ -130,7 +128,7 @@ rect 41 21 45 72 rect 41 0 45 17 rect 48 37 52 72 rect 48 0 52 33 -<< bb >> +<< comment >> rect 0 0 54 70 << labels >> rlabel metal1 19 63 19 63 1 wl0 diff --git a/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag index 38edce07..f215ff04 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag @@ -1,111 +1,107 @@ magic tech scmos -timestamp 1541194096 +timestamp 1542221056 << nwell >> -rect 0 50 54 79 +rect 0 46 54 75 << pwell >> -rect 0 0 54 50 +rect 0 0 54 46 << ntransistor >> -rect 14 35 16 41 -rect 22 29 24 41 -rect 30 29 32 41 -rect 38 35 40 41 -rect 14 17 16 25 -rect 22 17 24 25 -rect 30 17 32 25 -rect 38 17 40 25 +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 << ptransistor >> -rect 22 58 24 62 -rect 30 58 32 62 +rect 22 54 24 57 +rect 30 54 32 57 << ndiffusion >> -rect 9 39 14 41 -rect 13 35 14 39 -rect 16 35 17 41 -rect 21 33 22 41 +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 rect 17 29 22 33 -rect 24 29 25 41 -rect 29 29 30 41 -rect 32 33 33 41 -rect 37 35 38 41 -rect 40 39 45 41 -rect 40 35 41 39 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 rect 32 29 37 33 -rect 9 23 14 25 -rect 13 19 14 23 -rect 9 17 14 19 -rect 16 17 22 25 -rect 24 17 25 25 -rect 29 17 30 25 -rect 32 17 38 25 -rect 40 23 45 25 -rect 40 19 41 23 -rect 40 17 45 19 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 << pdiffusion >> -rect 21 58 22 62 -rect 24 58 25 62 -rect 29 58 30 62 -rect 32 58 33 62 +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 << ndcontact >> -rect 9 35 13 39 -rect 17 33 21 41 -rect 25 29 29 41 -rect 33 33 37 41 -rect 41 35 45 39 -rect 9 19 13 23 -rect 25 17 29 25 -rect 41 19 45 23 +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 << pdcontact >> -rect 17 58 21 62 -rect 25 58 29 62 -rect 33 58 37 62 +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 << psubstratepcontact >> rect 25 9 29 13 << nsubstratencontact >> -rect 25 72 29 76 +rect 25 68 29 72 << polysilicon >> -rect 22 62 24 64 -rect 30 62 32 64 -rect 22 48 24 58 -rect 30 55 32 58 -rect 31 51 32 55 -rect 14 41 16 46 -rect 22 44 23 48 -rect 22 41 24 44 -rect 30 41 32 51 -rect 38 41 40 46 -rect 14 33 16 35 -rect 38 33 40 35 -rect 14 25 16 26 -rect 22 25 24 29 -rect 30 25 32 29 -rect 38 25 40 26 +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 rect 14 15 16 17 rect 22 15 24 17 rect 30 15 32 17 rect 38 15 40 17 << polycontact >> -rect 27 51 31 55 -rect 10 42 14 46 -rect 23 44 27 48 -rect 40 42 44 46 -rect 12 26 16 30 -rect 38 26 42 30 +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 << metal1 >> -rect 0 72 25 76 -rect 29 72 54 76 -rect 0 65 54 69 -rect 10 46 14 65 -rect 29 58 33 62 -rect 17 55 20 58 -rect 17 51 27 55 -rect 17 41 20 51 -rect 34 48 37 58 -rect 27 44 37 48 -rect 34 41 37 44 -rect 40 46 44 65 -rect 6 35 9 39 -rect 45 35 48 39 -rect 25 25 29 29 +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 29 54 33 58 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 6 33 9 37 +rect 45 33 48 37 +rect 25 23 29 29 rect 25 13 29 17 rect 0 9 25 13 rect 29 9 54 13 @@ -113,37 +109,37 @@ rect 0 2 16 6 rect 20 2 34 6 rect 38 2 54 6 << m2contact >> -rect 25 72 29 76 -rect 25 58 29 62 -rect 2 35 6 39 -rect 16 26 20 30 -rect 48 35 52 39 -rect 34 26 38 30 -rect 9 19 13 23 -rect 41 19 45 23 +rect 25 68 29 72 +rect 25 54 29 58 +rect 2 33 6 37 +rect 48 33 52 37 +rect 16 24 20 28 +rect 34 24 38 28 +rect 9 17 13 21 +rect 41 17 45 21 rect 16 2 20 6 rect 34 2 38 6 << metal2 >> -rect 2 39 6 76 -rect 2 0 6 35 -rect 9 23 13 76 -rect 25 62 29 72 -rect 9 0 13 19 -rect 16 6 20 26 -rect 34 6 38 26 -rect 41 23 45 76 -rect 41 0 45 19 -rect 48 39 52 76 -rect 48 0 52 35 -<< bb >> -rect 0 0 54 74 +rect 2 37 6 72 +rect 2 0 6 33 +rect 9 21 13 72 +rect 25 58 29 68 +rect 9 0 13 17 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 21 45 72 +rect 41 0 45 17 +rect 48 37 52 72 +rect 48 0 52 33 +<< comment >> +rect 0 0 54 70 << labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd rlabel metal1 27 4 27 4 1 wl1 rlabel psubstratepcontact 27 11 27 11 1 gnd -rlabel metal1 19 67 19 67 1 wl0 rlabel metal2 4 7 4 7 2 bl0 rlabel metal2 11 7 11 7 1 bl1 rlabel metal2 43 7 43 7 1 br1 rlabel metal2 50 7 50 7 8 br0 -rlabel metal1 19 74 19 74 5 vdd << end >> diff --git a/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp index 0a235af8..94bdb75e 100644 --- a/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp +++ b/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp @@ -1,14 +1,14 @@ .SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd -MM9 RA_to_R_right wl1 br1 gnd n w=1.6u l=0.4u -MM8 RA_to_R_right Q gnd gnd n w=1.6u l=0.4u -MM7 RA_to_R_left vdd gnd gnd n w=1.6u l=0.4u -MM6 RA_to_R_left wl1 bl1 gnd n w=1.6u l=0.4u -MM5 Q wl0 bl0 gnd n w=1.2u l=0.4u -MM4 vdd wl0 br0 gnd n w=1.2u l=0.4u -MM1 Q vdd gnd gnd n w=2.4u l=0.4u -MM0 vdd Q gnd gnd n w=2.4u l=0.4u -MM3 Q vdd vdd vdd p w=0.8u l=0.4u -MM2 vdd Q vdd vdd p w=0.8u l=0.4u +MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u +MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u +MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u +MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u +MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u +MM1 Q vdd gnd gnd n w=1.6u l=0.4u +MM0 vdd Q gnd gnd n w=1.6u l=0.4u +MM3 Q vdd vdd vdd p w=0.6u l=0.4u +MM2 vdd Q vdd vdd p w=0.6u l=0.4u .ENDS From 05773ad16e8e98dd5c3c41e542ea5742b3ca5a76 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 14 Nov 2018 11:53:13 -0800 Subject: [PATCH 25/78] Altered 1rw,1r cell and replica to match tx widths pbitcell in freepdk45 --- technology/freepdk45/gds_lib/cell_1rw_1r.gds | Bin 16384 -> 14336 bytes .../freepdk45/gds_lib/replica_cell_1rw_1r.gds | Bin 16384 -> 14336 bytes technology/freepdk45/sp_lib/cell_1rw_1r.sp | 4 ++-- .../freepdk45/sp_lib/replica_cell_1rw_1r.sp | 4 ++-- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git 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compiler/characterizer/logical_effort.py | 19 ++++++--- compiler/modules/bank.py | 4 +- compiler/modules/control_logic.py | 51 ++++++++++++++++-------- compiler/modules/delay_chain.py | 6 ++- compiler/modules/replica_bitline.py | 12 ++++-- compiler/modules/wordline_driver.py | 10 +++-- compiler/pgates/pinv.py | 8 ++-- compiler/pgates/pinvbuf.py | 18 +++++---- compiler/pgates/pnand2.py | 8 ++-- compiler/pgates/pnand3.py | 8 ++-- compiler/sram_base.py | 4 +- 11 files changed, 97 insertions(+), 51 deletions(-) diff --git a/compiler/characterizer/logical_effort.py b/compiler/characterizer/logical_effort.py index 7d3a2eb9..b54124d5 100644 --- a/compiler/characterizer/logical_effort.py +++ b/compiler/characterizer/logical_effort.py @@ -10,12 +10,13 @@ class logical_effort(): min_inv_cin = 1+beta pinv=parameter["min_inv_para_delay"] - def __init__(self, size, cin, cout, parasitic): + def __init__(self, size, cin, cout, parasitic, out_is_rise=True): self.cin = cin self.cout = cout self.logical_effort = (self.cin/size)/logical_effort.min_inv_cin self.eletrical_effort = self.cout/self.cin self.parasitic_scale = parasitic + self.is_rise = out_is_rise def __str__(self): return "g = " + str(self.logical_effort) + ", h = " + str(self.eletrical_effort) + ", p = " + str(self.parasitic_scale)+"*pinv" @@ -31,8 +32,16 @@ class logical_effort(): def calculate_relative_delay(stage_effort_list, pinv=parameter["min_inv_para_delay"]): """Calculates the total delay of a given delay path made of a list of logical effort objects.""" - total_delay = 0 + total_rise_delay, total_fall_delay = calculate_relative_rise_fall_delays(stage_effort_list, pinv) + return total_rise_delay + total_fall_delay + +def calculate_relative_rise_fall_delays(stage_effort_list, pinv=parameter["min_inv_para_delay"]): + """Calculates the rise/fall delays of a given delay path made of a list of logical effort objects.""" + total_rise_delay, total_fall_delay = 0,0 for stage in stage_effort_list: - total_delay += stage.get_stage_delay(pinv) - return total_delay - \ No newline at end of file + if stage.is_rise: + total_rise_delay += stage.get_stage_delay(pinv) + else: + total_fall_delay += stage.get_stage_delay(pinv) + return total_rise_delay, total_fall_delay + \ No newline at end of file diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index cc379493..8c083517 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1225,12 +1225,12 @@ class bank(design.design): return results - def determine_wordline_stage_efforts(self, external_cout): + def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline""" #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption stage_effort_list = [] wordline_cout = self.bitcell_array.get_wordline_cin() + external_cout - stage_effort_list += self.wordline_driver.determine_wordline_stage_efforts(wordline_cout) + stage_effort_list += self.wordline_driver.determine_wordline_stage_efforts(wordline_cout,inp_is_rise) return stage_effort_list diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 90755e96..23d82998 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -109,7 +109,8 @@ class control_logic(design.design): #Resize the delay chain (by instantiating a new rbl) if the analytical timing failed. delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_resized_"+self.port_type) - + self.sen_delay = self.get_delay_to_sen() #get the new timing + self.add_mod(self.replica_bitline) def get_heuristic_delay_chain_size(self): @@ -139,6 +140,7 @@ class control_logic(design.design): def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" + from math import ceil previous_delay_chain_delay = (previous_fanout+1+self.parasitic_inv_delay)*previous_stages debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) @@ -147,7 +149,7 @@ class control_logic(design.design): #inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value required_delay = self.wl_delay*self.wl_timing_tolerance - (self.sen_delay-previous_delay_chain_delay) debug.check(required_delay > 0, "Cannot size delay chain to have negative delay") - delay_stages = int(required_delay/(delay_fanout+1+self.parasitic_inv_delay)) + delay_stages = ceil(required_delay/(delay_fanout+1+self.parasitic_inv_delay)) if delay_stages%2 == 1: #force an even number of stages. delay_stages+=1 #Fanout can be varied as well but is a little more complicated but potentially optimal. @@ -638,25 +640,33 @@ class control_logic(design.design): height=pin.height(), width=pin.width()) + def get_delay_to_wl(self): """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") stage_efforts = self.determine_wordline_stage_efforts() - clk_to_wl_delay = logical_effort.calculate_relative_delay(stage_efforts, self.parasitic_inv_delay) - debug.info(1, "Clock to wordline delay is {} delay units".format(clk_to_wl_delay)) - return clk_to_wl_delay + clk_to_wl_rise,clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(stage_efforts, self.parasitic_inv_delay) + total_delay = clk_to_wl_rise + clk_to_wl_fall + debug.info(1, "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, clk_to_wl_fall,total_delay)) + return total_delay + def determine_wordline_stage_efforts(self): """Follows the clock signal to the clk_buf signal to the wordline signal for the total path efforts""" stage_effort_list = [] + + #Initial direction of clock signal for this path + is_clk_rise = False + #Calculate the load on clk_buf within the module and add it to external load internal_cout = self.ctrl_dff_array.get_clk_cin() external_cout = self.sram.get_clk_cin() #First stage is the clock buffer - stage_effort_list += self.clkbuf.determine_clk_buf_stage_efforts(internal_cout+external_cout) + stage_effort_list += self.clkbuf.determine_clk_buf_stage_efforts(internal_cout+external_cout, is_clk_rise) + last_stage_is_rise = stage_effort_list[-1].is_rise #Then ask the sram for the other path delays (from the bank) - stage_effort_list += self.sram.determine_wordline_stage_efforts() + stage_effort_list += self.sram.determine_wordline_stage_efforts(last_stage_is_rise) return stage_effort_list @@ -666,9 +676,10 @@ class control_logic(design.design): """ debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") stage_efforts = self.determine_sa_enable_stage_efforts() - clk_to_sen_delay = logical_effort.calculate_relative_delay(stage_efforts, self.parasitic_inv_delay) - debug.info(1, "Clock to s_en delay is {} delay units".format(clk_to_sen_delay)) - return clk_to_sen_delay + clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(stage_efforts, self.parasitic_inv_delay) + total_delay = clk_to_sen_rise + clk_to_sen_fall + debug.info(1, "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, clk_to_sen_fall,total_delay)) + return total_delay def determine_sa_enable_stage_efforts(self): """Follows the clock signal to the sense amp enable signal adding each stages stage effort to a list""" @@ -677,33 +688,41 @@ class control_logic(design.design): int_clk_buf_cout = self.get_clk_buf_bar_cin() ext_clk_buf_cout = self.sram.get_clk_bar_cin() + #Initial direction of clock signal for this path + is_clk_rise = False + #First stage is the clock buffer - stage1 = self.clkbuf.determine_clk_buf_bar_stage_efforts(int_clk_buf_cout+ext_clk_buf_cout) + stage1 = self.clkbuf.determine_clk_buf_bar_stage_efforts(int_clk_buf_cout+ext_clk_buf_cout, is_clk_rise) stage_effort_list += stage1 + last_stage_rise = stage_effort_list[-1].is_rise #nand2 stage stage2_cout = self.inv1.get_cin() - stage2 = self.nand2.get_effort_stage(stage2_cout) + stage2 = self.nand2.get_effort_stage(stage2_cout, last_stage_rise) stage_effort_list.append(stage2) + last_stage_rise = stage_effort_list[-1].is_rise #inverter stage stage3_cout = self.replica_bitline.get_en_cin() - stage3 = self.inv1.get_effort_stage(stage3_cout) + stage3 = self.inv1.get_effort_stage(stage3_cout, last_stage_rise) stage_effort_list.append(stage3) + last_stage_rise = stage_effort_list[-1].is_rise #Replica bitline stage stage4_cout = self.inv2.get_cin() - stage4 = self.replica_bitline.determine_sen_stage_efforts(stage4_cout) + stage4 = self.replica_bitline.determine_sen_stage_efforts(stage4_cout, last_stage_rise) stage_effort_list += stage4 + last_stage_rise = stage_effort_list[-1].is_rise #inverter (inv2) stage stage5_cout = self.inv8.get_cin() - stage5 = self.inv2.get_effort_stage(stage5_cout) + stage5 = self.inv2.get_effort_stage(stage5_cout, last_stage_rise) stage_effort_list.append(stage5) + last_stage_rise = stage_effort_list[-1].is_rise #inverter (inv8) stage, s_en output clk_sen_cout = self.sram.get_sen_cin() - stage6 = self.inv8.get_effort_stage(clk_sen_cout) + stage6 = self.inv8.get_effort_stage(clk_sen_cout, last_stage_rise) stage_effort_list.append(stage6) return stage_effort_list diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index 72dfe93a..722328d1 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -225,15 +225,17 @@ class delay_chain(design.design): dc_cin = self.inv.get_cin() return dc_cin - def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout): + def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout, inp_is_rise=True): """Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load.""" stage_effort_list = [] #Add a stage to the list for every stage in delay chain. Stages only differ in fanout except the last which has an external cout. + last_stage_is_rise = inp_is_rise for stage_fanout in self.fanout_list: stage_cout = self.inv.get_cin()*(stage_fanout+1) if len(stage_effort_list) == len(self.fanout_list)-1: #last stage stage_cout+=ext_delayed_en_cout - stage = self.inv.get_effort_stage(stage_cout) + stage = self.inv.get_effort_stage(stage_cout, last_stage_is_rise) stage_effort_list.append(stage) + last_stage_is_rise = stage.is_rise return stage_effort_list \ No newline at end of file diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index 905bd4ff..65320666 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -615,17 +615,21 @@ class replica_bitline(design.design): en_cin = self.delay_chain.get_cin() return en_cin - def determine_sen_stage_efforts(self, ext_cout): + def determine_sen_stage_efforts(self, ext_cout, inp_is_rise=True): """Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load.""" stage_effort_list = [] #Stage 1 is the delay chain stage1_cout = self.get_delayed_en_cin() - stage1 = self.delay_chain.determine_delayed_en_stage_efforts(stage1_cout) + stage1 = self.delay_chain.determine_delayed_en_stage_efforts(stage1_cout, inp_is_rise) stage_effort_list += stage1 + #There is a disconnect between the delay chain and inverter. The rise/fall of the input to the inverter + #Will be the negation of the previous stage. + last_stage_is_rise = not stage_effort_list[-1].is_rise + #The delay chain triggers the enable on the replica bitline (rbl). This is used to track the bitline delay whereas this - #model is intended to track every but that. Therefore, the next stage is the inverter after the rbl. - stage2 = self.inv.get_effort_stage(ext_cout) + #model is intended to track every but that. Therefore, the next stage is the inverter after the rbl. + stage2 = self.inv.get_effort_stage(ext_cout, last_stage_is_rise) stage_effort_list.append(stage2) return stage_effort_list diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 67ac3743..d21fa391 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -240,18 +240,20 @@ class wordline_driver(design.design): """Gets the capacitance of the wordline driver in absolute units (fF)""" return self.nand2.input_load() - def determine_wordline_stage_efforts(self, external_cout): + def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): """Follows the clk_buf to a wordline signal adding each stages stage effort to a list""" stage_effort_list = [] stage1_cout = self.nand2.get_cin() - stage1 = self.inv_no_output.get_effort_stage(stage1_cout) + stage1 = self.inv_no_output.get_effort_stage(stage1_cout, inp_is_rise) stage_effort_list.append(stage1) + last_stage_is_rise = stage1.is_rise stage2_cout = self.inv.get_cin() - stage2 = self.nand2.get_effort_stage(stage2_cout) + stage2 = self.nand2.get_effort_stage(stage2_cout, last_stage_is_rise) stage_effort_list.append(stage2) + last_stage_is_rise = stage2.is_rise - stage3 = self.inv.get_effort_stage(external_cout) + stage3 = self.inv.get_effort_stage(external_cout, last_stage_is_rise) stage_effort_list.append(stage3) return stage_effort_list diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 4d59b715..31682360 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -288,7 +288,9 @@ class pinv(pgate.pgate): """Return the capacitance of the gate connection in generic capacitive units relative to the minimum width of a transistor""" return self.nmos_size + self.pmos_size - def get_effort_stage(self, cout): - """Returns an object representing the parameters for delay in tau units.""" + def get_effort_stage(self, cout, inp_is_rise=True): + """Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. Input inverted by this stage. + """ parasitic_delay = 1 - return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay) \ No newline at end of file + return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 23826cd2..13c376cf 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -187,30 +187,34 @@ class pinvbuf(design.design): inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load) return inv1_delay + inv2_delay - def determine_clk_buf_stage_efforts(self, external_cout): + def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False): """Get the stage efforts of the clk -> clk_buf path""" stage_effort_list = [] stage1_cout = self.inv1.get_cin() + self.inv2.get_cin() - stage1 = self.inv.get_effort_stage(stage1_cout) + stage1 = self.inv.get_effort_stage(stage1_cout, inp_is_rise) stage_effort_list.append(stage1) + last_stage_is_rise = stage1.is_rise - stage2 = self.inv2.get_effort_stage(external_cout) + stage2 = self.inv2.get_effort_stage(external_cout, last_stage_is_rise) stage_effort_list.append(stage2) return stage_effort_list - def determine_clk_buf_bar_stage_efforts(self, external_cout): + def determine_clk_buf_bar_stage_efforts(self, external_cout, inp_is_rise=False): """Get the stage efforts of the clk -> clk_buf path""" + #After (almost) every stage, the direction of the signal inverts. stage_effort_list = [] stage1_cout = self.inv1.get_cin() + self.inv2.get_cin() - stage1 = self.inv.get_effort_stage(stage1_cout) + stage1 = self.inv.get_effort_stage(stage1_cout, inp_is_rise) stage_effort_list.append(stage1) + last_stage_is_rise = stage_effort_list[-1].is_rise stage2_cout = self.inv2.get_cin() - stage2 = self.inv1.get_effort_stage(stage2_cout) + stage2 = self.inv1.get_effort_stage(stage2_cout, last_stage_is_rise) stage_effort_list.append(stage2) + last_stage_is_rise = stage_effort_list[-1].is_rise - stage3 = self.inv2.get_effort_stage(external_cout) + stage3 = self.inv2.get_effort_stage(external_cout, last_stage_is_rise) stage_effort_list.append(stage3) return stage_effort_list \ No newline at end of file diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index a79a7264..dc452f12 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -249,7 +249,9 @@ class pnand2(pgate.pgate): """Return the relative input capacitance of a single input""" return self.nmos_size+self.pmos_size - def get_effort_stage(self, cout): - """Returns an object representing the parameters for delay in tau units.""" + def get_effort_stage(self, cout, inp_is_rise=True): + """Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. Input inverted by this stage. + """ parasitic_delay = 2 - return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay) \ No newline at end of file + return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) \ No newline at end of file diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 555ee5b0..4dab5264 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -267,7 +267,9 @@ class pnand3(pgate.pgate): """Return the relative input capacitance of a single input""" return self.nmos_size+self.pmos_size - def get_effort_stage(self, cout): - """Returns an object representing the parameters for delay in tau units.""" + def get_effort_stage(self, cout, inp_is_rise=True): + """Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. Input inverted by this stage. + """ parasitic_delay = 3 - return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay) \ No newline at end of file + return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) \ No newline at end of file diff --git a/compiler/sram_base.py b/compiler/sram_base.py index d09ea2cd..9e8953dd 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -488,13 +488,13 @@ class sram_base(design): """ LH and HL are the same in analytical model. """ return self.bank.analytical_delay(vdd,slew,load) - def determine_wordline_stage_efforts(self): + def determine_wordline_stage_efforts(self, inp_is_rise=True): """Get the all the stage efforts for each stage in the path from clk_buf to a wordline""" stage_effort_list = [] #Clk_buf originates from the control logic so only the bank is related to the wordline path external_wordline_cout = 0 #No loading on the wordline other than in the bank. - stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout) + stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout, inp_is_rise) return stage_effort_list From 3716030a23ab071030ef919522cbd7d47ea89bd0 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 16 Nov 2018 16:57:22 -0800 Subject: [PATCH 27/78] Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts. --- compiler/characterizer/delay.py | 43 +-------------- compiler/modules/control_logic.py | 82 +++++++++++++++++++++++++---- compiler/modules/replica_bitline.py | 7 ++- 3 files changed, 76 insertions(+), 56 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 6b97fa52..3e103fc7 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -208,7 +208,7 @@ class delay(simulation): trig_slew_low = 0.1 * self.vdd_voltage targ_slew_high = 0.9 * self.vdd_voltage if 'delay' in delay_name: - trig_dir="RISE" + trig_dir="RISE" #FALL trig_val = half_vdd targ_val = half_vdd trig_name = trig_clk_name @@ -429,6 +429,7 @@ class delay(simulation): delay_names = ["{0}{1}".format(mname,port) for mname in self.delay_meas_names] delay_names = [mname for mname in self.delay_meas_names] delays = self.parse_values(delay_names, port, 1e9) # scale delays to ns + debug.info(2,"Delay values = {}".format(delays)) if not self.check_valid_delays(tuple(delays.values())): return (False,{}) result[port].update(delays) @@ -646,18 +647,6 @@ class delay(simulation): # slew=0.04 # self.try_period(target_period, feasible_delay_lh, feasible_delay_hl) # sys.exit(1) - - #For debugging, skips characterization and returns dummy values. - # char_data = self.get_empty_measure_data_dict() - # i = 1.0 - # for slew in slews: - # for load in loads: - # for k,v in char_data.items(): - # char_data[k].append(i) - # i+=1.0 - # char_data["min_period"] = i - # char_data["leakage_power"] = i+1.0 - # return char_data # 1) Find a feasible period and it's corresponding delays using the trimmed array. feasible_delays = self.find_feasible_period() @@ -834,34 +823,6 @@ class delay(simulation): return (sram_data,port_data) - # delay_lh = [] - # delay_hl = [] - # slew_lh = [] - # slew_hl = [] - # for slew in slews: - # for load in loads: - # self.set_load_slew(load,slew) - # bank_delay = sram.analytical_delay(self.vdd_voltage, self.slew,self.load) - # # Convert from ps to ns - # delay_lh.append(bank_delay.delay/1e3) - # delay_hl.append(bank_delay.delay/1e3) - # slew_lh.append(bank_delay.slew/1e3) - # slew_hl.append(bank_delay.slew/1e3) - - # power = self.analytical_power() - - # sram_data = { "min_period": 0, - # "leakage_power": power.leakage} - # port_data = [{"delay_lh": delay_lh, - # "delay_hl": delay_hl, - # "slew_lh": slew_lh, - # "slew_hl": slew_hl, - # "read0_power": power.dynamic, - # "read1_power": power.dynamic, - # "write0_power": power.dynamic, - # "write1_power": power.dynamic, - # }] - # return (sram_data,port_data) def analytical_power(self, slews, loads): """Get the dynamic and leakage power from the SRAM""" diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 23d82998..3ab04561 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -103,13 +103,17 @@ class control_logic(design.design): delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size() bitcell_loads = int(math.ceil(self.num_rows / 2.0)) - self.replica_bitline = replica_bitline(delay_stages_heuristic, delay_fanout_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type) + self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type) if self.sram != None and not self.is_sen_timing_okay(): - #Resize the delay chain (by instantiating a new rbl) if the analytical timing failed. + #This resizes to match fall and rise delays, can make the delay chain weird sizes. + #stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) + #self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + + #This resizes based on total delay. delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) - self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_resized_"+self.port_type) - self.sen_delay = self.get_delay_to_sen() #get the new timing + self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing self.add_mod(self.replica_bitline) @@ -124,16 +128,20 @@ class control_logic(design.design): delay_stages = 6 else: delay_stages = 4 + return (delay_stages, delay_fanout) def is_sen_timing_okay(self): - self.wl_delay = self.get_delay_to_wl() - self.sen_delay = self.get_delay_to_sen() + self.wl_delay_rise,self.wl_delay_fall = self.get_delays_to_wl() + self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() + self.wl_delay = self.wl_delay_rise+self.wl_delay_fall + self.sen_delay = self.sen_delay_rise+self.sen_delay_fall #The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before #a re-size is warranted. - if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay: + if (self.wl_delay_rise*self.wl_timing_tolerance >= self.sen_delay_rise or + self.wl_delay_fall*self.wl_timing_tolerance >= self.sen_delay_fall): return False else: return True @@ -155,7 +163,59 @@ class control_logic(design.design): #Fanout can be varied as well but is a little more complicated but potentially optimal. debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay)) return (delay_stages, delay_fanout) + + def get_dynamic_delay_fanout_list(self, previous_stages, previous_fanout): + """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" + previous_delay_chain_delay = (previous_fanout+1+self.parasitic_inv_delay)*previous_stages + debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay)) + + fanout_rise = fanout_fall = 2 # This can be anything >=2 + #The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each + #inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value + required_delay_fall = self.wl_delay_fall*self.wl_timing_tolerance - (self.sen_delay_fall-previous_delay_chain_delay/2) + required_delay_rise = self.wl_delay_rise*self.wl_timing_tolerance - (self.sen_delay_rise-previous_delay_chain_delay/2) + debug.info(2,"Required delays from chain: fall={}, rise={}".format(required_delay_fall,required_delay_rise)) + + #The stages need to be equal (or at least a even number of stages with matching rise/fall delays) + while True: + stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall,fanout_fall) + stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise,fanout_rise) + debug.info(1,"Fall stages={}, rise stages={}".format(stages_fall,stages_rise)) + if stages_fall == stages_rise: + break + elif abs(stages_fall-stages_rise) == 1: + break + #There should also be a condition to make sure the fanout does not get too large. + #Otherwise, increase the fanout of delay with the most stages, calculate new stages + elif stages_fall>stages_rise: + fanout_fall+=1 + else: + fanout_rise+=1 + + total_stages = max(stages_fall,stages_rise)*2 + debug.info(1, "New Delay chain: stages={}, fanout_rise={}, fanout_fall={}".format(total_stages, fanout_rise, fanout_fall)) + + #Creates interleaved fanout list of rise/fall delays. Assumes fall is the first stage. + stage_list = [fanout_fall if i%2==0 else fanout_rise for i in range(total_stages)] + return stage_list + + def calculate_stages_with_fixed_fanout(self, required_delay, fanout): + from math import ceil + #Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay + if required_delay<=3: #3 is the minimum delay per stage. + return 1 + delay_stages = ceil(required_delay/(fanout+1+self.parasitic_inv_delay)) + return delay_stages + + def calculate_stage_list(self, total_stages, fanout_rise, fanout_fall): + """Produces a list of fanouts which determine the size of the delay chain. List length is the number of stages. + Assumes the first stage is falling. + """ + stage_list = [] + for i in range(total_stages): + if i%2 == 0: + stage_list.append() def setup_signal_busses(self): """ Setup bus names, determine the size of the busses etc """ @@ -641,14 +701,14 @@ class control_logic(design.design): width=pin.width()) - def get_delay_to_wl(self): + def get_delays_to_wl(self): """Get the delay (in delay units) of the clk to a wordline in the bitcell array""" debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.") stage_efforts = self.determine_wordline_stage_efforts() clk_to_wl_rise,clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(stage_efforts, self.parasitic_inv_delay) total_delay = clk_to_wl_rise + clk_to_wl_fall debug.info(1, "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, clk_to_wl_fall,total_delay)) - return total_delay + return clk_to_wl_rise,clk_to_wl_fall def determine_wordline_stage_efforts(self): @@ -670,7 +730,7 @@ class control_logic(design.design): return stage_effort_list - def get_delay_to_sen(self): + def get_delays_to_sen(self): """Get the delay (in delay units) of the clk to a sense amp enable. This does not incorporate the delay of the replica bitline. """ @@ -679,7 +739,7 @@ class control_logic(design.design): clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(stage_efforts, self.parasitic_inv_delay) total_delay = clk_to_sen_rise + clk_to_sen_fall debug.info(1, "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, clk_to_sen_fall,total_delay)) - return total_delay + return clk_to_sen_rise, clk_to_sen_fall def determine_sa_enable_stage_efforts(self): """Follows the clock signal to the sense amp enable signal adding each stages stage effort to a list""" diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index 65320666..e6be9b3e 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -15,12 +15,11 @@ class replica_bitline(design.design): line and rows is the height of the replica bit loads. """ - def __init__(self, delay_stages, delay_fanout, bitcell_loads, name="replica_bitline"): + def __init__(self, delay_fanout_list, bitcell_loads, name="replica_bitline"): design.design.__init__(self, name) self.bitcell_loads = bitcell_loads - self.delay_stages = delay_stages - self.delay_fanout = delay_fanout + self.delay_fanout_list = delay_fanout_list self.create_netlist() if not OPTS.netlist_only: @@ -95,7 +94,7 @@ class replica_bitline(design.design): # FIXME: The FO and depth of this should be tuned from delay_chain import delay_chain - self.delay_chain = delay_chain([self.delay_fanout]*self.delay_stages) + self.delay_chain = delay_chain(self.delay_fanout_list) self.add_mod(self.delay_chain) self.inv = pinv() From d3c47ac97693481f28d6ab02687a9b36dc54a6c0 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Sun, 18 Nov 2018 23:28:49 -0800 Subject: [PATCH 28/78] Made delay measurements less dependent on period. --- compiler/characterizer/delay.py | 21 ++++++++++++--------- compiler/modules/control_logic.py | 23 +++++++++++++++++------ 2 files changed, 29 insertions(+), 15 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 3e103fc7..809e3974 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -208,14 +208,15 @@ class delay(simulation): trig_slew_low = 0.1 * self.vdd_voltage targ_slew_high = 0.9 * self.vdd_voltage if 'delay' in delay_name: - trig_dir="RISE" #FALL trig_val = half_vdd targ_val = half_vdd trig_name = trig_clk_name if 'lh' in delay_name: + trig_dir="RISE" targ_dir="RISE" trig_td = targ_td = self.cycle_times[self.measure_cycles[port]["read1"]] else: + trig_dir="FALL" targ_dir="FALL" trig_td = targ_td = self.cycle_times[self.measure_cycles[port]["read0"]] @@ -426,11 +427,10 @@ class delay(simulation): #Too much duplicate code here. Try reducing for port in self.targ_read_ports: debug.info(2, "Check delay values for port {}".format(port)) - delay_names = ["{0}{1}".format(mname,port) for mname in self.delay_meas_names] delay_names = [mname for mname in self.delay_meas_names] delays = self.parse_values(delay_names, port, 1e9) # scale delays to ns debug.info(2,"Delay values = {}".format(delays)) - if not self.check_valid_delays(tuple(delays.values())): + if not self.check_valid_delays(delays): return (False,{}) result[port].update(delays) @@ -479,10 +479,13 @@ class delay(simulation): #key=raw_input("press return to continue") return (leakage_power*1e3, trim_leakage_power*1e3) - def check_valid_delays(self, delay_tuple): + def check_valid_delays(self, delay_dict): """ Check if the measurements are defined and if they are valid. """ - - (delay_hl, delay_lh, slew_hl, slew_lh) = delay_tuple + #Hard coded names currently + delay_hl = delay_dict["delay_hl"] + delay_lh = delay_dict["delay_lh"] + slew_hl = delay_dict["slew_hl"] + slew_lh = delay_dict["slew_lh"] period_load_slew_str = "period {0} load {1} slew {2}".format(self.period,self.load, self.slew) # if it failed or the read was longer than a period @@ -496,7 +499,8 @@ class delay(simulation): delays_str = "delay_hl={0} delay_lh={1}".format(delay_hl, delay_lh) slews_str = "slew_hl={0} slew_lh={1}".format(slew_hl,slew_lh) - if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period: + half_period = self.period/2 #high-to-low delays start at neg. clk edge, so they need to be less than half_period + if delay_hl>half_period or delay_lh>self.period or slew_hl>half_period or slew_lh>self.period: debug.info(2,"UNsuccessful simulation (in ns):\n\t\t{0}\n\t\t{1}\n\t\t{2}".format(period_load_slew_str, delays_str, slews_str)) @@ -580,8 +584,7 @@ class delay(simulation): #Check the values of target readwrite and read ports. Write ports do not produce delays in this current version for port in self.targ_read_ports: - delay_port_names = [mname for mname in self.delay_meas_names if "delay" in mname] - for dname in delay_port_names: + for dname in self.delay_meas_names: #check that the delays and slews do not degrade with tested period. if not relative_compare(results[port][dname],feasible_delays[port][dname],error_tolerance=0.05): debug.info(2,"Delay too big {0} vs {1}".format(results[port][dname],feasible_delays[port][dname])) return False diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 3ab04561..f9c2b800 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -104,8 +104,9 @@ class control_logic(design.design): delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size() bitcell_loads = int(math.ceil(self.num_rows / 2.0)) self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type) + self.set_sen_wl_delays() - if self.sram != None and not self.is_sen_timing_okay(): + if self.sram != None and not self.does_sen_total_timing_match(): #This resizes to match fall and rise delays, can make the delay chain weird sizes. #stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) #self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) @@ -131,21 +132,31 @@ class control_logic(design.design): return (delay_stages, delay_fanout) - def is_sen_timing_okay(self): + def set_sen_wl_delays(self): + """Set delays for wordline and sense amp enable""" self.wl_delay_rise,self.wl_delay_fall = self.get_delays_to_wl() self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() - self.wl_delay = self.wl_delay_rise+self.wl_delay_fall self.sen_delay = self.sen_delay_rise+self.sen_delay_fall - #The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before - #a re-size is warranted. + def does_sen_rise_fall_timing_match(self): + """Compare the relative rise/fall delays of the sense amp enable and wordline""" + #This is not necessarily more reliable than total delay in some cases. if (self.wl_delay_rise*self.wl_timing_tolerance >= self.sen_delay_rise or self.wl_delay_fall*self.wl_timing_tolerance >= self.sen_delay_fall): return False else: return True - + + def does_sen_total_timing_match(self): + """Compare the total delays of the sense amp enable and wordline""" + #The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before + #a re-size is warranted. + if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay: + return False + else: + return True + def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout): """Determine the size of the delay chain used for the Sense Amp Enable using path delays""" from math import ceil From a55d907d03ff9ff0f56319f9eb78eb81ed34490e Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 19 Nov 2018 15:40:26 -0800 Subject: [PATCH 29/78] High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME --- compiler/characterizer/delay.py | 10 ++++++++++ compiler/modules/control_logic.py | 15 ++++++++------- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 809e3974..1f0b37fb 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -669,8 +669,18 @@ class delay(simulation): self.period = min_period char_port_data = self.simulate_loads_and_slews(slews, loads, leakage_offset) + #FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate. + self.alter_lh_char_data(char_port_data) + return (char_sram_data, char_port_data) + def alter_lh_char_data(self, char_port_data): + """Copies high-to-low data to low-to-high data to make them consistent on the same clock edge.""" + #This is basically a hack solution which should be removed/fixed later. + for port in self.all_ports: + char_port_data[port]['delay_lh'] = char_port_data[port]['delay_hl'] + char_port_data[port]['slew_lh'] = char_port_data[port]['slew_hl'] + def simulate_loads_and_slews(self, slews, loads, leakage_offset): """Simulate all specified output loads and input slews pairs of all ports""" measure_data = self.get_empty_measure_data_dict() diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index f9c2b800..fab78f72 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -33,7 +33,7 @@ class control_logic(design.design): self.sram=sram #self.sram=None #disable re-sizing for debugging self.wl_timing_tolerance = 1 #Determines how much larger the sen delay should be. Accounts for possible error in model. - self.parasitic_inv_delay = 0 #Keeping 0 for now until further testing. + self.parasitic_inv_delay = parameter["min_inv_para_delay"] #Keeping 0 for now until further testing. if self.port_type == "rw": self.num_control_signals = 2 @@ -106,14 +106,15 @@ class control_logic(design.design): self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type) self.set_sen_wl_delays() - if self.sram != None and not self.does_sen_total_timing_match(): + if self.sram != None and not self.does_sen_rise_fall_timing_match(): #This resizes to match fall and rise delays, can make the delay chain weird sizes. - #stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) - #self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) + self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) #This resizes based on total delay. - delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) - self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + # delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) + # self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing self.add_mod(self.replica_bitline) @@ -214,7 +215,7 @@ class control_logic(design.design): def calculate_stages_with_fixed_fanout(self, required_delay, fanout): from math import ceil #Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay - if required_delay<=3: #3 is the minimum delay per stage. + if required_delay <= 3+self.parasitic_inv_delay: #3 is the minimum delay per stage (with pinv=0). return 1 delay_stages = ceil(required_delay/(fanout+1+self.parasitic_inv_delay)) return delay_stages From 8257e4fe8cc3ea1a65ddf3a38003907891ffb93a Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 19 Nov 2018 16:51:43 -0800 Subject: [PATCH 30/78] Changed syntax in replica_bl tests, golden data to fit new values in delay tests. --- compiler/characterizer/delay.py | 1 - .../14_replica_bitline_multiport_test.py | 6 +-- compiler/tests/14_replica_bitline_test.py | 4 +- compiler/tests/21_hspice_delay_test.py | 40 +++++++++---------- compiler/tests/21_ngspice_delay_test.py | 40 +++++++++---------- 5 files changed, 45 insertions(+), 46 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 1f0b37fb..f7fcfbd4 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -429,7 +429,6 @@ class delay(simulation): debug.info(2, "Check delay values for port {}".format(port)) delay_names = [mname for mname in self.delay_meas_names] delays = self.parse_values(delay_names, port, 1e9) # scale delays to ns - debug.info(2,"Delay values = {}".format(delays)) if not self.check_valid_delays(delays): return (False,{}) result[port].update(delays) diff --git a/compiler/tests/14_replica_bitline_multiport_test.py b/compiler/tests/14_replica_bitline_multiport_test.py index 55e3e8f0..41c3aa51 100755 --- a/compiler/tests/14_replica_bitline_multiport_test.py +++ b/compiler/tests/14_replica_bitline_multiport_test.py @@ -28,7 +28,7 @@ class replica_bitline_multiport_test(openram_test): OPTS.num_w_ports = 0 debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) # check replica bitline in pbitcell multi-port @@ -39,7 +39,7 @@ class replica_bitline_multiport_test(openram_test): OPTS.num_r_ports = 0 debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) OPTS.num_rw_ports = 1 @@ -47,7 +47,7 @@ class replica_bitline_multiport_test(openram_test): OPTS.num_r_ports = 1 debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index 9efd3eec..94a49f55 100755 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -22,14 +22,14 @@ class replica_bitline_test(openram_test): fanout=4 rows=13 debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) #debug.error("Exiting...", 1) stages=8 rows=100 debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(stages,fanout,rows) + a = replica_bitline.replica_bitline(stages*[fanout],rows) self.local_check(a) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 5facb482..033cfbb6 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,27 +51,27 @@ class timing_sram_test(openram_test): #Assumes single rw port (6t sram) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.5829000000000004], - 'delay_lh': [0.2255964], - 'leakage_power': 0.0019498999999999996, - 'min_period': 4.844, - 'read0_power': [0.055371399999999994], - 'read1_power': [0.0520225], - 'slew_hl': [0.0794261], - 'slew_lh': [0.0236264], - 'write0_power': [0.06545659999999999], - 'write1_power': [0.057846299999999996]} + golden_data = {'delay_hl': [0.15801], + 'delay_lh': [0.15801], + 'leakage_power': 0.0023949, + 'min_period': 0.41, + 'read0_power': [0.628], + 'read1_power': [0.60328], + 'slew_hl': [0.092516], + 'slew_lh': [0.092516], + 'write0_power': [0.7510600000000001], + 'write1_power': [0.66619]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.452], - 'delay_lh': [1.3792000000000002], - 'leakage_power': 0.0257065, - 'min_period': 4.688, - 'read0_power': [15.0755], - 'read1_power': [14.4526], - 'slew_hl': [0.6137363], - 'slew_lh': [0.3381045], - 'write0_power': [16.9203], - 'write1_power': [15.367]} + golden_data = {'delay_hl': [1.2], + 'delay_lh': [1.2], + 'leakage_power': 0.026912, + 'min_period': 2.891, + 'read0_power': [24.7996], + 'read1_power': [23.9464], + 'slew_hl': [0.7045815], + 'slew_lh': [0.7045815], + 'write0_power': [27.8985], + 'write1_power': [25.1812]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index e203b878..b0275c1c 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,27 +50,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.584251], - 'delay_lh': [0.22870469999999998], - 'leakage_power': 0.0009567935, - 'min_period': 4.844, - 'read0_power': [0.0547588], - 'read1_power': [0.051159970000000006], - 'slew_hl': [0.08164099999999999], - 'slew_lh': [0.025474979999999998], - 'write0_power': [0.06513271999999999], - 'write1_power': [0.058057000000000004]} + golden_data = {'delay_hl': [0.16119519999999998], + 'delay_lh': [0.16119519999999998], + 'leakage_power': 0.01728358, + 'min_period': 0.469, + 'read0_power': [0.5486122], + 'read1_power': [0.5276639000000001], + 'slew_hl': [0.09102138], + 'slew_lh': [0.09102138], + 'write0_power': [0.6586793], + 'write1_power': [0.5893689999999999]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.644147], - 'delay_lh': [1.629815], - 'leakage_power': 0.001542964, - 'min_period': 4.688, - 'read0_power': [16.28732], - 'read1_power': [15.75155], - 'slew_hl': [0.6722473], - 'slew_lh': [0.3386347], - 'write0_power': [18.545450000000002], - 'write1_power': [16.81084]} + golden_data = {'delay_hl': [1.342843], + 'delay_lh': [1.342843], + 'leakage_power': 0.001683033, + 'min_period': 3.906, + 'read0_power': [19.55096], + 'read1_power': [18.99015], + 'slew_hl': [0.7687596], + 'slew_lh': [0.7687596], + 'write0_power': [22.285880000000002], + 'write1_power': [19.97167]} else: self.assertTrue(False) # other techs fail From 2f29ad55108bf6adcec11b3c085034e1bbd4e855 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 19 Nov 2018 22:13:58 -0800 Subject: [PATCH 31/78] Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed. --- compiler/modules/control_logic.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index fab78f72..5f751be8 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -104,16 +104,15 @@ class control_logic(design.design): delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size() bitcell_loads = int(math.ceil(self.num_rows / 2.0)) self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type) - self.set_sen_wl_delays() - if self.sram != None and not self.does_sen_rise_fall_timing_match(): + if self.sram != None and not self.does_sen_total_timing_match(): #check condition based on resizing method #This resizes to match fall and rise delays, can make the delay chain weird sizes. - stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) - self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + # stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) + # self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) #This resizes based on total delay. - # delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) - # self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) + self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type) self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing @@ -142,6 +141,7 @@ class control_logic(design.design): def does_sen_rise_fall_timing_match(self): """Compare the relative rise/fall delays of the sense amp enable and wordline""" + self.set_sen_wl_delays() #This is not necessarily more reliable than total delay in some cases. if (self.wl_delay_rise*self.wl_timing_tolerance >= self.sen_delay_rise or self.wl_delay_fall*self.wl_timing_tolerance >= self.sen_delay_fall): @@ -151,6 +151,7 @@ class control_logic(design.design): def does_sen_total_timing_match(self): """Compare the total delays of the sense amp enable and wordline""" + self.set_sen_wl_delays() #The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before #a re-size is warranted. if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay: From 67977bab3e02fb9e07b3a079607553cf1e7b1b8b Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 20 Nov 2018 11:39:14 -0800 Subject: [PATCH 32/78] Fixed port issue in bank. Changed golden data due to netlist change. --- compiler/modules/bank.py | 4 ++-- compiler/tests/21_ngspice_delay_test.py | 20 ++++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 41eb6483..0444d0f4 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1281,8 +1281,8 @@ class bank(design.design): """Get the relative capacitance of all the clk_bar connections in the bank""" #Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array. - #Assume single port - port = 0 + #Precharges are the all the same in Mulitport, one is picked + port = self.read_ports[0] total_clk_bar_cin = self.precharge_array[port].get_en_cin() return total_clk_bar_cin diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index b0275c1c..96b1c887 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,16 +50,16 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.16119519999999998], - 'delay_lh': [0.16119519999999998], - 'leakage_power': 0.01728358, - 'min_period': 0.469, - 'read0_power': [0.5486122], - 'read1_power': [0.5276639000000001], - 'slew_hl': [0.09102138], - 'slew_lh': [0.09102138], - 'write0_power': [0.6586793], - 'write1_power': [0.5893689999999999]} + golden_data = {'delay_hl': [0.1587689], + 'delay_lh': [0.1587689], + 'leakage_power': 0.02824871, + 'min_period': 0.43, + 'read0_power': [0.5932789], + 'read1_power': [0.5733669], + 'slew_hl': [0.09096027999999999], + 'slew_lh': [0.09096027999999999], + 'write0_power': [0.7133274], + 'write1_power': [0.6390777]} elif OPTS.tech_name == "scn4m_subm": golden_data = {'delay_hl': [1.342843], 'delay_lh': [1.342843], From 7d070c2652dc30a636479644bc75437218bc9574 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 20 Nov 2018 11:50:55 -0800 Subject: [PATCH 33/78] Added links to logos --- compiler/datasheet/datasheet.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 97635c96..e988abad 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -48,7 +48,7 @@ class datasheet(): self.html += row self.html +='-->' - self.html += 'VLSIDAOpenRAM' + self.html += 'VLSIDAOpenRAM' From 9ef5190d2e44356aea0d4e5a2db87e8109e7822c Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 20 Nov 2018 11:53:27 -0800 Subject: [PATCH 34/78] removed webserver files --- flask/client/client.py | 28 ---------------------------- flask/client/testfile | 1 - flask/server/server.py | 15 --------------- flask/server/templates/upload.html | 11 ----------- 4 files changed, 55 deletions(-) delete mode 100644 flask/client/client.py delete mode 100644 flask/client/testfile delete mode 100644 flask/server/server.py delete mode 100644 flask/server/templates/upload.html diff --git a/flask/client/client.py b/flask/client/client.py deleted file mode 100644 index 9dcd65e6..00000000 --- a/flask/client/client.py +++ /dev/null @@ -1,28 +0,0 @@ -import requests -import os -import sys -# TODO -# copy directory structure -# relative links to not break dataseets? -# look into proper string and packet sanitization -# index gui + results graphs - -base_url = 'http://localhost:5000/' -upload_url = 'upload' - -def send_file(path): - upload_file = open(path,'rb') - data = {'file' : upload_file} - return requests.post(url = base_url + upload_url, files = data) - -def send_mkdir(path): - -def send_directory(path): - for root, directories, filenames in os.walk(path): - for filename in filenames: - upload_file = os.path.join(root,filename) - print(upload_file) - print(send_file(upload_file)) - -send_directory(sys.argv[1]) - diff --git a/flask/client/testfile b/flask/client/testfile deleted file mode 100644 index 9daeafb9..00000000 --- a/flask/client/testfile +++ /dev/null @@ -1 +0,0 @@ -test diff --git a/flask/server/server.py b/flask/server/server.py deleted file mode 100644 index 78c39128..00000000 --- a/flask/server/server.py +++ /dev/null @@ -1,15 +0,0 @@ -import os -from flask import Flask, render_template, request -from werkzeug import secure_filename -app = Flask(__name__) - -@app.route('/uploader', methods = ['GET', 'POST']) -def upload(): - if request.method == 'POST': - f = request.files['file'] - dirname = os.path.dirname(os.path.abspath(__file__)) - f.save(dirname + '/uploads/' + secure_filename(f.filename)) - return 'file uploaded successfully' - -if __name__ == '__main__': - app.run(debug = True) diff --git a/flask/server/templates/upload.html b/flask/server/templates/upload.html deleted file mode 100644 index 761844f6..00000000 --- a/flask/server/templates/upload.html +++ /dev/null @@ -1,11 +0,0 @@ - - - -
- - -
- - - From 29f19ad70f58ffd1c118d548bda63d7660c75ec5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 20 Nov 2018 12:27:54 -0800 Subject: [PATCH 35/78] replaced absolute links with relative links --- compiler/datasheet/datasheet_gen.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index b48c2510..efb3780c 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -470,11 +470,11 @@ def parse_characterizer_csv(sram,f,pages): new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'lef'))) - new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'sp'))) - new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'v'))) - new_sheet.dlv.append(deliverables_item('.html','This datasheet','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'html'))) - new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'lib')))) - new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'py'))) + new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{0}.{1}'.format(OPTS.output_name,'sp'))) + new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{0}.{1}'.format(OPTS.output_name,'v'))) + new_sheet.dlv.append(deliverables_item('.html','This datasheet','{0}.{1}'.format(OPTS.output_name,'html'))) + new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) + new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','{0}.{1}'.format(OPTS.output_name,'py'))) From 5f954689a5b0ea1f52fd79fbc37f7b524e7b87b2 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 23 Nov 2018 13:19:55 -0800 Subject: [PATCH 36/78] In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. --- compiler/characterizer/charutils.py | 2 +- compiler/characterizer/delay.py | 46 +++++++++++++++++++---------- compiler/sram.py | 1 + 3 files changed, 32 insertions(+), 17 deletions(-) diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py index bc4beb88..a2140e51 100644 --- a/compiler/characterizer/charutils.py +++ b/compiler/characterizer/charutils.py @@ -5,7 +5,7 @@ from globals import OPTS def relative_compare(value1,value2,error_tolerance=0.001): """ This is used to compare relative values for convergence. """ - return (abs(value1 - value2) / max(value1,value2) <= error_tolerance) + return (abs(value1 - value2) / abs(max(value1,value2)) <= error_tolerance) def parse_spice_list(filename, key): diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index f7fcfbd4..3f000374 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -499,7 +499,7 @@ class delay(simulation): delays_str = "delay_hl={0} delay_lh={1}".format(delay_hl, delay_lh) slews_str = "slew_hl={0} slew_lh={1}".format(slew_hl,slew_lh) half_period = self.period/2 #high-to-low delays start at neg. clk edge, so they need to be less than half_period - if delay_hl>half_period or delay_lh>self.period or slew_hl>half_period or slew_lh>self.period: + if abs(delay_hl)>half_period or abs(delay_lh)>self.period or abs(slew_hl)>half_period or abs(slew_lh)>self.period: debug.info(2,"UNsuccessful simulation (in ns):\n\t\t{0}\n\t\t{1}\n\t\t{2}".format(period_load_slew_str, delays_str, slews_str)) @@ -584,6 +584,13 @@ class delay(simulation): #Check the values of target readwrite and read ports. Write ports do not produce delays in this current version for port in self.targ_read_ports: for dname in self.delay_meas_names: #check that the delays and slews do not degrade with tested period. + + #FIXME: This is a hack solution to fix the min period search. The slew will always be based on the period when there + #is a column mux. Therefore, the checks are skipped for this condition. This is hard to solve without changing the netlist. + #Delays/slews based on the period will cause the min_period search to come to the wrong period. + if self.sram.col_addr_size>0 and "slew" in dname: + continue + if not relative_compare(results[port][dname],feasible_delays[port][dname],error_tolerance=0.05): debug.info(2,"Delay too big {0} vs {1}".format(results[port][dname],feasible_delays[port][dname])) return False @@ -703,20 +710,27 @@ class delay(simulation): measure_data[port][mname].append(value) return measure_data - - def gen_test_cycles_one_port(self, read_port, write_port): - """Intended but not implemented: Returns a list of key time-points [ns] of the waveform (each rising edge) - of the cycles to do a timing evaluation of a single port. Current: Values overwritten for multiple calls""" - - # Create the inverse address for a scratch address + def calculate_inverse_address(self): + """Determine dummy test address based on probe address and column mux size.""" + #The inverse address needs to share the same bitlines as the probe address as the trimming will remove all other bitlines + #This is only an issue when there is a column mux and the address maps to different bitlines. + column_addr = self.probe_address[:self.sram.col_addr_size] #do not invert this part inverse_address = "" - for c in self.probe_address: + for c in self.probe_address[self.sram.col_addr_size:]: #invert everything else if c=="0": inverse_address += "1" elif c=="1": inverse_address += "0" else: debug.error("Non-binary address string",1) + return inverse_address+column_addr + + def gen_test_cycles_one_port(self, read_port, write_port): + """Sets a list of key time-points [ns] of the waveform (each rising edge) + of the cycles to do a timing evaluation of a single port """ + + # Create the inverse address for a scratch address + inverse_address = self.calculate_inverse_address() # For now, ignore data patterns and write ones or zeros data_ones = "1"*self.word_size @@ -726,36 +740,36 @@ class delay(simulation): self.add_noop_all_ports("Idle cycle (no positive clock edge)", inverse_address, data_zeros) - self.add_write("W data 1 address 0..00", + self.add_write("W data 1 address {}".format(inverse_address), inverse_address,data_ones,write_port) - self.add_write("W data 0 address 11..11 to write value", + self.add_write("W data 0 address {} to write value".format(self.probe_address), self.probe_address,data_zeros,write_port) self.measure_cycles[write_port]["write0"] = len(self.cycle_times)-1 # This also ensures we will have a H->L transition on the next read - self.add_read("R data 1 address 00..00 to set DOUT caps", + self.add_read("R data 1 address {} to set DOUT caps".format(inverse_address), inverse_address,data_zeros,read_port) - self.add_read("R data 0 address 11..11 to check W0 worked", + self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address), self.probe_address,data_zeros,read_port) self.measure_cycles[read_port]["read0"] = len(self.cycle_times)-1 self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)", inverse_address,data_zeros) - self.add_write("W data 1 address 11..11 to write value", + self.add_write("W data 1 address {} to write value".format(self.probe_address), self.probe_address,data_ones,write_port) self.measure_cycles[write_port]["write1"] = len(self.cycle_times)-1 - self.add_write("W data 0 address 00..00 to clear DIN caps", + self.add_write("W data 0 address {} to clear DIN caps".format(inverse_address), inverse_address,data_zeros,write_port) # This also ensures we will have a L->H transition on the next read - self.add_read("R data 0 address 00..00 to clear DOUT caps", + self.add_read("R data 0 address {} to clear DOUT caps".format(inverse_address), inverse_address,data_zeros,read_port) - self.add_read("R data 1 address 11..11 to check W1 worked", + self.add_read("R data 1 address {} to check W1 worked".format(self.probe_address), self.probe_address,data_zeros,read_port) self.measure_cycles[read_port]["read1"] = len(self.cycle_times)-1 diff --git a/compiler/sram.py b/compiler/sram.py index 1b6b104f..7ee09ecc 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -14,6 +14,7 @@ class sram(): """ def __init__(self, sram_config, name): + #sram_config.words_per_row = 1 #Disables column mux generation sram_config.compute_sizes() sram_config.set_local_config(self) From b06aa84824747296d0dfbf7fd59ba1489df6c6bf Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 23 Nov 2018 18:55:15 -0800 Subject: [PATCH 37/78] Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips. --- compiler/characterizer/functional.py | 29 ++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 0c60fc23..7e0816be 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -10,7 +10,7 @@ import utils from globals import OPTS from .simulation import simulation - +from .delay import delay class functional(simulation): """ @@ -27,6 +27,7 @@ class functional(simulation): self.set_corner(corner) self.set_spice_constants() + self.set_feasible_period(sram, spfile, corner) self.set_stimulus_variables() self.create_signal_names() @@ -36,13 +37,25 @@ class functional(simulation): self.write_check = [] self.read_check = [] - def set_spice_constants(self): - """Spice constants for functional test""" - simulation.set_spice_constants(self) - #Heuristic increase for functional period. Base feasible period typically does not pass the functional test - #for column mux or srams of this size. Increase the feasible period by 20% for this case. - if self.sram.words_per_row >= 4 or self.sram.num_cols*self.sram.num_rows >= 1024: - self.period = self.period*1.2 + def set_feasible_period(self, sram, spfile, corner): + """Creates a delay simulation to determine a feasible period for the functional tests to run. + Only determines the feasible period for a single port and assumes that for all ports for performance. + """ + OPTS.trim_netlist = False #This has to be false or the write port will flip a bit in the trimmed netlist. + debug.info(1, "Determining feasible period using untrimmed netlist for functional test.") + delay_sim = delay(sram, spfile, corner) + delay_sim.set_load_slew(self.load,self.slew) + delay_sim.set_probe(probe_address="1"*self.addr_size, probe_data=(self.sram.word_size-1)) + delay_sim.find_feasible_period_one_port(self.read_ports[0]) #Finds feasible and sets internal period + self.period = delay_sim.period #copy internal period of delay object here + + # def set_spice_constants(self): + # """Spice constants for functional test""" + # simulation.set_spice_constants(self) + # #Heuristic increase for functional period. Base feasible period typically does not pass the functional test + # #for column mux or srams of this size. Increase the feasible period by 20% for this case. + # if self.sram.words_per_row >= 4 or self.sram.num_cols*self.sram.num_rows >= 1024: + # self.period = self.period*1.2 def run(self): # Generate a random sequence of reads and writes From 0920321a2e661c02a7acfec3b55aca296555dfbd Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 27 Nov 2018 19:49:05 -0800 Subject: [PATCH 38/78] start of static html generation code --- compiler/datasheet/server_scripts/__init__.py | 29 + .../datasheet/server_scripts/datasheet_gen.py | 512 + .../datasheet/server_scripts/deliverable.py | 7 + compiler/datasheet/server_scripts/filelist.py | 18 + .../files/temp/sram_2_16_scn4m_subm.gds | Bin 0 -> 419780 bytes .../files/temp/sram_2_16_scn4m_subm.html | 116 + .../files/temp/sram_2_16_scn4m_subm.lef | 9314 +++++++++++++++++ .../files/temp/sram_2_16_scn4m_subm.py | 18 + .../files/temp/sram_2_16_scn4m_subm.sp | 767 ++ .../files/temp/sram_2_16_scn4m_subm.v | 47 + .../temp/sram_2_16_scn4m_subm_TT_3p3V_25C.lib | 321 + .../temp/sram_2_16_scn4m_subm_TT_5V_25C.lib | 321 + .../temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib | 625 ++ .../server_scripts/files/testfile.asdf | 0 .../server_scripts/templates/index.html | 5 + 15 files changed, 12100 insertions(+) create mode 100644 compiler/datasheet/server_scripts/__init__.py create mode 100644 compiler/datasheet/server_scripts/datasheet_gen.py create mode 100644 compiler/datasheet/server_scripts/deliverable.py create mode 100644 compiler/datasheet/server_scripts/filelist.py create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.gds create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.html create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.lef create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.py create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.sp create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.v create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_3p3V_25C.lib create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5V_25C.lib create mode 100644 compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib create mode 100644 compiler/datasheet/server_scripts/files/testfile.asdf create mode 100644 compiler/datasheet/server_scripts/templates/index.html diff --git a/compiler/datasheet/server_scripts/__init__.py b/compiler/datasheet/server_scripts/__init__.py new file mode 100644 index 00000000..f702e604 --- /dev/null +++ b/compiler/datasheet/server_scripts/__init__.py @@ -0,0 +1,29 @@ +import os +import jinja2 +from flask import Flask, render_template +from filelist import * + + +filedir = './files' +file_data = './filelist.info' + +def render_without_request(template_name, **template_vars): + env = jinja2.Environment( + loader = jinja2.PackageLoader('server_scripts','templates') + ) + template = env.get_template(template_name) + return template.render(**template_vars) + +app = Flask('server_scripts') + +if __name__ == '__main__': + + files = filelist() + + files.update_filelist(filedir,file_data) + + f = open('./output/index.html','w') + with app.app_context(): + f.write(render_template('index.html', files=files.list)) + + diff --git a/compiler/datasheet/server_scripts/datasheet_gen.py b/compiler/datasheet/server_scripts/datasheet_gen.py new file mode 100644 index 00000000..efb3780c --- /dev/null +++ b/compiler/datasheet/server_scripts/datasheet_gen.py @@ -0,0 +1,512 @@ +#!/usr/bin/env python3 +""" +This is a script to load data from the characterization and layout processes into +a web friendly html datasheet. This script requres the python-flask and flask-table +packages to be installed. +""" +#TODO: +#locate all port elements in .lib +#Locate all timing elements in .lib +#Diagram generation +#Improve css + +import debug +from globals import OPTS + +if OPTS.datasheet_gen: + import flask_table + import os, math + import optparse + import csv + from deliverables import * + from operating_conditions import * + from timing_and_current_data import * + from characterization_corners import * + from datasheet import * + from in_out import * +else: + debug.warning("Python library flask_table not found. Skipping html datasheet generation. This can be installed with pip install flask-table.") + #make sure appropriate python libraries are installed + + +def process_name(corner): + """ + Expands the names of the characterization corner types into something human friendly + """ + if corner == "TT": + return "Typical - Typical" + if corner == "SS": + return "Slow - Slow" + if corner == "FF": + return "Fast - Fast" + else: + return "custom" + +def parse_characterizer_csv(sram,f,pages): + """ + Parses output data of the Liberty file generator in order to construct the timing and + current table + """ + with open(f) as csv_file: + csv_reader = csv.reader(csv_file, delimiter=',') + line_count = 0 + for row in csv_reader: + + found = 0 + col = 0 + + #defines layout of csv file + NAME = row[col] + col += 1 + + NUM_WORDS = row[col] + col += 1 + + NUM_BANKS = row[col] + col += 1 + + NUM_RW_PORTS = row[col] + col += 1 + + NUM_W_PORTS = row[col] + col += 1 + + NUM_R_PORTS = row[col] + col += 1 + + TECH_NAME = row[col] + col += 1 + + TEMP = row[col] + col += 1 + + VOLT = row[col] + col += 1 + + PROC = row[col] + col += 1 + + MIN_PERIOD = row[col] + col += 1 + + OUT_DIR = row[col] + col += 1 + + LIB_NAME = row[col] + col += 1 + + WORD_SIZE = row[col] + col += 1 + + FF_SETUP_LH_MIN = "1" + FF_SETUP_LH_MAX = "2" + + FF_SETUP_HL_MIN = "3" + FF_SETUP_HL_MAX = "4" + + FF_HOLD_LH_MIN = "5" + FF_HOLD_LH_MAX = "6" + + FF_HOLD_HL_MIN = "7" + FF_HOLD_HL_MAX = "8" + + + for sheet in pages: + + + if sheet.name == NAME: + + found = 1 + #if the .lib information is for an existing datasheet compare timing data + + for item in sheet.operating: + #check if the new corner dataa is worse than the previous worse corner data + + if item.parameter == 'Operating Temperature': + if float(TEMP) > float(item.max): + item.typ = item.max + item.max = TEMP + if float(TEMP) < float(item.min): + item.typ = item.min + item.min = TEMP + + if item.parameter == 'Power supply (VDD) range': + if float(VOLT) > float(item.max): + item.typ = item.max + item.max = VOLT + if float(VOLT) < float(item.min): + item.typ = item.min + item.min = VOLT + + if item.parameter == 'Operating Frequncy (F)': + try: + if float(math.floor(1000/float(MIN_PERIOD)) < float(item.max)): + item.max = str(math.floor(1000/float(MIN_PERIOD))) + except Exception: + #pass if MIN_PERIOD is zero (not supported by analyitcal model) + pass + + + + while(True): + if(row[col].startswith('DIN')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + elif(row[col].startswith('DOUT')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('cell rise'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('cell fall'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('rise transition'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('fall transition'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + elif(row[col].startswith('CSb')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + + elif(row[col].startswith('WEb')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + + + elif(row[col].startswith('ADDR')): + start = col + for item in sheet.timing: + if item.parameter.startswith(row[col]): + + if item.parameter.endswith('setup rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('setup falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold rising'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + elif item.parameter.endswith('hold falling'): + if float(row[col+1]) < float(item.min): + item.min = row[col+1] + if float(row[col+2]) > float(item.max): + item.max = row[col+2] + + col += 2 + + col += 1 + else: + break + + + #regardless of if there is already a corner for the current sram, append the new corner to the datasheet + new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,''))) + new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) + + if found == 0: + + #if this is the first corner for this sram, run first time configuration and set up tables + new_sheet = datasheet(NAME) + pages.append(new_sheet) + + new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,''))) + + new_sheet.operating.append(operating_conditions_item('Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts')) + new_sheet.operating.append(operating_conditions_item('Operating Temperature',TEMP,TEMP,TEMP,'Celsius')) + try: + new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)*','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz')) + except Exception: + new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)*','','',"unknown",'MHz')) #analytical model fails to provide MIN_PERIOD + + #place holder timing and current data + + new_sheet.timing.append(timing_and_current_data_item('Cycle time','2','3','4')) + new_sheet.timing.append(timing_and_current_data_item('Access time','2','3','4')) + + new_sheet.timing.append(timing_and_current_data_item('Positive clk setup','2','3','4')) + new_sheet.timing.append(timing_and_current_data_item('Positive clk hold','2','3','4')) + + while(True): + if(row[col].startswith('DIN')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('DOUT')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} cell rise'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} cell fall'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} rise transition'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} fall transition'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('CSb')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('WEb')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + + elif(row[col].startswith('ADDR')): + start = col + new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns')) + col += 2 + + col +=1 + else: + break + + + + new_sheet.timing.append(timing_and_current_data_item('AC current','2','3','4')) + new_sheet.timing.append(timing_and_current_data_item('Standby current','2','3','4')) + + if not OPTS.netlist_only: + #physical layout files should not be generated in netlist only mode + new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'gds'))) + new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'lef'))) + + + new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{0}.{1}'.format(OPTS.output_name,'sp'))) + new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{0}.{1}'.format(OPTS.output_name,'v'))) + new_sheet.dlv.append(deliverables_item('.html','This datasheet','{0}.{1}'.format(OPTS.output_name,'html'))) + new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) + new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','{0}.{1}'.format(OPTS.output_name,'py'))) + + + + #debug table for multiport information + new_sheet.io.append(in_out_item('WORD_SIZE',WORD_SIZE)) + new_sheet.io.append(in_out_item('NUM_WORDS',NUM_WORDS)) + new_sheet.io.append(in_out_item('NUM_BANKS',NUM_BANKS)) + new_sheet.io.append(in_out_item('NUM_RW_PORTS',NUM_RW_PORTS)) + new_sheet.io.append(in_out_item('NUM_R_PORTS',NUM_R_PORTS)) + new_sheet.io.append(in_out_item('NUM_W_PORTS',NUM_W_PORTS)) + new_sheet.io.append(in_out_item('Area',sram.width * sram.height)) + + + + + + +class datasheet_gen(): + def datasheet_write(sram,name): + + if OPTS.datasheet_gen: + in_dir = OPTS.openram_temp + + if not (os.path.isdir(in_dir)): + os.mkdir(in_dir) + + + datasheets = [] + parse_characterizer_csv(sram, in_dir + "/datasheet.info", datasheets) + + + for sheets in datasheets: + with open(name, 'w+') as f: + sheets.generate_html() + f.write(sheets.html) diff --git a/compiler/datasheet/server_scripts/deliverable.py b/compiler/datasheet/server_scripts/deliverable.py new file mode 100644 index 00000000..801415c9 --- /dev/null +++ b/compiler/datasheet/server_scripts/deliverable.py @@ -0,0 +1,7 @@ +class deliverable: + def __init__(self, name, file_type, path, size): + self.name = name + self.file_type = file_type + self.path = path + self.size = size + diff --git a/compiler/datasheet/server_scripts/filelist.py b/compiler/datasheet/server_scripts/filelist.py new file mode 100644 index 00000000..2196a419 --- /dev/null +++ b/compiler/datasheet/server_scripts/filelist.py @@ -0,0 +1,18 @@ +import os +from deliverable import * +class filelist: + + + def __init__(self): + self.list = [] + + def update_filelist(self,path,outdir): + out_file = open(outdir,'w') + for root, dirs, files in os.walk(path): + for file in files: + self.list.append(root + '/' + file) + out_file.write('{}/{}\n'.format(root,file)) + print('{}/{}'.format(root,file)) + + + diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.gds b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.gds new file mode 100644 index 0000000000000000000000000000000000000000..ff2e666ff325f1d07f91fee68c5bfd58be9e8389 GIT binary patch literal 419780 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ze@8avzthLMvO05xzj2|zGiQ!(j=x-IZfwp^Jf<|N1i+a>rQrvre|K`eY+3dH E00W(EO#lD@ literal 0 HcmV?d00001 diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.html b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.html new file mode 100644 index 00000000..1fd87db0 --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.html @@ -0,0 +1,116 @@ + + +VLSIDAOpenRAM

sram_2_16_scn4m_subm.html

DRC: skipped

LVS: skipped

Ports and Configuration (DEBUG)

+ + + + + + + + + + +
TypeDescription
WORD_SIZE2
NUM_WORDS16
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS1
NUM_W_PORTS1
Area0

Operating Conditions

+ + + + + + +
ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)*unknownMHz

Timing and Current Data

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ParameterMinMaxUnits
Cycle time234
Access time234
Positive clk setup234
Positive clk hold234
DIN0[1:0] setup rising0.0090.009ns
DIN0[1:0] setup falling0.0090.009ns
DIN0[1:0] hold rising0.0010.001ns
DIN0[1:0] hold falling0.0010.001ns
DIN1[1:0] setup rising0.0090.009ns
DIN1[1:0] setup falling0.0090.009ns
DIN1[1:0] hold rising0.0010.001ns
DIN1[1:0] hold falling0.0010.001ns
DOUT0[1:0] cell rise0.0790.079ns
DOUT0[1:0] cell fall0.0790.079ns
DOUT0[1:0] rise transition0.0010.001ns
DOUT0[1:0] fall transition0.0010.001ns
DOUT2[1:0] cell rise0.0790.079ns
DOUT2[1:0] cell fall0.0790.079ns
DOUT2[1:0] rise transition0.0010.001ns
DOUT2[1:0] fall transition0.0010.001ns
CSb0 setup rising0.0090.009ns
CSb0 setup falling0.0090.009ns
CSb0 hold rising0.0010.001ns
CSb0 hold falling0.0010.001ns
CSb1 setup rising0.0090.009ns
CSb1 setup falling0.0090.009ns
CSb1 hold rising0.0010.001ns
CSb1 hold falling0.0010.001ns
CSb2 setup rising0.0090.009ns
CSb2 setup falling0.0090.009ns
CSb2 hold rising0.0010.001ns
CSb2 hold falling0.0010.001ns
ADDR0[3:0] setup rising0.0090.009ns
ADDR0[3:0] setup falling0.0090.009ns
ADDR0[3:0] hold rising0.0010.001ns
ADDR0[3:0] hold falling0.0010.001ns
ADDR1[3:0] setup rising0.0090.009ns
ADDR1[3:0] setup falling0.0090.009ns
ADDR1[3:0] hold rising0.0010.001ns
ADDR1[3:0] hold falling0.0010.001ns
ADDR2[3:0] setup rising0.0090.009ns
ADDR2[3:0] setup falling0.0090.009ns
ADDR2[3:0] hold rising0.0010.001ns
ADDR2[3:0] hold falling0.0010.001ns
WEb0 setup rising0.0090.009ns
WEb0 setup falling0.0090.009ns
WEb0 hold rising0.0010.001ns
WEb0 hold falling0.0010.001ns
AC current234
Standby current234

Characterization Corners

+ + + + +
Corner NameProcessPower SupplyTemperatureLibrary Name Suffix
TTTypical - Typical5.025_TT_5p0V_25C.lib

Deliverables

+ + + + + + + + +
TypeDescriptionLink
.spSPICE netlistssram_2_16_scn4m_subm.sp
.vVerilog simulation modelssram_2_16_scn4m_subm.v
.htmlThis datasheetsram_2_16_scn4m_subm.html
.libSynthesis modelssram_2_16_scn4m_subm_TT_5p0V_25C.lib
.pyOpenRAM configuration filesram_2_16_scn4m_subm.py

*Feature only supported with characterizer

\ No newline at end of file diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.lef b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.lef new file mode 100644 index 00000000..562ace7d --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.lef @@ -0,0 +1,9314 @@ +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS +SITE MacroSite + CLASS Core ; + SIZE 231500.0 by 299900.00000000006 ; +END MacroSite +MACRO sram_2_16_scn4m_subm + CLASS BLOCK ; + SIZE 231500.0 BY 299900.00000000006 ; + SYMMETRY X Y R90 ; + SITE MacroSite ; + PIN DIN0[0] + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 186200.0 8600.000000000002 187000.0 9400.000000000002 ; + END + END DIN0[0] + PIN DIN0[1] + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 208000.0 8600.000000000002 208800.0 9400.000000000002 ; + END + END DIN0[1] + PIN ADDR0[0] + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 56800.0 220500.0 57599.99999999999 221300.0 ; + END + END ADDR0[0] + PIN ADDR0[1] + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 56800.0 242500.0 57599.99999999999 243300.0 ; + END + END ADDR0[1] + PIN ADDR0[2] + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 56800.0 260500.0 57599.99999999999 261300.0 ; + END + END ADDR0[2] + PIN ADDR0[3] + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 56800.0 282500.0 57599.99999999999 283300.0 ; + END + END ADDR0[3] + PIN csb0 + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 7599.9999999999945 28200.000000000004 8399.99999999999 29000.000000000004 ; + END + END csb0 + PIN web0 + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 7599.9999999999945 50200.0 8399.99999999999 51000.0 ; + END + END web0 + PIN clk0 + DIRECTION INPUT ; + PORT + LAYER metal2 ; + RECT 36900.0 19600.0 37499.99999999999 29100.0 ; + END + END clk0 + PIN DOUT0[0] + DIRECTION OUTPUT ; + PORT + LAYER metal2 ; + RECT 179200.0 68800.00000000001 180000.0 71800.00000000001 ; + END + END DOUT0[0] + PIN DOUT0[1] + DIRECTION OUTPUT ; + PORT + LAYER metal2 ; + RECT 186000.0 68800.00000000001 186800.0 71800.00000000001 ; + END + END DOUT0[1] + PIN vdd + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal3 ; + RECT 181700.00000000003 131300.0 182300.0 131900.0 ; + LAYER metal3 ; + RECT 188500.0 131300.0 189100.00000000003 131900.0 ; + LAYER metal3 ; + RECT 181700.00000000003 149700.00000000003 182300.0 150300.0 ; + LAYER metal3 ; + RECT 188500.0 149700.00000000003 189100.00000000003 150300.0 ; + LAYER metal3 ; + RECT 181700.00000000003 168100.00000000003 182300.0 168700.00000000003 ; + LAYER metal3 ; + RECT 188500.0 168100.00000000003 189100.00000000003 168700.00000000003 ; + LAYER metal3 ; + RECT 181700.00000000003 186500.0 182300.0 187100.00000000003 ; + LAYER metal3 ; + RECT 188500.0 186500.0 189100.00000000003 187100.00000000003 ; + LAYER metal3 ; + RECT 181700.00000000003 204900.0 182300.0 205500.0 ; + LAYER metal3 ; + RECT 188500.0 204900.0 189100.00000000003 205500.0 ; + LAYER metal3 ; + RECT 181700.00000000003 223300.0 182300.0 223900.0 ; + LAYER metal3 ; + RECT 188500.0 223300.0 189100.00000000003 223900.0 ; + LAYER metal3 ; + RECT 181700.00000000003 241700.00000000003 182300.0 242300.0 ; + LAYER metal3 ; + RECT 188500.0 241700.00000000003 189100.00000000003 242300.0 ; + LAYER metal3 ; + RECT 181700.00000000003 260100.00000000003 182300.0 260700.0 ; + LAYER metal3 ; + RECT 188500.0 260100.00000000003 189100.00000000003 260700.0 ; + LAYER metal3 ; + RECT 181400.0 112000.0 182200.00000000003 112800.00000000001 ; + LAYER metal3 ; + RECT 188200.00000000003 112000.0 189000.0 112800.00000000001 ; + LAYER metal3 ; + RECT 184100.00000000003 81700.0 184700.00000000003 82300.00000000001 ; + LAYER metal3 ; + RECT 190900.0 81700.0 191500.0 82300.00000000001 ; + LAYER metal3 ; + RECT 182500.0 30500.0 183100.00000000003 31100.0 ; + LAYER metal3 ; + RECT 181900.0 47900.00000000001 182500.0 48500.0 ; + LAYER metal3 ; + RECT 189300.0 30500.0 189900.0 31100.0 ; + LAYER metal3 ; + RECT 188700.00000000003 47900.00000000001 189300.0 48500.0 ; + LAYER metal3 ; + RECT 130100.0 131600.0 130900.0 132400.0 ; + LAYER metal3 ; + RECT 130100.0 150000.0 130900.0 150800.0 ; + LAYER metal3 ; + RECT 130100.0 168400.0 130900.0 169200.00000000003 ; + LAYER metal3 ; + RECT 130100.0 186800.0 130900.0 187600.00000000003 ; + LAYER metal3 ; + RECT 130100.0 205200.00000000003 130900.0 206000.0 ; + LAYER metal3 ; + RECT 130100.0 223600.00000000003 130900.0 224400.0 ; + LAYER metal3 ; + RECT 130100.0 242000.0 130900.0 242800.0 ; + LAYER metal3 ; + RECT 130100.0 260400.00000000003 130900.0 261200.0 ; + LAYER metal3 ; + RECT 89700.0 131600.0 90500.0 132400.0 ; + LAYER metal3 ; + RECT 107700.0 131600.0 108500.0 132400.0 ; + LAYER metal3 ; + RECT 89700.0 150000.0 90500.0 150800.0 ; + LAYER metal3 ; + RECT 107700.0 150000.0 108500.0 150800.0 ; + LAYER metal3 ; + RECT 89700.0 168400.0 90500.0 169200.00000000003 ; + LAYER metal3 ; + RECT 107700.0 168400.0 108500.0 169200.00000000003 ; + LAYER metal3 ; + RECT 89700.0 186800.0 90500.0 187600.00000000003 ; + LAYER metal3 ; + RECT 107700.0 186800.0 108500.0 187600.00000000003 ; + LAYER metal3 ; + RECT 154400.0 131700.00000000003 155000.0 132300.0 ; + LAYER metal3 ; + RECT 164000.0 131700.00000000003 164600.00000000003 132300.0 ; + LAYER metal3 ; + RECT 154400.0 150100.0 155000.0 150700.00000000003 ; + LAYER metal3 ; + RECT 164000.0 150100.0 164600.00000000003 150700.00000000003 ; + LAYER metal3 ; + RECT 154400.0 168500.0 155000.0 169100.00000000003 ; + LAYER metal3 ; + RECT 164000.0 168500.0 164600.00000000003 169100.00000000003 ; + LAYER metal3 ; + RECT 154400.0 186900.0 155000.0 187500.0 ; + LAYER metal3 ; + RECT 164000.0 186900.0 164600.00000000003 187500.0 ; + LAYER metal3 ; + RECT 154400.0 205300.0 155000.0 205900.0 ; + LAYER metal3 ; + RECT 164000.0 205300.0 164600.00000000003 205900.0 ; + LAYER metal3 ; + RECT 154400.0 223700.00000000003 155000.0 224300.0 ; + LAYER metal3 ; + RECT 164000.0 223700.00000000003 164600.00000000003 224300.0 ; + LAYER metal3 ; + RECT 154400.0 242100.00000000003 155000.0 242700.00000000003 ; + LAYER metal3 ; + RECT 164000.0 242100.00000000003 164600.00000000003 242700.00000000003 ; + LAYER metal3 ; + RECT 154400.0 260500.0 155000.0 261100.00000000003 ; + LAYER metal3 ; + RECT 164000.0 260500.0 164600.00000000003 261100.00000000003 ; + LAYER metal3 ; + RECT 69200.0 39200.0 70000.0 40000.0 ; + LAYER metal3 ; + RECT 69200.0 79200.0 70000.0 80000.0 ; + LAYER metal3 ; + RECT 69200.0 119200.0 70000.0 120000.0 ; + LAYER metal3 ; + RECT 31500.0 142600.0 32100.0 143200.00000000003 ; + LAYER metal3 ; + RECT 31500.0 161000.0 32100.0 161600.00000000003 ; + LAYER metal3 ; + RECT 31500.0 179400.0 32100.0 180000.0 ; + LAYER metal3 ; + RECT 31500.0 197800.0 32100.0 198400.0 ; + LAYER metal3 ; + RECT 12400.0 142500.0 13200.000000000002 143300.0 ; + LAYER metal3 ; + RECT 18800.0 142500.0 19600.0 143300.0 ; + LAYER metal3 ; + RECT 12400.0 160900.0 13200.000000000002 161700.00000000003 ; + LAYER metal3 ; + RECT 18800.0 160900.0 19600.0 161700.00000000003 ; + LAYER metal3 ; + RECT 6000.0 124100.00000000001 6800.000000000001 124900.0 ; + LAYER metal3 ; + RECT 31400.000000000004 122700.0 32200.000000000004 123500.0 ; + LAYER metal3 ; + RECT 17200.0 129100.0 18000.0 129900.0 ; + LAYER metal3 ; + RECT -400.0 39200.0 400.0 40000.0 ; + LAYER metal3 ; + RECT 59700.0 231500.0 60500.0 232300.0 ; + LAYER metal3 ; + RECT 59700.0 271500.0 60500.0 272300.0 ; + LAYER metal3 ; + RECT 189100.00000000003 19600.0 189900.0 20400.000000000004 ; + LAYER metal3 ; + RECT 210900.0 19600.0 211700.00000000003 20400.000000000004 ; + LAYER metal3 ; + RECT 0.0 3900.0000000000005 168000.0 8100.0 ; + LAYER metal3 ; + RECT 0.0 13500.0 232800.0 17700.0 ; + LAYER metal3 ; + RECT 0.0 23100.0 232800.0 27300.0 ; + LAYER metal3 ; + RECT 0.0 32700.000000000004 177600.00000000003 36900.0 ; + LAYER metal3 ; + RECT 194400.0 32700.000000000004 232800.0 36900.0 ; + LAYER metal3 ; + RECT 0.0 42300.00000000001 177600.00000000003 46500.0 ; + LAYER metal3 ; + RECT 196800.0 42300.00000000001 232800.0 46500.0 ; + LAYER metal3 ; + RECT 0.0 51900.00000000001 177600.00000000003 56100.0 ; + LAYER metal3 ; + RECT 196800.0 51900.00000000001 232800.0 56100.0 ; + LAYER metal3 ; + RECT 0.0 61500.0 232800.0 65700.0 ; + LAYER metal3 ; + RECT 0.0 71100.00000000001 232800.0 75300.0 ; + LAYER metal3 ; + RECT 0.0 80700.0 232800.0 84900.0 ; + LAYER metal3 ; + RECT 52800.00000000001 90300.00000000001 180000.0 94500.0 ; + LAYER metal3 ; + RECT 196800.0 90300.00000000001 232800.0 94500.0 ; + LAYER metal3 ; + RECT 0.0 99900.0 64800.0 104100.00000000001 ; + LAYER metal3 ; + RECT 74400.0 99900.0 232800.0 104100.00000000001 ; + LAYER metal3 ; + RECT 0.0 109500.0 64800.0 113700.0 ; + LAYER metal3 ; + RECT 182400.0 109500.0 232800.0 113700.0 ; + LAYER metal3 ; + RECT 0.0 119100.00000000001 84000.0 123300.00000000001 ; + LAYER metal3 ; + RECT 170400.0 119100.00000000001 232800.0 123300.00000000001 ; + LAYER metal3 ; + RECT 40800.00000000001 128700.00000000001 69600.00000000001 132900.0 ; + LAYER metal3 ; + RECT 86400.0 128700.00000000001 105600.00000000001 132900.0 ; + LAYER metal3 ; + RECT 120000.0 128700.00000000001 232800.0 132900.0 ; + LAYER metal3 ; + RECT 40800.00000000001 138300.0 69600.00000000001 142500.0 ; + LAYER metal3 ; + RECT 170400.0 138300.0 232800.0 142500.0 ; + LAYER metal3 ; + RECT 43200.0 147900.0 105600.00000000001 152100.0 ; + LAYER metal3 ; + RECT 122400.0 147900.0 232800.0 152100.0 ; + LAYER metal3 ; + RECT 40800.00000000001 157500.0 84000.0 161700.00000000003 ; + LAYER metal3 ; + RECT 170400.0 157500.0 232800.0 161700.00000000003 ; + LAYER metal3 ; + RECT 43200.0 167100.00000000003 72000.0 171300.0 ; + LAYER metal3 ; + RECT 86400.0 167100.00000000003 105600.00000000001 171300.0 ; + LAYER metal3 ; + RECT 127200.0 167100.00000000003 232800.0 171300.0 ; + LAYER metal3 ; + RECT 0.0 176700.00000000003 72000.0 180900.0 ; + LAYER metal3 ; + RECT 170400.0 176700.00000000003 232800.0 180900.0 ; + LAYER metal3 ; + RECT 0.0 186300.0 31200.000000000004 190500.0 ; + LAYER metal3 ; + RECT 43200.0 186300.0 105600.00000000001 190500.0 ; + LAYER metal3 ; + RECT 129600.0 186300.0 172800.0 190500.0 ; + LAYER metal3 ; + RECT 196800.0 186300.0 232800.0 190500.0 ; + LAYER metal3 ; + RECT 0.0 195900.0 84000.0 200100.00000000003 ; + LAYER metal3 ; + RECT 196800.0 195900.0 232800.0 200100.00000000003 ; + LAYER metal3 ; + RECT 0.0 205500.0 31200.000000000004 209700.00000000003 ; + LAYER metal3 ; + RECT 43200.0 205500.0 172800.0 209700.00000000003 ; + LAYER metal3 ; + RECT 196800.0 205500.0 232800.0 209700.00000000003 ; + LAYER metal3 ; + RECT 0.0 215100.00000000003 43200.0 219300.0 ; + LAYER metal3 ; + RECT 76800.00000000001 215100.00000000003 124800.00000000001 219300.0 ; + LAYER metal3 ; + RECT 196800.0 215100.00000000003 232800.0 219300.0 ; + LAYER metal3 ; + RECT 0.0 224700.00000000003 172800.0 228900.0 ; + LAYER metal3 ; + RECT 196800.0 224700.00000000003 232800.0 228900.0 ; + LAYER metal3 ; + RECT 0.0 234300.0 172800.0 238500.0 ; + LAYER metal3 ; + RECT 196800.0 234300.0 232800.0 238500.0 ; + LAYER metal3 ; + RECT 0.0 243900.0 172800.0 248100.00000000003 ; + LAYER metal3 ; + RECT 196800.0 243900.0 232800.0 248100.00000000003 ; + LAYER metal3 ; + RECT 0.0 253500.0 172800.0 257700.0 ; + LAYER metal3 ; + RECT 196800.0 253500.0 232800.0 257700.0 ; + LAYER metal3 ; + RECT 0.0 263100.0 172800.0 267300.0 ; + LAYER metal3 ; + RECT 196800.0 263100.0 232800.0 267300.0 ; + LAYER metal3 ; + RECT 0.0 272700.0 232800.0 276900.00000000006 ; + LAYER metal3 ; + RECT 0.0 282300.0 62400.00000000001 286500.0 ; + LAYER metal3 ; + RECT 84000.0 282300.0 232800.0 286500.0 ; + LAYER metal3 ; + RECT 0.0 291900.00000000006 55200.0 296100.0 ; + LAYER metal3 ; + RECT 64800.0 291900.00000000006 232800.0 296100.0 ; + LAYER metal4 ; + RECT 4200.0 0.0 7800.000000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 13800.0 0.0 17400.000000000004 302400.00000000006 ; + LAYER metal4 ; + RECT 23400.000000000004 0.0 27000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 33000.0 0.0 36600.0 302400.00000000006 ; + LAYER metal4 ; + RECT 42600.0 0.0 46200.0 302400.00000000006 ; + LAYER metal4 ; + RECT 52200.0 0.0 55800.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 61800.00000000001 0.0 65400.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 71400.0 0.0 75000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 81000.0 0.0 84600.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 90600.00000000001 0.0 94200.0 302400.00000000006 ; + LAYER metal4 ; + RECT 100200.0 0.0 103800.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 109800.00000000001 0.0 113400.0 302400.00000000006 ; + LAYER metal4 ; + RECT 119400.0 0.0 123000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 129000.0 0.0 132600.0 302400.00000000006 ; + LAYER metal4 ; + RECT 138600.0 0.0 142200.00000000003 302400.00000000006 ; + LAYER metal4 ; + RECT 148200.00000000003 0.0 151800.0 302400.00000000006 ; + LAYER metal4 ; + RECT 157800.0 0.0 161400.0 302400.00000000006 ; + LAYER metal4 ; + RECT 167400.0 0.0 171000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 177000.0 0.0 180600.00000000003 302400.00000000006 ; + LAYER metal4 ; + RECT 186600.00000000003 0.0 190200.00000000003 302400.00000000006 ; + LAYER metal4 ; + RECT 196200.00000000003 0.0 199800.0 302400.00000000006 ; + LAYER metal4 ; + RECT 205800.0 0.0 209400.0 302400.00000000006 ; + LAYER metal4 ; + RECT 215400.0 0.0 219000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 225000.0 0.0 228600.00000000003 302400.00000000006 ; + END + END vdd + PIN gnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal3 ; + RECT 178300.0 126700.0 178900.0 127300.00000000001 ; + LAYER metal3 ; + RECT 185100.00000000003 126700.0 185700.00000000003 127300.00000000001 ; + LAYER metal3 ; + RECT 191900.0 126700.0 192500.0 127300.00000000001 ; + LAYER metal3 ; + RECT 178300.0 135900.0 178900.0 136500.0 ; + LAYER metal3 ; + RECT 185100.00000000003 135900.0 185700.00000000003 136500.0 ; + LAYER metal3 ; + RECT 191900.0 135900.0 192500.0 136500.0 ; + LAYER metal3 ; + RECT 178300.0 145100.0 178900.0 145700.00000000003 ; + LAYER metal3 ; + RECT 185100.00000000003 145100.0 185700.00000000003 145700.00000000003 ; + LAYER metal3 ; + RECT 191900.0 145100.0 192500.0 145700.00000000003 ; + LAYER metal3 ; + RECT 178300.0 154300.0 178900.0 154900.0 ; + LAYER metal3 ; + RECT 185100.00000000003 154300.0 185700.00000000003 154900.0 ; + LAYER metal3 ; + RECT 191900.0 154300.0 192500.0 154900.0 ; + LAYER metal3 ; + RECT 178300.0 163500.0 178900.0 164100.00000000003 ; + LAYER metal3 ; + RECT 185100.00000000003 163500.0 185700.00000000003 164100.00000000003 ; + LAYER metal3 ; + RECT 191900.0 163500.0 192500.0 164100.00000000003 ; + LAYER metal3 ; + RECT 178300.0 172700.00000000003 178900.0 173300.0 ; + LAYER metal3 ; + RECT 185100.00000000003 172700.00000000003 185700.00000000003 173300.0 ; + LAYER metal3 ; + RECT 191900.0 172700.00000000003 192500.0 173300.0 ; + LAYER metal3 ; + RECT 178300.0 181900.0 178900.0 182500.0 ; + LAYER metal3 ; + RECT 185100.00000000003 181900.0 185700.00000000003 182500.0 ; + LAYER metal3 ; + RECT 191900.0 181900.0 192500.0 182500.0 ; + LAYER metal3 ; + RECT 178300.0 191100.00000000003 178900.0 191700.00000000003 ; + LAYER metal3 ; + RECT 185100.00000000003 191100.00000000003 185700.00000000003 191700.00000000003 ; + LAYER metal3 ; + RECT 191900.0 191100.00000000003 192500.0 191700.00000000003 ; + LAYER metal3 ; + RECT 178300.0 200300.0 178900.0 200900.0 ; + LAYER metal3 ; + RECT 185100.00000000003 200300.0 185700.00000000003 200900.0 ; + LAYER metal3 ; + RECT 191900.0 200300.0 192500.0 200900.0 ; + LAYER metal3 ; + RECT 178300.0 209500.0 178900.0 210100.00000000003 ; + LAYER metal3 ; + RECT 185100.00000000003 209500.0 185700.00000000003 210100.00000000003 ; + LAYER metal3 ; + RECT 191900.0 209500.0 192500.0 210100.00000000003 ; + LAYER metal3 ; + RECT 178300.0 218700.00000000003 178900.0 219300.0 ; + LAYER metal3 ; + RECT 185100.00000000003 218700.00000000003 185700.00000000003 219300.0 ; + LAYER metal3 ; + RECT 191900.0 218700.00000000003 192500.0 219300.0 ; + LAYER metal3 ; + RECT 178300.0 227900.0 178900.0 228500.0 ; + LAYER metal3 ; + RECT 185100.00000000003 227900.0 185700.00000000003 228500.0 ; + LAYER metal3 ; + RECT 191900.0 227900.0 192500.0 228500.0 ; + LAYER metal3 ; + RECT 178300.0 237100.00000000003 178900.0 237700.00000000003 ; + LAYER metal3 ; + RECT 185100.00000000003 237100.00000000003 185700.00000000003 237700.00000000003 ; + LAYER metal3 ; + RECT 191900.0 237100.00000000003 192500.0 237700.00000000003 ; + LAYER metal3 ; + RECT 178300.0 246300.0 178900.0 246900.0 ; + LAYER metal3 ; + RECT 185100.00000000003 246300.0 185700.00000000003 246900.0 ; + LAYER metal3 ; + RECT 191900.0 246300.0 192500.0 246900.0 ; + LAYER metal3 ; + RECT 178300.0 255500.0 178900.0 256100.00000000003 ; + LAYER metal3 ; + RECT 185100.00000000003 255500.0 185700.00000000003 256100.00000000003 ; + LAYER metal3 ; + RECT 191900.0 255500.0 192500.0 256100.00000000003 ; + LAYER metal3 ; + RECT 178300.0 264700.0 178900.0 265300.0 ; + LAYER metal3 ; + RECT 185100.00000000003 264700.0 185700.00000000003 265300.0 ; + LAYER metal3 ; + RECT 191900.0 264700.0 192500.0 265300.0 ; + LAYER metal3 ; + RECT 185100.00000000003 95100.00000000001 185700.00000000003 95700.0 ; + LAYER metal3 ; + RECT 191900.0 95100.00000000001 192500.0 95700.0 ; + LAYER metal3 ; + RECT 182500.0 37100.0 183100.00000000003 37700.0 ; + LAYER metal3 ; + RECT 183900.0 41500.0 184500.0 42100.0 ; + LAYER metal3 ; + RECT 183300.0 54900.00000000001 183900.0 55500.0 ; + LAYER metal3 ; + RECT 189300.0 37100.0 189900.0 37700.0 ; + LAYER metal3 ; + RECT 190700.00000000003 41500.0 191300.0 42100.0 ; + LAYER metal3 ; + RECT 190100.00000000003 54900.00000000001 190700.00000000003 55500.0 ; + LAYER metal3 ; + RECT 130100.0 122400.0 130900.0 123200.0 ; + LAYER metal3 ; + RECT 130100.0 140800.0 130900.0 141600.0 ; + LAYER metal3 ; + RECT 130100.0 159200.00000000003 130900.0 160000.0 ; + LAYER metal3 ; + RECT 130100.0 177600.00000000003 130900.0 178400.0 ; + LAYER metal3 ; + RECT 130100.0 196000.0 130900.0 196800.0 ; + LAYER metal3 ; + RECT 130100.0 214400.0 130900.0 215200.00000000003 ; + LAYER metal3 ; + RECT 130100.0 232800.0 130900.0 233600.00000000003 ; + LAYER metal3 ; + RECT 130100.0 251200.00000000003 130900.0 252000.0 ; + LAYER metal3 ; + RECT 130100.0 269600.0 130900.0 270400.00000000006 ; + LAYER metal3 ; + RECT 89700.0 122400.0 90500.0 123200.0 ; + LAYER metal3 ; + RECT 107700.0 122400.0 108500.0 123200.0 ; + LAYER metal3 ; + RECT 89700.0 140800.0 90500.0 141600.0 ; + LAYER metal3 ; + RECT 107700.0 140800.0 108500.0 141600.0 ; + LAYER metal3 ; + RECT 89700.0 159200.00000000003 90500.0 160000.0 ; + LAYER metal3 ; + RECT 107700.0 159200.00000000003 108500.0 160000.0 ; + LAYER metal3 ; + RECT 89700.0 177600.00000000003 90500.0 178400.0 ; + LAYER metal3 ; + RECT 107700.0 177600.00000000003 108500.0 178400.0 ; + LAYER metal3 ; + RECT 89700.0 196000.0 90500.0 196800.0 ; + LAYER metal3 ; + RECT 107700.0 196000.0 108500.0 196800.0 ; + LAYER metal3 ; + RECT 154400.0 122500.0 155000.0 123100.00000000001 ; + LAYER metal3 ; + RECT 164000.0 122500.0 164600.00000000003 123100.00000000001 ; + LAYER metal3 ; + RECT 154400.0 140900.0 155000.0 141500.0 ; + LAYER metal3 ; + RECT 164000.0 140900.0 164600.00000000003 141500.0 ; + LAYER metal3 ; + RECT 154400.0 159300.0 155000.0 159900.0 ; + LAYER metal3 ; + RECT 164000.0 159300.0 164600.00000000003 159900.0 ; + LAYER metal3 ; + RECT 154400.0 177700.00000000003 155000.0 178300.0 ; + LAYER metal3 ; + RECT 164000.0 177700.00000000003 164600.00000000003 178300.0 ; + LAYER metal3 ; + RECT 154400.0 196100.00000000003 155000.0 196700.00000000003 ; + LAYER metal3 ; + RECT 164000.0 196100.00000000003 164600.00000000003 196700.00000000003 ; + LAYER metal3 ; + RECT 154400.0 214500.0 155000.0 215100.00000000003 ; + LAYER metal3 ; + RECT 164000.0 214500.0 164600.00000000003 215100.00000000003 ; + LAYER metal3 ; + RECT 154400.0 232900.0 155000.0 233500.0 ; + LAYER metal3 ; + RECT 164000.0 232900.0 164600.00000000003 233500.0 ; + LAYER metal3 ; + RECT 154400.0 251300.0 155000.0 251900.0 ; + LAYER metal3 ; + RECT 164000.0 251300.0 164600.00000000003 251900.0 ; + LAYER metal3 ; + RECT 154400.0 269700.0 155000.0 270300.0 ; + LAYER metal3 ; + RECT 164000.0 269700.0 164600.00000000003 270300.0 ; + LAYER metal3 ; + RECT 69200.0 59200.0 70000.0 60000.0 ; + LAYER metal3 ; + RECT 69200.0 19200.000000000004 70000.0 20000.0 ; + LAYER metal3 ; + RECT 69200.0 99200.0 70000.0 100000.0 ; + LAYER metal3 ; + RECT 28100.0 138000.0 28700.000000000004 138600.0 ; + LAYER metal3 ; + RECT 34900.0 138000.0 35500.0 138600.0 ; + LAYER metal3 ; + RECT 28100.0 147200.00000000003 28700.000000000004 147800.0 ; + LAYER metal3 ; + RECT 34900.0 147200.00000000003 35500.0 147800.0 ; + LAYER metal3 ; + RECT 28100.0 156400.0 28700.000000000004 157000.0 ; + LAYER metal3 ; + RECT 34900.0 156400.0 35500.0 157000.0 ; + LAYER metal3 ; + RECT 28100.0 165600.00000000003 28700.000000000004 166200.00000000003 ; + LAYER metal3 ; + RECT 34900.0 165600.00000000003 35500.0 166200.00000000003 ; + LAYER metal3 ; + RECT 28100.0 174800.0 28700.000000000004 175400.0 ; + LAYER metal3 ; + RECT 34900.0 174800.0 35500.0 175400.0 ; + LAYER metal3 ; + RECT 28100.0 184000.0 28700.000000000004 184600.00000000003 ; + LAYER metal3 ; + RECT 34900.0 184000.0 35500.0 184600.00000000003 ; + LAYER metal3 ; + RECT 28100.0 193200.00000000003 28700.000000000004 193800.0 ; + LAYER metal3 ; + RECT 34900.0 193200.00000000003 35500.0 193800.0 ; + LAYER metal3 ; + RECT 28100.0 202400.0 28700.000000000004 203000.0 ; + LAYER metal3 ; + RECT 34900.0 202400.0 35500.0 203000.0 ; + LAYER metal3 ; + RECT 12400.0 133300.0 13200.000000000002 134100.0 ; + LAYER metal3 ; + RECT 18800.0 133300.0 19600.0 134100.0 ; + LAYER metal3 ; + RECT 12400.0 151700.00000000003 13200.000000000002 152500.0 ; + LAYER metal3 ; + RECT 18800.0 151700.00000000003 19600.0 152500.0 ; + LAYER metal3 ; + RECT 12400.0 170100.00000000003 13200.000000000002 170900.0 ; + LAYER metal3 ; + RECT 18800.0 170100.00000000003 19600.0 170900.0 ; + LAYER metal3 ; + RECT 28000.0 128700.00000000001 28800.0 129500.0 ; + LAYER metal3 ; + RECT 34800.00000000001 128700.00000000001 35600.0 129500.0 ; + LAYER metal3 ; + RECT 36400.0 134700.00000000003 37200.0 135500.0 ; + LAYER metal3 ; + RECT 36400.0 150300.0 37200.0 151100.0 ; + LAYER metal3 ; + RECT 36400.0 153100.0 37200.0 153900.0 ; + LAYER metal3 ; + RECT 36400.0 168700.00000000003 37200.0 169500.0 ; + LAYER metal3 ; + RECT 36400.0 171500.0 37200.0 172300.0 ; + LAYER metal3 ; + RECT 36400.0 187100.00000000003 37200.0 187900.0 ; + LAYER metal3 ; + RECT 36400.0 189900.0 37200.0 190700.00000000003 ; + LAYER metal3 ; + RECT 36400.0 205500.0 37200.0 206300.0 ; + LAYER metal3 ; + RECT -400.0 19200.000000000004 400.0 20000.0 ; + LAYER metal3 ; + RECT -400.0 59200.0 400.0 60000.0 ; + LAYER metal3 ; + RECT 59700.0 211500.0 60500.0 212300.0 ; + LAYER metal3 ; + RECT 59700.0 251500.0 60500.0 252300.0 ; + LAYER metal3 ; + RECT 59700.0 291500.0 60500.0 292300.0 ; + LAYER metal3 ; + RECT 189100.00000000003 -400.0 189900.0 400.0 ; + LAYER metal3 ; + RECT 210900.0 -400.0 211700.00000000003 400.0 ; + LAYER metal3 ; + RECT 0.0 -900.0 168000.0 3300.0000000000005 ; + LAYER metal3 ; + RECT 0.0 8700.000000000002 232800.0 12900.0 ; + LAYER metal3 ; + RECT 0.0 18300.0 184800.0 22500.0 ; + LAYER metal3 ; + RECT 216000.0 18300.0 232800.0 22500.0 ; + LAYER metal3 ; + RECT 194400.0 27900.000000000004 232800.0 32100.0 ; + LAYER metal3 ; + RECT 4800.000000000001 37500.0 64800.0 41700.0 ; + LAYER metal3 ; + RECT 74400.0 37500.0 232800.0 41700.0 ; + LAYER metal3 ; + RECT 194400.0 47100.0 232800.0 51300.00000000001 ; + LAYER metal3 ; + RECT 0.0 56700.0 232800.0 60900.00000000001 ; + LAYER metal3 ; + RECT 0.0 66300.0 64800.0 70500.0 ; + LAYER metal3 ; + RECT 180000.0 66300.0 232800.0 70500.0 ; + LAYER metal3 ; + RECT 0.0 75900.0 64800.0 80100.00000000001 ; + LAYER metal3 ; + RECT 74400.0 75900.0 232800.0 80100.00000000001 ; + LAYER metal3 ; + RECT 52800.00000000001 85500.0 232800.0 89700.0 ; + LAYER metal3 ; + RECT 0.0 95100.00000000001 232800.0 99300.00000000001 ; + LAYER metal3 ; + RECT 0.0 104700.0 64800.0 108900.0 ; + LAYER metal3 ; + RECT 182400.0 104700.0 232800.0 108900.0 ; + LAYER metal3 ; + RECT 0.0 114300.00000000001 232800.0 118500.0 ; + LAYER metal3 ; + RECT 38400.00000000001 123900.0 232800.0 128100.0 ; + LAYER metal3 ; + RECT 26400.000000000004 133500.0 69600.00000000001 137700.00000000003 ; + LAYER metal3 ; + RECT 86400.0 133500.0 232800.0 137700.00000000003 ; + LAYER metal3 ; + RECT 38400.00000000001 143100.0 69600.00000000001 147300.0 ; + LAYER metal3 ; + RECT 88800.00000000001 143100.0 232800.0 147300.0 ; + LAYER metal3 ; + RECT 26400.000000000004 152700.00000000003 232800.0 156900.0 ; + LAYER metal3 ; + RECT 38400.00000000001 162300.0 232800.0 166500.0 ; + LAYER metal3 ; + RECT 0.0 171900.0 232800.0 176100.00000000003 ; + LAYER metal3 ; + RECT 0.0 181500.0 232800.0 185700.00000000003 ; + LAYER metal3 ; + RECT 0.0 191100.00000000003 232800.0 195300.0 ; + LAYER metal3 ; + RECT 0.0 200700.00000000003 124800.00000000001 204900.0 ; + LAYER metal3 ; + RECT 194400.0 200700.00000000003 232800.0 204900.0 ; + LAYER metal3 ; + RECT 0.0 210300.0 43200.0 214500.0 ; + LAYER metal3 ; + RECT 76800.00000000001 210300.0 232800.0 214500.0 ; + LAYER metal3 ; + RECT 0.0 219900.0 62400.00000000001 224100.00000000003 ; + LAYER metal3 ; + RECT 79200.0 219900.0 124800.00000000001 224100.00000000003 ; + LAYER metal3 ; + RECT 194400.0 219900.0 232800.0 224100.00000000003 ; + LAYER metal3 ; + RECT 0.0 229500.0 55200.0 233700.00000000003 ; + LAYER metal3 ; + RECT 64800.0 229500.0 232800.0 233700.00000000003 ; + LAYER metal3 ; + RECT 0.0 239100.00000000003 62400.00000000001 243300.0 ; + LAYER metal3 ; + RECT 81600.00000000001 239100.00000000003 124800.00000000001 243300.0 ; + LAYER metal3 ; + RECT 194400.0 239100.00000000003 232800.0 243300.0 ; + LAYER metal3 ; + RECT 0.0 248700.00000000003 232800.0 252900.0 ; + LAYER metal3 ; + RECT 0.0 258300.0 62400.00000000001 262500.0 ; + LAYER metal3 ; + RECT 81600.00000000001 258300.0 124800.00000000001 262500.0 ; + LAYER metal3 ; + RECT 194400.0 258300.0 232800.0 262500.0 ; + LAYER metal3 ; + RECT 0.0 267900.00000000006 55200.0 272100.0 ; + LAYER metal3 ; + RECT 64800.0 267900.00000000006 232800.0 272100.0 ; + LAYER metal3 ; + RECT 0.0 277500.0 62400.00000000001 281700.0 ; + LAYER metal3 ; + RECT 84000.0 277500.0 232800.0 281700.0 ; + LAYER metal3 ; + RECT 0.0 287100.0 232800.0 291300.0 ; + LAYER metal3 ; + RECT 0.0 296700.0 232800.0 300900.00000000006 ; + LAYER metal4 ; + RECT -600.0000000000001 0.0 3000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 9000.0 0.0 12600.000000000002 302400.00000000006 ; + LAYER metal4 ; + RECT 18600.0 0.0 22200.000000000004 302400.00000000006 ; + LAYER metal4 ; + RECT 28200.000000000004 0.0 31800.0 302400.00000000006 ; + LAYER metal4 ; + RECT 37800.00000000001 0.0 41400.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 47400.00000000001 0.0 51000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 57000.0 0.0 60600.0 302400.00000000006 ; + LAYER metal4 ; + RECT 66600.00000000001 0.0 70200.0 302400.00000000006 ; + LAYER metal4 ; + RECT 76200.0 0.0 79800.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 85800.00000000001 0.0 89400.0 302400.00000000006 ; + LAYER metal4 ; + RECT 95400.0 0.0 99000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 105000.0 0.0 108600.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 114600.00000000001 0.0 118200.0 302400.00000000006 ; + LAYER metal4 ; + RECT 124200.0 0.0 127800.00000000001 302400.00000000006 ; + LAYER metal4 ; + RECT 133800.0 0.0 137400.0 302400.00000000006 ; + LAYER metal4 ; + RECT 143400.0 0.0 147000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 153000.0 0.0 156600.00000000003 302400.00000000006 ; + LAYER metal4 ; + RECT 162600.00000000003 0.0 166200.00000000003 302400.00000000006 ; + LAYER metal4 ; + RECT 172200.00000000003 0.0 175800.0 302400.00000000006 ; + LAYER metal4 ; + RECT 181800.0 0.0 185400.0 302400.00000000006 ; + LAYER metal4 ; + RECT 191400.0 0.0 195000.0 302400.00000000006 ; + LAYER metal4 ; + RECT 201000.0 0.0 204600.00000000003 302400.00000000006 ; + LAYER metal4 ; + RECT 210600.00000000003 0.0 214200.00000000003 302400.00000000006 ; + LAYER metal4 ; + RECT 220200.00000000003 0.0 223800.0 302400.00000000006 ; + LAYER metal4 ; + RECT 229800.0 0.0 233400.0 302400.00000000006 ; + END + END gnd + OBS + LAYER metal1 ; + RECT 182000.0 22500.000000000004 197800.0 23100.000000000004 ; + RECT 182000.0 22500.000000000004 189900.0 23100.000000000004 ; + RECT 189900.0 22500.000000000004 197800.0 23100.000000000004 ; + RECT 188800.0 23900.000000000004 219600.00000000003 24500.000000000004 ; + RECT 188800.0 23900.000000000004 204200.00000000003 24500.000000000004 ; + RECT 204200.0 23900.000000000004 219600.0 24500.000000000004 ; + RECT 141300.0 126900.0 141899.99999999997 127500.0 ; + RECT 141300.0 125300.00000000001 141899.99999999997 125900.0 ; + RECT 139200.0 126900.0 141600.00000000003 127500.0 ; + RECT 141300.0 125600.00000000001 141899.99999999997 127200.0 ; + RECT 141600.00000000003 125300.00000000001 144100.00000000003 125900.0 ; + RECT 172900.0 126900.0 173500.0 127500.0 ; + RECT 172900.0 123500.0 173500.0 124100.0 ; + RECT 168200.0 126900.0 173200.0 127500.0 ; + RECT 172900.0 123800.00000000001 173500.0 127200.00000000001 ; + RECT 173200.0 123500.0 178200.0 124100.0 ; + RECT 141300.0 136500.0 141899.99999999997 137100.00000000003 ; + RECT 141300.0 138100.00000000003 141899.99999999997 138700.0 ; + RECT 139200.0 136500.0 141600.00000000003 137100.00000000003 ; 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141300.0 156500.0 141899.99999999997 157100.00000000003 ; + RECT 139200.0 154899.99999999997 141600.00000000003 155500.0 ; + RECT 141300.0 155200.0 141899.99999999997 156800.0 ; + RECT 141600.00000000003 156500.0 144100.00000000003 157100.00000000003 ; + RECT 172900.0 154899.99999999997 173500.0 155500.0 ; + RECT 172900.0 157500.0 173500.0 158100.00000000003 ; + RECT 168200.0 154899.99999999997 173200.0 155500.0 ; + RECT 172900.0 155200.0 173500.0 157800.0 ; + RECT 173200.0 157500.0 178200.0 158100.00000000003 ; + RECT 141300.0 163700.0 141899.99999999997 164300.0 ; + RECT 141300.0 162100.00000000003 141899.99999999997 162700.0 ; + RECT 139200.0 163700.0 141600.00000000003 164300.0 ; + RECT 141300.0 162399.99999999997 141899.99999999997 164000.0 ; + RECT 141600.00000000003 162100.00000000003 144100.00000000003 162700.0 ; + RECT 172900.0 163700.0 173500.0 164300.0 ; + RECT 172900.0 160300.0 173500.0 160899.99999999997 ; + RECT 168200.0 163700.0 173200.0 164300.0 ; + RECT 172900.0 160600.00000000003 173500.0 164000.0 ; + RECT 173200.0 160300.0 178200.0 160899.99999999997 ; + RECT 141300.0 173300.0 141899.99999999997 173900.00000000003 ; + RECT 141300.0 174899.99999999997 141899.99999999997 175500.0 ; + RECT 139200.0 173300.0 141600.00000000003 173900.00000000003 ; + RECT 141300.0 173600.00000000003 141899.99999999997 175200.0 ; + RECT 141600.00000000003 174899.99999999997 144100.00000000003 175500.0 ; + RECT 172900.0 173300.0 173500.0 173900.00000000003 ; + RECT 172900.0 175899.99999999997 173500.0 176500.0 ; + RECT 168200.0 173300.0 173200.0 173900.00000000003 ; + RECT 172900.0 173600.00000000003 173500.0 176200.0 ; + RECT 173200.0 175899.99999999997 178200.0 176500.0 ; + RECT 141300.0 182100.00000000003 141899.99999999997 182700.0 ; + RECT 141300.0 180500.0 141899.99999999997 181100.00000000003 ; + RECT 139200.0 182100.00000000003 141600.00000000003 182700.0 ; + RECT 141300.0 180800.0 141899.99999999997 182400.00000000003 ; + RECT 141600.00000000003 180500.0 144100.00000000003 181100.00000000003 ; + RECT 172900.0 182100.00000000003 173500.0 182700.0 ; + RECT 172900.0 178700.0 173500.0 179300.0 ; + RECT 168200.0 182100.00000000003 173200.0 182700.0 ; + RECT 172900.0 179000.0 173500.0 182400.00000000003 ; + RECT 173200.0 178700.0 178200.0 179300.0 ; + RECT 141300.0 191700.0 141899.99999999997 192300.0 ; + RECT 141300.0 193300.0 141899.99999999997 193900.00000000003 ; + RECT 139200.0 191700.0 141600.00000000003 192300.0 ; + RECT 141300.0 192000.0 141899.99999999997 193600.00000000003 ; + RECT 141600.00000000003 193300.0 144100.00000000003 193900.00000000003 ; + RECT 172900.0 191700.0 173500.0 192300.0 ; + RECT 172900.0 194300.0 173500.0 194900.00000000003 ; + RECT 168200.0 191700.0 173200.0 192300.0 ; + RECT 172900.0 192000.0 173500.0 194600.00000000003 ; + RECT 173200.0 194300.0 178200.0 194900.00000000003 ; + RECT 141300.0 200500.0 141899.99999999997 201100.00000000003 ; + RECT 141300.0 198899.99999999997 141899.99999999997 199500.0 ; + RECT 139200.0 200500.0 141600.00000000003 201100.00000000003 ; + RECT 141300.0 199200.0 141899.99999999997 200800.0 ; + RECT 141600.00000000003 198899.99999999997 144100.00000000003 199500.0 ; + RECT 172900.0 200500.0 173500.0 201100.00000000003 ; + RECT 172900.0 197100.00000000003 173500.0 197700.0 ; + RECT 168200.0 200500.0 173200.0 201100.00000000003 ; + RECT 172900.0 197399.99999999997 173500.0 200800.0 ; + RECT 173200.0 197100.00000000003 178200.0 197700.0 ; + RECT 141300.0 210100.00000000003 141899.99999999997 210700.0 ; + RECT 141300.0 211700.0 141899.99999999997 212300.0 ; + RECT 139200.0 210100.00000000003 141600.00000000003 210700.0 ; + RECT 141300.0 210399.99999999997 141899.99999999997 212000.0 ; + RECT 141600.00000000003 211700.0 144100.00000000003 212300.0 ; + RECT 172900.0 210100.00000000003 173500.0 210700.0 ; + RECT 172900.0 212700.0 173500.0 213300.0 ; + RECT 168200.0 210100.00000000003 173200.0 210700.0 ; + RECT 172900.0 210399.99999999997 173500.0 213000.0 ; + RECT 173200.0 212700.0 178200.0 213300.0 ; + RECT 141300.0 218899.99999999997 141899.99999999997 219500.0 ; + RECT 141300.0 217300.0 141899.99999999997 217900.00000000003 ; + RECT 139200.0 218899.99999999997 141600.00000000003 219500.0 ; + RECT 141300.0 217600.00000000003 141899.99999999997 219200.0 ; + RECT 141600.00000000003 217300.0 144100.00000000003 217900.00000000003 ; + RECT 172900.0 218899.99999999997 173500.0 219500.0 ; + RECT 172900.0 215500.0 173500.0 216100.00000000003 ; + RECT 168200.0 218899.99999999997 173200.0 219500.0 ; + RECT 172900.0 215800.0 173500.0 219200.00000000006 ; + RECT 173200.0 215500.0 178200.0 216100.00000000003 ; + RECT 141300.0 228500.0 141899.99999999997 229100.00000000003 ; + RECT 141300.0 230100.00000000003 141899.99999999997 230700.0 ; + RECT 139200.0 228500.0 141600.00000000003 229100.00000000003 ; + RECT 141300.0 228800.0 141899.99999999997 230400.00000000003 ; + RECT 141600.00000000003 230100.00000000003 144100.00000000003 230700.0 ; + RECT 172900.0 228500.0 173500.0 229100.00000000003 ; + RECT 172900.0 231100.00000000003 173500.0 231700.0 ; + RECT 168200.0 228500.0 173200.0 229100.00000000003 ; + RECT 172900.0 228800.0 173500.0 231400.00000000003 ; + RECT 173200.0 231100.00000000003 178200.0 231700.0 ; + RECT 141300.0 237300.0 141899.99999999997 237900.00000000003 ; + RECT 141300.0 235700.0 141899.99999999997 236300.0 ; + RECT 139200.0 237300.0 141600.00000000003 237900.00000000003 ; + RECT 141300.0 236000.0 141899.99999999997 237600.00000000003 ; + RECT 141600.00000000003 235700.0 144100.00000000003 236300.0 ; + RECT 172900.0 237300.0 173500.0 237900.00000000003 ; + RECT 172900.0 233899.99999999997 173500.0 234500.0 ; + RECT 168200.0 237300.0 173200.0 237900.00000000003 ; + RECT 172900.0 234200.0 173500.0 237600.00000000003 ; + RECT 173200.0 233899.99999999997 178200.0 234500.0 ; + RECT 141300.0 246899.99999999997 141899.99999999997 247500.0 ; + RECT 141300.0 248500.0 141899.99999999997 249100.00000000003 ; + RECT 139200.0 246899.99999999997 141600.00000000003 247500.0 ; + RECT 141300.0 247200.0 141899.99999999997 248800.0 ; + RECT 141600.00000000003 248500.0 144100.00000000003 249100.00000000003 ; + RECT 172900.0 246899.99999999997 173500.0 247500.0 ; + RECT 172900.0 249500.0 173500.0 250100.00000000003 ; + RECT 168200.0 246899.99999999997 173200.0 247500.0 ; + RECT 172900.0 247200.0 173500.0 249800.0 ; + RECT 173200.0 249500.0 178200.0 250100.00000000003 ; + RECT 141300.0 255700.0 141899.99999999997 256300.0 ; + RECT 141300.0 254100.00000000003 141899.99999999997 254700.00000000006 ; + RECT 139200.0 255700.0 141600.00000000003 256300.0 ; + RECT 141300.0 254399.99999999997 141899.99999999997 256000.0 ; + RECT 141600.00000000003 254100.00000000003 144100.00000000003 254700.00000000006 ; + RECT 172900.0 255700.0 173500.0 256300.0 ; + RECT 172900.0 252300.0 173500.0 252900.00000000003 ; + RECT 168200.0 255700.0 173200.0 256300.0 ; + RECT 172900.0 252600.00000000003 173500.0 256000.00000000006 ; + RECT 173200.0 252300.0 178200.0 252900.00000000003 ; + RECT 141300.0 265300.0 141899.99999999997 265900.00000000006 ; + RECT 141300.0 266900.0 141899.99999999997 267500.0 ; + RECT 139200.0 265300.0 141600.00000000003 265900.00000000006 ; + RECT 141300.0 265600.0 141899.99999999997 267200.00000000006 ; + RECT 141600.00000000003 266900.0 144100.00000000003 267500.0 ; + RECT 172900.0 265300.0 173500.0 265900.00000000006 ; + RECT 172900.0 267900.0 173500.0 268500.0 ; + RECT 168200.0 265300.0 173200.0 265900.00000000006 ; + RECT 172900.0 265600.0 173500.0 268200.00000000006 ; + RECT 173200.0 267900.0 178200.0 268500.0 ; + RECT 174100.00000000003 108800.0 178600.00000000003 109399.99999999999 ; + RECT 175500.0 29000.0 178600.00000000003 29600.0 ; + RECT 176900.0 98600.00000000001 178600.00000000003 99200.0 ; + RECT 146200.0 271100.0 172700.0 271700.00000000006 ; + RECT 178600.00000000003 122400.0 185400.0 131600.00000000003 ; + RECT 178600.00000000003 140800.0 185400.0 131600.00000000003 ; + RECT 178600.00000000003 140800.0 185400.0 150000.0 ; + RECT 178600.00000000003 159200.0 185400.0 150000.0 ; + RECT 178600.00000000003 159200.0 185400.0 168400.00000000003 ; + RECT 178600.00000000003 177600.00000000003 185400.0 168399.99999999997 ; + RECT 178600.00000000003 177600.00000000003 185400.0 186800.0 ; + RECT 178600.00000000003 196000.0 185400.0 186800.0 ; + RECT 178600.00000000003 196000.0 185400.0 205200.0 ; + RECT 178600.00000000003 214399.99999999997 185400.0 205200.0 ; + RECT 178600.00000000003 214399.99999999997 185400.0 223600.00000000003 ; + RECT 178600.00000000003 232800.0 185400.0 223600.00000000003 ; + RECT 178600.00000000003 232800.0 185400.0 242000.0 ; + RECT 178600.00000000003 251200.0 185400.0 242000.0 ; + RECT 178600.00000000003 251200.0 185400.0 260399.99999999997 ; + RECT 178600.00000000003 269600.0 185400.0 260400.00000000003 ; + RECT 185400.0 122400.0 192200.0 131600.00000000003 ; + RECT 185400.0 140800.0 192200.0 131600.00000000003 ; + RECT 185400.0 140800.0 192200.0 150000.0 ; + RECT 185400.0 159200.0 192200.0 150000.0 ; + RECT 185400.0 159200.0 192200.0 168400.00000000003 ; + RECT 185400.0 177600.00000000003 192200.0 168399.99999999997 ; + RECT 185400.0 177600.00000000003 192200.0 186800.0 ; + RECT 185400.0 196000.0 192200.0 186800.0 ; + RECT 185400.0 196000.0 192200.0 205200.0 ; + RECT 185400.0 214399.99999999997 192200.0 205200.0 ; + RECT 185400.0 214399.99999999997 192200.0 223600.00000000003 ; + RECT 185400.0 232800.0 192200.0 223600.00000000003 ; + RECT 185400.0 232800.0 192200.0 242000.0 ; + RECT 185400.0 251200.0 192200.0 242000.0 ; + RECT 185400.0 251200.0 192200.0 260399.99999999997 ; + RECT 185400.0 269600.0 192200.0 260400.00000000003 ; + RECT 178200.0 123400.0 192400.0 124200.0 ; + RECT 178200.0 139000.0 192400.0 139800.0 ; + RECT 178200.0 141800.0 192400.0 142600.00000000003 ; + RECT 178200.0 157399.99999999997 192400.0 158200.0 ; + RECT 178200.0 160200.0 192400.0 161000.0 ; + RECT 178200.0 175800.0 192400.0 176600.00000000003 ; + RECT 178200.0 178600.00000000003 192400.0 179399.99999999997 ; + RECT 178200.0 194200.0 192400.0 195000.0 ; + RECT 178200.0 197000.0 192400.0 197800.0 ; + RECT 178200.0 212600.00000000003 192400.0 213399.99999999997 ; + RECT 178200.0 215399.99999999997 192400.0 216200.0 ; + RECT 178200.0 231000.0 192400.0 231800.0 ; + RECT 178200.0 233800.0 192400.0 234600.00000000003 ; + RECT 178200.0 249399.99999999997 192400.0 250200.0 ; + RECT 178200.0 252200.0 192400.0 253000.0 ; + RECT 178200.0 267800.0 192400.0 268600.0 ; + RECT 178600.00000000003 117900.0 185400.0 118500.00000000001 ; + RECT 181500.0 112800.00000000001 182100.00000000003 118200.0 ; + RECT 181800.0 107300.00000000001 183800.0 107900.0 ; + RECT 183400.0 112100.00000000001 183800.0 112700.0 ; + RECT 179800.0 107200.0 180600.00000000003 108000.00000000001 ; + RECT 181400.0 107200.0 182200.0 108000.00000000001 ; + RECT 181400.0 107200.0 182200.0 108000.00000000001 ; + RECT 179800.0 107200.0 180600.00000000003 108000.00000000001 ; + RECT 179800.0 112000.00000000001 180600.00000000003 112800.00000000001 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 179800.0 112000.00000000001 180600.00000000003 112800.00000000001 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 183000.0 112000.00000000001 183800.0 112800.00000000001 ; + RECT 183000.0 112000.00000000001 183800.0 112800.00000000001 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 181200.0 108700.0 180400.0 109500.00000000001 ; + RECT 181400.0 115600.00000000001 182200.0 116400.0 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 179800.0 112000.00000000001 180600.00000000003 112800.00000000001 ; + RECT 179800.0 107200.0 180600.00000000003 108000.00000000001 ; + RECT 183400.0 112000.00000000001 184200.0 112800.00000000001 ; + RECT 183400.0 107200.0 184200.0 108000.00000000001 ; + RECT 178600.00000000003 108800.00000000001 185400.0 109400.0 ; + RECT 185400.0 117900.0 192200.0 118500.00000000001 ; + RECT 188300.0 112800.00000000001 188900.0 118200.0 ; + RECT 188600.00000000003 107300.00000000001 190600.00000000003 107900.0 ; + RECT 190200.0 112100.00000000001 190600.00000000003 112700.0 ; + RECT 186600.00000000003 107200.0 187400.0 108000.00000000001 ; + RECT 188200.0 107200.0 189000.0 108000.00000000001 ; + RECT 188200.0 107200.0 189000.0 108000.00000000001 ; + RECT 186600.00000000003 107200.0 187400.0 108000.00000000001 ; + RECT 186600.00000000003 112000.00000000001 187400.0 112800.00000000001 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 186600.00000000003 112000.00000000001 187400.0 112800.00000000001 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 189800.0 112000.00000000001 190600.00000000003 112800.00000000001 ; + RECT 189800.0 112000.00000000001 190600.00000000003 112800.00000000001 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 188000.0 108700.0 187200.0 109500.00000000001 ; + RECT 188200.0 115600.00000000001 189000.0 116400.0 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 186600.00000000003 112000.00000000001 187400.0 112800.00000000001 ; + RECT 186600.00000000003 107200.0 187400.0 108000.00000000001 ; + RECT 190200.0 112000.00000000001 191000.0 112800.00000000001 ; + RECT 190200.0 107200.0 191000.0 108000.00000000001 ; + RECT 185400.0 108800.00000000001 192200.0 109400.0 ; + RECT 178600.00000000003 108800.00000000001 192200.0 109400.0 ; + RECT 178600.00000000003 68800.00000000001 185400.0 101400.0 ; + RECT 185400.0 68800.00000000001 192200.0 101400.0 ; + RECT 178600.00000000003 98600.00000000001 192200.0 99200.0 ; + RECT 178600.00000000003 24200.000000000004 185400.0 64599.99999999999 ; + RECT 185400.0 24200.000000000004 192200.0 64599.99999999999 ; + RECT 178600.00000000003 29000.000000000004 192200.0 29600.0 ; + RECT 133600.0 127300.00000000001 134200.0 127900.0 ; + RECT 133600.0 126900.0 134200.0 127500.00000000001 ; + RECT 130900.0 127300.00000000001 133900.0 127900.0 ; + RECT 133600.0 127200.0 134200.0 127600.00000000001 ; + RECT 133900.0 126900.0 136900.0 127500.00000000001 ; + RECT 133600.0 136100.00000000003 134200.0 136700.0 ; + RECT 133600.0 136500.0 134200.0 137100.00000000003 ; + RECT 130900.0 136100.00000000003 133900.0 136700.0 ; + RECT 133600.0 136400.0 134200.0 136800.0 ; + RECT 133900.0 136500.0 136900.0 137100.00000000003 ; + RECT 133600.0 145700.0 134200.0 146300.0 ; + RECT 133600.0 145300.0 134200.0 145900.0 ; + RECT 130900.0 145700.0 133900.0 146300.0 ; + RECT 133600.0 145600.00000000003 134200.0 146000.0 ; + RECT 133900.0 145300.0 136900.0 145900.0 ; + RECT 133600.0 154500.0 134200.0 155100.00000000003 ; + RECT 133600.0 154899.99999999997 134200.0 155500.0 ; + RECT 130900.0 154500.0 133900.0 155100.00000000003 ; + RECT 133600.0 154800.0 134200.0 155200.0 ; + RECT 133900.0 154899.99999999997 136900.0 155500.0 ; + RECT 133600.0 164100.00000000003 134200.0 164700.0 ; + RECT 133600.0 163700.0 134200.0 164300.0 ; + RECT 130900.0 164100.00000000003 133900.0 164700.0 ; + RECT 133600.0 164000.0 134200.0 164399.99999999997 ; + RECT 133900.0 163700.0 136900.0 164300.0 ; + RECT 133600.0 172899.99999999997 134200.0 173500.0 ; + RECT 133600.0 173300.0 134200.0 173899.99999999997 ; + RECT 130900.0 172899.99999999997 133900.0 173500.0 ; + RECT 133600.0 173200.0 134200.0 173600.00000000003 ; + RECT 133900.0 173300.0 136900.0 173899.99999999997 ; + RECT 133600.0 182500.0 134200.0 183100.00000000003 ; + RECT 133600.0 182100.00000000003 134200.0 182700.0 ; + RECT 130900.0 182500.0 133900.0 183100.00000000003 ; + RECT 133600.0 182399.99999999997 134200.0 182800.0 ; + RECT 133900.0 182100.00000000003 136900.0 182700.0 ; + RECT 133600.0 191300.0 134200.0 191899.99999999997 ; + RECT 133600.0 191700.0 134200.0 192300.0 ; + RECT 130900.0 191300.0 133900.0 191899.99999999997 ; + RECT 133600.0 191600.00000000003 134200.0 192000.0 ; + RECT 133900.0 191700.0 136900.0 192300.0 ; + RECT 133600.0 200900.00000000003 134200.0 201500.0 ; + RECT 133600.0 200500.0 134200.0 201100.00000000003 ; + RECT 130900.0 200900.00000000003 133900.0 201500.0 ; + RECT 133600.0 200800.0 134200.0 201200.0 ; + RECT 133900.0 200500.0 136900.0 201100.00000000003 ; + RECT 133600.0 209700.0 134200.0 210300.0 ; + RECT 133600.0 210100.00000000003 134200.0 210700.0 ; + RECT 130900.0 209700.0 133900.0 210300.0 ; + RECT 133600.0 210000.0 134200.0 210400.00000000003 ; + RECT 133900.0 210100.00000000003 136900.0 210700.0 ; + RECT 133600.0 219300.0 134200.0 219899.99999999997 ; + RECT 133600.0 218900.00000000003 134200.0 219500.0 ; + RECT 130900.0 219300.0 133900.0 219899.99999999997 ; + RECT 133600.0 219200.0 134200.0 219600.00000000003 ; + RECT 133900.0 218900.00000000003 136900.0 219500.0 ; + RECT 133600.0 228100.00000000003 134200.0 228700.0 ; + RECT 133600.0 228500.0 134200.0 229100.00000000003 ; + RECT 130900.0 228100.00000000003 133900.0 228700.0 ; + RECT 133600.0 228400.00000000003 134200.0 228800.0 ; + RECT 133900.0 228500.0 136900.0 229100.00000000003 ; + RECT 133600.0 237700.0 134200.0 238300.0 ; + RECT 133600.0 237300.0 134200.0 237899.99999999997 ; + RECT 130900.0 237700.0 133900.0 238300.0 ; + RECT 133600.0 237600.00000000003 134200.0 238000.0 ; + RECT 133900.0 237300.0 136900.0 237899.99999999997 ; + RECT 133600.0 246500.0 134200.0 247100.00000000003 ; + RECT 133600.0 246900.00000000003 134200.0 247500.0 ; + RECT 130900.0 246500.0 133900.0 247100.00000000003 ; + RECT 133600.0 246800.0 134200.0 247200.0 ; + RECT 133900.0 246900.00000000003 136900.0 247500.0 ; + RECT 133600.0 256100.00000000003 134200.0 256700.0 ; + RECT 133600.0 255700.0 134200.0 256300.0 ; + RECT 130900.0 256100.00000000003 133900.0 256700.0 ; + RECT 133600.0 256000.0 134200.0 256400.00000000003 ; + RECT 133900.0 255700.0 136900.0 256300.0 ; + RECT 133600.0 264900.0 134200.0 265500.0 ; + RECT 133600.0 265300.0 134200.0 265900.0 ; + RECT 130900.0 264900.0 133900.0 265500.0 ; + RECT 133600.0 265200.0 134200.0 265600.0 ; + RECT 133900.0 265300.0 136900.0 265900.0 ; + RECT 115100.0 127300.00000000001 127300.00000000001 127900.0 ; + RECT 120700.0 125900.0 129300.00000000001 126500.0 ; + RECT 115100.0 136100.00000000003 127300.00000000001 136700.0 ; + RECT 122100.0 137500.0 129300.00000000001 138100.00000000003 ; + RECT 115100.0 145700.0 127300.00000000001 146300.0 ; + RECT 123500.0 144300.0 129300.00000000001 144900.0 ; + RECT 115100.0 154500.0 127300.00000000001 155100.00000000003 ; + RECT 124900.0 155899.99999999997 129300.00000000001 156500.0 ; + RECT 116500.0 164100.00000000003 127300.0 164700.0 ; + RECT 120700.0 162700.0 129300.00000000001 163300.0 ; + RECT 116500.0 172899.99999999997 127300.0 173500.0 ; + RECT 122100.0 174300.0 129300.00000000001 174899.99999999997 ; + RECT 116500.0 182500.0 127300.0 183100.00000000003 ; + RECT 123500.0 181100.00000000003 129300.00000000001 181700.0 ; + RECT 116500.0 191300.0 127300.0 191899.99999999997 ; + RECT 124900.0 192700.0 129300.00000000001 193300.0 ; + RECT 117900.0 200900.00000000003 127300.0 201500.0 ; + RECT 120700.0 199500.0 129300.00000000001 200100.00000000003 ; + RECT 117900.0 209700.0 127300.0 210300.0 ; + RECT 122100.0 211100.00000000003 129300.00000000001 211700.0 ; + RECT 117900.0 219300.0 127300.0 219899.99999999997 ; + RECT 123500.0 217900.00000000003 129300.00000000001 218500.0 ; + RECT 117900.0 228100.00000000003 127300.0 228700.0 ; + RECT 124900.0 229500.0 129300.00000000001 230100.00000000003 ; + RECT 119300.0 237700.0 127300.0 238300.0 ; + RECT 120700.0 236300.0 129300.00000000001 236899.99999999997 ; + RECT 119300.0 246500.0 127300.0 247100.00000000003 ; + RECT 122100.0 247900.00000000003 129300.00000000001 248500.0 ; + RECT 119300.0 256100.00000000003 127300.0 256700.0 ; + RECT 123500.0 254700.0 129300.00000000001 255300.0 ; + RECT 119300.0 264900.0 127300.0 265500.0 ; + RECT 124900.0 266300.0 129300.00000000001 266900.0 ; + RECT 125700.0 131700.0 141700.0 132300.0 ; + RECT 125700.0 122500.0 141700.0 123100.00000000001 ; + RECT 125700.0 150100.00000000003 141700.0 150700.0 ; + RECT 125700.0 140900.0 141700.0 141500.0 ; + RECT 125700.0 168500.0 141700.0 169100.00000000003 ; + RECT 125700.0 159300.0 141700.0 159899.99999999997 ; + RECT 125700.0 186900.00000000003 141700.0 187500.0 ; + RECT 125700.0 177700.0 141700.0 178300.0 ; + RECT 125700.0 205300.0 141700.0 205899.99999999997 ; + RECT 125700.0 196100.00000000003 141700.0 196700.0 ; + RECT 125700.0 223700.0 141700.0 224300.0 ; + RECT 125700.0 214500.0 141700.0 215100.00000000003 ; + RECT 125700.0 242100.00000000003 141700.0 242700.0 ; + RECT 125700.0 232900.00000000003 141700.0 233500.0 ; + RECT 125700.0 260500.0 141700.0 261100.00000000003 ; + RECT 125700.0 251300.0 141700.0 251899.99999999997 ; + RECT 90400.0 126900.0 91000.0 127500.00000000001 ; + RECT 90400.0 129900.0 91000.0 130500.0 ; + RECT 87600.0 126900.0 90700.0 127500.00000000001 ; + RECT 90400.0 127200.0 91000.0 130199.99999999999 ; + RECT 90700.0 129900.0 93200.0 130500.0 ; + RECT 81500.0 126900.0 85300.0 127500.00000000001 ; + RECT 90400.0 136500.0 91000.0 137100.00000000003 ; + RECT 90400.0 139100.00000000003 91000.0 139700.0 ; + RECT 87600.0 136500.0 90700.0 137100.00000000003 ; + RECT 90400.0 136800.0 91000.0 139400.0 ; + RECT 90700.0 139100.00000000003 94600.0 139700.0 ; + RECT 82900.0 136500.0 85300.0 137100.00000000003 ; + RECT 81500.0 142300.0 96000.0 142900.0 ; + RECT 82900.0 151500.0 97400.0 152100.00000000003 ; + RECT 93200.0 127300.00000000001 100100.0 127900.0 ; + RECT 94600.0 125900.0 102100.0 126500.0 ; + RECT 96000.0 136100.00000000003 100100.0 136700.0 ; + RECT 94600.0 137500.0 102100.0 138100.00000000003 ; + RECT 93200.0 145700.0 100100.0 146300.0 ; + RECT 97400.0 144300.0 102100.0 144900.0 ; + RECT 96000.0 154500.0 100100.0 155100.00000000003 ; + RECT 97400.0 155899.99999999997 102100.0 156500.0 ; + RECT 106400.0 127300.00000000001 107000.0 127900.0 ; + RECT 106400.0 126900.0 107000.0 127500.00000000001 ; + RECT 103700.0 127300.00000000001 106700.0 127900.0 ; + RECT 106400.0 127200.0 107000.0 127600.00000000001 ; + RECT 106700.0 126900.0 109700.0 127500.00000000001 ; + RECT 106400.0 136100.00000000003 107000.0 136700.0 ; + RECT 106400.0 136500.0 107000.0 137100.00000000003 ; + RECT 103700.0 136100.00000000003 106700.0 136700.0 ; + RECT 106400.0 136400.0 107000.0 136800.0 ; + RECT 106700.0 136500.0 109700.0 137100.00000000003 ; + RECT 106400.0 145700.0 107000.0 146300.0 ; + RECT 106400.0 145300.0 107000.0 145900.0 ; + RECT 103700.0 145700.0 106700.0 146300.0 ; + RECT 106400.0 145600.00000000003 107000.0 146000.0 ; + RECT 106700.0 145300.0 109700.0 145900.0 ; + RECT 106400.0 154500.0 107000.0 155100.00000000003 ; + RECT 106400.0 154899.99999999997 107000.0 155500.0 ; + RECT 103700.0 154500.0 106700.0 155100.00000000003 ; + RECT 106400.0 154800.0 107000.0 155200.0 ; + RECT 106700.0 154899.99999999997 109700.0 155500.0 ; + RECT 80900.0 131700.0 114500.0 132300.0 ; + RECT 80900.0 122500.0 114500.0 123100.00000000001 ; + RECT 80900.0 131700.0 114500.0 132300.0 ; + RECT 80900.0 140900.0 114500.0 141500.0 ; + RECT 80900.0 150100.00000000003 114500.0 150700.0 ; + RECT 80900.0 140900.0 114500.0 141500.0 ; + RECT 80900.0 150100.00000000003 114500.0 150700.0 ; + RECT 80900.0 159300.0 114500.0 159899.99999999997 ; + RECT 88100.0 130699.99999999999 88900.0 132000.0 ; + RECT 88100.0 122800.00000000001 88900.0 124100.00000000001 ; + RECT 84900.0 123700.0 85700.0 122500.0 ; + RECT 84900.0 129900.0 85700.0 132300.0 ; + RECT 86700.0 123700.0 87300.0 129900.0 ; + RECT 84900.0 129900.0 85700.0 130699.99999999999 ; + RECT 86500.0 129900.0 87300.0 130699.99999999999 ; + RECT 86500.0 129900.0 87300.0 130699.99999999999 ; + RECT 84900.0 129900.0 85700.0 130699.99999999999 ; + RECT 84900.0 123700.0 85700.0 124500.0 ; + RECT 86500.0 123700.0 87300.0 124500.0 ; + RECT 86500.0 123700.0 87300.0 124500.0 ; + RECT 84900.0 123700.0 85700.0 124500.0 ; + RECT 88100.0 130300.00000000001 88900.0 131100.00000000003 ; + RECT 88100.0 123700.0 88900.0 124500.0 ; + RECT 85300.0 126800.00000000001 86100.0 127600.00000000001 ; + RECT 85300.0 126800.00000000001 86100.0 127600.00000000001 ; + RECT 87000.0 126900.0 87600.0 127500.0 ; + RECT 83700.0 131700.0 90100.0 132300.0 ; + RECT 83700.0 122500.0 90100.0 123100.00000000001 ; + RECT 88100.0 133300.0 88900.0 132000.0 ; + RECT 88100.0 141200.0 88900.0 139900.0 ; + RECT 84900.0 140300.0 85700.0 141500.0 ; + RECT 84900.0 134100.00000000003 85700.0 131700.0 ; + RECT 86700.0 140300.0 87300.0 134100.00000000003 ; + RECT 84900.0 134100.00000000003 85700.0 133300.0 ; + RECT 86500.0 134100.00000000003 87300.0 133300.0 ; + RECT 86500.0 134100.00000000003 87300.0 133300.0 ; + RECT 84900.0 134100.00000000003 85700.0 133300.0 ; + RECT 84900.0 140300.0 85700.0 139500.0 ; + RECT 86500.0 140300.0 87300.0 139500.0 ; + RECT 86500.0 140300.0 87300.0 139500.0 ; + RECT 84900.0 140300.0 85700.0 139500.0 ; + RECT 88100.0 133700.0 88900.0 132900.0 ; + RECT 88100.0 140300.0 88900.0 139500.0 ; + RECT 85300.0 137200.0 86100.0 136400.0 ; + RECT 85300.0 137200.0 86100.0 136400.0 ; + RECT 87000.0 137100.00000000003 87600.0 136500.0 ; + RECT 83700.0 132300.0 90100.0 131700.0 ; + RECT 83700.0 141500.0 90100.0 140900.0 ; + RECT 112500.0 130699.99999999999 113300.00000000001 132000.0 ; + RECT 112500.0 122800.00000000001 113300.00000000001 124100.00000000001 ; + RECT 109300.0 123700.0 110100.0 122500.0 ; + RECT 109300.0 129900.0 110100.0 132300.0 ; + RECT 111100.0 123700.0 111700.0 129900.0 ; + RECT 109300.0 129900.0 110100.0 130699.99999999999 ; + RECT 110900.0 129900.0 111700.0 130699.99999999999 ; + RECT 110900.0 129900.0 111700.0 130699.99999999999 ; + RECT 109300.0 129900.0 110100.0 130699.99999999999 ; + RECT 109300.0 123700.0 110100.0 124500.0 ; + RECT 110900.0 123700.0 111700.0 124500.0 ; + RECT 110900.0 123700.0 111700.0 124500.0 ; + RECT 109300.0 123700.0 110100.0 124500.0 ; + RECT 112500.0 130300.00000000001 113300.00000000001 131100.00000000003 ; + RECT 112500.0 123700.0 113300.00000000001 124500.0 ; + RECT 109700.0 126800.00000000001 110500.0 127600.00000000001 ; + RECT 109700.0 126800.00000000001 110500.0 127600.00000000001 ; + RECT 111400.0 126900.0 112000.0 127500.0 ; + RECT 108100.0 131700.0 114500.0 132300.0 ; + RECT 108100.0 122500.0 114500.0 123100.00000000001 ; + RECT 112500.0 133300.0 113300.00000000001 132000.0 ; + RECT 112500.0 141200.0 113300.00000000001 139900.0 ; + RECT 109300.0 140300.0 110100.0 141500.0 ; + RECT 109300.0 134100.00000000003 110100.0 131700.0 ; + RECT 111100.0 140300.0 111700.0 134100.00000000003 ; + RECT 109300.0 134100.00000000003 110100.0 133300.0 ; + RECT 110900.0 134100.00000000003 111700.0 133300.0 ; + RECT 110900.0 134100.00000000003 111700.0 133300.0 ; + RECT 109300.0 134100.00000000003 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102900.0 134100.00000000003 103700.0 133300.0 ; + RECT 102900.0 134100.00000000003 103700.0 133300.0 ; + RECT 101300.0 134100.00000000003 102100.0 133300.0 ; + RECT 99700.0 139900.0 100500.0 139100.00000000003 ; + RECT 101300.0 139900.0 102100.0 139100.00000000003 ; + RECT 101300.0 139900.0 102100.0 139100.00000000003 ; + RECT 99700.0 139900.0 100500.0 139100.00000000003 ; + RECT 101300.0 139900.0 102100.0 139100.00000000003 ; + RECT 102900.0 139900.0 103700.0 139100.00000000003 ; + RECT 102900.0 139900.0 103700.0 139100.00000000003 ; + RECT 101300.0 139900.0 102100.0 139100.00000000003 ; + RECT 104500.0 133700.0 105300.0 132900.0 ; + RECT 104500.0 140300.0 105300.0 139500.0 ; + RECT 102900.0 138200.0 102100.0 137400.0 ; + RECT 100900.0 136800.0 100100.0 136000.0 ; + RECT 101300.0 134100.00000000003 102100.0 133300.0 ; + RECT 102900.0 139900.0 103700.0 139100.00000000003 ; + RECT 103700.0 136800.0 102900.0 136000.0 ; + RECT 100100.0 136800.0 100900.0 136000.0 ; + RECT 102100.0 138200.0 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93600.0 145600.00000000003 92800.0 146400.0 ; + RECT 97800.0 144200.0 97000.0 145000.0 ; + RECT 96400.0 154399.99999999997 95600.0 155200.0 ; + RECT 97800.0 155800.0 97000.0 156600.00000000003 ; + RECT 90500.0 131600.00000000003 89700.0 132400.0 ; + RECT 108500.0 131600.00000000003 107700.0 132400.0 ; + RECT 90500.0 122400.0 89700.0 123200.0 ; + RECT 108500.0 122400.0 107700.0 123200.0 ; + RECT 90500.0 131600.00000000003 89700.0 132400.0 ; + RECT 108500.0 131600.00000000003 107700.0 132400.0 ; + RECT 90500.0 140800.0 89700.0 141600.00000000003 ; + RECT 108500.0 140800.0 107700.0 141600.00000000003 ; + RECT 90500.0 150000.0 89700.0 150800.0 ; + RECT 108500.0 150000.0 107700.0 150800.0 ; + RECT 90500.0 140800.0 89700.0 141600.00000000003 ; + RECT 108500.0 140800.0 107700.0 141600.00000000003 ; + RECT 90500.0 150000.0 89700.0 150800.0 ; + RECT 108500.0 150000.0 107700.0 150800.0 ; + RECT 90500.0 159200.0 89700.0 160000.0 ; + RECT 108500.0 159200.0 107700.0 160000.0 ; + RECT 111400.0 126900.0 112000.0 127500.0 ; + RECT 111400.0 136500.0 112000.0 137100.00000000003 ; + RECT 111400.0 145300.0 112000.0 145900.0 ; + RECT 111400.0 154899.99999999997 112000.0 155500.0 ; + RECT 90400.0 163700.0 91000.0 164300.0 ; + RECT 90400.0 166700.0 91000.0 167300.0 ; + RECT 87600.0 163700.0 90700.0 164300.0 ; + RECT 90400.0 164000.0 91000.0 167000.0 ; + RECT 90700.0 166700.0 93200.0 167300.0 ; + RECT 81500.0 163700.0 85300.0 164300.0 ; + RECT 90400.0 173300.0 91000.0 173899.99999999997 ; + RECT 90400.0 175899.99999999997 91000.0 176500.0 ; + RECT 87600.0 173300.0 90700.0 173899.99999999997 ; + RECT 90400.0 173600.00000000003 91000.0 176200.0 ; + RECT 90700.0 175899.99999999997 94600.0 176500.0 ; + RECT 82900.0 173300.0 85300.0 173899.99999999997 ; + RECT 81500.0 179100.00000000003 96000.0 179700.0 ; + RECT 82900.0 188300.0 97400.0 188899.99999999997 ; + RECT 93200.0 164100.00000000003 100100.0 164700.0 ; + RECT 94600.0 162700.0 102100.0 163300.0 ; + RECT 96000.0 172899.99999999997 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231100.00000000003 ; + RECT 131700.0 225700.0 132500.0 224900.00000000003 ; + RECT 131700.0 232300.0 132500.0 231500.0 ; + RECT 130100.0 230200.0 129300.00000000001 229400.00000000003 ; + RECT 128100.0 228800.0 127300.00000000001 228000.0 ; + RECT 128500.0 226100.00000000003 129300.00000000001 225300.0 ; + RECT 130100.0 231900.00000000003 130900.0 231100.00000000003 ; + RECT 130900.0 228800.0 130100.0 228000.0 ; + RECT 127300.00000000001 228800.0 128100.0 228000.0 ; + RECT 129300.00000000001 230200.0 130100.0 229400.00000000003 ; + RECT 130100.0 228800.0 130900.0 228000.0 ; + RECT 125700.0 224300.0 135300.0 223700.0 ; + RECT 125700.0 233500.0 135300.0 232900.00000000003 ; + RECT 126900.0 234500.0 127700.0 232900.00000000003 ; + RECT 126900.0 240300.0 127700.0 242700.0 ; + RECT 130100.0 240300.0 130900.0 242700.0 ; + RECT 131700.0 241100.00000000003 132500.0 242400.00000000003 ; + RECT 131700.0 233200.0 132500.0 234500.0 ; + RECT 126900.0 240300.0 127700.0 241100.00000000003 ; + RECT 128500.0 240300.0 129300.00000000001 241100.00000000003 ; + RECT 128500.0 240300.0 129300.00000000001 241100.00000000003 ; + RECT 126900.0 240300.0 127700.0 241100.00000000003 ; + RECT 128500.0 240300.0 129300.00000000001 241100.00000000003 ; + RECT 130100.0 240300.0 130900.0 241100.00000000003 ; + RECT 130100.0 240300.0 130900.0 241100.00000000003 ; + RECT 128500.0 240300.0 129300.00000000001 241100.00000000003 ; + RECT 126900.0 234500.0 127700.0 235300.0 ; + RECT 128500.0 234500.0 129300.00000000001 235300.0 ; + RECT 128500.0 234500.0 129300.00000000001 235300.0 ; + RECT 126900.0 234500.0 127700.0 235300.0 ; + RECT 128500.0 234500.0 129300.00000000001 235300.0 ; + RECT 130100.0 234500.0 130900.0 235300.0 ; + RECT 130100.0 234500.0 130900.0 235300.0 ; + RECT 128500.0 234500.0 129300.00000000001 235300.0 ; + RECT 131700.0 240700.0 132500.0 241500.0 ; + RECT 131700.0 234100.00000000003 132500.0 234900.00000000003 ; + RECT 130100.0 236200.0 129300.00000000001 237000.0 ; + RECT 128100.0 237600.00000000003 127300.00000000001 238400.00000000003 ; + RECT 128500.0 240300.0 129300.00000000001 241100.00000000003 ; + RECT 130100.0 234500.0 130900.0 235300.0 ; + RECT 130900.0 237600.00000000003 130100.0 238400.00000000003 ; + RECT 127300.00000000001 237600.00000000003 128100.0 238400.00000000003 ; + RECT 129300.00000000001 236200.0 130100.0 237000.0 ; + RECT 130100.0 237600.00000000003 130900.0 238400.00000000003 ; + RECT 125700.0 242100.00000000003 135300.0 242700.0 ; + RECT 125700.0 232900.00000000003 135300.0 233500.0 ; + RECT 126900.0 250300.0 127700.0 251900.00000000003 ; + RECT 126900.0 244500.0 127700.0 242100.00000000003 ; + RECT 130100.0 244500.0 130900.0 242100.00000000003 ; + RECT 131700.0 243700.0 132500.0 242400.00000000003 ; + RECT 131700.0 251600.00000000003 132500.0 250300.0 ; + RECT 126900.0 244500.0 127700.0 243700.0 ; + RECT 128500.0 244500.0 129300.00000000001 243700.0 ; + RECT 128500.0 244500.0 129300.00000000001 243700.0 ; + RECT 126900.0 244500.0 127700.0 243700.0 ; + RECT 128500.0 244500.0 129300.00000000001 243700.0 ; + RECT 130100.0 244500.0 130900.0 243700.0 ; + RECT 130100.0 244500.0 130900.0 243700.0 ; + RECT 128500.0 244500.0 129300.00000000001 243700.0 ; + RECT 126900.0 250300.0 127700.0 249500.0 ; + RECT 128500.0 250300.0 129300.00000000001 249500.0 ; + RECT 128500.0 250300.0 129300.00000000001 249500.0 ; + RECT 126900.0 250300.0 127700.0 249500.0 ; + RECT 128500.0 250300.0 129300.00000000001 249500.0 ; + RECT 130100.0 250300.0 130900.0 249500.0 ; + RECT 130100.0 250300.0 130900.0 249500.0 ; + RECT 128500.0 250300.0 129300.00000000001 249500.0 ; + RECT 131700.0 244100.00000000003 132500.0 243300.0 ; + RECT 131700.0 250700.0 132500.0 249900.00000000003 ; + RECT 130100.0 248600.00000000003 129300.00000000001 247800.0 ; + RECT 128100.0 247200.0 127300.00000000001 246400.00000000003 ; + RECT 128500.0 244500.0 129300.00000000001 243700.0 ; + RECT 130100.0 250300.0 130900.0 249500.0 ; + RECT 130900.0 247200.0 130100.0 246400.00000000003 ; + RECT 127300.00000000001 247200.0 128100.0 246400.00000000003 ; + RECT 129300.00000000001 248600.00000000003 130100.0 247800.0 ; + RECT 130100.0 247200.0 130900.0 246400.00000000003 ; + RECT 125700.0 242700.0 135300.0 242100.00000000003 ; + RECT 125700.0 251900.00000000003 135300.0 251300.0 ; + RECT 126900.0 252900.00000000003 127700.0 251300.0 ; + RECT 126900.0 258700.0 127700.0 261100.00000000003 ; + RECT 130100.0 258700.0 130900.0 261100.00000000003 ; + RECT 131700.0 259500.0 132500.0 260800.0 ; + RECT 131700.0 251600.00000000003 132500.0 252900.00000000003 ; + RECT 126900.0 258700.0 127700.0 259500.0 ; + RECT 128500.0 258700.0 129300.00000000001 259500.0 ; + RECT 128500.0 258700.0 129300.00000000001 259500.0 ; + RECT 126900.0 258700.0 127700.0 259500.0 ; + RECT 128500.0 258700.0 129300.00000000001 259500.0 ; + RECT 130100.0 258700.0 130900.0 259500.0 ; + RECT 130100.0 258700.0 130900.0 259500.0 ; + RECT 128500.0 258700.0 129300.00000000001 259500.0 ; + RECT 126900.0 252900.00000000003 127700.0 253700.0 ; + RECT 128500.0 252900.00000000003 129300.00000000001 253700.0 ; + RECT 128500.0 252900.00000000003 129300.00000000001 253700.0 ; + RECT 126900.0 252900.00000000003 127700.0 253700.0 ; + RECT 128500.0 252900.00000000003 129300.00000000001 253700.0 ; + RECT 130100.0 252900.00000000003 130900.0 253700.0 ; + RECT 130100.0 252900.00000000003 130900.0 253700.0 ; + RECT 128500.0 252900.00000000003 129300.00000000001 253700.0 ; + RECT 131700.0 259100.00000000003 132500.0 259900.00000000003 ; + RECT 131700.0 252500.0 132500.0 253300.0 ; + RECT 130100.0 254600.00000000003 129300.00000000001 255400.00000000003 ; + RECT 128100.0 256000.0 127300.00000000001 256800.0 ; + RECT 128500.0 258700.0 129300.00000000001 259500.0 ; + RECT 130100.0 252900.00000000003 130900.0 253700.0 ; + RECT 130900.0 256000.0 130100.0 256800.0 ; + RECT 127300.00000000001 256000.0 128100.0 256800.0 ; + RECT 129300.00000000001 254600.00000000003 130100.0 255400.00000000003 ; + RECT 130100.0 256000.0 130900.0 256800.0 ; + RECT 125700.0 260500.0 135300.0 261100.00000000003 ; + RECT 125700.0 251300.0 135300.0 251900.00000000003 ; + RECT 126900.0 268700.0 127700.0 270300.0 ; + RECT 126900.0 262900.00000000006 127700.0 260500.0 ; + RECT 130100.0 262900.00000000006 130900.0 260500.0 ; + RECT 131700.0 262100.00000000003 132500.0 260800.0 ; + RECT 131700.0 270000.0 132500.0 268700.0 ; + RECT 126900.0 262900.00000000006 127700.0 262100.00000000003 ; + RECT 128500.0 262900.00000000006 129300.00000000001 262100.00000000003 ; + RECT 128500.0 262900.00000000006 129300.00000000001 262100.00000000003 ; + RECT 126900.0 262900.00000000006 127700.0 262100.00000000003 ; + RECT 128500.0 262900.00000000006 129300.00000000001 262100.00000000003 ; + RECT 130100.0 262900.00000000006 130900.0 262100.00000000003 ; + RECT 130100.0 262900.00000000006 130900.0 262100.00000000003 ; + RECT 128500.0 262900.00000000006 129300.00000000001 262100.00000000003 ; + RECT 126900.0 268700.0 127700.0 267900.00000000006 ; + RECT 128500.0 268700.0 129300.00000000001 267900.00000000006 ; + RECT 128500.0 268700.0 129300.00000000001 267900.00000000006 ; + RECT 126900.0 268700.0 127700.0 267900.00000000006 ; + RECT 128500.0 268700.0 129300.00000000001 267900.00000000006 ; + RECT 130100.0 268700.0 130900.0 267900.00000000006 ; + RECT 130100.0 268700.0 130900.0 267900.00000000006 ; + RECT 128500.0 268700.0 129300.00000000001 267900.00000000006 ; + RECT 131700.0 262500.0 132500.0 261700.0 ; + RECT 131700.0 269100.0 132500.0 268300.0 ; + RECT 130100.0 267000.0 129300.00000000001 266200.0 ; + RECT 128100.0 265600.0 127300.00000000001 264800.0 ; + RECT 128500.0 262900.00000000006 129300.00000000001 262100.00000000003 ; + RECT 130100.0 268700.0 130900.0 267900.00000000006 ; + RECT 130900.0 265600.0 130100.0 264800.0 ; + RECT 127300.00000000001 265600.0 128100.0 264800.0 ; + RECT 129300.00000000001 267000.0 130100.0 266200.0 ; + RECT 130100.0 265600.0 130900.0 264800.0 ; + RECT 125700.0 261100.00000000003 135300.0 260500.0 ; + RECT 125700.0 270300.0 135300.0 269700.0 ; + RECT 139700.0 130699.99999999999 140500.0 132000.0 ; + RECT 139700.0 122800.00000000001 140500.0 124100.00000000001 ; + RECT 136500.0 123700.0 137300.0 122500.0 ; + RECT 136500.0 129900.0 137300.0 132300.0 ; + RECT 138300.0 123700.0 138899.99999999997 129900.0 ; + RECT 136500.0 129900.0 137300.0 130699.99999999999 ; + RECT 138100.0 129900.0 138899.99999999997 130699.99999999999 ; + RECT 138100.0 129900.0 138899.99999999997 130699.99999999999 ; + RECT 136500.0 129900.0 137300.0 130699.99999999999 ; + RECT 136500.0 123700.0 137300.0 124500.0 ; + RECT 138100.0 123700.0 138899.99999999997 124500.0 ; + RECT 138100.0 123700.0 138899.99999999997 124500.0 ; + RECT 136500.0 123700.0 137300.0 124500.0 ; + RECT 139700.0 130300.00000000001 140500.0 131100.00000000003 ; + RECT 139700.0 123700.0 140500.0 124500.0 ; + RECT 136900.0 126800.00000000001 137700.0 127600.00000000001 ; + RECT 136900.0 126800.00000000001 137700.0 127600.00000000001 ; + RECT 138600.0 126900.0 139200.0 127500.0 ; + RECT 135300.0 131700.0 141700.0 132300.0 ; + RECT 135300.0 122500.0 141700.0 123100.00000000001 ; + RECT 139700.0 133300.0 140500.0 132000.0 ; + RECT 139700.0 141200.0 140500.0 139900.0 ; + RECT 136500.0 140300.0 137300.0 141500.0 ; + RECT 136500.0 134100.00000000003 137300.0 131700.0 ; + RECT 138300.0 140300.0 138899.99999999997 134100.00000000003 ; + RECT 136500.0 134100.00000000003 137300.0 133300.0 ; + RECT 138100.0 134100.00000000003 138899.99999999997 133300.0 ; + RECT 138100.0 134100.00000000003 138899.99999999997 133300.0 ; + RECT 136500.0 134100.00000000003 137300.0 133300.0 ; + RECT 136500.0 140300.0 137300.0 139500.0 ; + RECT 138100.0 140300.0 138899.99999999997 139500.0 ; + RECT 138100.0 140300.0 138899.99999999997 139500.0 ; + RECT 136500.0 140300.0 137300.0 139500.0 ; + RECT 139700.0 133700.0 140500.0 132900.0 ; + RECT 139700.0 140300.0 140500.0 139500.0 ; + RECT 136900.0 137200.0 137700.0 136400.0 ; + RECT 136900.0 137200.0 137700.0 136400.0 ; + RECT 138600.0 137100.00000000003 139200.0 136500.0 ; + RECT 135300.0 132300.0 141700.0 131700.0 ; + RECT 135300.0 141500.0 141700.0 140900.0 ; + RECT 139700.0 149100.00000000003 140500.0 150400.0 ; + RECT 139700.0 141200.0 140500.0 142500.0 ; + RECT 136500.0 142100.00000000003 137300.0 140900.0 ; + RECT 136500.0 148300.0 137300.0 150700.0 ; + RECT 138300.0 142100.00000000003 138899.99999999997 148300.0 ; + RECT 136500.0 148300.0 137300.0 149100.00000000003 ; + RECT 138100.0 148300.0 138899.99999999997 149100.00000000003 ; + RECT 138100.0 148300.0 138899.99999999997 149100.00000000003 ; + RECT 136500.0 148300.0 137300.0 149100.00000000003 ; + RECT 136500.0 142100.00000000003 137300.0 142900.0 ; + RECT 138100.0 142100.00000000003 138899.99999999997 142900.0 ; + RECT 138100.0 142100.00000000003 138899.99999999997 142900.0 ; + RECT 136500.0 142100.00000000003 137300.0 142900.0 ; + RECT 139700.0 148700.0 140500.0 149500.0 ; + RECT 139700.0 142100.00000000003 140500.0 142900.0 ; + RECT 136900.0 145200.0 137700.0 146000.0 ; + RECT 136900.0 145200.0 137700.0 146000.0 ; + RECT 138600.0 145300.0 139200.0 145900.0 ; + RECT 135300.0 150100.00000000003 141700.0 150700.0 ; + RECT 135300.0 140900.0 141700.0 141500.0 ; + RECT 139700.0 151700.0 140500.0 150400.0 ; + RECT 139700.0 159600.00000000003 140500.0 158300.0 ; + RECT 136500.0 158700.0 137300.0 159899.99999999997 ; + RECT 136500.0 152500.0 137300.0 150100.00000000003 ; + RECT 138300.0 158700.0 138899.99999999997 152500.0 ; + RECT 136500.0 152500.0 137300.0 151700.0 ; + RECT 138100.0 152500.0 138899.99999999997 151700.0 ; + RECT 138100.0 152500.0 138899.99999999997 151700.0 ; + RECT 136500.0 152500.0 137300.0 151700.0 ; + RECT 136500.0 158700.0 137300.0 157899.99999999997 ; + RECT 138100.0 158700.0 138899.99999999997 157899.99999999997 ; + RECT 138100.0 158700.0 138899.99999999997 157899.99999999997 ; + RECT 136500.0 158700.0 137300.0 157899.99999999997 ; + RECT 139700.0 152100.00000000003 140500.0 151300.0 ; + RECT 139700.0 158700.0 140500.0 157899.99999999997 ; + RECT 136900.0 155600.00000000003 137700.0 154800.0 ; + RECT 136900.0 155600.00000000003 137700.0 154800.0 ; + RECT 138600.0 155500.0 139200.0 154899.99999999997 ; + RECT 135300.0 150700.0 141700.0 150100.00000000003 ; + RECT 135300.0 159899.99999999997 141700.0 159300.0 ; + RECT 139700.0 167500.0 140500.0 168800.0 ; + RECT 139700.0 159600.00000000003 140500.0 160899.99999999997 ; + RECT 136500.0 160500.0 137300.0 159300.0 ; + RECT 136500.0 166700.0 137300.0 169100.00000000003 ; + RECT 138300.0 160500.0 138899.99999999997 166700.0 ; + RECT 136500.0 166700.0 137300.0 167500.0 ; + RECT 138100.0 166700.0 138899.99999999997 167500.0 ; + RECT 138100.0 166700.0 138899.99999999997 167500.0 ; + RECT 136500.0 166700.0 137300.0 167500.0 ; + RECT 136500.0 160500.0 137300.0 161300.0 ; + RECT 138100.0 160500.0 138899.99999999997 161300.0 ; + RECT 138100.0 160500.0 138899.99999999997 161300.0 ; + RECT 136500.0 160500.0 137300.0 161300.0 ; + RECT 139700.0 167100.00000000003 140500.0 167899.99999999997 ; + RECT 139700.0 160500.0 140500.0 161300.0 ; + RECT 136900.0 163600.00000000003 137700.0 164399.99999999997 ; + RECT 136900.0 163600.00000000003 137700.0 164399.99999999997 ; + RECT 138600.0 163700.0 139200.0 164300.0 ; + RECT 135300.0 168500.0 141700.0 169100.00000000003 ; + RECT 135300.0 159300.0 141700.0 159899.99999999997 ; + RECT 139700.0 170100.00000000003 140500.0 168800.0 ; + RECT 139700.0 178000.0 140500.0 176700.0 ; + RECT 136500.0 177100.00000000003 137300.0 178300.0 ; + RECT 136500.0 170899.99999999997 137300.0 168500.0 ; + RECT 138300.0 177100.00000000003 138899.99999999997 170899.99999999997 ; + RECT 136500.0 170899.99999999997 137300.0 170100.00000000003 ; + RECT 138100.0 170899.99999999997 138899.99999999997 170100.00000000003 ; + RECT 138100.0 170899.99999999997 138899.99999999997 170100.00000000003 ; + RECT 136500.0 170899.99999999997 137300.0 170100.00000000003 ; + RECT 136500.0 177100.00000000003 137300.0 176300.0 ; + RECT 138100.0 177100.00000000003 138899.99999999997 176300.0 ; + RECT 138100.0 177100.00000000003 138899.99999999997 176300.0 ; + RECT 136500.0 177100.00000000003 137300.0 176300.0 ; + RECT 139700.0 170500.0 140500.0 169700.0 ; + RECT 139700.0 177100.00000000003 140500.0 176300.0 ; + RECT 136900.0 174000.0 137700.0 173200.0 ; + RECT 136900.0 174000.0 137700.0 173200.0 ; + RECT 138600.0 173899.99999999997 139200.0 173300.0 ; + RECT 135300.0 169100.00000000003 141700.0 168500.0 ; + RECT 135300.0 178300.0 141700.0 177700.0 ; + RECT 139700.0 185899.99999999997 140500.0 187200.0 ; + RECT 139700.0 178000.0 140500.0 179300.0 ; + RECT 136500.0 178899.99999999997 137300.0 177700.0 ; + RECT 136500.0 185100.00000000003 137300.0 187500.0 ; + RECT 138300.0 178899.99999999997 138899.99999999997 185100.00000000003 ; + RECT 136500.0 185100.00000000003 137300.0 185899.99999999997 ; + RECT 138100.0 185100.00000000003 138899.99999999997 185899.99999999997 ; + RECT 138100.0 185100.00000000003 138899.99999999997 185899.99999999997 ; + RECT 136500.0 185100.00000000003 137300.0 185899.99999999997 ; + RECT 136500.0 178899.99999999997 137300.0 179700.0 ; + RECT 138100.0 178899.99999999997 138899.99999999997 179700.0 ; + RECT 138100.0 178899.99999999997 138899.99999999997 179700.0 ; + RECT 136500.0 178899.99999999997 137300.0 179700.0 ; + RECT 139700.0 185500.0 140500.0 186300.0 ; + RECT 139700.0 178899.99999999997 140500.0 179700.0 ; + RECT 136900.0 182000.0 137700.0 182800.0 ; + RECT 136900.0 182000.0 137700.0 182800.0 ; + RECT 138600.0 182100.00000000003 139200.0 182700.0 ; + RECT 135300.0 186899.99999999997 141700.0 187500.0 ; + RECT 135300.0 177700.0 141700.0 178300.0 ; + RECT 139700.0 188500.0 140500.0 187200.0 ; + RECT 139700.0 196400.00000000003 140500.0 195100.00000000003 ; + RECT 136500.0 195500.0 137300.0 196700.0 ; + RECT 136500.0 189300.0 137300.0 186900.00000000003 ; + RECT 138300.0 195500.0 138899.99999999997 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136500.0 234100.00000000003 137300.0 234900.00000000003 ; + RECT 139700.0 240700.0 140500.0 241500.0 ; + RECT 139700.0 234100.00000000003 140500.0 234900.00000000003 ; + RECT 136900.0 237200.0 137700.0 238000.0 ; + RECT 136900.0 237200.0 137700.0 238000.0 ; + RECT 138600.0 237300.0 139200.0 237900.00000000003 ; + RECT 135300.0 242100.00000000003 141700.0 242700.0 ; + RECT 135300.0 232900.00000000003 141700.0 233500.0 ; + RECT 139700.0 243700.0 140500.0 242400.00000000003 ; + RECT 139700.0 251600.00000000003 140500.0 250300.0 ; + RECT 136500.0 250700.0 137300.0 251900.00000000003 ; + RECT 136500.0 244500.0 137300.0 242100.00000000003 ; + RECT 138300.0 250700.0 138899.99999999997 244500.0 ; + RECT 136500.0 244500.0 137300.0 243700.0 ; + RECT 138100.0 244500.0 138899.99999999997 243700.0 ; + RECT 138100.0 244500.0 138899.99999999997 243700.0 ; + RECT 136500.0 244500.0 137300.0 243700.0 ; + RECT 136500.0 250700.0 137300.0 249900.00000000003 ; + RECT 138100.0 250700.0 138899.99999999997 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136500.0 252500.0 137300.0 253300.0 ; + RECT 138100.0 252500.0 138899.99999999997 253300.0 ; + RECT 138100.0 252500.0 138899.99999999997 253300.0 ; + RECT 136500.0 252500.0 137300.0 253300.0 ; + RECT 139700.0 259100.00000000003 140500.0 259900.00000000003 ; + RECT 139700.0 252500.0 140500.0 253300.0 ; + RECT 136900.0 255600.00000000003 137700.0 256400.00000000003 ; + RECT 136900.0 255600.00000000003 137700.0 256400.00000000003 ; + RECT 138600.0 255700.0 139200.0 256300.0 ; + RECT 135300.0 260500.0 141700.0 261100.00000000003 ; + RECT 135300.0 251300.0 141700.0 251900.00000000003 ; + RECT 139700.0 262100.00000000003 140500.0 260800.0 ; + RECT 139700.0 270000.0 140500.0 268700.0 ; + RECT 136500.0 269100.0 137300.0 270300.0 ; + RECT 136500.0 262900.00000000006 137300.0 260500.0 ; + RECT 138300.0 269100.0 138899.99999999997 262900.00000000006 ; + RECT 136500.0 262900.00000000006 137300.0 262100.00000000003 ; + RECT 138100.0 262900.00000000006 138899.99999999997 262100.00000000003 ; + RECT 138100.0 262900.00000000006 138899.99999999997 262100.00000000003 ; + RECT 136500.0 262900.00000000006 137300.0 262100.00000000003 ; + RECT 136500.0 269100.0 137300.0 268300.0 ; + RECT 138100.0 269100.0 138899.99999999997 268300.0 ; + RECT 138100.0 269100.0 138899.99999999997 268300.0 ; + RECT 136500.0 269100.0 137300.0 268300.0 ; + RECT 139700.0 262500.0 140500.0 261700.0 ; + RECT 139700.0 269100.0 140500.0 268300.0 ; + RECT 136900.0 266000.0 137700.0 265200.0 ; + RECT 136900.0 266000.0 137700.0 265200.0 ; + RECT 138600.0 265900.00000000006 139200.0 265300.0 ; + RECT 135300.0 261100.00000000003 141700.0 260500.0 ; + RECT 135300.0 270300.0 141700.0 269700.0 ; + RECT 112100.0 126800.00000000001 111300.00000000001 127600.00000000001 ; + RECT 112100.0 136400.0 111300.00000000001 137200.0 ; + RECT 112100.0 145200.0 111300.00000000001 146000.0 ; + RECT 112100.0 154800.0 111300.00000000001 155600.00000000003 ; + RECT 112100.0 163600.00000000003 111300.00000000001 164399.99999999997 ; + RECT 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262100.00000000003 ; + RECT 159100.0 262900.00000000006 159899.99999999997 262100.00000000003 ; + RECT 157500.0 262900.00000000006 158300.0 262100.00000000003 ; + RECT 155899.99999999997 268700.0 156700.0 267900.00000000006 ; + RECT 157500.0 268700.0 158300.0 267900.00000000006 ; + RECT 157500.0 268700.0 158300.0 267900.00000000006 ; + RECT 155899.99999999997 268700.0 156700.0 267900.00000000006 ; + RECT 157500.0 268700.0 158300.0 267900.00000000006 ; + RECT 159100.0 268700.0 159900.0 267900.00000000006 ; + RECT 159100.0 268700.0 159899.99999999997 267900.00000000006 ; + RECT 157500.0 268700.0 158300.0 267900.00000000006 ; + RECT 160700.0 262500.0 161500.0 261700.0 ; + RECT 160700.0 269100.0 161500.0 268300.0 ; + RECT 159100.0 267000.0 158300.0 266200.0 ; + RECT 157100.0 265600.0 156300.0 264800.0 ; + RECT 157500.0 262900.00000000006 158300.0 262100.00000000003 ; + RECT 159100.0 268700.0 159899.99999999997 267900.00000000006 ; + RECT 159899.99999999997 265600.0 159100.0 264800.0 ; + RECT 156300.0 265600.0 157100.0 264800.0 ; + RECT 158300.0 267000.0 159100.0 266200.0 ; + RECT 159100.0 265600.0 159899.99999999997 264800.0 ; + RECT 154700.0 261100.00000000003 164300.0 260500.0 ; + RECT 154700.0 270300.0 164300.0 269700.0 ; + RECT 168700.0 262100.00000000003 169500.0 260800.0 ; + RECT 168700.0 270000.0 169500.0 268700.0 ; + RECT 165500.0 269100.0 166300.0 270300.0 ; + RECT 165500.0 262900.00000000006 166300.0 260500.0 ; + RECT 167300.0 269100.0 167900.0 262900.00000000006 ; + RECT 165500.0 262900.00000000006 166300.0 262100.00000000003 ; + RECT 167100.00000000003 262900.00000000006 167900.0 262100.00000000003 ; + RECT 167100.00000000003 262900.00000000006 167900.0 262100.00000000003 ; + RECT 165500.0 262900.00000000006 166300.0 262100.00000000003 ; + RECT 165500.0 269100.0 166300.0 268300.0 ; + RECT 167100.00000000003 269100.0 167900.0 268300.0 ; + RECT 167100.00000000003 269100.0 167900.0 268300.0 ; + RECT 165500.0 269100.0 166300.0 268300.0 ; + RECT 168700.0 262500.0 169500.0 261700.0 ; + RECT 168700.0 269100.0 169500.0 268300.0 ; + RECT 165900.0 266000.0 166700.0 265200.0 ; + RECT 165900.0 266000.0 166700.0 265200.0 ; + RECT 167600.00000000003 265900.00000000006 168200.0 265300.0 ; + RECT 164300.0 261100.00000000003 170700.0 260500.0 ; + RECT 164300.0 270300.0 170700.0 269700.0 ; + RECT 145800.0 126800.00000000001 146600.0 127600.00000000001 ; + RECT 147100.0 125200.0 147899.99999999997 126000.0 ; + RECT 158300.0 125800.00000000001 157500.0 126600.00000000001 ; + RECT 145800.0 136400.0 146600.0 137200.0 ; + RECT 147100.0 138000.0 147899.99999999997 138800.0 ; + RECT 158300.0 137400.0 157500.0 138200.0 ; + RECT 145800.0 145200.0 146600.0 146000.0 ; + RECT 147100.0 143600.00000000003 147899.99999999997 144400.0 ; + RECT 158300.0 144200.0 157500.0 145000.0 ; + RECT 145800.0 154800.0 146600.0 155600.00000000003 ; + RECT 147100.0 156399.99999999997 147899.99999999997 157200.0 ; + RECT 158300.0 155800.0 157500.0 156600.00000000003 ; + RECT 145800.0 163600.00000000003 146600.0 164399.99999999997 ; + RECT 147100.0 162000.0 147899.99999999997 162800.0 ; + RECT 158300.0 162600.00000000003 157500.0 163399.99999999997 ; + RECT 145800.0 173200.0 146600.0 174000.0 ; + RECT 147100.0 174800.0 147899.99999999997 175600.00000000003 ; + RECT 158300.0 174200.0 157500.0 175000.0 ; + RECT 145800.0 182000.0 146600.0 182800.0 ; + RECT 147100.0 180399.99999999997 147899.99999999997 181200.0 ; + RECT 158300.0 181000.0 157500.0 181800.0 ; + RECT 145800.0 191600.00000000003 146600.0 192399.99999999997 ; + RECT 147100.0 193200.0 147899.99999999997 194000.0 ; + RECT 158300.0 192600.00000000003 157500.0 193399.99999999997 ; + RECT 145800.0 200400.00000000003 146600.0 201200.0 ; + RECT 147100.0 198800.0 147899.99999999997 199600.00000000003 ; + RECT 158300.0 199400.00000000003 157500.0 200200.0 ; + RECT 145800.0 210000.0 146600.0 210800.0 ; + RECT 147100.0 211600.00000000003 147899.99999999997 212400.00000000003 ; + RECT 158300.0 211000.0 157500.0 211800.0 ; + RECT 145800.0 218800.0 146600.0 219600.00000000003 ; + RECT 147100.0 217200.0 147899.99999999997 218000.0 ; + RECT 158300.0 217800.0 157500.0 218600.00000000003 ; + RECT 145800.0 228400.00000000003 146600.0 229200.0 ; + RECT 147100.0 230000.0 147899.99999999997 230800.0 ; + RECT 158300.0 229400.00000000003 157500.0 230200.0 ; + RECT 145800.0 237200.0 146600.0 238000.0 ; + RECT 147100.0 235600.00000000003 147899.99999999997 236400.00000000003 ; + RECT 158300.0 236200.0 157500.0 237000.0 ; + RECT 145800.0 246800.0 146600.0 247600.00000000003 ; + RECT 147100.0 248400.00000000003 147899.99999999997 249200.0 ; + RECT 158300.0 247800.0 157500.0 248600.00000000003 ; + RECT 145800.0 255600.00000000003 146600.0 256400.00000000003 ; + RECT 147100.0 254000.0 147899.99999999997 254800.0 ; + RECT 158300.0 254600.00000000003 157500.0 255400.00000000003 ; + RECT 145800.0 265200.0 146600.0 266000.0 ; + RECT 147100.0 266800.0 147899.99999999997 267600.0 ; + RECT 158300.0 266200.0 157500.0 267000.0 ; + RECT 155100.0 131600.00000000003 154300.0 132400.0 ; + RECT 164700.0 131600.00000000003 163899.99999999997 132400.0 ; + RECT 155100.0 122400.0 154300.0 123200.0 ; + RECT 164700.0 122400.0 163899.99999999997 123200.0 ; + RECT 155100.0 131600.00000000003 154300.0 132400.0 ; + RECT 164700.0 131600.00000000003 163899.99999999997 132400.0 ; + RECT 155100.0 140800.0 154300.0 141600.00000000003 ; + RECT 164700.0 140800.0 163899.99999999997 141600.00000000003 ; + RECT 155100.0 150000.0 154300.0 150800.0 ; + RECT 164700.0 150000.0 163899.99999999997 150800.0 ; + RECT 155100.0 140800.0 154300.0 141600.00000000003 ; + RECT 164700.0 140800.0 163899.99999999997 141600.00000000003 ; + RECT 155100.0 150000.0 154300.0 150800.0 ; + RECT 164700.0 150000.0 163899.99999999997 150800.0 ; + RECT 155100.0 159200.0 154300.0 160000.0 ; + RECT 164700.0 159200.0 163899.99999999997 160000.0 ; + RECT 155100.0 168399.99999999997 154300.0 169200.0 ; + RECT 164700.0 168399.99999999997 163899.99999999997 169200.0 ; + RECT 155100.0 159200.0 154300.0 160000.0 ; + RECT 164700.0 159200.0 163899.99999999997 160000.0 ; + RECT 155100.0 168399.99999999997 154300.0 169200.0 ; + RECT 164700.0 168399.99999999997 163899.99999999997 169200.0 ; + RECT 155100.0 177600.00000000003 154300.0 178399.99999999997 ; + RECT 164700.0 177600.00000000003 163899.99999999997 178399.99999999997 ; + RECT 155100.0 186800.0 154300.0 187600.00000000003 ; + RECT 164700.0 186800.0 163899.99999999997 187600.00000000003 ; + RECT 155100.0 177600.00000000003 154300.0 178399.99999999997 ; + RECT 164700.0 177600.00000000003 163899.99999999997 178399.99999999997 ; + RECT 155100.0 186800.0 154300.0 187600.00000000003 ; + RECT 164700.0 186800.0 163899.99999999997 187600.00000000003 ; + RECT 155100.0 196000.0 154300.0 196800.0 ; + RECT 164700.0 196000.0 163899.99999999997 196800.0 ; + RECT 155100.0 205200.0 154300.0 206000.0 ; + RECT 164700.0 205200.0 163899.99999999997 206000.0 ; + RECT 155100.0 196000.0 154300.0 196800.0 ; + RECT 164700.0 196000.0 163899.99999999997 196800.0 ; + RECT 155100.0 205200.0 154300.0 206000.0 ; + RECT 164700.0 205200.0 163899.99999999997 206000.0 ; + RECT 155100.0 214400.00000000003 154300.0 215200.0 ; + RECT 164700.0 214400.00000000003 163899.99999999997 215200.0 ; + RECT 155100.0 223600.00000000003 154300.0 224400.00000000003 ; + RECT 164700.0 223600.00000000003 163899.99999999997 224400.00000000003 ; + RECT 155100.0 214400.00000000003 154300.0 215200.0 ; + RECT 164700.0 214400.00000000003 163899.99999999997 215200.0 ; + RECT 155100.0 223600.00000000003 154300.0 224400.00000000003 ; + RECT 164700.0 223600.00000000003 163899.99999999997 224400.00000000003 ; + RECT 155100.0 232800.0 154300.0 233600.00000000003 ; + RECT 164700.0 232800.0 163899.99999999997 233600.00000000003 ; + RECT 155100.0 242000.0 154300.0 242800.0 ; + RECT 164700.0 242000.0 163899.99999999997 242800.0 ; + RECT 155100.0 232800.0 154300.0 233600.00000000003 ; + RECT 164700.0 232800.0 163899.99999999997 233600.00000000003 ; + RECT 155100.0 242000.0 154300.0 242800.0 ; + RECT 164700.0 242000.0 163899.99999999997 242800.0 ; + RECT 155100.0 251200.0 154300.0 252000.0 ; + RECT 164700.0 251200.0 163899.99999999997 252000.0 ; + RECT 155100.0 260399.99999999997 154300.0 261200.0 ; + RECT 164700.0 260399.99999999997 163899.99999999997 261200.0 ; + RECT 155100.0 251200.0 154300.0 252000.0 ; + RECT 164700.0 251200.0 163899.99999999997 252000.0 ; + RECT 155100.0 260399.99999999997 154300.0 261200.0 ; + RECT 164700.0 260399.99999999997 163899.99999999997 261200.0 ; + RECT 155100.0 269600.0 154300.0 270400.00000000006 ; + RECT 164700.0 269600.0 163899.99999999997 270400.00000000006 ; + RECT 144100.0 125300.00000000001 147500.0 125900.0 ; + RECT 144100.0 138100.00000000003 147500.0 138700.0 ; + RECT 144100.0 143700.0 147500.0 144300.0 ; + RECT 144100.0 156500.0 147500.0 157100.00000000003 ; + RECT 144100.0 162100.00000000003 147500.0 162700.0 ; + RECT 144100.0 174899.99999999997 147500.0 175500.0 ; + RECT 144100.0 180500.0 147500.0 181100.00000000003 ; + RECT 144100.0 193300.0 147500.0 193900.00000000003 ; + RECT 144100.0 198900.00000000003 147500.0 199500.0 ; + RECT 144100.0 211700.0 147500.0 212300.0 ; + RECT 144100.0 217300.0 147500.0 217900.00000000003 ; + RECT 144100.0 230100.00000000003 147500.0 230700.0 ; + RECT 144100.0 235700.0 147500.0 236300.0 ; + RECT 144100.0 248500.0 147500.0 249100.00000000003 ; + RECT 144100.0 254100.00000000003 147500.0 254700.0 ; + RECT 144100.0 266900.0 147500.0 267500.0 ; + RECT 167600.0 126900.0 168200.0 127500.0 ; + RECT 167600.0 136500.0 168200.0 137100.00000000003 ; + RECT 167600.0 145300.0 168200.0 145900.0 ; + RECT 167600.0 154899.99999999997 168200.0 155500.0 ; + RECT 167600.0 163700.0 168200.0 164300.0 ; + RECT 167600.0 173300.0 168200.0 173899.99999999997 ; + RECT 167600.0 182100.00000000003 168200.0 182700.0 ; + RECT 167600.0 191700.0 168200.0 192300.0 ; + RECT 167600.0 200500.0 168200.0 201100.00000000003 ; + RECT 167600.0 210100.00000000003 168200.0 210700.0 ; + RECT 167600.0 218900.00000000003 168200.0 219500.0 ; + RECT 167600.0 228500.0 168200.0 229100.00000000003 ; + RECT 167600.0 237300.0 168200.0 237900.00000000003 ; + RECT 167600.0 246900.00000000003 168200.0 247500.0 ; + RECT 167600.0 255700.0 168200.0 256300.0 ; + RECT 167600.0 265300.0 168200.0 265900.0 ; + RECT 174500.0 108700.0 173700.00000000003 109500.0 ; + RECT 175900.0 28900.000000000007 175100.00000000003 29700.000000000007 ; + RECT 177300.0 98500.0 176500.0 99300.0 ; + RECT 146600.00000000003 271000.0 145800.0 271800.0 ; + RECT 173100.00000000003 271000.0 172300.0 271800.0 ; + RECT 25400.000000000004 28900.000000000004 32700.000000000004 29500.0 ; + RECT 25400.000000000004 49700.0 31300.000000000004 50300.00000000001 ; + RECT 3100.0 62100.0 28500.000000000004 62700.0 ; + RECT 29900.000000000004 65000.0 37600.0 65600.00000000001 ; + RECT 32700.000000000004 63700.0 39200.0 64300.000000000015 ; + RECT 31300.0 62400.00000000001 40800.0 63000.00000000001 ; + RECT 47300.00000000001 65000.0 47900.00000000001 65600.00000000001 ; + RECT 41600.0 65000.0 47600.0 65600.00000000001 ; + RECT 47300.00000000001 65300.000000000015 47900.00000000001 69400.0 ; + RECT 48900.00000000001 68500.0 49500.00000000001 69100.00000000001 ; + RECT 48900.00000000001 68800.00000000001 49500.00000000001 69400.0 ; + RECT 49200.0 68500.0 54000.0 69100.00000000001 ; + RECT 55600.0 68500.0 60400.00000000001 69100.00000000001 ; + RECT 29900.000000000004 94500.0 37200.0 95100.0 ; + RECT 32700.000000000004 95900.0 39200.0 96500.0 ; + RECT 46500.0 94500.0 47100.0 95100.0 ; + RECT 40000.0 94500.0 46800.0 95100.0 ; + RECT 46500.0 89800.00000000001 47100.0 94800.00000000001 ; + RECT 9200.000000000002 108500.0 36800.00000000001 109100.0 ; + RECT 38800.00000000001 108500.0 43600.00000000001 109100.0 ; + RECT 54400.00000000001 39300.00000000001 69600.00000000001 39900.00000000001 ; + RECT 54400.00000000001 59300.00000000001 69600.00000000001 59900.00000000001 ; + RECT 54400.00000000001 19300.0 69600.00000000001 19900.000000000004 ; + RECT 51200.0 79300.00000000001 69600.00000000001 79900.0 ; + RECT 51200.0 99300.00000000001 69600.00000000001 99900.0 ; + RECT 52800.00000000001 119300.00000000001 69600.00000000001 119900.0 ; + RECT 52800.00000000001 99300.00000000001 69600.00000000001 99900.0 ; + RECT 0.0 19600.0 21800.0 39600.0 ; + RECT 26200.000000000004 38300.0 27000.0 39600.0 ; + RECT 26200.000000000004 19600.0 27000.0 20900.000000000004 ; + RECT 23000.0 20900.000000000004 23800.0 19300.0 ; + RECT 23000.0 36700.0 23800.0 39900.00000000001 ; + RECT 24800.0 20900.000000000004 25400.000000000004 36700.0 ; + RECT 23000.0 36700.0 23800.0 37500.0 ; + RECT 24600.0 36700.0 25400.000000000004 37500.0 ; + RECT 24600.0 36700.0 25400.000000000004 37500.0 ; + RECT 23000.0 36700.0 23800.0 37500.0 ; + RECT 23000.0 20900.000000000004 23800.0 21700.000000000004 ; + RECT 24600.0 20900.000000000004 25400.000000000004 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58300.00000000001 ; + RECT 23000.0 58300.00000000001 23800.0 59900.0 ; + RECT 23000.0 42500.0 23800.0 39300.0 ; + RECT 24800.0 58300.00000000001 25400.000000000004 42500.0 ; + RECT 23000.0 42500.0 23800.0 41700.0 ; + RECT 24600.0 42500.0 25400.000000000004 41700.0 ; + RECT 24600.0 42500.0 25400.000000000004 41700.0 ; + RECT 23000.0 42500.0 23800.0 41700.0 ; + RECT 23000.0 58300.00000000001 23800.0 57500.0 ; + RECT 24600.0 58300.00000000001 25400.000000000004 57500.0 ; + RECT 24600.0 58300.00000000001 25400.000000000004 57500.0 ; + RECT 23000.0 58300.00000000001 23800.0 57500.0 ; + RECT 26200.000000000004 41300.0 27000.0 40500.0 ; + RECT 26200.000000000004 58700.0 27000.0 57900.0 ; + RECT 23400.000000000004 50400.0 24200.000000000004 49600.0 ; + RECT 23400.000000000004 50400.0 24200.000000000004 49600.0 ; + RECT 25100.0 50300.0 25700.000000000004 49700.0 ; + RECT 21800.0 39900.0 28200.000000000004 39300.0 ; + RECT 21800.0 59900.0 28200.000000000004 59300.00000000001 ; + RECT 23400.000000000004 50400.0 24200.000000000004 49600.0 ; + RECT 25000.0 50400.0 25800.0 49600.0 ; + RECT 0.0 40200.0 28200.000000000004 39000.0 ; + RECT 0.0 60200.0 28200.000000000004 59000.0 ; + RECT 400.0 39200.0 -400.0 40000.0 ; + RECT 400.0 19200.000000000004 -400.0 20000.0 ; + RECT 400.0 39200.0 -400.0 40000.0 ; + RECT 400.0 59200.0 -400.0 60000.0 ; + RECT 38500.0 28900.000000000004 39100.0 29500.0 ; + RECT 38500.0 29200.000000000004 39100.0 29400.000000000004 ; + RECT 38800.00000000001 28900.000000000004 43600.0 29500.0 ; + RECT 44900.00000000001 28500.0 45500.0 29100.0 ; + RECT 44900.00000000001 28800.000000000004 45500.0 29200.000000000004 ; + RECT 45200.0 28500.0 50000.0 29100.0 ; + RECT 38800.00000000001 50100.0 50000.0 50700.0 ; + RECT 39600.0 38300.0 40400.00000000001 39600.0 ; + RECT 39600.0 19600.0 40400.00000000001 20900.000000000004 ; + RECT 36400.00000000001 20500.0 37200.0 19300.0 ; + RECT 36400.00000000001 37500.0 37200.0 39900.00000000001 ; + RECT 38200.0 20500.0 38800.00000000001 37500.0 ; + RECT 36400.00000000001 37500.0 37200.0 38300.0 ; + RECT 38000.0 37500.0 38800.00000000001 38300.0 ; + RECT 38000.0 37500.0 38800.00000000001 38300.0 ; + RECT 36400.00000000001 37500.0 37200.0 38300.0 ; + RECT 36400.00000000001 20500.0 37200.0 21300.0 ; + RECT 38000.0 20500.0 38800.00000000001 21300.0 ; + RECT 38000.0 20500.0 38800.00000000001 21300.0 ; + RECT 36400.00000000001 20500.0 37200.0 21300.0 ; + RECT 39600.0 37900.00000000001 40400.00000000001 38700.0 ; + RECT 39600.0 20500.0 40400.00000000001 21300.0 ; + RECT 36800.00000000001 29000.0 37600.0 29800.000000000004 ; + RECT 36800.00000000001 29000.0 37600.0 29800.000000000004 ; + RECT 38500.0 29100.0 39100.0 29700.000000000004 ; + RECT 35200.0 39300.00000000001 41600.0 39900.00000000001 ; + RECT 35200.0 19300.0 41600.0 19900.000000000004 ; + RECT 46000.0 38300.0 46800.00000000001 39600.0 ; + RECT 46000.0 19600.0 46800.00000000001 20900.000000000004 ; + RECT 42800.00000000001 20900.000000000004 43600.0 19300.0 ; + RECT 42800.00000000001 36700.0 43600.0 39900.00000000001 ; + RECT 44600.0 20900.000000000004 45200.0 36700.0 ; + RECT 42800.00000000001 36700.0 43600.0 37500.0 ; + RECT 44400.00000000001 36700.0 45200.0 37500.0 ; + RECT 44400.00000000001 36700.0 45200.0 37500.0 ; + RECT 42800.00000000001 36700.0 43600.0 37500.0 ; + RECT 42800.00000000001 20900.000000000004 43600.0 21700.000000000004 ; + RECT 44400.00000000001 20900.000000000004 45200.0 21700.000000000004 ; + RECT 44400.00000000001 20900.000000000004 45200.0 21700.000000000004 ; + RECT 42800.00000000001 20900.000000000004 43600.0 21700.000000000004 ; + RECT 46000.0 37900.00000000001 46800.00000000001 38700.0 ; + RECT 46000.0 20500.0 46800.00000000001 21300.0 ; + RECT 43200.0 28800.000000000004 44000.0 29600.0 ; + RECT 43200.0 28800.000000000004 44000.0 29600.0 ; + RECT 44900.00000000001 28900.000000000004 45500.0 29500.0 ; + RECT 41600.0 39300.00000000001 48000.0 39900.00000000001 ; + RECT 41600.0 19300.0 48000.0 19900.000000000004 ; + RECT 52400.00000000001 38300.0 53200.0 39600.0 ; + RECT 52400.00000000001 19600.0 53200.0 20900.000000000004 ; + RECT 49200.0 21700.000000000004 50000.0 19300.0 ; + RECT 49200.0 35100.0 50000.0 39900.00000000001 ; + RECT 51000.0 21700.000000000004 51600.00000000001 35100.0 ; + RECT 49200.0 35100.0 50000.0 35900.00000000001 ; + RECT 50800.00000000001 35100.0 51600.00000000001 35900.00000000001 ; + RECT 50800.00000000001 35100.0 51600.00000000001 35900.00000000001 ; + RECT 49200.0 35100.0 50000.0 35900.00000000001 ; + RECT 49200.0 21700.000000000004 50000.0 22500.0 ; + RECT 50800.00000000001 21700.000000000004 51600.00000000001 22500.0 ; + RECT 50800.00000000001 21700.000000000004 51600.00000000001 22500.0 ; + RECT 49200.0 21700.000000000004 50000.0 22500.0 ; + RECT 52400.00000000001 37900.00000000001 53200.0 38700.0 ; + RECT 52400.00000000001 20500.0 53200.0 21300.0 ; + RECT 49600.0 28400.000000000004 50400.00000000001 29200.000000000004 ; + RECT 49600.0 28400.000000000004 50400.00000000001 29200.000000000004 ; + RECT 51300.00000000001 28500.0 51900.00000000001 29100.0 ; + RECT 48000.0 39300.00000000001 54400.00000000001 39900.00000000001 ; + RECT 48000.0 19300.0 54400.00000000001 19900.000000000004 ; + RECT 52400.00000000001 40900.00000000001 53200.0 39600.0 ; + RECT 52400.00000000001 59600.0 53200.0 58300.00000000001 ; + RECT 49200.0 57500.0 50000.0 59900.0 ; + RECT 49200.0 44100.0 50000.0 39300.0 ; + RECT 51000.0 57500.0 51600.00000000001 44100.0 ; + RECT 49200.0 44100.0 50000.0 43300.0 ; + RECT 50800.00000000001 44100.0 51600.00000000001 43300.0 ; + RECT 50800.00000000001 44100.0 51600.00000000001 43300.0 ; + RECT 49200.0 44100.0 50000.0 43300.0 ; + RECT 49200.0 57500.0 50000.0 56700.0 ; + RECT 50800.00000000001 57500.0 51600.00000000001 56700.0 ; + RECT 50800.00000000001 57500.0 51600.00000000001 56700.0 ; + RECT 49200.0 57500.0 50000.0 56700.0 ; + RECT 52400.00000000001 41300.0 53200.0 40500.0 ; + RECT 52400.00000000001 58700.0 53200.0 57900.0 ; + RECT 49600.0 50800.0 50400.00000000001 50000.0 ; + RECT 49600.0 50800.0 50400.00000000001 50000.0 ; + RECT 51300.00000000001 50700.0 51900.00000000001 50100.0 ; + RECT 48000.0 39900.0 54400.00000000001 39300.0 ; + RECT 48000.0 59900.0 54400.00000000001 59300.00000000001 ; + RECT 39200.0 50000.0 38400.00000000001 50800.00000000001 ; + RECT 38400.00000000001 29000.0 39200.0 29800.000000000004 ; + RECT 51200.0 50000.0 52000.0 50800.00000000001 ; + RECT 51200.0 28400.000000000004 52000.0 29200.000000000004 ; + RECT 36800.00000000001 29000.0 37600.0 29800.000000000004 ; + RECT 35200.0 39300.00000000001 54400.00000000001 39900.00000000001 ; + RECT 35200.0 59300.00000000001 54400.00000000001 59900.00000000001 ; + RECT 35200.0 19300.0 54400.00000000001 19900.000000000004 ; + RECT 36400.00000000001 60900.0 37200.0 59300.00000000001 ; + RECT 36400.00000000001 77500.0 37200.0 79900.0 ; + RECT 39600.0 77500.0 40400.00000000001 79900.0 ; + RECT 42800.00000000001 78300.00000000001 43600.0 79600.0 ; + RECT 42800.00000000001 59600.0 43600.0 60900.0 ; + RECT 36400.00000000001 77500.0 37200.0 78300.00000000001 ; + RECT 38000.0 77500.0 38800.00000000001 78300.00000000001 ; + RECT 38000.0 77500.0 38800.00000000001 78300.00000000001 ; + RECT 36400.00000000001 77500.0 37200.0 78300.00000000001 ; + RECT 38000.0 77500.0 38800.00000000001 78300.00000000001 ; + RECT 39600.0 77500.0 40400.00000000001 78300.00000000001 ; + RECT 39600.0 77500.0 40400.00000000001 78300.00000000001 ; + RECT 38000.0 77500.0 38800.00000000001 78300.00000000001 ; + RECT 39600.0 77500.0 40400.00000000001 78300.00000000001 ; + RECT 41200.0 77500.0 42000.0 78300.00000000001 ; + RECT 41200.0 77500.0 42000.0 78300.00000000001 ; + RECT 39600.0 77500.0 40400.00000000001 78300.00000000001 ; + RECT 36400.00000000001 60900.0 37200.0 61700.0 ; + RECT 38000.0 60900.0 38800.00000000001 61700.0 ; + RECT 38000.0 60900.0 38800.00000000001 61700.0 ; + RECT 36400.00000000001 60900.0 37200.0 61700.0 ; + RECT 38000.0 60900.0 38800.00000000001 61700.0 ; + RECT 39600.0 60900.0 40400.00000000001 61700.0 ; + RECT 39600.0 60900.0 40400.00000000001 61700.0 ; + RECT 38000.0 60900.0 38800.00000000001 61700.0 ; + RECT 39600.0 60900.0 40400.00000000001 61700.0 ; + RECT 41200.0 60900.0 42000.0 61700.0 ; + RECT 41200.0 60900.0 42000.0 61700.0 ; + RECT 39600.0 60900.0 40400.00000000001 61700.0 ; + RECT 42800.00000000001 77900.0 43600.0 78700.0 ; + RECT 42800.00000000001 60500.0 43600.0 61300.00000000001 ; + RECT 41200.0 62300.00000000001 40400.00000000001 63100.0 ; + RECT 39600.0 63600.0 38800.00000000001 64400.00000000001 ; + RECT 38000.0 64900.00000000001 37200.0 65700.0 ; + RECT 38000.0 77500.0 38800.00000000001 78300.00000000001 ; + RECT 41200.0 77500.0 42000.0 78300.00000000001 ; + RECT 41200.0 60900.0 42000.0 61700.0 ; + RECT 41200.0 64900.00000000001 42000.0 65700.0 ; + RECT 37200.0 64900.00000000001 38000.0 65700.0 ; + RECT 38800.00000000001 63600.0 39600.0 64400.00000000001 ; + RECT 40400.00000000001 62300.00000000001 41200.0 63100.0 ; + RECT 41200.0 64900.00000000001 42000.0 65700.0 ; + RECT 35200.0 79300.00000000001 45600.0 79900.0 ; + RECT 35200.0 59300.00000000001 45600.0 59900.0 ; + RECT 50000.0 78300.00000000001 50800.00000000001 79600.0 ; + RECT 50000.0 59600.0 50800.00000000001 60900.0 ; + RECT 46800.00000000001 60500.0 47600.0 59300.00000000001 ; + RECT 46800.00000000001 77500.0 47600.0 79900.0 ; + RECT 48600.0 60500.0 49200.0 77500.0 ; + RECT 46800.00000000001 77500.0 47600.0 78300.00000000001 ; + RECT 48400.0 77500.0 49200.0 78300.00000000001 ; + RECT 48400.0 77500.0 49200.0 78300.00000000001 ; + RECT 46800.00000000001 77500.0 47600.0 78300.00000000001 ; + RECT 46800.00000000001 60500.0 47600.0 61300.00000000001 ; + RECT 48400.0 60500.0 49200.0 61300.00000000001 ; + RECT 48400.0 60500.0 49200.0 61300.00000000001 ; + RECT 46800.00000000001 60500.0 47600.0 61300.00000000001 ; + RECT 50000.0 77900.0 50800.00000000001 78700.0 ; + RECT 50000.0 60500.0 50800.00000000001 61300.00000000001 ; + RECT 47200.0 69000.0 48000.0 69800.00000000001 ; + RECT 47200.0 69000.0 48000.0 69800.00000000001 ; + RECT 48900.0 69100.0 49500.0 69700.0 ; + RECT 45600.0 79300.00000000001 52000.0 79900.0 ; + RECT 45600.0 59300.00000000001 52000.0 59900.0 ; + RECT 56400.0 78300.00000000001 57200.0 79600.0 ; + RECT 56400.0 59600.0 57200.0 60900.0 ; + RECT 53200.0 61700.0 54000.0 59300.00000000001 ; + RECT 53200.0 75100.0 54000.0 79900.0 ; + RECT 55000.0 61700.0 55600.0 75100.0 ; + RECT 53200.0 75100.0 54000.0 75900.0 ; + RECT 54800.0 75100.0 55600.0 75900.0 ; + RECT 54800.0 75100.0 55600.0 75900.0 ; + RECT 53200.0 75100.0 54000.0 75900.0 ; + RECT 53200.0 61700.0 54000.0 62500.0 ; + RECT 54800.0 61700.0 55600.0 62500.0 ; + RECT 54800.0 61700.0 55600.0 62500.0 ; + RECT 53200.0 61700.0 54000.0 62500.0 ; + RECT 56400.0 77900.0 57200.0 78700.0 ; + RECT 56400.0 60500.0 57200.0 61300.00000000001 ; + RECT 53600.0 68400.0 54400.0 69200.0 ; + RECT 53600.0 68400.0 54400.0 69200.0 ; + RECT 55300.0 68500.0 55900.0 69100.0 ; + RECT 52000.0 79300.00000000001 58400.0 79900.0 ; + RECT 52000.0 59300.00000000001 58400.0 59900.0 ; + RECT 67600.00000000001 78300.00000000001 68400.0 79600.0 ; + RECT 67600.00000000001 59600.0 68400.0 60900.0 ; + RECT 59700.0 60500.0 66700.0 59300.00000000001 ; + RECT 59700.0 76500.0 66700.0 79900.0 ; + RECT 64500.0 63100.0 65100.00000000001 73900.0 ; + RECT 59700.0 75500.0 60300.00000000001 76800.00000000001 ; + RECT 62900.00000000001 75500.0 63500.00000000001 76800.00000000001 ; + RECT 66100.00000000001 75500.0 66700.0 76800.00000000001 ; + RECT 61300.00000000001 74200.0 61900.00000000001 75500.0 ; + RECT 64500.0 74200.0 65100.00000000001 75500.0 ; + RECT 59600.00000000001 75100.0 60400.00000000001 75900.0 ; + RECT 62800.00000000001 75100.0 63600.00000000001 75900.0 ; + RECT 66000.0 75100.0 66800.00000000001 75900.0 ; + RECT 61200.0 75100.0 62000.00000000001 75900.0 ; + RECT 64400.00000000001 75100.0 65200.0 75900.0 ; + RECT 61300.00000000001 73900.0 65100.00000000001 74500.0 ; + RECT 59700.0 76500.0 66700.0 77100.0 ; + RECT 59700.0 60800.00000000001 60300.00000000001 62100.0 ; + RECT 62900.00000000001 60800.00000000001 63500.00000000001 62100.0 ; + RECT 66100.00000000001 60800.00000000001 66700.0 62100.0 ; + RECT 61300.00000000001 62100.0 61900.00000000001 63400.0 ; + RECT 64500.0 62100.0 65100.00000000001 63400.0 ; + RECT 59600.00000000001 61700.0 60400.00000000001 62500.0 ; + RECT 62800.00000000001 61700.0 63600.00000000001 62500.0 ; + RECT 66000.0 61700.0 66800.00000000001 62500.0 ; + RECT 61200.0 61700.0 62000.00000000001 62500.0 ; + RECT 64400.00000000001 61700.0 65200.0 62500.0 ; + RECT 61300.00000000001 63100.0 65100.00000000001 63700.0 ; + RECT 59700.0 60500.0 66700.0 61100.0 ; + RECT 67600.00000000001 77900.0 68400.0 78700.0 ; + RECT 67600.00000000001 60500.0 68400.0 61300.00000000001 ; + RECT 60000.00000000001 68400.0 60800.00000000001 69200.0 ; + RECT 60000.00000000001 68400.0 60800.00000000001 69200.0 ; + RECT 64800.000000000015 68500.0 65400.00000000001 69100.0 ; + RECT 58400.00000000001 79300.00000000001 69600.00000000001 79900.0 ; + RECT 58400.00000000001 59300.00000000001 69600.00000000001 59900.0 ; + RECT 36400.00000000001 98300.00000000001 37200.0 99900.0 ; + RECT 36400.00000000001 81699.99999999999 37200.0 79300.0 ; + RECT 39600.0 81699.99999999999 40400.00000000001 79300.0 ; + RECT 41200.0 80900.0 42000.0 79600.0 ; + RECT 41200.0 99600.0 42000.0 98300.00000000001 ; + RECT 36400.00000000001 81700.0 37200.0 80900.0 ; + RECT 38000.0 81700.0 38800.00000000001 80900.0 ; + RECT 38000.0 81700.0 38800.00000000001 80900.0 ; + RECT 36400.00000000001 81700.0 37200.0 80900.0 ; + RECT 38000.0 81700.0 38800.00000000001 80900.0 ; + RECT 39600.0 81700.0 40400.00000000001 80900.0 ; + RECT 39600.0 81700.0 40400.00000000001 80900.0 ; + RECT 38000.0 81700.0 38800.00000000001 80900.0 ; + RECT 36400.00000000001 98300.00000000001 37200.0 97500.0 ; + RECT 38000.0 98300.00000000001 38800.00000000001 97500.0 ; + RECT 38000.0 98300.00000000001 38800.00000000001 97500.0 ; + RECT 36400.00000000001 98300.00000000001 37200.0 97500.0 ; + RECT 38000.0 98300.00000000001 38800.00000000001 97500.0 ; + RECT 39600.0 98300.00000000001 40400.00000000001 97500.0 ; + RECT 39600.0 98300.00000000001 40400.00000000001 97500.0 ; + RECT 38000.0 98300.00000000001 38800.00000000001 97500.0 ; + RECT 41200.0 81300.00000000001 42000.0 80500.0 ; + RECT 41200.0 98699.99999999999 42000.0 97900.0 ; + RECT 39600.0 96600.0 38800.00000000001 95800.00000000001 ; + RECT 37600.0 95199.99999999999 36800.00000000001 94400.0 ; + RECT 38000.0 81699.99999999999 38800.00000000001 80900.0 ; + RECT 39600.0 98300.00000000001 40400.00000000001 97500.0 ; + RECT 40400.00000000001 95199.99999999999 39600.0 94400.0 ; + RECT 36800.00000000001 95199.99999999999 37600.0 94400.0 ; + RECT 38800.00000000001 96600.0 39600.0 95800.00000000001 ; + RECT 39600.0 95199.99999999999 40400.00000000001 94400.0 ; + RECT 35200.0 79900.0 44800.00000000001 79300.00000000001 ; + RECT 35200.0 99900.0 44800.00000000001 99300.00000000001 ; + RECT 49200.0 80900.0 50000.00000000001 79600.0 ; + RECT 49200.0 99600.0 50000.00000000001 98300.00000000001 ; + RECT 46000.00000000001 98699.99999999999 46800.00000000001 99900.0 ; + RECT 46000.00000000001 81699.99999999999 46800.00000000001 79300.0 ; + RECT 47800.00000000001 98699.99999999999 48400.00000000001 81700.0 ; + RECT 46000.00000000001 81700.0 46800.00000000001 80900.0 ; + RECT 47600.0 81700.0 48400.00000000001 80900.0 ; + RECT 47600.0 81700.0 48400.00000000001 80900.0 ; + RECT 46000.00000000001 81700.0 46800.00000000001 80900.0 ; + RECT 46000.00000000001 98699.99999999999 46800.00000000001 97900.0 ; + RECT 47600.0 98699.99999999999 48400.00000000001 97900.0 ; + RECT 47600.0 98699.99999999999 48400.00000000001 97900.0 ; + RECT 46000.00000000001 98699.99999999999 46800.00000000001 97900.0 ; + RECT 49200.0 81300.00000000001 50000.00000000001 80500.0 ; + RECT 49200.0 98699.99999999999 50000.00000000001 97900.0 ; + RECT 46400.00000000001 90199.99999999999 47200.0 89400.0 ; + RECT 46400.00000000001 90199.99999999999 47200.0 89400.0 ; + RECT 48100.0 90100.0 48700.0 89500.0 ; + RECT 44800.00000000001 79900.0 51200.0 79300.00000000001 ; + RECT 44800.00000000001 99900.0 51200.0 99300.00000000001 ; + RECT 39600.0 118300.00000000001 40400.00000000001 119600.0 ; + RECT 39600.0 99600.0 40400.00000000001 100900.0 ; + RECT 36400.00000000001 101699.99999999999 37200.0 99300.00000000001 ; + RECT 36400.00000000001 115100.0 37200.0 119900.0 ; + RECT 38200.0 101699.99999999999 38800.00000000001 115100.0 ; + RECT 36400.00000000001 115100.0 37200.0 115900.0 ; + RECT 38000.0 115100.0 38800.00000000001 115900.0 ; + RECT 38000.0 115100.0 38800.00000000001 115900.0 ; + RECT 36400.00000000001 115100.0 37200.0 115900.0 ; + RECT 36400.00000000001 101699.99999999999 37200.0 102500.0 ; + RECT 38000.0 101699.99999999999 38800.00000000001 102500.0 ; + RECT 38000.0 101699.99999999999 38800.00000000001 102500.0 ; + RECT 36400.00000000001 101699.99999999999 37200.0 102500.0 ; + RECT 39600.0 117900.0 40400.00000000001 118699.99999999999 ; + RECT 39600.0 100500.0 40400.00000000001 101300.00000000001 ; + RECT 36800.00000000001 108400.0 37600.0 109199.99999999999 ; + RECT 36800.00000000001 108400.0 37600.0 109199.99999999999 ; + RECT 38500.0 108500.0 39100.0 109100.0 ; + RECT 35200.0 119300.00000000001 41600.0 119900.0 ; + RECT 35200.0 99300.00000000001 41600.0 99900.0 ; + RECT 50800.00000000001 118300.00000000001 51600.0 119600.0 ; + RECT 50800.00000000001 99600.0 51600.0 100900.0 ; + RECT 42900.0 100500.0 49900.00000000001 99300.00000000001 ; + RECT 42900.0 116500.0 49900.00000000001 119900.0 ; + RECT 47700.0 103100.0 48300.00000000001 113900.0 ; + RECT 42900.0 115500.0 43500.0 116800.00000000001 ; + RECT 46100.0 115500.0 46700.0 116800.00000000001 ; + RECT 49300.00000000001 115500.0 49900.00000000001 116800.00000000001 ; + RECT 44500.0 114199.99999999999 45100.0 115500.0 ; + RECT 47700.0 114199.99999999999 48300.00000000001 115500.0 ; + RECT 42800.00000000001 115100.0 43600.0 115900.0 ; + RECT 46000.0 115100.0 46800.00000000001 115900.0 ; + RECT 49200.0 115100.0 50000.0 115900.0 ; + RECT 44400.0 115100.0 45200.0 115900.0 ; + RECT 47600.0 115100.0 48400.0 115900.0 ; + RECT 44500.0 113900.0 48300.00000000001 114500.0 ; + RECT 42900.0 116500.0 49900.00000000001 117100.0 ; + RECT 42900.0 100800.00000000001 43500.0 102100.0 ; + RECT 46100.0 100800.00000000001 46700.0 102100.0 ; + RECT 49300.00000000001 100800.00000000001 49900.00000000001 102100.0 ; + RECT 44500.0 102100.0 45100.0 103400.0 ; + RECT 47700.0 102100.0 48300.00000000001 103400.0 ; + RECT 42800.00000000001 101699.99999999999 43600.0 102500.0 ; + RECT 46000.0 101699.99999999999 46800.00000000001 102500.0 ; + RECT 49200.0 101699.99999999999 50000.0 102500.0 ; + RECT 44400.0 101699.99999999999 45200.0 102500.0 ; + RECT 47600.0 101699.99999999999 48400.0 102500.0 ; + RECT 44500.0 103100.0 48300.00000000001 103699.99999999999 ; + RECT 42900.0 100500.0 49900.00000000001 101100.0 ; + RECT 50800.00000000001 117900.0 51600.0 118699.99999999999 ; + RECT 50800.00000000001 100500.0 51600.0 101300.00000000001 ; + RECT 43200.0 108400.0 44000.0 109199.99999999999 ; + RECT 43200.0 108400.0 44000.0 109199.99999999999 ; + RECT 48000.0 108500.0 48600.0 109100.0 ; + RECT 41600.0 119300.00000000001 52800.00000000001 119900.0 ; + RECT 41600.0 99300.00000000001 52800.00000000001 99900.0 ; + RECT 31500.000000000004 123100.00000000003 32100.0 124500.0 ; + RECT 35400.00000000001 134700.00000000003 36800.00000000001 135500.0 ; + RECT 35400.00000000001 150300.0 36800.00000000001 151100.0 ; + RECT 35400.00000000001 153100.0 36800.00000000001 153900.0 ; + RECT 35400.00000000001 168700.00000000003 36800.00000000001 169500.0 ; + RECT 35400.00000000001 171500.0 36800.00000000001 172300.0 ; + RECT 35400.00000000001 187100.0 36800.00000000001 187900.0 ; + RECT 35400.00000000001 189900.0 36800.00000000001 190700.00000000003 ; + RECT 35400.00000000001 205500.0 36800.00000000001 206299.99999999997 ; + RECT 26800.0 132000.0 27400.000000000004 132600.00000000003 ; + RECT 26800.0 131400.0 27400.000000000004 132000.0 ; + RECT 27100.0 132000.0 28000.0 132600.00000000003 ; + RECT 26800.0 131700.00000000003 27400.000000000004 132300.0 ; + RECT 16800.0 131400.0 27100.0 132000.0 ; + RECT 15700.000000000002 129000.0 16300.0 129600.00000000003 ; + RECT 15700.000000000002 129300.00000000001 16300.0 129500.0 ; + RECT 10800.0 129000.0 16000.0 129600.00000000003 ; + RECT 8399.999999999998 125800.00000000001 7600.0 124500.0 ; + RECT 8400.0 133700.00000000003 7600.000000000001 132400.0 ; + RECT 11600.000000000002 132800.0 10800.0 134000.0 ; + RECT 11600.0 126600.00000000003 10799.999999999998 124200.00000000001 ; + RECT 9800.0 132800.0 9200.0 126600.00000000003 ; + RECT 11600.0 126600.00000000003 10800.0 125800.00000000001 ; + RECT 10000.0 126600.00000000003 9200.0 125800.00000000001 ; + RECT 10000.0 126600.00000000003 9200.0 125800.00000000001 ; + RECT 11600.0 126600.00000000003 10800.0 125800.00000000001 ; + RECT 11600.000000000002 132800.0 10800.0 132000.0 ; + RECT 10000.0 132800.0 9200.0 132000.0 ; + RECT 10000.0 132800.0 9200.000000000002 132000.0 ; + RECT 11600.000000000002 132800.0 10800.0 132000.0 ; + RECT 8399.999999999998 126200.00000000001 7600.0 125400.0 ; + RECT 8400.0 132800.0 7600.000000000001 132000.0 ; + RECT 11200.0 129700.00000000001 10400.0 128900.0 ; + RECT 11200.0 129700.00000000001 10400.0 128900.0 ; + RECT 9500.0 129600.00000000003 8900.0 129000.0 ; + RECT 12799.999999999998 124800.00000000001 6399.999999999999 124200.00000000001 ; + RECT 12800.0 134000.0 6400.0 133400.0 ; + RECT 15600.000000000002 129100.00000000003 16400.000000000004 129900.0 ; + RECT 17200.000000000004 129100.00000000003 18000.0 129900.0 ; + RECT 17200.000000000004 129100.00000000003 18000.0 129900.0 ; + RECT 15600.000000000002 129100.00000000003 16400.000000000004 129900.0 ; + RECT 4400.0 141600.00000000003 5200.0 142900.0 ; + RECT 4400.0 133700.00000000003 5200.0 135000.0 ; + RECT 1200.0000000000002 134600.00000000003 2000.0 133400.0 ; + RECT 1200.0000000000002 140800.0 2000.0 143200.00000000003 ; + RECT 3000.0 134600.00000000003 3600.0 140800.0 ; + RECT 1200.0000000000002 140800.0 2000.0 141600.00000000003 ; + RECT 2800.0000000000005 140800.0 3600.0000000000005 141600.00000000003 ; + RECT 2800.0000000000005 140800.0 3600.0 141600.00000000003 ; + RECT 1200.0000000000002 140800.0 2000.0 141600.00000000003 ; + RECT 1200.0000000000002 134600.00000000003 2000.0 135400.0 ; + RECT 2800.0000000000005 134600.00000000003 3600.0000000000005 135400.0 ; + RECT 2800.0000000000005 134600.00000000003 3600.0 135400.0 ; + RECT 1200.0000000000002 134600.00000000003 2000.0 135400.0 ; + RECT 4400.0 141200.00000000003 5200.0 142000.0 ; + RECT 4400.0 134600.00000000003 5200.0 135400.0 ; + RECT 1600.0 137700.00000000003 2400.0000000000005 138500.0 ; + RECT 1600.0 137700.00000000003 2400.0000000000005 138500.0 ; + RECT 3300.0000000000005 137800.0 3900.0000000000005 138400.0 ; + RECT 0.0 142600.00000000003 6400.0 143200.00000000003 ; + RECT 0.0 133400.0 6400.0 134000.0 ; + RECT 10800.0 141600.00000000003 11600.000000000002 142900.0 ; + RECT 10800.0 133700.00000000003 11600.000000000002 135000.0 ; + RECT 7600.000000000001 134600.00000000003 8400.0 133400.0 ; + RECT 7600.000000000001 140800.0 8400.0 143200.00000000003 ; + RECT 9400.0 134600.00000000003 10000.0 140800.0 ; + RECT 7600.000000000001 140800.0 8400.0 141600.00000000003 ; + RECT 9200.000000000002 140800.0 10000.0 141600.00000000003 ; + RECT 9200.000000000002 140800.0 10000.0 141600.00000000003 ; + RECT 7600.000000000001 140800.0 8400.0 141600.00000000003 ; + RECT 7600.000000000001 134600.00000000003 8400.0 135400.0 ; + RECT 9200.000000000002 134600.00000000003 10000.0 135400.0 ; + RECT 9200.000000000002 134600.00000000003 10000.0 135400.0 ; + RECT 7600.000000000001 134600.00000000003 8400.0 135400.0 ; + RECT 10800.0 141200.00000000003 11600.000000000002 142000.0 ; + RECT 10800.0 134600.00000000003 11600.000000000002 135400.0 ; + RECT 8000.0 137700.00000000003 8800.0 138500.0 ; + RECT 8000.0 137700.00000000003 8800.0 138500.0 ; + RECT 9700.000000000002 137800.0 10300.0 138400.0 ; + RECT 6400.0 142600.00000000003 12800.0 143200.00000000003 ; + RECT 6400.0 133400.0 12800.0 134000.0 ; + RECT 17200.000000000004 141600.00000000003 18000.0 142900.0 ; + RECT 17200.000000000004 133700.00000000003 18000.0 135000.0 ; + RECT 14000.0 134600.00000000003 14800.0 133400.0 ; + RECT 14000.0 140800.0 14800.0 143200.00000000003 ; + RECT 15800.0 134600.00000000003 16400.000000000004 140800.0 ; + RECT 14000.0 140800.0 14800.0 141600.00000000003 ; + RECT 15600.000000000002 140800.0 16400.000000000004 141600.00000000003 ; + RECT 15600.000000000002 140800.0 16400.000000000004 141600.00000000003 ; + RECT 14000.0 140800.0 14800.0 141600.00000000003 ; + RECT 14000.0 134600.00000000003 14800.0 135400.0 ; + RECT 15600.000000000002 134600.00000000003 16400.000000000004 135400.0 ; + RECT 15600.000000000002 134600.00000000003 16400.000000000004 135400.0 ; + RECT 14000.0 134600.00000000003 14800.0 135400.0 ; + RECT 17200.000000000004 141200.00000000003 18000.0 142000.0 ; + RECT 17200.000000000004 134600.00000000003 18000.0 135400.0 ; + RECT 14400.0 137700.00000000003 15200.000000000002 138500.0 ; + RECT 14400.0 137700.00000000003 15200.000000000002 138500.0 ; + RECT 16100.000000000002 137800.0 16700.000000000004 138400.0 ; + RECT 12800.0 142600.00000000003 19200.000000000004 143200.00000000003 ; + RECT 12800.0 133400.0 19200.000000000004 134000.0 ; + RECT 23600.0 141600.00000000003 24400.000000000004 142900.0 ; + RECT 23600.0 133700.00000000003 24400.000000000004 135000.0 ; + RECT 20400.000000000004 134600.00000000003 21200.000000000004 133400.0 ; + RECT 20400.000000000004 140800.0 21200.000000000004 143200.00000000003 ; + RECT 22200.000000000004 134600.00000000003 22800.000000000004 140800.0 ; + RECT 20400.000000000004 140800.0 21200.000000000004 141600.00000000003 ; + RECT 22000.000000000004 140800.0 22800.000000000004 141600.00000000003 ; + RECT 22000.000000000004 140800.0 22800.000000000004 141600.00000000003 ; + RECT 20400.000000000004 140800.0 21200.000000000004 141600.00000000003 ; + RECT 20400.000000000004 134600.00000000003 21200.000000000004 135400.0 ; + RECT 22000.000000000004 134600.00000000003 22800.000000000004 135400.0 ; + RECT 22000.000000000004 134600.00000000003 22800.000000000004 135400.0 ; + RECT 20400.000000000004 134600.00000000003 21200.000000000004 135400.0 ; + RECT 23600.0 141200.00000000003 24400.000000000004 142000.0 ; + RECT 23600.0 134600.00000000003 24400.000000000004 135400.0 ; + RECT 20800.000000000004 137700.00000000003 21600.0 138500.0 ; + RECT 20800.000000000004 137700.00000000003 21600.0 138500.0 ; + RECT 22500.000000000004 137800.0 23100.0 138400.0 ; + RECT 19200.000000000004 142600.00000000003 25600.0 143200.00000000003 ; + RECT 19200.000000000004 133400.0 25600.0 134000.0 ; + RECT 4400.0 144200.00000000003 5200.0 142900.0 ; + RECT 4400.0 152100.0 5200.0 150800.0 ; + RECT 1200.0000000000002 151200.00000000003 2000.0 152400.0 ; + RECT 1200.0000000000002 145000.0 2000.0 142600.00000000003 ; + RECT 3000.0 151200.00000000003 3600.0 145000.0 ; + RECT 1200.0000000000002 145000.0 2000.0 144200.00000000003 ; + RECT 2800.0000000000005 145000.0 3600.0000000000005 144200.00000000003 ; + RECT 2800.0000000000005 145000.0 3600.0 144200.00000000003 ; + RECT 1200.0000000000002 145000.0 2000.0 144200.00000000003 ; + RECT 1200.0000000000002 151200.00000000003 2000.0 150400.0 ; + RECT 2800.0000000000005 151200.00000000003 3600.0000000000005 150400.0 ; + RECT 2800.0000000000005 151200.00000000003 3600.0 150400.0 ; + RECT 1200.0000000000002 151200.00000000003 2000.0 150400.0 ; + RECT 4400.0 144600.00000000003 5200.0 143800.0 ; + RECT 4400.0 151200.00000000003 5200.0 150400.0 ; + RECT 1600.0 148100.0 2400.0000000000005 147300.0 ; + RECT 1600.0 148100.0 2400.0000000000005 147300.0 ; + RECT 3300.0000000000005 148000.0 3900.0000000000005 147400.0 ; + RECT 0.0 143200.00000000003 6400.0 142600.00000000003 ; + RECT 0.0 152400.0 6400.0 151800.0 ; + RECT 10800.0 144200.00000000003 11600.000000000002 142900.0 ; + RECT 10800.0 152100.0 11600.000000000002 150800.0 ; + RECT 7600.000000000001 151200.00000000003 8400.0 152400.0 ; + RECT 7600.000000000001 145000.0 8400.0 142600.00000000003 ; + RECT 9400.0 151200.00000000003 10000.0 145000.0 ; + RECT 7600.000000000001 145000.0 8400.0 144200.00000000003 ; + RECT 9200.000000000002 145000.0 10000.0 144200.00000000003 ; + RECT 9200.000000000002 145000.0 10000.0 144200.00000000003 ; + RECT 7600.000000000001 145000.0 8400.0 144200.00000000003 ; + RECT 7600.000000000001 151200.00000000003 8400.0 150400.0 ; + RECT 9200.000000000002 151200.00000000003 10000.0 150400.0 ; + RECT 9200.000000000002 151200.00000000003 10000.0 150400.0 ; + RECT 7600.000000000001 151200.00000000003 8400.0 150400.0 ; + RECT 10800.0 144600.00000000003 11600.000000000002 143800.0 ; + RECT 10800.0 151200.00000000003 11600.000000000002 150400.0 ; + RECT 8000.0 148100.0 8800.0 147300.0 ; + RECT 8000.0 148100.0 8800.0 147300.0 ; + RECT 9700.000000000002 148000.0 10300.0 147400.0 ; + RECT 6400.0 143200.00000000003 12800.0 142600.00000000003 ; + RECT 6400.0 152400.0 12800.0 151800.0 ; + RECT 17200.000000000004 144200.00000000003 18000.0 142900.0 ; + RECT 17200.000000000004 152100.0 18000.0 150800.0 ; + RECT 14000.0 151200.00000000003 14800.0 152400.0 ; + RECT 14000.0 145000.0 14800.0 142600.00000000003 ; + RECT 15800.0 151200.00000000003 16400.000000000004 145000.0 ; + RECT 14000.0 145000.0 14800.0 144200.00000000003 ; + RECT 15600.000000000002 145000.0 16400.000000000004 144200.00000000003 ; + RECT 15600.000000000002 145000.0 16400.000000000004 144200.00000000003 ; + RECT 14000.0 145000.0 14800.0 144200.00000000003 ; + RECT 14000.0 151200.00000000003 14800.0 150400.0 ; + RECT 15600.000000000002 151200.00000000003 16400.000000000004 150400.0 ; + RECT 15600.000000000002 151200.00000000003 16400.000000000004 150400.0 ; + RECT 14000.0 151200.00000000003 14800.0 150400.0 ; + RECT 17200.000000000004 144600.00000000003 18000.0 143800.0 ; + RECT 17200.000000000004 151200.00000000003 18000.0 150400.0 ; + RECT 14400.0 148100.0 15200.000000000002 147300.0 ; + RECT 14400.0 148100.0 15200.000000000002 147300.0 ; + RECT 16100.000000000002 148000.0 16700.000000000004 147400.0 ; + RECT 12800.0 143200.00000000003 19200.000000000004 142600.00000000003 ; + RECT 12800.0 152400.0 19200.000000000004 151800.0 ; + RECT 23600.0 144200.00000000003 24400.000000000004 142900.0 ; + RECT 23600.0 152100.0 24400.000000000004 150800.0 ; + RECT 20400.000000000004 151200.00000000003 21200.000000000004 152400.0 ; + RECT 20400.000000000004 145000.0 21200.000000000004 142600.00000000003 ; + RECT 22200.000000000004 151200.00000000003 22800.000000000004 145000.0 ; + RECT 20400.000000000004 145000.0 21200.000000000004 144200.00000000003 ; + RECT 22000.000000000004 145000.0 22800.000000000004 144200.00000000003 ; + RECT 22000.000000000004 145000.0 22800.000000000004 144200.00000000003 ; + RECT 20400.000000000004 145000.0 21200.000000000004 144200.00000000003 ; + RECT 20400.000000000004 151200.00000000003 21200.000000000004 150400.0 ; + RECT 22000.000000000004 151200.00000000003 22800.000000000004 150400.0 ; + RECT 22000.000000000004 151200.00000000003 22800.000000000004 150400.0 ; + RECT 20400.000000000004 151200.00000000003 21200.000000000004 150400.0 ; + RECT 23600.0 144600.00000000003 24400.000000000004 143800.0 ; + RECT 23600.0 151200.00000000003 24400.000000000004 150400.0 ; + RECT 20800.000000000004 148100.0 21600.0 147300.0 ; + RECT 20800.000000000004 148100.0 21600.0 147300.0 ; + RECT 22500.000000000004 148000.0 23100.0 147400.0 ; + RECT 19200.000000000004 143200.00000000003 25600.0 142600.00000000003 ; + RECT 19200.000000000004 152400.0 25600.0 151800.0 ; + RECT 4400.0 160000.00000000003 5200.0 161300.0 ; + RECT 4400.0 152100.0 5200.0 153400.0 ; + RECT 1200.0000000000002 153000.0 2000.0 151800.0 ; + RECT 1200.0000000000002 159200.00000000003 2000.0 161600.0 ; + RECT 3000.0 153000.0 3600.0 159200.00000000003 ; + RECT 1200.0000000000002 159200.00000000003 2000.0 160000.00000000003 ; + RECT 2800.0000000000005 159200.00000000003 3600.0000000000005 160000.00000000003 ; + RECT 2800.0000000000005 159200.00000000003 3600.0 160000.00000000003 ; + RECT 1200.0000000000002 159200.00000000003 2000.0 160000.00000000003 ; + RECT 1200.0000000000002 153000.0 2000.0 153800.0 ; + RECT 2800.0000000000005 153000.0 3600.0000000000005 153800.0 ; + RECT 2800.0000000000005 153000.0 3600.0 153800.0 ; + RECT 1200.0000000000002 153000.0 2000.0 153800.0 ; + RECT 4400.0 159600.0 5200.0 160400.0 ; + RECT 4400.0 153000.0 5200.0 153800.0 ; + RECT 1600.0 156100.0 2400.0000000000005 156900.0 ; + RECT 1600.0 156100.0 2400.0000000000005 156900.0 ; + RECT 3300.0000000000005 156200.00000000003 3900.0000000000005 156800.0 ; + RECT 0.0 161000.00000000003 6400.0 161600.0 ; + RECT 0.0 151800.0 6400.0 152400.0 ; + RECT 10800.0 160000.00000000003 11600.000000000002 161300.0 ; + RECT 10800.0 152100.0 11600.000000000002 153400.0 ; + RECT 7600.000000000001 153000.0 8400.0 151800.0 ; + RECT 7600.000000000001 159200.00000000003 8400.0 161600.0 ; + RECT 9400.0 153000.0 10000.0 159200.00000000003 ; + RECT 7600.000000000001 159200.00000000003 8400.0 160000.00000000003 ; + RECT 9200.000000000002 159200.00000000003 10000.0 160000.00000000003 ; + RECT 9200.000000000002 159200.00000000003 10000.0 160000.00000000003 ; + RECT 7600.000000000001 159200.00000000003 8400.0 160000.00000000003 ; + RECT 7600.000000000001 153000.0 8400.0 153800.0 ; + RECT 9200.000000000002 153000.0 10000.0 153800.0 ; + RECT 9200.000000000002 153000.0 10000.0 153800.0 ; + RECT 7600.000000000001 153000.0 8400.0 153800.0 ; + RECT 10800.0 159600.0 11600.000000000002 160400.0 ; + RECT 10800.0 153000.0 11600.000000000002 153800.0 ; + RECT 8000.0 156100.0 8800.0 156900.0 ; + RECT 8000.0 156100.0 8800.0 156900.0 ; + RECT 9700.000000000002 156200.00000000003 10300.0 156800.0 ; + RECT 6400.0 161000.00000000003 12800.0 161600.0 ; + RECT 6400.0 151800.0 12800.0 152400.0 ; + RECT 17200.000000000004 160000.00000000003 18000.0 161300.0 ; + RECT 17200.000000000004 152100.0 18000.0 153400.0 ; + RECT 14000.0 153000.0 14800.0 151800.0 ; + RECT 14000.0 159200.00000000003 14800.0 161600.0 ; + RECT 15800.0 153000.0 16400.000000000004 159200.00000000003 ; + RECT 14000.0 159200.00000000003 14800.0 160000.00000000003 ; + RECT 15600.000000000002 159200.00000000003 16400.000000000004 160000.00000000003 ; + RECT 15600.000000000002 159200.00000000003 16400.000000000004 160000.00000000003 ; + RECT 14000.0 159200.00000000003 14800.0 160000.00000000003 ; + RECT 14000.0 153000.0 14800.0 153800.0 ; + RECT 15600.000000000002 153000.0 16400.000000000004 153800.0 ; + RECT 15600.000000000002 153000.0 16400.000000000004 153800.0 ; + RECT 14000.0 153000.0 14800.0 153800.0 ; + RECT 17200.000000000004 159600.0 18000.0 160400.0 ; + RECT 17200.000000000004 153000.0 18000.0 153800.0 ; + RECT 14400.0 156100.0 15200.000000000002 156900.0 ; + RECT 14400.0 156100.0 15200.000000000002 156900.0 ; + RECT 16100.000000000002 156200.00000000003 16700.000000000004 156800.0 ; + RECT 12800.0 161000.00000000003 19200.000000000004 161600.0 ; + RECT 12800.0 151800.0 19200.000000000004 152400.0 ; + RECT 23600.0 160000.00000000003 24400.000000000004 161300.0 ; + RECT 23600.0 152100.0 24400.000000000004 153400.0 ; + RECT 20400.000000000004 153000.0 21200.000000000004 151800.0 ; + RECT 20400.000000000004 159200.00000000003 21200.000000000004 161600.0 ; + RECT 22200.000000000004 153000.0 22800.000000000004 159200.00000000003 ; + RECT 20400.000000000004 159200.00000000003 21200.000000000004 160000.00000000003 ; + RECT 22000.000000000004 159200.00000000003 22800.000000000004 160000.00000000003 ; + RECT 22000.000000000004 159200.00000000003 22800.000000000004 160000.00000000003 ; + RECT 20400.000000000004 159200.00000000003 21200.000000000004 160000.00000000003 ; + RECT 20400.000000000004 153000.0 21200.000000000004 153800.0 ; + RECT 22000.000000000004 153000.0 22800.000000000004 153800.0 ; + RECT 22000.000000000004 153000.0 22800.000000000004 153800.0 ; + RECT 20400.000000000004 153000.0 21200.000000000004 153800.0 ; + RECT 23600.0 159600.0 24400.000000000004 160400.0 ; + RECT 23600.0 153000.0 24400.000000000004 153800.0 ; + RECT 20800.000000000004 156100.0 21600.0 156900.0 ; + RECT 20800.000000000004 156100.0 21600.0 156900.0 ; + RECT 22500.000000000004 156200.00000000003 23100.0 156800.0 ; + RECT 19200.000000000004 161000.00000000003 25600.0 161600.0 ; + RECT 19200.000000000004 151800.0 25600.0 152400.0 ; + RECT 4400.0 162600.0 5200.0 161300.0 ; + RECT 4400.0 170500.00000000003 5200.0 169200.00000000003 ; + RECT 1200.0000000000002 169600.0 2000.0 170800.0 ; + RECT 1200.0000000000002 163400.0 2000.0 161000.00000000003 ; + RECT 3000.0 169600.0 3600.0 163400.0 ; + RECT 1200.0000000000002 163400.0 2000.0 162600.0 ; + RECT 2800.0000000000005 163400.0 3600.0000000000005 162600.0 ; + RECT 2800.0000000000005 163400.0 3600.0 162600.0 ; + RECT 1200.0000000000002 163400.0 2000.0 162600.0 ; + RECT 1200.0000000000002 169600.0 2000.0 168800.0 ; + RECT 2800.0000000000005 169600.0 3600.0000000000005 168800.0 ; + RECT 2800.0000000000005 169600.0 3600.0 168800.0 ; + RECT 1200.0000000000002 169600.0 2000.0 168800.0 ; + RECT 4400.0 163000.00000000003 5200.0 162200.00000000003 ; + RECT 4400.0 169600.0 5200.0 168800.0 ; + RECT 1600.0 166500.00000000003 2400.0000000000005 165700.00000000003 ; + RECT 1600.0 166500.00000000003 2400.0000000000005 165700.00000000003 ; + RECT 3300.0000000000005 166400.0 3900.0000000000005 165800.0 ; + RECT 0.0 161600.0 6400.0 161000.00000000003 ; + RECT 0.0 170800.0 6400.0 170200.00000000003 ; + RECT 10800.0 162600.0 11600.000000000002 161300.0 ; + RECT 10800.0 170500.00000000003 11600.000000000002 169200.00000000003 ; + RECT 7600.000000000001 169600.0 8400.0 170800.0 ; + RECT 7600.000000000001 163400.0 8400.0 161000.00000000003 ; + RECT 9400.0 169600.0 10000.0 163400.0 ; + RECT 7600.000000000001 163400.0 8400.0 162600.0 ; + RECT 9200.000000000002 163400.0 10000.0 162600.0 ; + RECT 9200.000000000002 163400.0 10000.0 162600.0 ; + RECT 7600.000000000001 163400.0 8400.0 162600.0 ; + RECT 7600.000000000001 169600.0 8400.0 168800.0 ; + RECT 9200.000000000002 169600.0 10000.0 168800.0 ; + RECT 9200.000000000002 169600.0 10000.0 168800.0 ; + RECT 7600.000000000001 169600.0 8400.0 168800.0 ; + RECT 10800.0 163000.00000000003 11600.000000000002 162200.00000000003 ; + RECT 10800.0 169600.0 11600.000000000002 168800.0 ; + RECT 8000.0 166500.00000000003 8800.0 165700.00000000003 ; + RECT 8000.0 166500.00000000003 8800.0 165700.00000000003 ; + RECT 9700.000000000002 166400.0 10300.0 165800.0 ; + RECT 6400.0 161600.0 12800.0 161000.00000000003 ; + RECT 6400.0 170800.0 12800.0 170200.00000000003 ; + RECT 17200.000000000004 162600.0 18000.0 161300.0 ; + RECT 17200.000000000004 170500.00000000003 18000.0 169200.00000000003 ; + RECT 14000.0 169600.0 14800.0 170800.0 ; + RECT 14000.0 163400.0 14800.0 161000.00000000003 ; + RECT 15800.0 169600.0 16400.000000000004 163400.0 ; + RECT 14000.0 163400.0 14800.0 162600.0 ; + RECT 15600.000000000002 163400.0 16400.000000000004 162600.0 ; + RECT 15600.000000000002 163400.0 16400.000000000004 162600.0 ; + RECT 14000.0 163400.0 14800.0 162600.0 ; + RECT 14000.0 169600.0 14800.0 168800.0 ; + RECT 15600.000000000002 169600.0 16400.000000000004 168800.0 ; + RECT 15600.000000000002 169600.0 16400.000000000004 168800.0 ; + RECT 14000.0 169600.0 14800.0 168800.0 ; + RECT 17200.000000000004 163000.00000000003 18000.0 162200.00000000003 ; + RECT 17200.000000000004 169600.0 18000.0 168800.0 ; + RECT 14400.0 166500.00000000003 15200.000000000002 165700.00000000003 ; + RECT 14400.0 166500.00000000003 15200.000000000002 165700.00000000003 ; + RECT 16100.000000000002 166400.0 16700.000000000004 165800.0 ; + RECT 12800.0 161600.0 19200.000000000004 161000.00000000003 ; + RECT 12800.0 170800.0 19200.000000000004 170200.00000000003 ; + RECT 23600.0 162600.0 24400.000000000004 161300.0 ; + RECT 23600.0 170500.00000000003 24400.000000000004 169200.00000000003 ; + RECT 20400.000000000004 169600.0 21200.000000000004 170800.0 ; + RECT 20400.000000000004 163400.0 21200.000000000004 161000.00000000003 ; + RECT 22200.000000000004 169600.0 22800.000000000004 163400.0 ; + RECT 20400.000000000004 163400.0 21200.000000000004 162600.0 ; + RECT 22000.000000000004 163400.0 22800.000000000004 162600.0 ; + RECT 22000.000000000004 163400.0 22800.000000000004 162600.0 ; + RECT 20400.000000000004 163400.0 21200.000000000004 162600.0 ; + RECT 20400.000000000004 169600.0 21200.000000000004 168800.0 ; + RECT 22000.000000000004 169600.0 22800.000000000004 168800.0 ; + RECT 22000.000000000004 169600.0 22800.000000000004 168800.0 ; + RECT 20400.000000000004 169600.0 21200.000000000004 168800.0 ; + RECT 23600.0 163000.00000000003 24400.000000000004 162200.00000000003 ; + RECT 23600.0 169600.0 24400.000000000004 168800.0 ; + RECT 20800.000000000004 166500.00000000003 21600.0 165700.00000000003 ; + RECT 20800.000000000004 166500.00000000003 21600.0 165700.00000000003 ; + RECT 22500.000000000004 166400.0 23100.0 165800.0 ; + RECT 19200.000000000004 161600.0 25600.0 161000.00000000003 ; + RECT 19200.000000000004 170800.0 25600.0 170200.00000000003 ; + RECT 8000.0 137700.00000000003 8800.0 138500.0 ; + RECT 14400.0 137700.00000000003 15200.000000000002 138500.0 ; + RECT 20800.0 137700.00000000003 21600.0 138500.0 ; + RECT 1600.0 137700.00000000003 2400.0000000000005 138500.0 ; + RECT 3200.0 137700.00000000003 4000.0 138500.0 ; + RECT 8000.0 147300.0 8800.0 148100.0 ; + RECT 14400.0 147300.0 15200.000000000002 148100.0 ; + RECT 20800.0 147300.0 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28800.000000000004 174400.0 148700.00000000003 ; + RECT 172400.0 50400.00000000001 173000.0 148700.00000000003 ; + RECT 73899.99999999999 159600.00000000003 74499.99999999999 221700.00000000003 ; + RECT 75300.0 159600.00000000003 75899.99999999999 242100.00000000003 ; + RECT 76700.0 159600.00000000003 77300.0 261700.00000000006 ; + RECT 78100.0 159600.00000000003 78699.99999999999 282100.0 ; + RECT 181700.0 22800.000000000004 182299.99999999997 25200.000000000004 ; + RECT 197500.0 9800.000000000002 198100.0 22800.000000000004 ; + RECT 188500.0 24200.000000000004 189100.0 25200.000000000004 ; + RECT 219300.0 9800.000000000002 219900.0 24200.000000000004 ; + RECT 180700.0 64599.99999999999 181300.0 71500.0 ; + RECT 180700.0 71500.0 181300.0 78400.0 ; + RECT 182700.0 64599.99999999999 183300.0 71500.0 ; + RECT 182700.0 71500.0 183300.0 78400.0 ; + RECT 187500.0 64599.99999999999 188100.00000000003 71500.0 ; + RECT 187500.0 71500.0 188100.00000000003 78400.0 ; + RECT 189500.0 64599.99999999999 190100.00000000003 71500.0 ; + RECT 189500.0 71500.0 190100.00000000003 78400.0 ; + RECT 180700.0 103200.0 181300.0 103800.0 ; + RECT 179900.0 103200.0 180500.0 103800.0 ; + RECT 180700.0 101400.0 181300.0 103500.0 ; + RECT 180200.0 103200.0 181000.0 103800.0 ; + RECT 179900.0 103500.0 180500.0 105600.0 ; + RECT 182700.0 103200.0 183300.0 103800.0 ; + RECT 183500.0 103200.0 184100.00000000003 103800.0 ; + RECT 182700.0 101400.0 183300.0 103500.0 ; + RECT 183000.0 103200.0 183800.0 103800.0 ; + RECT 183500.0 103500.0 184100.00000000003 105600.0 ; + RECT 187500.0 103200.0 188100.00000000003 103800.0 ; + RECT 186700.0 103200.0 187300.0 103800.0 ; + RECT 187500.0 101400.0 188100.00000000003 103500.0 ; + RECT 187000.0 103200.0 187800.0 103800.0 ; + RECT 186700.0 103500.0 187300.0 105600.0 ; + RECT 189500.0 103200.0 190100.00000000003 103800.0 ; + RECT 190300.0 103200.0 190900.0 103800.0 ; + RECT 189500.0 101400.0 190100.00000000003 103500.0 ; + RECT 189800.0 103200.0 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168000.0 189200.0 168800.0 ; + RECT 181600.00000000003 168000.0 182400.0 168800.0 ; + RECT 188400.0 168000.0 189200.0 168800.0 ; + RECT 181600.00000000003 186399.99999999997 182400.0 187200.0 ; + RECT 188400.0 186399.99999999997 189200.0 187200.0 ; + RECT 181600.00000000003 186399.99999999997 182400.0 187200.0 ; + RECT 188400.0 186399.99999999997 189200.0 187200.0 ; + RECT 181600.00000000003 204800.0 182400.0 205600.00000000003 ; + RECT 188400.0 204800.0 189200.0 205600.00000000003 ; + RECT 181600.00000000003 204800.0 182400.0 205600.00000000003 ; + RECT 188400.0 204800.0 189200.0 205600.00000000003 ; + RECT 181600.00000000003 223200.0 182400.0 224000.0 ; + RECT 188400.0 223200.0 189200.0 224000.0 ; + RECT 181600.00000000003 223200.0 182400.0 224000.0 ; + RECT 188400.0 223200.0 189200.0 224000.0 ; + RECT 181600.00000000003 241600.00000000003 182400.0 242399.99999999997 ; + RECT 188400.0 241600.00000000003 189200.0 242399.99999999997 ; + RECT 181600.00000000003 241600.00000000003 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185000.0 154200.0 185800.0 155000.0 ; + RECT 185000.0 154200.0 185800.0 155000.0 ; + RECT 191800.0 154200.0 192600.00000000003 155000.0 ; + RECT 178200.0 163399.99999999997 179000.0 164200.0 ; + RECT 185000.0 163399.99999999997 185800.0 164200.0 ; + RECT 185000.0 163399.99999999997 185800.0 164200.0 ; + RECT 191800.0 163399.99999999997 192600.00000000003 164200.0 ; + RECT 178200.0 172600.00000000003 179000.0 173399.99999999997 ; + RECT 185000.0 172600.00000000003 185800.0 173399.99999999997 ; + RECT 185000.0 172600.00000000003 185800.0 173399.99999999997 ; + RECT 191800.0 172600.00000000003 192600.00000000003 173399.99999999997 ; + RECT 178200.0 181800.0 179000.0 182600.00000000003 ; + RECT 185000.0 181800.0 185800.0 182600.00000000003 ; + RECT 185000.0 181800.0 185800.0 182600.00000000003 ; + RECT 191800.0 181800.0 192600.00000000003 182600.00000000003 ; + RECT 178200.0 191000.0 179000.0 191800.0 ; + RECT 185000.0 191000.0 185800.0 191800.0 ; + RECT 185000.0 191000.0 185800.0 191800.0 ; + RECT 191800.0 191000.0 192600.00000000003 191800.0 ; + RECT 178200.0 200200.0 179000.0 201000.0 ; + RECT 185000.0 200200.0 185800.0 201000.0 ; + RECT 185000.0 200200.0 185800.0 201000.0 ; + RECT 191800.0 200200.0 192600.00000000003 201000.0 ; + RECT 178200.0 209399.99999999997 179000.0 210200.0 ; + RECT 185000.0 209399.99999999997 185800.0 210200.0 ; + RECT 185000.0 209399.99999999997 185800.0 210200.0 ; + RECT 191800.0 209399.99999999997 192600.00000000003 210200.0 ; + RECT 178200.0 218600.00000000003 179000.0 219399.99999999997 ; + RECT 185000.0 218600.00000000003 185800.0 219399.99999999997 ; + RECT 185000.0 218600.00000000003 185800.0 219399.99999999997 ; + RECT 191800.0 218600.00000000003 192600.00000000003 219399.99999999997 ; + RECT 178200.0 227800.0 179000.0 228600.00000000003 ; + RECT 185000.0 227800.0 185800.0 228600.00000000003 ; + RECT 185000.0 227800.0 185800.0 228600.00000000003 ; + RECT 191800.0 227800.0 192600.00000000003 228600.00000000003 ; + RECT 178200.0 237000.0 179000.0 237800.0 ; + RECT 185000.0 237000.0 185800.0 237800.0 ; + RECT 185000.0 237000.0 185800.0 237800.0 ; + RECT 191800.0 237000.0 192600.00000000003 237800.0 ; + RECT 178200.0 246200.0 179000.0 247000.0 ; + RECT 185000.0 246200.0 185800.0 247000.0 ; + RECT 185000.0 246200.0 185800.0 247000.0 ; + RECT 191800.0 246200.0 192600.00000000003 247000.0 ; + RECT 178200.0 255399.99999999997 179000.0 256200.0 ; + RECT 185000.0 255399.99999999997 185800.0 256200.0 ; + RECT 185000.0 255399.99999999997 185800.0 256200.0 ; + RECT 191800.0 255399.99999999997 192600.00000000003 256200.0 ; + RECT 178200.0 264600.0 179000.0 265400.00000000006 ; + RECT 185000.0 264600.0 185800.0 265400.00000000006 ; + RECT 185000.0 264600.0 185800.0 265400.00000000006 ; + RECT 191800.0 264600.0 192600.00000000003 265400.00000000006 ; + RECT 179800.0 122000.0 180600.00000000003 271000.0 ; + RECT 183400.0 122800.00000000001 184200.0 271800.0 ; + RECT 186600.00000000003 122000.0 187400.0 271000.0 ; + RECT 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RECT 130199.99999999999 210300.0 130800.00000000001 209700.0 ; + RECT 128600.0 210000.0 129199.99999999999 207700.0 ; + RECT 128900.0 210300.0 130500.0 209700.0 ; + RECT 130199.99999999999 212700.0 130800.00000000001 210000.0 ; + RECT 128500.0 207700.0 129300.00000000001 206899.99999999997 ; + RECT 130100.0 213500.0 130900.0 212700.0 ; + RECT 130900.0 210399.99999999997 130100.0 209600.00000000003 ; + RECT 128600.0 219300.0 129199.99999999999 219899.99999999997 ; + RECT 130199.99999999999 219300.0 130800.00000000001 219899.99999999997 ; + RECT 128600.0 219600.00000000003 129199.99999999999 221899.99999999997 ; + RECT 128900.0 219300.0 130500.0 219899.99999999997 ; + RECT 130199.99999999999 216899.99999999997 130800.00000000001 219600.00000000003 ; + RECT 128500.0 221899.99999999997 129300.00000000001 222700.0 ; + RECT 130100.0 216100.00000000003 130900.0 216899.99999999997 ; + RECT 130900.0 219200.0 130100.0 220000.0 ; + RECT 128600.0 228700.0 129199.99999999999 228100.00000000003 ; + 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131600.00000000003 130100.00000000003 132400.0 ; + RECT 130900.0 131600.00000000003 130100.00000000003 132400.0 ; + RECT 130900.0 122400.0 130100.00000000003 123200.0 ; + RECT 130900.0 122400.0 130100.00000000003 123200.0 ; + RECT 130900.0 131600.00000000003 130100.00000000003 132400.0 ; + RECT 130900.0 131600.00000000003 130100.00000000003 132400.0 ; + RECT 130900.0 140800.0 130100.00000000003 141600.00000000003 ; + RECT 130900.0 140800.0 130100.00000000003 141600.00000000003 ; + RECT 130900.0 150000.0 130100.00000000003 150800.0 ; + RECT 130900.0 150000.0 130100.00000000003 150800.0 ; + RECT 130900.0 140800.0 130100.00000000003 141600.00000000003 ; + RECT 130900.0 140800.0 130100.00000000003 141600.00000000003 ; + RECT 130900.0 150000.0 130100.00000000003 150800.0 ; + RECT 130900.0 150000.0 130100.00000000003 150800.0 ; + RECT 130900.0 159200.0 130100.00000000003 160000.0 ; + RECT 130900.0 159200.0 130100.00000000003 160000.0 ; + RECT 130900.0 168399.99999999997 130100.00000000003 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148100.0 ; + RECT 3200.0 147300.0 4000.0 148100.0 ; + RECT 8000.0 156100.0 8800.0 156900.0 ; + RECT 8000.0 156100.0 8800.0 156900.0 ; + RECT 14400.0 156100.0 15200.000000000002 156900.0 ; + RECT 14400.0 156100.0 15200.000000000002 156900.0 ; + RECT 20800.0 156100.0 21600.0 156900.0 ; + RECT 20800.0 156100.0 21600.0 156900.0 ; + RECT 1600.0 156100.0 2400.0000000000005 156900.0 ; + RECT 3200.0 156100.0 4000.0 156900.0 ; + RECT 3200.0 156100.0 4000.0 156900.0 ; + RECT 8000.0 165700.00000000003 8800.0 166500.0 ; + RECT 8000.0 165700.00000000003 8800.0 166500.0 ; + RECT 14400.0 165700.00000000003 15200.000000000002 166500.0 ; + RECT 14400.0 165700.00000000003 15200.000000000002 166500.0 ; + RECT 20800.0 165700.00000000003 21600.0 166500.0 ; + RECT 20800.0 165700.00000000003 21600.0 166500.0 ; + RECT 1600.0 165700.00000000003 2400.0000000000005 166500.0 ; + RECT 3200.0 165700.00000000003 4000.0 166500.0 ; + RECT 3200.0 165700.00000000003 4000.0 166500.0 ; + RECT 13200.000000000002 142500.0 12400.0 143300.0 ; + RECT 13200.000000000002 142500.0 12400.0 143300.0 ; + RECT 13200.000000000002 133300.0 12400.0 134100.00000000003 ; + RECT 13200.000000000002 133300.0 12400.0 134100.00000000003 ; + RECT 19600.0 142500.0 18800.0 143300.0 ; + RECT 19600.0 142500.0 18800.0 143300.0 ; + RECT 19600.0 133300.0 18800.0 134100.00000000003 ; + RECT 19600.0 133300.0 18800.0 134100.00000000003 ; + RECT 13200.000000000002 160900.0 12400.0 161700.00000000003 ; + RECT 13200.000000000002 160900.0 12400.0 161700.00000000003 ; + RECT 13200.000000000002 151700.00000000003 12400.0 152500.0 ; + RECT 13200.000000000002 151700.00000000003 12400.0 152500.0 ; + RECT 19600.0 160900.0 18800.0 161700.00000000003 ; + RECT 19600.0 160900.0 18800.0 161700.00000000003 ; + RECT 19600.0 151700.00000000003 18800.0 152500.0 ; + RECT 19600.0 151700.00000000003 18800.0 152500.0 ; + RECT 13200.000000000002 170100.0 12400.0 170900.0 ; + RECT 13200.000000000002 170100.0 12400.0 170900.0 ; + RECT 19600.0 170100.0 18800.0 170900.0 ; + RECT 19600.0 170100.0 18800.0 170900.0 ; + RECT 1600.0 137700.00000000003 2400.0000000000005 138500.0 ; + RECT 20800.0 165700.00000000003 21600.0 166500.0 ; + RECT 1600.0 133700.00000000003 2200.0 138100.00000000003 ; + RECT 22700.000000000004 133700.00000000003 23300.0 166100.0 ; + RECT 28400.000000000004 133700.00000000003 35200.0 124500.0 ; + RECT 28400.000000000004 133700.00000000003 35200.0 142900.0 ; + RECT 28400.000000000004 152100.0 35200.0 142900.0 ; + RECT 28400.000000000004 152100.0 35200.0 161300.0 ; + RECT 28400.000000000004 170500.00000000003 35200.0 161300.0 ; + RECT 28400.000000000004 170500.00000000003 35200.0 179700.00000000003 ; + RECT 28400.000000000004 188900.0 35200.0 179700.00000000003 ; + RECT 28400.000000000004 188900.0 35200.0 198100.0 ; + RECT 28400.000000000004 207300.0 35200.0 198100.0 ; + RECT 31400.000000000004 142500.0 32200.000000000004 143300.0 ; + RECT 31400.000000000004 142500.0 32200.000000000004 143300.0 ; + RECT 31400.000000000004 160900.0 32200.000000000004 161700.00000000003 ; + RECT 31400.000000000004 160900.0 32200.000000000004 161700.00000000003 ; + RECT 31400.000000000004 179300.0 32200.000000000004 180100.0 ; + RECT 31400.000000000004 179300.0 32200.000000000004 180100.0 ; + RECT 31400.000000000004 197700.00000000003 32200.000000000004 198500.0 ; + RECT 31400.000000000004 197700.00000000003 32200.000000000004 198500.0 ; + RECT 28000.000000000004 137900.0 28800.0 138700.00000000003 ; + RECT 34800.00000000001 137900.0 35600.0 138700.00000000003 ; + RECT 28000.000000000004 147100.00000000003 28800.0 147900.0 ; + RECT 34800.00000000001 147100.00000000003 35600.0 147900.0 ; + RECT 28000.000000000004 156300.0 28800.0 157100.0 ; + RECT 34800.00000000001 156300.0 35600.0 157100.0 ; + RECT 28000.000000000004 165500.0 28800.0 166300.0 ; + RECT 34800.00000000001 165500.0 35600.0 166300.0 ; + RECT 28000.000000000004 174700.00000000003 28800.0 175500.0 ; + RECT 34800.00000000001 174700.00000000003 35600.0 175500.0 ; + RECT 28000.000000000004 183900.0 28800.0 184700.00000000003 ; + RECT 34800.00000000001 183900.0 35600.0 184700.00000000003 ; + RECT 28000.000000000004 193100.0 28800.0 193900.0 ; + RECT 34800.00000000001 193100.0 35600.0 193900.0 ; + RECT 28000.000000000004 202300.0 28800.0 203100.0 ; + RECT 34800.00000000001 202300.0 35600.0 203100.0 ; + RECT 29600.0 133300.0 30400.000000000004 208700.00000000003 ; + RECT 33200.0 134100.00000000003 34000.0 209500.0 ; + RECT 6800.000000000001 124100.00000000003 6000.000000000001 124900.0 ; + RECT 6800.000000000001 124100.00000000003 6000.000000000001 124900.0 ; + RECT 31400.000000000004 122700.00000000001 32200.000000000004 123500.0 ; + RECT 31400.000000000004 122700.00000000001 32200.000000000004 123500.0 ; + RECT 28800.0 128700.00000000001 28000.0 129500.0 ; + RECT 28800.0 128700.00000000001 28000.0 129500.0 ; + RECT 35600.0 128700.00000000001 34800.00000000001 129500.0 ; + RECT 35600.0 128700.00000000001 34800.00000000001 129500.0 ; + RECT 37200.0 134700.00000000003 36400.00000000001 135500.0 ; + RECT 37200.0 134700.00000000003 36400.00000000001 135500.0 ; + RECT 37200.0 150300.0 36400.00000000001 151100.0 ; + RECT 37200.0 150300.0 36400.00000000001 151100.0 ; + RECT 37200.0 153100.0 36400.00000000001 153900.0 ; + RECT 37200.0 153100.0 36400.00000000001 153900.0 ; + RECT 37200.0 168700.00000000003 36400.00000000001 169500.0 ; + RECT 37200.0 168700.00000000003 36400.00000000001 169500.0 ; + RECT 37200.0 171500.0 36400.00000000001 172300.0 ; + RECT 37200.0 171500.0 36400.00000000001 172300.0 ; + RECT 37200.0 187100.0 36400.00000000001 187900.0 ; + RECT 37200.0 187100.0 36400.00000000001 187900.0 ; + RECT 37200.0 189900.0 36400.00000000001 190700.00000000003 ; + RECT 37200.0 189900.0 36400.00000000001 190700.00000000003 ; + RECT 37200.0 205500.0 36400.00000000001 206299.99999999997 ; + RECT 37200.0 205500.0 36400.00000000001 206299.99999999997 ; + RECT 16400.000000000004 131300.0 17200.000000000004 132100.00000000003 ; + RECT 17200.000000000004 129100.00000000003 18000.000000000004 129900.0 ; + RECT 17200.000000000004 129100.00000000003 18000.000000000004 129900.0 ; + RECT 15600.000000000002 129100.00000000003 16400.000000000004 129900.0 ; + RECT 8800.0 128900.0 9600.000000000002 129700.00000000001 ; + RECT 1600.0000000000014 124500.0 2199.999999999999 133700.00000000003 ; + RECT 8900.000000000002 124500.0 9500.0 129300.00000000001 ; + RECT 33100.0 28800.000000000004 32300.000000000004 29600.0 ; + RECT 25000.0 28800.000000000004 25800.0 29600.0 ; + RECT 31700.000000000004 49600.0 30900.000000000004 50400.00000000001 ; + RECT 25000.0 49600.0 25800.0 50400.00000000001 ; + RECT 3500.0 62000.00000000001 2700.0 62800.00000000001 ; + RECT 28900.000000000004 62000.00000000001 28100.0 62800.00000000001 ; + RECT 30300.0 64900.00000000001 29500.0 65700.0 ; + RECT 33100.0 63600.0 32300.000000000004 64400.00000000001 ; + RECT 31700.000000000004 62300.00000000001 30900.000000000004 63100.0 ; + RECT 30300.0 94400.0 29500.0 95199.99999999999 ; + RECT 33100.0 95800.00000000001 32300.000000000004 96600.0 ; + RECT 2300.0000000000005 89400.0 1500.0000000000002 90199.99999999999 ; + RECT 48800.00000000001 89400.0 48000.00000000001 90199.99999999999 ; + RECT 48800.00000000001 89400.0 48000.00000000001 90199.99999999999 ; + RECT 9600.000000000002 108400.0 8800.0 109200.00000000001 ; + RECT 28900.000000000004 50000.0 28100.0 50800.00000000001 ; + RECT 51200.0 50000.0 52000.0 50800.00000000001 ; + RECT 30300.0 28400.000000000004 29500.0 29200.000000000004 ; + RECT 51200.0 28400.000000000004 52000.0 29200.000000000004 ; + RECT 70000.0 39200.0 69200.0 40000.0 ; + RECT 70000.0 39200.0 69200.0 40000.0 ; + RECT 70000.0 59200.0 69200.0 60000.0 ; + RECT 70000.0 59200.0 69200.0 60000.0 ; + RECT 70000.0 19200.000000000004 69200.0 20000.0 ; + RECT 70000.0 19200.000000000004 69200.0 20000.0 ; + RECT 70000.0 79200.0 69200.0 80000.0 ; + RECT 70000.0 79200.0 69200.0 80000.0 ; + RECT 70000.0 59200.0 69200.0 60000.0 ; + RECT 70000.0 59200.0 69200.0 60000.0 ; + RECT 70000.0 79200.0 69200.0 80000.0 ; + RECT 70000.0 79200.0 69200.0 80000.0 ; + RECT 70000.0 99200.00000000001 69200.0 100000.0 ; + RECT 70000.0 99200.00000000001 69200.0 100000.0 ; + RECT 70000.0 119200.00000000001 69200.0 120000.0 ; + RECT 70000.0 119200.00000000001 69200.0 120000.0 ; + RECT 70000.0 99200.00000000001 69200.0 100000.0 ; + RECT 70000.0 99200.00000000001 69200.0 100000.0 ; + RECT 7600.000000000001 28200.000000000004 8400.0 29000.0 ; + RECT 7600.000000000001 50200.0 8400.0 51000.0 ; + RECT 36900.0 19600.0 37500.0 29100.0 ; + RECT 51999.99999999999 211900.00000000003 52599.99999999999 291900.00000000006 ; + RECT 49199.99999999999 211900.00000000003 71000.0 231900.00000000003 ; + RECT 49199.99999999999 251900.00000000003 71000.0 231900.00000000003 ; + RECT 49199.99999999999 251900.00000000003 71000.0 271900.00000000006 ; + RECT 49199.99999999999 291900.00000000006 71000.0 271900.00000000006 ; + RECT 60500.0 231500.00000000003 59699.99999999999 232300.00000000003 ; + RECT 60500.0 231500.00000000003 59699.99999999999 232300.00000000003 ; + RECT 60500.0 211500.00000000003 59699.99999999999 212300.00000000003 ; + RECT 60500.0 211500.00000000003 59699.99999999999 212300.00000000003 ; + RECT 60500.0 231500.00000000003 59699.99999999999 232300.00000000003 ; + RECT 60500.0 231500.00000000003 59699.99999999999 232300.00000000003 ; + RECT 60500.0 251500.00000000003 59699.99999999999 252300.00000000003 ; + RECT 60500.0 251500.00000000003 59699.99999999999 252300.00000000003 ; + RECT 60500.0 271500.00000000006 59699.99999999999 272300.0 ; + RECT 60500.0 271500.00000000006 59699.99999999999 272300.0 ; + RECT 60500.0 251500.00000000003 59699.99999999999 252300.00000000003 ; + RECT 60500.0 251500.00000000003 59699.99999999999 252300.00000000003 ; + RECT 60500.0 271500.00000000006 59699.99999999999 272300.0 ; + RECT 60500.0 271500.00000000006 59699.99999999999 272300.0 ; + RECT 60500.0 291500.00000000006 59699.99999999999 292300.00000000006 ; + RECT 60500.0 291500.00000000006 59699.99999999999 292300.00000000006 ; + RECT 51999.99999999999 214900.00000000003 52800.0 215700.00000000006 ; + RECT 56800.0 220500.00000000003 57599.99999999999 221300.00000000003 ; + RECT 56800.0 242500.00000000003 57599.99999999999 243300.00000000003 ; + RECT 56800.0 260500.00000000006 57599.99999999999 261300.00000000006 ; + RECT 56800.0 282500.00000000006 57599.99999999999 283300.00000000006 ; + RECT 68000.0 221300.00000000003 68800.0 222100.00000000003 ; + RECT 68000.0 241700.00000000006 68800.0 242500.00000000003 ; + RECT 68000.0 261300.00000000006 68800.0 262100.00000000003 ; + RECT 68000.0 281700.00000000006 68800.0 282500.00000000006 ; + RECT 181400.00000000003 0.0 182000.00000000003 20000.0 ; + RECT 203200.00000000003 0.0 203800.0 20000.0 ; + RECT 178600.00000000003 0.0 200400.00000000003 20000.0 ; + RECT 200400.00000000003 0.0 222200.00000000003 20000.0 ; + RECT 189900.00000000003 19600.0 189100.00000000003 20400.000000000004 ; + RECT 189900.00000000003 19600.0 189100.00000000003 20400.000000000004 ; + RECT 189900.00000000003 -400.0 189100.00000000003 400.0 ; + RECT 189900.00000000003 -400.0 189100.00000000003 400.0 ; + RECT 211700.00000000003 19600.0 210900.00000000003 20400.000000000004 ; + RECT 211700.00000000003 19600.0 210900.00000000003 20400.000000000004 ; + RECT 211700.00000000003 -400.0 210900.00000000003 400.0 ; + RECT 211700.00000000003 -400.0 210900.00000000003 400.0 ; + RECT 181400.00000000003 3000.0 182200.00000000003 3800.0 ; + RECT 203200.00000000003 3000.0 204000.00000000003 3800.0 ; + RECT 186200.00000000003 8600.0 187000.00000000003 9400.0 ; + RECT 208000.00000000003 8600.0 208800.0 9400.0 ; + RECT 197400.00000000003 9400.0 198200.00000000003 10200.000000000002 ; + RECT 219200.00000000003 9400.0 220000.00000000003 10200.000000000002 ; + RECT 173100.00000000003 3000.0 172300.0 3800.0 ; + RECT 72800.0 214900.00000000003 72000.0 215700.00000000006 ; + RECT 72800.0 50000.0 72000.0 50800.0 ; + RECT 177300.0 108400.0 176500.0 109200.0 ; + RECT 71399.99999999999 108400.0 70600.0 109200.0 ; + RECT 71399.99999999999 108400.0 70600.0 109200.0 ; + RECT 175900.0 68400.0 175100.0 69200.0 ; + RECT 71399.99999999999 68400.0 70600.0 69200.0 ; + RECT 71399.99999999999 68400.0 70600.0 69200.0 ; + RECT 174500.0 28400.000000000004 173700.0 29200.000000000004 ; + RECT 71399.99999999999 28400.000000000004 70600.0 29200.000000000004 ; + RECT 71399.99999999999 28400.000000000004 70600.0 29200.000000000004 ; + RECT 173100.00000000003 50000.0 172300.0 50800.0 ; + RECT 71399.99999999999 50000.0 70600.0 50800.0 ; + RECT 71399.99999999999 50000.0 70600.0 50800.0 ; + RECT 74600.0 221300.0 73800.0 222100.00000000003 ; + RECT 68800.0 221300.0 68000.0 222100.00000000003 ; + RECT 76000.0 241700.0 75200.0 242500.0 ; + RECT 68800.0 241700.0 68000.0 242500.0 ; + RECT 77399.99999999999 261300.0 76600.0 262100.00000000003 ; + RECT 68800.0 261300.0 68000.0 262100.00000000003 ; + RECT 78800.0 281700.0 78000.0 282500.0 ; + RECT 68800.0 281700.0 68000.0 282500.0 ; + RECT 182400.0 22400.000000000004 181600.0 23200.000000000004 ; + RECT 198200.0 22400.000000000004 197399.99999999997 23200.000000000004 ; + RECT 189200.0 23800.000000000004 188399.99999999997 24600.000000000004 ; + RECT 220000.0 23800.000000000004 219200.0 24600.000000000004 ; + LAYER metal3 ; + RECT 172700.0 3100.0000000000014 200399.99999999997 3700.0000000000014 ; + RECT 71000.0 215000.0 72400.0 215600.0 ; + RECT 71000.0 50100.00000000001 72400.0 50700.00000000001 ; + RECT 71000.0 108500.00000000001 176900.0 109100.00000000001 ; + RECT 71000.0 68500.0 175500.0 69100.0 ; + RECT 71000.0 28500.000000000004 174100.00000000003 29100.000000000004 ; + RECT 71000.0 50100.00000000001 172700.0 50700.00000000001 ; + RECT 68399.99999999999 221400.00000000003 74199.99999999999 222000.00000000003 ; + RECT 68399.99999999999 241800.0 75600.0 242400.0 ; + RECT 68399.99999999999 261400.00000000003 76999.99999999999 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212100.00000000003 22500.0 ; + RECT -900.0 37500.0 900.0 41700.0 ; + RECT 128700.00000000001 222300.0 132900.0 226500.0 ; + RECT 186300.0 111900.0 190500.0 113700.0 ; + RECT 107100.00000000001 167100.00000000003 108900.0 171300.0 ; + RECT 18300.0 140700.00000000003 20100.0 144900.0 ; + RECT 128700.00000000001 203100.00000000003 132900.0 207300.0 ; + RECT 87900.0 186300.0 92100.00000000001 188100.00000000003 ; + RECT 59100.0 270300.0 60900.0 274500.0 ; + RECT 107100.00000000001 131100.0 108900.0 132900.0 ; + RECT 128700.00000000001 147900.0 132900.0 152100.0 ; + RECT 188700.00000000003 18300.0 190500.00000000003 22500.0 ; + RECT 11100.000000000002 159900.0 15300.0 164100.0 ; + RECT 68700.0 78300.00000000001 70500.0 80100.00000000001 ; + RECT 3900.0000000000005 123900.0 8100.000000000002 125700.0 ; + RECT 128700.00000000001 258300.0 132900.0 262500.0 ; + RECT 107100.00000000001 147900.0 108900.0 152100.0 ; + RECT 162300.0 241500.0 166500.0 243300.0 ; + RECT 186300.0 186300.0 190500.0 188100.00000000003 ; + RECT 183900.0 80700.0 185700.00000000003 82500.0 ; + RECT 30300.0 179100.00000000003 34500.0 180900.00000000003 ; + RECT 181500.0 203100.00000000003 183300.0 207300.0 ; + RECT 186300.0 131100.0 190500.0 132900.0 ; + RECT 152700.00000000003 203100.00000000003 156900.0 207300.0 ; + RECT 152700.00000000003 258300.0 156900.0 262500.0 ; + RECT 152700.00000000003 167100.00000000003 156900.0 171300.0 ; + RECT 181500.0 222300.0 183300.0 224100.00000000003 ; + RECT 181500.0 147900.0 183300.0 152100.0 ; + RECT 162300.0 203100.00000000003 166500.0 207300.0 ; + RECT 30300.0 140700.00000000003 34500.0 144900.0 ; + RECT 162300.0 186300.0 166500.0 188100.00000000003 ; + RECT 181500.0 30300.0 183300.0 32100.0 ; + RECT 186300.0 47100.0 190500.0 48900.0 ; + RECT 162300.0 147900.0 166500.0 152100.0 ; + RECT 162300.0 167100.00000000003 166500.0 171300.0 ; + RECT 188700.00000000003 30300.0 190500.00000000003 32100.0 ; + RECT 186300.0 167100.00000000003 190500.0 168900.00000000003 ; + RECT 152700.00000000003 131100.0 156900.0 132900.0 ; + RECT 30300.0 195900.0 34500.0 200100.0 ; + RECT 181500.0 47100.0 183300.0 48900.0 ; + RECT 152700.00000000003 241500.0 156900.0 243300.0 ; + RECT 30300.0 159900.0 34500.0 164100.0 ; + RECT 181500.0 131100.0 183300.0 132900.0 ; + RECT 162300.0 131100.0 166500.0 132900.0 ; + RECT 162300.0 222300.0 166500.0 226500.0 ; + RECT 186300.0 147900.0 190500.0 152100.0 ; + RECT 188700.00000000003 80700.0 192900.0 82500.0 ; + RECT 186300.0 241500.0 190500.0 243300.0 ; + RECT 186300.0 203100.00000000003 190500.0 207300.0 ; + RECT 181500.0 258300.0 183300.0 262500.0 ; + RECT 186300.0 258300.0 190500.0 262500.0 ; + RECT 181500.0 241500.0 183300.0 243300.0 ; + RECT 152700.00000000003 186300.0 156900.0 188100.00000000003 ; + RECT 152700.00000000003 222300.0 156900.0 226500.0 ; + RECT 181500.0 167100.00000000003 183300.0 168900.00000000003 ; + RECT 186300.0 222300.0 190500.0 224100.00000000003 ; + RECT 181500.0 186300.0 183300.0 188100.00000000003 ; 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212700.00000000003 132900.0 216900.0 ; + RECT 11100.000000000002 131100.0 15300.0 135299.99999999997 ; + RECT 32700.000000000004 128700.00000000001 36900.00000000001 130500.00000000003 ; + RECT 128700.00000000001 121500.0 132900.0 123300.0 ; + RECT 11100.000000000002 169500.0 15300.0 171300.0 ; + RECT 87900.0 157500.0 92100.00000000001 161700.0 ; + RECT 18300.0 131100.0 20100.0 135299.99999999997 ; + RECT 18300.0 169500.0 20100.0 171300.0 ; + RECT 11100.000000000002 150300.0 15300.0 154500.0 ; + RECT 210300.0 -900.0 212100.00000000003 900.0 ; + RECT 107100.00000000001 157500.0 108900.0 161700.0 ; + RECT 68700.0 97500.0 70500.0 101700.0 ; + RECT -900.0 18300.0 900.0 20100.0 ; + RECT 68700.0 59100.0 70500.0 60900.0 ; + RECT 107100.00000000001 195900.0 108900.0 197700.00000000003 ; + RECT 128700.00000000001 176700.00000000003 132900.0 178500.00000000003 ; + RECT 87900.0 121500.0 92100.00000000001 123300.0 ; + RECT 128700.00000000001 267900.00000000006 132900.0 272100.0 ; + RECT 128700.00000000001 140700.00000000003 132900.0 142500.00000000003 ; + RECT 107100.00000000001 121500.0 108900.0 123300.0 ; + RECT -900.0 59100.0 900.0 60900.0 ; + RECT 128700.00000000001 251100.00000000003 132900.0 252900.00000000003 ; + RECT 128700.00000000001 231900.0 132900.0 233700.00000000003 ; + RECT 191100.00000000003 198300.0 192900.00000000003 202500.0 ; + RECT 183900.0 236700.00000000003 188100.0 238500.00000000003 ; + RECT 191100.00000000003 253500.0 192900.00000000003 257700.0 ; + RECT 183900.0 207900.0 188100.0 212100.0 ; + RECT 176700.00000000003 171900.0 180900.0 173700.00000000003 ; + RECT 191100.00000000003 236700.00000000003 192900.00000000003 238500.00000000003 ; + RECT 162300.0 231900.0 166500.0 233700.00000000003 ; + RECT 183900.0 198300.0 188100.0 202500.0 ; + RECT 191100.00000000003 263100.0 192900.00000000003 267300.0 ; + RECT 176700.00000000003 152700.00000000003 180900.0 156900.0 ; + RECT 183900.0 263100.0 188100.0 267300.0 ; + RECT 183900.0 143100.0 188100.0 147299.99999999997 ; + RECT 176700.00000000003 243900.0 180900.0 248100.0 ; + RECT 183900.0 227100.00000000003 188100.0 228900.00000000003 ; + RECT 176700.00000000003 227100.00000000003 180900.0 228900.00000000003 ; + RECT 183900.0 133500.0 188100.0 137700.0 ; + RECT 162300.0 195900.0 166500.0 197700.00000000003 ; + RECT 191100.00000000003 227100.00000000003 192900.00000000003 228900.00000000003 ; + RECT 183900.0 243900.0 188100.0 248100.0 ; + RECT 188700.00000000003 54300.00000000001 192900.0 56100.0 ; + RECT 191100.00000000003 188700.00000000003 192900.00000000003 192900.0 ; + RECT 191100.00000000003 143100.0 192900.00000000003 147299.99999999997 ; + RECT 152700.00000000003 140700.00000000003 156900.0 142500.00000000003 ; + RECT 27900.000000000004 155100.00000000003 29700.000000000004 159300.0 ; + RECT 191100.00000000003 162300.0 192900.00000000003 166500.0 ; + RECT 176700.00000000003 236700.00000000003 180900.0 238500.00000000003 ; + RECT 176700.00000000003 253500.0 180900.0 257700.0 ; + RECT 162300.0 157500.0 166500.0 161700.0 ; + RECT 162300.0 251100.00000000003 166500.0 252900.00000000003 ; + RECT 152700.00000000003 267900.00000000006 156900.0 272100.0 ; + RECT 176700.00000000003 207900.0 180900.0 212100.0 ; + RECT 191100.00000000003 92700.0 192900.00000000003 96900.0 ; + RECT 152700.00000000003 176700.00000000003 156900.0 178500.00000000003 ; + RECT 176700.00000000003 126300.00000000001 180900.0 128100.00000000003 ; + RECT 176700.00000000003 162300.0 180900.0 166500.0 ; + RECT 176700.00000000003 217500.0 180900.0 221700.0 ; + RECT 191100.00000000003 181500.0 192900.00000000003 183300.0 ; + RECT 183900.0 217500.0 188100.0 221700.0 ; + RECT 27900.000000000004 145500.0 29700.000000000004 149700.0 ; + RECT 191100.00000000003 126300.00000000001 192900.00000000003 128100.00000000003 ; + RECT 152700.00000000003 251100.00000000003 156900.0 252900.00000000003 ; + RECT 191100.00000000003 133500.0 192900.00000000003 137700.0 ; + RECT 176700.00000000003 133500.0 180900.0 137700.0 ; + RECT 176700.00000000003 181500.0 180900.0 183300.0 ; + RECT 162300.0 176700.00000000003 166500.0 178500.00000000003 ; + RECT 191100.00000000003 207900.0 192900.00000000003 212100.0 ; + RECT 162300.0 212700.00000000003 166500.0 216900.0 ; + RECT 183900.0 253500.0 188100.0 257700.0 ; + RECT 162300.0 121500.0 166500.0 123300.0 ; + RECT 176700.00000000003 188700.00000000003 180900.0 192900.0 ; + RECT 183900.0 126300.00000000001 188100.0 128100.00000000003 ; + RECT 183900.0 181500.0 188100.0 183300.0 ; + RECT 152700.00000000003 121500.0 156900.0 123300.0 ; + RECT 176700.00000000003 263100.0 180900.0 267300.0 ; + RECT 152700.00000000003 231900.0 156900.0 233700.00000000003 ; + RECT 27900.000000000004 164700.00000000003 29700.000000000004 166500.00000000003 ; + RECT 162300.0 140700.00000000003 166500.0 142500.00000000003 ; + RECT 191100.00000000003 243900.0 192900.00000000003 248100.0 ; + RECT 191100.00000000003 152700.00000000003 192900.00000000003 156900.0 ; + RECT 27900.000000000004 200700.00000000003 29700.000000000004 204900.0 ; + RECT 176700.00000000003 198300.0 180900.0 202500.0 ; + RECT 191100.00000000003 171900.0 192900.00000000003 173700.00000000003 ; + RECT 27900.000000000004 135900.0 29700.000000000004 140100.0 ; + RECT 152700.00000000003 157500.0 156900.0 161700.0 ; + RECT 152700.00000000003 212700.00000000003 156900.0 216900.0 ; + RECT 183900.0 152700.00000000003 188100.0 156900.0 ; + RECT 27900.000000000004 174300.0 29700.000000000004 176100.00000000003 ; + RECT 183900.0 162300.0 188100.0 166500.0 ; + RECT 176700.00000000003 143100.0 180900.0 147299.99999999997 ; + RECT 183900.0 188700.00000000003 188100.0 192900.0 ; + RECT 27900.000000000004 181500.0 29700.000000000004 185700.0 ; + RECT 191100.00000000003 217500.0 192900.00000000003 221700.0 ; + RECT 27900.000000000004 191100.00000000003 29700.000000000004 195300.0 ; + RECT 181500.0 54300.00000000001 185700.0 56100.0 ; + RECT 162300.0 267900.00000000006 166500.0 272100.0 ; + RECT 183900.0 171900.0 188100.0 173700.00000000003 ; + RECT 183900.0 92700.0 188100.0 96900.0 ; + RECT 152700.00000000003 195900.0 156900.0 197700.00000000003 ; + RECT 35100.0 205500.0 39300.00000000001 207300.0 ; + RECT 35100.0 200700.00000000003 36900.0 207300.0 ; + RECT 32700.000000000004 200700.00000000003 36900.00000000001 204900.0 ; + RECT 35100.0 133500.0 36900.0 140100.0 ; + RECT 35100.0 133500.0 39300.00000000001 137700.0 ; + RECT 32700.000000000004 135900.0 36900.00000000001 140100.0 ; + RECT 32700.000000000004 135900.0 39300.00000000001 137700.00000000003 ; + RECT 188700.00000000003 35100.0 190500.00000000003 44100.0 ; + RECT 188700.00000000003 39900.00000000001 192900.0 44100.00000000001 ; + RECT 181500.0 35100.0 183300.0 44100.0 ; + RECT 181500.0 39900.00000000001 185700.0 44100.00000000001 ; + RECT 32700.000000000004 174300.0 36900.00000000001 176100.00000000003 ; + RECT 32700.000000000004 164700.00000000003 36900.00000000001 166500.00000000003 ; + RECT 35100.0 167100.00000000003 39300.00000000001 173700.00000000003 ; + RECT 35100.0 164700.00000000003 36900.0 176100.00000000003 ; + RECT 35100.0 186300.0 39300.00000000001 192900.0 ; + RECT 32700.000000000004 191100.00000000003 36900.00000000001 195300.0 ; + RECT 32700.000000000004 191100.00000000003 39300.00000000001 192900.00000000003 ; + RECT 35100.0 181500.0 36900.0 195300.0 ; + RECT 32700.000000000004 181500.0 36900.00000000001 185700.0 ; + RECT 35100.0 145500.0 36900.0 159300.0 ; + RECT 32700.000000000004 155100.00000000003 36900.00000000001 159300.0 ; + RECT 32700.000000000004 145500.0 36900.00000000001 149700.0 ; + RECT 35100.0 147900.0 39300.00000000001 154500.0 ; + RECT 32700.000000000004 147900.0 39300.00000000001 149700.00000000003 ; + RECT 15900.0 159900.0 17700.0 161700.00000000003 ; + RECT 16800.0 159900.0 19200.000000000004 161700.00000000003 ; + RECT 18300.0 159900.0 20100.0 161700.00000000003 ; + RECT 15900.0 128700.00000000001 17700.0 130500.00000000003 ; + RECT 59100.0 227100.00000000003 60900.0 228900.00000000003 ; + RECT 59100.0 228000.0 60900.0 230400.0 ; + RECT 59100.0 229500.0 60900.0 231300.0 ; + RECT 59100.0 227100.00000000003 60900.0 228900.00000000003 ; + RECT 68700.0 35100.0 70500.0 36900.0 ; + RECT 68700.0 36000.0 70500.0 38400.0 ; + RECT 68700.0 37500.0 70500.0 39300.0 ; + RECT 68700.0 35100.0 70500.0 36900.0 ; + RECT 13500.0 140700.00000000003 15300.0 142500.00000000003 ; + RECT 104700.0 186300.0 106500.0 188100.00000000003 ; + RECT 105600.00000000001 186300.0 108000.00000000001 188100.00000000003 ; + RECT 107100.00000000001 186300.0 108900.0 188100.00000000003 ; + RECT 104700.0 186300.0 106500.0 188100.00000000003 ; + RECT 131100.0 243900.0 132900.0 245700.00000000003 ; + RECT 131100.0 242400.0 132900.0 244800.0 ; + RECT 131100.0 241500.0 132900.0 243300.0 ; + RECT 131100.0 243900.0 132900.0 245700.00000000003 ; + RECT 210300.0 23100.0 212100.00000000003 24900.000000000004 ; + RECT 210300.0 21600.0 212100.00000000003 24000.0 ; + RECT 210300.0 20700.000000000004 212100.00000000003 22500.000000000004 ; + RECT 210300.0 23100.0 212100.00000000003 24900.000000000004 ; + RECT -900.0 42300.00000000001 900.0 44100.0 ; + RECT -900.0 40800.00000000001 900.0 43200.0 ; + RECT -900.0 39900.00000000001 900.0 41700.0 ; + RECT -900.0 42300.00000000001 900.0 44100.0 ; + RECT 104700.0 167100.00000000003 106500.0 168900.00000000003 ; + RECT 105600.00000000001 167100.00000000003 108000.00000000001 168900.00000000003 ; + RECT 107100.00000000001 167100.00000000003 108900.0 168900.00000000003 ; + RECT 104700.0 167100.00000000003 106500.0 168900.00000000003 ; + RECT 15900.0 140700.00000000003 17700.0 142500.00000000003 ; + RECT 16800.0 140700.00000000003 19200.000000000004 142500.00000000003 ; + RECT 18300.0 140700.00000000003 20100.0 142500.00000000003 ; + RECT 104700.0 131100.0 106500.0 132900.0 ; + RECT 105600.00000000001 131100.0 108000.00000000001 132900.0 ; + RECT 107100.00000000001 131100.0 108900.0 132900.0 ; + RECT 104700.0 131100.0 106500.0 132900.0 ; + RECT 188700.00000000003 15900.0 190500.00000000003 17700.0 ; + RECT 188700.00000000003 16800.0 190500.00000000003 19200.000000000004 ; + RECT 188700.00000000003 18300.0 190500.00000000003 20100.0 ; + RECT 188700.00000000003 15900.0 190500.00000000003 17700.0 ; + RECT 13500.0 159900.0 15300.0 161700.00000000003 ; + RECT 68700.0 80700.0 70500.0 82500.0 ; + RECT 68700.0 79200.0 70500.0 81600.00000000001 ; + RECT 68700.0 78300.00000000001 70500.0 80100.00000000001 ; + RECT 68700.0 80700.0 70500.0 82500.0 ; + RECT 3900.0000000000005 121500.0 5700.0 123300.0 ; + RECT 3900.0000000000005 122400.0 5700.0 124800.00000000001 ; + RECT 3900.0000000000005 123900.0 5700.0 125700.0 ; + RECT 3900.0000000000005 121500.0 5700.0 123300.0 ; + RECT 131100.0 255900.0 132900.0 257700.0 ; + RECT 131100.0 256800.0 132900.0 259200.0 ; + RECT 131100.0 258300.0 132900.0 260100.00000000003 ; + RECT 131100.0 255900.0 132900.0 257700.0 ; + RECT 104700.0 147900.0 106500.0 149700.00000000003 ; + RECT 105600.00000000001 147900.0 108000.00000000001 149700.00000000003 ; + RECT 107100.00000000001 147900.0 108900.0 149700.00000000003 ; + RECT 104700.0 147900.0 106500.0 149700.00000000003 ; + RECT 164700.00000000003 243900.0 166500.00000000003 245700.00000000003 ; + RECT 164700.00000000003 242400.0 166500.00000000003 244800.0 ; + RECT 164700.00000000003 241500.0 166500.00000000003 243300.0 ; + RECT 164700.00000000003 243900.0 166500.00000000003 245700.00000000003 ; + RECT 188700.00000000003 186300.0 190500.00000000003 188100.00000000003 ; + RECT 179100.00000000003 205500.0 180900.00000000003 207300.0 ; + RECT 180000.0 205500.0 182400.0 207300.0 ; + RECT 181500.0 205500.0 183300.0 207300.0 ; + RECT 155100.00000000003 263100.0 156900.00000000003 264900.00000000006 ; + RECT 155100.00000000003 261600.00000000003 156900.00000000003 264000.0 ; + RECT 155100.00000000003 260700.0 156900.00000000003 262500.0 ; + RECT 155100.00000000003 263100.0 156900.00000000003 264900.00000000006 ; + RECT 179100.00000000003 222300.0 180900.00000000003 224100.00000000003 ; + RECT 180000.0 222300.0 182400.0 224100.00000000003 ; + RECT 181500.0 222300.0 183300.0 224100.00000000003 ; + RECT 32700.000000000004 140700.00000000003 34500.0 142500.00000000003 ; + RECT 179100.00000000003 30300.0 180900.00000000003 32100.0 ; + RECT 180000.0 30300.0 182400.0 32100.0 ; + RECT 181500.0 30300.0 183300.0 32100.0 ; + RECT 188700.00000000003 47100.0 190500.00000000003 48900.0 ; + RECT 188700.00000000003 30300.0 190500.00000000003 32100.0 ; + RECT 179100.00000000003 47100.0 180900.00000000003 48900.0 ; + RECT 180000.0 47100.0 182400.0 48900.0 ; + RECT 181500.0 47100.0 183300.0 48900.0 ; + RECT 155100.00000000003 243900.0 156900.00000000003 245700.00000000003 ; + RECT 155100.00000000003 242400.0 156900.00000000003 244800.0 ; + RECT 155100.00000000003 241500.0 156900.00000000003 243300.0 ; + RECT 155100.00000000003 243900.0 156900.00000000003 245700.00000000003 ; + RECT 32700.000000000004 159900.0 34500.0 161700.00000000003 ; + RECT 188700.00000000003 241500.0 190500.00000000003 243300.0 ; + RECT 188700.00000000003 205500.0 190500.00000000003 207300.0 ; + RECT 179100.00000000003 260700.0 180900.00000000003 262500.0 ; + RECT 180000.0 260700.0 182400.0 262500.0 ; + RECT 181500.0 260700.0 183300.0 262500.0 ; + RECT 188700.00000000003 260700.0 190500.00000000003 262500.0 ; + RECT 179100.00000000003 241500.0 180900.00000000003 243300.0 ; + RECT 180000.0 241500.0 182400.0 243300.0 ; + RECT 181500.0 241500.0 183300.0 243300.0 ; + RECT 188700.00000000003 222300.0 190500.00000000003 224100.00000000003 ; + RECT 179100.00000000003 186300.0 180900.00000000003 188100.00000000003 ; + RECT 180000.0 186300.0 182400.0 188100.00000000003 ; + RECT 181500.0 186300.0 183300.0 188100.00000000003 ; + RECT 164700.00000000003 263100.0 166500.00000000003 264900.00000000006 ; + RECT 164700.00000000003 261600.00000000003 166500.00000000003 264000.0 ; + RECT 164700.00000000003 260700.0 166500.00000000003 262500.0 ; + RECT 164700.00000000003 263100.0 166500.00000000003 264900.00000000006 ; + RECT 87900.0 143100.0 89700.0 144900.0 ; + RECT 87900.0 141600.0 89700.0 144000.0 ; + RECT 87900.0 140700.00000000003 89700.0 142500.00000000003 ; + RECT 87900.0 143100.0 89700.0 144900.0 ; + RECT 107100.00000000001 143100.0 108900.0 144900.0 ; + RECT 107100.00000000001 141600.0 108900.0 144000.0 ; + RECT 107100.00000000001 140700.00000000003 108900.0 142500.00000000003 ; + RECT 107100.00000000001 143100.0 108900.0 144900.0 ; + RECT 87900.0 193500.0 89700.0 195300.0 ; + RECT 87900.0 194400.0 89700.0 196800.0 ; + RECT 87900.0 195900.0 89700.0 197700.00000000003 ; + RECT 87900.0 193500.0 89700.0 195300.0 ; + RECT 27900.000000000004 128700.00000000001 29700.000000000004 130500.00000000003 ; + RECT 191100.00000000003 -900.0 192900.00000000003 900.0 ; + RECT 189600.00000000003 -900.0 192000.00000000003 900.0 ; + RECT 188700.00000000003 -900.0 190500.00000000003 900.0 ; + RECT 59100.0 210300.0 60900.0 212100.00000000003 ; + RECT 87900.0 174300.0 89700.0 176100.00000000003 ; + RECT 87900.0 175200.00000000003 89700.0 177600.00000000003 ; + RECT 87900.0 176700.00000000003 89700.0 178500.00000000003 ; + RECT 87900.0 174300.0 89700.0 176100.00000000003 ; + RECT 128700.00000000001 193500.0 130500.00000000003 195300.0 ; + RECT 128700.00000000001 194400.0 130500.00000000003 196800.0 ; + RECT 128700.00000000001 195900.0 130500.00000000003 197700.00000000003 ; + RECT 128700.00000000001 193500.0 130500.00000000003 195300.0 ; + RECT 107100.00000000001 174300.0 108900.0 176100.00000000003 ; + RECT 107100.00000000001 175200.00000000003 108900.0 177600.00000000003 ; + RECT 107100.00000000001 176700.00000000003 108900.0 178500.00000000003 ; + RECT 107100.00000000001 174300.0 108900.0 176100.00000000003 ; + RECT 128700.00000000001 155100.00000000003 130500.00000000003 156900.00000000003 ; + RECT 128700.00000000001 156000.0 130500.00000000003 158400.0 ; + RECT 128700.00000000001 157500.0 130500.00000000003 159300.0 ; + RECT 128700.00000000001 155100.00000000003 130500.00000000003 156900.00000000003 ; + RECT 18300.0 152700.00000000003 20100.0 154500.00000000003 ; + RECT 11100.000000000002 133500.0 12900.000000000002 135300.0 ; + RECT 37500.0 128700.00000000001 39300.0 130500.00000000003 ; + RECT 36000.0 128700.00000000001 38400.0 130500.00000000003 ; + RECT 37500.0 126300.00000000001 39300.0 128100.00000000003 ; + RECT 37500.0 127200.0 39300.0 129600.0 ; + RECT 35100.0 128700.00000000001 36900.0 130500.00000000003 ; + RECT 37500.0 126300.00000000001 39300.0 128100.00000000003 ; + RECT 128700.00000000001 123900.0 130500.00000000003 125700.0 ; + RECT 128700.00000000001 122400.0 130500.00000000003 124800.00000000001 ; + RECT 128700.00000000001 121500.0 130500.00000000003 123300.0 ; + RECT 128700.00000000001 123900.0 130500.00000000003 125700.0 ; + RECT 11100.000000000002 171900.0 12900.000000000002 173700.00000000003 ; + RECT 11100.000000000002 170400.0 12900.000000000002 172800.0 ; + RECT 11100.000000000002 169500.0 12900.000000000002 171300.0 ; + RECT 11100.000000000002 171900.0 12900.000000000002 173700.00000000003 ; + RECT 87900.0 162300.0 89700.0 164100.00000000003 ; + RECT 87900.0 160800.0 89700.0 163200.00000000003 ; + RECT 87900.0 159900.0 89700.0 161700.00000000003 ; + RECT 87900.0 162300.0 89700.0 164100.00000000003 ; + RECT 18300.0 133500.0 20100.0 135300.0 ; + RECT 18300.0 171900.0 20100.0 173700.00000000003 ; + RECT 18300.0 170400.0 20100.0 172800.0 ; + RECT 18300.0 169500.0 20100.0 171300.0 ; + RECT 18300.0 171900.0 20100.0 173700.00000000003 ; + RECT 11100.000000000002 150300.0 12900.000000000002 152100.00000000003 ; + RECT 210300.0 -900.0 212100.00000000003 900.0 ; + RECT 107100.00000000001 155100.00000000003 108900.0 156900.00000000003 ; + RECT 107100.00000000001 156000.0 108900.0 158400.0 ; + RECT 107100.00000000001 157500.0 108900.0 159300.0 ; + RECT 107100.00000000001 155100.00000000003 108900.0 156900.00000000003 ; + RECT 107100.00000000001 193500.0 108900.0 195300.0 ; + RECT 107100.00000000001 194400.0 108900.0 196800.0 ; + RECT 107100.00000000001 195900.0 108900.0 197700.00000000003 ; + RECT 107100.00000000001 193500.0 108900.0 195300.0 ; + RECT 128700.00000000001 174300.0 130500.00000000003 176100.00000000003 ; + RECT 128700.00000000001 175200.00000000003 130500.00000000003 177600.00000000003 ; + RECT 128700.00000000001 176700.00000000003 130500.00000000003 178500.00000000003 ; + RECT 128700.00000000001 174300.0 130500.00000000003 176100.00000000003 ; + RECT 87900.0 123900.0 89700.0 125700.0 ; + RECT 87900.0 122400.0 89700.0 124800.00000000001 ; + RECT 87900.0 121500.0 89700.0 123300.0 ; + RECT 87900.0 123900.0 89700.0 125700.0 ; + RECT 128700.00000000001 143100.0 130500.00000000003 144900.0 ; + RECT 128700.00000000001 141600.0 130500.00000000003 144000.0 ; + RECT 128700.00000000001 140700.00000000003 130500.00000000003 142500.00000000003 ; + RECT 128700.00000000001 143100.0 130500.00000000003 144900.0 ; + RECT 107100.00000000001 123900.0 108900.0 125700.0 ; + RECT 107100.00000000001 122400.0 108900.0 124800.00000000001 ; + RECT 107100.00000000001 121500.0 108900.0 123300.0 ; + RECT 107100.00000000001 123900.0 108900.0 125700.0 ; + RECT 191100.00000000003 198300.0 192900.00000000003 200100.00000000003 ; + RECT 183900.0 236700.00000000003 185700.00000000003 238500.00000000003 ; + RECT 191100.00000000003 255900.0 192900.00000000003 257700.0 ; + RECT 191100.00000000003 236700.00000000003 192900.00000000003 238500.00000000003 ; + RECT 183900.0 200700.00000000003 185700.00000000003 202500.00000000003 ; + RECT 191100.00000000003 267900.00000000006 192900.00000000003 269700.00000000006 ; + RECT 191100.00000000003 266400.00000000006 192900.00000000003 268800.0 ; + RECT 191100.00000000003 265500.0 192900.00000000003 267300.0 ; + RECT 191100.00000000003 267900.00000000006 192900.00000000003 269700.00000000006 ; + RECT 183900.0 263100.0 185700.00000000003 264900.00000000006 ; + RECT 176700.00000000003 248700.00000000003 178500.00000000003 250500.00000000003 ; + RECT 176700.00000000003 247200.00000000003 178500.00000000003 249600.00000000003 ; + RECT 176700.00000000003 246300.0 178500.00000000003 248100.00000000003 ; + RECT 176700.00000000003 248700.00000000003 178500.00000000003 250500.00000000003 ; + RECT 183900.0 229500.0 185700.00000000003 231300.0 ; + RECT 183900.0 228000.0 185700.00000000003 230400.0 ; + RECT 183900.0 227100.00000000003 185700.00000000003 228900.00000000003 ; + RECT 183900.0 229500.0 185700.00000000003 231300.0 ; + RECT 176700.00000000003 229500.0 178500.00000000003 231300.0 ; + RECT 176700.00000000003 228000.0 178500.00000000003 230400.0 ; + RECT 176700.00000000003 227100.00000000003 178500.00000000003 228900.00000000003 ; + RECT 176700.00000000003 229500.0 178500.00000000003 231300.0 ; + RECT 162300.0 193500.0 164100.00000000003 195300.0 ; + RECT 162300.0 194400.0 164100.00000000003 196800.0 ; + RECT 162300.0 195900.0 164100.00000000003 197700.00000000003 ; + RECT 162300.0 193500.0 164100.00000000003 195300.0 ; + RECT 191100.00000000003 229500.0 192900.00000000003 231300.0 ; + RECT 191100.00000000003 228000.0 192900.00000000003 230400.0 ; + RECT 191100.00000000003 227100.00000000003 192900.00000000003 228900.00000000003 ; + RECT 191100.00000000003 229500.0 192900.00000000003 231300.0 ; + RECT 183900.0 248700.00000000003 185700.00000000003 250500.00000000003 ; + RECT 183900.0 247200.00000000003 185700.00000000003 249600.00000000003 ; + RECT 183900.0 246300.0 185700.00000000003 248100.00000000003 ; + RECT 183900.0 248700.00000000003 185700.00000000003 250500.00000000003 ; + RECT 191100.00000000003 56700.0 192900.00000000003 58500.0 ; + RECT 191100.00000000003 55200.0 192900.00000000003 57600.0 ; + RECT 191100.00000000003 54300.00000000001 192900.00000000003 56100.0 ; + RECT 191100.00000000003 56700.0 192900.00000000003 58500.0 ; + RECT 152700.00000000003 143100.0 154500.00000000003 144900.0 ; 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152700.00000000003 174300.0 154500.00000000003 176100.00000000003 ; + RECT 152700.00000000003 175200.00000000003 154500.00000000003 177600.00000000003 ; + RECT 152700.00000000003 176700.00000000003 154500.00000000003 178500.00000000003 ; + RECT 152700.00000000003 174300.0 154500.00000000003 176100.00000000003 ; + RECT 174300.0 219900.0 176100.00000000003 221700.00000000003 ; + RECT 175200.00000000003 219900.0 177600.00000000003 221700.00000000003 ; + RECT 176700.00000000003 219900.0 178500.00000000003 221700.00000000003 ; + RECT 183900.0 219900.0 185700.00000000003 221700.00000000003 ; + RECT 27900.000000000004 147900.0 29700.000000000004 149700.00000000003 ; + RECT 162300.0 174300.0 164100.00000000003 176100.00000000003 ; + RECT 162300.0 175200.00000000003 164100.00000000003 177600.00000000003 ; + RECT 162300.0 176700.00000000003 164100.00000000003 178500.00000000003 ; + RECT 162300.0 174300.0 164100.00000000003 176100.00000000003 ; + RECT 183900.0 255900.0 185700.00000000003 257700.0 ; + RECT 162300.0 123900.0 164100.00000000003 125700.0 ; + RECT 162300.0 122400.0 164100.00000000003 124800.00000000001 ; + RECT 162300.0 121500.0 164100.00000000003 123300.0 ; + RECT 162300.0 123900.0 164100.00000000003 125700.0 ; + RECT 152700.00000000003 123900.0 154500.00000000003 125700.0 ; + RECT 152700.00000000003 122400.0 154500.00000000003 124800.00000000001 ; + RECT 152700.00000000003 121500.0 154500.00000000003 123300.0 ; + RECT 152700.00000000003 123900.0 154500.00000000003 125700.0 ; + RECT 179100.00000000003 267900.00000000006 180900.00000000003 269700.00000000006 ; + RECT 179100.00000000003 266400.00000000006 180900.00000000003 268800.0 ; + RECT 179100.00000000003 265500.0 180900.00000000003 267300.0 ; + RECT 179100.00000000003 267900.00000000006 180900.00000000003 269700.00000000006 ; + RECT 27900.000000000004 164700.00000000003 29700.000000000004 166500.00000000003 ; + RECT 162300.0 143100.0 164100.00000000003 144900.0 ; + RECT 162300.0 141600.0 164100.00000000003 144000.0 ; + RECT 162300.0 140700.00000000003 164100.00000000003 142500.00000000003 ; + RECT 162300.0 143100.0 164100.00000000003 144900.0 ; + RECT 191100.00000000003 248700.00000000003 192900.00000000003 250500.00000000003 ; + RECT 191100.00000000003 247200.00000000003 192900.00000000003 249600.00000000003 ; + RECT 191100.00000000003 246300.0 192900.00000000003 248100.00000000003 ; + RECT 191100.00000000003 248700.00000000003 192900.00000000003 250500.00000000003 ; + RECT 181500.0 198300.0 183300.0 200100.00000000003 ; + RECT 180000.0 198300.0 182400.0 200100.00000000003 ; + RECT 179100.00000000003 198300.0 180900.00000000003 200100.00000000003 ; + RECT 152700.00000000003 155100.00000000003 154500.00000000003 156900.00000000003 ; + RECT 152700.00000000003 156000.0 154500.00000000003 158400.0 ; + RECT 152700.00000000003 157500.0 154500.00000000003 159300.0 ; + RECT 152700.00000000003 155100.00000000003 154500.00000000003 156900.00000000003 ; + RECT 191100.00000000003 217500.0 192900.00000000003 219300.0 ; + RECT 181500.0 56700.0 183300.0 58500.0 ; + RECT 181500.0 55200.0 183300.0 57600.0 ; + RECT 181500.0 54300.00000000001 183300.0 56100.0 ; + RECT 181500.0 56700.0 183300.0 58500.0 ; + RECT 152700.00000000003 193500.0 154500.00000000003 195300.0 ; + RECT 152700.00000000003 194400.0 154500.00000000003 196800.0 ; + RECT 152700.00000000003 195900.0 154500.00000000003 197700.00000000003 ; + RECT 152700.00000000003 193500.0 154500.00000000003 195300.0 ; + RECT 181600.00000000003 131200.0 182400.0 132000.0 ; + RECT 188400.0 131200.0 189200.0 132000.0 ; + RECT 181600.00000000003 131200.0 182400.0 132000.0 ; + RECT 188400.0 131200.0 189200.0 132000.0 ; + RECT 181600.00000000003 149600.00000000003 182400.0 150400.0 ; + RECT 188400.0 149600.00000000003 189200.0 150400.0 ; + RECT 181600.00000000003 149600.00000000003 182400.0 150400.0 ; + RECT 188400.0 149600.00000000003 189200.0 150400.0 ; + RECT 181600.00000000003 168000.0 182400.0 168800.0 ; + RECT 188400.0 168000.0 189200.0 168800.0 ; + RECT 181600.00000000003 168000.0 182400.0 168800.0 ; + RECT 188400.0 168000.0 189200.0 168800.0 ; + RECT 181600.00000000003 186399.99999999997 182400.0 187200.0 ; + RECT 188400.0 186399.99999999997 189200.0 187200.0 ; + RECT 181600.00000000003 186399.99999999997 182400.0 187200.0 ; + RECT 188400.0 186399.99999999997 189200.0 187200.0 ; + RECT 181600.00000000003 204800.0 182400.0 205600.00000000003 ; + RECT 188400.0 204800.0 189200.0 205600.00000000003 ; + RECT 181600.00000000003 204800.0 182400.0 205600.00000000003 ; + RECT 188400.0 204800.0 189200.0 205600.00000000003 ; + RECT 181600.00000000003 223200.0 182400.0 224000.0 ; + RECT 188400.0 223200.0 189200.0 224000.0 ; + RECT 181600.00000000003 223200.0 182400.0 224000.0 ; + RECT 188400.0 223200.0 189200.0 224000.0 ; + RECT 181600.00000000003 241600.00000000003 182400.0 242399.99999999997 ; + RECT 188400.0 241600.00000000003 189200.0 242399.99999999997 ; + RECT 181600.00000000003 241600.00000000003 182400.0 242399.99999999997 ; + RECT 188400.0 241600.00000000003 189200.0 242399.99999999997 ; + RECT 181600.00000000003 260000.0 182400.0 260800.0 ; + RECT 188400.0 260000.0 189200.0 260800.0 ; + RECT 181600.00000000003 260000.0 182400.0 260800.0 ; + RECT 188400.0 260000.0 189200.0 260800.0 ; + RECT 178200.0 126600.00000000001 179000.0 127400.0 ; + RECT 185000.0 126600.00000000001 185800.0 127400.0 ; + RECT 185000.0 126600.00000000001 185800.0 127400.0 ; + RECT 191800.0 126600.00000000001 192600.00000000003 127400.0 ; + RECT 178200.0 135800.0 179000.0 136600.00000000003 ; + RECT 185000.0 135800.0 185800.0 136600.00000000003 ; + RECT 185000.0 135800.0 185800.0 136600.00000000003 ; + RECT 191800.0 135800.0 192600.00000000003 136600.00000000003 ; + RECT 178200.0 145000.0 179000.0 145800.0 ; + RECT 185000.0 145000.0 185800.0 145800.0 ; + RECT 185000.0 145000.0 185800.0 145800.0 ; + RECT 191800.0 145000.0 192600.00000000003 145800.0 ; + RECT 178200.0 154200.0 179000.0 155000.0 ; + RECT 185000.0 154200.0 185800.0 155000.0 ; + RECT 185000.0 154200.0 185800.0 155000.0 ; + RECT 191800.0 154200.0 192600.00000000003 155000.0 ; + RECT 178200.0 163399.99999999997 179000.0 164200.0 ; + RECT 185000.0 163399.99999999997 185800.0 164200.0 ; + RECT 185000.0 163399.99999999997 185800.0 164200.0 ; + RECT 191800.0 163399.99999999997 192600.00000000003 164200.0 ; + RECT 178200.0 172600.00000000003 179000.0 173399.99999999997 ; + RECT 185000.0 172600.00000000003 185800.0 173399.99999999997 ; + RECT 185000.0 172600.00000000003 185800.0 173399.99999999997 ; + RECT 191800.0 172600.00000000003 192600.00000000003 173399.99999999997 ; + RECT 178200.0 181800.0 179000.0 182600.00000000003 ; + RECT 185000.0 181800.0 185800.0 182600.00000000003 ; + RECT 185000.0 181800.0 185800.0 182600.00000000003 ; + RECT 191800.0 181800.0 192600.00000000003 182600.00000000003 ; + RECT 178200.0 191000.0 179000.0 191800.0 ; + RECT 185000.0 191000.0 185800.0 191800.0 ; + RECT 185000.0 191000.0 185800.0 191800.0 ; + RECT 191800.0 191000.0 192600.00000000003 191800.0 ; + RECT 178200.0 200200.0 179000.0 201000.0 ; + RECT 185000.0 200200.0 185800.0 201000.0 ; + RECT 185000.0 200200.0 185800.0 201000.0 ; + RECT 191800.0 200200.0 192600.00000000003 201000.0 ; + RECT 178200.0 209399.99999999997 179000.0 210200.0 ; + RECT 185000.0 209399.99999999997 185800.0 210200.0 ; + RECT 185000.0 209399.99999999997 185800.0 210200.0 ; + RECT 191800.0 209399.99999999997 192600.00000000003 210200.0 ; + RECT 178200.0 218600.00000000003 179000.0 219399.99999999997 ; + RECT 185000.0 218600.00000000003 185800.0 219399.99999999997 ; + RECT 185000.0 218600.00000000003 185800.0 219399.99999999997 ; + RECT 191800.0 218600.00000000003 192600.00000000003 219399.99999999997 ; + RECT 178200.0 227800.0 179000.0 228600.00000000003 ; + RECT 185000.0 227800.0 185800.0 228600.00000000003 ; + RECT 185000.0 227800.0 185800.0 228600.00000000003 ; + RECT 191800.0 227800.0 192600.00000000003 228600.00000000003 ; + RECT 178200.0 237000.0 179000.0 237800.0 ; + RECT 185000.0 237000.0 185800.0 237800.0 ; + RECT 185000.0 237000.0 185800.0 237800.0 ; + RECT 191800.0 237000.0 192600.00000000003 237800.0 ; + RECT 178200.0 246200.0 179000.0 247000.0 ; + RECT 185000.0 246200.0 185800.0 247000.0 ; + RECT 185000.0 246200.0 185800.0 247000.0 ; + RECT 191800.0 246200.0 192600.00000000003 247000.0 ; + RECT 178200.0 255399.99999999997 179000.0 256200.0 ; + RECT 185000.0 255399.99999999997 185800.0 256200.0 ; + RECT 185000.0 255399.99999999997 185800.0 256200.0 ; + RECT 191800.0 255399.99999999997 192600.00000000003 256200.0 ; + RECT 178200.0 264600.0 179000.0 265400.00000000006 ; + RECT 185000.0 264600.0 185800.0 265400.00000000006 ; + RECT 185000.0 264600.0 185800.0 265400.00000000006 ; + RECT 191800.0 264600.0 192600.00000000003 265400.00000000006 ; + RECT 181700.0 131300.0 182300.0 131900.0 ; + RECT 188500.0 131300.0 189100.00000000003 131900.0 ; + RECT 181700.0 149700.0 182300.0 150300.0 ; + RECT 188500.0 149700.0 189100.00000000003 150300.0 ; + RECT 181700.0 168100.00000000003 182300.0 168700.0 ; + RECT 188500.0 168100.00000000003 189100.00000000003 168700.0 ; + RECT 181700.0 186500.0 182300.0 187100.00000000003 ; + RECT 188500.0 186500.0 189100.00000000003 187100.00000000003 ; + RECT 181700.0 204899.99999999997 182300.0 205500.0 ; + RECT 188500.0 204899.99999999997 189100.00000000003 205500.0 ; + RECT 181700.0 223300.0 182300.0 223899.99999999997 ; + RECT 188500.0 223300.0 189100.00000000003 223899.99999999997 ; + RECT 181700.0 241700.0 182300.0 242300.0 ; + RECT 188500.0 241700.0 189100.00000000003 242300.0 ; + RECT 181700.0 260100.00000000003 182300.0 260700.0 ; + RECT 188500.0 260100.00000000003 189100.00000000003 260700.0 ; + RECT 178300.0 126700.0 178900.0 127300.00000000001 ; + RECT 185100.00000000003 126700.0 185700.0 127300.00000000001 ; + RECT 191900.0 126700.0 192500.0 127300.00000000001 ; + RECT 178300.0 135900.0 178900.0 136500.0 ; + RECT 185100.00000000003 135900.0 185700.0 136500.0 ; + RECT 191900.0 135900.0 192500.0 136500.0 ; + RECT 178300.0 145100.00000000003 178900.0 145700.0 ; + RECT 185100.00000000003 145100.00000000003 185700.0 145700.0 ; + RECT 191900.0 145100.00000000003 192500.0 145700.0 ; + RECT 178300.0 154300.0 178900.0 154899.99999999997 ; + RECT 185100.00000000003 154300.0 185700.0 154899.99999999997 ; + RECT 191900.0 154300.0 192500.0 154899.99999999997 ; + RECT 178300.0 163500.0 178900.0 164100.00000000003 ; + RECT 185100.00000000003 163500.0 185700.0 164100.00000000003 ; + RECT 191900.0 163500.0 192500.0 164100.00000000003 ; + RECT 178300.0 172700.0 178900.0 173300.0 ; + RECT 185100.00000000003 172700.0 185700.0 173300.0 ; + RECT 191900.0 172700.0 192500.0 173300.0 ; + RECT 178300.0 181899.99999999997 178900.0 182500.0 ; + RECT 185100.00000000003 181899.99999999997 185700.0 182500.0 ; + RECT 191900.0 181899.99999999997 192500.0 182500.0 ; + RECT 178300.0 191100.00000000003 178900.0 191700.0 ; + RECT 185100.00000000003 191100.00000000003 185700.0 191700.0 ; + RECT 191900.0 191100.00000000003 192500.0 191700.0 ; + RECT 178300.0 200300.0 178900.0 200899.99999999997 ; + RECT 185100.00000000003 200300.0 185700.0 200899.99999999997 ; + RECT 191900.0 200300.0 192500.0 200899.99999999997 ; + RECT 178300.0 209500.0 178900.0 210100.00000000003 ; + RECT 185100.00000000003 209500.0 185700.0 210100.00000000003 ; + RECT 191900.0 209500.0 192500.0 210100.00000000003 ; + RECT 178300.0 218700.0 178900.0 219300.0 ; + RECT 185100.00000000003 218700.0 185700.0 219300.0 ; + RECT 191900.0 218700.0 192500.0 219300.0 ; + RECT 178300.0 227899.99999999997 178900.0 228500.0 ; + RECT 185100.00000000003 227899.99999999997 185700.0 228500.0 ; + RECT 191900.0 227899.99999999997 192500.0 228500.0 ; + RECT 178300.0 237100.00000000003 178900.0 237700.0 ; + RECT 185100.00000000003 237100.00000000003 185700.0 237700.0 ; + RECT 191900.0 237100.00000000003 192500.0 237700.0 ; + RECT 178300.0 246300.0 178900.0 246899.99999999997 ; + RECT 185100.00000000003 246300.0 185700.0 246899.99999999997 ; + RECT 191900.0 246300.0 192500.0 246899.99999999997 ; + RECT 178300.0 255500.0 178900.0 256100.00000000003 ; + RECT 185100.00000000003 255500.0 185700.0 256100.00000000003 ; + RECT 191900.0 255500.0 192500.0 256100.00000000003 ; + RECT 178300.0 264700.0 178900.0 265300.0 ; + RECT 185100.00000000003 264700.0 185700.0 265300.0 ; + RECT 191900.0 264700.0 192500.0 265300.0 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 181400.0 112000.00000000001 182200.0 112800.00000000001 ; + RECT 188200.0 112000.00000000001 189000.0 112800.00000000001 ; + RECT 185000.0 95000.00000000001 185800.0 95800.00000000001 ; + RECT 184000.0 81600.00000000001 184800.0 82400.0 ; + RECT 191800.0 95000.00000000001 192600.00000000003 95800.00000000001 ; + RECT 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RECT 164700.0 205200.0 163899.99999999997 206000.0 ; + RECT 155100.0 214400.00000000003 154300.0 215200.0 ; + RECT 164700.0 214400.00000000003 163899.99999999997 215200.0 ; + RECT 155100.0 223600.00000000003 154300.0 224400.00000000003 ; + RECT 164700.0 223600.00000000003 163899.99999999997 224400.00000000003 ; + RECT 155100.0 214400.00000000003 154300.0 215200.0 ; + RECT 164700.0 214400.00000000003 163899.99999999997 215200.0 ; + RECT 155100.0 223600.00000000003 154300.0 224400.00000000003 ; + RECT 164700.0 223600.00000000003 163899.99999999997 224400.00000000003 ; + RECT 155100.0 232800.0 154300.0 233600.00000000003 ; + RECT 164700.0 232800.0 163899.99999999997 233600.00000000003 ; + RECT 155100.0 242000.0 154300.0 242800.0 ; + RECT 164700.0 242000.0 163899.99999999997 242800.0 ; + RECT 155100.0 232800.0 154300.0 233600.00000000003 ; + RECT 164700.0 232800.0 163899.99999999997 233600.00000000003 ; + RECT 155100.0 242000.0 154300.0 242800.0 ; + RECT 164700.0 242000.0 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; + RECT 191900.0 191100.00000000003 192500.0 191700.0 ; + RECT 178300.0 200300.0 178900.0 200899.99999999997 ; + RECT 185100.00000000003 200300.0 185700.0 200899.99999999997 ; + RECT 191900.0 200300.0 192500.0 200899.99999999997 ; + RECT 178300.0 209500.0 178900.0 210100.00000000003 ; + RECT 185100.00000000003 209500.0 185700.0 210100.00000000003 ; + RECT 191900.0 209500.0 192500.0 210100.00000000003 ; + RECT 178300.0 218700.0 178900.0 219300.0 ; + RECT 185100.00000000003 218700.0 185700.0 219300.0 ; + RECT 191900.0 218700.0 192500.0 219300.0 ; + RECT 178300.0 227899.99999999997 178900.0 228500.0 ; + RECT 185100.00000000003 227899.99999999997 185700.0 228500.0 ; + RECT 191900.0 227899.99999999997 192500.0 228500.0 ; + RECT 178300.0 237100.00000000003 178900.0 237700.0 ; + RECT 185100.00000000003 237100.00000000003 185700.0 237700.0 ; + RECT 191900.0 237100.00000000003 192500.0 237700.0 ; + RECT 178300.0 246300.0 178900.0 246899.99999999997 ; + RECT 185100.00000000003 246300.0 185700.0 246899.99999999997 ; + RECT 191900.0 246300.0 192500.0 246899.99999999997 ; + RECT 178300.0 255500.0 178900.0 256100.00000000003 ; + RECT 185100.00000000003 255500.0 185700.0 256100.00000000003 ; + RECT 191900.0 255500.0 192500.0 256100.00000000003 ; + RECT 178300.0 264700.0 178900.0 265300.0 ; + RECT 185100.00000000003 264700.0 185700.0 265300.0 ; + RECT 191900.0 264700.0 192500.0 265300.0 ; + RECT 185100.00000000003 95100.00000000001 185700.0 95700.0 ; + RECT 191900.0 95100.00000000001 192500.0 95700.0 ; + RECT 182500.0 37099.99999999999 183100.00000000003 37700.0 ; + RECT 183900.0 41500.0 184500.0 42099.99999999999 ; + RECT 183300.0 54900.00000000001 183900.0 55500.0 ; + RECT 189300.0 37099.99999999999 189900.0 37700.0 ; + RECT 190700.0 41500.0 191300.0 42099.99999999999 ; + RECT 190100.00000000003 54900.00000000001 190700.0 55500.0 ; + RECT 130100.00000000003 122400.0 130900.0 123200.0 ; + RECT 130100.00000000003 140800.0 130900.0 141600.00000000003 ; + RECT 130100.00000000003 159200.0 130900.0 160000.0 ; + RECT 130100.00000000003 177600.00000000003 130900.0 178399.99999999997 ; + RECT 130100.00000000003 196000.0 130900.0 196800.0 ; + RECT 130100.00000000003 214399.99999999997 130900.0 215200.0 ; + RECT 130100.00000000003 232800.0 130900.0 233600.00000000003 ; + RECT 130100.00000000003 251200.0 130900.0 252000.0 ; + RECT 130100.00000000003 269600.0 130900.0 270400.0 ; + RECT 89700.0 122400.0 90500.0 123200.0 ; + RECT 107700.0 122400.0 108500.0 123200.0 ; + RECT 89700.0 140800.0 90500.0 141600.00000000003 ; + RECT 107700.0 140800.0 108500.0 141600.00000000003 ; + RECT 89700.0 159200.0 90500.0 160000.0 ; + RECT 107700.0 159200.0 108500.0 160000.0 ; + RECT 89700.0 177600.00000000003 90500.0 178399.99999999997 ; + RECT 107700.0 177600.00000000003 108500.0 178399.99999999997 ; + RECT 89700.0 196000.0 90500.0 196800.0 ; + RECT 107700.0 196000.0 108500.0 196800.0 ; + RECT 154400.0 122500.0 155000.0 123100.00000000001 ; + RECT 164000.0 122500.0 164600.00000000003 123100.00000000001 ; + RECT 154400.0 140900.0 155000.0 141500.0 ; + RECT 164000.0 140900.0 164600.00000000003 141500.0 ; + RECT 154400.0 159300.0 155000.0 159899.99999999997 ; + RECT 164000.0 159300.0 164600.00000000003 159899.99999999997 ; + RECT 154400.0 177700.0 155000.0 178300.0 ; + RECT 164000.0 177700.0 164600.00000000003 178300.0 ; + RECT 154400.0 196100.00000000003 155000.0 196700.0 ; + RECT 164000.0 196100.00000000003 164600.00000000003 196700.0 ; + RECT 154400.0 214500.0 155000.0 215100.00000000003 ; + RECT 164000.0 214500.0 164600.00000000003 215100.00000000003 ; + RECT 154400.0 232899.99999999997 155000.0 233500.0 ; + RECT 164000.0 232899.99999999997 164600.00000000003 233500.0 ; + RECT 154400.0 251300.0 155000.0 251899.99999999997 ; + RECT 164000.0 251300.0 164600.00000000003 251899.99999999997 ; + RECT 154400.0 269700.0 155000.0 270300.0 ; + RECT 164000.0 269700.0 164600.00000000003 270300.0 ; + RECT 1900.0000000000002 89500.0 48400.0 90100.0 ; + RECT 28500.0 50100.0 51600.0 50700.0 ; + RECT 29900.000000000004 28500.0 51600.00000000001 29100.0 ; + RECT 21200.000000000004 29100.0 21800.000000000004 29700.000000000004 ; + RECT 21200.000000000004 28900.000000000004 21800.000000000004 29500.0 ; + RECT 19200.000000000004 29100.0 21500.000000000004 29700.000000000004 ; + RECT 21200.000000000004 29200.000000000004 21800.000000000004 29400.000000000004 ; + RECT 21500.0 28900.000000000004 23800.0 29500.0 ; + RECT 18800.0 29000.0 19600.0 29800.000000000004 ; + RECT 23400.000000000004 28800.000000000004 24200.000000000004 29600.0 ; + RECT 21200.000000000004 50100.0 21800.000000000004 49500.0 ; + RECT 21200.000000000004 50300.0 21800.000000000004 49700.0 ; + RECT 19200.000000000004 50100.0 21500.000000000004 49500.0 ; + RECT 21200.000000000004 50000.0 21800.000000000004 49800.0 ; + RECT 21500.0 50300.0 23800.0 49700.0 ; + RECT 18800.0 50200.0 19600.0 49400.0 ; + RECT 23400.000000000004 50400.0 24200.000000000004 49600.0 ; + RECT 400.0 39200.0 -400.0 40000.0 ; + RECT 400.0 19200.000000000004 -400.0 20000.0 ; + RECT 400.0 39200.0 -400.0 40000.0 ; + RECT 400.0 59200.0 -400.0 60000.0 ; + RECT -400.0 39200.0 400.0 40000.0 ; + RECT -400.0 19200.000000000004 400.0 20000.0 ; + RECT -400.0 59200.0 400.0 60000.00000000001 ; + RECT 3600.0 137800.0 21200.000000000004 138400.0 ; + RECT 3600.0 147400.0 21200.000000000004 148000.0 ; + RECT 3600.0 156200.00000000003 21200.000000000004 156800.0 ; + RECT 3600.0 165800.0 21200.000000000004 166400.0 ; + RECT 8000.0 137700.00000000003 8800.0 138500.0 ; + RECT 14400.0 137700.00000000003 15200.000000000002 138500.0 ; + RECT 20800.0 137700.00000000003 21600.0 138500.0 ; + RECT 3200.0 137700.00000000003 4000.0 138500.0 ; + RECT 8000.0 147300.0 8800.0 148100.0 ; + RECT 14400.0 147300.0 15200.000000000002 148100.0 ; + RECT 20800.0 147300.0 21600.0 148100.0 ; + RECT 3200.0 147300.0 4000.0 148100.0 ; + RECT 8000.0 156100.0 8800.0 156900.0 ; + RECT 14400.0 156100.0 15200.000000000002 156900.0 ; + RECT 20800.0 156100.0 21600.0 156900.0 ; + RECT 3200.0 156100.0 4000.0 156900.0 ; + RECT 8000.0 165700.00000000003 8800.0 166500.0 ; + RECT 14400.0 165700.00000000003 15200.000000000002 166500.0 ; + RECT 20800.0 165700.00000000003 21600.0 166500.0 ; + RECT 3200.0 165700.00000000003 4000.0 166500.0 ; + RECT 13200.000000000002 142500.0 12400.0 143300.0 ; + RECT 13200.000000000002 133300.0 12400.0 134100.00000000003 ; + RECT 19600.0 142500.0 18800.0 143300.0 ; + RECT 19600.0 133300.0 18800.0 134100.00000000003 ; + RECT 13200.000000000002 160900.0 12400.0 161700.00000000003 ; + RECT 13200.000000000002 151700.00000000003 12400.0 152500.0 ; + RECT 19600.0 160900.0 18800.0 161700.00000000003 ; + RECT 19600.0 151700.00000000003 18800.0 152500.0 ; + RECT 13200.000000000002 170100.0 12400.0 170900.0 ; + RECT 19600.0 170100.0 18800.0 170900.0 ; + RECT 12400.0 142500.0 13200.000000000002 143300.0 ; + RECT 18800.0 142500.0 19600.0 143300.0 ; + RECT 12400.0 160900.0 13200.000000000002 161700.00000000003 ; + RECT 18800.0 160900.0 19600.0 161700.00000000003 ; + RECT 12400.0 133300.0 13200.000000000002 134100.00000000003 ; + RECT 18800.0 133300.0 19600.0 134100.00000000003 ; + RECT 12400.0 151700.00000000003 13200.000000000002 152500.0 ; + RECT 18800.0 151700.00000000003 19600.0 152500.0 ; + RECT 12400.0 170100.0 13200.000000000002 170900.0 ; + RECT 18800.0 170100.0 19600.0 170900.0 ; + RECT 31400.000000000004 142500.0 32200.000000000004 143300.0 ; + RECT 31400.000000000004 142500.0 32200.000000000004 143300.0 ; + RECT 31400.000000000004 160900.0 32200.000000000004 161700.00000000003 ; + RECT 31400.000000000004 160900.0 32200.000000000004 161700.00000000003 ; + RECT 31400.000000000004 179300.0 32200.000000000004 180100.0 ; + RECT 31400.000000000004 179300.0 32200.000000000004 180100.0 ; + RECT 31400.000000000004 197700.00000000003 32200.000000000004 198500.0 ; + RECT 31400.000000000004 197700.00000000003 32200.000000000004 198500.0 ; + RECT 28000.000000000004 137900.0 28800.0 138700.00000000003 ; + RECT 34800.00000000001 137900.0 35600.0 138700.00000000003 ; + RECT 28000.000000000004 147100.00000000003 28800.0 147900.0 ; + RECT 34800.00000000001 147100.00000000003 35600.0 147900.0 ; + RECT 28000.000000000004 156300.0 28800.0 157100.0 ; + RECT 34800.00000000001 156300.0 35600.0 157100.0 ; + RECT 28000.000000000004 165500.0 28800.0 166300.0 ; + RECT 34800.00000000001 165500.0 35600.0 166300.0 ; + RECT 28000.000000000004 174700.00000000003 28800.0 175500.0 ; + RECT 34800.00000000001 174700.00000000003 35600.0 175500.0 ; + RECT 28000.000000000004 183900.0 28800.0 184700.00000000003 ; + RECT 34800.00000000001 183900.0 35600.0 184700.00000000003 ; + RECT 28000.000000000004 193100.0 28800.0 193900.0 ; + RECT 34800.00000000001 193100.0 35600.0 193900.0 ; + RECT 28000.000000000004 202300.0 28800.0 203100.0 ; + RECT 34800.00000000001 202300.0 35600.0 203100.0 ; + RECT 31500.000000000004 142600.00000000003 32100.0 143200.00000000003 ; + RECT 31500.000000000004 161000.0 32100.0 161600.0 ; + RECT 31500.000000000004 179400.0 32100.0 180000.00000000003 ; + RECT 31500.000000000004 197800.0 32100.0 198400.0 ; + RECT 28100.0 138000.0 28700.000000000004 138600.00000000003 ; + RECT 34900.00000000001 138000.0 35500.0 138600.00000000003 ; + RECT 28100.0 147200.00000000003 28700.000000000004 147800.0 ; + RECT 34900.00000000001 147200.00000000003 35500.0 147800.0 ; + RECT 28100.0 156400.0 28700.000000000004 157000.0 ; + RECT 34900.00000000001 156400.0 35500.0 157000.0 ; + RECT 28100.0 165600.0 28700.000000000004 166200.00000000003 ; + RECT 34900.00000000001 165600.0 35500.0 166200.00000000003 ; + RECT 28100.0 174800.0 28700.000000000004 175400.0 ; + RECT 34900.00000000001 174800.0 35500.0 175400.0 ; + RECT 28100.0 184000.00000000003 28700.000000000004 184600.0 ; + RECT 34900.00000000001 184000.00000000003 35500.0 184600.0 ; + RECT 28100.0 193200.00000000003 28700.000000000004 193800.0 ; + RECT 34900.00000000001 193200.00000000003 35500.0 193800.0 ; + RECT 28100.0 202400.0 28700.000000000004 203000.0 ; + RECT 34900.00000000001 202400.0 35500.0 203000.0 ; + RECT 6800.000000000001 124100.00000000003 6000.000000000001 124900.0 ; + RECT 31400.000000000004 122700.00000000001 32200.000000000004 123500.0 ; + RECT 28800.0 128700.00000000001 28000.0 129500.0 ; + RECT 35600.0 128700.00000000001 34800.00000000001 129500.0 ; + RECT 37200.0 134700.00000000003 36400.00000000001 135500.0 ; + RECT 37200.0 150300.0 36400.00000000001 151100.0 ; + RECT 37200.0 153100.0 36400.00000000001 153900.0 ; + RECT 37200.0 168700.00000000003 36400.00000000001 169500.0 ; + RECT 37200.0 171500.0 36400.00000000001 172300.0 ; + RECT 37200.0 187100.0 36400.00000000001 187900.0 ; + RECT 37200.0 189900.0 36400.00000000001 190700.00000000003 ; + RECT 37200.0 205500.0 36400.00000000001 206299.99999999997 ; + RECT 17200.000000000004 129100.00000000003 18000.000000000004 129900.0 ; + RECT 31500.000000000004 142600.00000000003 32100.0 143200.00000000003 ; + RECT 31500.000000000004 161000.0 32100.0 161600.0 ; + RECT 31500.000000000004 179400.0 32100.0 180000.0 ; + RECT 31500.000000000004 197799.99999999997 32100.0 198400.0 ; + RECT 12400.000000000002 142500.0 13200.000000000002 143300.0 ; + RECT 18800.0 142500.0 19600.0 143300.0 ; + RECT 12400.000000000002 160900.0 13200.000000000002 161700.00000000003 ; + RECT 18800.0 160900.0 19600.0 161700.00000000003 ; + RECT 6000.0 124100.00000000003 6800.000000000001 124900.0 ; + RECT 31400.000000000004 122700.00000000001 32200.000000000004 123500.0 ; + RECT 17200.000000000004 129100.00000000003 18000.0 129900.0 ; + RECT 28100.0 138000.0 28700.000000000004 138600.00000000003 ; + RECT 34900.00000000001 138000.0 35500.0 138600.00000000003 ; + RECT 28100.0 147200.00000000003 28700.000000000004 147800.0 ; + RECT 34900.00000000001 147200.00000000003 35500.0 147800.0 ; + RECT 28100.0 156400.0 28700.000000000004 157000.0 ; + RECT 34900.00000000001 156400.0 35500.0 157000.0 ; + RECT 28100.0 165600.0 28700.000000000004 166200.00000000003 ; + RECT 34900.00000000001 165600.0 35500.0 166200.00000000003 ; + RECT 28100.0 174800.0 28700.000000000004 175400.0 ; + RECT 34900.00000000001 174800.0 35500.0 175400.0 ; + RECT 28100.0 184000.0 28700.000000000004 184600.0 ; + RECT 34900.00000000001 184000.0 35500.0 184600.0 ; + RECT 28100.0 193200.00000000003 28700.000000000004 193799.99999999997 ; + RECT 34900.00000000001 193200.00000000003 35500.0 193799.99999999997 ; + RECT 28100.0 202400.0 28700.000000000004 203000.0 ; + RECT 34900.00000000001 202400.0 35500.0 203000.0 ; + RECT 12400.000000000002 133300.0 13200.000000000002 134100.00000000003 ; + RECT 18800.0 133300.0 19600.0 134100.00000000003 ; + RECT 12400.000000000002 151700.00000000003 13200.000000000002 152500.0 ; + RECT 18800.0 151700.00000000003 19600.0 152500.0 ; + RECT 12400.000000000002 170100.0 13200.000000000002 170900.0 ; + RECT 18800.0 170100.0 19600.0 170900.0 ; + RECT 28000.000000000004 128700.00000000001 28800.0 129500.0 ; + RECT 34800.00000000001 128700.00000000001 35600.0 129500.0 ; + RECT 36400.00000000001 134700.00000000003 37200.0 135500.0 ; + RECT 36400.00000000001 150300.0 37200.0 151100.0 ; + RECT 36400.00000000001 153100.0 37200.0 153900.0 ; + RECT 36400.00000000001 168700.00000000003 37200.0 169500.0 ; + RECT 36400.00000000001 171500.0 37200.0 172300.0 ; + RECT 36400.00000000001 187100.0 37200.0 187900.0 ; + RECT 36400.00000000001 189900.0 37200.0 190700.00000000003 ; + RECT 36400.00000000001 205500.0 37200.0 206300.0 ; + RECT 2300.0000000000005 89400.0 1500.0000000000002 90199.99999999999 ; + RECT 48800.00000000001 89400.0 48000.00000000001 90199.99999999999 ; + RECT 28900.000000000004 50000.0 28100.0 50800.00000000001 ; + RECT 51200.0 50000.0 52000.0 50800.00000000001 ; + RECT 30300.0 28400.000000000004 29500.0 29200.000000000004 ; + RECT 51200.0 28400.000000000004 52000.0 29200.000000000004 ; + RECT 70000.0 39200.0 69200.0 40000.0 ; + RECT 70000.0 59200.0 69200.0 60000.0 ; + RECT 70000.0 19200.000000000004 69200.0 20000.0 ; + RECT 70000.0 79200.0 69200.0 80000.0 ; + RECT 70000.0 59200.0 69200.0 60000.0 ; + RECT 70000.0 79200.0 69200.0 80000.0 ; + RECT 70000.0 99200.00000000001 69200.0 100000.0 ; + RECT 70000.0 119200.00000000001 69200.0 120000.0 ; + RECT 70000.0 99200.00000000001 69200.0 100000.0 ; + RECT 69200.0 39200.0 70000.0 40000.0 ; + RECT 69200.0 79200.0 70000.0 80000.0 ; + RECT 69200.0 119200.00000000001 70000.0 120000.0 ; + RECT 31500.0 142600.0 32100.0 143200.00000000003 ; + RECT 31500.0 161000.0 32100.0 161600.0 ; + RECT 31500.0 179400.0 32100.0 180000.0 ; + RECT 31500.0 197800.0 32100.0 198400.0 ; + RECT 12400.0 142500.0 13200.000000000002 143300.0 ; + RECT 18800.0 142500.0 19600.0 143300.0 ; + RECT 12400.0 160900.0 13200.000000000002 161700.0 ; + RECT 18800.0 160900.0 19600.0 161700.0 ; + RECT 6000.0 124100.0 6800.000000000001 124900.0 ; + RECT 31400.000000000004 122700.00000000001 32200.000000000004 123500.0 ; + RECT 17200.0 129100.0 18000.0 129900.0 ; + RECT -400.0 39200.0 400.0 40000.0 ; + RECT 69200.0 59200.0 70000.0 60000.00000000001 ; + RECT 69200.0 19200.000000000004 70000.0 20000.0 ; + RECT 69200.0 99200.00000000001 70000.0 100000.0 ; + RECT 28100.0 138000.0 28700.000000000004 138600.0 ; + RECT 34900.0 138000.0 35500.0 138600.0 ; + RECT 28100.0 147200.00000000003 28700.000000000004 147800.0 ; + RECT 34900.0 147200.00000000003 35500.0 147800.0 ; + RECT 28100.0 156400.0 28700.000000000004 157000.0 ; + RECT 34900.0 156400.0 35500.0 157000.0 ; + RECT 28100.0 165600.0 28700.000000000004 166200.0 ; + RECT 34900.0 165600.0 35500.0 166200.0 ; + RECT 28100.0 174800.0 28700.000000000004 175400.0 ; + RECT 34900.0 174800.0 35500.0 175400.0 ; + RECT 28100.0 184000.0 28700.000000000004 184600.0 ; + RECT 34900.0 184000.0 35500.0 184600.0 ; + RECT 28100.0 193200.00000000003 28700.000000000004 193800.0 ; + RECT 34900.0 193200.00000000003 35500.0 193800.0 ; + RECT 28100.0 202400.0 28700.000000000004 203000.0 ; + RECT 34900.0 202400.0 35500.0 203000.0 ; + RECT 12400.0 133300.0 13200.000000000002 134100.0 ; + RECT 18800.0 133300.0 19600.0 134100.0 ; + RECT 12400.0 151700.0 13200.000000000002 152500.0 ; + RECT 18800.0 151700.0 19600.0 152500.0 ; + RECT 12400.0 170100.0 13200.000000000002 170900.0 ; + RECT 18800.0 170100.0 19600.0 170900.0 ; + RECT 28000.0 128700.00000000001 28800.0 129500.0 ; + RECT 34800.00000000001 128700.00000000001 35600.0 129500.0 ; + RECT 36400.0 134700.00000000003 37200.0 135500.0 ; + RECT 36400.0 150300.0 37200.0 151100.0 ; + RECT 36400.0 153100.0 37200.0 153900.0 ; + RECT 36400.0 168700.0 37200.0 169500.0 ; + RECT 36400.0 171500.0 37200.0 172300.0 ; + RECT 36400.0 187100.0 37200.0 187900.0 ; + RECT 36400.0 189900.0 37200.0 190700.00000000003 ; + RECT 36400.0 205500.0 37200.0 206300.0 ; + RECT -400.0 19200.000000000004 400.0 20000.0 ; + RECT -400.0 59200.0 400.0 60000.00000000001 ; + RECT 60500.0 231500.00000000003 59699.99999999999 232300.00000000003 ; + RECT 60500.0 211500.00000000003 59699.99999999999 212300.00000000003 ; + RECT 60500.0 231500.00000000003 59699.99999999999 232300.00000000003 ; + RECT 60500.0 251500.00000000003 59699.99999999999 252300.00000000003 ; + RECT 60500.0 271500.00000000006 59699.99999999999 272300.0 ; + RECT 60500.0 251500.00000000003 59699.99999999999 252300.00000000003 ; + RECT 60500.0 271500.00000000006 59699.99999999999 272300.0 ; + RECT 60500.0 291500.00000000006 59699.99999999999 292300.00000000006 ; + RECT 51999.99999999999 214900.00000000003 52800.0 215700.00000000006 ; + RECT 49199.99999999999 215000.00000000003 71000.0 215600.00000000003 ; + RECT 59699.99999999999 231500.00000000003 60500.0 232300.00000000003 ; + RECT 59699.99999999999 271500.00000000006 60500.0 272300.00000000006 ; + RECT 59699.99999999999 211500.00000000003 60500.0 212300.00000000003 ; + RECT 59699.99999999999 251500.00000000003 60500.0 252300.00000000003 ; + RECT 59699.99999999999 291500.00000000006 60500.0 292300.00000000006 ; + RECT 189900.00000000003 19600.0 189100.00000000003 20400.000000000004 ; + RECT 189900.00000000003 -400.0 189100.00000000003 400.0 ; + RECT 211700.00000000003 19600.0 210900.00000000003 20400.000000000004 ; + RECT 211700.00000000003 -400.0 210900.00000000003 400.0 ; + RECT 181400.00000000003 3000.0 182200.00000000003 3800.0 ; + RECT 203200.00000000003 3000.0 204000.00000000003 3800.0 ; + RECT 178600.00000000003 3100.0 222200.00000000003 3700.0 ; + RECT 189100.00000000003 19600.0 189900.00000000003 20400.000000000004 ; + RECT 210900.00000000003 19600.0 211700.00000000003 20400.000000000004 ; + RECT 189100.00000000003 -400.0 189900.00000000003 400.0 ; + RECT 210900.00000000003 -400.0 211700.00000000003 400.0 ; + RECT 173100.00000000003 3000.0 172300.0 3800.0 ; + RECT 72800.0 214900.00000000003 72000.0 215700.00000000006 ; + RECT 72800.0 50000.0 72000.0 50800.0 ; + RECT 177300.0 108400.0 176500.0 109200.0 ; + RECT 71399.99999999999 108400.0 70600.0 109200.0 ; + RECT 175900.0 68400.0 175100.0 69200.0 ; + RECT 71399.99999999999 68400.0 70600.0 69200.0 ; + RECT 174500.0 28400.000000000004 173700.0 29200.000000000004 ; + RECT 71399.99999999999 28400.000000000004 70600.0 29200.000000000004 ; + RECT 173100.00000000003 50000.0 172300.0 50800.0 ; + RECT 71399.99999999999 50000.0 70600.0 50800.0 ; + RECT 74600.0 221300.0 73800.0 222100.00000000003 ; + RECT 68800.0 221300.0 68000.0 222100.00000000003 ; + RECT 76000.0 241700.0 75200.0 242500.0 ; + RECT 68800.0 241700.0 68000.0 242500.0 ; + RECT 77399.99999999999 261300.0 76600.0 262100.00000000003 ; + RECT 68800.0 261300.0 68000.0 262100.00000000003 ; + RECT 78800.0 281700.0 78000.0 282500.0 ; + RECT 68800.0 281700.0 68000.0 282500.0 ; + RECT 1500.0 1500.0 3300.0 3300.0 ; + RECT 9900.0 1500.0 11700.000000000002 3300.0 ; + RECT 19500.0 1500.0 21300.0 3300.0 ; + RECT 29100.0 1500.0 30900.000000000004 3300.0 ; + RECT 38700.0 1500.0 40500.0 3300.0 ; + RECT 48300.00000000001 1500.0 50100.0 3300.0 ; + RECT 57900.00000000001 1500.0 59700.0 3300.0 ; + RECT 67500.0 1500.0 69300.0 3300.0 ; + RECT 77100.00000000001 1500.0 78900.0 3300.0 ; + RECT 86700.0 1500.0 88500.0 3300.0 ; + RECT 96300.00000000001 1500.0 98100.00000000001 3300.0 ; + RECT 105900.0 1500.0 107700.0 3300.0 ; + RECT 115500.00000000001 1500.0 117300.00000000001 3300.0 ; + RECT 125100.00000000001 1500.0 126900.0 3300.0 ; + RECT 134700.0 1500.0 136500.0 3300.0 ; + RECT 144299.99999999997 1500.0 146100.0 3300.0 ; + RECT 153900.0 1500.0 155700.00000000003 3300.0 ; + RECT 163500.0 1500.0 165300.0 3300.0 ; + RECT 1500.0 9900.0 3300.0 11700.000000000002 ; + RECT 9900.0 9900.0 11700.000000000002 11700.000000000002 ; + RECT 19500.0 9900.0 21300.0 11700.000000000002 ; + RECT 29100.0 9900.0 30900.000000000004 11700.000000000002 ; + RECT 38700.0 9900.0 40500.0 11700.000000000002 ; + RECT 48300.00000000001 9900.0 50100.0 11700.000000000002 ; + RECT 57900.00000000001 9900.0 59700.0 11700.000000000002 ; + RECT 67500.0 9900.0 69300.0 11700.000000000002 ; + RECT 77100.00000000001 9900.0 78900.0 11700.000000000002 ; + RECT 86700.0 9900.0 88500.0 11700.000000000002 ; + RECT 96300.00000000001 9900.0 98100.00000000001 11700.000000000002 ; + RECT 105900.0 9900.0 107700.0 11700.000000000002 ; + RECT 115500.00000000001 9900.0 117300.00000000001 11700.000000000002 ; + RECT 125100.00000000001 9900.0 126900.0 11700.000000000002 ; + RECT 134700.0 9900.0 136500.0 11700.000000000002 ; + RECT 144299.99999999997 9900.0 146100.0 11700.000000000002 ; + RECT 153900.0 9900.0 155700.00000000003 11700.000000000002 ; + RECT 163500.0 9900.0 165300.0 11700.000000000002 ; + RECT 173100.0 9900.0 174900.0 11700.000000000002 ; + RECT 182700.0 9900.0 184500.0 11700.000000000002 ; + RECT 192300.0 9900.0 194100.00000000003 11700.000000000002 ; + RECT 201900.0 9900.0 203700.00000000003 11700.000000000002 ; + RECT 211500.0 9900.0 213300.0 11700.000000000002 ; + RECT 221100.0 9900.0 222900.0 11700.000000000002 ; + RECT 229500.0 9900.0 231300.0 11700.000000000002 ; + RECT 1500.0 19500.0 3300.0 21300.0 ; + RECT 9900.0 19500.0 11700.000000000002 21300.0 ; + RECT 19500.0 19500.0 21300.0 21300.0 ; + RECT 29100.0 19500.0 30900.000000000004 21300.0 ; + RECT 38700.0 19500.0 40500.0 21300.0 ; + RECT 48300.00000000001 19500.0 50100.0 21300.0 ; + RECT 57900.00000000001 19500.0 59700.0 21300.0 ; + RECT 67500.0 19500.0 69300.0 21300.0 ; + RECT 77100.00000000001 19500.0 78900.0 21300.0 ; + RECT 86700.0 19500.0 88500.0 21300.0 ; + RECT 96300.00000000001 19500.0 98100.00000000001 21300.0 ; + RECT 105900.0 19500.0 107700.0 21300.0 ; + RECT 115500.00000000001 19500.0 117300.00000000001 21300.0 ; + RECT 125100.00000000001 19500.0 126900.0 21300.0 ; + RECT 134700.0 19500.0 136500.0 21300.0 ; + RECT 144299.99999999997 19500.0 146100.0 21300.0 ; + RECT 153900.0 19500.0 155700.00000000003 21300.0 ; + RECT 163500.0 19500.0 165300.0 21300.0 ; + RECT 173100.0 19500.0 174900.0 21300.0 ; + RECT 181500.0 19500.0 183300.0 21300.0 ; + RECT 221100.0 19500.0 222900.0 21300.0 ; + RECT 229500.0 19500.0 231300.0 21300.0 ; + RECT 201900.0 29100.0 203700.00000000003 30900.000000000004 ; + RECT 211500.0 29100.0 213300.0 30900.000000000004 ; + RECT 221100.0 29100.0 222900.0 30900.000000000004 ; + RECT 229500.0 29100.0 231300.0 30900.000000000004 ; + RECT 9900.0 38700.0 11700.000000000002 40500.0 ; + RECT 19500.0 38700.0 21300.0 40500.0 ; + RECT 29100.0 38700.0 30900.000000000004 40500.0 ; + RECT 38700.0 38700.0 40500.0 40500.0 ; + RECT 48300.00000000001 38700.0 50100.0 40500.0 ; + RECT 57900.00000000001 38700.0 59700.0 40500.0 ; + RECT 77100.00000000001 38700.0 78900.0 40500.0 ; + RECT 86700.0 38700.0 88500.0 40500.0 ; + RECT 96300.00000000001 38700.0 98100.00000000001 40500.0 ; + RECT 105900.0 38700.0 107700.0 40500.0 ; + RECT 115500.00000000001 38700.0 117300.00000000001 40500.0 ; + RECT 125100.00000000001 38700.0 126900.0 40500.0 ; + RECT 134700.0 38700.0 136500.0 40500.0 ; + RECT 144299.99999999997 38700.0 146100.0 40500.0 ; + RECT 153900.0 38700.0 155700.00000000003 40500.0 ; + RECT 163500.0 38700.0 165300.0 40500.0 ; + RECT 173100.0 38700.0 174900.0 40500.0 ; + RECT 182700.0 38700.0 184500.0 40500.0 ; + RECT 192300.0 38700.0 194100.00000000003 40500.0 ; + RECT 201900.0 38700.0 203700.00000000003 40500.0 ; + RECT 211500.0 38700.0 213300.0 40500.0 ; + RECT 221100.0 38700.0 222900.0 40500.0 ; + RECT 229500.0 38700.0 231300.0 40500.0 ; + RECT 201900.0 48300.00000000001 203700.00000000003 50100.0 ; + RECT 211500.0 48300.00000000001 213300.0 50100.0 ; + RECT 221100.0 48300.00000000001 222900.0 50100.0 ; + RECT 229500.0 48300.00000000001 231300.0 50100.0 ; + RECT 1500.0 57900.00000000001 3300.0 59700.0 ; + RECT 9900.0 57900.00000000001 11700.000000000002 59700.0 ; + RECT 19500.0 57900.00000000001 21300.0 59700.0 ; + RECT 29100.0 57900.00000000001 30900.000000000004 59700.0 ; + RECT 38700.0 57900.00000000001 40500.0 59700.0 ; + RECT 48300.00000000001 57900.00000000001 50100.0 59700.0 ; + RECT 57900.00000000001 57900.00000000001 59700.0 59700.0 ; + RECT 67500.0 57900.00000000001 69300.0 59700.0 ; + RECT 77100.00000000001 57900.00000000001 78900.0 59700.0 ; + RECT 86700.0 57900.00000000001 88500.0 59700.0 ; + RECT 96300.00000000001 57900.00000000001 98100.00000000001 59700.0 ; + RECT 105900.0 57900.00000000001 107700.0 59700.0 ; + RECT 115500.00000000001 57900.00000000001 117300.00000000001 59700.0 ; + RECT 125100.00000000001 57900.00000000001 126900.0 59700.0 ; + RECT 134700.0 57900.00000000001 136500.0 59700.0 ; + RECT 144299.99999999997 57900.00000000001 146100.0 59700.0 ; + RECT 153900.0 57900.00000000001 155700.00000000003 59700.0 ; + RECT 163500.0 57900.00000000001 165300.0 59700.0 ; + RECT 173100.0 57900.00000000001 174900.0 59700.0 ; + RECT 182700.0 57900.00000000001 184500.0 59700.0 ; + RECT 192300.0 57900.00000000001 194100.00000000003 59700.0 ; + RECT 201900.0 57900.00000000001 203700.00000000003 59700.0 ; + RECT 211500.0 57900.00000000001 213300.0 59700.0 ; + RECT 221100.0 57900.00000000001 222900.0 59700.0 ; + RECT 229500.0 57900.00000000001 231300.0 59700.0 ; + RECT 1500.0 67500.0 3300.0 69300.0 ; + RECT 9900.0 67500.0 11700.000000000002 69300.0 ; + RECT 19500.0 67500.0 21300.0 69300.0 ; + RECT 29100.0 67500.0 30900.000000000004 69300.0 ; + RECT 38700.0 67500.0 40500.0 69300.0 ; + RECT 48300.00000000001 67500.0 50100.0 69300.0 ; + RECT 57900.00000000001 67500.0 59700.0 69300.0 ; + RECT 182700.0 67500.0 184500.0 69300.0 ; + RECT 192300.0 67500.0 194100.00000000003 69300.0 ; + RECT 201900.0 67500.0 203700.00000000003 69300.0 ; + RECT 211500.0 67500.0 213300.0 69300.0 ; + RECT 221100.0 67500.0 222900.0 69300.0 ; + RECT 229500.0 67500.0 231300.0 69300.0 ; + RECT 1500.0 77100.00000000001 3300.0 78900.0 ; + RECT 9900.0 77100.00000000001 11700.000000000002 78900.0 ; + RECT 19500.0 77100.00000000001 21300.0 78900.0 ; + RECT 29100.0 77100.00000000001 30900.000000000004 78900.0 ; + RECT 38700.0 77100.00000000001 40500.0 78900.0 ; + RECT 48300.00000000001 77100.00000000001 50100.0 78900.0 ; + RECT 57900.00000000001 77100.00000000001 59700.0 78900.0 ; + RECT 77100.00000000001 77100.00000000001 78900.0 78900.0 ; + RECT 86700.0 77100.00000000001 88500.0 78900.0 ; + RECT 96300.00000000001 77100.00000000001 98100.00000000001 78900.0 ; + RECT 105900.0 77100.00000000001 107700.0 78900.0 ; + RECT 115500.00000000001 77100.00000000001 117300.00000000001 78900.0 ; + RECT 125100.00000000001 77100.00000000001 126900.0 78900.0 ; + RECT 134700.0 77100.00000000001 136500.0 78900.0 ; + RECT 144299.99999999997 77100.00000000001 146100.0 78900.0 ; + RECT 153900.0 77100.00000000001 155700.00000000003 78900.0 ; + RECT 163500.0 77100.00000000001 165300.0 78900.0 ; + RECT 173100.0 77100.00000000001 174900.0 78900.0 ; + RECT 182700.0 77100.00000000001 184500.0 78900.0 ; + RECT 192300.0 77100.00000000001 194100.00000000003 78900.0 ; + RECT 201900.0 77100.00000000001 203700.00000000003 78900.0 ; + RECT 211500.0 77100.00000000001 213300.0 78900.0 ; + RECT 221100.0 77100.00000000001 222900.0 78900.0 ; + RECT 229500.0 77100.00000000001 231300.0 78900.0 ; + RECT 57900.00000000001 86700.0 59700.0 88500.0 ; + RECT 67500.0 86700.0 69300.0 88500.0 ; + RECT 77100.00000000001 86700.0 78900.0 88500.0 ; + RECT 86700.0 86700.0 88500.0 88500.0 ; + RECT 96300.00000000001 86700.0 98100.00000000001 88500.0 ; + RECT 105900.0 86700.0 107700.0 88500.0 ; + RECT 115500.00000000001 86700.0 117300.00000000001 88500.0 ; + RECT 125100.00000000001 86700.0 126900.0 88500.0 ; + RECT 134700.0 86700.0 136500.0 88500.0 ; + RECT 144299.99999999997 86700.0 146100.0 88500.0 ; + RECT 153900.0 86700.0 155700.00000000003 88500.0 ; + RECT 163500.0 86700.0 165300.0 88500.0 ; + RECT 173100.0 86700.0 174900.0 88500.0 ; + RECT 182700.0 86700.0 184500.0 88500.0 ; + RECT 192300.0 86700.0 194100.00000000003 88500.0 ; + RECT 201900.0 86700.0 203700.00000000003 88500.0 ; + RECT 211500.0 86700.0 213300.0 88500.0 ; + RECT 221100.0 86700.0 222900.0 88500.0 ; + RECT 229500.0 86700.0 231300.0 88500.0 ; + RECT 1500.0 96300.00000000001 3300.0 98100.00000000001 ; + RECT 9900.0 96300.00000000001 11700.000000000002 98100.00000000001 ; + RECT 19500.0 96300.00000000001 21300.0 98100.00000000001 ; + RECT 29100.0 96300.00000000001 30900.000000000004 98100.00000000001 ; + RECT 38700.0 96300.00000000001 40500.0 98100.00000000001 ; + RECT 48300.00000000001 96300.00000000001 50100.0 98100.00000000001 ; + RECT 57900.00000000001 96300.00000000001 59700.0 98100.00000000001 ; + RECT 67500.0 96300.00000000001 69300.0 98100.00000000001 ; + RECT 77100.00000000001 96300.00000000001 78900.0 98100.00000000001 ; + RECT 86700.0 96300.00000000001 88500.0 98100.00000000001 ; + RECT 96300.00000000001 96300.00000000001 98100.00000000001 98100.00000000001 ; + RECT 105900.0 96300.00000000001 107700.0 98100.00000000001 ; + RECT 115500.00000000001 96300.00000000001 117300.00000000001 98100.00000000001 ; + RECT 125100.00000000001 96300.00000000001 126900.0 98100.00000000001 ; + RECT 134700.0 96300.00000000001 136500.0 98100.00000000001 ; + RECT 144299.99999999997 96300.00000000001 146100.0 98100.00000000001 ; + RECT 153900.0 96300.00000000001 155700.00000000003 98100.00000000001 ; + RECT 163500.0 96300.00000000001 165300.0 98100.00000000001 ; + RECT 173100.0 96300.00000000001 174900.0 98100.00000000001 ; + RECT 182700.0 96300.00000000001 184500.0 98100.00000000001 ; + RECT 192300.0 96300.00000000001 194100.00000000003 98100.00000000001 ; + RECT 201900.0 96300.00000000001 203700.00000000003 98100.00000000001 ; + RECT 211500.0 96300.00000000001 213300.0 98100.00000000001 ; + RECT 221100.0 96300.00000000001 222900.0 98100.00000000001 ; + RECT 229500.0 96300.00000000001 231300.0 98100.00000000001 ; + RECT 1500.0 105900.0 3300.0 107700.0 ; + RECT 9900.0 105900.0 11700.000000000002 107700.0 ; + RECT 19500.0 105900.0 21300.0 107700.0 ; + RECT 29100.0 105900.0 30900.000000000004 107700.0 ; + RECT 38700.0 105900.0 40500.0 107700.0 ; + RECT 48300.00000000001 105900.0 50100.0 107700.0 ; + RECT 57900.00000000001 105900.0 59700.0 107700.0 ; + RECT 183900.0 105900.0 185700.00000000003 107700.0 ; + RECT 192300.0 105900.0 194100.00000000003 107700.0 ; + RECT 201900.0 105900.0 203700.00000000003 107700.0 ; + RECT 211500.0 105900.0 213300.0 107700.0 ; + RECT 221100.0 105900.0 222900.0 107700.0 ; + RECT 229500.0 105900.0 231300.0 107700.0 ; + RECT 1500.0 115500.00000000001 3300.0 117300.00000000001 ; + RECT 9900.0 115500.00000000001 11700.000000000002 117300.00000000001 ; + RECT 19500.0 115500.00000000001 21300.0 117300.00000000001 ; + RECT 29100.0 115500.00000000001 30900.000000000004 117300.00000000001 ; + RECT 38700.0 115500.00000000001 40500.0 117300.00000000001 ; + RECT 48300.00000000001 115500.00000000001 50100.0 117300.00000000001 ; + RECT 57900.00000000001 115500.00000000001 59700.0 117300.00000000001 ; + RECT 67500.0 115500.00000000001 69300.0 117300.00000000001 ; + RECT 77100.00000000001 115500.00000000001 78900.0 117300.00000000001 ; + RECT 86700.0 115500.00000000001 88500.0 117300.00000000001 ; + RECT 96300.00000000001 115500.00000000001 98100.00000000001 117300.00000000001 ; + RECT 105900.0 115500.00000000001 107700.0 117300.00000000001 ; + RECT 115500.00000000001 115500.00000000001 117300.00000000001 117300.00000000001 ; + RECT 125100.00000000001 115500.00000000001 126900.0 117300.00000000001 ; + RECT 134700.0 115500.00000000001 136500.0 117300.00000000001 ; + RECT 144299.99999999997 115500.00000000001 146100.0 117300.00000000001 ; + RECT 153900.0 115500.00000000001 155700.00000000003 117300.00000000001 ; + RECT 163500.0 115500.00000000001 165300.0 117300.00000000001 ; + RECT 173100.0 115500.00000000001 174900.0 117300.00000000001 ; + RECT 182700.0 115500.00000000001 184500.0 117300.00000000001 ; + RECT 192300.0 115500.00000000001 194100.00000000003 117300.00000000001 ; + RECT 201900.0 115500.00000000001 203700.00000000003 117300.00000000001 ; + RECT 211500.0 115500.00000000001 213300.0 117300.00000000001 ; + RECT 221100.0 115500.00000000001 222900.0 117300.00000000001 ; + RECT 229500.0 115500.00000000001 231300.0 117300.00000000001 ; + RECT 39900.00000000001 125100.00000000001 41700.0 126900.0 ; + RECT 48300.00000000001 125100.00000000001 50100.0 126900.0 ; + RECT 57900.00000000001 125100.00000000001 59700.0 126900.0 ; + RECT 67500.0 125100.00000000001 69300.0 126900.0 ; + RECT 77100.00000000001 125100.00000000001 78900.0 126900.0 ; + RECT 86700.0 125100.00000000001 88500.0 126900.0 ; + RECT 96300.00000000001 125100.00000000001 98100.00000000001 126900.0 ; + RECT 105900.0 125100.00000000001 107700.0 126900.0 ; + RECT 115500.00000000001 125100.00000000001 117300.00000000001 126900.0 ; + RECT 125100.00000000001 125100.00000000001 126900.0 126900.0 ; + RECT 134700.0 125100.00000000001 136500.0 126900.0 ; + RECT 144299.99999999997 125100.00000000001 146100.0 126900.0 ; + RECT 153900.0 125100.00000000001 155700.00000000003 126900.0 ; + RECT 163500.0 125100.00000000001 165300.0 126900.0 ; + RECT 173100.0 125100.00000000001 174900.0 126900.0 ; + RECT 182700.0 125100.00000000001 184500.0 126900.0 ; + RECT 192300.0 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59700.0 165300.0 ; + RECT 67500.0 163500.0 69300.0 165300.0 ; + RECT 77100.00000000001 163500.0 78900.0 165300.0 ; + RECT 86700.0 163500.0 88500.0 165300.0 ; + RECT 96300.00000000001 163500.0 98100.00000000001 165300.0 ; + RECT 105900.0 163500.0 107700.0 165300.0 ; + RECT 115500.00000000001 163500.0 117300.00000000001 165300.0 ; + RECT 125100.00000000001 163500.0 126900.0 165300.0 ; + RECT 134700.0 163500.0 136500.0 165300.0 ; + RECT 144299.99999999997 163500.0 146100.0 165300.0 ; + RECT 153900.0 163500.0 155700.00000000003 165300.0 ; + RECT 163500.0 163500.0 165300.0 165300.0 ; + RECT 173100.0 163500.0 174900.0 165300.0 ; + RECT 182700.0 163500.0 184500.0 165300.0 ; + RECT 192300.0 163500.0 194100.00000000003 165300.0 ; + RECT 201900.0 163500.0 203700.00000000003 165300.0 ; + RECT 211500.0 163500.0 213300.0 165300.0 ; + RECT 221100.0 163500.0 222900.0 165300.0 ; + RECT 229500.0 163500.0 231300.0 165300.0 ; + RECT 1500.0 173100.0 3300.0 174900.0 ; + RECT 9900.0 173100.0 11700.000000000002 174900.0 ; + RECT 19500.0 173100.0 21300.0 174900.0 ; + RECT 29100.0 173100.0 30900.000000000004 174900.0 ; + RECT 38700.0 173100.0 40500.0 174900.0 ; + RECT 48300.00000000001 173100.0 50100.0 174900.0 ; + RECT 57900.00000000001 173100.0 59700.0 174900.0 ; + RECT 67500.0 173100.0 69300.0 174900.0 ; + RECT 77100.00000000001 173100.0 78900.0 174900.0 ; + RECT 86700.0 173100.0 88500.0 174900.0 ; + RECT 96300.00000000001 173100.0 98100.00000000001 174900.0 ; + RECT 105900.0 173100.0 107700.0 174900.0 ; + RECT 115500.00000000001 173100.0 117300.00000000001 174900.0 ; + RECT 125100.00000000001 173100.0 126900.0 174900.0 ; + RECT 134700.0 173100.0 136500.0 174900.0 ; + RECT 144299.99999999997 173100.0 146100.0 174900.0 ; + RECT 153900.0 173100.0 155700.00000000003 174900.0 ; + RECT 163500.0 173100.0 165300.0 174900.0 ; + RECT 173100.0 173100.0 174900.0 174900.0 ; + RECT 182700.0 173100.0 184500.0 174900.0 ; + RECT 192300.0 173100.0 194100.00000000003 174900.0 ; + RECT 201900.0 173100.0 203700.00000000003 174900.0 ; + RECT 211500.0 173100.0 213300.0 174900.0 ; + RECT 221100.0 173100.0 222900.0 174900.0 ; + RECT 229500.0 173100.0 231300.0 174900.0 ; + RECT 1500.0 182700.0 3300.0 184500.0 ; + RECT 9900.0 182700.0 11700.000000000002 184500.0 ; + RECT 19500.0 182700.0 21300.0 184500.0 ; + RECT 29100.0 182700.0 30900.000000000004 184500.0 ; + RECT 38700.0 182700.0 40500.0 184500.0 ; + RECT 48300.00000000001 182700.0 50100.0 184500.0 ; + RECT 57900.00000000001 182700.0 59700.0 184500.0 ; + RECT 67500.0 182700.0 69300.0 184500.0 ; + RECT 77100.00000000001 182700.0 78900.0 184500.0 ; + RECT 86700.0 182700.0 88500.0 184500.0 ; + RECT 96300.00000000001 182700.0 98100.00000000001 184500.0 ; + RECT 105900.0 182700.0 107700.0 184500.0 ; + RECT 115500.00000000001 182700.0 117300.00000000001 184500.0 ; + RECT 125100.00000000001 182700.0 126900.0 184500.0 ; + RECT 134700.0 182700.0 136500.0 184500.0 ; + RECT 144299.99999999997 182700.0 146100.0 184500.0 ; + RECT 153900.0 182700.0 155700.00000000003 184500.0 ; + RECT 163500.0 182700.0 165300.0 184500.0 ; + RECT 173100.0 182700.0 174900.0 184500.0 ; + RECT 182700.0 182700.0 184500.0 184500.0 ; + RECT 192300.0 182700.0 194100.00000000003 184500.0 ; + RECT 201900.0 182700.0 203700.00000000003 184500.0 ; + RECT 211500.0 182700.0 213300.0 184500.0 ; + RECT 221100.0 182700.0 222900.0 184500.0 ; + RECT 229500.0 182700.0 231300.0 184500.0 ; + RECT 1500.0 192300.0 3300.0 194100.00000000003 ; + RECT 9900.0 192300.0 11700.000000000002 194100.00000000003 ; + RECT 19500.0 192300.0 21300.0 194100.00000000003 ; + RECT 29100.0 192300.0 30900.000000000004 194100.00000000003 ; + RECT 38700.0 192300.0 40500.0 194100.00000000003 ; + RECT 48300.00000000001 192300.0 50100.0 194100.00000000003 ; + RECT 57900.00000000001 192300.0 59700.0 194100.00000000003 ; + RECT 67500.0 192300.0 69300.0 194100.00000000003 ; + RECT 77100.00000000001 192300.0 78900.0 194100.00000000003 ; + RECT 86700.0 192300.0 88500.0 194100.00000000003 ; + RECT 96300.00000000001 192300.0 98100.00000000001 194100.00000000003 ; + RECT 105900.0 192300.0 107700.0 194100.00000000003 ; + RECT 115500.00000000001 192300.0 117300.00000000001 194100.00000000003 ; + RECT 125100.00000000001 192300.0 126900.0 194100.00000000003 ; + RECT 134700.0 192300.0 136500.0 194100.00000000003 ; + RECT 144299.99999999997 192300.0 146100.0 194100.00000000003 ; + RECT 153900.0 192300.0 155700.00000000003 194100.00000000003 ; + RECT 163500.0 192300.0 165300.0 194100.00000000003 ; + RECT 173100.0 192300.0 174900.0 194100.00000000003 ; + RECT 182700.0 192300.0 184500.0 194100.00000000003 ; + RECT 192300.0 192300.0 194100.00000000003 194100.00000000003 ; + RECT 201900.0 192300.0 203700.00000000003 194100.00000000003 ; + RECT 211500.0 192300.0 213300.0 194100.00000000003 ; + RECT 221100.0 192300.0 222900.0 194100.00000000003 ; + RECT 229500.0 192300.0 231300.0 194100.00000000003 ; + RECT 1500.0 201900.0 3300.0 203700.00000000003 ; + RECT 9900.0 201900.0 11700.000000000002 203700.00000000003 ; + RECT 19500.0 201900.0 21300.0 203700.00000000003 ; + RECT 29100.0 201900.0 30900.000000000004 203700.00000000003 ; + RECT 38700.0 201900.0 40500.0 203700.00000000003 ; + RECT 48300.00000000001 201900.0 50100.0 203700.00000000003 ; + RECT 57900.00000000001 201900.0 59700.0 203700.00000000003 ; + RECT 67500.0 201900.0 69300.0 203700.00000000003 ; + RECT 77100.00000000001 201900.0 78900.0 203700.00000000003 ; + RECT 86700.0 201900.0 88500.0 203700.00000000003 ; + RECT 96300.00000000001 201900.0 98100.00000000001 203700.00000000003 ; + RECT 105900.0 201900.0 107700.0 203700.00000000003 ; + RECT 115500.00000000001 201900.0 117300.00000000001 203700.00000000003 ; + RECT 201900.0 201900.0 203700.00000000003 203700.00000000003 ; + RECT 211500.0 201900.0 213300.0 203700.00000000003 ; + RECT 221100.0 201900.0 222900.0 203700.00000000003 ; + RECT 229500.0 201900.0 231300.0 203700.00000000003 ; + RECT 1500.0 211500.0 3300.0 213300.0 ; + RECT 9900.0 211500.0 11700.000000000002 213300.0 ; + RECT 19500.0 211500.0 21300.0 213300.0 ; + RECT 29100.0 211500.0 30900.000000000004 213300.0 ; + RECT 38700.0 211500.0 40500.0 213300.0 ; + RECT 78300.00000000001 211500.0 80100.00000000001 213300.0 ; + RECT 86700.0 211500.0 88500.0 213300.0 ; + RECT 96300.00000000001 211500.0 98100.00000000001 213300.0 ; + RECT 105900.0 211500.0 107700.0 213300.0 ; + RECT 115500.00000000001 211500.0 117300.00000000001 213300.0 ; + RECT 125100.00000000001 211500.0 126900.0 213300.0 ; + RECT 134700.0 211500.0 136500.0 213300.0 ; + RECT 144299.99999999997 211500.0 146100.0 213300.0 ; + RECT 153900.0 211500.0 155700.00000000003 213300.0 ; + RECT 163500.0 211500.0 165300.0 213300.0 ; + RECT 173100.0 211500.0 174900.0 213300.0 ; + RECT 182700.0 211500.0 184500.0 213300.0 ; + RECT 192300.0 211500.0 194100.00000000003 213300.0 ; + RECT 201900.0 211500.0 203700.00000000003 213300.0 ; + RECT 211500.0 211500.0 213300.0 213300.0 ; + RECT 221100.0 211500.0 222900.0 213300.0 ; + RECT 229500.0 211500.0 231300.0 213300.0 ; + RECT 1500.0 221100.0 3300.0 222900.0 ; + RECT 9900.0 221100.0 11700.000000000002 222900.0 ; + RECT 19500.0 221100.0 21300.0 222900.0 ; + RECT 29100.0 221100.0 30900.000000000004 222900.0 ; + RECT 38700.0 221100.0 40500.0 222900.0 ; + RECT 48300.00000000001 221100.0 50100.0 222900.0 ; + RECT 57900.00000000001 221100.0 59700.0 222900.0 ; + RECT 86700.0 221100.0 88500.0 222900.0 ; + RECT 96300.00000000001 221100.0 98100.00000000001 222900.0 ; + RECT 105900.0 221100.0 107700.0 222900.0 ; + RECT 115500.00000000001 221100.0 117300.00000000001 222900.0 ; + RECT 201900.0 221100.0 203700.00000000003 222900.0 ; + RECT 211500.0 221100.0 213300.0 222900.0 ; + RECT 221100.0 221100.0 222900.0 222900.0 ; + RECT 229500.0 221100.0 231300.0 222900.0 ; + RECT 1500.0 230700.0 3300.0 232500.0 ; + RECT 9900.0 230700.0 11700.000000000002 232500.0 ; + RECT 19500.0 230700.0 21300.0 232500.0 ; + RECT 29100.0 230700.0 30900.000000000004 232500.0 ; + RECT 38700.0 230700.0 40500.0 232500.0 ; + RECT 48300.00000000001 230700.0 50100.0 232500.0 ; + RECT 67500.0 230700.0 69300.0 232500.0 ; + RECT 77100.00000000001 230700.0 78900.0 232500.0 ; + RECT 86700.0 230700.0 88500.0 232500.0 ; + RECT 96300.00000000001 230700.0 98100.00000000001 232500.0 ; + RECT 105900.0 230700.0 107700.0 232500.0 ; + RECT 115500.00000000001 230700.0 117300.00000000001 232500.0 ; + RECT 125100.00000000001 230700.0 126900.0 232500.0 ; + RECT 134700.0 230700.0 136500.0 232500.0 ; + RECT 144299.99999999997 230700.0 146100.0 232500.0 ; + RECT 153900.0 230700.0 155700.00000000003 232500.0 ; + RECT 163500.0 230700.0 165300.0 232500.0 ; + RECT 173100.0 230700.0 174900.0 232500.0 ; + RECT 182700.0 230700.0 184500.0 232500.0 ; + RECT 192300.0 230700.0 194100.00000000003 232500.0 ; + RECT 201900.0 230700.0 203700.00000000003 232500.0 ; + RECT 211500.0 230700.0 213300.0 232500.0 ; + RECT 221100.0 230700.0 222900.0 232500.0 ; + RECT 229500.0 230700.0 231300.0 232500.0 ; + RECT 1500.0 240300.0 3300.0 242100.00000000003 ; + RECT 9900.0 240300.0 11700.000000000002 242100.00000000003 ; + RECT 19500.0 240300.0 21300.0 242100.00000000003 ; + RECT 29100.0 240300.0 30900.000000000004 242100.00000000003 ; + RECT 38700.0 240300.0 40500.0 242100.00000000003 ; + RECT 48300.00000000001 240300.0 50100.0 242100.00000000003 ; + RECT 57900.00000000001 240300.0 59700.0 242100.00000000003 ; + RECT 86700.0 240300.0 88500.0 242100.00000000003 ; + RECT 96300.00000000001 240300.0 98100.00000000001 242100.00000000003 ; + RECT 105900.0 240300.0 107700.0 242100.00000000003 ; + RECT 115500.00000000001 240300.0 117300.00000000001 242100.00000000003 ; + RECT 201900.0 240300.0 203700.00000000003 242100.00000000003 ; + RECT 211500.0 240300.0 213300.0 242100.00000000003 ; + RECT 221100.0 240300.0 222900.0 242100.00000000003 ; + RECT 229500.0 240300.0 231300.0 242100.00000000003 ; + RECT 1500.0 249900.0 3300.0 251700.00000000003 ; + RECT 9900.0 249900.0 11700.000000000002 251700.00000000003 ; + RECT 19500.0 249900.0 21300.0 251700.00000000003 ; + RECT 29100.0 249900.0 30900.000000000004 251700.00000000003 ; + RECT 38700.0 249900.0 40500.0 251700.00000000003 ; + RECT 48300.00000000001 249900.0 50100.0 251700.00000000003 ; + RECT 57900.00000000001 249900.0 59700.0 251700.00000000003 ; + RECT 67500.0 249900.0 69300.0 251700.00000000003 ; + RECT 77100.00000000001 249900.0 78900.0 251700.00000000003 ; + RECT 86700.0 249900.0 88500.0 251700.00000000003 ; + RECT 96300.00000000001 249900.0 98100.00000000001 251700.00000000003 ; + RECT 105900.0 249900.0 107700.0 251700.00000000003 ; + RECT 115500.00000000001 249900.0 117300.00000000001 251700.00000000003 ; + RECT 125100.00000000001 249900.0 126900.0 251700.00000000003 ; + RECT 134700.0 249900.0 136500.0 251700.00000000003 ; + RECT 144299.99999999997 249900.0 146100.0 251700.00000000003 ; + RECT 153900.0 249900.0 155700.00000000003 251700.00000000003 ; + RECT 163500.0 249900.0 165300.0 251700.00000000003 ; + RECT 173100.0 249900.0 174900.0 251700.00000000003 ; + RECT 182700.0 249900.0 184500.0 251700.00000000003 ; + RECT 192300.0 249900.0 194100.00000000003 251700.00000000003 ; + RECT 201900.0 249900.0 203700.00000000003 251700.00000000003 ; + RECT 211500.0 249900.0 213300.0 251700.00000000003 ; + RECT 221100.0 249900.0 222900.0 251700.00000000003 ; + RECT 229500.0 249900.0 231300.0 251700.00000000003 ; + RECT 1500.0 259500.0 3300.0 261300.0 ; + RECT 9900.0 259500.0 11700.000000000002 261300.0 ; + RECT 19500.0 259500.0 21300.0 261300.0 ; + RECT 29100.0 259500.0 30900.000000000004 261300.0 ; + RECT 38700.0 259500.0 40500.0 261300.0 ; + RECT 48300.00000000001 259500.0 50100.0 261300.0 ; + RECT 57900.00000000001 259500.0 59700.0 261300.0 ; + RECT 86700.0 259500.0 88500.0 261300.0 ; + RECT 96300.00000000001 259500.0 98100.00000000001 261300.0 ; + RECT 105900.0 259500.0 107700.0 261300.0 ; + RECT 115500.00000000001 259500.0 117300.00000000001 261300.0 ; + RECT 201900.0 259500.0 203700.00000000003 261300.0 ; + RECT 211500.0 259500.0 213300.0 261300.0 ; + RECT 221100.0 259500.0 222900.0 261300.0 ; + RECT 229500.0 259500.0 231300.0 261300.0 ; + RECT 1500.0 269100.0 3300.0 270900.00000000006 ; + RECT 9900.0 269100.0 11700.000000000002 270900.00000000006 ; + RECT 19500.0 269100.0 21300.0 270900.00000000006 ; + RECT 29100.0 269100.0 30900.000000000004 270900.00000000006 ; + RECT 38700.0 269100.0 40500.0 270900.00000000006 ; + RECT 48300.00000000001 269100.0 50100.0 270900.00000000006 ; + RECT 67500.0 269100.0 69300.0 270900.00000000006 ; + RECT 77100.00000000001 269100.0 78900.0 270900.00000000006 ; + RECT 86700.0 269100.0 88500.0 270900.00000000006 ; + RECT 96300.00000000001 269100.0 98100.00000000001 270900.00000000006 ; + RECT 105900.0 269100.0 107700.0 270900.00000000006 ; + RECT 115500.00000000001 269100.0 117300.00000000001 270900.00000000006 ; + RECT 125100.00000000001 269100.0 126900.0 270900.00000000006 ; + RECT 134700.0 269100.0 136500.0 270900.00000000006 ; + RECT 144299.99999999997 269100.0 146100.0 270900.00000000006 ; + RECT 153900.0 269100.0 155700.00000000003 270900.00000000006 ; + RECT 163500.0 269100.0 165300.0 270900.00000000006 ; + RECT 173100.0 269100.0 174900.0 270900.00000000006 ; + RECT 182700.0 269100.0 184500.0 270900.00000000006 ; + RECT 192300.0 269100.0 194100.00000000003 270900.00000000006 ; + RECT 201900.0 269100.0 203700.00000000003 270900.00000000006 ; + RECT 211500.0 269100.0 213300.0 270900.00000000006 ; + RECT 221100.0 269100.0 222900.0 270900.00000000006 ; + RECT 229500.0 269100.0 231300.0 270900.00000000006 ; + RECT 1500.0 278700.0 3300.0 280500.0 ; + RECT 9900.0 278700.0 11700.000000000002 280500.0 ; + RECT 19500.0 278700.0 21300.0 280500.0 ; + RECT 29100.0 278700.0 30900.000000000004 280500.0 ; + RECT 38700.0 278700.0 40500.0 280500.0 ; + RECT 48300.00000000001 278700.0 50100.0 280500.0 ; + RECT 57900.00000000001 278700.0 59700.0 280500.0 ; + RECT 86700.0 278700.0 88500.0 280500.0 ; + RECT 96300.00000000001 278700.0 98100.00000000001 280500.0 ; + RECT 105900.0 278700.0 107700.0 280500.0 ; + RECT 115500.00000000001 278700.0 117300.00000000001 280500.0 ; + RECT 125100.00000000001 278700.0 126900.0 280500.0 ; + RECT 134700.0 278700.0 136500.0 280500.0 ; + RECT 144299.99999999997 278700.0 146100.0 280500.0 ; + RECT 153900.0 278700.0 155700.00000000003 280500.0 ; + RECT 163500.0 278700.0 165300.0 280500.0 ; + RECT 173100.0 278700.0 174900.0 280500.0 ; + RECT 182700.0 278700.0 184500.0 280500.0 ; + RECT 192300.0 278700.0 194100.00000000003 280500.0 ; + RECT 201900.0 278700.0 203700.00000000003 280500.0 ; + RECT 211500.0 278700.0 213300.0 280500.0 ; + RECT 221100.0 278700.0 222900.0 280500.0 ; + RECT 229500.0 278700.0 231300.0 280500.0 ; + RECT 1500.0 288300.0 3300.0 290100.0 ; + RECT 9900.0 288300.0 11700.000000000002 290100.0 ; + RECT 19500.0 288300.0 21300.0 290100.0 ; + RECT 29100.0 288300.0 30900.000000000004 290100.0 ; + RECT 38700.0 288300.0 40500.0 290100.0 ; + RECT 48300.00000000001 288300.0 50100.0 290100.0 ; + RECT 57900.00000000001 288300.0 59700.0 290100.0 ; + RECT 67500.0 288300.0 69300.0 290100.0 ; + RECT 77100.00000000001 288300.0 78900.0 290100.0 ; + RECT 86700.0 288300.0 88500.0 290100.0 ; + RECT 96300.00000000001 288300.0 98100.00000000001 290100.0 ; + RECT 105900.0 288300.0 107700.0 290100.0 ; + RECT 115500.00000000001 288300.0 117300.00000000001 290100.0 ; + RECT 125100.00000000001 288300.0 126900.0 290100.0 ; + RECT 134700.0 288300.0 136500.0 290100.0 ; + RECT 144299.99999999997 288300.0 146100.0 290100.0 ; + RECT 153900.0 288300.0 155700.00000000003 290100.0 ; + RECT 163500.0 288300.0 165300.0 290100.0 ; + RECT 173100.0 288300.0 174900.0 290100.0 ; + RECT 182700.0 288300.0 184500.0 290100.0 ; + RECT 192300.0 288300.0 194100.00000000003 290100.0 ; + RECT 201900.0 288300.0 203700.00000000003 290100.0 ; + RECT 211500.0 288300.0 213300.0 290100.0 ; + RECT 221100.0 288300.0 222900.0 290100.0 ; + RECT 229500.0 288300.0 231300.0 290100.0 ; + RECT 1500.0 297900.0 3300.0 299700.0 ; + RECT 9900.0 297900.0 11700.000000000002 299700.0 ; + RECT 19500.0 297900.0 21300.0 299700.0 ; + RECT 29100.0 297900.0 30900.000000000004 299700.0 ; + RECT 38700.0 297900.0 40500.0 299700.0 ; + RECT 48300.00000000001 297900.0 50100.0 299700.0 ; + RECT 57900.00000000001 297900.0 59700.0 299700.0 ; + RECT 67500.0 297900.0 69300.0 299700.0 ; + RECT 77100.00000000001 297900.0 78900.0 299700.0 ; + RECT 86700.0 297900.0 88500.0 299700.0 ; + RECT 96300.00000000001 297900.0 98100.00000000001 299700.0 ; + RECT 105900.0 297900.0 107700.0 299700.0 ; + RECT 115500.00000000001 297900.0 117300.00000000001 299700.0 ; + RECT 125100.00000000001 297900.0 126900.0 299700.0 ; + RECT 134700.0 297900.0 136500.0 299700.0 ; + RECT 144299.99999999997 297900.0 146100.0 299700.0 ; + RECT 153900.0 297900.0 155700.00000000003 299700.0 ; + RECT 163500.0 297900.0 165300.0 299700.0 ; + RECT 173100.0 297900.0 174900.0 299700.0 ; + RECT 182700.0 297900.0 184500.0 299700.0 ; + RECT 192300.0 297900.0 194100.00000000003 299700.0 ; + RECT 201900.0 297900.0 203700.00000000003 299700.0 ; + RECT 211500.0 297900.0 213300.0 299700.0 ; + RECT 221100.0 297900.0 222900.0 299700.0 ; + RECT 229500.0 297900.0 231300.0 299700.0 ; + RECT 5100.000000000001 5100.000000000001 6900.0 6900.0 ; + RECT 14700.0 5100.000000000001 16500.0 6900.0 ; + RECT 24300.0 5100.000000000001 26100.0 6900.0 ; + RECT 33900.00000000001 5100.000000000001 35700.0 6900.0 ; + RECT 43500.00000000001 5100.000000000001 45300.00000000001 6900.0 ; + RECT 53100.00000000001 5100.000000000001 54900.00000000001 6900.0 ; + RECT 62700.0 5100.000000000001 64500.0 6900.0 ; + RECT 72300.00000000001 5100.000000000001 74100.00000000001 6900.0 ; + RECT 81900.0 5100.000000000001 83700.0 6900.0 ; + RECT 91500.00000000001 5100.000000000001 93300.00000000001 6900.0 ; + RECT 101100.00000000001 5100.000000000001 102900.0 6900.0 ; + RECT 110700.0 5100.000000000001 112500.0 6900.0 ; + RECT 120300.00000000001 5100.000000000001 122100.00000000001 6900.0 ; + RECT 129900.0 5100.000000000001 131700.00000000003 6900.0 ; + RECT 139500.0 5100.000000000001 141300.0 6900.0 ; + RECT 149100.0 5100.000000000001 150900.0 6900.0 ; + RECT 158700.0 5100.000000000001 160500.0 6900.0 ; + RECT 5100.000000000001 14700.0 6900.0 16500.0 ; + RECT 14700.0 14700.0 16500.0 16500.0 ; + RECT 24300.0 14700.0 26100.0 16500.0 ; + RECT 33900.00000000001 14700.0 35700.0 16500.0 ; + RECT 43500.00000000001 14700.0 45300.00000000001 16500.0 ; + RECT 53100.00000000001 14700.0 54900.00000000001 16500.0 ; + RECT 62700.0 14700.0 64500.0 16500.0 ; + RECT 72300.00000000001 14700.0 74100.00000000001 16500.0 ; + RECT 81900.0 14700.0 83700.0 16500.0 ; + RECT 91500.00000000001 14700.0 93300.00000000001 16500.0 ; + RECT 101100.00000000001 14700.0 102900.0 16500.0 ; + RECT 110700.0 14700.0 112500.0 16500.0 ; + RECT 120300.00000000001 14700.0 122100.00000000001 16500.0 ; + RECT 129900.0 14700.0 131700.00000000003 16500.0 ; + RECT 139500.0 14700.0 141300.0 16500.0 ; + RECT 149100.0 14700.0 150900.0 16500.0 ; + RECT 158700.0 14700.0 160500.0 16500.0 ; + RECT 168300.0 14700.0 170100.00000000003 16500.0 ; + RECT 177900.0 14700.0 179700.00000000003 16500.0 ; + RECT 187500.0 14700.0 189300.0 16500.0 ; + RECT 197100.0 14700.0 198900.0 16500.0 ; + RECT 206700.0 14700.0 208500.0 16500.0 ; + RECT 216300.0 14700.0 218100.00000000003 16500.0 ; + RECT 225900.0 14700.0 227700.00000000003 16500.0 ; + RECT 5100.000000000001 24300.0 6900.0 26100.0 ; + RECT 14700.0 24300.0 16500.0 26100.0 ; + RECT 24300.0 24300.0 26100.0 26100.0 ; + RECT 33900.00000000001 24300.0 35700.0 26100.0 ; + RECT 43500.00000000001 24300.0 45300.00000000001 26100.0 ; + RECT 53100.00000000001 24300.0 54900.00000000001 26100.0 ; + RECT 62700.0 24300.0 64500.0 26100.0 ; + RECT 72300.00000000001 24300.0 74100.00000000001 26100.0 ; + RECT 81900.0 24300.0 83700.0 26100.0 ; + RECT 91500.00000000001 24300.0 93300.00000000001 26100.0 ; + RECT 101100.00000000001 24300.0 102900.0 26100.0 ; + RECT 110700.0 24300.0 112500.0 26100.0 ; + RECT 120300.00000000001 24300.0 122100.00000000001 26100.0 ; + RECT 129900.0 24300.0 131700.00000000003 26100.0 ; + RECT 139500.0 24300.0 141300.0 26100.0 ; + RECT 149100.0 24300.0 150900.0 26100.0 ; + RECT 158700.0 24300.0 160500.0 26100.0 ; + RECT 168300.0 24300.0 170100.00000000003 26100.0 ; + RECT 177900.0 24300.0 179700.00000000003 26100.0 ; + RECT 187500.0 24300.0 189300.0 26100.0 ; + RECT 197100.0 24300.0 198900.0 26100.0 ; + RECT 206700.0 24300.0 208500.0 26100.0 ; + RECT 216300.0 24300.0 218100.00000000003 26100.0 ; + RECT 225900.0 24300.0 227700.00000000003 26100.0 ; + RECT 5100.000000000001 33900.00000000001 6900.0 35700.0 ; + RECT 14700.0 33900.00000000001 16500.0 35700.0 ; + RECT 24300.0 33900.00000000001 26100.0 35700.0 ; + RECT 33900.00000000001 33900.00000000001 35700.0 35700.0 ; + RECT 43500.00000000001 33900.00000000001 45300.00000000001 35700.0 ; + RECT 53100.00000000001 33900.00000000001 54900.00000000001 35700.0 ; + RECT 62700.0 33900.00000000001 64500.0 35700.0 ; + RECT 72300.00000000001 33900.00000000001 74100.00000000001 35700.0 ; + RECT 81900.0 33900.00000000001 83700.0 35700.0 ; + RECT 91500.00000000001 33900.00000000001 93300.00000000001 35700.0 ; + RECT 101100.00000000001 33900.00000000001 102900.0 35700.0 ; + RECT 110700.0 33900.00000000001 112500.0 35700.0 ; + RECT 120300.00000000001 33900.00000000001 122100.00000000001 35700.0 ; + RECT 129900.0 33900.00000000001 131700.00000000003 35700.0 ; + RECT 139500.0 33900.00000000001 141300.0 35700.0 ; + RECT 149100.0 33900.00000000001 150900.0 35700.0 ; + RECT 158700.0 33900.00000000001 160500.0 35700.0 ; + RECT 168300.0 33900.00000000001 170100.00000000003 35700.0 ; + RECT 197100.0 33900.00000000001 198900.0 35700.0 ; + RECT 206700.0 33900.00000000001 208500.0 35700.0 ; + RECT 216300.0 33900.00000000001 218100.00000000003 35700.0 ; + RECT 225900.0 33900.00000000001 227700.00000000003 35700.0 ; + RECT 5100.000000000001 43500.00000000001 6900.0 45300.00000000001 ; + RECT 14700.0 43500.00000000001 16500.0 45300.00000000001 ; + RECT 24300.0 43500.00000000001 26100.0 45300.00000000001 ; + RECT 33900.00000000001 43500.00000000001 35700.0 45300.00000000001 ; + RECT 43500.00000000001 43500.00000000001 45300.00000000001 45300.00000000001 ; + RECT 53100.00000000001 43500.00000000001 54900.00000000001 45300.00000000001 ; + RECT 62700.0 43500.00000000001 64500.0 45300.00000000001 ; + RECT 72300.00000000001 43500.00000000001 74100.00000000001 45300.00000000001 ; + RECT 81900.0 43500.00000000001 83700.0 45300.00000000001 ; + RECT 91500.00000000001 43500.00000000001 93300.00000000001 45300.00000000001 ; + RECT 101100.00000000001 43500.00000000001 102900.0 45300.00000000001 ; + RECT 110700.0 43500.00000000001 112500.0 45300.00000000001 ; + RECT 120300.00000000001 43500.00000000001 122100.00000000001 45300.00000000001 ; + RECT 129900.0 43500.00000000001 131700.00000000003 45300.00000000001 ; + RECT 139500.0 43500.00000000001 141300.0 45300.00000000001 ; + RECT 149100.0 43500.00000000001 150900.0 45300.00000000001 ; + RECT 158700.0 43500.00000000001 160500.0 45300.00000000001 ; + RECT 168300.0 43500.00000000001 170100.00000000003 45300.00000000001 ; + RECT 198300.0 43500.00000000001 200100.00000000003 45300.00000000001 ; + RECT 206700.0 43500.00000000001 208500.0 45300.00000000001 ; + RECT 216300.0 43500.00000000001 218100.00000000003 45300.00000000001 ; + RECT 225900.0 43500.00000000001 227700.00000000003 45300.00000000001 ; + RECT 5100.000000000001 53100.00000000001 6900.0 54900.00000000001 ; + RECT 14700.0 53100.00000000001 16500.0 54900.00000000001 ; + RECT 24300.0 53100.00000000001 26100.0 54900.00000000001 ; + RECT 33900.00000000001 53100.00000000001 35700.0 54900.00000000001 ; + RECT 43500.00000000001 53100.00000000001 45300.00000000001 54900.00000000001 ; + RECT 53100.00000000001 53100.00000000001 54900.00000000001 54900.00000000001 ; + RECT 62700.0 53100.00000000001 64500.0 54900.00000000001 ; + RECT 72300.00000000001 53100.00000000001 74100.00000000001 54900.00000000001 ; + RECT 81900.0 53100.00000000001 83700.0 54900.00000000001 ; + RECT 91500.00000000001 53100.00000000001 93300.00000000001 54900.00000000001 ; + RECT 101100.00000000001 53100.00000000001 102900.0 54900.00000000001 ; + RECT 110700.0 53100.00000000001 112500.0 54900.00000000001 ; + RECT 120300.00000000001 53100.00000000001 122100.00000000001 54900.00000000001 ; + RECT 129900.0 53100.00000000001 131700.00000000003 54900.00000000001 ; + RECT 139500.0 53100.00000000001 141300.0 54900.00000000001 ; + RECT 149100.0 53100.00000000001 150900.0 54900.00000000001 ; + RECT 158700.0 53100.00000000001 160500.0 54900.00000000001 ; + RECT 168300.0 53100.00000000001 170100.00000000003 54900.00000000001 ; + RECT 198300.0 53100.00000000001 200100.00000000003 54900.00000000001 ; + RECT 206700.0 53100.00000000001 208500.0 54900.00000000001 ; + RECT 216300.0 53100.00000000001 218100.00000000003 54900.00000000001 ; + RECT 225900.0 53100.00000000001 227700.00000000003 54900.00000000001 ; + RECT 5100.000000000001 62700.0 6900.0 64500.0 ; + RECT 14700.0 62700.0 16500.0 64500.0 ; + RECT 24300.0 62700.0 26100.0 64500.0 ; + RECT 33900.00000000001 62700.0 35700.0 64500.0 ; + RECT 43500.00000000001 62700.0 45300.00000000001 64500.0 ; + RECT 53100.00000000001 62700.0 54900.00000000001 64500.0 ; + RECT 62700.0 62700.0 64500.0 64500.0 ; + RECT 72300.00000000001 62700.0 74100.00000000001 64500.0 ; + RECT 81900.0 62700.0 83700.0 64500.0 ; + RECT 91500.00000000001 62700.0 93300.00000000001 64500.0 ; + RECT 101100.00000000001 62700.0 102900.0 64500.0 ; + RECT 110700.0 62700.0 112500.0 64500.0 ; + RECT 120300.00000000001 62700.0 122100.00000000001 64500.0 ; + RECT 129900.0 62700.0 131700.00000000003 64500.0 ; + RECT 139500.0 62700.0 141300.0 64500.0 ; + RECT 149100.0 62700.0 150900.0 64500.0 ; + RECT 158700.0 62700.0 160500.0 64500.0 ; + RECT 168300.0 62700.0 170100.00000000003 64500.0 ; + RECT 177900.0 62700.0 179700.00000000003 64500.0 ; + RECT 187500.0 62700.0 189300.0 64500.0 ; + RECT 197100.0 62700.0 198900.0 64500.0 ; + RECT 206700.0 62700.0 208500.0 64500.0 ; + RECT 216300.0 62700.0 218100.00000000003 64500.0 ; + RECT 225900.0 62700.0 227700.00000000003 64500.0 ; + RECT 5100.000000000001 72300.00000000001 6900.0 74100.00000000001 ; + RECT 14700.0 72300.00000000001 16500.0 74100.00000000001 ; + RECT 24300.0 72300.00000000001 26100.0 74100.00000000001 ; + RECT 33900.00000000001 72300.00000000001 35700.0 74100.00000000001 ; + RECT 43500.00000000001 72300.00000000001 45300.00000000001 74100.00000000001 ; + RECT 53100.00000000001 72300.00000000001 54900.00000000001 74100.00000000001 ; + RECT 62700.0 72300.00000000001 64500.0 74100.00000000001 ; + RECT 72300.00000000001 72300.00000000001 74100.00000000001 74100.00000000001 ; + RECT 81900.0 72300.00000000001 83700.0 74100.00000000001 ; + RECT 91500.00000000001 72300.00000000001 93300.00000000001 74100.00000000001 ; + RECT 101100.00000000001 72300.00000000001 102900.0 74100.00000000001 ; + RECT 110700.0 72300.00000000001 112500.0 74100.00000000001 ; + RECT 120300.00000000001 72300.00000000001 122100.00000000001 74100.00000000001 ; + RECT 129900.0 72300.00000000001 131700.00000000003 74100.00000000001 ; + RECT 139500.0 72300.00000000001 141300.0 74100.00000000001 ; + RECT 149100.0 72300.00000000001 150900.0 74100.00000000001 ; + RECT 158700.0 72300.00000000001 160500.0 74100.00000000001 ; + RECT 168300.0 72300.00000000001 170100.00000000003 74100.00000000001 ; + RECT 177900.0 72300.00000000001 179700.00000000003 74100.00000000001 ; + RECT 187500.0 72300.00000000001 189300.0 74100.00000000001 ; + RECT 197100.0 72300.00000000001 198900.0 74100.00000000001 ; + RECT 206700.0 72300.00000000001 208500.0 74100.00000000001 ; + RECT 216300.0 72300.00000000001 218100.00000000003 74100.00000000001 ; + RECT 225900.0 72300.00000000001 227700.00000000003 74100.00000000001 ; + RECT 5100.000000000001 81900.0 6900.0 83700.0 ; + RECT 14700.0 81900.0 16500.0 83700.0 ; + RECT 24300.0 81900.0 26100.0 83700.0 ; + RECT 33900.00000000001 81900.0 35700.0 83700.0 ; + RECT 43500.00000000001 81900.0 45300.00000000001 83700.0 ; + RECT 53100.00000000001 81900.0 54900.00000000001 83700.0 ; + RECT 62700.0 81900.0 64500.0 83700.0 ; + RECT 72300.00000000001 81900.0 74100.00000000001 83700.0 ; + RECT 81900.0 81900.0 83700.0 83700.0 ; + RECT 91500.00000000001 81900.0 93300.00000000001 83700.0 ; + RECT 101100.00000000001 81900.0 102900.0 83700.0 ; + RECT 110700.0 81900.0 112500.0 83700.0 ; + RECT 120300.00000000001 81900.0 122100.00000000001 83700.0 ; + RECT 129900.0 81900.0 131700.00000000003 83700.0 ; + RECT 139500.0 81900.0 141300.0 83700.0 ; + RECT 149100.0 81900.0 150900.0 83700.0 ; + RECT 158700.0 81900.0 160500.0 83700.0 ; + RECT 168300.0 81900.0 170100.00000000003 83700.0 ; + RECT 177900.0 81900.0 179700.00000000003 83700.0 ; + RECT 187500.0 81900.0 189300.0 83700.0 ; + RECT 197100.0 81900.0 198900.0 83700.0 ; + RECT 206700.0 81900.0 208500.0 83700.0 ; + RECT 216300.0 81900.0 218100.00000000003 83700.0 ; + RECT 225900.0 81900.0 227700.00000000003 83700.0 ; + RECT 54300.00000000001 91500.00000000001 56100.0 93300.00000000001 ; + RECT 62700.0 91500.00000000001 64500.0 93300.00000000001 ; + RECT 72300.00000000001 91500.00000000001 74100.00000000001 93300.00000000001 ; + RECT 81900.0 91500.00000000001 83700.0 93300.00000000001 ; + RECT 91500.00000000001 91500.00000000001 93300.00000000001 93300.00000000001 ; + RECT 101100.00000000001 91500.00000000001 102900.0 93300.00000000001 ; + RECT 110700.0 91500.00000000001 112500.0 93300.00000000001 ; + RECT 120300.00000000001 91500.00000000001 122100.00000000001 93300.00000000001 ; + RECT 129900.0 91500.00000000001 131700.00000000003 93300.00000000001 ; + RECT 139500.0 91500.00000000001 141300.0 93300.00000000001 ; + RECT 149100.0 91500.00000000001 150900.0 93300.00000000001 ; + RECT 158700.0 91500.00000000001 160500.0 93300.00000000001 ; + RECT 168300.0 91500.00000000001 170100.00000000003 93300.00000000001 ; + RECT 176700.0 91500.00000000001 178500.0 93300.00000000001 ; + RECT 198300.0 91500.00000000001 200100.00000000003 93300.00000000001 ; + RECT 206700.0 91500.00000000001 208500.0 93300.00000000001 ; + RECT 216300.0 91500.00000000001 218100.00000000003 93300.00000000001 ; + RECT 225900.0 91500.00000000001 227700.00000000003 93300.00000000001 ; + RECT 5100.000000000001 101100.00000000001 6900.0 102900.0 ; + RECT 14700.0 101100.00000000001 16500.0 102900.0 ; + RECT 24300.0 101100.00000000001 26100.0 102900.0 ; + RECT 33900.00000000001 101100.00000000001 35700.0 102900.0 ; + RECT 43500.00000000001 101100.00000000001 45300.00000000001 102900.0 ; + RECT 53100.00000000001 101100.00000000001 54900.00000000001 102900.0 ; + RECT 61500.00000000001 101100.00000000001 63300.00000000001 102900.0 ; + RECT 81900.0 101100.00000000001 83700.0 102900.0 ; + RECT 91500.00000000001 101100.00000000001 93300.00000000001 102900.0 ; + RECT 101100.00000000001 101100.00000000001 102900.0 102900.0 ; + RECT 110700.0 101100.00000000001 112500.0 102900.0 ; + RECT 120300.00000000001 101100.00000000001 122100.00000000001 102900.0 ; + RECT 129900.0 101100.00000000001 131700.00000000003 102900.0 ; + RECT 139500.0 101100.00000000001 141300.0 102900.0 ; + RECT 149100.0 101100.00000000001 150900.0 102900.0 ; + RECT 158700.0 101100.00000000001 160500.0 102900.0 ; + RECT 168300.0 101100.00000000001 170100.00000000003 102900.0 ; + RECT 177900.0 101100.00000000001 179700.00000000003 102900.0 ; + RECT 187500.0 101100.00000000001 189300.0 102900.0 ; + RECT 197100.0 101100.00000000001 198900.0 102900.0 ; + RECT 206700.0 101100.00000000001 208500.0 102900.0 ; + RECT 216300.0 101100.00000000001 218100.00000000003 102900.0 ; + RECT 225900.0 101100.00000000001 227700.00000000003 102900.0 ; + RECT 5100.000000000001 110700.0 6900.0 112500.0 ; + RECT 14700.0 110700.0 16500.0 112500.0 ; + RECT 24300.0 110700.0 26100.0 112500.0 ; + RECT 33900.00000000001 110700.0 35700.0 112500.0 ; + RECT 43500.00000000001 110700.0 45300.00000000001 112500.0 ; + RECT 53100.00000000001 110700.0 54900.00000000001 112500.0 ; + RECT 61500.00000000001 110700.0 63300.00000000001 112500.0 ; + RECT 187500.0 110700.0 189300.0 112500.0 ; + RECT 197100.0 110700.0 198900.0 112500.0 ; + RECT 206700.0 110700.0 208500.0 112500.0 ; + RECT 216300.0 110700.0 218100.00000000003 112500.0 ; + RECT 225900.0 110700.0 227700.00000000003 112500.0 ; + RECT 5100.000000000001 120300.00000000001 6900.0 122100.00000000001 ; + RECT 14700.0 120300.00000000001 16500.0 122100.00000000001 ; + RECT 24300.0 120300.00000000001 26100.0 122100.00000000001 ; + RECT 33900.00000000001 120300.00000000001 35700.0 122100.00000000001 ; + RECT 43500.00000000001 120300.00000000001 45300.00000000001 122100.00000000001 ; + RECT 53100.00000000001 120300.00000000001 54900.00000000001 122100.00000000001 ; + RECT 62700.0 120300.00000000001 64500.0 122100.00000000001 ; + RECT 72300.00000000001 120300.00000000001 74100.00000000001 122100.00000000001 ; + RECT 80700.0 120300.00000000001 82500.0 122100.00000000001 ; + RECT 177900.0 120300.00000000001 179700.00000000003 122100.00000000001 ; + RECT 187500.0 120300.00000000001 189300.0 122100.00000000001 ; + RECT 197100.0 120300.00000000001 198900.0 122100.00000000001 ; + RECT 206700.0 120300.00000000001 208500.0 122100.00000000001 ; + RECT 216300.0 120300.00000000001 218100.00000000003 122100.00000000001 ; + RECT 225900.0 120300.00000000001 227700.00000000003 122100.00000000001 ; + RECT 43500.00000000001 129900.0 45300.00000000001 131700.00000000003 ; + RECT 53100.00000000001 129900.0 54900.00000000001 131700.00000000003 ; + RECT 62700.0 129900.0 64500.0 131700.00000000003 ; + RECT 91500.00000000001 129900.0 93300.00000000001 131700.00000000003 ; + RECT 101100.00000000001 129900.0 102900.0 131700.00000000003 ; + RECT 121500.00000000001 129900.0 123300.00000000001 131700.00000000003 ; + RECT 129900.0 129900.0 131700.00000000003 131700.00000000003 ; + RECT 139500.0 129900.0 141300.0 131700.00000000003 ; + RECT 149100.0 129900.0 150900.0 131700.00000000003 ; + RECT 158700.0 129900.0 160500.0 131700.00000000003 ; + RECT 168300.0 129900.0 170100.00000000003 131700.00000000003 ; + RECT 177900.0 129900.0 179700.00000000003 131700.00000000003 ; + RECT 187500.0 129900.0 189300.0 131700.00000000003 ; + RECT 197100.0 129900.0 198900.0 131700.00000000003 ; + RECT 206700.0 129900.0 208500.0 131700.00000000003 ; + RECT 216300.0 129900.0 218100.00000000003 131700.00000000003 ; + RECT 225900.0 129900.0 227700.00000000003 131700.00000000003 ; + RECT 43500.00000000001 139500.0 45300.00000000001 141300.0 ; + RECT 53100.00000000001 139500.0 54900.00000000001 141300.0 ; + RECT 62700.0 139500.0 64500.0 141300.0 ; + RECT 177900.0 139500.0 179700.00000000003 141300.0 ; + RECT 187500.0 139500.0 189300.0 141300.0 ; + RECT 197100.0 139500.0 198900.0 141300.0 ; + RECT 206700.0 139500.0 208500.0 141300.0 ; + RECT 216300.0 139500.0 218100.00000000003 141300.0 ; + RECT 225900.0 139500.0 227700.00000000003 141300.0 ; + RECT 44700.0 149100.0 46500.0 150900.0 ; + RECT 53100.00000000001 149100.0 54900.00000000001 150900.0 ; + RECT 62700.0 149100.0 64500.0 150900.0 ; + RECT 72300.00000000001 149100.0 74100.00000000001 150900.0 ; + RECT 81900.0 149100.0 83700.0 150900.0 ; + RECT 91500.00000000001 149100.0 93300.00000000001 150900.0 ; + RECT 101100.00000000001 149100.0 102900.0 150900.0 ; + RECT 129900.0 149100.0 131700.00000000003 150900.0 ; + RECT 139500.0 149100.0 141300.0 150900.0 ; + RECT 149100.0 149100.0 150900.0 150900.0 ; + RECT 158700.0 149100.0 160500.0 150900.0 ; + RECT 168300.0 149100.0 170100.00000000003 150900.0 ; + RECT 177900.0 149100.0 179700.00000000003 150900.0 ; + RECT 187500.0 149100.0 189300.0 150900.0 ; + RECT 197100.0 149100.0 198900.0 150900.0 ; + RECT 206700.0 149100.0 208500.0 150900.0 ; + RECT 216300.0 149100.0 218100.00000000003 150900.0 ; + RECT 225900.0 149100.0 227700.00000000003 150900.0 ; + RECT 43500.00000000001 158700.0 45300.00000000001 160500.0 ; + RECT 53100.00000000001 158700.0 54900.00000000001 160500.0 ; + RECT 62700.0 158700.0 64500.0 160500.0 ; + RECT 72300.00000000001 158700.0 74100.00000000001 160500.0 ; + RECT 80700.0 158700.0 82500.0 160500.0 ; + RECT 177900.0 158700.0 179700.00000000003 160500.0 ; + RECT 187500.0 158700.0 189300.0 160500.0 ; + RECT 197100.0 158700.0 198900.0 160500.0 ; + RECT 206700.0 158700.0 208500.0 160500.0 ; + RECT 216300.0 158700.0 218100.00000000003 160500.0 ; + RECT 225900.0 158700.0 227700.00000000003 160500.0 ; + RECT 44700.0 168300.0 46500.0 170100.00000000003 ; + RECT 53100.00000000001 168300.0 54900.00000000001 170100.00000000003 ; + RECT 62700.0 168300.0 64500.0 170100.00000000003 ; + RECT 91500.00000000001 168300.0 93300.00000000001 170100.00000000003 ; + RECT 101100.00000000001 168300.0 102900.0 170100.00000000003 ; + RECT 129900.0 168300.0 131700.00000000003 170100.00000000003 ; + RECT 139500.0 168300.0 141300.0 170100.00000000003 ; + RECT 149100.0 168300.0 150900.0 170100.00000000003 ; + RECT 158700.0 168300.0 160500.0 170100.00000000003 ; + RECT 168300.0 168300.0 170100.00000000003 170100.00000000003 ; + RECT 177900.0 168300.0 179700.00000000003 170100.00000000003 ; + RECT 187500.0 168300.0 189300.0 170100.00000000003 ; + RECT 197100.0 168300.0 198900.0 170100.00000000003 ; + RECT 206700.0 168300.0 208500.0 170100.00000000003 ; + RECT 216300.0 168300.0 218100.00000000003 170100.00000000003 ; + RECT 225900.0 168300.0 227700.00000000003 170100.00000000003 ; + RECT 5100.000000000001 177900.0 6900.0 179700.00000000003 ; + RECT 14700.0 177900.0 16500.0 179700.00000000003 ; + RECT 24300.0 177900.0 26100.0 179700.00000000003 ; + RECT 33900.00000000001 177900.0 35700.0 179700.00000000003 ; + RECT 43500.00000000001 177900.0 45300.00000000001 179700.00000000003 ; + RECT 53100.00000000001 177900.0 54900.00000000001 179700.00000000003 ; + RECT 62700.0 177900.0 64500.0 179700.00000000003 ; + RECT 177900.0 177900.0 179700.00000000003 179700.00000000003 ; + RECT 187500.0 177900.0 189300.0 179700.00000000003 ; + RECT 197100.0 177900.0 198900.0 179700.00000000003 ; + RECT 206700.0 177900.0 208500.0 179700.00000000003 ; + RECT 216300.0 177900.0 218100.00000000003 179700.00000000003 ; + RECT 225900.0 177900.0 227700.00000000003 179700.00000000003 ; + RECT 5100.000000000001 187500.0 6900.0 189300.0 ; + RECT 14700.0 187500.0 16500.0 189300.0 ; + RECT 24300.0 187500.0 26100.0 189300.0 ; + RECT 44700.0 187500.0 46500.0 189300.0 ; + RECT 53100.00000000001 187500.0 54900.00000000001 189300.0 ; + RECT 62700.0 187500.0 64500.0 189300.0 ; + RECT 72300.00000000001 187500.0 74100.00000000001 189300.0 ; + RECT 81900.0 187500.0 83700.0 189300.0 ; + RECT 91500.00000000001 187500.0 93300.00000000001 189300.0 ; + RECT 101100.00000000001 187500.0 102900.0 189300.0 ; + RECT 131100.0 187500.0 132900.0 189300.0 ; + RECT 139500.0 187500.0 141300.0 189300.0 ; + RECT 149100.0 187500.0 150900.0 189300.0 ; + RECT 158700.0 187500.0 160500.0 189300.0 ; + RECT 168300.0 187500.0 170100.00000000003 189300.0 ; + RECT 198300.0 187500.0 200100.00000000003 189300.0 ; + RECT 206700.0 187500.0 208500.0 189300.0 ; + RECT 216300.0 187500.0 218100.00000000003 189300.0 ; + RECT 225900.0 187500.0 227700.00000000003 189300.0 ; + RECT 5100.000000000001 197100.0 6900.0 198900.0 ; + RECT 14700.0 197100.0 16500.0 198900.0 ; + RECT 24300.0 197100.0 26100.0 198900.0 ; + RECT 33900.00000000001 197100.0 35700.0 198900.0 ; + RECT 43500.00000000001 197100.0 45300.00000000001 198900.0 ; + RECT 53100.00000000001 197100.0 54900.00000000001 198900.0 ; + RECT 62700.0 197100.0 64500.0 198900.0 ; + RECT 72300.00000000001 197100.0 74100.00000000001 198900.0 ; + RECT 80700.0 197100.0 82500.0 198900.0 ; + RECT 198300.0 197100.0 200100.00000000003 198900.0 ; + RECT 206700.0 197100.0 208500.0 198900.0 ; + RECT 216300.0 197100.0 218100.00000000003 198900.0 ; + RECT 225900.0 197100.0 227700.00000000003 198900.0 ; + RECT 5100.000000000001 206700.0 6900.0 208500.0 ; + RECT 14700.0 206700.0 16500.0 208500.0 ; + RECT 24300.0 206700.0 26100.0 208500.0 ; + RECT 44700.0 206700.0 46500.0 208500.0 ; + RECT 53100.00000000001 206700.0 54900.00000000001 208500.0 ; + RECT 62700.0 206700.0 64500.0 208500.0 ; + RECT 72300.00000000001 206700.0 74100.00000000001 208500.0 ; + RECT 81900.0 206700.0 83700.0 208500.0 ; + RECT 91500.00000000001 206700.0 93300.00000000001 208500.0 ; + RECT 101100.00000000001 206700.0 102900.0 208500.0 ; + RECT 110700.0 206700.0 112500.0 208500.0 ; + RECT 120300.00000000001 206700.0 122100.00000000001 208500.0 ; + RECT 129900.0 206700.0 131700.00000000003 208500.0 ; + RECT 139500.0 206700.0 141300.0 208500.0 ; + RECT 149100.0 206700.0 150900.0 208500.0 ; + RECT 158700.0 206700.0 160500.0 208500.0 ; + RECT 168300.0 206700.0 170100.00000000003 208500.0 ; + RECT 198300.0 206700.0 200100.00000000003 208500.0 ; + RECT 206700.0 206700.0 208500.0 208500.0 ; + RECT 216300.0 206700.0 218100.00000000003 208500.0 ; + RECT 225900.0 206700.0 227700.00000000003 208500.0 ; + RECT 5100.000000000001 216300.0 6900.0 218100.00000000003 ; + RECT 14700.0 216300.0 16500.0 218100.00000000003 ; + RECT 24300.0 216300.0 26100.0 218100.00000000003 ; + RECT 33900.00000000001 216300.0 35700.0 218100.00000000003 ; + RECT 81900.0 216300.0 83700.0 218100.00000000003 ; + RECT 91500.00000000001 216300.0 93300.00000000001 218100.00000000003 ; + RECT 101100.00000000001 216300.0 102900.0 218100.00000000003 ; + RECT 110700.0 216300.0 112500.0 218100.00000000003 ; + RECT 120300.00000000001 216300.0 122100.00000000001 218100.00000000003 ; + RECT 198300.0 216300.0 200100.00000000003 218100.00000000003 ; + RECT 206700.0 216300.0 208500.0 218100.00000000003 ; + RECT 216300.0 216300.0 218100.00000000003 218100.00000000003 ; + RECT 225900.0 216300.0 227700.00000000003 218100.00000000003 ; + RECT 5100.000000000001 225900.0 6900.0 227700.00000000003 ; + RECT 14700.0 225900.0 16500.0 227700.00000000003 ; + RECT 24300.0 225900.0 26100.0 227700.00000000003 ; + RECT 33900.00000000001 225900.0 35700.0 227700.00000000003 ; + RECT 43500.00000000001 225900.0 45300.00000000001 227700.00000000003 ; + RECT 53100.00000000001 225900.0 54900.00000000001 227700.00000000003 ; + RECT 62700.0 225900.0 64500.0 227700.00000000003 ; + RECT 72300.00000000001 225900.0 74100.00000000001 227700.00000000003 ; + RECT 81900.0 225900.0 83700.0 227700.00000000003 ; + RECT 91500.00000000001 225900.0 93300.00000000001 227700.00000000003 ; + RECT 101100.00000000001 225900.0 102900.0 227700.00000000003 ; + RECT 110700.0 225900.0 112500.0 227700.00000000003 ; + RECT 120300.00000000001 225900.0 122100.00000000001 227700.00000000003 ; + RECT 129900.0 225900.0 131700.00000000003 227700.00000000003 ; + RECT 139500.0 225900.0 141300.0 227700.00000000003 ; + RECT 149100.0 225900.0 150900.0 227700.00000000003 ; + RECT 158700.0 225900.0 160500.0 227700.00000000003 ; + RECT 168300.0 225900.0 170100.00000000003 227700.00000000003 ; + RECT 198300.0 225900.0 200100.00000000003 227700.00000000003 ; + RECT 206700.0 225900.0 208500.0 227700.00000000003 ; + RECT 216300.0 225900.0 218100.00000000003 227700.00000000003 ; + RECT 225900.0 225900.0 227700.00000000003 227700.00000000003 ; + RECT 5100.000000000001 235500.0 6900.0 237300.0 ; + RECT 14700.0 235500.0 16500.0 237300.0 ; + RECT 24300.0 235500.0 26100.0 237300.0 ; + RECT 33900.00000000001 235500.0 35700.0 237300.0 ; + RECT 43500.00000000001 235500.0 45300.00000000001 237300.0 ; + RECT 53100.00000000001 235500.0 54900.00000000001 237300.0 ; + RECT 62700.0 235500.0 64500.0 237300.0 ; + RECT 72300.00000000001 235500.0 74100.00000000001 237300.0 ; + RECT 81900.0 235500.0 83700.0 237300.0 ; + RECT 91500.00000000001 235500.0 93300.00000000001 237300.0 ; + RECT 101100.00000000001 235500.0 102900.0 237300.0 ; + RECT 110700.0 235500.0 112500.0 237300.0 ; + RECT 120300.00000000001 235500.0 122100.00000000001 237300.0 ; + RECT 129900.0 235500.0 131700.00000000003 237300.0 ; + RECT 139500.0 235500.0 141300.0 237300.0 ; + RECT 149100.0 235500.0 150900.0 237300.0 ; + RECT 158700.0 235500.0 160500.0 237300.0 ; + RECT 168300.0 235500.0 170100.00000000003 237300.0 ; + RECT 198300.0 235500.0 200100.00000000003 237300.0 ; + RECT 206700.0 235500.0 208500.0 237300.0 ; + RECT 216300.0 235500.0 218100.00000000003 237300.0 ; + RECT 225900.0 235500.0 227700.00000000003 237300.0 ; + RECT 5100.000000000001 245100.0 6900.0 246900.0 ; + RECT 14700.0 245100.0 16500.0 246900.0 ; + RECT 24300.0 245100.0 26100.0 246900.0 ; + RECT 33900.00000000001 245100.0 35700.0 246900.0 ; + RECT 43500.00000000001 245100.0 45300.00000000001 246900.0 ; + RECT 53100.00000000001 245100.0 54900.00000000001 246900.0 ; + RECT 62700.0 245100.0 64500.0 246900.0 ; + RECT 72300.00000000001 245100.0 74100.00000000001 246900.0 ; + RECT 81900.0 245100.0 83700.0 246900.0 ; + RECT 91500.00000000001 245100.0 93300.00000000001 246900.0 ; + RECT 101100.00000000001 245100.0 102900.0 246900.0 ; + RECT 110700.0 245100.0 112500.0 246900.0 ; + RECT 120300.00000000001 245100.0 122100.00000000001 246900.0 ; + RECT 129900.0 245100.0 131700.00000000003 246900.0 ; + RECT 139500.0 245100.0 141300.0 246900.0 ; + RECT 149100.0 245100.0 150900.0 246900.0 ; + RECT 158700.0 245100.0 160500.0 246900.0 ; + RECT 168300.0 245100.0 170100.00000000003 246900.0 ; + RECT 198300.0 245100.0 200100.00000000003 246900.0 ; + RECT 206700.0 245100.0 208500.0 246900.0 ; + RECT 216300.0 245100.0 218100.00000000003 246900.0 ; + RECT 225900.0 245100.0 227700.00000000003 246900.0 ; + RECT 5100.000000000001 254700.0 6900.0 256500.0 ; + RECT 14700.0 254700.0 16500.0 256500.0 ; + RECT 24300.0 254700.0 26100.0 256500.0 ; + RECT 33900.00000000001 254700.0 35700.0 256500.0 ; + RECT 43500.00000000001 254700.0 45300.00000000001 256500.0 ; + RECT 53100.00000000001 254700.0 54900.00000000001 256500.0 ; + RECT 62700.0 254700.0 64500.0 256500.0 ; + RECT 72300.00000000001 254700.0 74100.00000000001 256500.0 ; + RECT 81900.0 254700.0 83700.0 256500.0 ; + RECT 91500.00000000001 254700.0 93300.00000000001 256500.0 ; + RECT 101100.00000000001 254700.0 102900.0 256500.0 ; + RECT 110700.0 254700.0 112500.0 256500.0 ; + RECT 120300.00000000001 254700.0 122100.00000000001 256500.0 ; + RECT 129900.0 254700.0 131700.00000000003 256500.0 ; + RECT 139500.0 254700.0 141300.0 256500.0 ; + RECT 149100.0 254700.0 150900.0 256500.0 ; + RECT 158700.0 254700.0 160500.0 256500.0 ; + RECT 168300.0 254700.0 170100.00000000003 256500.0 ; + RECT 198300.0 254700.0 200100.00000000003 256500.0 ; + RECT 206700.0 254700.0 208500.0 256500.0 ; + RECT 216300.0 254700.0 218100.00000000003 256500.0 ; + RECT 225900.0 254700.0 227700.00000000003 256500.0 ; + RECT 5100.000000000001 264300.0 6900.0 266100.0 ; + RECT 14700.0 264300.0 16500.0 266100.0 ; + RECT 24300.0 264300.0 26100.0 266100.0 ; + RECT 33900.00000000001 264300.0 35700.0 266100.0 ; + RECT 43500.00000000001 264300.0 45300.00000000001 266100.0 ; + RECT 53100.00000000001 264300.0 54900.00000000001 266100.0 ; + RECT 62700.0 264300.0 64500.0 266100.0 ; + RECT 72300.00000000001 264300.0 74100.00000000001 266100.0 ; + RECT 81900.0 264300.0 83700.0 266100.0 ; + RECT 91500.00000000001 264300.0 93300.00000000001 266100.0 ; + RECT 101100.00000000001 264300.0 102900.0 266100.0 ; + RECT 110700.0 264300.0 112500.0 266100.0 ; + RECT 120300.00000000001 264300.0 122100.00000000001 266100.0 ; + RECT 129900.0 264300.0 131700.00000000003 266100.0 ; + RECT 139500.0 264300.0 141300.0 266100.0 ; + RECT 149100.0 264300.0 150900.0 266100.0 ; + RECT 158700.0 264300.0 160500.0 266100.0 ; + RECT 168300.0 264300.0 170100.00000000003 266100.0 ; + RECT 198300.0 264300.0 200100.00000000003 266100.0 ; + RECT 206700.0 264300.0 208500.0 266100.0 ; + RECT 216300.0 264300.0 218100.00000000003 266100.0 ; + RECT 225900.0 264300.0 227700.00000000003 266100.0 ; + RECT 5100.000000000001 273900.0 6900.0 275700.0 ; + RECT 14700.0 273900.0 16500.0 275700.0 ; + RECT 24300.0 273900.0 26100.0 275700.0 ; + RECT 33900.00000000001 273900.0 35700.0 275700.0 ; + RECT 43500.00000000001 273900.0 45300.00000000001 275700.0 ; + RECT 53100.00000000001 273900.0 54900.00000000001 275700.0 ; + RECT 62700.0 273900.0 64500.0 275700.0 ; + RECT 72300.00000000001 273900.0 74100.00000000001 275700.0 ; + RECT 81900.0 273900.0 83700.0 275700.0 ; + RECT 91500.00000000001 273900.0 93300.00000000001 275700.0 ; + RECT 101100.00000000001 273900.0 102900.0 275700.0 ; + RECT 110700.0 273900.0 112500.0 275700.0 ; + RECT 120300.00000000001 273900.0 122100.00000000001 275700.0 ; + RECT 129900.0 273900.0 131700.00000000003 275700.0 ; + RECT 139500.0 273900.0 141300.0 275700.0 ; + RECT 149100.0 273900.0 150900.0 275700.0 ; + RECT 158700.0 273900.0 160500.0 275700.0 ; + RECT 168300.0 273900.0 170100.00000000003 275700.0 ; + RECT 177900.0 273900.0 179700.00000000003 275700.0 ; + RECT 187500.0 273900.0 189300.0 275700.0 ; + RECT 197100.0 273900.0 198900.0 275700.0 ; + RECT 206700.0 273900.0 208500.0 275700.0 ; + RECT 216300.0 273900.0 218100.00000000003 275700.0 ; + RECT 225900.0 273900.0 227700.00000000003 275700.0 ; + RECT 5100.000000000001 283500.0 6900.0 285300.0 ; + RECT 14700.0 283500.0 16500.0 285300.0 ; + RECT 24300.0 283500.0 26100.0 285300.0 ; + RECT 33900.00000000001 283500.0 35700.0 285300.0 ; + RECT 43500.00000000001 283500.0 45300.00000000001 285300.0 ; + RECT 53100.00000000001 283500.0 54900.00000000001 285300.0 ; + RECT 91500.00000000001 283500.0 93300.00000000001 285300.0 ; + RECT 101100.00000000001 283500.0 102900.0 285300.0 ; + RECT 110700.0 283500.0 112500.0 285300.0 ; + RECT 120300.00000000001 283500.0 122100.00000000001 285300.0 ; + RECT 129900.0 283500.0 131700.00000000003 285300.0 ; + RECT 139500.0 283500.0 141300.0 285300.0 ; + RECT 149100.0 283500.0 150900.0 285300.0 ; + RECT 158700.0 283500.0 160500.0 285300.0 ; + RECT 168300.0 283500.0 170100.00000000003 285300.0 ; + RECT 177900.0 283500.0 179700.00000000003 285300.0 ; + RECT 187500.0 283500.0 189300.0 285300.0 ; + RECT 197100.0 283500.0 198900.0 285300.0 ; + RECT 206700.0 283500.0 208500.0 285300.0 ; + RECT 216300.0 283500.0 218100.00000000003 285300.0 ; + RECT 225900.0 283500.0 227700.00000000003 285300.0 ; + RECT 5100.000000000001 293100.0 6900.0 294900.00000000006 ; + RECT 14700.0 293100.0 16500.0 294900.00000000006 ; + RECT 24300.0 293100.0 26100.0 294900.00000000006 ; + RECT 33900.00000000001 293100.0 35700.0 294900.00000000006 ; + RECT 43500.00000000001 293100.0 45300.00000000001 294900.00000000006 ; + RECT 51900.00000000001 293100.0 53700.0 294900.00000000006 ; + RECT 72300.00000000001 293100.0 74100.00000000001 294900.00000000006 ; + RECT 81900.0 293100.0 83700.0 294900.00000000006 ; + RECT 91500.00000000001 293100.0 93300.00000000001 294900.00000000006 ; + RECT 101100.00000000001 293100.0 102900.0 294900.00000000006 ; + RECT 110700.0 293100.0 112500.0 294900.00000000006 ; + RECT 120300.00000000001 293100.0 122100.00000000001 294900.00000000006 ; + RECT 129900.0 293100.0 131700.00000000003 294900.00000000006 ; + RECT 139500.0 293100.0 141300.0 294900.00000000006 ; + RECT 149100.0 293100.0 150900.0 294900.00000000006 ; + RECT 158700.0 293100.0 160500.0 294900.00000000006 ; + RECT 168300.0 293100.0 170100.00000000003 294900.00000000006 ; + RECT 177900.0 293100.0 179700.00000000003 294900.00000000006 ; + RECT 187500.0 293100.0 189300.0 294900.00000000006 ; + RECT 197100.0 293100.0 198900.0 294900.00000000006 ; + RECT 206700.0 293100.0 208500.0 294900.00000000006 ; + RECT 216300.0 293100.0 218100.00000000003 294900.00000000006 ; + RECT 225900.0 293100.0 227700.00000000003 294900.00000000006 ; + RECT 17200.000000000004 160400.0 16400.000000000004 161200.00000000003 ; + RECT 17200.000000000004 129199.99999999999 16400.000000000004 130000.0 ; + RECT 14800.0 141200.0 14000.0 142000.0 ; + RECT 17200.000000000004 141200.0 16400.000000000004 142000.0 ; + RECT 14800.0 160400.0 14000.0 161200.00000000003 ; + RECT 190000.00000000003 186800.0 189200.00000000003 187600.00000000003 ; + RECT 180400.00000000003 206000.0 179600.00000000003 206800.0 ; + RECT 180400.00000000003 222800.0 179600.00000000003 223600.00000000003 ; + RECT 34000.0 141200.0 33200.0 142000.0 ; + RECT 180400.00000000003 30800.0 179600.00000000003 31600.0 ; + RECT 190000.00000000003 47600.00000000001 189200.00000000003 48400.00000000001 ; + RECT 190000.00000000003 30800.0 189200.00000000003 31600.0 ; + RECT 180400.00000000003 47600.00000000001 179600.00000000003 48400.00000000001 ; + RECT 34000.0 160400.0 33200.0 161200.00000000003 ; + RECT 190000.00000000003 242000.0 189200.00000000003 242800.0 ; + RECT 190000.00000000003 206000.0 189200.00000000003 206800.0 ; + RECT 180400.00000000003 261200.0 179600.00000000003 262000.0 ; + RECT 190000.00000000003 261200.0 189200.00000000003 262000.0 ; + RECT 180400.00000000003 242000.0 179600.00000000003 242800.0 ; + RECT 190000.00000000003 222800.0 189200.00000000003 223600.00000000003 ; + RECT 180400.00000000003 186800.0 179600.00000000003 187600.00000000003 ; + RECT 29200.000000000004 129199.99999999999 28400.000000000004 130000.0 ; + RECT 192400.00000000003 -400.00000000000006 191600.00000000003 399.9999999999999 ; + RECT 60400.0 210800.0 59600.0 211600.00000000003 ; + RECT 19600.0 153200.0 18800.0 154000.0 ; + RECT 12400.000000000002 134000.0 11600.000000000002 134800.0 ; + RECT 19600.0 134000.0 18800.0 134800.0 ; + RECT 12400.000000000002 150799.99999999997 11600.000000000002 151600.0 ; + RECT 211600.00000000003 -400.00000000000006 210800.0 399.9999999999999 ; + RECT 192400.00000000003 198800.0 191600.00000000003 199600.00000000003 ; + RECT 185200.00000000003 237200.0 184400.0 238000.0 ; + RECT 192400.00000000003 256399.99999999997 191600.00000000003 257200.0 ; + RECT 192400.00000000003 237200.0 191600.00000000003 238000.0 ; + RECT 185200.00000000003 201200.0 184400.0 202000.0 ; + RECT 185200.00000000003 263600.0 184400.0 264400.00000000006 ; + RECT 182800.0 237200.0 182000.0 238000.0 ; + RECT 175600.00000000003 220400.0 174800.0 221200.00000000003 ; + RECT 185200.00000000003 220400.0 184400.0 221200.00000000003 ; + RECT 29200.000000000004 148400.0 28400.000000000004 149200.00000000003 ; + RECT 185200.00000000003 256399.99999999997 184400.0 257200.0 ; + RECT 29200.000000000004 165200.0 28400.000000000004 166000.0 ; + RECT 182800.0 198800.0 182000.0 199600.00000000003 ; + RECT 192400.00000000003 218000.0 191600.00000000003 218800.0 ; + END + END sram_2_16_scn4m_subm +END LIBRARY diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.py b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.py new file mode 100644 index 00000000..1b26c11d --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.py @@ -0,0 +1,18 @@ +word_size = 2 +num_words = 16 + +tech_name = "scn4m_subm" +process_corners = ["TT"] +supply_voltages = [ 5.0 ] +temperatures = [ 25 ] + +output_path = "temp" +output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) + +#Setting for multiport +netlist_only = True +bitcell = "pbitcell" +replica_bitcell="replica_pbitcell" +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 1 diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.sp b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.sp new file mode 100644 index 00000000..3b8783d8 --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.sp @@ -0,0 +1,767 @@ +************************************************** +* OpenRAM generated memory. +* Words: 16 +* Data bits: 2 +* Banks: 1 +* Column mux: 1:1 +************************************************** +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS + +* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p + +* ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p + +.SUBCKT pinv_2 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pinv_2 + +.SUBCKT dff_inv_2 D Q Qb clk vdd gnd +Xdff_inv_dff D Q clk vdd gnd dff +Xdff_inv_inv1 Q Qb vdd gnd pinv_2 +.ENDS dff_inv_2 + +.SUBCKT dff_inv_array_2x1_1 din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd +XXdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_inv_2 +XXdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_inv_2 +.ENDS dff_inv_array_2x1_1 + +* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p + +.SUBCKT pnand2_1 A B Z vdd gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand2_1 + +.SUBCKT pnand3_1 A B C Z vdd gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand3_1 + +* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p + +.SUBCKT pinv_3 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_3 + +.SUBCKT pinv_4 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pinv_4 + +* ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p + +* ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p + +.SUBCKT pinv_5 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +.ENDS pinv_5 + +.SUBCKT pinvbuf_2_4_1 A Zb Z vdd gnd +Xbuf_inv1 A zb_int vdd gnd pinv_3 +Xbuf_inv2 zb_int z_int vdd gnd pinv_4 +Xbuf_inv3 z_int Zb vdd gnd pinv_5 +Xbuf_inv4 zb_int Z vdd gnd pinv_5 +.ENDS pinvbuf_2_4_1 + +.SUBCKT pinv_6 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_6 + +.SUBCKT pinv_7 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +.ENDS pinv_7 + +* ptx M{0} {1} n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p + +* ptx M{0} {1} p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p + +.SUBCKT pinv_8 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p +Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p +.ENDS pinv_8 + +* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p + +* ptx M{0} {1} p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p + +* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p + +* ptx M{0} {1} n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p + +.SUBCKT replica_pbitcell_1RW_1W_1R bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd +Minverter_nmos_left Q vdd gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Minverter_nmos_right gnd Q vdd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Minverter_pmos_left Q vdd vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p +Minverter_pmos_right vdd Q vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p +Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mreadwrite_nmos_right0 vdd wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mwrite_nmos_left0 bl1 wl1 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mwrite_nmos_right0 vdd wl1 br1 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mread_access_nmos_left0 RA_to_R_left0 vdd gnd gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +Mread_access_nmos_right0 gnd Q RA_to_R_right0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +Mread_nmos_left0 bl2 wl2 RA_to_R_left0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +Mread_nmos_right0 RA_to_R_right0 wl2 br2 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +.ENDS replica_pbitcell_1RW_1W_1R + +.SUBCKT replica_pbitcell bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd +Xpbitcell bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd replica_pbitcell_1RW_1W_1R +.ENDS replica_pbitcell + +.SUBCKT pbitcell_1RW_1W_1R bl0 br0 bl1 br1 bl2 br2 wl0 wl1 wl2 vdd gnd +Minverter_nmos_left Q Q_bar gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Minverter_nmos_right gnd Q Q_bar gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Minverter_pmos_left Q Q_bar vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p +Minverter_pmos_right vdd Q Q_bar vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.0u ps=2.0u as=0.6000000000000001p ad=0.6000000000000001p +Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mreadwrite_nmos_right0 Q_bar wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mwrite_nmos_left0 bl1 wl1 Q gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mwrite_nmos_right0 Q_bar wl1 br1 gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Mread_access_nmos_left0 RA_to_R_left0 Q_bar gnd gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +Mread_access_nmos_right0 gnd Q RA_to_R_right0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +Mread_nmos_left0 bl2 wl2 RA_to_R_left0 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +Mread_nmos_right0 RA_to_R_right0 wl2 br2 gnd n m=1 w=1.2000000000000002u l=0.4u pd=3.2u ps=3.2u as=1.2000000000000002p ad=1.2000000000000002p +.ENDS pbitcell_1RW_1W_1R + +.SUBCKT bitcell_array_8x1_1 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 vdd gnd +Xbit_r0_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R +Xbit_r1_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R +Xbit_r2_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R +Xbit_r3_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R +Xbit_r4_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R +Xbit_r5_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R +Xbit_r6_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R +Xbit_r7_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R +.ENDS bitcell_array_8x1_1 + +.SUBCKT pinv_9 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_9 + +.SUBCKT delay_chain_1 in out vdd gnd +Xdinv0 in dout_1 vdd gnd pinv_9 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_9 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_9 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_9 +Xdinv1 dout_1 dout_2 vdd gnd pinv_9 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_9 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_9 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_9 +Xdinv2 dout_2 dout_3 vdd gnd pinv_9 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_9 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_9 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_9 +Xdinv3 dout_3 out vdd gnd pinv_9 +Xdload_3_0 out n_3_0 vdd gnd pinv_9 +Xdload_3_1 out n_3_1 vdd gnd pinv_9 +Xdload_3_2 out n_3_2 vdd gnd pinv_9 +.ENDS delay_chain_1 + +.SUBCKT pinv_10 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_10 + +* ptx M{0} {1} p m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p + +.SUBCKT replica_bitline_rw en out vdd gnd +Xrbl_inv bl0_0 out vdd gnd pinv_10 +Mrbl_access_tx vdd delayed_en bl0_0 vdd p m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Xdelay_chain en delayed_en vdd gnd delay_chain_1 +Xbitcell bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 delayed_en delayed_en delayed_en vdd gnd replica_pbitcell +Xload bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vdd gnd bitcell_array_8x1_1 +.ENDS replica_bitline_rw + +.SUBCKT control_logic_rw csb web clk s_en w_en clk_buf_bar clk_buf vdd gnd +Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_inv_array_2x1_1 +Xclkbuf clk clk_buf_bar clk_buf vdd gnd pinvbuf_2_4_1 +Xnand3_w_en_bar clk_buf_bar cs we w_en_bar vdd gnd pnand3_1 +Xinv_pre_w_en w_en_bar pre_w_en vdd gnd pinv_6 +Xinv_pre_w_en_bar pre_w_en pre_w_en_bar vdd gnd pinv_7 +Xinv_w_en2 pre_w_en_bar w_en vdd gnd pinv_8 +Xnand2_rbl_in_bar clk_buf_bar cs rbl_in_bar vdd gnd pnand2_1 +Xinv_rbl_in rbl_in_bar rbl_in vdd gnd pinv_6 +Xinv_pre_s_en_bar pre_s_en pre_s_en_bar vdd gnd pinv_7 +Xinv_s_en pre_s_en_bar s_en vdd gnd pinv_8 +Xreplica_bitline rbl_in pre_s_en vdd gnd replica_bitline_rw +.ENDS control_logic_rw + +.SUBCKT pinv_12 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pinv_12 + +.SUBCKT dff_inv_4 D Q Qb clk vdd gnd +Xdff_inv_dff D Q clk vdd gnd dff +Xdff_inv_inv1 Q Qb vdd gnd pinv_12 +.ENDS dff_inv_4 + +.SUBCKT dff_inv_array_1x1_2 din_0 dout_0 dout_bar_0 clk vdd gnd +XXdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_inv_4 +.ENDS dff_inv_array_1x1_2 + +.SUBCKT pnand2_2 A B Z vdd gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand2_2 + +.SUBCKT pnand3_2 A B C Z vdd gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand3_2 + +.SUBCKT pinv_13 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_13 + +.SUBCKT pinv_14 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pinv_14 + +.SUBCKT pinv_15 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +.ENDS pinv_15 + +.SUBCKT pinvbuf_2_4_2 A Zb Z vdd gnd +Xbuf_inv1 A zb_int vdd gnd pinv_13 +Xbuf_inv2 zb_int z_int vdd gnd pinv_14 +Xbuf_inv3 z_int Zb vdd gnd pinv_15 +Xbuf_inv4 zb_int Z vdd gnd pinv_15 +.ENDS pinvbuf_2_4_2 + +.SUBCKT pinv_16 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_16 + +.SUBCKT pinv_17 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +.ENDS pinv_17 + +.SUBCKT pinv_18 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p +Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p +.ENDS pinv_18 + +.SUBCKT control_logic_w csb clk w_en clk_buf_bar clk_buf vdd gnd +Xctrl_dffs csb cs_bar cs clk_buf vdd gnd dff_inv_array_1x1_2 +Xclkbuf clk clk_buf_bar clk_buf vdd gnd pinvbuf_2_4_2 +Xnand3_w_en_bar clk_buf_bar cs w_en_bar vdd gnd pnand2_2 +Xinv_pre_w_en w_en_bar pre_w_en vdd gnd pinv_16 +Xinv_pre_w_en_bar pre_w_en pre_w_en_bar vdd gnd pinv_17 +Xinv_w_en2 pre_w_en_bar w_en vdd gnd pinv_18 +.ENDS control_logic_w + +.SUBCKT pinv_20 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pinv_20 + +.SUBCKT dff_inv_6 D Q Qb clk vdd gnd +Xdff_inv_dff D Q clk vdd gnd dff +Xdff_inv_inv1 Q Qb vdd gnd pinv_20 +.ENDS dff_inv_6 + +.SUBCKT dff_inv_array_1x1_3 din_0 dout_0 dout_bar_0 clk vdd gnd +XXdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_inv_6 +.ENDS dff_inv_array_1x1_3 + +.SUBCKT pnand2_3 A B Z vdd gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand2_3 + +.SUBCKT pnand3_3 A B C Z vdd gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand3_3 + +.SUBCKT pinv_21 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_21 + +.SUBCKT pinv_22 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pinv_22 + +.SUBCKT pinv_23 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +.ENDS pinv_23 + +.SUBCKT pinvbuf_2_4_3 A Zb Z vdd gnd +Xbuf_inv1 A zb_int vdd gnd pinv_21 +Xbuf_inv2 zb_int z_int vdd gnd pinv_22 +Xbuf_inv3 z_int Zb vdd gnd pinv_23 +Xbuf_inv4 zb_int Z vdd gnd pinv_23 +.ENDS pinvbuf_2_4_3 + +.SUBCKT pinv_24 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_24 + +.SUBCKT pinv_25 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.600000000000001u ps=13.600000000000001u as=6.4p ad=6.4p +Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.2u ps=7.2u as=3.2p ad=3.2p +.ENDS pinv_25 + +.SUBCKT pinv_26 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.0u ps=52.0u as=25.6p ad=25.6p +Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.400000000000002u ps=26.400000000000002u as=12.8p ad=12.8p +.ENDS pinv_26 + +.SUBCKT bitcell_array_8x1_2 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 vdd gnd +Xbit_r0_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R +Xbit_r1_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R +Xbit_r2_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R +Xbit_r3_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R +Xbit_r4_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R +Xbit_r5_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R +Xbit_r6_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R +Xbit_r7_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R +.ENDS bitcell_array_8x1_2 + +.SUBCKT pinv_27 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_27 + +.SUBCKT delay_chain_2 in out vdd gnd +Xdinv0 in dout_1 vdd gnd pinv_27 +Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_27 +Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_27 +Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_27 +Xdinv1 dout_1 dout_2 vdd gnd pinv_27 +Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_27 +Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_27 +Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_27 +Xdinv2 dout_2 dout_3 vdd gnd pinv_27 +Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_27 +Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_27 +Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_27 +Xdinv3 dout_3 out vdd gnd pinv_27 +Xdload_3_0 out n_3_0 vdd gnd pinv_27 +Xdload_3_1 out n_3_1 vdd gnd pinv_27 +Xdload_3_2 out n_3_2 vdd gnd pinv_27 +.ENDS delay_chain_2 + +.SUBCKT pinv_28 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_28 + +.SUBCKT replica_bitline_r en out vdd gnd +Xrbl_inv bl0_0 out vdd gnd pinv_28 +Mrbl_access_tx vdd delayed_en bl0_0 vdd p m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +Xdelay_chain en delayed_en vdd gnd delay_chain_2 +Xbitcell bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 delayed_en delayed_en delayed_en vdd gnd replica_pbitcell +Xload bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vdd gnd bitcell_array_8x1_2 +.ENDS replica_bitline_r + +.SUBCKT control_logic_r csb clk s_en clk_buf_bar clk_buf vdd gnd +Xctrl_dffs csb cs_bar cs clk_buf vdd gnd dff_inv_array_1x1_3 +Xclkbuf clk clk_buf_bar clk_buf vdd gnd pinvbuf_2_4_3 +Xnand2_rbl_in_bar clk_buf_bar cs rbl_in_bar vdd gnd pnand2_3 +Xinv_rbl_in rbl_in_bar rbl_in vdd gnd pinv_24 +Xinv_pre_s_en_bar pre_s_en pre_s_en_bar vdd gnd pinv_25 +Xinv_s_en pre_s_en_bar s_en vdd gnd pinv_26 +Xreplica_bitline rbl_in pre_s_en vdd gnd replica_bitline_r +.ENDS control_logic_r + +.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd +XXdff_r0_c0 din_0 dout_0 clk vdd gnd dff +XXdff_r1_c0 din_1 dout_1 clk vdd gnd dff +XXdff_r2_c0 din_2 dout_2 clk vdd gnd dff +XXdff_r3_c0 din_3 dout_3 clk vdd gnd dff +.ENDS row_addr_dff + +.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd +XXdff_r0_c0 din_0 dout_0 clk vdd gnd dff +XXdff_r0_c1 din_1 dout_1 clk vdd gnd dff +.ENDS data_dff + +.SUBCKT bitcell_array_16x2_1 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 wl0_8 wl1_8 wl2_8 wl0_9 wl1_9 wl2_9 wl0_10 wl1_10 wl2_10 wl0_11 wl1_11 wl2_11 wl0_12 wl1_12 wl2_12 wl0_13 wl1_13 wl2_13 wl0_14 wl1_14 wl2_14 wl0_15 wl1_15 wl2_15 vdd gnd +Xbit_r0_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R +Xbit_r1_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R +Xbit_r2_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R +Xbit_r3_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R +Xbit_r4_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R +Xbit_r5_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R +Xbit_r6_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R +Xbit_r7_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R +Xbit_r8_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_8 wl1_8 wl2_8 vdd gnd pbitcell_1RW_1W_1R +Xbit_r9_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_9 wl1_9 wl2_9 vdd gnd pbitcell_1RW_1W_1R +Xbit_r10_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_10 wl1_10 wl2_10 vdd gnd pbitcell_1RW_1W_1R +Xbit_r11_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_11 wl1_11 wl2_11 vdd gnd pbitcell_1RW_1W_1R +Xbit_r12_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_12 wl1_12 wl2_12 vdd gnd pbitcell_1RW_1W_1R +Xbit_r13_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_13 wl1_13 wl2_13 vdd gnd pbitcell_1RW_1W_1R +Xbit_r14_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_14 wl1_14 wl2_14 vdd gnd pbitcell_1RW_1W_1R +Xbit_r15_c0 bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 wl0_15 wl1_15 wl2_15 vdd gnd pbitcell_1RW_1W_1R +Xbit_r0_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_0 wl1_0 wl2_0 vdd gnd pbitcell_1RW_1W_1R +Xbit_r1_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_1 wl1_1 wl2_1 vdd gnd pbitcell_1RW_1W_1R +Xbit_r2_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_2 wl1_2 wl2_2 vdd gnd pbitcell_1RW_1W_1R +Xbit_r3_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_3 wl1_3 wl2_3 vdd gnd pbitcell_1RW_1W_1R +Xbit_r4_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_4 wl1_4 wl2_4 vdd gnd pbitcell_1RW_1W_1R +Xbit_r5_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_5 wl1_5 wl2_5 vdd gnd pbitcell_1RW_1W_1R +Xbit_r6_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_6 wl1_6 wl2_6 vdd gnd pbitcell_1RW_1W_1R +Xbit_r7_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_7 wl1_7 wl2_7 vdd gnd pbitcell_1RW_1W_1R +Xbit_r8_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_8 wl1_8 wl2_8 vdd gnd pbitcell_1RW_1W_1R +Xbit_r9_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_9 wl1_9 wl2_9 vdd gnd pbitcell_1RW_1W_1R +Xbit_r10_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_10 wl1_10 wl2_10 vdd gnd pbitcell_1RW_1W_1R +Xbit_r11_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_11 wl1_11 wl2_11 vdd gnd pbitcell_1RW_1W_1R +Xbit_r12_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_12 wl1_12 wl2_12 vdd gnd pbitcell_1RW_1W_1R +Xbit_r13_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_13 wl1_13 wl2_13 vdd gnd pbitcell_1RW_1W_1R +Xbit_r14_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_14 wl1_14 wl2_14 vdd gnd pbitcell_1RW_1W_1R +Xbit_r15_c1 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_15 wl1_15 wl2_15 vdd gnd pbitcell_1RW_1W_1R +.ENDS bitcell_array_16x2_1 + +* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p + +.SUBCKT precharge_1 bl br en vdd +Mlower_pmos bl en br vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mupper_pmos1 bl en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mupper_pmos2 br en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS precharge_1 + +.SUBCKT precharge_array_1 bl_0 br_0 bl_1 br_1 en vdd +Xpre_column_0 bl_0 br_0 en vdd precharge_1 +Xpre_column_1 bl_1 br_1 en vdd precharge_1 +.ENDS precharge_array_1 + +.SUBCKT precharge_2 bl br en vdd +Mlower_pmos bl en br vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mupper_pmos1 bl en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mupper_pmos2 br en vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS precharge_2 + +.SUBCKT precharge_array_2 bl_0 br_0 bl_1 br_1 en vdd +Xpre_column_0 bl_0 br_0 en vdd precharge_2 +Xpre_column_1 bl_1 br_1 en vdd precharge_2 +.ENDS precharge_array_2 +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS + +.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd +Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp +Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp +.ENDS sense_amp_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd +* SPICE3 file created from write_driver.ext - technology: scmos + +M1000 a_44_708# a_36_700# bl gnd n w=2.4u l=0.4u +M1001 br a_16_500# a_44_708# gnd n w=2.4u l=0.4u +M1002 a_44_708# en gnd gnd n w=2.4u l=0.4u +M1003 gnd a_8_284# a_16_500# gnd n w=0.8u l=0.4u +M1004 a_36_700# a_20_328# gnd gnd n w=0.8u l=0.4u +M1005 vdd a_8_284# a_16_500# vdd p w=1.4u l=0.4u +M1006 a_36_700# a_20_328# vdd vdd p w=1.4u l=0.4u +M1007 vdd en a_20_328# vdd p w=1.4u l=0.4u +M1008 a_20_328# a_64_360# vdd vdd p w=1.4u l=0.4u +M1009 a_48_328# en a_20_328# gnd n w=1.4u l=0.4u +M1010 gnd a_64_360# a_48_328# gnd n w=1.4u l=0.4u +M1011 a_40_228# en a_8_284# gnd n w=1.4u l=0.4u +M1012 gnd din a_40_228# gnd n w=1.4u l=0.4u +M1013 a_64_360# din gnd gnd n w=0.8u l=0.4u +M1014 a_8_284# en vdd vdd p w=1.4u l=0.4u +M1015 vdd din a_8_284# vdd p w=1.4u l=0.4u +M1016 a_64_360# din vdd vdd p w=1.4u l=0.4u + +.ENDS + +.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd +XXwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver +XXwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver +.ENDS write_driver_array + +.SUBCKT pinv_29 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_29 + +.SUBCKT pnand2_4 A B Z vdd gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand2_4 + +.SUBCKT pnand3_4 A B C Z vdd gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand3_4 + +.SUBCKT pinv_30 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_30 + +.SUBCKT pnand2_5 A B Z vdd gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand2_5 + +.SUBCKT pre2x4 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd +XXpre_inv_0 in_0 inbar_0 vdd gnd pinv_30 +XXpre_inv_1 in_1 inbar_1 vdd gnd pinv_30 +XXpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_30 +XXpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_30 +XXpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_30 +XXpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_30 +XXpre2x4_nand_0 inbar_0 inbar_1 Z_0 vdd gnd pnand2_5 +XXpre2x4_nand_1 in_0 inbar_1 Z_1 vdd gnd pnand2_5 +XXpre2x4_nand_2 inbar_0 in_1 Z_2 vdd gnd pnand2_5 +XXpre2x4_nand_3 in_0 in_1 Z_3 vdd gnd pnand2_5 +.ENDS pre2x4 + +.SUBCKT pinv_31 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_31 + +.SUBCKT pnand3_5 A B C Z vdd gnd +Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand3_5 + +.SUBCKT pre3x8 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd +XXpre_inv_0 in_0 inbar_0 vdd gnd pinv_31 +XXpre_inv_1 in_1 inbar_1 vdd gnd pinv_31 +XXpre_inv_2 in_2 inbar_2 vdd gnd pinv_31 +XXpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_31 +XXpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_31 +XXpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_31 +XXpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_31 +XXpre_nand_inv_4 Z_4 out_4 vdd gnd pinv_31 +XXpre_nand_inv_5 Z_5 out_5 vdd gnd pinv_31 +XXpre_nand_inv_6 Z_6 out_6 vdd gnd pinv_31 +XXpre_nand_inv_7 Z_7 out_7 vdd gnd pinv_31 +XXpre3x8_nand_0 inbar_0 inbar_1 inbar_2 Z_0 vdd gnd pnand3_5 +XXpre3x8_nand_1 in_0 inbar_1 inbar_2 Z_1 vdd gnd pnand3_5 +XXpre3x8_nand_2 inbar_0 in_1 inbar_2 Z_2 vdd gnd pnand3_5 +XXpre3x8_nand_3 in_0 in_1 inbar_2 Z_3 vdd gnd pnand3_5 +XXpre3x8_nand_4 inbar_0 inbar_1 in_2 Z_4 vdd gnd pnand3_5 +XXpre3x8_nand_5 in_0 inbar_1 in_2 Z_5 vdd gnd pnand3_5 +XXpre3x8_nand_6 inbar_0 in_1 in_2 Z_6 vdd gnd pnand3_5 +XXpre3x8_nand_7 in_0 in_1 in_2 Z_7 vdd gnd pnand3_5 +.ENDS pre3x8 + +.SUBCKT hierarchical_decoder_16rows addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd +Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd pre2x4 +Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd pre2x4 +XDEC_NAND_0 out_0 out_4 Z_0 vdd gnd pnand2_4 +XDEC_NAND_1 out_0 out_5 Z_1 vdd gnd pnand2_4 +XDEC_NAND_2 out_0 out_6 Z_2 vdd gnd pnand2_4 +XDEC_NAND_3 out_0 out_7 Z_3 vdd gnd pnand2_4 +XDEC_NAND_4 out_1 out_4 Z_4 vdd gnd pnand2_4 +XDEC_NAND_5 out_1 out_5 Z_5 vdd gnd pnand2_4 +XDEC_NAND_6 out_1 out_6 Z_6 vdd gnd pnand2_4 +XDEC_NAND_7 out_1 out_7 Z_7 vdd gnd pnand2_4 +XDEC_NAND_8 out_2 out_4 Z_8 vdd gnd pnand2_4 +XDEC_NAND_9 out_2 out_5 Z_9 vdd gnd pnand2_4 +XDEC_NAND_10 out_2 out_6 Z_10 vdd gnd pnand2_4 +XDEC_NAND_11 out_2 out_7 Z_11 vdd gnd pnand2_4 +XDEC_NAND_12 out_3 out_4 Z_12 vdd gnd pnand2_4 +XDEC_NAND_13 out_3 out_5 Z_13 vdd gnd pnand2_4 +XDEC_NAND_14 out_3 out_6 Z_14 vdd gnd pnand2_4 +XDEC_NAND_15 out_3 out_7 Z_15 vdd gnd pnand2_4 +XDEC_INV_0 Z_0 decode_0 vdd gnd pinv_29 +XDEC_INV_1 Z_1 decode_1 vdd gnd pinv_29 +XDEC_INV_2 Z_2 decode_2 vdd gnd pinv_29 +XDEC_INV_3 Z_3 decode_3 vdd gnd pinv_29 +XDEC_INV_4 Z_4 decode_4 vdd gnd pinv_29 +XDEC_INV_5 Z_5 decode_5 vdd gnd pinv_29 +XDEC_INV_6 Z_6 decode_6 vdd gnd pinv_29 +XDEC_INV_7 Z_7 decode_7 vdd gnd pinv_29 +XDEC_INV_8 Z_8 decode_8 vdd gnd pinv_29 +XDEC_INV_9 Z_9 decode_9 vdd gnd pinv_29 +XDEC_INV_10 Z_10 decode_10 vdd gnd pinv_29 +XDEC_INV_11 Z_11 decode_11 vdd gnd pinv_29 +XDEC_INV_12 Z_12 decode_12 vdd gnd pinv_29 +XDEC_INV_13 Z_13 decode_13 vdd gnd pinv_29 +XDEC_INV_14 Z_14 decode_14 vdd gnd pinv_29 +XDEC_INV_15 Z_15 decode_15 vdd gnd pinv_29 +.ENDS hierarchical_decoder_16rows + +.SUBCKT pinv_32 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_32 + +.SUBCKT pinv_33 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_33 + +.SUBCKT pnand2_6 A B Z vdd gnd +Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +.ENDS pnand2_6 + +.SUBCKT wordline_driver in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd +Xwl_driver_inv_en0 en en_bar_0 vdd gnd pinv_33 +Xwl_driver_nand0 en_bar_0 in_0 wl_bar_0 vdd gnd pnand2_6 +Xwl_driver_inv0 wl_bar_0 wl_0 vdd gnd pinv_32 +Xwl_driver_inv_en1 en en_bar_1 vdd gnd pinv_33 +Xwl_driver_nand1 en_bar_1 in_1 wl_bar_1 vdd gnd pnand2_6 +Xwl_driver_inv1 wl_bar_1 wl_1 vdd gnd pinv_32 +Xwl_driver_inv_en2 en en_bar_2 vdd gnd pinv_33 +Xwl_driver_nand2 en_bar_2 in_2 wl_bar_2 vdd gnd pnand2_6 +Xwl_driver_inv2 wl_bar_2 wl_2 vdd gnd pinv_32 +Xwl_driver_inv_en3 en en_bar_3 vdd gnd pinv_33 +Xwl_driver_nand3 en_bar_3 in_3 wl_bar_3 vdd gnd pnand2_6 +Xwl_driver_inv3 wl_bar_3 wl_3 vdd gnd pinv_32 +Xwl_driver_inv_en4 en en_bar_4 vdd gnd pinv_33 +Xwl_driver_nand4 en_bar_4 in_4 wl_bar_4 vdd gnd pnand2_6 +Xwl_driver_inv4 wl_bar_4 wl_4 vdd gnd pinv_32 +Xwl_driver_inv_en5 en en_bar_5 vdd gnd pinv_33 +Xwl_driver_nand5 en_bar_5 in_5 wl_bar_5 vdd gnd pnand2_6 +Xwl_driver_inv5 wl_bar_5 wl_5 vdd gnd pinv_32 +Xwl_driver_inv_en6 en en_bar_6 vdd gnd pinv_33 +Xwl_driver_nand6 en_bar_6 in_6 wl_bar_6 vdd gnd pnand2_6 +Xwl_driver_inv6 wl_bar_6 wl_6 vdd gnd pinv_32 +Xwl_driver_inv_en7 en en_bar_7 vdd gnd pinv_33 +Xwl_driver_nand7 en_bar_7 in_7 wl_bar_7 vdd gnd pnand2_6 +Xwl_driver_inv7 wl_bar_7 wl_7 vdd gnd pinv_32 +Xwl_driver_inv_en8 en en_bar_8 vdd gnd pinv_33 +Xwl_driver_nand8 en_bar_8 in_8 wl_bar_8 vdd gnd pnand2_6 +Xwl_driver_inv8 wl_bar_8 wl_8 vdd gnd pinv_32 +Xwl_driver_inv_en9 en en_bar_9 vdd gnd pinv_33 +Xwl_driver_nand9 en_bar_9 in_9 wl_bar_9 vdd gnd pnand2_6 +Xwl_driver_inv9 wl_bar_9 wl_9 vdd gnd pinv_32 +Xwl_driver_inv_en10 en en_bar_10 vdd gnd pinv_33 +Xwl_driver_nand10 en_bar_10 in_10 wl_bar_10 vdd gnd pnand2_6 +Xwl_driver_inv10 wl_bar_10 wl_10 vdd gnd pinv_32 +Xwl_driver_inv_en11 en en_bar_11 vdd gnd pinv_33 +Xwl_driver_nand11 en_bar_11 in_11 wl_bar_11 vdd gnd pnand2_6 +Xwl_driver_inv11 wl_bar_11 wl_11 vdd gnd pinv_32 +Xwl_driver_inv_en12 en en_bar_12 vdd gnd pinv_33 +Xwl_driver_nand12 en_bar_12 in_12 wl_bar_12 vdd gnd pnand2_6 +Xwl_driver_inv12 wl_bar_12 wl_12 vdd gnd pinv_32 +Xwl_driver_inv_en13 en en_bar_13 vdd gnd pinv_33 +Xwl_driver_nand13 en_bar_13 in_13 wl_bar_13 vdd gnd pnand2_6 +Xwl_driver_inv13 wl_bar_13 wl_13 vdd gnd pinv_32 +Xwl_driver_inv_en14 en en_bar_14 vdd gnd pinv_33 +Xwl_driver_nand14 en_bar_14 in_14 wl_bar_14 vdd gnd pnand2_6 +Xwl_driver_inv14 wl_bar_14 wl_14 vdd gnd pinv_32 +Xwl_driver_inv_en15 en en_bar_15 vdd gnd pinv_33 +Xwl_driver_nand15 en_bar_15 in_15 wl_bar_15 vdd gnd pnand2_6 +Xwl_driver_inv15 wl_bar_15 wl_15 vdd gnd pinv_32 +.ENDS wordline_driver + +.SUBCKT pinv_34 A Z vdd gnd +Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.0u ps=4.0u as=1.6p ad=1.6p +Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.4000000000000004u ps=2.4000000000000004u as=0.8p ad=0.8p +.ENDS pinv_34 + +.SUBCKT bank dout0_0 dout0_1 dout2_0 dout2_1 din0_0 din0_1 din1_0 din1_1 addr0_0 addr0_1 addr0_2 addr0_3 addr1_0 addr1_1 addr1_2 addr1_3 addr2_0 addr2_1 addr2_2 addr2_3 s_en0 s_en2 w_en0 w_en1 clk_buf_bar0 clk_buf0 clk_buf_bar1 clk_buf1 clk_buf_bar2 clk_buf2 vdd gnd +Xbitcell_array bl0_0 br0_0 bl1_0 br1_0 bl2_0 br2_0 bl0_1 br0_1 bl1_1 br1_1 bl2_1 br2_1 wl0_0 wl1_0 wl2_0 wl0_1 wl1_1 wl2_1 wl0_2 wl1_2 wl2_2 wl0_3 wl1_3 wl2_3 wl0_4 wl1_4 wl2_4 wl0_5 wl1_5 wl2_5 wl0_6 wl1_6 wl2_6 wl0_7 wl1_7 wl2_7 wl0_8 wl1_8 wl2_8 wl0_9 wl1_9 wl2_9 wl0_10 wl1_10 wl2_10 wl0_11 wl1_11 wl2_11 wl0_12 wl1_12 wl2_12 wl0_13 wl1_13 wl2_13 wl0_14 wl1_14 wl2_14 wl0_15 wl1_15 wl2_15 vdd gnd bitcell_array_16x2_1 +Xprecharge_array0 bl0_0 br0_0 bl0_1 br0_1 clk_buf_bar0 vdd precharge_array_1 +Xprecharge_array2 bl2_0 br2_0 bl2_1 br2_1 clk_buf_bar2 vdd precharge_array_2 +Xsense_amp_array0 dout0_0 bl0_0 br0_0 dout0_1 bl0_1 br0_1 s_en0 vdd gnd sense_amp_array +Xsense_amp_array2 dout2_0 bl2_0 br2_0 dout2_1 bl2_1 br2_1 s_en2 vdd gnd sense_amp_array +Xwrite_driver_array0 din0_0 din0_1 bl0_0 br0_0 bl0_1 br0_1 w_en0 vdd gnd write_driver_array +Xwrite_driver_array1 din1_0 din1_1 bl1_0 br1_0 bl1_1 br1_1 w_en1 vdd gnd write_driver_array +Xrow_decoder0 addr0_0 addr0_1 addr0_2 addr0_3 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 vdd gnd hierarchical_decoder_16rows +Xrow_decoder1 addr1_0 addr1_1 addr1_2 addr1_3 dec_out1_0 dec_out1_1 dec_out1_2 dec_out1_3 dec_out1_4 dec_out1_5 dec_out1_6 dec_out1_7 dec_out1_8 dec_out1_9 dec_out1_10 dec_out1_11 dec_out1_12 dec_out1_13 dec_out1_14 dec_out1_15 vdd gnd hierarchical_decoder_16rows +Xrow_decoder2 addr2_0 addr2_1 addr2_2 addr2_3 dec_out2_0 dec_out2_1 dec_out2_2 dec_out2_3 dec_out2_4 dec_out2_5 dec_out2_6 dec_out2_7 dec_out2_8 dec_out2_9 dec_out2_10 dec_out2_11 dec_out2_12 dec_out2_13 dec_out2_14 dec_out2_15 vdd gnd hierarchical_decoder_16rows +Xwordline_driver0 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 clk_buf0 vdd gnd wordline_driver +Xwordline_driver1 dec_out1_0 dec_out1_1 dec_out1_2 dec_out1_3 dec_out1_4 dec_out1_5 dec_out1_6 dec_out1_7 dec_out1_8 dec_out1_9 dec_out1_10 dec_out1_11 dec_out1_12 dec_out1_13 dec_out1_14 dec_out1_15 wl1_0 wl1_1 wl1_2 wl1_3 wl1_4 wl1_5 wl1_6 wl1_7 wl1_8 wl1_9 wl1_10 wl1_11 wl1_12 wl1_13 wl1_14 wl1_15 clk_buf1 vdd gnd wordline_driver +Xwordline_driver2 dec_out2_0 dec_out2_1 dec_out2_2 dec_out2_3 dec_out2_4 dec_out2_5 dec_out2_6 dec_out2_7 dec_out2_8 dec_out2_9 dec_out2_10 dec_out2_11 dec_out2_12 dec_out2_13 dec_out2_14 dec_out2_15 wl2_0 wl2_1 wl2_2 wl2_3 wl2_4 wl2_5 wl2_6 wl2_7 wl2_8 wl2_9 wl2_10 wl2_11 wl2_12 wl2_13 wl2_14 wl2_15 clk_buf2 vdd gnd wordline_driver +.ENDS bank + +.SUBCKT sram_2_16_scn4m_subm DIN0[0] DIN0[1] DIN1[0] DIN1[1] ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] ADDR1[0] ADDR1[1] ADDR1[2] ADDR1[3] ADDR2[0] ADDR2[1] ADDR2[2] ADDR2[3] csb0 csb1 csb2 web0 clk0 clk1 clk2 DOUT0[0] DOUT0[1] DOUT2[0] DOUT2[1] vdd gnd +Xbank0 DOUT0[0] DOUT0[1] DOUT2[0] DOUT2[1] BANK_DIN0[0] BANK_DIN0[1] BANK_DIN1[0] BANK_DIN1[1] A0[0] A0[1] A0[2] A0[3] A1[0] A1[1] A1[2] A1[3] A2[0] A2[1] A2[2] A2[3] s_en0 s_en2 w_en0 w_en1 clk_buf_bar0 clk_buf0 clk_buf_bar1 clk_buf1 clk_buf_bar2 clk_buf2 vdd gnd bank +Xcontrol0 csb0 web0 clk0 s_en0 w_en0 clk_buf_bar0 clk_buf0 vdd gnd control_logic_rw +Xcontrol1 csb1 clk1 w_en1 clk_buf_bar1 clk_buf1 vdd gnd control_logic_w +Xcontrol2 csb2 clk2 s_en2 clk_buf_bar2 clk_buf2 vdd gnd control_logic_r +Xrow_address0 ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] A0[0] A0[1] A0[2] A0[3] clk_buf0 vdd gnd row_addr_dff +Xrow_address1 ADDR1[0] ADDR1[1] ADDR1[2] ADDR1[3] A1[0] A1[1] A1[2] A1[3] clk_buf1 vdd gnd row_addr_dff +Xrow_address2 ADDR2[0] ADDR2[1] ADDR2[2] ADDR2[3] A2[0] A2[1] A2[2] A2[3] clk_buf2 vdd gnd row_addr_dff +Xdata_dff0 DIN0[0] DIN0[1] BANK_DIN0[0] BANK_DIN0[1] clk_buf0 vdd gnd data_dff +Xdata_dff1 DIN1[0] DIN1[1] BANK_DIN1[0] BANK_DIN1[1] clk_buf1 vdd gnd data_dff +.ENDS sram_2_16_scn4m_subm diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.v b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.v new file mode 100644 index 00000000..779fd6e9 --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm.v @@ -0,0 +1,47 @@ +// OpenRAM SRAM model +// Words: 16 +// Word size: 2 + +module sram_2_16_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk); + + parameter DATA_WIDTH = 2 ; + parameter ADDR_WIDTH = 4 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + parameter DELAY = 3 ; + + inout [DATA_WIDTH-1:0] DATA; + input [ADDR_WIDTH-1:0] ADDR; + input CSb; // active low chip select + input WEb; // active low write control + input OEb; // active output enable + input clk; // clock + + reg [DATA_WIDTH-1:0] data_out ; + reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Tri-State Buffer control + // output : When WEb = 1, oeb = 0, csb = 0 + assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz; + + // Memory Write Block + // Write Operation : When WEb = 0, CSb = 0 + always @ (posedge clk) + begin : MEM_WRITE + if ( !CSb && !WEb ) begin + mem[ADDR] = DATA; + $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA); + end + end + + + // Memory Read Block + // Read Operation : When WEb = 1, CSb = 0 + always @ (posedge clk) + begin : MEM_READ + if (!CSb && WEb) begin + data_out <= #(DELAY) mem[ADDR]; + $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]); + end + end + +endmodule diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_3p3V_25C.lib b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_3p3V_25C.lib new file mode 100644 index 00000000..a516aa25 --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_3p3V_25C.lib @@ -0,0 +1,321 @@ +library (sram_2_16_scn4m_subm_TT_3p3V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 3.3 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 69426.85; + + leakage_power () { + when : "CSb0"; + value : 0.000179; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk0; + } + pin(DIN0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + cell_fall(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk0 & !WEb0"; + rise_power(scalar){ + values("2.46222038320038"); + } + fall_power(scalar){ + values("2.46222038320038"); + } + } + internal_power(){ + when : "!CSb0 & !clk0 & WEb0"; + rise_power(scalar){ + values("2.46222038320038"); + } + fall_power(scalar){ + values("2.46222038320038"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + + } +} diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5V_25C.lib b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5V_25C.lib new file mode 100644 index 00000000..18a74796 --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5V_25C.lib @@ -0,0 +1,321 @@ +library (sram_2_16_scn4m_subm_TT_5V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 68347.21; + + leakage_power () { + when : "CSb0"; + value : 0.000179; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk0; + } + pin(DIN0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + cell_fall(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk0 & !WEb0"; + rise_power(scalar){ + values("2.46222038320038"); + } + fall_power(scalar){ + values("2.46222038320038"); + } + } + internal_power(){ + when : "!CSb0 & !clk0 & WEb0"; + rise_power(scalar){ + values("2.46222038320038"); + } + fall_power(scalar){ + values("2.46222038320038"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + + } +} diff --git a/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib new file mode 100644 index 00000000..4ce58d08 --- /dev/null +++ b/compiler/datasheet/server_scripts/files/temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib @@ -0,0 +1,625 @@ +library (sram_2_16_scn4m_subm_TT_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 0; + + leakage_power () { + when : "CSb0 & CSb1 & CSb2"; + value : 0.000436; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk0; + } + pin(DIN0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079"); + } + cell_fall(CELL_TABLE) { + values("0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079"); + } + rise_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk0 & !WEb0"; + rise_power(scalar){ + values("15.41143495605"); + } + fall_power(scalar){ + values("15.41143495605"); + } + } + internal_power(){ + when : "!CSb0 & !clk0 & WEb0"; + rise_power(scalar){ + values("15.41143495605"); + } + fall_power(scalar){ + values("15.41143495605"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + + bus(DIN1){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR1; + clocked_on : clk1; + } + pin(DIN1[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(ADDR1){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR1[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb1){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk1){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb1 & clk1"; + rise_power(scalar){ + values("15.41143495605"); + } + fall_power(scalar){ + values("15.41143495605"); + } + } + internal_power(){ + when : "CSb1"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk1; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk1; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + + bus(DOUT2){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR2; + } + pin(DOUT2[1:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk2"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079"); + } + cell_fall(CELL_TABLE) { + values("0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079",\ + "0.079, 0.079, 0.079"); + } + rise_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + bus(ADDR2){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR2[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk2"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk2"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb2){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk2"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk2"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk2){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb2 & !clk2"; + rise_power(scalar){ + values("15.41143495605"); + } + fall_power(scalar){ + values("15.41143495605"); + } + } + internal_power(){ + when : "CSb2"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk2; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk2; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + + } +} diff --git a/compiler/datasheet/server_scripts/files/testfile.asdf b/compiler/datasheet/server_scripts/files/testfile.asdf new file mode 100644 index 00000000..e69de29b diff --git a/compiler/datasheet/server_scripts/templates/index.html b/compiler/datasheet/server_scripts/templates/index.html new file mode 100644 index 00000000..ae448a80 --- /dev/null +++ b/compiler/datasheet/server_scripts/templates/index.html @@ -0,0 +1,5 @@ +
    + {% for file in files %} +
  • {{ file }}
    • + {% endfor %} +
From a56e3f609b67ac242d5709462d54aa83d143a72b Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 28 Nov 2018 09:39:58 -0800 Subject: [PATCH 39/78] removed debug print statements --- compiler/datasheet/server_scripts/filelist.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/datasheet/server_scripts/filelist.py b/compiler/datasheet/server_scripts/filelist.py index 2196a419..01f32682 100644 --- a/compiler/datasheet/server_scripts/filelist.py +++ b/compiler/datasheet/server_scripts/filelist.py @@ -12,7 +12,7 @@ class filelist: for file in files: self.list.append(root + '/' + file) out_file.write('{}/{}\n'.format(root,file)) - print('{}/{}'.format(root,file)) + #print('{}/{}'.format(root,file)) From 44638cb885e3014ce8ea7069ec717e0caa38aed2 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 28 Nov 2018 16:48:24 -0800 Subject: [PATCH 40/78] jinja2 file browser working --- compiler/datasheet/server_scripts/__init__.py | 11 ++--- compiler/datasheet/server_scripts/filelist.py | 1 + .../files/temp/testfolder/file1 | 0 .../files/temp/testfolder/file2 | 0 .../files/temp/testfolder2/file3 | 0 .../files/temp/testfolder2/file4 | 0 .../server_scripts/templates/index.html | 42 +++++++++++++++++-- 7 files changed, 42 insertions(+), 12 deletions(-) create mode 100644 compiler/datasheet/server_scripts/files/temp/testfolder/file1 create mode 100644 compiler/datasheet/server_scripts/files/temp/testfolder/file2 create mode 100644 compiler/datasheet/server_scripts/files/temp/testfolder2/file3 create mode 100644 compiler/datasheet/server_scripts/files/temp/testfolder2/file4 diff --git a/compiler/datasheet/server_scripts/__init__.py b/compiler/datasheet/server_scripts/__init__.py index f702e604..f670aeaf 100644 --- a/compiler/datasheet/server_scripts/__init__.py +++ b/compiler/datasheet/server_scripts/__init__.py @@ -7,23 +7,18 @@ from filelist import * filedir = './files' file_data = './filelist.info' -def render_without_request(template_name, **template_vars): - env = jinja2.Environment( - loader = jinja2.PackageLoader('server_scripts','templates') - ) - template = env.get_template(template_name) - return template.render(**template_vars) app = Flask('server_scripts') + if __name__ == '__main__': files = filelist() files.update_filelist(filedir,file_data) - f = open('./output/index.html','w') + f = open('./index.html','w') with app.app_context(): - f.write(render_template('index.html', files=files.list)) + f.write(render_template('index.html', filedir = filedir , os = os)) diff --git a/compiler/datasheet/server_scripts/filelist.py b/compiler/datasheet/server_scripts/filelist.py index 01f32682..ec2eee88 100644 --- a/compiler/datasheet/server_scripts/filelist.py +++ b/compiler/datasheet/server_scripts/filelist.py @@ -16,3 +16,4 @@ class filelist: + diff --git a/compiler/datasheet/server_scripts/files/temp/testfolder/file1 b/compiler/datasheet/server_scripts/files/temp/testfolder/file1 new file mode 100644 index 00000000..e69de29b diff --git a/compiler/datasheet/server_scripts/files/temp/testfolder/file2 b/compiler/datasheet/server_scripts/files/temp/testfolder/file2 new file mode 100644 index 00000000..e69de29b diff --git a/compiler/datasheet/server_scripts/files/temp/testfolder2/file3 b/compiler/datasheet/server_scripts/files/temp/testfolder2/file3 new file mode 100644 index 00000000..e69de29b diff --git a/compiler/datasheet/server_scripts/files/temp/testfolder2/file4 b/compiler/datasheet/server_scripts/files/temp/testfolder2/file4 new file mode 100644 index 00000000..e69de29b diff --git a/compiler/datasheet/server_scripts/templates/index.html b/compiler/datasheet/server_scripts/templates/index.html index ae448a80..a2e3ec13 100644 --- a/compiler/datasheet/server_scripts/templates/index.html +++ b/compiler/datasheet/server_scripts/templates/index.html @@ -1,5 +1,39 @@ -
    - {% for file in files %} -
  • {{ file }}
    • - {% endfor %} + +
+ + + + {% for root, dir, files in os.walk(filedir) %} + + + +
+ {% for f in files %} + +
+

file information

+
+ {% endfor %} +
+ + + {% endfor %} + + + From 79c4b3c4cd83ea79dffe19d7a8765b4a8a3af5a1 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 28 Nov 2018 16:56:24 -0800 Subject: [PATCH 41/78] added files links --- .../server_scripts/templates/index.html | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/compiler/datasheet/server_scripts/templates/index.html b/compiler/datasheet/server_scripts/templates/index.html index a2e3ec13..66720d67 100644 --- a/compiler/datasheet/server_scripts/templates/index.html +++ b/compiler/datasheet/server_scripts/templates/index.html @@ -2,24 +2,27 @@ + +
- {% for root, dir, files in os.walk(filedir) %} + {% for root, dir, files in os.walk(filedir) %} - -
- {% for f in files %} - +
-

file information

-
+ {% for f in files %} + +
+ link +
+ {% endfor %} +
+ + {% endfor %}
- {% endfor %} - -