From 493c9125f1aaa3c7050ac0537bc0bdca0227ee6f Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Fri, 6 Nov 2020 11:09:50 -0800
Subject: [PATCH] Read different modules overrides for different num ports

---
 compiler/globals.py                | 2 +-
 compiler/pgates/column_mux.py      | 3 ++-
 compiler/pgates/pinv_dec.py        | 2 +-
 compiler/pgates/precharge.py       | 2 +-
 compiler/pgates/pwrite_driver.py   | 6 +++---
 compiler/pgates/wordline_driver.py | 2 +-
 compiler/sram_factory.py           | 6 ++++++
 7 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/compiler/globals.py b/compiler/globals.py
index d93ac776..23bb5bfb 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -314,7 +314,7 @@ def read_config(config_file, is_unit_test=True):
     try:
         config = importlib.import_module(module_name)
     except:
-        debug.error("Unable to read configuration file: {0}".format(config_file),2)
+        debug.error("Unable to read configuration file: {0}".format(config_file), 2)
 
     OPTS.overridden = {}
     for k, v in config.__dict__.items():
diff --git a/compiler/pgates/column_mux.py b/compiler/pgates/column_mux.py
index 844fd00a..cf08aa71 100644
--- a/compiler/pgates/column_mux.py
+++ b/compiler/pgates/column_mux.py
@@ -11,6 +11,7 @@ from tech import drc, layer
 from vector import vector
 from sram_factory import factory
 from tech import cell_properties as cell_props
+from globals import OPTS
 
 
 class column_mux(pgate.pgate):
@@ -64,7 +65,7 @@ class column_mux(pgate.pgate):
         self.add_pn_wells()
 
     def add_ptx(self):
-        self.bitcell = factory.create(module_type="bitcell")
+        self.bitcell = factory.create(module_type=OPTS.bitcell)
 
         # Adds nmos_lower,nmos_upper to the module
         self.ptx_width = self.tx_size * drc("minwidth_tx")
diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py
index 1a078a3c..b355b28f 100644
--- a/compiler/pgates/pinv_dec.py
+++ b/compiler/pgates/pinv_dec.py
@@ -27,7 +27,7 @@ class pinv_dec(pinv.pinv):
                    "creating pinv_dec structure {0} with size of {1}".format(name,
                                                                              size))
         if not height:
-            b = factory.create(module_type="bitcell")
+            b = factory.create(module_type=OPTS.bitcell)
             self.cell_height = b.height
         else:
             self.cell_height = height
diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index d3599902..545b6ae8 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -26,7 +26,7 @@ class precharge(design.design):
         debug.info(2, "creating precharge cell {0}".format(name))
         super().__init__(name)
 
-        self.bitcell = factory.create(module_type="bitcell")
+        self.bitcell = factory.create(module_type=OPTS.bitcell)
         self.beta = parameter["beta"]
         self.ptx_width = self.beta * parameter["min_tx_size"]
         self.ptx_mults = 1
diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py
index 26c49d2f..674d8283 100644
--- a/compiler/pgates/pwrite_driver.py
+++ b/compiler/pgates/pwrite_driver.py
@@ -25,15 +25,15 @@ class pwrite_driver(design.design):
         super().__init__(name)
         self.size = size
         self.beta = parameter["beta"]
-        self.pmos_width = self.beta*self.size*parameter["min_tx_size"]
-        self.nmos_width = self.size*parameter["min_tx_size"]
+        self.pmos_width = self.beta * self.size * parameter["min_tx_size"]
+        self.nmos_width = self.size * parameter["min_tx_size"]
 
         # The tech M2 pitch is based on old via orientations
         self.m2_pitch = self.m2_space + self.m2_width
 
         # Width is matched to the bitcell,
         # Height will be variable
-        self.bitcell = factory.create(module_type="bitcell")
+        self.bitcell = factory.create(module_type=OPTS.bitcell)
         self.width = self.bitcell.width
 
         # Creates the netlist and layout
diff --git a/compiler/pgates/wordline_driver.py b/compiler/pgates/wordline_driver.py
index b5e8478d..4c66d0b1 100644
--- a/compiler/pgates/wordline_driver.py
+++ b/compiler/pgates/wordline_driver.py
@@ -25,7 +25,7 @@ class wordline_driver(design.design):
         super().__init__(name)
 
         if height is None:
-            b = factory.create(module_type="bitcell")
+            b = factory.create(module_type=OPTS.bitcell)
             self.height = b.height
         else:
             self.height = height
diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py
index 3680e5d5..dd13b7a0 100644
--- a/compiler/sram_factory.py
+++ b/compiler/sram_factory.py
@@ -7,6 +7,7 @@
 #
 from globals import OPTS
 
+
 class sram_factory:
     """
     This is a factory pattern to create modules for usage in an SRAM.
@@ -39,6 +40,11 @@ class sram_factory:
         try:
             from tech import tech_modules
             real_module_type = tech_modules[module_type]
+            # If we are given a list of modules, it is indexed by number of ports starting from 1
+            if type(real_module_type) is list:
+                # For now we will just index by the number of ports (except can't have 0 ports)
+                num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
+                real_module_type = real_module_type[num_ports - 1]
             overridden = tech_modules.is_overridden(module_type)
         except ImportError:
             # If they didn't define these, then don't use the option types.