diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py
index 9f896955..68276fab 100644
--- a/compiler/modules/write_mask_and_array.py
+++ b/compiler/modules/write_mask_and_array.py
@@ -108,8 +108,6 @@ class write_mask_and_array(design.design):
 
 
     def add_layout_pins(self):
-        self.nand2 = factory.create(module_type="pnand2")
-        supply_pin=self.nand2.get_pin("vdd")
         for i in range(self.num_wmasks):
             wmask_in_pin = self.and2_insts[i].get_pin("A")
             self.add_layout_pin(text="wmask_in_{0}".format(i),
@@ -117,6 +115,8 @@ class write_mask_and_array(design.design):
                                 offset=wmask_in_pin.ll(),
                                 width=wmask_in_pin.width(),
                                 height=wmask_in_pin.height())
+            self.add_via_center(layers=("metal1", "via1", "metal2"),
+                                offset=wmask_in_pin.center())
 
             en_pin = self.and2_insts[i].get_pin("B")
             # Add the M1->M2 stack
@@ -143,7 +143,7 @@ class write_mask_and_array(design.design):
             for n in ["vdd", "gnd"]:
                 pin_list = self.and2_insts[i].get_pins(n)
                 for pin in pin_list:
-                    pin_pos = pin.lc()
+                    pin_pos = vector(pin.lx()-0.75*drc('minwidth_metal1'), pin.cy())
                     # Add the M1->M2 stack
                     self.add_via_center(layers=("metal1", "via1", "metal2"),
                                         offset=pin_pos)
diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index e42970f7..245ec9e9 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -81,12 +81,12 @@ class sram_1bank(sram_base):
             if port in self.write_ports:
                 # Add the write mask flops below the write mask AND array.
                 wmask_pos[port] = vector(self.bank.bank_array_ll.x,
-                                         - max_gap_size - self.dff.height)
+                                         -0.5*max_gap_size - self.dff.height)
                 self.wmask_dff_insts[port].place(wmask_pos[port])
 
                 # Add the data flops below the write mask flops.
                 data_pos[port] = vector(self.bank.bank_array_ll.x,
-                                        -2*max_gap_size - 2*self.dff.height)
+                                        -1.5*max_gap_size - 2*self.dff.height)
                 self.data_dff_insts[port].place(data_pos[port])
             else:
                 wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0)
@@ -355,7 +355,7 @@ class sram_1bank(sram_base):
             if port%2:
                 offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) 
             else:
-                offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)                                
+                offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)
 
 
             dff_names = ["dout_{}".format(x) for x in range(self.word_size)]
@@ -369,10 +369,12 @@ class sram_1bank(sram_base):
             bank_names = ["din{0}_{1}".format(port,x) for x in range(self.word_size)]
             bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
             for x in bank_names:
+                pin_offset = vector(self.bank_inst.get_pin(x).cx(),
+                                self.bank_inst.get_pin(x).by() - 0.75*drc('minwidth_metal1'))
                 self.add_via_center(layers=("metal1", "via1", "metal2"),
-                                    offset=self.bank_inst.get_pin(x).bc())
+                                    offset=pin_offset)
                 self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                    offset=self.bank_inst.get_pin(x).bc())
+                                    offset=pin_offset)
             
             route_map = list(zip(bank_pins, dff_pins))
             self.create_horizontal_channel_route(netlist=route_map,