From 480862c7656efd1bef1501f8e8271593a0f6aaa7 Mon Sep 17 00:00:00 2001
From: samuelkcrow <samuelkcrow@gmail.com>
Date: Fri, 22 Jul 2022 11:24:54 -0700
Subject: [PATCH] remove sys.path.append calls from tests

---
 compiler/tests/16_control_logic_delay_multiport_test.py | 2 +-
 compiler/tests/16_control_logic_delay_r_test.py         | 2 +-
 compiler/tests/16_control_logic_delay_rw_test.py        | 2 +-
 compiler/tests/16_control_logic_delay_w_test.py         | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)
 mode change 100644 => 100755 compiler/tests/16_control_logic_delay_multiport_test.py
 mode change 100644 => 100755 compiler/tests/16_control_logic_delay_r_test.py
 mode change 100644 => 100755 compiler/tests/16_control_logic_delay_rw_test.py
 mode change 100644 => 100755 compiler/tests/16_control_logic_delay_w_test.py

diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py
old mode 100644
new mode 100755
index 448f14d4..7ea40309
--- a/compiler/tests/16_control_logic_delay_multiport_test.py
+++ b/compiler/tests/16_control_logic_delay_multiport_test.py
@@ -13,7 +13,7 @@ Run a regression test on a control_logic_delay
 import unittest
 from testutils import header,openram_test
 import sys, os
-sys.path.append(os.path.join(sys.path[0],".."))
+
 import globals
 from globals import OPTS
 from sram_factory import factory
diff --git a/compiler/tests/16_control_logic_delay_r_test.py b/compiler/tests/16_control_logic_delay_r_test.py
old mode 100644
new mode 100755
index ec1e401b..1a184b39
--- a/compiler/tests/16_control_logic_delay_r_test.py
+++ b/compiler/tests/16_control_logic_delay_r_test.py
@@ -9,7 +9,7 @@
 import unittest
 from testutils import *
 import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
+
 import globals
 from globals import OPTS
 from sram_factory import factory
diff --git a/compiler/tests/16_control_logic_delay_rw_test.py b/compiler/tests/16_control_logic_delay_rw_test.py
old mode 100644
new mode 100755
index cb592b5a..2c2f6cf7
--- a/compiler/tests/16_control_logic_delay_rw_test.py
+++ b/compiler/tests/16_control_logic_delay_rw_test.py
@@ -9,7 +9,7 @@
 import unittest
 from testutils import *
 import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
+
 import globals
 from globals import OPTS
 from sram_factory import factory
diff --git a/compiler/tests/16_control_logic_delay_w_test.py b/compiler/tests/16_control_logic_delay_w_test.py
old mode 100644
new mode 100755
index 748a3f0d..989b190a
--- a/compiler/tests/16_control_logic_delay_w_test.py
+++ b/compiler/tests/16_control_logic_delay_w_test.py
@@ -9,7 +9,7 @@
 import unittest
 from testutils import *
 import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
+
 import globals
 from globals import OPTS
 from sram_factory import factory