diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py
old mode 100644
new mode 100755
index 448f14d4..7ea40309
--- a/compiler/tests/16_control_logic_delay_multiport_test.py
+++ b/compiler/tests/16_control_logic_delay_multiport_test.py
@@ -13,7 +13,7 @@ Run a regression test on a control_logic_delay
 import unittest
 from testutils import header,openram_test
 import sys, os
-sys.path.append(os.path.join(sys.path[0],".."))
+
 import globals
 from globals import OPTS
 from sram_factory import factory
diff --git a/compiler/tests/16_control_logic_delay_r_test.py b/compiler/tests/16_control_logic_delay_r_test.py
old mode 100644
new mode 100755
index ec1e401b..1a184b39
--- a/compiler/tests/16_control_logic_delay_r_test.py
+++ b/compiler/tests/16_control_logic_delay_r_test.py
@@ -9,7 +9,7 @@
 import unittest
 from testutils import *
 import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
+
 import globals
 from globals import OPTS
 from sram_factory import factory
diff --git a/compiler/tests/16_control_logic_delay_rw_test.py b/compiler/tests/16_control_logic_delay_rw_test.py
old mode 100644
new mode 100755
index cb592b5a..2c2f6cf7
--- a/compiler/tests/16_control_logic_delay_rw_test.py
+++ b/compiler/tests/16_control_logic_delay_rw_test.py
@@ -9,7 +9,7 @@
 import unittest
 from testutils import *
 import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
+
 import globals
 from globals import OPTS
 from sram_factory import factory
diff --git a/compiler/tests/16_control_logic_delay_w_test.py b/compiler/tests/16_control_logic_delay_w_test.py
old mode 100644
new mode 100755
index 748a3f0d..989b190a
--- a/compiler/tests/16_control_logic_delay_w_test.py
+++ b/compiler/tests/16_control_logic_delay_w_test.py
@@ -9,7 +9,7 @@
 import unittest
 from testutils import *
 import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
+
 import globals
 from globals import OPTS
 from sram_factory import factory