diff --git a/compiler/tests/18_port_address_16rows_1rw_1r_test.py b/compiler/tests/18_port_address_16rows_1rw_1r_test.py index dce0469f..b021f3e1 100755 --- a/compiler/tests/18_port_address_16rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_16rows_1rw_1r_test.py @@ -27,7 +27,7 @@ class port_address_1rw_1r_test(openram_test): openram.setup_bitcell() debug.info(1, "Port address 16 rows") - a = factory.create("port_address", cols=16, rows=16, port=0) + a = factory.create("port_address", cols=16, rows=16, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_address_16rows_test.py b/compiler/tests/18_port_address_16rows_test.py index 52d32f31..5453e85f 100755 --- a/compiler/tests/18_port_address_16rows_test.py +++ b/compiler/tests/18_port_address_16rows_test.py @@ -21,7 +21,7 @@ class port_address_test(openram_test): openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Port address 16 rows") - a = factory.create("port_address", cols=16, rows=16, port=0) + a = factory.create("port_address", cols=16, rows=16, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_address_256rows_1rw_1r_test.py b/compiler/tests/18_port_address_256rows_1rw_1r_test.py index 28d14b33..c7a5d5b1 100755 --- a/compiler/tests/18_port_address_256rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_256rows_1rw_1r_test.py @@ -27,7 +27,7 @@ class port_address_1rw_1r_test(openram_test): openram.setup_bitcell() debug.info(1, "Port address 256 rows") - a = factory.create("port_address", cols=256, rows=256, port=1) + a = factory.create("port_address", cols=256, rows=256, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_address_512rows_test.py b/compiler/tests/18_port_address_512rows_test.py index 5c1848b0..ff7070c2 100755 --- a/compiler/tests/18_port_address_512rows_test.py +++ b/compiler/tests/18_port_address_512rows_test.py @@ -21,7 +21,7 @@ class port_address_test(openram_test): openram.init_openram(config_file, is_unit_test=True) debug.info(1, "Port address 512 rows") - a = factory.create("port_address", cols=256, rows=512, port=0) + a = factory.create("port_address", cols=256, rows=512, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py index b4b50323..863dc37d 100755 --- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py @@ -34,9 +34,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=16 c.recompute_sizes() debug.info(1, "Sixteen way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py index 66d4c4bf..e46d1107 100755 --- a/compiler/tests/18_port_data_16mux_test.py +++ b/compiler/tests/18_port_data_16mux_test.py @@ -38,7 +38,7 @@ class port_data_test(openram_test): c.words_per_row=16 c.recompute_sizes() debug.info(1, "Sixteen way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py index fc0d9243..a0f88622 100755 --- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py @@ -33,9 +33,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py index 8eb29615..2864baee 100755 --- a/compiler/tests/18_port_data_2mux_test.py +++ b/compiler/tests/18_port_data_2mux_test.py @@ -37,7 +37,7 @@ class port_data_test(openram_test): c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py index ac81e561..a19a9698 100755 --- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py @@ -33,9 +33,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py index c3eae434..42d40335 100755 --- a/compiler/tests/18_port_data_4mux_test.py +++ b/compiler/tests/18_port_data_4mux_test.py @@ -37,7 +37,7 @@ class port_data_test(openram_test): c.words_per_row=4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py index e57d12ef..add22345 100755 --- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py @@ -34,9 +34,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py index a8f82489..700a7b59 100755 --- a/compiler/tests/18_port_data_8mux_test.py +++ b/compiler/tests/18_port_data_8mux_test.py @@ -38,7 +38,7 @@ class port_data_test(openram_test): c.words_per_row=8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py index 8b887d9b..48b2ddee 100755 --- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py @@ -32,9 +32,9 @@ class port_data_1rw_1r_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py index e479de1f..ceeff4cf 100755 --- a/compiler/tests/18_port_data_nomux_test.py +++ b/compiler/tests/18_port_data_nomux_test.py @@ -36,7 +36,7 @@ class port_data_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index 0db34da0..ad05c64c 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -28,14 +28,14 @@ class port_data_spare_cols_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words=32 c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words=64 @@ -43,7 +43,7 @@ class port_data_spare_cols_test(openram_test): c.num_spare_cols=3 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.word_size=2 @@ -52,7 +52,7 @@ class port_data_spare_cols_test(openram_test): c.num_spare_cols=4 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) OPTS.num_rw_ports = 0 @@ -64,27 +64,27 @@ class port_data_spare_cols_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words=32 c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words=64 c.words_per_row=4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.word_size=2 @@ -92,9 +92,9 @@ class port_data_spare_cols_test(openram_test): c.words_per_row=8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index b731a1d0..6aadd417 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -33,28 +33,28 @@ class port_data_wmask_1rw_1r_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 128 c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) OPTS.num_rw_ports = 0 @@ -66,27 +66,27 @@ class port_data_wmask_1rw_1r_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) # c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.word_size = 8 @@ -94,9 +94,9 @@ class port_data_wmask_1rw_1r_test(openram_test): c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index 3db910c1..30565ba8 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -37,28 +37,28 @@ class port_data_wmask_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) c.num_words = 128 c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) OPTS.num_rw_ports = 0 @@ -70,27 +70,27 @@ class port_data_wmask_test(openram_test): c.words_per_row = 1 c.recompute_sizes() debug.info(1, "No column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) # c.num_words = 32 c.words_per_row = 2 c.recompute_sizes() debug.info(1, "Two way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.num_words = 64 c.words_per_row = 4 c.recompute_sizes() debug.info(1, "Four way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) c.word_size = 8 @@ -98,9 +98,9 @@ class port_data_wmask_test(openram_test): c.words_per_row = 8 c.recompute_sizes() debug.info(1, "Eight way column mux") - a = factory.create("port_data", sram_config=c, port=0) + a = factory.create("port_data", sram_config=c, port=0, has_rbl=True) self.local_check(a) - a = factory.create("port_data", sram_config=c, port=1) + a = factory.create("port_data", sram_config=c, port=1, has_rbl=True) self.local_check(a) openram.end_openram()