diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py
index b7bce868..2bc4a0d2 100755
--- a/compiler/tests/05_replica_pbitcell_array_test.py
+++ b/compiler/tests/05_replica_pbitcell_array_test.py
@@ -18,7 +18,6 @@ class replica_bitcell_array_test(openram_test):
     def runTest(self):
         globals.init_openram("config_{0}".format(OPTS.tech_name))
 
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell = "replica_pbitcell"
         OPTS.dummy_bitcell = "dummy_pbitcell"
@@ -30,6 +29,18 @@ class replica_bitcell_array_test(openram_test):
         a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0,1])
         self.local_check(a)
 
+        OPTS.bitcell = "pbitcell"
+        OPTS.replica_bitcell = "replica_pbitcell"
+        OPTS.dummy_bitcell = "dummy_pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing 4x4 array for pbitcell")
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
+        self.local_check(a)
+        
         globals.end_openram()
 
 # run the test from the command line