From 4183638f0354cb7ac909c1d6752b67a137d1191d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 16:05:57 -0700 Subject: [PATCH] Align precharge bitlines with col mux --- compiler/pgates/precharge.py | 12 ++++++------ ...w1r_test.py => 08_precharge_array_1rw_1r_test.py} | 0 2 files changed, 6 insertions(+), 6 deletions(-) rename compiler/tests/{08_precharge_array_1rw1r_test.py => 08_precharge_array_1rw_1r_test.py} (100%) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 8b84a1b8..278fef3d 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -235,11 +235,11 @@ class precharge(design.design): """ Adds both bit-line and bit-line-bar to the module """ - layer_width = drc("minwidth_" + self.bitline_layer) - layer_space = drc("{0}_to_{0}".format(self.bitline_layer)) + layer_pitch = getattr(self, "{}_pitch".format(self.bitline_layer)) + layer_width = getattr(self, "{}_width".format(self.bitline_layer)) - # adds the BL - self.bl_xoffset = layer_space + 0.5 * layer_width + # adds the BL so it aligns with the col mux + self.bl_xoffset = layer_pitch + 0.5 * layer_width top_pos = vector(self.bl_xoffset, self.height) pin_pos = vector(self.bl_xoffset, 0) self.add_path(self.bitline_layer, [top_pos, pin_pos]) @@ -248,8 +248,8 @@ class precharge(design.design): start=pin_pos, end=top_pos) - # adds the BR - self.br_xoffset = self.width - layer_space - 0.5 * layer_width + # adds the BR so it aligns with the col mux + self.br_xoffset = self.width - layer_pitch - 0.5 * layer_width top_pos = vector(self.br_xoffset, self.height) pin_pos = vector(self.br_xoffset, 0) self.add_path(self.bitline_layer, [top_pos, pin_pos]) diff --git a/compiler/tests/08_precharge_array_1rw1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py similarity index 100% rename from compiler/tests/08_precharge_array_1rw1r_test.py rename to compiler/tests/08_precharge_array_1rw_1r_test.py