From 58da8af619689fb2002e2b03dbcd7eae0a859dd1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 31 Jan 2018 10:04:28 -0800 Subject: [PATCH 1/4] Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. --- compiler/bitcell_array.py | 2 +- technology/scn3me_subm/gds_lib/cell_6t.gds | Bin 5724 -> 5596 bytes .../scn3me_subm/gds_lib/replica_cell_6t.gds | Bin 5804 -> 5804 bytes 3 files changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/bitcell_array.py b/compiler/bitcell_array.py index 10bbf78a..30696b7c 100644 --- a/compiler/bitcell_array.py +++ b/compiler/bitcell_array.py @@ -116,7 +116,7 @@ class bitcell_array(design.design): for gnd_pin in gnd_pins: # avoid duplicates by only doing even rows # also skip if it isn't the pin that spans the entire cell down to the bottom - if gnd_pin.layer=="metal2" and col%2 == 0 and gnd_pin.by()==lower_y: + if gnd_pin.layer=="metal2" and gnd_pin.by()==lower_y: self.add_layout_pin(text="gnd", layer="metal2", offset=gnd_pin.ll(), diff --git a/technology/scn3me_subm/gds_lib/cell_6t.gds b/technology/scn3me_subm/gds_lib/cell_6t.gds index 7433d63f961547839c338fcb31eef23376858e9b..e7298ccee60d5f5ed6de698a0e07e62e82453894 100644 GIT binary patch delta 920 zcmbV~u}|Aj5XL`0T-!2~*d_)OMNVWyfD(l!c2iWA2z6xY#FU{zQAQ?4=pWD_@G^8j zRfQNBn8?Dwzz}tg5F?5@R8{`~)UCYw`SBV{WWvkOcc;&H_xbM1cdG$35KJJi5bQxg z0cISprQV~%U}a`px>+|j`i%Yg25j^XzqaUmVma@=01L~2WOcn)Qaq)%PrfTb*a2R> z1|-)Tz~U!BGVJtP>W~D{6|kZLl5ev>=^T)Zu6iv!rym#*V-L50`B@TB%776`CVABc zR0Ggn64ang698pv0`QK7E_W{}bl$P#6Mc20XOvC97_$>&f6w?%f?n0<=E$wUI%H6i2pHDG>Q`}$v)+Bd(=Jm+67{W*Ph>qR#z zlgg^N8sz!U_a&2*zPWKTNwqAOmpwtpR^X}@Twk~0`n2gqbiY1Fuf27-TNfjX&Ahh; z9kMfJbT_nb zc*4}a?gsOme_XBUt{=Alu0;lZ*NL0z%U}Gc+M=u@CaQQfnF_#ETa?a}dUevun^Yn_ z;eRBp`WOF19Srq@c#twGZ3am(w*GPHC|GIV{Dk6Q0yG!)Ts^m(*Y4Z*9-c`m?V0p| Y9)}AD;ft>HHTw2WD!+OW&5^Y58}HN3NB{r; diff --git a/technology/scn3me_subm/gds_lib/replica_cell_6t.gds b/technology/scn3me_subm/gds_lib/replica_cell_6t.gds index fbe8a28adc266b244ecddf38f178b94ac922e162..9f0f120d040f293a8cea1ab5c20632f3642fc06f 100644 GIT binary patch delta 1070 zcmbW0y>HV%7{(u8jcu7ye~`FNlrI^P7Svj#4k4lviaJN7LJXNYRZ*s>Q`Yhapvu*C zV2BVy2ZpEvkt&7`3>9++CI*BM1Ajo(4a}XdM=Z4yUVgsE_q-qX`X;NB)c_g@=1@`y zMo>_N$yT|{d*L8x+`UQeKQq_QlH~Fouzq%M+@~*z?LK`2+*<}D8|`UJ@s;U5`K$y{ z3_N@UNVYq`{a1iw6i-L$Hxe{Yfd?ue`6LI_CxB%0bUMxQ0^}_^-=K`=5qk$ delta 1059 zcmbW0F>KRN6h*Hc#|{A;JGI>;ib~{)3Q%eh2U6$|p{OGRV(L^eL{WzdRSX$e!pH=v z-qMkQfg$RWg@J*Q2{LqystycHOsE@}|NZ+Ei^75>>)6-t`oH_WJz1ZuhcKZdhq|U? z2n{t@SP>duUqf&ZwwC@T54y$8!z4L-18g2191X&_4>Vr_%=>%5>J5My_op4LqS33I zNuK7EWu1J^Y~7o7^b;+NPJvsu0p^AWTz>&Dqtj`}IMKuQ7`SNw%)8%!wF$s%kEb20 zW{s>ulKeUbEvbY@4zxUXb!8 zsQz9W6#WXIZv%dXcAP*L7&<$2>^k(-ap;Fzr$=s=>~fFBJ3%em@Oz5lsePdrJ);%x2h20_Q(y%S^7B2&sk!sR`YXas{eEKU`zQLGp6zd zTg(goc6JM1yMFo4k&9sty{IU^s>|=?PSBATj^w7wA Date: Wed, 31 Jan 2018 10:35:28 -0800 Subject: [PATCH 2/4] Fix via1 BL disconnect error. --- technology/scn3me_subm/mag_lib/cell_6t.mag | 22 ++++++------- .../scn3me_subm/mag_lib/replica_cell_6t.mag | 31 ++++++++++--------- 2 files changed, 27 insertions(+), 26 deletions(-) diff --git a/technology/scn3me_subm/mag_lib/cell_6t.mag b/technology/scn3me_subm/mag_lib/cell_6t.mag index e38b0aea..eb8b8605 100644 --- a/technology/scn3me_subm/mag_lib/cell_6t.mag +++ b/technology/scn3me_subm/mag_lib/cell_6t.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1517005451 +timestamp 1517421767 << nwell >> rect -8 29 42 51 << pwell >> @@ -75,39 +75,39 @@ rect 17 6 21 10 rect -2 44 32 48 rect -2 40 2 44 rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 rect -2 16 2 29 rect 11 18 15 36 rect 23 24 27 36 rect 25 20 27 24 +rect 14 14 15 18 rect 23 18 27 20 rect 32 26 36 29 +rect 23 14 24 18 rect 32 16 36 22 rect -2 6 17 9 rect 21 6 36 9 rect -2 5 36 6 -rect 9 -2 10 2 -rect 23 -2 24 2 << m2contact >> rect -2 29 2 33 rect 32 29 36 33 -rect 5 -2 9 2 -rect 19 -2 23 2 +rect 6 -2 10 2 +rect 20 -2 24 2 << metal2 >> rect -2 33 2 48 -rect -2 12 2 29 -rect 10 2 14 48 +rect -2 -2 2 29 +rect 10 -2 14 48 rect 20 2 24 48 -rect 9 -2 14 2 -rect 23 -2 24 2 rect 32 33 36 48 rect 32 -2 36 29 << m3p >> rect 0 0 34 46 << labels >> -rlabel m2contact 20 2 20 2 1 BR -rlabel metal2 10 2 10 2 1 BL rlabel metal1 2 6 2 6 3 WL rlabel metal2 -1 28 -1 28 1 gnd rlabel metal2 33 28 33 28 1 gnd rlabel metal1 17 46 17 46 5 vdd +rlabel metal2 11 43 11 43 1 BL +rlabel metal2 21 43 21 43 1 BR << end >> diff --git a/technology/scn3me_subm/mag_lib/replica_cell_6t.mag b/technology/scn3me_subm/mag_lib/replica_cell_6t.mag index 6ae96be7..24d0aa8e 100644 --- a/technology/scn3me_subm/mag_lib/replica_cell_6t.mag +++ b/technology/scn3me_subm/mag_lib/replica_cell_6t.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1517005488 +timestamp 1517421800 << nwell >> rect -8 29 42 51 << pwell >> @@ -75,41 +75,42 @@ rect 17 6 21 10 rect -2 44 32 48 rect -2 40 2 44 rect 32 40 36 44 -rect -2 18 2 29 -rect 11 18 15 36 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 25 2 29 +rect 11 25 15 36 +rect -2 21 15 25 rect 23 24 27 36 +rect -2 16 2 21 +rect 11 18 15 21 rect 25 20 27 24 +rect 14 14 15 18 rect 23 18 27 20 rect 32 26 36 29 -rect -2 16 10 18 -rect 2 14 10 16 +rect 23 14 24 18 rect 32 16 36 22 rect -2 6 17 9 rect 21 6 36 9 rect -2 5 36 6 -rect 9 -2 10 2 -rect 23 -2 24 2 << m2contact >> rect -2 29 2 33 rect 32 29 36 33 -rect 5 -2 9 2 -rect 19 -2 23 2 +rect 6 -2 10 2 +rect 20 -2 24 2 << metal2 >> rect -2 33 2 48 -rect -2 12 2 29 -rect 10 2 14 48 +rect -2 -2 2 29 +rect 10 -2 14 48 rect 20 2 24 48 -rect 9 -2 14 2 -rect 23 -2 24 2 rect 32 33 36 48 rect 32 -2 36 29 << m3p >> rect 0 0 34 46 << labels >> -rlabel m2contact 20 2 20 2 1 BR -rlabel metal2 10 2 10 2 1 BL rlabel metal1 2 6 2 6 3 WL rlabel metal2 -1 28 -1 28 1 gnd rlabel metal2 33 28 33 28 1 gnd rlabel metal1 17 46 17 46 5 vdd +rlabel metal2 11 43 11 43 1 BL +rlabel metal2 21 43 21 43 1 BR << end >> From 1175f515c83eef5e7cfa3c181a7a11b24705c1cd Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 31 Jan 2018 10:35:51 -0800 Subject: [PATCH 3/4] Add descriptive exceptions along with cleanup in unit test checking. --- compiler/tests/testutils.py | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 12a77c31..57932a68 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -26,16 +26,32 @@ class openram_test(unittest.TestCase): a.gds_write(tempgds) import verify - self.assertFalse(verify.run_drc(a.name, tempgds)) - self.assertFalse(verify.run_lvs(a.name, tempgds, tempspice)) + try: + self.assertFalse(verify.run_drc(a.name, tempgds)==0) + except: + self.reset() + raise Exception('DRC failed: {}'.format(a.name)) + + try: + self.assertFalse(verify.run_lvs(a.name, tempgds, tempspice)==0) + except: + self.reset() + raise Exception('LVS failed: {}'.format(a.name)) + self.cleanup() + + def cleanup(self): + """ Reset the duplicate checker and cleanup files. """ + self.reset() + files = glob.glob(OPTS.openram_temp + '*') for f in files: # Only remove the files if os.path.isfile(f): os.remove(f) - # reset the static duplicate name checker for unit tests + def reset(self): + """ Reset the static duplicate name checker for unit tests """ import design design.design.name_map=[] From 621de4b47b3304664daa0c329bbb8f51ee1cff23 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 31 Jan 2018 11:45:12 -0800 Subject: [PATCH 4/4] Added first test power model to sram --- compiler/characterizer/delay.py | 10 ++++++---- compiler/sram.py | 4 ++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 094d2e15..1cc2693d 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -451,15 +451,17 @@ class delay(): LH_slew.append(bank_delay.slew/1e3) HL_slew.append(bank_delay.slew/1e3) + power = sram.analytical_power(slew, load) + data = {"min_period": 0, "delay1": LH_delay, "delay0": HL_delay, "slew1": LH_slew, "slew0": HL_slew, - "read0_power": 0, - "read1_power": 0, - "write0_power": 0, - "write1_power": 0 + "read0_power": power, + "read1_power": power, + "write0_power": power, + "write1_power": power } return data diff --git a/compiler/sram.py b/compiler/sram.py index 9d602097..d9eb9db8 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -1003,3 +1003,7 @@ class sram(design.design): def analytical_delay(self,slew,load): """ LH and HL are the same in analytical model. """ return self.bank.analytical_delay(slew,load) + + def analytical_power(self,slew,load): + """ Just a test function for the power.""" + return 1