From 3c7f35d2958782303248075f1057da8987147c14 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Fri, 7 Apr 2023 10:02:38 -0700 Subject: [PATCH] add no rbl support to bank module --- compiler/modules/bank.py | 59 ++++++++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 8cf92961..47dcad44 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -85,7 +85,8 @@ class bank(design): for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout{0}_{1}".format(port, bit), "OUTPUT") for port in self.all_ports: - self.add_pin("rbl_bl_{0}_{0}".format(port), "OUTPUT") + if self.has_rbl: + self.add_pin("rbl_bl_{0}_{0}".format(port), "OUTPUT") for port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_pin("din{0}_{1}".format(port, bit), "INPUT") @@ -118,7 +119,8 @@ class bank(design): for port in self.all_ports: self.route_bitlines(port) - self.route_rbl(port) + if self.has_rbl: + self.route_rbl(port) self.route_port_address(port) self.route_column_address_lines(port) self.route_control_lines(port) @@ -360,6 +362,18 @@ class bank(design): def add_modules(self): """ Add all the modules using the class loader """ + # delay control logic does not have RBLs + if OPTS.control_logic != "control_logic_delay": + self.has_rbl = True + rbl = [1, 1 if len(self.all_ports)>1 else 0] + left_rbl = [0] + right_rbl = [1] if len(self.all_ports)>1 else [] + else: + self.has_rbl = False + rbl = [0, 0] + left_rbl = [] + right_rbl = [] + local_array_size = OPTS.local_array_size if local_array_size > 0: @@ -372,21 +386,25 @@ class bank(design): cols.append(local_array_size + final_size) self.bitcell_array = factory.create(module_type="global_bitcell_array", cols=cols, - rows=self.num_rows) + rows=self.num_rows, + rbl=rbl, + left_rbl=left_rbl, + right_rbl=right_rbl) else: self.bitcell_array = factory.create(module_type="capped_replica_bitcell_array", cols=self.num_cols + self.num_spare_cols, rows=self.num_rows, - rbl=[1, 1 if len(self.all_ports)>1 else 0], - left_rbl=[0], - right_rbl=[1] if len(self.all_ports)>1 else []) + rbl=rbl, + left_rbl=left_rbl, + right_rbl=right_rbl) self.port_address = [] for port in self.all_ports: self.port_address.append(factory.create(module_type="port_address", cols=self.num_cols + self.num_spare_cols, rows=self.num_rows, - port=port)) + port=port, + has_rbl=self.has_rbl)) self.port_data = [] self.bit_offsets = self.get_column_offsets() @@ -394,6 +412,7 @@ class bank(design): self.port_data.append(factory.create(module_type="port_data", sram_config=self.sram_config, port=port, + has_rbl=self.has_rbl, bit_offsets=self.bit_offsets)) def create_bitcell_array(self): @@ -407,9 +426,10 @@ class bank(design): # gnd temp = self.bitcell_array.get_inouts() - temp.append("rbl_wl0") + if self.has_rbl: + temp.append("rbl_wl0") temp.extend(self.bitcell_array.get_wordline_names()) - if len(self.all_ports) > 1: + if len(self.all_ports) > 1 and self.has_rbl: temp.append("rbl_wl1") temp.append("vdd") @@ -432,7 +452,8 @@ class bank(design): mod=self.port_data[port]) temp = [] - temp.extend(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)]) + if self.has_rbl: + temp.extend(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)]) temp.extend(self.bitcell_array.get_bitline_names(port)) if port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): @@ -480,7 +501,8 @@ class bank(design): temp.append("wl_en{}".format(port)) wordline_names = self.bitcell_array.get_wordline_names(port) temp.extend(wordline_names) - temp.append("rbl_wl{}".format(port)) + if self.has_rbl: + temp.append("rbl_wl{}".format(port)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) @@ -719,8 +741,9 @@ class bank(design): inst2_br_name=inst2_br_name) # Connect the replica bitlines - for (array_name, data_name) in zip(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)], ["rbl_bl", "rbl_br"]): - self.connect_bitline(inst1, inst2, array_name, data_name) + if self.has_rbl: + for (array_name, data_name) in zip(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)], ["rbl_bl", "rbl_br"]): + self.connect_bitline(inst1, inst2, array_name, data_name) def route_port_data_out(self, port): """ Add pins for the port data out """ @@ -841,7 +864,10 @@ class bank(design): def route_port_address_out(self, port, side="left"): """ Connecting Wordline driver output to Bitcell WL connection """ - driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + ["rbl_wl"] + driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + if self.has_rbl: + driver_names = driver_names + ["rbl_wl"] + # rbl_wl in next two lines will be ignored by zip once driver_names is exhausted in the no rbl case rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]): # The mid guarantees we exit the input cell to the right. @@ -875,7 +901,10 @@ class bank(design): def route_port_address_right(self, port): """ Connecting Wordline driver output to Bitcell WL connection """ - driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + ["rbl_wl"] + driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + if self.has_rbl: + driver_names = driver_names + ["rbl_wl"] + # rbl_wl in next two lines will be ignored by zip once driver_names is exhausted in the no rbl case rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]): # The mid guarantees we exit the input cell to the right.