From 3c5ecb963d5c3895b705d318ed7bf0602406e1ef Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 29 Jan 2018 15:25:15 -0800 Subject: [PATCH] Remove level of indirection to ptx devices to allow LVS symmetries. --- compiler/hierarchy_spice.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/compiler/hierarchy_spice.py b/compiler/hierarchy_spice.py index e9d1bb8d..d218227e 100644 --- a/compiler/hierarchy_spice.py +++ b/compiler/hierarchy_spice.py @@ -126,6 +126,8 @@ class spice(verilog.verilog): return if self.pins == []: return + + # write out the first spice line (the subcircuit) sp.write("\n.SUBCKT {0} {1}\n".format(self.name, " ".join(self.pins))) @@ -146,9 +148,15 @@ class spice(verilog.verilog): # these are wires and paths if self.conns[i] == []: continue - sp.write("X{0} {1} {2}\n".format(self.insts[i].name, - " ".join(self.conns[i]), - self.insts[i].mod.name)) + if hasattr(self.insts[i].mod,"spice_device"): + sp.write(self.insts[i].mod.spice_device.format(self.insts[i].name, + " ".join(self.conns[i]))) + sp.write("\n") + + else: + sp.write("X{0} {1} {2}\n".format(self.insts[i].name, + " ".join(self.conns[i]), + self.insts[i].mod.name)) sp.write(".ENDS {0}\n".format(self.name)) @@ -158,6 +166,7 @@ class spice(verilog.verilog): #if os.path.isfile(self.sp_file): # sp.write("\n* {0}\n".format(self.sp_file)) sp.write("\n".join(self.spice)) + sp.write("\n") def sp_write(self, spname):