From 3c3456596a4ed89076dfc2d6eebdf17d67efbc1d Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Fri, 14 Jun 2019 14:38:55 -0700
Subject: [PATCH] Add replica row with dummy cells.

---
 compiler/modules/replica_row.py               | 133 ++++++++++++++++++
 compiler/tests/05_replica_row_test.py         |  32 +++++
 .../scn4m_subm/mag_lib/dummy_cell_6t.mag      | 117 +++++++++++++++
 technology/scn4m_subm/sp_lib/dummy_cell_6t.sp |  18 +++
 4 files changed, 300 insertions(+)
 create mode 100644 compiler/modules/replica_row.py
 create mode 100755 compiler/tests/05_replica_row_test.py
 create mode 100644 technology/scn4m_subm/mag_lib/dummy_cell_6t.mag
 create mode 100644 technology/scn4m_subm/sp_lib/dummy_cell_6t.sp

diff --git a/compiler/modules/replica_row.py b/compiler/modules/replica_row.py
new file mode 100644
index 00000000..25268993
--- /dev/null
+++ b/compiler/modules/replica_row.py
@@ -0,0 +1,133 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California 
+# All rights reserved.
+#
+import debug
+import design
+from tech import drc
+import contact
+from sram_factory import factory
+from vector import vector
+from globals import OPTS
+
+class replica_row(design.design):
+    """
+    Generate a replica wordline row for the replica array.
+    """
+
+    def __init__(self, name, cols):
+        design.design.__init__(self, name)
+
+        self.column_size = cols 
+
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+            
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_instances()
+
+    def create_layout(self):
+        self.place_instances()
+        self.add_layout_pins()
+
+        self.add_boundary()
+        self.DRC_LVS()
+
+    def add_pins(self):
+        column_list = self.cell.list_all_bitline_names()
+        for col in range(self.column_size):
+            for cell_column in column_list:
+                self.add_pin("{0}_{1}".format(cell_column,col))
+        row_list = self.cell.list_all_wl_names()
+        for cell_row in row_list:
+            self.add_pin("{0}_{1}".format(cell_row,0))
+                    
+        self.add_pin("vdd")
+        self.add_pin("gnd")
+
+    def add_modules(self):
+        self.dummy_cell = factory.create(module_type="dummy_bitcell")
+        self.add_mod(self.dummy_cell)
+        # Used for pin names only
+        self.cell = factory.create(module_type="bitcell")
+        
+    def create_instances(self):
+        self.cell_inst = {}
+        for col in range(self.column_size):
+            name="dummy_{0}".format(col)
+            self.cell_inst[col]=self.add_inst(name=name,
+                                              mod=self.dummy_cell)
+            self.connect_inst(self.list_bitcell_pins(col, 0))
+            
+    def create_layout(self):
+
+        # We increase it by a well enclosure so the precharges don't overlap our wells
+        self.height = self.cell.height
+        self.width = self.column_size*self.cell.width 
+        
+        xoffset = 0.0
+        tempy = self.cell.height
+        dir_key = "MX"
+        for col in range(self.column_size):
+            name = "bit_{0}_c{1}".format("dummy",col)
+            self.cell_inst[col].place(offset=[xoffset, tempy],
+                                      mirror=dir_key)
+            xoffset += self.cell.width
+
+        self.add_layout_pins()
+
+        self.add_boundary()
+        
+        self.DRC_LVS()
+
+
+    def add_layout_pins(self):
+        """ Add the layout pins """
+        
+        row_list = self.cell.list_all_wl_names()
+        column_list = self.cell.list_all_bitline_names()
+
+        for col in range(self.column_size):
+            for cell_column in column_list:
+                bl_pin = self.cell_inst[col].get_pin(cell_column)
+                self.add_layout_pin(text=cell_column+"_{0}".format(col),
+                                    layer="metal2",
+                                    offset=bl_pin.ll(),
+                                    width=bl_pin.width(),
+                                    height=self.height)
+
+        for cell_row in row_list:
+            wl_pin = self.cell_inst[0].get_pin(cell_row)
+            self.add_layout_pin(text=cell_row+"_{0}".format(0),
+                                layer="metal1",
+                                offset=wl_pin.ll(),
+                                width=self.width,
+                                height=wl_pin.height())
+
+        # For every second row and column, add a via for gnd and vdd
+        for col in range(self.column_size):
+            inst = self.cell_inst[col]
+            for pin_name in ["vdd", "gnd"]:
+                self.copy_layout_pin(inst, pin_name)
+
+    def list_bitcell_pins(self, col, row):
+        """ Creates a list of connections in the bitcell, 
+        indexed by column and row, for instance use in bitcell_array """
+
+        bitcell_pins = []
+        
+        pin_names = self.cell.list_all_bitline_names()
+        for pin in pin_names:
+            bitcell_pins.append(pin+"_{0}".format(col))
+        pin_names = self.cell.list_all_wl_names()
+        for pin in pin_names:
+            bitcell_pins.append(pin+"_{0}".format(row))
+        bitcell_pins.append("vdd")
+        bitcell_pins.append("gnd")
+        
+        return bitcell_pins
+                
diff --git a/compiler/tests/05_replica_row_test.py b/compiler/tests/05_replica_row_test.py
new file mode 100755
index 00000000..9d8e7ce2
--- /dev/null
+++ b/compiler/tests/05_replica_row_test.py
@@ -0,0 +1,32 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California 
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class replica_row_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
+
+        debug.info(2, "Testing replica row for 6t_cell")
+        a = factory.create(module_type="replica_row", cols=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag
new file mode 100644
index 00000000..f2e9906a
--- /dev/null
+++ b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag
@@ -0,0 +1,117 @@
+magic
+tech scmos
+timestamp 1536091415
+<< nwell >>
+rect -8 29 42 51
+<< pwell >>
+rect -8 -8 42 29
+<< ntransistor >>
+rect 7 10 9 18
+rect 29 10 31 18
+rect 10 3 14 5
+rect 24 3 28 5
+<< ptransistor >>
+rect 7 37 11 40
+rect 27 37 31 40
+<< ndiffusion >>
+rect -2 16 7 18
+rect 2 12 7 16
+rect -2 10 7 12
+rect 9 14 10 18
+rect 9 10 14 14
+rect 28 14 29 18
+rect 24 10 29 14
+rect 31 16 36 18
+rect 31 12 32 16
+rect 31 10 36 12
+rect 10 5 14 10
+rect 24 5 28 10
+rect 10 2 14 3
+rect 24 2 28 3
+<< pdiffusion >>
+rect 2 37 7 40
+rect 11 37 12 40
+rect 26 37 27 40
+rect 31 37 32 40
+<< ndcontact >>
+rect -2 12 2 16
+rect 10 14 14 18
+rect 24 14 28 18
+rect 32 12 36 16
+rect 10 -2 14 2
+rect 24 -2 28 2
+<< pdcontact >>
+rect -2 36 2 40
+rect 12 36 16 40
+rect 22 36 26 40
+rect 32 36 36 40
+<< psubstratepcontact >>
+rect -2 22 2 26
+rect 32 22 36 26
+<< nsubstratencontact >>
+rect 32 44 36 48
+<< polysilicon >>
+rect 7 40 11 42
+rect 27 40 31 42
+rect 7 35 11 37
+rect 7 21 9 35
+rect 27 34 31 37
+rect 15 33 31 34
+rect 19 32 31 33
+rect 7 20 21 21
+rect 7 19 24 20
+rect 7 18 9 19
+rect 29 18 31 32
+rect 7 8 9 10
+rect 17 5 21 6
+rect 29 8 31 10
+rect -2 3 10 5
+rect 14 3 24 5
+rect 28 3 36 5
+<< polycontact >>
+rect 15 29 19 33
+rect 21 20 25 24
+rect 17 6 21 10
+<< metal1 >>
+rect -2 44 15 48
+rect 19 44 32 48
+rect -2 40 2 44
+rect 32 40 36 44
+rect 11 36 12 40
+rect 26 36 27 40
+rect -2 26 2 29
+rect -2 16 2 22
+rect 11 18 15 36
+rect 23 24 27 36
+rect 25 20 27 24
+rect 14 14 15 18
+rect 23 18 27 20
+rect 32 26 36 29
+rect 23 14 24 18
+rect 32 16 36 22
+rect -2 6 17 9
+rect 21 6 36 9
+rect -2 5 36 6
+<< m2contact >>
+rect 15 44 19 48
+rect -2 29 2 33
+rect 32 29 36 33
+rect 6 -2 10 2
+rect 20 -2 24 2
+<< metal2 >>
+rect -2 33 2 48
+rect -2 -2 2 29
+rect 6 2 10 48
+rect 24 -2 28 48
+rect 32 33 36 48
+rect 32 -2 36 29
+<< bb >>
+rect 0 0 34 46
+<< labels >>
+rlabel metal2 0 0 0 0 1 gnd
+rlabel metal2 34 0 34 0 1 gnd
+rlabel m2contact 17 46 17 46 5 vdd
+rlabel metal2 8 43 8 43 1 bl
+rlabel metal2 26 43 26 43 1 br
+rlabel metal1 4 7 4 7 1 wl
+<< end >>
diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp
new file mode 100644
index 00000000..ea939036
--- /dev/null
+++ b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp
@@ -0,0 +1,18 @@
+
+*********************** "cell_6t" ******************************
+.SUBCKT cell_6t bl br wl vdd gnd
+* SPICE3 file created from cell_6t.ext - technology: scmos
+
+* Inverter 1
+M1000 Q Qbar vdd vdd p w=0.6u l=0.8u
+M1002 Q Qbar gnd gnd n w=1.6u l=0.4u
+
+* Inverter 2
+M1001 vdd Q Qbar vdd p w=0.6u l=0.8u
+M1003 gnd Q Qbar gnd n w=1.6u l=0.4u
+
+* Access transistors
+M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u
+M1005 Qbar wl br_noconn gnd n w=0.8u l=0.4u
+
+.ENDS