From 3b69cafde7f97691561e1bf4f2140978687fd90d Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Fri, 17 Feb 2023 19:15:14 -0800 Subject: [PATCH] Update Xyce char tests --- compiler/characterizer/stimuli.py | 2 +- compiler/tests/21_model_delay_test.py | 4 +++- compiler/tests/21_xyce_delay_test.py | 28 +++++++++++++-------------- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 5e692fc0..c2bf3e39 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -279,7 +279,7 @@ class stimuli(): self.sf.write(".OPTIONS DEVICE TEMP={}\n".format(self.temperature)) self.sf.write(".OPTIONS MEASURE MEASFAIL=1\n") self.sf.write(".OPTIONS LINSOL type=klu\n") - self.sf.write(".OPTIONS TIMEINT RELTOL=1e-6 ABSTOL=1e-10 method=gear minorder=2\n") + self.sf.write(".OPTIONS TIMEINT RELTOL=1e-3 ABSTOL=1e-6 method=gear minorder=2\n") # Format: .TRAN self.sf.write(".TRAN {0}p {1}n 0n {0}p\n".format(timestep, end_time)) elif OPTS.spice_name: diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 5a6d1ce3..46e2e66f 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -25,6 +25,8 @@ class model_delay_test(openram_test): openram.init_openram(config_file, is_unit_test=True) OPTS.analytical_delay = False OPTS.netlist_only = True + OPTS.spice_name = "Xyce" + OPTS.num_sim_threads = 8 # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload @@ -93,7 +95,7 @@ class model_delay_test(openram_test): else: self.assertTrue(False) # other techs fail - debug.info(3, 'spice_delays {}'.fomrat(spice_delays)) + debug.info(3, 'spice_delays {}'.format(spice_delays)) debug.info(3, 'model_delays {}'.format(model_delays)) # Check if no too many or too few results diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py index be5a70ee..1c62ad1b 100755 --- a/compiler/tests/21_xyce_delay_test.py +++ b/compiler/tests/21_xyce_delay_test.py @@ -84,20 +84,20 @@ class timing_sram_test(openram_test): 'write0_power': [0.429895901], 'write1_power': [0.383337501]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.884186], - 'delay_lh': [1.884186], - 'disabled_read0_power': [20.86336], - 'disabled_read1_power': [22.10636], - 'disabled_write0_power': [22.62321], - 'disabled_write1_power': [23.316010000000002], - 'leakage_power': 13.351170000000002, - 'min_period': 7.188, - 'read0_power': [29.90159], - 'read1_power': [30.47858], - 'slew_hl': [2.042723], - 'slew_lh': [2.042723], - 'write0_power': [32.13199], - 'write1_power': [28.46703]} + golden_data = {'delay_hl': [1.78586], + 'delay_lh': [1.78586], + 'disabled_read0_power': [7.8296693788], + 'disabled_read1_power': [9.1464723788], + 'disabled_write0_power': [9.6889073788], + 'disabled_write1_power': [10.4123023788], + 'leakage_power': 0.0002442851, + 'min_period': 6.875, + 'read0_power': [16.995952378800002], + 'read1_power': [17.5845523788], + 'slew_hl': [2.039202], + 'slew_lh': [2.039202], + 'write0_power': [19.785462378800002], + 'write1_power': [15.742192378799999]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results