From 3af1bbba269535a1052867b87022d8f699627442 Mon Sep 17 00:00:00 2001 From: mguthaus Date: Tue, 6 Feb 2018 07:58:25 -0800 Subject: [PATCH] Updated delay tests with new delays including ps, pd, as, ad. --- compiler/tests/21_hspice_delay_test.py | 36 ++++++++++++------------- compiler/tests/21_ngspice_delay_test.py | 34 +++++++++++------------ 2 files changed, 35 insertions(+), 35 deletions(-) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 1647adbc..ebdc9093 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -49,25 +49,25 @@ class timing_sram_test(openram_test): slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data,slews,loads) if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.0296933, - 'read0_power': 0.029897899999999998, - 'write0_power': 0.0258029, - 'delay1': [0.049100700000000004], - 'delay0': [0.13766139999999996], - 'min_period': 0.322, - 'write1_power': 0.0260398, - 'slew0': [0.0265264], - 'slew1': [0.0195507]} + golden_data = {'read1_power': 0.0339194, + 'read0_power': 0.0340617, + 'write0_power': 0.0287779, + 'delay1': [0.0575725], + 'delay0': [0.16744839999999997], + 'min_period': 0.391, + 'write1_power': 0.0299736, + 'slew0': [0.026416], + 'slew1': [0.020441199999999996]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 4.443, - 'read0_power': 4.4712, - 'write0_power': 3.0032, - 'delay1': [0.8596608], - 'delay0': [1.9534000000000002], - 'min_period': 5.625, - 'write1_power': 2.8086, - 'slew0': [1.2982], - 'slew1': [0.9909933]} + golden_data = {'read1_power': 5.557800000000001, + 'read0_power': 5.5712, + 'write0_power': 3.8325, + 'delay1': [1.0323], + 'delay0': [2.2134], + 'min_period': 6.25, + 'write1_power': 3.6903, + 'slew0': [1.3009000000000002], + 'slew1': [0.983561]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index ea0df783..ccf40f31 100644 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -47,25 +47,25 @@ class timing_sram_test(openram_test): slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data,slews,loads) if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.026660760000000002, - 'read0_power': 0.02711731, - 'write0_power': 0.02501428, - 'delay1': [0.04867702], - 'delay0': [0.1423633], - 'min_period': 0.332, - 'write1_power': 0.024162890000000003, - 'slew0': [0.02733451], - 'slew1': [0.02121624]} + golden_data = {'read1_power': 0.03228762, + 'read0_power': 0.03281849, + 'write0_power': 0.02902607, + 'delay1': [0.059081419999999996], + 'delay0': [0.1716648], + 'min_period': 0.391, + 'write1_power': 0.02879424, + 'slew0': [0.02851539], + 'slew1': [0.02319674]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 4.250786000000001, - 'read0_power': 4.093461, - 'write0_power': 2.762675, - 'delay1': [0.920068], - 'delay0': [2.051821], + golden_data = {'read1_power': 5.063901, + 'read0_power': 4.926464999999999, + 'write0_power': 3.480712, + 'delay1': [1.044746], + 'delay0': [2.23024], 'min_period': 6.563, - 'write1_power': 2.4545719999999998, - 'slew0': [1.342015], - 'slew1': [1.040868]} + 'write1_power': 3.1949449999999997, + 'slew0': [1.3469], + 'slew1': [1.035352]} else: self.assertTrue(False) # other techs fail