diff --git a/compiler/sram/multibank_template.v b/compiler/sram/multibank_template.v
new file mode 100644
index 00000000..2c6d559e
--- /dev/null
+++ b/compiler/sram/multibank_template.v
@@ -0,0 +1,36 @@
+
+module multibank # (
+  DATA_WIDTH = 32,
+  ADDR_WIDTH= 8
+)(
+#<RW_PORTS
+    clk#$PORT_NUM$#,
+    addr#$PORT_NUM$#,
+    din#$PORT_NUM$#,
+    csb#$PORT_NUM$#,
+    web#$PORT_NUM$#,
+    dout#$PORT_NUM$#,
+#>RW_PORTS
+#<R_PORTS
+    clk#$PORT_NUM$#,
+    addr#$PORT_NUM$#,
+    csb#$PORT_NUM$#,
+    web#$PORT_NUM$#,
+    dout#$PORT_NUM$#,
+#>R_PORTS
+  );
+
+  parameter RAM_DEPTH = 1 << ADRR_WIDTH;
+  
+#<BANK_INIT
+  bank bank#$BANK_NUM$# #(DATA_WIDTH, ADDR_WIDTH) (
+#<BANK_RW_PORTS
+    clk#$PORT_NUM$#,
+    addr#$PORT_NUM$#,
+    din#$PORT_NUM$#,
+    csb#$PORT_NUM$#,
+    web#$PORT_NUM$#,
+    dout#$PORT_NUM$#,
+#>BANK_R_PORTS
+  )
+#>BANK_INIT
diff --git a/compiler/sram/verilog_template.py b/compiler/sram/verilog_template.py
new file mode 100644
index 00000000..2fc0656f
--- /dev/null
+++ b/compiler/sram/verilog_template.py
@@ -0,0 +1,47 @@
+
+
+class TextSection:
+    
+    def __init__(self, name, parent):
+        self.name = name
+        self.parent = parent
+        self.lines = []
+        self.sections = []
+        self.sectionPos = []
+        self.lineNum = 0
+        self.repeat = 0
+
+    def addLine(self, line):
+        self.lines.append(line)
+        self.lineNum+= 1
+
+    def addSection(self, section):
+        self.sections.append(section)
+        self.sectionPos.append(self.lineNum)
+
+    def expand(self):
+        for i
+
+class VerilogTemplate:
+    
+    def __init__(self, template, output);
+        self.template = template
+        self.output = output
+        self.sections = []
+
+    def readTemplate(self):
+        lines = []
+        with open(self.template, 'r') as f:
+            lines = f.readlines()
+        currentSection = TextSection('base', None)
+        for line in lines:
+            if line[:2] == '#<':
+                section = TextSection(line[2:], currentSection)
+                currentSection.addSection(section)
+                currentSection = section
+            if line[:2] == '#>' and line[2:] == section.name:
+                currentSection = currentSection.parent
+            else:
+                currentSection.addLine(line)
+
+